blob: c2c219bf3758ed75e7c26a2be3b25d61b690de0c [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100040#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080041#include "drm_crtc_helper.h"
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Zhenyu Wang32f9d652009-07-24 01:00:32 +080044#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
Akshay Joshi0206e352011-08-16 15:34:10 -040046bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
50typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040051 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080060} intel_clock_t;
61
62typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040063 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080064} intel_range_t;
65
66typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040067 int dot_limit;
68 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080069} intel_p2_t;
70
71#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080072typedef struct intel_limit intel_limit_t;
73struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040074 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
Sean Paulcec2f352012-01-10 15:09:36 -080077 int, int, intel_clock_t *, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080078};
Jesse Barnes79e53942008-11-07 14:24:08 -080079
Jesse Barnes2377b742010-07-07 14:06:43 -070080/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
Ma Lingd4906092009-03-18 20:13:27 +080083static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080085 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080087static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080089 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080091
Keith Packarda4fc5ed2009-04-07 16:16:42 -070092static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080094 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080096static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050097intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080098 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700100
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
Chris Wilson021357a2010-09-07 20:54:59 +0100106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
Chris Wilson8b99e682010-10-13 09:59:17 +0100109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100114}
115
Keith Packarde4b36692009-06-05 19:22:17 -0700116static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800127 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800141 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700142};
Eric Anholt273e27c2011-03-30 13:01:10 -0700143
Keith Packarde4b36692009-06-05 19:22:17 -0700144static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800155 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800169 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700170};
171
Eric Anholt273e27c2011-03-30 13:01:10 -0700172
Keith Packarde4b36692009-06-05 19:22:17 -0700173static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800185 },
Ma Lingd4906092009-03-18 20:13:27 +0800186 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800200 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800214 },
Ma Lingd4906092009-03-18 20:13:27 +0800215 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800229 },
Ma Lingd4906092009-03-18 20:13:27 +0800230 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700245};
246
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500247static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700250 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700253 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800260 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700261};
262
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500263static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800274 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700275};
276
Eric Anholt273e27c2011-03-30 13:01:10 -0700277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800282static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800293 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700294};
295
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800296static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800321 .find_pll = intel_g4x_find_best_PLL,
322};
323
Eric Anholt273e27c2011-03-30 13:01:10 -0700324/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400333 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400347 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700363 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800365};
366
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
Vijay Purushothaman17dc9252012-09-27 19:13:09 +0530383 .vco = { .min = 4000000, .max = 5994000},
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530396 .dot = { .min = 25000, .max = 270000 },
397 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700398 .n = { .min = 1, .max = 7 },
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530399 .m = { .min = 22, .max = 450 },
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
Jesse Barnes57f350b2012-03-28 13:39:25 -0700409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
Jesse Barnes57f350b2012-03-28 13:39:25 -0700456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
Daniel Vetter618563e2012-04-01 13:38:50 +0200467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
Takashi Iwaib0354382012-03-20 13:07:05 +0100485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
Takashi Iwai121d5272012-03-20 13:07:06 +0100490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
Daniel Vetter618563e2012-04-01 13:38:50 +0200494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
Takashi Iwaib0354382012-03-20 13:07:05 +0100497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
Seth Forshee14d94a32012-06-13 13:46:58 -0500506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
Takashi Iwaib0354382012-03-20 13:07:05 +0100507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
Chris Wilson1b894b52010-12-14 20:04:54 +0000513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800515{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800518 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800522 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000523 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000528 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800536 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800537 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800538
539 return limit;
540}
541
Ma Ling044c7c42009-03-18 20:13:23 +0800542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100549 if (is_dual_link_lvds(dev_priv, LVDS))
Ma Ling044c7c42009-03-18 20:13:23 +0800550 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700551 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800552 else
553 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700554 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700557 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700559 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700561 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800562 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700563 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800564
565 return limit;
566}
567
Chris Wilson1b894b52010-12-14 20:04:54 +0000568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
Eric Anholtbad720f2009-10-22 16:11:14 -0700573 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000574 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800575 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800576 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500577 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500579 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800580 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500581 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700596 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 else
Keith Packarde4b36692009-06-05 19:22:17 -0700598 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 }
600 return limit;
601}
602
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800605{
Shaohua Li21778322009-02-23 15:19:16 +0800606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800616 return;
617 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
Jesse Barnes79e53942008-11-07 14:24:08 -0800624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800628{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100629 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100630 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800631
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100634 return true;
635
636 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800637}
638
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
Chris Wilson1b894b52010-12-14 20:04:54 +0000645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800648{
Jesse Barnes79e53942008-11-07 14:24:08 -0800649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400650 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800651 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400652 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400654 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400656 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400658 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400660 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400662 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400664 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400669 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800670
671 return true;
672}
673
Ma Lingd4906092009-03-18 20:13:27 +0800674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800678
Jesse Barnes79e53942008-11-07 14:24:08 -0800679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 int err = target;
684
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800686 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
Takashi Iwaib0354382012-03-20 13:07:05 +0100693 if (is_dual_link_lvds(dev_priv, LVDS))
Jesse Barnes79e53942008-11-07 14:24:08 -0800694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
Akshay Joshi0206e352011-08-16 15:34:10 -0400704 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800705
Zhao Yakui42158662009-11-20 11:24:18 +0800706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800717 int this_err;
718
Shaohua Li21778322009-02-23 15:19:16 +0800719 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800722 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
Ma Lingd4906092009-03-18 20:13:27 +0800740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800755 int lvds_reg;
756
Eric Anholtc619eed2010-01-28 16:45:52 -0800757 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200775 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200777 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
Shaohua Li21778322009-02-23 15:19:16 +0800786 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800789 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000793
794 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800805 return found;
806}
Ma Lingd4906092009-03-18 20:13:27 +0800807
Zhenyu Wang2c072452009-06-05 15:38:42 +0800808static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800815
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700839{
Chris Wilson5eddb702010-09-11 13:48:45 +0100840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700860}
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
Alan Coxaf447bd2012-07-25 13:49:18 +0100872 flag = 0;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700929
Paulo Zanonia928d532012-05-04 17:18:15 -0300930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800950{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800952 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700953
Paulo Zanonia928d532012-05-04 17:18:15 -0300954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
Chris Wilson300387c2010-09-05 20:25:43 +0100959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700975 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
Keith Packardab7ad7f2010-10-03 00:33:06 -0700982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100997 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700998 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001002
Keith Packardab7ad7f2010-10-03 00:33:06 -07001003 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001004 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001005
Keith Packardab7ad7f2010-10-03 00:33:06 -07001006 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001009 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001010 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001011 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001012 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
Paulo Zanoni837ba002012-05-04 17:18:14 -03001015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
Keith Packardab7ad7f2010-10-03 00:33:06 -07001020 /* Wait for the display line to settle */
1021 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001022 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001023 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -03001024 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
Daniel Vetter284637d2012-07-09 09:51:57 +02001027 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001028 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001029}
1030
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
Jesse Barnes040484a2011-01-03 12:14:26 -08001054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
Chris Wilson92b27b02012-05-20 18:10:50 +01001056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001059{
Jesse Barnes040484a2011-01-03 12:14:26 -08001060 u32 val;
1061 bool cur_state;
1062
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
Chris Wilson92b27b02012-05-20 18:10:50 +01001068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001070 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071
Chris Wilson92b27b02012-05-20 18:10:50 +01001072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
Chris Wilson92b27b02012-05-20 18:10:50 +01001083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001095 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001096}
Chris Wilson92b27b02012-05-20 18:10:50 +01001097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
Jesse Barnes040484a2011-01-03 12:14:26 -08001099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
Jesse Barnes040484a2011-01-03 12:14:26 -08001160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
Jesse Barnesea0760c2011-01-04 15:09:32 -08001180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001186 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001206 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001207}
1208
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211{
1212 int reg;
1213 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001214 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001215
Daniel Vetter8e636782012-01-22 01:36:48 +01001216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
Jesse Barnesb24e7172011-01-04 15:09:30 -08001220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001225 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001226}
1227
Chris Wilson931872f2012-01-16 23:01:13 +00001228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001230{
1231 int reg;
1232 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001233 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001241}
1242
Chris Wilson931872f2012-01-16 23:01:13 +00001243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
Jesse Barnes19ec1352011-02-02 12:28:02 -08001253 /* Planes are fixed to pipes on ILK+ */
Adam Jackson28c057942011-10-07 14:38:42 -04001254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001260 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001261 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001262
Jesse Barnesb24e7172011-01-04 15:09:30 -08001263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001272 }
1273}
1274
Jesse Barnes92f25842011-01-04 15:09:34 -08001275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
Jesse Barnes92f25842011-01-04 15:09:34 -08001285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001304}
1305
Keith Packard4e634382011-08-06 10:39:45 -07001306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
Keith Packard1519b992011-08-06 10:35:34 -07001324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
Jesse Barnes291906f2011-02-02 12:28:03 -08001371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001372 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001373{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001374 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001377 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001378
Daniel Vetter75c5da22012-09-10 21:58:29 +02001379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001381 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001382}
1383
1384static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, int reg)
1386{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001387 u32 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001390 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001391
Daniel Vetter75c5da22012-09-10 21:58:29 +02001392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001394 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001395}
1396
1397static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001402
Keith Packardf0575e92011-07-25 22:12:43 -07001403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001406
1407 reg = PCH_ADPA;
1408 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001409 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001410 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001411 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001412
1413 reg = PCH_LVDS;
1414 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001415 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001416 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001417 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001418
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422}
1423
Jesse Barnesb24e7172011-01-04 15:09:30 -08001424/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001425 * intel_enable_pll - enable a PLL
1426 * @dev_priv: i915 private structure
1427 * @pipe: pipe PLL to enable
1428 *
1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1430 * make sure the PLL reg is writable first though, since the panel write
1431 * protect mechanism may be enabled.
1432 *
1433 * Note! This is for pre-ILK only.
Thomas Richter7434a252012-07-18 19:22:30 +02001434 *
1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001436 */
Daniel Vettera37b9b32012-08-12 19:27:09 +02001437static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001438{
1439 int reg;
1440 u32 val;
1441
1442 /* No really, not for ILK+ */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07001443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001444
1445 /* PLL is protected by panel, make sure we can write it */
1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447 assert_panel_unlocked(dev_priv, pipe);
1448
1449 reg = DPLL(pipe);
1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452
1453 /* We do this three times for luck */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463}
1464
1465/**
1466 * intel_disable_pll - disable a PLL
1467 * @dev_priv: i915 private structure
1468 * @pipe: pipe PLL to disable
1469 *
1470 * Disable the PLL for @pipe, making sure the pipe is off first.
1471 *
1472 * Note! This is for pre-ILK only.
1473 */
1474static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475{
1476 int reg;
1477 u32 val;
1478
1479 /* Don't disable pipe A or pipe A PLLs if needed */
1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 return;
1482
1483 /* Make sure the pipe isn't still relying on us */
1484 assert_pipe_disabled(dev_priv, pipe);
1485
1486 reg = DPLL(pipe);
1487 val = I915_READ(reg);
1488 val &= ~DPLL_VCO_ENABLE;
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491}
1492
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001493/* SBI access */
1494static void
1495intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496{
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001500 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001501 100)) {
1502 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503 goto out_unlock;
1504 }
1505
1506 I915_WRITE(SBI_ADDR,
1507 (reg << 16));
1508 I915_WRITE(SBI_DATA,
1509 value);
1510 I915_WRITE(SBI_CTL_STAT,
1511 SBI_BUSY |
1512 SBI_CTL_OP_CRWR);
1513
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 goto out_unlock;
1518 }
1519
1520out_unlock:
1521 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522}
1523
1524static u32
1525intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526{
1527 unsigned long flags;
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001528 u32 value = 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001529
1530 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001532 100)) {
1533 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534 goto out_unlock;
1535 }
1536
1537 I915_WRITE(SBI_ADDR,
1538 (reg << 16));
1539 I915_WRITE(SBI_CTL_STAT,
1540 SBI_BUSY |
1541 SBI_CTL_OP_CRRD);
1542
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001543 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001544 100)) {
1545 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546 goto out_unlock;
1547 }
1548
1549 value = I915_READ(SBI_DATA);
1550
1551out_unlock:
1552 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553 return value;
1554}
1555
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001556/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001557 * intel_enable_pch_pll - enable PCH PLL
1558 * @dev_priv: i915 private structure
1559 * @pipe: pipe PLL to enable
1560 *
1561 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562 * drives the transcoder clock.
1563 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001564static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001565{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001566 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Chris Wilson48da64a2012-05-13 20:16:12 +01001567 struct intel_pch_pll *pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001568 int reg;
1569 u32 val;
1570
Chris Wilson48da64a2012-05-13 20:16:12 +01001571 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001572 BUG_ON(dev_priv->info->gen < 5);
Chris Wilson48da64a2012-05-13 20:16:12 +01001573 pll = intel_crtc->pch_pll;
1574 if (pll == NULL)
1575 return;
1576
1577 if (WARN_ON(pll->refcount == 0))
1578 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001579
1580 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001583
1584 /* PCH refclock must be enabled first */
1585 assert_pch_refclk_enabled(dev_priv);
1586
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001587 if (pll->active++ && pll->on) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001588 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001589 return;
1590 }
1591
1592 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001595 val = I915_READ(reg);
1596 val |= DPLL_VCO_ENABLE;
1597 I915_WRITE(reg, val);
1598 POSTING_READ(reg);
1599 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001600
1601 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001602}
1603
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001604static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001605{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001606 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607 struct intel_pch_pll *pll = intel_crtc->pch_pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001608 int reg;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001609 u32 val;
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001610
Jesse Barnes92f25842011-01-04 15:09:34 -08001611 /* PCH only available on ILK+ */
1612 BUG_ON(dev_priv->info->gen < 5);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001613 if (pll == NULL)
1614 return;
1615
Chris Wilson48da64a2012-05-13 20:16:12 +01001616 if (WARN_ON(pll->refcount == 0))
1617 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001618
1619 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620 pll->pll_reg, pll->active, pll->on,
1621 intel_crtc->base.base.id);
1622
Chris Wilson48da64a2012-05-13 20:16:12 +01001623 if (WARN_ON(pll->active == 0)) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001624 assert_pch_pll_disabled(dev_priv, pll, NULL);
Chris Wilson48da64a2012-05-13 20:16:12 +01001625 return;
1626 }
1627
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001628 if (--pll->active) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001629 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001630 return;
1631 }
1632
1633 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
Jesse Barnes92f25842011-01-04 15:09:34 -08001634
1635 /* Make sure transcoder isn't still depending on us */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001636 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001637
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001638 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001639 val = I915_READ(reg);
1640 val &= ~DPLL_VCO_ENABLE;
1641 I915_WRITE(reg, val);
1642 POSTING_READ(reg);
1643 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001644
1645 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001646}
1647
Jesse Barnes040484a2011-01-03 12:14:26 -08001648static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649 enum pipe pipe)
1650{
1651 int reg;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001652 u32 val, pipeconf_val;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Jesse Barnes040484a2011-01-03 12:14:26 -08001654
1655 /* PCH only available on ILK+ */
1656 BUG_ON(dev_priv->info->gen < 5);
1657
1658 /* Make sure PCH DPLL is enabled */
Chris Wilson92b27b02012-05-20 18:10:50 +01001659 assert_pch_pll_enabled(dev_priv,
1660 to_intel_crtc(crtc)->pch_pll,
1661 to_intel_crtc(crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001662
1663 /* FDI must be feeding us bits for PCH ports */
1664 assert_fdi_tx_enabled(dev_priv, pipe);
1665 assert_fdi_rx_enabled(dev_priv, pipe);
1666
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001667 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 return;
1670 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001673 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
1680 val &= ~PIPE_BPC_MASK;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001681 val |= pipeconf_val & PIPE_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001682 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001691 else
1692 val |= TRANS_PROGRESSIVE;
1693
Jesse Barnes040484a2011-01-03 12:14:26 -08001694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
1699static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
1702 int reg;
1703 u32 val;
1704
1705 /* FDI relies on the transcoder */
1706 assert_fdi_tx_disabled(dev_priv, pipe);
1707 assert_fdi_rx_disabled(dev_priv, pipe);
1708
Jesse Barnes291906f2011-02-02 12:28:03 -08001709 /* Ports must be off as well */
1710 assert_pch_ports_disabled(dev_priv, pipe);
1711
Jesse Barnes040484a2011-01-03 12:14:26 -08001712 reg = TRANSCONF(pipe);
1713 val = I915_READ(reg);
1714 val &= ~TRANS_ENABLE;
1715 I915_WRITE(reg, val);
1716 /* wait for PCH transcoder off, transcoder state */
1717 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001718 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001719}
1720
Jesse Barnes92f25842011-01-04 15:09:34 -08001721/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001722 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001723 * @dev_priv: i915 private structure
1724 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001725 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001726 *
1727 * Enable @pipe, making sure that various hardware specific requirements
1728 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729 *
1730 * @pipe should be %PIPE_A or %PIPE_B.
1731 *
1732 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 * returning.
1734 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001735static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001737{
1738 int reg;
1739 u32 val;
1740
1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
1747 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001748 else {
1749 if (pch_port) {
1750 /* if driving the PCH, we need FDI enabled */
1751 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753 }
1754 /* FIXME: assert CPU port conditions for SNB+ */
1755 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001756
1757 reg = PIPECONF(pipe);
1758 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001759 if (val & PIPECONF_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001763 intel_wait_for_vblank(dev_priv->dev, pipe);
1764}
1765
1766/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001767 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001768 * @dev_priv: i915 private structure
1769 * @pipe: pipe to disable
1770 *
1771 * Disable @pipe, making sure that various hardware specific requirements
1772 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 *
1774 * @pipe should be %PIPE_A or %PIPE_B.
1775 *
1776 * Will wait until the pipe has shut down before returning.
1777 */
1778static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779 enum pipe pipe)
1780{
1781 int reg;
1782 u32 val;
1783
1784 /*
1785 * Make sure planes won't keep trying to pump pixels to us,
1786 * or we might hang the display.
1787 */
1788 assert_planes_disabled(dev_priv, pipe);
1789
1790 /* Don't disable pipe A or pipe A PLLs if needed */
1791 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 return;
1793
1794 reg = PIPECONF(pipe);
1795 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001796 if ((val & PIPECONF_ENABLE) == 0)
1797 return;
1798
1799 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001800 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801}
1802
Keith Packardd74362c2011-07-28 14:47:14 -07001803/*
1804 * Plane regs are double buffered, going from enabled->disabled needs a
1805 * trigger in order to latch. The display address reg provides this.
1806 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001807void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001808 enum plane plane)
1809{
1810 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812}
1813
Jesse Barnesb24e7172011-01-04 15:09:30 -08001814/**
1815 * intel_enable_plane - enable a display plane on a given pipe
1816 * @dev_priv: i915 private structure
1817 * @plane: plane to enable
1818 * @pipe: pipe being fed
1819 *
1820 * Enable @plane on @pipe, making sure that @pipe is running first.
1821 */
1822static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823 enum plane plane, enum pipe pipe)
1824{
1825 int reg;
1826 u32 val;
1827
1828 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829 assert_pipe_enabled(dev_priv, pipe);
1830
1831 reg = DSPCNTR(plane);
1832 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001833 if (val & DISPLAY_PLANE_ENABLE)
1834 return;
1835
1836 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001837 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001838 intel_wait_for_vblank(dev_priv->dev, pipe);
1839}
1840
Jesse Barnesb24e7172011-01-04 15:09:30 -08001841/**
1842 * intel_disable_plane - disable a display plane
1843 * @dev_priv: i915 private structure
1844 * @plane: plane to disable
1845 * @pipe: pipe consuming the data
1846 *
1847 * Disable @plane; should be an independent operation.
1848 */
1849static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850 enum plane plane, enum pipe pipe)
1851{
1852 int reg;
1853 u32 val;
1854
1855 reg = DSPCNTR(plane);
1856 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001857 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 return;
1859
1860 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001861 intel_flush_display_plane(dev_priv, plane);
1862 intel_wait_for_vblank(dev_priv->dev, pipe);
1863}
1864
Chris Wilson127bd2a2010-07-23 23:32:05 +01001865int
Chris Wilson48b956c2010-09-14 12:50:34 +01001866intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001867 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001868 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001869{
Chris Wilsonce453d82011-02-21 14:43:56 +00001870 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001871 u32 alignment;
1872 int ret;
1873
Chris Wilson05394f32010-11-08 19:18:58 +00001874 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001875 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001876 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001878 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001879 alignment = 4 * 1024;
1880 else
1881 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001882 break;
1883 case I915_TILING_X:
1884 /* pin() will align the object as required by fence */
1885 alignment = 0;
1886 break;
1887 case I915_TILING_Y:
1888 /* FIXME: Is this true? */
1889 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890 return -EINVAL;
1891 default:
1892 BUG();
1893 }
1894
Chris Wilsonce453d82011-02-21 14:43:56 +00001895 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001896 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001897 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001898 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001899
1900 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901 * fence, whereas 965+ only requires a fence if using
1902 * framebuffer compression. For simplicity, we always install
1903 * a fence as the cost is not that onerous.
1904 */
Chris Wilson06d98132012-04-17 15:31:24 +01001905 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001906 if (ret)
1907 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001908
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001909 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001910
Chris Wilsonce453d82011-02-21 14:43:56 +00001911 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001912 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001913
1914err_unpin:
1915 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001916err_interruptible:
1917 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001918 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001919}
1920
Chris Wilson1690e1e2011-12-14 13:57:08 +01001921void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922{
1923 i915_gem_object_unpin_fence(obj);
1924 i915_gem_object_unpin(obj);
1925}
1926
Daniel Vetterc2c75132012-07-05 12:17:30 +02001927/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928 * is assumed to be a power-of-two. */
1929static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930 unsigned int bpp,
1931 unsigned int pitch)
1932{
1933 int tile_rows, tiles;
1934
1935 tile_rows = *y / 8;
1936 *y %= 8;
1937 tiles = *x / (512/bpp);
1938 *x %= 512/bpp;
1939
1940 return tile_rows * pitch * 8 + tiles * 4096;
1941}
1942
Jesse Barnes17638cd2011-06-24 12:19:23 -07001943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001950 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001951 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02001952 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07001953 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01001954 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07001955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
1961 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07001967
Chris Wilson5eddb702010-09-11 13:48:45 +01001968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07001970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972 switch (fb->bits_per_pixel) {
1973 case 8:
1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
1976 case 16:
1977 if (fb->depth == 15)
1978 dspcntr |= DISPPLANE_15_16BPP;
1979 else
1980 dspcntr |= DISPPLANE_16BPP;
1981 break;
1982 case 24:
1983 case 32:
1984 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985 break;
1986 default:
Jesse Barnes17638cd2011-06-24 12:19:23 -07001987 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
Jesse Barnes81255562010-08-02 12:07:50 -07001988 return -EINVAL;
1989 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001990 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00001991 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07001992 dspcntr |= DISPPLANE_TILED;
1993 else
1994 dspcntr &= ~DISPPLANE_TILED;
1995 }
1996
Chris Wilson5eddb702010-09-11 13:48:45 +01001997 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07001998
Daniel Vettere506a0c2012-07-05 12:17:29 +02001999 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002000
Daniel Vetterc2c75132012-07-05 12:17:30 +02002001 if (INTEL_INFO(dev)->gen >= 4) {
2002 intel_crtc->dspaddr_offset =
2003 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004 fb->bits_per_pixel / 8,
2005 fb->pitches[0]);
2006 linear_offset -= intel_crtc->dspaddr_offset;
2007 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002008 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002009 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002010
2011 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002013 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002014 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002015 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002017 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002018 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002019 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02002020 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002021 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002022
Jesse Barnes17638cd2011-06-24 12:19:23 -07002023 return 0;
2024}
2025
2026static int ironlake_update_plane(struct drm_crtc *crtc,
2027 struct drm_framebuffer *fb, int x, int y)
2028{
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 struct intel_framebuffer *intel_fb;
2033 struct drm_i915_gem_object *obj;
2034 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002035 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002036 u32 dspcntr;
2037 u32 reg;
2038
2039 switch (plane) {
2040 case 0:
2041 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002042 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
2051
2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth != 16)
2062 return -EINVAL;
2063
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 if (fb->depth == 24)
2069 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070 else if (fb->depth == 30)
2071 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072 else
2073 return -EINVAL;
2074 break;
2075 default:
2076 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077 return -EINVAL;
2078 }
2079
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084
2085 /* must disable */
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088 I915_WRITE(reg, dspcntr);
2089
Daniel Vettere506a0c2012-07-05 12:17:29 +02002090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002091 intel_crtc->dspaddr_offset =
2092 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
2095 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002096
Daniel Vettere506a0c2012-07-05 12:17:29 +02002097 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002099 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002100 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101 obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002102 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002103 I915_WRITE(DSPLINOFF(plane), linear_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002104 POSTING_READ(reg);
2105
2106 return 0;
2107}
2108
2109/* Assume fb object is pinned & idle & fenced and just update base pointers */
2110static int
2111intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2113{
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002116
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002119 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002120
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002121 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002122}
2123
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002124static int
Chris Wilson14667a42012-04-03 17:58:35 +01002125intel_finish_fb(struct drm_framebuffer *old_fb)
2126{
2127 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 bool was_interruptible = dev_priv->mm.interruptible;
2130 int ret;
2131
2132 wait_event(dev_priv->pending_flip_queue,
2133 atomic_read(&dev_priv->mm.wedged) ||
2134 atomic_read(&obj->pending_flip) == 0);
2135
2136 /* Big Hammer, we also need to ensure that any pending
2137 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138 * current scanout is retired before unpinning the old
2139 * framebuffer.
2140 *
2141 * This should only fail upon a hung GPU, in which case we
2142 * can safely continue.
2143 */
2144 dev_priv->mm.interruptible = false;
2145 ret = i915_gem_object_finish_gpu(obj);
2146 dev_priv->mm.interruptible = was_interruptible;
2147
2148 return ret;
2149}
2150
2151static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002152intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002153 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002154{
2155 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002156 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002157 struct drm_i915_master_private *master_priv;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002159 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002160 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002161
2162 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002163 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002164 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002165 return 0;
2166 }
2167
Eugeni Dodonov5826eca2012-05-09 15:37:12 -03002168 if(intel_crtc->plane > dev_priv->num_pipe) {
2169 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170 intel_crtc->plane,
2171 dev_priv->num_pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002172 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002173 }
2174
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002175 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002176 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002177 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002178 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002179 if (ret != 0) {
2180 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002181 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002182 return ret;
2183 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002184
Daniel Vetter94352cf2012-07-05 22:51:56 +02002185 if (crtc->fb)
2186 intel_finish_fb(crtc->fb);
Chris Wilson265db952010-09-20 15:41:01 +01002187
Daniel Vetter94352cf2012-07-05 22:51:56 +02002188 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002189 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002190 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002191 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002192 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002193 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002194 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002195
Daniel Vetter94352cf2012-07-05 22:51:56 +02002196 old_fb = crtc->fb;
2197 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002198 crtc->x = x;
2199 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002200
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002201 if (old_fb) {
2202 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002203 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002204 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002205
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002206 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002207 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002208
2209 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002210 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002211
2212 master_priv = dev->primary->master->driver_priv;
2213 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002214 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002215
Chris Wilson265db952010-09-20 15:41:01 +01002216 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002217 master_priv->sarea_priv->pipeB_x = x;
2218 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002219 } else {
2220 master_priv->sarea_priv->pipeA_x = x;
2221 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002222 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002223
2224 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002225}
2226
Chris Wilson5eddb702010-09-11 13:48:45 +01002227static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002228{
2229 struct drm_device *dev = crtc->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
2231 u32 dpa_ctl;
2232
Zhao Yakui28c97732009-10-09 11:39:41 +08002233 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002234 dpa_ctl = I915_READ(DP_A);
2235 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237 if (clock < 200000) {
2238 u32 temp;
2239 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240 /* workaround for 160Mhz:
2241 1) program 0x4600c bits 15:0 = 0x8124
2242 2) program 0x46010 bit 0 = 1
2243 3) program 0x46034 bit 24 = 1
2244 4) program 0x64000 bit 14 = 1
2245 */
2246 temp = I915_READ(0x4600c);
2247 temp &= 0xffff0000;
2248 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250 temp = I915_READ(0x46010);
2251 I915_WRITE(0x46010, temp | 1);
2252
2253 temp = I915_READ(0x46034);
2254 I915_WRITE(0x46034, temp | (1 << 24));
2255 } else {
2256 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257 }
2258 I915_WRITE(DP_A, dpa_ctl);
2259
Chris Wilson5eddb702010-09-11 13:48:45 +01002260 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002261 udelay(500);
2262}
2263
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002264static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 int pipe = intel_crtc->pipe;
2270 u32 reg, temp;
2271
2272 /* enable normal train */
2273 reg = FDI_TX_CTL(pipe);
2274 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002275 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002278 } else {
2279 temp &= ~FDI_LINK_TRAIN_NONE;
2280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002281 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002282 I915_WRITE(reg, temp);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 if (HAS_PCH_CPT(dev)) {
2287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289 } else {
2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_NONE;
2292 }
2293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295 /* wait one idle pattern time */
2296 POSTING_READ(reg);
2297 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002298
2299 /* IVB wants error correction enabled */
2300 if (IS_IVYBRIDGE(dev))
2301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002303}
2304
Jesse Barnes291427f2011-07-29 12:42:37 -07002305static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310 flags |= FDI_PHASE_SYNC_OVR(pipe);
2311 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312 flags |= FDI_PHASE_SYNC_EN(pipe);
2313 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314 POSTING_READ(SOUTH_CHICKEN1);
2315}
2316
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002317/* The FDI link training functions for ILK/Ibexpeak. */
2318static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002324 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002325 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002326
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002327 /* FDI needs bits from pipe & plane first */
2328 assert_pipe_enabled(dev_priv, pipe);
2329 assert_plane_enabled(dev_priv, plane);
2330
Adam Jacksone1a44742010-06-25 15:32:14 -04002331 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002333 reg = FDI_RX_IMR(pipe);
2334 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002335 temp &= ~FDI_RX_SYMBOL_LOCK;
2336 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002337 I915_WRITE(reg, temp);
2338 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002339 udelay(150);
2340
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002341 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002344 temp &= ~(7 << 19);
2345 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002348 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002349
Chris Wilson5eddb702010-09-11 13:48:45 +01002350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002354 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002357 udelay(150);
2358
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002359 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002360 if (HAS_PCH_IBX(dev)) {
2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
2364 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002365
Chris Wilson5eddb702010-09-11 13:48:45 +01002366 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002367 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002368 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002369 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371 if ((temp & FDI_RX_BIT_LOCK)) {
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002373 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002374 break;
2375 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002376 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002377 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002378 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002379
2380 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002381 reg = FDI_TX_CTL(pipe);
2382 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002385 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002386
Chris Wilson5eddb702010-09-11 13:48:45 +01002387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002391 I915_WRITE(reg, temp);
2392
2393 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002394 udelay(150);
2395
Chris Wilson5eddb702010-09-11 13:48:45 +01002396 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002397 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002398 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002399 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002402 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002403 DRM_DEBUG_KMS("FDI train 2 done.\n");
2404 break;
2405 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002406 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002407 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002408 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002409
2410 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002411
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002412}
2413
Akshay Joshi0206e352011-08-16 15:34:10 -04002414static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002415 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419};
2420
2421/* The FDI link training functions for SNB/Cougarpoint. */
2422static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423{
2424 struct drm_device *dev = crtc->dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002428 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002429
Adam Jacksone1a44742010-06-25 15:32:14 -04002430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002439 udelay(150);
2440
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002441 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002444 temp &= ~(7 << 19);
2445 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449 /* SNB-B */
2450 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002452
Chris Wilson5eddb702010-09-11 13:48:45 +01002453 reg = FDI_RX_CTL(pipe);
2454 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002455 if (HAS_PCH_CPT(dev)) {
2456 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458 } else {
2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002462 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002465 udelay(150);
2466
Jesse Barnes291427f2011-07-29 12:42:37 -07002467 if (HAS_PCH_CPT(dev))
2468 cpt_phase_pointer_enable(dev, pipe);
2469
Akshay Joshi0206e352011-08-16 15:34:10 -04002470 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002473 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002475 I915_WRITE(reg, temp);
2476
2477 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002478 udelay(500);
2479
Sean Paulfa37d392012-03-02 12:53:39 -05002480 for (retry = 0; retry < 5; retry++) {
2481 reg = FDI_RX_IIR(pipe);
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484 if (temp & FDI_RX_BIT_LOCK) {
2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487 break;
2488 }
2489 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002490 }
Sean Paulfa37d392012-03-02 12:53:39 -05002491 if (retry < 5)
2492 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002493 }
2494 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002495 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002496
2497 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_2;
2502 if (IS_GEN6(dev)) {
2503 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504 /* SNB-B */
2505 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002508
Chris Wilson5eddb702010-09-11 13:48:45 +01002509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002511 if (HAS_PCH_CPT(dev)) {
2512 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514 } else {
2515 temp &= ~FDI_LINK_TRAIN_NONE;
2516 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002521 udelay(150);
2522
Akshay Joshi0206e352011-08-16 15:34:10 -04002523 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002528 I915_WRITE(reg, temp);
2529
2530 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002531 udelay(500);
2532
Sean Paulfa37d392012-03-02 12:53:39 -05002533 for (retry = 0; retry < 5; retry++) {
2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
2542 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002543 }
Sean Paulfa37d392012-03-02 12:53:39 -05002544 if (retry < 5)
2545 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002546 }
2547 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002548 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002549
2550 DRM_DEBUG_KMS("FDI train done.\n");
2551}
2552
Jesse Barnes357555c2011-04-28 15:09:55 -07002553/* Manual link training for Ivy Bridge A0 parts */
2554static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp, i;
2561
2562 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563 for train result */
2564 reg = FDI_RX_IMR(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_RX_SYMBOL_LOCK;
2567 temp &= ~FDI_RX_BIT_LOCK;
2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
2571 udelay(150);
2572
2573 /* enable CPU FDI TX and PCH FDI RX */
2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
2576 temp &= ~(7 << 19);
2577 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002582 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_AUTO;
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002590 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002591 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593 POSTING_READ(reg);
2594 udelay(150);
2595
Jesse Barnes291427f2011-07-29 12:42:37 -07002596 if (HAS_PCH_CPT(dev))
2597 cpt_phase_pointer_enable(dev, pipe);
2598
Akshay Joshi0206e352011-08-16 15:34:10 -04002599 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
2607 udelay(500);
2608
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613 if (temp & FDI_RX_BIT_LOCK ||
2614 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 }
2620 if (i == 4)
2621 DRM_ERROR("FDI train 1 fail!\n");
2622
2623 /* Train 2 */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp);
2631
2632 reg = FDI_RX_CTL(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
Akshay Joshi0206e352011-08-16 15:34:10 -04002641 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= snb_b_fdi_train_param[i];
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(500);
2650
2651 reg = FDI_RX_IIR(pipe);
2652 temp = I915_READ(reg);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655 if (temp & FDI_RX_SYMBOL_LOCK) {
2656 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657 DRM_DEBUG_KMS("FDI train 2 done.\n");
2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 2 fail!\n");
2663
2664 DRM_DEBUG_KMS("FDI train done.\n");
2665}
2666
Daniel Vetter88cefb62012-08-12 19:27:14 +02002667static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002668{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002669 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002670 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002671 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002672 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002673
Jesse Barnesc64e3112010-09-10 11:27:03 -07002674 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002675 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002677
Jesse Barnes0e23b992010-09-10 11:10:00 -07002678 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002679 reg = FDI_RX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002682 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002683 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002687 udelay(200);
2688
2689 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002690 temp = I915_READ(reg);
2691 I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002694 udelay(200);
2695
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002696 /* On Haswell, the PLL configuration for ports and pipes is handled
2697 * separately, as part of DDI setup */
2698 if (!IS_HASWELL(dev)) {
2699 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700 reg = FDI_TX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002704
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002705 POSTING_READ(reg);
2706 udelay(100);
2707 }
Jesse Barnes0e23b992010-09-10 11:10:00 -07002708 }
2709}
2710
Daniel Vetter88cefb62012-08-12 19:27:14 +02002711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
Jesse Barnes291427f2011-07-29 12:42:37 -07002740static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741{
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749 POSTING_READ(SOUTH_CHICKEN1);
2750}
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002751static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752{
2753 struct drm_device *dev = crtc->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756 int pipe = intel_crtc->pipe;
2757 u32 reg, temp;
2758
2759 /* disable CPU FDI tx and PCH FDI rx */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763 POSTING_READ(reg);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~(0x7 << 16);
2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002775 if (HAS_PCH_IBX(dev)) {
2776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002777 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002779 ~FDI_RX_PHASE_SYNC_POINTER_EN));
Jesse Barnes291427f2011-07-29 12:42:37 -07002780 } else if (HAS_PCH_CPT(dev)) {
2781 cpt_phase_pointer_disable(dev, pipe);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002782 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807}
2808
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002809static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810{
Chris Wilson0f911282012-04-17 10:05:38 +01002811 struct drm_device *dev = crtc->dev;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002812
2813 if (crtc->fb == NULL)
2814 return;
2815
Chris Wilson0f911282012-04-17 10:05:38 +01002816 mutex_lock(&dev->struct_mutex);
2817 intel_finish_fb(crtc->fb);
2818 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002819}
2820
Jesse Barnes040484a2011-01-03 12:14:26 -08002821static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822{
2823 struct drm_device *dev = crtc->dev;
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002824 struct intel_encoder *intel_encoder;
Jesse Barnes040484a2011-01-03 12:14:26 -08002825
2826 /*
2827 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828 * must be driven by its own crtc; no sharing is possible.
2829 */
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002830 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002831
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002832 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833 * CPU handles all others */
2834 if (IS_HASWELL(dev)) {
2835 /* It is still unclear how this will work on PPT, so throw up a warning */
2836 WARN_ON(!HAS_PCH_LPT(dev));
2837
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002838 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002839 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840 return true;
2841 } else {
2842 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002843 intel_encoder->type);
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002844 return false;
2845 }
2846 }
2847
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002848 switch (intel_encoder->type) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002849 case INTEL_OUTPUT_EDP:
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002850 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnes040484a2011-01-03 12:14:26 -08002851 return false;
2852 continue;
2853 }
2854 }
2855
2856 return true;
2857}
2858
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002859/* Program iCLKIP clock to the desired frequency */
2860static void lpt_program_iclkip(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865 u32 temp;
2866
2867 /* It is necessary to ungate the pixclk gate prior to programming
2868 * the divisors, and gate it back when it is done.
2869 */
2870 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872 /* Disable SSCCTL */
2873 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875 SBI_SSCCTL_DISABLE);
2876
2877 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878 if (crtc->mode.clock == 20000) {
2879 auxdiv = 1;
2880 divsel = 0x41;
2881 phaseinc = 0x20;
2882 } else {
2883 /* The iCLK virtual clock root frequency is in MHz,
2884 * but the crtc->mode.clock in in KHz. To get the divisors,
2885 * it is necessary to divide one by another, so we
2886 * convert the virtual clock precision to KHz here for higher
2887 * precision.
2888 */
2889 u32 iclk_virtual_root_freq = 172800 * 1000;
2890 u32 iclk_pi_range = 64;
2891 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894 msb_divisor_value = desired_divisor / iclk_pi_range;
2895 pi_value = desired_divisor % iclk_pi_range;
2896
2897 auxdiv = 0;
2898 divsel = msb_divisor_value - 2;
2899 phaseinc = pi_value;
2900 }
2901
2902 /* This should not happen with any sane values */
2903 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909 crtc->mode.clock,
2910 auxdiv,
2911 divsel,
2912 phasedir,
2913 phaseinc);
2914
2915 /* Program SSCDIVINTPHASE6 */
2916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924 intel_sbi_write(dev_priv,
2925 SBI_SSCDIVINTPHASE6,
2926 temp);
2927
2928 /* Program SSCAUXDIV */
2929 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932 intel_sbi_write(dev_priv,
2933 SBI_SSCAUXDIV6,
2934 temp);
2935
2936
2937 /* Enable modulator and associated divider */
2938 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939 temp &= ~SBI_SSCCTL_DISABLE;
2940 intel_sbi_write(dev_priv,
2941 SBI_SSCCTL6,
2942 temp);
2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948}
2949
Jesse Barnesf67a5592011-01-05 10:31:48 -08002950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002959{
2960 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002964 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002965
Chris Wilsone7e164d2012-05-11 09:21:25 +01002966 assert_transcoder_disabled(dev_priv, pipe);
2967
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002968 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002969 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002970
Chris Wilson6f13b7b2012-05-13 09:54:09 +01002971 intel_enable_pch_pll(intel_crtc);
2972
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002973 if (HAS_PCH_LPT(dev)) {
2974 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975 lpt_program_iclkip(crtc);
2976 } else if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002977 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07002978
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002979 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002980 switch (pipe) {
2981 default:
2982 case 0:
2983 temp |= TRANSA_DPLL_ENABLE;
2984 sel = TRANSA_DPLLB_SEL;
2985 break;
2986 case 1:
2987 temp |= TRANSB_DPLL_ENABLE;
2988 sel = TRANSB_DPLLB_SEL;
2989 break;
2990 case 2:
2991 temp |= TRANSC_DPLL_ENABLE;
2992 sel = TRANSC_DPLLB_SEL;
2993 break;
Jesse Barnesd64311a2011-10-12 15:01:33 -07002994 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002995 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996 temp |= sel;
2997 else
2998 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002999 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003000 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003001
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003002 /* set transcoder timing, panel must allow it */
3003 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01003004 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3007
3008 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003011 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003012
Eugeni Dodonovf57e1e32012-05-09 15:37:14 -03003013 if (!IS_HASWELL(dev))
3014 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003015
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003016 /* For PCH DP, enable TRANS_DP_CTL */
3017 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003018 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003020 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003021 reg = TRANS_DP_CTL(pipe);
3022 temp = I915_READ(reg);
3023 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003024 TRANS_DP_SYNC_MASK |
3025 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003026 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003028 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003029
3030 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003031 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003032 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003033 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003034
3035 switch (intel_trans_dp_port_sel(crtc)) {
3036 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003037 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003038 break;
3039 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003040 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003041 break;
3042 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003043 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003044 break;
3045 default:
3046 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003047 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003048 break;
3049 }
3050
Chris Wilson5eddb702010-09-11 13:48:45 +01003051 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003052 }
3053
Jesse Barnes040484a2011-01-03 12:14:26 -08003054 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003055}
3056
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003057static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058{
3059 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061 if (pll == NULL)
3062 return;
3063
3064 if (pll->refcount == 0) {
3065 WARN(1, "bad PCH PLL refcount\n");
3066 return;
3067 }
3068
3069 --pll->refcount;
3070 intel_crtc->pch_pll = NULL;
3071}
3072
3073static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074{
3075 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076 struct intel_pch_pll *pll;
3077 int i;
3078
3079 pll = intel_crtc->pch_pll;
3080 if (pll) {
3081 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082 intel_crtc->base.base.id, pll->pll_reg);
3083 goto prepare;
3084 }
3085
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003086 if (HAS_PCH_IBX(dev_priv->dev)) {
3087 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088 i = intel_crtc->pipe;
3089 pll = &dev_priv->pch_plls[i];
3090
3091 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092 intel_crtc->base.base.id, pll->pll_reg);
3093
3094 goto found;
3095 }
3096
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003097 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098 pll = &dev_priv->pch_plls[i];
3099
3100 /* Only want to check enabled timings first */
3101 if (pll->refcount == 0)
3102 continue;
3103
3104 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105 fp == I915_READ(pll->fp0_reg)) {
3106 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107 intel_crtc->base.base.id,
3108 pll->pll_reg, pll->refcount, pll->active);
3109
3110 goto found;
3111 }
3112 }
3113
3114 /* Ok no matching timings, maybe there's a free one? */
3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117 if (pll->refcount == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119 intel_crtc->base.base.id, pll->pll_reg);
3120 goto found;
3121 }
3122 }
3123
3124 return NULL;
3125
3126found:
3127 intel_crtc->pch_pll = pll;
3128 pll->refcount++;
3129 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130prepare: /* separate function? */
3131 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003132
Chris Wilsone04c7352012-05-02 20:43:56 +01003133 /* Wait for the clocks to stabilize before rewriting the regs */
3134 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003135 POSTING_READ(pll->pll_reg);
3136 udelay(150);
Chris Wilsone04c7352012-05-02 20:43:56 +01003137
3138 I915_WRITE(pll->fp0_reg, fp);
3139 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003140 pll->on = false;
3141 return pll;
3142}
3143
Jesse Barnesd4270e52011-10-11 10:43:02 -07003144void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153 /* Without this, mode sets may fail silently on FDI */
3154 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155 udelay(250);
3156 I915_WRITE(tc2reg, 0);
3157 if (wait_for(I915_READ(dslreg) != temp, 5))
3158 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159 }
3160}
3161
Jesse Barnesf67a5592011-01-05 10:31:48 -08003162static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003167 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003168 int pipe = intel_crtc->pipe;
3169 int plane = intel_crtc->plane;
3170 u32 temp;
3171 bool is_pch_port;
3172
Daniel Vetter08a48462012-07-02 11:43:47 +02003173 WARN_ON(!crtc->enabled);
3174
Jesse Barnesf67a5592011-01-05 10:31:48 -08003175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
3179 intel_update_watermarks(dev);
3180
3181 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182 temp = I915_READ(PCH_LVDS);
3183 if ((temp & LVDS_PORT_EN) == 0)
3184 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185 }
3186
3187 is_pch_port = intel_crtc_driving_pch(crtc);
3188
Daniel Vetter46b6f812012-09-06 22:08:33 +02003189 if (is_pch_port) {
Daniel Vetter88cefb62012-08-12 19:27:14 +02003190 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003191 } else {
3192 assert_fdi_tx_disabled(dev_priv, pipe);
3193 assert_fdi_rx_disabled(dev_priv, pipe);
3194 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003195
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003196 for_each_encoder_on_crtc(dev, crtc, encoder)
3197 if (encoder->pre_enable)
3198 encoder->pre_enable(encoder);
3199
Paulo Zanonifc914632012-10-05 12:05:54 -03003200 if (IS_HASWELL(dev))
3201 intel_ddi_enable_pipe_clock(intel_crtc);
3202
Jesse Barnesf67a5592011-01-05 10:31:48 -08003203 /* Enable panel fitting for LVDS */
3204 if (dev_priv->pch_pf_size &&
3205 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3206 /* Force use of hard-coded filter coefficients
3207 * as some pre-programmed values are broken,
3208 * e.g. x201.
3209 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003210 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3211 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3212 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003213 }
3214
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003215 /*
3216 * On ILK+ LUT must be loaded before the pipe is running but with
3217 * clocks enabled
3218 */
3219 intel_crtc_load_lut(crtc);
3220
Paulo Zanonidae84792012-10-15 15:51:30 -03003221 if (IS_HASWELL(dev)) {
3222 intel_ddi_set_pipe_settings(crtc);
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03003223 intel_ddi_enable_pipe_func(crtc);
Paulo Zanonidae84792012-10-15 15:51:30 -03003224 }
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03003225
Jesse Barnesf67a5592011-01-05 10:31:48 -08003226 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3227 intel_enable_plane(dev_priv, plane, pipe);
3228
3229 if (is_pch_port)
3230 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003231
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003232 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003233 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003234 mutex_unlock(&dev->struct_mutex);
3235
Chris Wilson6b383a72010-09-13 13:54:26 +01003236 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003237
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003238 for_each_encoder_on_crtc(dev, crtc, encoder)
3239 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003240
3241 if (HAS_PCH_CPT(dev))
3242 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003243}
3244
3245static void ironlake_crtc_disable(struct drm_crtc *crtc)
3246{
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003250 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003251 int pipe = intel_crtc->pipe;
3252 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003253 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003254
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003255
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003256 if (!intel_crtc->active)
3257 return;
3258
Daniel Vetterea9d7582012-07-10 10:42:52 +02003259 for_each_encoder_on_crtc(dev, crtc, encoder)
3260 encoder->disable(encoder);
3261
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003262 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003263 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003264 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003265
Jesse Barnesb24e7172011-01-04 15:09:30 -08003266 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003267
Chris Wilson973d04f2011-07-08 12:22:37 +01003268 if (dev_priv->cfb_plane == plane)
3269 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003270
Jesse Barnesb24e7172011-01-04 15:09:30 -08003271 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003272
Paulo Zanoni8d9ddbc2012-10-05 12:05:53 -03003273 if (IS_HASWELL(dev))
3274 intel_ddi_disable_pipe_func(dev_priv, pipe);
3275
Jesse Barnes6be4a602010-09-10 10:26:01 -07003276 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003277 I915_WRITE(PF_CTL(pipe), 0);
3278 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003279
Paulo Zanonifc914632012-10-05 12:05:54 -03003280 if (IS_HASWELL(dev))
3281 intel_ddi_disable_pipe_clock(intel_crtc);
3282
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003283 for_each_encoder_on_crtc(dev, crtc, encoder)
3284 if (encoder->post_disable)
3285 encoder->post_disable(encoder);
3286
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003287 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003288
Jesse Barnes040484a2011-01-03 12:14:26 -08003289 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003290
Jesse Barnes6be4a602010-09-10 10:26:01 -07003291 if (HAS_PCH_CPT(dev)) {
3292 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003293 reg = TRANS_DP_CTL(pipe);
3294 temp = I915_READ(reg);
3295 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003296 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003297 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003298
3299 /* disable DPLL_SEL */
3300 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003301 switch (pipe) {
3302 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003303 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003304 break;
3305 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003306 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003307 break;
3308 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003309 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003310 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003311 break;
3312 default:
3313 BUG(); /* wtf */
3314 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003315 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003316 }
3317
3318 /* disable PCH DPLL */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003319 intel_disable_pch_pll(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003320
Daniel Vetter88cefb62012-08-12 19:27:14 +02003321 ironlake_fdi_pll_disable(intel_crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +01003322
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003323 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003324 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003325
3326 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003327 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003328 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003329}
3330
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003331static void ironlake_crtc_off(struct drm_crtc *crtc)
3332{
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334 intel_put_pch_pll(intel_crtc);
3335}
3336
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003337static void haswell_crtc_off(struct drm_crtc *crtc)
3338{
3339 intel_ddi_put_crtc_pll(crtc);
3340}
3341
Daniel Vetter02e792f2009-09-15 22:57:34 +02003342static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3343{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003344 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003345 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003346 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003347
Chris Wilson23f09ce2010-08-12 13:53:37 +01003348 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003349 dev_priv->mm.interruptible = false;
3350 (void) intel_overlay_switch_off(intel_crtc->overlay);
3351 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003352 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003353 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003354
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003355 /* Let userspace switch the overlay on again. In most cases userspace
3356 * has to recompute where to put it anyway.
3357 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003358}
3359
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003360static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003361{
3362 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003365 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003366 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003367 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003368
Daniel Vetter08a48462012-07-02 11:43:47 +02003369 WARN_ON(!crtc->enabled);
3370
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003371 if (intel_crtc->active)
3372 return;
3373
3374 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003375 intel_update_watermarks(dev);
3376
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003377 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003378 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003379 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003380
3381 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003382 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003383
3384 /* Give the overlay scaler a chance to enable if it's on this pipe */
3385 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003386 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003387
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003390}
3391
3392static void i9xx_crtc_disable(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003397 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003398 int pipe = intel_crtc->pipe;
3399 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003400
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003401
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003402 if (!intel_crtc->active)
3403 return;
3404
Daniel Vetterea9d7582012-07-10 10:42:52 +02003405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->disable(encoder);
3407
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003408 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003409 intel_crtc_wait_for_pending_flips(crtc);
3410 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003411 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003412 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003413
Chris Wilson973d04f2011-07-08 12:22:37 +01003414 if (dev_priv->cfb_plane == plane)
3415 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003416
Jesse Barnesb24e7172011-01-04 15:09:30 -08003417 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003418 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003419 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003420
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003421 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003422 intel_update_fbc(dev);
3423 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003424}
3425
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003426static void i9xx_crtc_off(struct drm_crtc *crtc)
3427{
3428}
3429
Daniel Vetter976f8a22012-07-08 22:34:21 +02003430static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3431 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003432{
3433 struct drm_device *dev = crtc->dev;
3434 struct drm_i915_master_private *master_priv;
3435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003437
3438 if (!dev->primary->master)
3439 return;
3440
3441 master_priv = dev->primary->master->driver_priv;
3442 if (!master_priv->sarea_priv)
3443 return;
3444
Jesse Barnes79e53942008-11-07 14:24:08 -08003445 switch (pipe) {
3446 case 0:
3447 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3448 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3449 break;
3450 case 1:
3451 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3452 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3453 break;
3454 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003455 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003456 break;
3457 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003458}
3459
Daniel Vetter976f8a22012-07-08 22:34:21 +02003460/**
3461 * Sets the power management mode of the pipe and plane.
3462 */
3463void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01003464{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003465 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003466 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003467 struct intel_encoder *intel_encoder;
3468 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003469
Daniel Vetter976f8a22012-07-08 22:34:21 +02003470 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3471 enable |= intel_encoder->connectors_active;
3472
3473 if (enable)
3474 dev_priv->display.crtc_enable(crtc);
3475 else
3476 dev_priv->display.crtc_disable(crtc);
3477
3478 intel_crtc_update_sarea(crtc, enable);
3479}
3480
3481static void intel_crtc_noop(struct drm_crtc *crtc)
3482{
3483}
3484
3485static void intel_crtc_disable(struct drm_crtc *crtc)
3486{
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_connector *connector;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490
3491 /* crtc should still be enabled when we disable it. */
3492 WARN_ON(!crtc->enabled);
3493
3494 dev_priv->display.crtc_disable(crtc);
3495 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003496 dev_priv->display.off(crtc);
3497
Chris Wilson931872f2012-01-16 23:01:13 +00003498 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3499 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003500
3501 if (crtc->fb) {
3502 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003503 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003504 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003505 crtc->fb = NULL;
3506 }
3507
3508 /* Update computed state. */
3509 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3510 if (!connector->encoder || !connector->encoder->crtc)
3511 continue;
3512
3513 if (connector->encoder->crtc != crtc)
3514 continue;
3515
3516 connector->dpms = DRM_MODE_DPMS_OFF;
3517 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003518 }
3519}
3520
Daniel Vettera261b242012-07-26 19:21:47 +02003521void intel_modeset_disable(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003522{
Daniel Vettera261b242012-07-26 19:21:47 +02003523 struct drm_crtc *crtc;
3524
3525 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3526 if (crtc->enabled)
3527 intel_crtc_disable(crtc);
3528 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003529}
3530
Daniel Vetter1f703852012-07-11 16:51:39 +02003531void intel_encoder_noop(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003532{
Jesse Barnes79e53942008-11-07 14:24:08 -08003533}
3534
Chris Wilsonea5b2132010-08-04 13:50:23 +01003535void intel_encoder_destroy(struct drm_encoder *encoder)
3536{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003537 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003538
Chris Wilsonea5b2132010-08-04 13:50:23 +01003539 drm_encoder_cleanup(encoder);
3540 kfree(intel_encoder);
3541}
3542
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003543/* Simple dpms helper for encodres with just one connector, no cloning and only
3544 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3545 * state of the entire output pipe. */
3546void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3547{
3548 if (mode == DRM_MODE_DPMS_ON) {
3549 encoder->connectors_active = true;
3550
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003551 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003552 } else {
3553 encoder->connectors_active = false;
3554
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003555 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003556 }
3557}
3558
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003559/* Cross check the actual hw state with our own modeset state tracking (and it's
3560 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02003561static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003562{
3563 if (connector->get_hw_state(connector)) {
3564 struct intel_encoder *encoder = connector->encoder;
3565 struct drm_crtc *crtc;
3566 bool encoder_enabled;
3567 enum pipe pipe;
3568
3569 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3570 connector->base.base.id,
3571 drm_get_connector_name(&connector->base));
3572
3573 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3574 "wrong connector dpms state\n");
3575 WARN(connector->base.encoder != &encoder->base,
3576 "active connector not linked to encoder\n");
3577 WARN(!encoder->connectors_active,
3578 "encoder->connectors_active not set\n");
3579
3580 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3581 WARN(!encoder_enabled, "encoder not enabled\n");
3582 if (WARN_ON(!encoder->base.crtc))
3583 return;
3584
3585 crtc = encoder->base.crtc;
3586
3587 WARN(!crtc->enabled, "crtc not enabled\n");
3588 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3589 WARN(pipe != to_intel_crtc(crtc)->pipe,
3590 "encoder active on the wrong pipe\n");
3591 }
3592}
3593
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003594/* Even simpler default implementation, if there's really no special case to
3595 * consider. */
3596void intel_connector_dpms(struct drm_connector *connector, int mode)
3597{
3598 struct intel_encoder *encoder = intel_attached_encoder(connector);
3599
3600 /* All the simple cases only support two dpms states. */
3601 if (mode != DRM_MODE_DPMS_ON)
3602 mode = DRM_MODE_DPMS_OFF;
3603
3604 if (mode == connector->dpms)
3605 return;
3606
3607 connector->dpms = mode;
3608
3609 /* Only need to change hw state when actually enabled */
3610 if (encoder->base.crtc)
3611 intel_encoder_dpms(encoder, mode);
3612 else
Daniel Vetter8af6cf82012-07-10 09:50:11 +02003613 WARN_ON(encoder->connectors_active != false);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003614
Daniel Vetterb9805142012-08-31 17:37:33 +02003615 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003616}
3617
Daniel Vetterf0947c32012-07-02 13:10:34 +02003618/* Simple connector->get_hw_state implementation for encoders that support only
3619 * one connector and no cloning and hence the encoder state determines the state
3620 * of the connector. */
3621bool intel_connector_get_hw_state(struct intel_connector *connector)
3622{
Daniel Vetter24929352012-07-02 20:28:59 +02003623 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02003624 struct intel_encoder *encoder = connector->encoder;
3625
3626 return encoder->get_hw_state(encoder, &pipe);
3627}
3628
Jesse Barnes79e53942008-11-07 14:24:08 -08003629static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
Daniel Vetter35313cd2012-07-20 10:30:45 +02003630 const struct drm_display_mode *mode,
Jesse Barnes79e53942008-11-07 14:24:08 -08003631 struct drm_display_mode *adjusted_mode)
3632{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003633 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003634
Eric Anholtbad720f2009-10-22 16:11:14 -07003635 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003636 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003637 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3638 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003639 }
Chris Wilson89749352010-09-12 18:25:19 +01003640
Daniel Vetterf9bef082012-04-15 19:53:19 +02003641 /* All interlaced capable intel hw wants timings in frames. Note though
3642 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3643 * timings, so we need to be careful not to clobber these.*/
3644 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3645 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01003646
Chris Wilson44f46b422012-06-21 13:19:59 +03003647 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3648 * with a hsync front porch of 0.
3649 */
3650 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3651 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3652 return false;
3653
Jesse Barnes79e53942008-11-07 14:24:08 -08003654 return true;
3655}
3656
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003657static int valleyview_get_display_clock_speed(struct drm_device *dev)
3658{
3659 return 400000; /* FIXME */
3660}
3661
Jesse Barnese70236a2009-09-21 10:42:27 -07003662static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003663{
Jesse Barnese70236a2009-09-21 10:42:27 -07003664 return 400000;
3665}
Jesse Barnes79e53942008-11-07 14:24:08 -08003666
Jesse Barnese70236a2009-09-21 10:42:27 -07003667static int i915_get_display_clock_speed(struct drm_device *dev)
3668{
3669 return 333000;
3670}
Jesse Barnes79e53942008-11-07 14:24:08 -08003671
Jesse Barnese70236a2009-09-21 10:42:27 -07003672static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3673{
3674 return 200000;
3675}
Jesse Barnes79e53942008-11-07 14:24:08 -08003676
Jesse Barnese70236a2009-09-21 10:42:27 -07003677static int i915gm_get_display_clock_speed(struct drm_device *dev)
3678{
3679 u16 gcfgc = 0;
3680
3681 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3682
3683 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003684 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003685 else {
3686 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3687 case GC_DISPLAY_CLOCK_333_MHZ:
3688 return 333000;
3689 default:
3690 case GC_DISPLAY_CLOCK_190_200_MHZ:
3691 return 190000;
3692 }
3693 }
3694}
Jesse Barnes79e53942008-11-07 14:24:08 -08003695
Jesse Barnese70236a2009-09-21 10:42:27 -07003696static int i865_get_display_clock_speed(struct drm_device *dev)
3697{
3698 return 266000;
3699}
3700
3701static int i855_get_display_clock_speed(struct drm_device *dev)
3702{
3703 u16 hpllcc = 0;
3704 /* Assume that the hardware is in the high speed state. This
3705 * should be the default.
3706 */
3707 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3708 case GC_CLOCK_133_200:
3709 case GC_CLOCK_100_200:
3710 return 200000;
3711 case GC_CLOCK_166_250:
3712 return 250000;
3713 case GC_CLOCK_100_133:
3714 return 133000;
3715 }
3716
3717 /* Shouldn't happen */
3718 return 0;
3719}
3720
3721static int i830_get_display_clock_speed(struct drm_device *dev)
3722{
3723 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003724}
3725
Zhenyu Wang2c072452009-06-05 15:38:42 +08003726struct fdi_m_n {
3727 u32 tu;
3728 u32 gmch_m;
3729 u32 gmch_n;
3730 u32 link_m;
3731 u32 link_n;
3732};
3733
3734static void
3735fdi_reduce_ratio(u32 *num, u32 *den)
3736{
3737 while (*num > 0xffffff || *den > 0xffffff) {
3738 *num >>= 1;
3739 *den >>= 1;
3740 }
3741}
3742
Zhenyu Wang2c072452009-06-05 15:38:42 +08003743static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003744ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3745 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003746{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003747 m_n->tu = 64; /* default size */
3748
Chris Wilson22ed1112010-12-04 01:01:29 +00003749 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3750 m_n->gmch_m = bits_per_pixel * pixel_clock;
3751 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003752 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3753
Chris Wilson22ed1112010-12-04 01:01:29 +00003754 m_n->link_m = pixel_clock;
3755 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003756 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3757}
3758
Chris Wilsona7615032011-01-12 17:04:08 +00003759static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3760{
Keith Packard72bbe582011-09-26 16:09:45 -07003761 if (i915_panel_use_ssc >= 0)
3762 return i915_panel_use_ssc != 0;
3763 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07003764 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00003765}
3766
Jesse Barnes5a354202011-06-24 12:19:22 -07003767/**
3768 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3769 * @crtc: CRTC structure
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003770 * @mode: requested mode
Jesse Barnes5a354202011-06-24 12:19:22 -07003771 *
3772 * A pipe may be connected to one or more outputs. Based on the depth of the
3773 * attached framebuffer, choose a good color depth to use on the pipe.
3774 *
3775 * If possible, match the pipe depth to the fb depth. In some cases, this
3776 * isn't ideal, because the connected output supports a lesser or restricted
3777 * set of depths. Resolve that here:
3778 * LVDS typically supports only 6bpc, so clamp down in that case
3779 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3780 * Displays may support a restricted set as well, check EDID and clamp as
3781 * appropriate.
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003782 * DP may want to dither down to 6bpc to fit larger modes
Jesse Barnes5a354202011-06-24 12:19:22 -07003783 *
3784 * RETURNS:
3785 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3786 * true if they don't match).
3787 */
3788static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02003789 struct drm_framebuffer *fb,
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003790 unsigned int *pipe_bpp,
3791 struct drm_display_mode *mode)
Jesse Barnes5a354202011-06-24 12:19:22 -07003792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes5a354202011-06-24 12:19:22 -07003795 struct drm_connector *connector;
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003796 struct intel_encoder *intel_encoder;
Jesse Barnes5a354202011-06-24 12:19:22 -07003797 unsigned int display_bpc = UINT_MAX, bpc;
3798
3799 /* Walk the encoders & connectors on this crtc, get min bpc */
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003800 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes5a354202011-06-24 12:19:22 -07003801
3802 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3803 unsigned int lvds_bpc;
3804
3805 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3806 LVDS_A3_POWER_UP)
3807 lvds_bpc = 8;
3808 else
3809 lvds_bpc = 6;
3810
3811 if (lvds_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003812 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003813 display_bpc = lvds_bpc;
3814 }
3815 continue;
3816 }
3817
Jesse Barnes5a354202011-06-24 12:19:22 -07003818 /* Not one of the known troublemakers, check the EDID */
3819 list_for_each_entry(connector, &dev->mode_config.connector_list,
3820 head) {
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003821 if (connector->encoder != &intel_encoder->base)
Jesse Barnes5a354202011-06-24 12:19:22 -07003822 continue;
3823
Jesse Barnes62ac41a2011-07-28 12:55:14 -07003824 /* Don't use an invalid EDID bpc value */
3825 if (connector->display_info.bpc &&
3826 connector->display_info.bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003827 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003828 display_bpc = connector->display_info.bpc;
3829 }
3830 }
3831
3832 /*
3833 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3834 * through, clamp it down. (Note: >12bpc will be caught below.)
3835 */
3836 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3837 if (display_bpc > 8 && display_bpc < 12) {
Adam Jackson82820492011-10-10 16:33:34 -04003838 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003839 display_bpc = 12;
3840 } else {
Adam Jackson82820492011-10-10 16:33:34 -04003841 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003842 display_bpc = 8;
3843 }
3844 }
3845 }
3846
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003847 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3848 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3849 display_bpc = 6;
3850 }
3851
Jesse Barnes5a354202011-06-24 12:19:22 -07003852 /*
3853 * We could just drive the pipe at the highest bpc all the time and
3854 * enable dithering as needed, but that costs bandwidth. So choose
3855 * the minimum value that expresses the full color range of the fb but
3856 * also stays within the max display bpc discovered above.
3857 */
3858
Daniel Vetter94352cf2012-07-05 22:51:56 +02003859 switch (fb->depth) {
Jesse Barnes5a354202011-06-24 12:19:22 -07003860 case 8:
3861 bpc = 8; /* since we go through a colormap */
3862 break;
3863 case 15:
3864 case 16:
3865 bpc = 6; /* min is 18bpp */
3866 break;
3867 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07003868 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07003869 break;
3870 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07003871 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07003872 break;
3873 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07003874 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07003875 break;
3876 default:
3877 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3878 bpc = min((unsigned int)8, display_bpc);
3879 break;
3880 }
3881
Keith Packard578393c2011-09-05 11:53:21 -07003882 display_bpc = min(display_bpc, bpc);
3883
Adam Jackson82820492011-10-10 16:33:34 -04003884 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3885 bpc, display_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003886
Keith Packard578393c2011-09-05 11:53:21 -07003887 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07003888
3889 return display_bpc != bpc;
3890}
3891
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003892static int vlv_get_refclk(struct drm_crtc *crtc)
3893{
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 int refclk = 27000; /* for DP & HDMI */
3897
3898 return 100000; /* only one validated so far */
3899
3900 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3901 refclk = 96000;
3902 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3903 if (intel_panel_use_ssc(dev_priv))
3904 refclk = 100000;
3905 else
3906 refclk = 96000;
3907 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3908 refclk = 100000;
3909 }
3910
3911 return refclk;
3912}
3913
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003914static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3915{
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918 int refclk;
3919
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003920 if (IS_VALLEYVIEW(dev)) {
3921 refclk = vlv_get_refclk(crtc);
3922 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003923 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3924 refclk = dev_priv->lvds_ssc_freq * 1000;
3925 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3926 refclk / 1000);
3927 } else if (!IS_GEN2(dev)) {
3928 refclk = 96000;
3929 } else {
3930 refclk = 48000;
3931 }
3932
3933 return refclk;
3934}
3935
3936static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3937 intel_clock_t *clock)
3938{
3939 /* SDVO TV has fixed PLL values depend on its clock range,
3940 this mirrors vbios setting. */
3941 if (adjusted_mode->clock >= 100000
3942 && adjusted_mode->clock < 140500) {
3943 clock->p1 = 2;
3944 clock->p2 = 10;
3945 clock->n = 3;
3946 clock->m1 = 16;
3947 clock->m2 = 8;
3948 } else if (adjusted_mode->clock >= 140500
3949 && adjusted_mode->clock <= 200000) {
3950 clock->p1 = 1;
3951 clock->p2 = 10;
3952 clock->n = 6;
3953 clock->m1 = 12;
3954 clock->m2 = 8;
3955 }
3956}
3957
Jesse Barnesa7516a02011-12-15 12:30:37 -08003958static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3959 intel_clock_t *clock,
3960 intel_clock_t *reduced_clock)
3961{
3962 struct drm_device *dev = crtc->dev;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3965 int pipe = intel_crtc->pipe;
3966 u32 fp, fp2 = 0;
3967
3968 if (IS_PINEVIEW(dev)) {
3969 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3970 if (reduced_clock)
3971 fp2 = (1 << reduced_clock->n) << 16 |
3972 reduced_clock->m1 << 8 | reduced_clock->m2;
3973 } else {
3974 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3975 if (reduced_clock)
3976 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3977 reduced_clock->m2;
3978 }
3979
3980 I915_WRITE(FP0(pipe), fp);
3981
3982 intel_crtc->lowfreq_avail = false;
3983 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3984 reduced_clock && i915_powersave) {
3985 I915_WRITE(FP1(pipe), fp2);
3986 intel_crtc->lowfreq_avail = true;
3987 } else {
3988 I915_WRITE(FP1(pipe), fp);
3989 }
3990}
3991
Daniel Vetter93e537a2012-03-28 23:11:26 +02003992static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3993 struct drm_display_mode *adjusted_mode)
3994{
3995 struct drm_device *dev = crtc->dev;
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3998 int pipe = intel_crtc->pipe;
Chris Wilson284d5df2012-04-14 17:41:59 +01003999 u32 temp;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004000
4001 temp = I915_READ(LVDS);
4002 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4003 if (pipe == 1) {
4004 temp |= LVDS_PIPEB_SELECT;
4005 } else {
4006 temp &= ~LVDS_PIPEB_SELECT;
4007 }
4008 /* set the corresponsding LVDS_BORDER bit */
4009 temp |= dev_priv->lvds_border_bits;
4010 /* Set the B0-B3 data pairs corresponding to whether we're going to
4011 * set the DPLLs for dual-channel mode or not.
4012 */
4013 if (clock->p2 == 7)
4014 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4015 else
4016 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4017
4018 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4019 * appropriately here, but we need to look more thoroughly into how
4020 * panels behave in the two modes.
4021 */
4022 /* set the dithering flag on LVDS as needed */
4023 if (INTEL_INFO(dev)->gen >= 4) {
4024 if (dev_priv->lvds_dither)
4025 temp |= LVDS_ENABLE_DITHER;
4026 else
4027 temp &= ~LVDS_ENABLE_DITHER;
4028 }
Chris Wilson284d5df2012-04-14 17:41:59 +01004029 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Daniel Vetter93e537a2012-03-28 23:11:26 +02004030 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004031 temp |= LVDS_HSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004032 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004033 temp |= LVDS_VSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004034 I915_WRITE(LVDS, temp);
4035}
4036
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004037static void vlv_update_pll(struct drm_crtc *crtc,
4038 struct drm_display_mode *mode,
4039 struct drm_display_mode *adjusted_mode,
4040 intel_clock_t *clock, intel_clock_t *reduced_clock,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304041 int num_connectors)
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 int pipe = intel_crtc->pipe;
4047 u32 dpll, mdiv, pdiv;
4048 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304049 bool is_sdvo;
4050 u32 temp;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004051
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304052 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4053 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4054
4055 dpll = DPLL_VGA_MODE_DIS;
4056 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4057 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4058 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4059
4060 I915_WRITE(DPLL(pipe), dpll);
4061 POSTING_READ(DPLL(pipe));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004062
4063 bestn = clock->n;
4064 bestm1 = clock->m1;
4065 bestm2 = clock->m2;
4066 bestp1 = clock->p1;
4067 bestp2 = clock->p2;
4068
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304069 /*
4070 * In Valleyview PLL and program lane counter registers are exposed
4071 * through DPIO interface
4072 */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004073 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4074 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4075 mdiv |= ((bestn << DPIO_N_SHIFT));
4076 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4077 mdiv |= (1 << DPIO_K_SHIFT);
4078 mdiv |= DPIO_ENABLE_CALIBRATION;
4079 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4080
4081 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4082
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304083 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004084 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304085 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4086 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004087 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4088
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304089 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004090
4091 dpll |= DPLL_VCO_ENABLE;
4092 I915_WRITE(DPLL(pipe), dpll);
4093 POSTING_READ(DPLL(pipe));
4094 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4095 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4096
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304097 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004098
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304099 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4100 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4101
4102 I915_WRITE(DPLL(pipe), dpll);
4103
4104 /* Wait for the clocks to stabilize. */
4105 POSTING_READ(DPLL(pipe));
4106 udelay(150);
4107
4108 temp = 0;
4109 if (is_sdvo) {
4110 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004111 if (temp > 1)
4112 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4113 else
4114 temp = 0;
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004115 }
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304116 I915_WRITE(DPLL_MD(pipe), temp);
4117 POSTING_READ(DPLL_MD(pipe));
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004118
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304119 /* Now program lane control registers */
4120 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4121 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4122 {
4123 temp = 0x1000C4;
4124 if(pipe == 1)
4125 temp |= (1 << 21);
4126 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4127 }
4128 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4129 {
4130 temp = 0x1000C4;
4131 if(pipe == 1)
4132 temp |= (1 << 21);
4133 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4134 }
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004135}
4136
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004137static void i9xx_update_pll(struct drm_crtc *crtc,
4138 struct drm_display_mode *mode,
4139 struct drm_display_mode *adjusted_mode,
4140 intel_clock_t *clock, intel_clock_t *reduced_clock,
4141 int num_connectors)
4142{
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4146 int pipe = intel_crtc->pipe;
4147 u32 dpll;
4148 bool is_sdvo;
4149
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304150 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4151
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004152 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4153 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4154
4155 dpll = DPLL_VGA_MODE_DIS;
4156
4157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4158 dpll |= DPLLB_MODE_LVDS;
4159 else
4160 dpll |= DPLLB_MODE_DAC_SERIAL;
4161 if (is_sdvo) {
4162 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4163 if (pixel_multiplier > 1) {
4164 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4165 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4166 }
4167 dpll |= DPLL_DVO_HIGH_SPEED;
4168 }
4169 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4170 dpll |= DPLL_DVO_HIGH_SPEED;
4171
4172 /* compute bitmask from p1 value */
4173 if (IS_PINEVIEW(dev))
4174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4175 else {
4176 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4177 if (IS_G4X(dev) && reduced_clock)
4178 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4179 }
4180 switch (clock->p2) {
4181 case 5:
4182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4183 break;
4184 case 7:
4185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4186 break;
4187 case 10:
4188 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4189 break;
4190 case 14:
4191 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4192 break;
4193 }
4194 if (INTEL_INFO(dev)->gen >= 4)
4195 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4196
4197 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4198 dpll |= PLL_REF_INPUT_TVCLKINBC;
4199 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4200 /* XXX: just matching BIOS for now */
4201 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4202 dpll |= 3;
4203 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4204 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4205 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4206 else
4207 dpll |= PLL_REF_INPUT_DREFCLK;
4208
4209 dpll |= DPLL_VCO_ENABLE;
4210 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4211 POSTING_READ(DPLL(pipe));
4212 udelay(150);
4213
4214 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4215 * This is an exception to the general rule that mode_set doesn't turn
4216 * things on.
4217 */
4218 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4219 intel_update_lvds(crtc, clock, adjusted_mode);
4220
4221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4222 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4223
4224 I915_WRITE(DPLL(pipe), dpll);
4225
4226 /* Wait for the clocks to stabilize. */
4227 POSTING_READ(DPLL(pipe));
4228 udelay(150);
4229
4230 if (INTEL_INFO(dev)->gen >= 4) {
4231 u32 temp = 0;
4232 if (is_sdvo) {
4233 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4234 if (temp > 1)
4235 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4236 else
4237 temp = 0;
4238 }
4239 I915_WRITE(DPLL_MD(pipe), temp);
4240 } else {
4241 /* The pixel multiplier can only be updated once the
4242 * DPLL is enabled and the clocks are stable.
4243 *
4244 * So write it again.
4245 */
4246 I915_WRITE(DPLL(pipe), dpll);
4247 }
4248}
4249
4250static void i8xx_update_pll(struct drm_crtc *crtc,
4251 struct drm_display_mode *adjusted_mode,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304252 intel_clock_t *clock, intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004253 int num_connectors)
4254{
4255 struct drm_device *dev = crtc->dev;
4256 struct drm_i915_private *dev_priv = dev->dev_private;
4257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4258 int pipe = intel_crtc->pipe;
4259 u32 dpll;
4260
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304261 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4262
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004263 dpll = DPLL_VGA_MODE_DIS;
4264
4265 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4266 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4267 } else {
4268 if (clock->p1 == 2)
4269 dpll |= PLL_P1_DIVIDE_BY_TWO;
4270 else
4271 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4272 if (clock->p2 == 4)
4273 dpll |= PLL_P2_DIVIDE_BY_4;
4274 }
4275
4276 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4277 /* XXX: just matching BIOS for now */
4278 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4279 dpll |= 3;
4280 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4281 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4282 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4283 else
4284 dpll |= PLL_REF_INPUT_DREFCLK;
4285
4286 dpll |= DPLL_VCO_ENABLE;
4287 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4288 POSTING_READ(DPLL(pipe));
4289 udelay(150);
4290
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004291 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4292 * This is an exception to the general rule that mode_set doesn't turn
4293 * things on.
4294 */
4295 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4296 intel_update_lvds(crtc, clock, adjusted_mode);
4297
Daniel Vetter5b5896e2012-09-11 12:37:55 +02004298 I915_WRITE(DPLL(pipe), dpll);
4299
4300 /* Wait for the clocks to stabilize. */
4301 POSTING_READ(DPLL(pipe));
4302 udelay(150);
4303
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004304 /* The pixel multiplier can only be updated once the
4305 * DPLL is enabled and the clocks are stable.
4306 *
4307 * So write it again.
4308 */
4309 I915_WRITE(DPLL(pipe), dpll);
4310}
4311
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004312static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4313 struct drm_display_mode *mode,
4314 struct drm_display_mode *adjusted_mode)
4315{
4316 struct drm_device *dev = intel_crtc->base.dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 enum pipe pipe = intel_crtc->pipe;
4319 uint32_t vsyncshift;
4320
4321 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4322 /* the chip adds 2 halflines automatically */
4323 adjusted_mode->crtc_vtotal -= 1;
4324 adjusted_mode->crtc_vblank_end -= 1;
4325 vsyncshift = adjusted_mode->crtc_hsync_start
4326 - adjusted_mode->crtc_htotal / 2;
4327 } else {
4328 vsyncshift = 0;
4329 }
4330
4331 if (INTEL_INFO(dev)->gen > 3)
4332 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4333
4334 I915_WRITE(HTOTAL(pipe),
4335 (adjusted_mode->crtc_hdisplay - 1) |
4336 ((adjusted_mode->crtc_htotal - 1) << 16));
4337 I915_WRITE(HBLANK(pipe),
4338 (adjusted_mode->crtc_hblank_start - 1) |
4339 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4340 I915_WRITE(HSYNC(pipe),
4341 (adjusted_mode->crtc_hsync_start - 1) |
4342 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4343
4344 I915_WRITE(VTOTAL(pipe),
4345 (adjusted_mode->crtc_vdisplay - 1) |
4346 ((adjusted_mode->crtc_vtotal - 1) << 16));
4347 I915_WRITE(VBLANK(pipe),
4348 (adjusted_mode->crtc_vblank_start - 1) |
4349 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4350 I915_WRITE(VSYNC(pipe),
4351 (adjusted_mode->crtc_vsync_start - 1) |
4352 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4353
4354 /* pipesrc controls the size that is scaled from, which should
4355 * always be the user's requested size.
4356 */
4357 I915_WRITE(PIPESRC(pipe),
4358 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4359}
4360
Eric Anholtf564048e2011-03-30 13:01:02 -07004361static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4362 struct drm_display_mode *mode,
4363 struct drm_display_mode *adjusted_mode,
4364 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004365 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004366{
4367 struct drm_device *dev = crtc->dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004371 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004372 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004373 intel_clock_t clock, reduced_clock;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004374 u32 dspcntr, pipeconf;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004375 bool ok, has_reduced_clock = false, is_sdvo = false;
4376 bool is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004377 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004378 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004379 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004380
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02004381 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004382 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004383 case INTEL_OUTPUT_LVDS:
4384 is_lvds = true;
4385 break;
4386 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004387 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004388 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004389 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004390 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004391 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004392 case INTEL_OUTPUT_TVOUT:
4393 is_tv = true;
4394 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004395 case INTEL_OUTPUT_DISPLAYPORT:
4396 is_dp = true;
4397 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004398 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004399
Eric Anholtc751ce42010-03-25 11:48:48 -07004400 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004401 }
4402
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004403 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004404
Ma Lingd4906092009-03-18 20:13:27 +08004405 /*
4406 * Returns a set of divisors for the desired target clock with the given
4407 * refclk, or FALSE. The returned values represent the clock equation:
4408 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4409 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004410 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004411 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4412 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004413 if (!ok) {
4414 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004415 return -EINVAL;
4416 }
4417
4418 /* Ensure that the cursor is valid for the new mode before changing... */
4419 intel_crtc_update_cursor(crtc, true);
4420
4421 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004422 /*
4423 * Ensure we match the reduced clock's P to the target clock.
4424 * If the clocks don't match, we can't switch the display clock
4425 * by using the FP0/FP1. In such case we will disable the LVDS
4426 * downclock feature.
4427 */
Eric Anholtf564048e2011-03-30 13:01:02 -07004428 has_reduced_clock = limit->find_pll(limit, crtc,
4429 dev_priv->lvds_downclock,
4430 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004431 &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004432 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004433 }
4434
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004435 if (is_sdvo && is_tv)
4436 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004437
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004438 if (IS_GEN2(dev))
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304439 i8xx_update_pll(crtc, adjusted_mode, &clock,
4440 has_reduced_clock ? &reduced_clock : NULL,
4441 num_connectors);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004442 else if (IS_VALLEYVIEW(dev))
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304443 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4444 has_reduced_clock ? &reduced_clock : NULL,
4445 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004446 else
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004447 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4448 has_reduced_clock ? &reduced_clock : NULL,
4449 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004450
4451 /* setup pipeconf */
4452 pipeconf = I915_READ(PIPECONF(pipe));
4453
4454 /* Set up the display plane register */
4455 dspcntr = DISPPLANE_GAMMA_ENABLE;
4456
Eric Anholt929c77f2011-03-30 13:01:04 -07004457 if (pipe == 0)
4458 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4459 else
4460 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004461
4462 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4463 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4464 * core speed.
4465 *
4466 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4467 * pipe == 0 check?
4468 */
4469 if (mode->clock >
4470 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4471 pipeconf |= PIPECONF_DOUBLE_WIDE;
4472 else
4473 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4474 }
4475
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004476 /* default to 8bpc */
4477 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4478 if (is_dp) {
4479 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4480 pipeconf |= PIPECONF_BPP_6 |
4481 PIPECONF_DITHER_EN |
4482 PIPECONF_DITHER_TYPE_SP;
4483 }
4484 }
4485
Gajanan Bhat19c03922012-09-27 19:13:07 +05304486 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4487 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4488 pipeconf |= PIPECONF_BPP_6 |
4489 PIPECONF_ENABLE |
4490 I965_PIPECONF_ACTIVE;
4491 }
4492 }
4493
Eric Anholtf564048e2011-03-30 13:01:02 -07004494 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4495 drm_mode_debug_printmodeline(mode);
4496
Jesse Barnesa7516a02011-12-15 12:30:37 -08004497 if (HAS_PIPE_CXSR(dev)) {
4498 if (intel_crtc->lowfreq_avail) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004499 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4500 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004501 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07004502 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4503 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4504 }
4505 }
4506
Keith Packard617cf882012-02-08 13:53:38 -08004507 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Daniel Vetterdbb02572012-01-28 14:49:23 +01004508 if (!IS_GEN2(dev) &&
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004509 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Eric Anholtf564048e2011-03-30 13:01:02 -07004510 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004511 else
Keith Packard617cf882012-02-08 13:53:38 -08004512 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004513
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004514 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Eric Anholtf564048e2011-03-30 13:01:02 -07004515
4516 /* pipesrc and dspsize control the size that is scaled from,
4517 * which should always be the user's requested size.
4518 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004519 I915_WRITE(DSPSIZE(plane),
4520 ((mode->vdisplay - 1) << 16) |
4521 (mode->hdisplay - 1));
4522 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004523
Eric Anholtf564048e2011-03-30 13:01:02 -07004524 I915_WRITE(PIPECONF(pipe), pipeconf);
4525 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004526 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004527
4528 intel_wait_for_vblank(dev, pipe);
4529
Eric Anholtf564048e2011-03-30 13:01:02 -07004530 I915_WRITE(DSPCNTR(plane), dspcntr);
4531 POSTING_READ(DSPCNTR(plane));
4532
Daniel Vetter94352cf2012-07-05 22:51:56 +02004533 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07004534
4535 intel_update_watermarks(dev);
4536
Eric Anholtf564048e2011-03-30 13:01:02 -07004537 return ret;
4538}
4539
Keith Packard9fb526d2011-09-26 22:24:57 -07004540/*
4541 * Initialize reference clocks when the driver loads
4542 */
4543void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004544{
4545 struct drm_i915_private *dev_priv = dev->dev_private;
4546 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004547 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004548 u32 temp;
4549 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004550 bool has_cpu_edp = false;
4551 bool has_pch_edp = false;
4552 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004553 bool has_ck505 = false;
4554 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004555
4556 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004557 list_for_each_entry(encoder, &mode_config->encoder_list,
4558 base.head) {
4559 switch (encoder->type) {
4560 case INTEL_OUTPUT_LVDS:
4561 has_panel = true;
4562 has_lvds = true;
4563 break;
4564 case INTEL_OUTPUT_EDP:
4565 has_panel = true;
4566 if (intel_encoder_is_pch_edp(&encoder->base))
4567 has_pch_edp = true;
4568 else
4569 has_cpu_edp = true;
4570 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004571 }
4572 }
4573
Keith Packard99eb6a02011-09-26 14:29:12 -07004574 if (HAS_PCH_IBX(dev)) {
4575 has_ck505 = dev_priv->display_clock_mode;
4576 can_ssc = has_ck505;
4577 } else {
4578 has_ck505 = false;
4579 can_ssc = true;
4580 }
4581
4582 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4583 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4584 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004585
4586 /* Ironlake: try to setup display ref clock before DPLL
4587 * enabling. This is only under driver's control after
4588 * PCH B stepping, previous chipset stepping should be
4589 * ignoring this setting.
4590 */
4591 temp = I915_READ(PCH_DREF_CONTROL);
4592 /* Always enable nonspread source */
4593 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004594
Keith Packard99eb6a02011-09-26 14:29:12 -07004595 if (has_ck505)
4596 temp |= DREF_NONSPREAD_CK505_ENABLE;
4597 else
4598 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004599
Keith Packard199e5d72011-09-22 12:01:57 -07004600 if (has_panel) {
4601 temp &= ~DREF_SSC_SOURCE_MASK;
4602 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004603
Keith Packard199e5d72011-09-22 12:01:57 -07004604 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07004605 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004606 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004607 temp |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02004608 } else
4609 temp &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004610
4611 /* Get SSC going before enabling the outputs */
4612 I915_WRITE(PCH_DREF_CONTROL, temp);
4613 POSTING_READ(PCH_DREF_CONTROL);
4614 udelay(200);
4615
Jesse Barnes13d83a62011-08-03 12:59:20 -07004616 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4617
4618 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07004619 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07004620 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004621 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004622 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004623 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07004624 else
4625 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004626 } else
4627 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4628
4629 I915_WRITE(PCH_DREF_CONTROL, temp);
4630 POSTING_READ(PCH_DREF_CONTROL);
4631 udelay(200);
4632 } else {
4633 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4634
4635 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4636
4637 /* Turn off CPU output */
4638 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4639
4640 I915_WRITE(PCH_DREF_CONTROL, temp);
4641 POSTING_READ(PCH_DREF_CONTROL);
4642 udelay(200);
4643
4644 /* Turn off the SSC source */
4645 temp &= ~DREF_SSC_SOURCE_MASK;
4646 temp |= DREF_SSC_SOURCE_DISABLE;
4647
4648 /* Turn off SSC1 */
4649 temp &= ~ DREF_SSC1_ENABLE;
4650
Jesse Barnes13d83a62011-08-03 12:59:20 -07004651 I915_WRITE(PCH_DREF_CONTROL, temp);
4652 POSTING_READ(PCH_DREF_CONTROL);
4653 udelay(200);
4654 }
4655}
4656
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004657static int ironlake_get_refclk(struct drm_crtc *crtc)
4658{
4659 struct drm_device *dev = crtc->dev;
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004662 struct intel_encoder *edp_encoder = NULL;
4663 int num_connectors = 0;
4664 bool is_lvds = false;
4665
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02004666 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004667 switch (encoder->type) {
4668 case INTEL_OUTPUT_LVDS:
4669 is_lvds = true;
4670 break;
4671 case INTEL_OUTPUT_EDP:
4672 edp_encoder = encoder;
4673 break;
4674 }
4675 num_connectors++;
4676 }
4677
4678 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4679 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4680 dev_priv->lvds_ssc_freq);
4681 return dev_priv->lvds_ssc_freq * 1000;
4682 }
4683
4684 return 120000;
4685}
4686
Paulo Zanonic8203562012-09-12 10:06:29 -03004687static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4688 struct drm_display_mode *adjusted_mode,
4689 bool dither)
4690{
4691 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693 int pipe = intel_crtc->pipe;
4694 uint32_t val;
4695
4696 val = I915_READ(PIPECONF(pipe));
4697
4698 val &= ~PIPE_BPC_MASK;
4699 switch (intel_crtc->bpp) {
4700 case 18:
4701 val |= PIPE_6BPC;
4702 break;
4703 case 24:
4704 val |= PIPE_8BPC;
4705 break;
4706 case 30:
4707 val |= PIPE_10BPC;
4708 break;
4709 case 36:
4710 val |= PIPE_12BPC;
4711 break;
4712 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03004713 /* Case prevented by intel_choose_pipe_bpp_dither. */
4714 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03004715 }
4716
4717 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4718 if (dither)
4719 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4720
4721 val &= ~PIPECONF_INTERLACE_MASK;
4722 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4723 val |= PIPECONF_INTERLACED_ILK;
4724 else
4725 val |= PIPECONF_PROGRESSIVE;
4726
4727 I915_WRITE(PIPECONF(pipe), val);
4728 POSTING_READ(PIPECONF(pipe));
4729}
4730
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03004731static void haswell_set_pipeconf(struct drm_crtc *crtc,
4732 struct drm_display_mode *adjusted_mode,
4733 bool dither)
4734{
4735 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4737 int pipe = intel_crtc->pipe;
4738 uint32_t val;
4739
4740 val = I915_READ(PIPECONF(pipe));
4741
4742 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4743 if (dither)
4744 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4745
4746 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4747 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4748 val |= PIPECONF_INTERLACED_ILK;
4749 else
4750 val |= PIPECONF_PROGRESSIVE;
4751
4752 I915_WRITE(PIPECONF(pipe), val);
4753 POSTING_READ(PIPECONF(pipe));
4754}
4755
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03004756static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4757 struct drm_display_mode *adjusted_mode,
4758 intel_clock_t *clock,
4759 bool *has_reduced_clock,
4760 intel_clock_t *reduced_clock)
4761{
4762 struct drm_device *dev = crtc->dev;
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 struct intel_encoder *intel_encoder;
4765 int refclk;
4766 const intel_limit_t *limit;
4767 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4768
4769 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4770 switch (intel_encoder->type) {
4771 case INTEL_OUTPUT_LVDS:
4772 is_lvds = true;
4773 break;
4774 case INTEL_OUTPUT_SDVO:
4775 case INTEL_OUTPUT_HDMI:
4776 is_sdvo = true;
4777 if (intel_encoder->needs_tv_clock)
4778 is_tv = true;
4779 break;
4780 case INTEL_OUTPUT_TVOUT:
4781 is_tv = true;
4782 break;
4783 }
4784 }
4785
4786 refclk = ironlake_get_refclk(crtc);
4787
4788 /*
4789 * Returns a set of divisors for the desired target clock with the given
4790 * refclk, or FALSE. The returned values represent the clock equation:
4791 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4792 */
4793 limit = intel_limit(crtc, refclk);
4794 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4795 clock);
4796 if (!ret)
4797 return false;
4798
4799 if (is_lvds && dev_priv->lvds_downclock_avail) {
4800 /*
4801 * Ensure we match the reduced clock's P to the target clock.
4802 * If the clocks don't match, we can't switch the display clock
4803 * by using the FP0/FP1. In such case we will disable the LVDS
4804 * downclock feature.
4805 */
4806 *has_reduced_clock = limit->find_pll(limit, crtc,
4807 dev_priv->lvds_downclock,
4808 refclk,
4809 clock,
4810 reduced_clock);
4811 }
4812
4813 if (is_sdvo && is_tv)
4814 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4815
4816 return true;
4817}
4818
Paulo Zanonif48d8f22012-09-20 18:36:04 -03004819static void ironlake_set_m_n(struct drm_crtc *crtc,
4820 struct drm_display_mode *mode,
4821 struct drm_display_mode *adjusted_mode)
4822{
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826 enum pipe pipe = intel_crtc->pipe;
4827 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4828 struct fdi_m_n m_n = {0};
4829 int target_clock, pixel_multiplier, lane, link_bw;
4830 bool is_dp = false, is_cpu_edp = false;
4831
4832 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4833 switch (intel_encoder->type) {
4834 case INTEL_OUTPUT_DISPLAYPORT:
4835 is_dp = true;
4836 break;
4837 case INTEL_OUTPUT_EDP:
4838 is_dp = true;
4839 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4840 is_cpu_edp = true;
4841 edp_encoder = intel_encoder;
4842 break;
4843 }
4844 }
4845
4846 /* FDI link */
4847 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4848 lane = 0;
4849 /* CPU eDP doesn't require FDI link, so just set DP M/N
4850 according to current link config */
4851 if (is_cpu_edp) {
4852 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4853 } else {
4854 /* FDI is a binary signal running at ~2.7GHz, encoding
4855 * each output octet as 10 bits. The actual frequency
4856 * is stored as a divider into a 100MHz clock, and the
4857 * mode pixel clock is stored in units of 1KHz.
4858 * Hence the bw of each lane in terms of the mode signal
4859 * is:
4860 */
4861 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4862 }
4863
4864 /* [e]DP over FDI requires target mode clock instead of link clock. */
4865 if (edp_encoder)
4866 target_clock = intel_edp_target_clock(edp_encoder, mode);
4867 else if (is_dp)
4868 target_clock = mode->clock;
4869 else
4870 target_clock = adjusted_mode->clock;
4871
4872 if (!lane) {
4873 /*
4874 * Account for spread spectrum to avoid
4875 * oversubscribing the link. Max center spread
4876 * is 2.5%; use 5% for safety's sake.
4877 */
4878 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4879 lane = bps / (link_bw * 8) + 1;
4880 }
4881
4882 intel_crtc->fdi_lanes = lane;
4883
4884 if (pixel_multiplier > 1)
4885 link_bw *= pixel_multiplier;
4886 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4887 &m_n);
4888
4889 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4890 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4891 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4892 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4893}
4894
Paulo Zanonide13a2e2012-09-20 18:36:05 -03004895static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4896 struct drm_display_mode *adjusted_mode,
4897 intel_clock_t *clock, u32 fp)
4898{
4899 struct drm_crtc *crtc = &intel_crtc->base;
4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 struct intel_encoder *intel_encoder;
4903 uint32_t dpll;
4904 int factor, pixel_multiplier, num_connectors = 0;
4905 bool is_lvds = false, is_sdvo = false, is_tv = false;
4906 bool is_dp = false, is_cpu_edp = false;
4907
4908 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4909 switch (intel_encoder->type) {
4910 case INTEL_OUTPUT_LVDS:
4911 is_lvds = true;
4912 break;
4913 case INTEL_OUTPUT_SDVO:
4914 case INTEL_OUTPUT_HDMI:
4915 is_sdvo = true;
4916 if (intel_encoder->needs_tv_clock)
4917 is_tv = true;
4918 break;
4919 case INTEL_OUTPUT_TVOUT:
4920 is_tv = true;
4921 break;
4922 case INTEL_OUTPUT_DISPLAYPORT:
4923 is_dp = true;
4924 break;
4925 case INTEL_OUTPUT_EDP:
4926 is_dp = true;
4927 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4928 is_cpu_edp = true;
4929 break;
4930 }
4931
4932 num_connectors++;
4933 }
4934
4935 /* Enable autotuning of the PLL clock (if permissible) */
4936 factor = 21;
4937 if (is_lvds) {
4938 if ((intel_panel_use_ssc(dev_priv) &&
4939 dev_priv->lvds_ssc_freq == 100) ||
4940 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4941 factor = 25;
4942 } else if (is_sdvo && is_tv)
4943 factor = 20;
4944
4945 if (clock->m < factor * clock->n)
4946 fp |= FP_CB_TUNE;
4947
4948 dpll = 0;
4949
4950 if (is_lvds)
4951 dpll |= DPLLB_MODE_LVDS;
4952 else
4953 dpll |= DPLLB_MODE_DAC_SERIAL;
4954 if (is_sdvo) {
4955 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4956 if (pixel_multiplier > 1) {
4957 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4958 }
4959 dpll |= DPLL_DVO_HIGH_SPEED;
4960 }
4961 if (is_dp && !is_cpu_edp)
4962 dpll |= DPLL_DVO_HIGH_SPEED;
4963
4964 /* compute bitmask from p1 value */
4965 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4966 /* also FPA1 */
4967 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4968
4969 switch (clock->p2) {
4970 case 5:
4971 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4972 break;
4973 case 7:
4974 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4975 break;
4976 case 10:
4977 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4978 break;
4979 case 14:
4980 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4981 break;
4982 }
4983
4984 if (is_sdvo && is_tv)
4985 dpll |= PLL_REF_INPUT_TVCLKINBC;
4986 else if (is_tv)
4987 /* XXX: just matching BIOS for now */
4988 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4989 dpll |= 3;
4990 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4991 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4992 else
4993 dpll |= PLL_REF_INPUT_DREFCLK;
4994
4995 return dpll;
4996}
4997
Eric Anholtf564048e2011-03-30 13:01:02 -07004998static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4999 struct drm_display_mode *mode,
5000 struct drm_display_mode *adjusted_mode,
5001 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005002 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005003{
5004 struct drm_device *dev = crtc->dev;
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005008 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005009 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005010 intel_clock_t clock, reduced_clock;
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005011 u32 dpll, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005012 bool ok, has_reduced_clock = false;
5013 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005014 struct intel_encoder *encoder;
Eric Anholtfae14982011-03-30 13:01:09 -07005015 u32 temp;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005016 int ret;
Jesse Barnes5a354202011-06-24 12:19:22 -07005017 bool dither;
Jesse Barnes79e53942008-11-07 14:24:08 -08005018
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02005019 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005020 switch (encoder->type) {
5021 case INTEL_OUTPUT_LVDS:
5022 is_lvds = true;
5023 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005024 case INTEL_OUTPUT_DISPLAYPORT:
5025 is_dp = true;
5026 break;
5027 case INTEL_OUTPUT_EDP:
Jesse Barnese3aef172012-04-10 11:58:03 -07005028 is_dp = true;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005029 if (!intel_encoder_is_pch_edp(&encoder->base))
Jesse Barnese3aef172012-04-10 11:58:03 -07005030 is_cpu_edp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005031 break;
5032 }
5033
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005034 num_connectors++;
5035 }
5036
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005037 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5038 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5039
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005040 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5041 &has_reduced_clock, &reduced_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005042 if (!ok) {
5043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5044 return -EINVAL;
5045 }
5046
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005047 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005048 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005049
Eric Anholt8febb292011-03-30 13:01:07 -07005050 /* determine panel color depth */
Paulo Zanonicc769b62012-09-20 18:36:03 -03005051 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
Paulo Zanonic8203562012-09-12 10:06:29 -03005052 if (is_lvds && dev_priv->lvds_dither)
5053 dither = true;
Eric Anholt8febb292011-03-30 13:01:07 -07005054
Eric Anholta07d6782011-03-30 13:01:08 -07005055 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5056 if (has_reduced_clock)
5057 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5058 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08005059
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005060 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005061
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07005062 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005063 drm_mode_debug_printmodeline(mode);
5064
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005065 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5066 if (!is_cpu_edp) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005067 struct intel_pch_pll *pll;
Chris Wilson5eddb702010-09-11 13:48:45 +01005068
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005069 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5070 if (pll == NULL) {
5071 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5072 pipe);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005073 return -EINVAL;
5074 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005075 } else
5076 intel_put_pch_pll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005077
5078 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5079 * This is an exception to the general rule that mode_set doesn't turn
5080 * things on.
5081 */
5082 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005083 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01005084 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Jesse Barnes7885d202012-01-12 14:51:17 -08005085 if (HAS_PCH_CPT(dev)) {
5086 temp &= ~PORT_TRANS_SEL_MASK;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005087 temp |= PORT_TRANS_SEL_CPT(pipe);
Jesse Barnes7885d202012-01-12 14:51:17 -08005088 } else {
5089 if (pipe == 1)
5090 temp |= LVDS_PIPEB_SELECT;
5091 else
5092 temp &= ~LVDS_PIPEB_SELECT;
5093 }
Jesse Barnes4b645f12011-10-12 09:51:31 -07005094
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005095 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01005096 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08005097 /* Set the B0-B3 data pairs corresponding to whether we're going to
5098 * set the DPLLs for dual-channel mode or not.
5099 */
5100 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01005101 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08005102 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005103 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08005104
5105 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5106 * appropriately here, but we need to look more thoroughly into how
5107 * panels behave in the two modes.
5108 */
Chris Wilson284d5df2012-04-14 17:41:59 +01005109 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Bryan Freedaa9b5002011-01-12 13:43:19 -08005110 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01005111 temp |= LVDS_HSYNC_POLARITY;
Bryan Freedaa9b5002011-01-12 13:43:19 -08005112 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01005113 temp |= LVDS_VSYNC_POLARITY;
Eric Anholtfae14982011-03-30 13:01:09 -07005114 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005115 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005116
Jesse Barnese3aef172012-04-10 11:58:03 -07005117 if (is_dp && !is_cpu_edp) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005118 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07005119 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005120 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005121 I915_WRITE(TRANSDATA_M1(pipe), 0);
5122 I915_WRITE(TRANSDATA_N1(pipe), 0);
5123 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5124 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005125 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005126
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005127 if (intel_crtc->pch_pll) {
5128 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005129
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005130 /* Wait for the clocks to stabilize. */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005131 POSTING_READ(intel_crtc->pch_pll->pll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005132 udelay(150);
5133
Eric Anholt8febb292011-03-30 13:01:07 -07005134 /* The pixel multiplier can only be updated once the
5135 * DPLL is enabled and the clocks are stable.
5136 *
5137 * So write it again.
5138 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005139 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005140 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005141
Chris Wilson5eddb702010-09-11 13:48:45 +01005142 intel_crtc->lowfreq_avail = false;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005143 if (intel_crtc->pch_pll) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07005144 if (is_lvds && has_reduced_clock && i915_powersave) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005145 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005146 intel_crtc->lowfreq_avail = true;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005147 } else {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005148 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005149 }
5150 }
5151
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005152 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005153
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005154 ironlake_set_m_n(crtc, mode, adjusted_mode);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005155
Jesse Barnese3aef172012-04-10 11:58:03 -07005156 if (is_cpu_edp)
Eric Anholt8febb292011-03-30 13:01:07 -07005157 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005158
Paulo Zanonic8203562012-09-12 10:06:29 -03005159 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
Jesse Barnes79e53942008-11-07 14:24:08 -08005160
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005161 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005162
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005163 /* Set up the display plane register */
5164 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005165 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005166
Daniel Vetter94352cf2012-07-05 22:51:56 +02005167 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005168
5169 intel_update_watermarks(dev);
5170
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03005171 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5172
Chris Wilson1f803ee2009-06-06 09:45:59 +01005173 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005174}
5175
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005176static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5177 struct drm_display_mode *mode,
5178 struct drm_display_mode *adjusted_mode,
5179 int x, int y,
5180 struct drm_framebuffer *fb)
5181{
5182 struct drm_device *dev = crtc->dev;
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5185 int pipe = intel_crtc->pipe;
5186 int plane = intel_crtc->plane;
5187 int num_connectors = 0;
5188 intel_clock_t clock, reduced_clock;
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005189 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005190 bool ok, has_reduced_clock = false;
5191 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5192 struct intel_encoder *encoder;
5193 u32 temp;
5194 int ret;
5195 bool dither;
5196
5197 for_each_encoder_on_crtc(dev, crtc, encoder) {
5198 switch (encoder->type) {
5199 case INTEL_OUTPUT_LVDS:
5200 is_lvds = true;
5201 break;
5202 case INTEL_OUTPUT_DISPLAYPORT:
5203 is_dp = true;
5204 break;
5205 case INTEL_OUTPUT_EDP:
5206 is_dp = true;
5207 if (!intel_encoder_is_pch_edp(&encoder->base))
5208 is_cpu_edp = true;
5209 break;
5210 }
5211
5212 num_connectors++;
5213 }
5214
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005215 /* We are not sure yet this won't happen. */
5216 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5217 INTEL_PCH_TYPE(dev));
5218
5219 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5220 num_connectors, pipe_name(pipe));
5221
Paulo Zanoni1ce42922012-10-05 12:06:01 -03005222 WARN_ON(I915_READ(PIPECONF(pipe)) &
5223 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5224
5225 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5226
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005227 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5228 return -EINVAL;
5229
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005230 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5231 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5232 &has_reduced_clock,
5233 &reduced_clock);
5234 if (!ok) {
5235 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5236 return -EINVAL;
5237 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005238 }
5239
5240 /* Ensure that the cursor is valid for the new mode before changing... */
5241 intel_crtc_update_cursor(crtc, true);
5242
5243 /* determine panel color depth */
5244 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5245 if (is_lvds && dev_priv->lvds_dither)
5246 dither = true;
5247
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005248 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5249 drm_mode_debug_printmodeline(mode);
5250
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005251 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5252 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5253 if (has_reduced_clock)
5254 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5255 reduced_clock.m2;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005256
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005257 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5258 fp);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005259
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005260 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5261 * own on pre-Haswell/LPT generation */
5262 if (!is_cpu_edp) {
5263 struct intel_pch_pll *pll;
5264
5265 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5266 if (pll == NULL) {
5267 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5268 pipe);
5269 return -EINVAL;
5270 }
5271 } else
5272 intel_put_pch_pll(intel_crtc);
5273
5274 /* The LVDS pin pair needs to be on before the DPLLs are
5275 * enabled. This is an exception to the general rule that
5276 * mode_set doesn't turn things on.
5277 */
5278 if (is_lvds) {
5279 temp = I915_READ(PCH_LVDS);
5280 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5281 if (HAS_PCH_CPT(dev)) {
5282 temp &= ~PORT_TRANS_SEL_MASK;
5283 temp |= PORT_TRANS_SEL_CPT(pipe);
5284 } else {
5285 if (pipe == 1)
5286 temp |= LVDS_PIPEB_SELECT;
5287 else
5288 temp &= ~LVDS_PIPEB_SELECT;
5289 }
5290
5291 /* set the corresponsding LVDS_BORDER bit */
5292 temp |= dev_priv->lvds_border_bits;
5293 /* Set the B0-B3 data pairs corresponding to whether
5294 * we're going to set the DPLLs for dual-channel mode or
5295 * not.
5296 */
5297 if (clock.p2 == 7)
5298 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005299 else
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005300 temp &= ~(LVDS_B0B3_POWER_UP |
5301 LVDS_CLKB_POWER_UP);
5302
5303 /* It would be nice to set 24 vs 18-bit mode
5304 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5305 * look more thoroughly into how panels behave in the
5306 * two modes.
5307 */
5308 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5309 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5310 temp |= LVDS_HSYNC_POLARITY;
5311 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5312 temp |= LVDS_VSYNC_POLARITY;
5313 I915_WRITE(PCH_LVDS, temp);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005314 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005315 }
5316
5317 if (is_dp && !is_cpu_edp) {
5318 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5319 } else {
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005320 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5321 /* For non-DP output, clear any trans DP clock recovery
5322 * setting.*/
5323 I915_WRITE(TRANSDATA_M1(pipe), 0);
5324 I915_WRITE(TRANSDATA_N1(pipe), 0);
5325 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5326 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5327 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005328 }
5329
5330 intel_crtc->lowfreq_avail = false;
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005331 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5332 if (intel_crtc->pch_pll) {
5333 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5334
5335 /* Wait for the clocks to stabilize. */
5336 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5337 udelay(150);
5338
5339 /* The pixel multiplier can only be updated once the
5340 * DPLL is enabled and the clocks are stable.
5341 *
5342 * So write it again.
5343 */
5344 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5345 }
5346
5347 if (intel_crtc->pch_pll) {
5348 if (is_lvds && has_reduced_clock && i915_powersave) {
5349 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5350 intel_crtc->lowfreq_avail = true;
5351 } else {
5352 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5353 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005354 }
5355 }
5356
5357 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5358
Paulo Zanoni1eb8dfe2012-10-18 12:42:10 -03005359 if (!is_dp || is_cpu_edp)
5360 ironlake_set_m_n(crtc, mode, adjusted_mode);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005361
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005362 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5363 if (is_cpu_edp)
5364 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005365
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005366 haswell_set_pipeconf(crtc, adjusted_mode, dither);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005367
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005368 /* Set up the display plane register */
5369 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5370 POSTING_READ(DSPCNTR(plane));
5371
5372 ret = intel_pipe_set_base(crtc, x, y, fb);
5373
5374 intel_update_watermarks(dev);
5375
5376 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5377
5378 return ret;
5379}
5380
Eric Anholtf564048e2011-03-30 13:01:02 -07005381static int intel_crtc_mode_set(struct drm_crtc *crtc,
5382 struct drm_display_mode *mode,
5383 struct drm_display_mode *adjusted_mode,
5384 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005385 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07005386{
5387 struct drm_device *dev = crtc->dev;
5388 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07005389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5390 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005391 int ret;
5392
Eric Anholt0b701d22011-03-30 13:01:03 -07005393 drm_vblank_pre_modeset(dev, pipe);
5394
Eric Anholtf564048e2011-03-30 13:01:02 -07005395 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005396 x, y, fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005397 drm_vblank_post_modeset(dev, pipe);
5398
5399 return ret;
5400}
5401
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005402static bool intel_eld_uptodate(struct drm_connector *connector,
5403 int reg_eldv, uint32_t bits_eldv,
5404 int reg_elda, uint32_t bits_elda,
5405 int reg_edid)
5406{
5407 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5408 uint8_t *eld = connector->eld;
5409 uint32_t i;
5410
5411 i = I915_READ(reg_eldv);
5412 i &= bits_eldv;
5413
5414 if (!eld[0])
5415 return !i;
5416
5417 if (!i)
5418 return false;
5419
5420 i = I915_READ(reg_elda);
5421 i &= ~bits_elda;
5422 I915_WRITE(reg_elda, i);
5423
5424 for (i = 0; i < eld[2]; i++)
5425 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5426 return false;
5427
5428 return true;
5429}
5430
Wu Fengguange0dac652011-09-05 14:25:34 +08005431static void g4x_write_eld(struct drm_connector *connector,
5432 struct drm_crtc *crtc)
5433{
5434 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5435 uint8_t *eld = connector->eld;
5436 uint32_t eldv;
5437 uint32_t len;
5438 uint32_t i;
5439
5440 i = I915_READ(G4X_AUD_VID_DID);
5441
5442 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5443 eldv = G4X_ELDV_DEVCL_DEVBLC;
5444 else
5445 eldv = G4X_ELDV_DEVCTG;
5446
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005447 if (intel_eld_uptodate(connector,
5448 G4X_AUD_CNTL_ST, eldv,
5449 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5450 G4X_HDMIW_HDMIEDID))
5451 return;
5452
Wu Fengguange0dac652011-09-05 14:25:34 +08005453 i = I915_READ(G4X_AUD_CNTL_ST);
5454 i &= ~(eldv | G4X_ELD_ADDR);
5455 len = (i >> 9) & 0x1f; /* ELD buffer size */
5456 I915_WRITE(G4X_AUD_CNTL_ST, i);
5457
5458 if (!eld[0])
5459 return;
5460
5461 len = min_t(uint8_t, eld[2], len);
5462 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5463 for (i = 0; i < len; i++)
5464 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5465
5466 i = I915_READ(G4X_AUD_CNTL_ST);
5467 i |= eldv;
5468 I915_WRITE(G4X_AUD_CNTL_ST, i);
5469}
5470
Wang Xingchao83358c852012-08-16 22:43:37 +08005471static void haswell_write_eld(struct drm_connector *connector,
5472 struct drm_crtc *crtc)
5473{
5474 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5475 uint8_t *eld = connector->eld;
5476 struct drm_device *dev = crtc->dev;
5477 uint32_t eldv;
5478 uint32_t i;
5479 int len;
5480 int pipe = to_intel_crtc(crtc)->pipe;
5481 int tmp;
5482
5483 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5484 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5485 int aud_config = HSW_AUD_CFG(pipe);
5486 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5487
5488
5489 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5490
5491 /* Audio output enable */
5492 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5493 tmp = I915_READ(aud_cntrl_st2);
5494 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5495 I915_WRITE(aud_cntrl_st2, tmp);
5496
5497 /* Wait for 1 vertical blank */
5498 intel_wait_for_vblank(dev, pipe);
5499
5500 /* Set ELD valid state */
5501 tmp = I915_READ(aud_cntrl_st2);
5502 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5503 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5504 I915_WRITE(aud_cntrl_st2, tmp);
5505 tmp = I915_READ(aud_cntrl_st2);
5506 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5507
5508 /* Enable HDMI mode */
5509 tmp = I915_READ(aud_config);
5510 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5511 /* clear N_programing_enable and N_value_index */
5512 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5513 I915_WRITE(aud_config, tmp);
5514
5515 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5516
5517 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5518
5519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5520 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5521 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5522 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5523 } else
5524 I915_WRITE(aud_config, 0);
5525
5526 if (intel_eld_uptodate(connector,
5527 aud_cntrl_st2, eldv,
5528 aud_cntl_st, IBX_ELD_ADDRESS,
5529 hdmiw_hdmiedid))
5530 return;
5531
5532 i = I915_READ(aud_cntrl_st2);
5533 i &= ~eldv;
5534 I915_WRITE(aud_cntrl_st2, i);
5535
5536 if (!eld[0])
5537 return;
5538
5539 i = I915_READ(aud_cntl_st);
5540 i &= ~IBX_ELD_ADDRESS;
5541 I915_WRITE(aud_cntl_st, i);
5542 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5543 DRM_DEBUG_DRIVER("port num:%d\n", i);
5544
5545 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5546 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5547 for (i = 0; i < len; i++)
5548 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5549
5550 i = I915_READ(aud_cntrl_st2);
5551 i |= eldv;
5552 I915_WRITE(aud_cntrl_st2, i);
5553
5554}
5555
Wu Fengguange0dac652011-09-05 14:25:34 +08005556static void ironlake_write_eld(struct drm_connector *connector,
5557 struct drm_crtc *crtc)
5558{
5559 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5560 uint8_t *eld = connector->eld;
5561 uint32_t eldv;
5562 uint32_t i;
5563 int len;
5564 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005565 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08005566 int aud_cntl_st;
5567 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08005568 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08005569
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08005570 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08005571 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5572 aud_config = IBX_AUD_CFG(pipe);
5573 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005574 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005575 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08005576 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5577 aud_config = CPT_AUD_CFG(pipe);
5578 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005579 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005580 }
5581
Wang Xingchao9b138a82012-08-09 16:52:18 +08005582 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08005583
5584 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08005585 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08005586 if (!i) {
5587 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5588 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005589 eldv = IBX_ELD_VALIDB;
5590 eldv |= IBX_ELD_VALIDB << 4;
5591 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08005592 } else {
5593 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005594 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08005595 }
5596
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005597 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5598 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5599 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06005600 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5601 } else
5602 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005603
5604 if (intel_eld_uptodate(connector,
5605 aud_cntrl_st2, eldv,
5606 aud_cntl_st, IBX_ELD_ADDRESS,
5607 hdmiw_hdmiedid))
5608 return;
5609
Wu Fengguange0dac652011-09-05 14:25:34 +08005610 i = I915_READ(aud_cntrl_st2);
5611 i &= ~eldv;
5612 I915_WRITE(aud_cntrl_st2, i);
5613
5614 if (!eld[0])
5615 return;
5616
Wu Fengguange0dac652011-09-05 14:25:34 +08005617 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005618 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08005619 I915_WRITE(aud_cntl_st, i);
5620
5621 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5622 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5623 for (i = 0; i < len; i++)
5624 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5625
5626 i = I915_READ(aud_cntrl_st2);
5627 i |= eldv;
5628 I915_WRITE(aud_cntrl_st2, i);
5629}
5630
5631void intel_write_eld(struct drm_encoder *encoder,
5632 struct drm_display_mode *mode)
5633{
5634 struct drm_crtc *crtc = encoder->crtc;
5635 struct drm_connector *connector;
5636 struct drm_device *dev = encoder->dev;
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638
5639 connector = drm_select_eld(encoder, mode);
5640 if (!connector)
5641 return;
5642
5643 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5644 connector->base.id,
5645 drm_get_connector_name(connector),
5646 connector->encoder->base.id,
5647 drm_get_encoder_name(connector->encoder));
5648
5649 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5650
5651 if (dev_priv->display.write_eld)
5652 dev_priv->display.write_eld(connector, crtc);
5653}
5654
Jesse Barnes79e53942008-11-07 14:24:08 -08005655/** Loads the palette/gamma unit for the CRTC with the prepared values */
5656void intel_crtc_load_lut(struct drm_crtc *crtc)
5657{
5658 struct drm_device *dev = crtc->dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005661 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005662 int i;
5663
5664 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00005665 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08005666 return;
5667
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005668 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005669 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005670 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005671
Jesse Barnes79e53942008-11-07 14:24:08 -08005672 for (i = 0; i < 256; i++) {
5673 I915_WRITE(palreg + 4 * i,
5674 (intel_crtc->lut_r[i] << 16) |
5675 (intel_crtc->lut_g[i] << 8) |
5676 intel_crtc->lut_b[i]);
5677 }
5678}
5679
Chris Wilson560b85b2010-08-07 11:01:38 +01005680static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5681{
5682 struct drm_device *dev = crtc->dev;
5683 struct drm_i915_private *dev_priv = dev->dev_private;
5684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5685 bool visible = base != 0;
5686 u32 cntl;
5687
5688 if (intel_crtc->cursor_visible == visible)
5689 return;
5690
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005691 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005692 if (visible) {
5693 /* On these chipsets we can only modify the base whilst
5694 * the cursor is disabled.
5695 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005696 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005697
5698 cntl &= ~(CURSOR_FORMAT_MASK);
5699 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5700 cntl |= CURSOR_ENABLE |
5701 CURSOR_GAMMA_ENABLE |
5702 CURSOR_FORMAT_ARGB;
5703 } else
5704 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005705 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005706
5707 intel_crtc->cursor_visible = visible;
5708}
5709
5710static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5711{
5712 struct drm_device *dev = crtc->dev;
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5715 int pipe = intel_crtc->pipe;
5716 bool visible = base != 0;
5717
5718 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005719 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005720 if (base) {
5721 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5722 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5723 cntl |= pipe << 28; /* Connect to correct pipe */
5724 } else {
5725 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5726 cntl |= CURSOR_MODE_DISABLE;
5727 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005728 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005729
5730 intel_crtc->cursor_visible = visible;
5731 }
5732 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005733 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005734}
5735
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005736static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5737{
5738 struct drm_device *dev = crtc->dev;
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5741 int pipe = intel_crtc->pipe;
5742 bool visible = base != 0;
5743
5744 if (intel_crtc->cursor_visible != visible) {
5745 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5746 if (base) {
5747 cntl &= ~CURSOR_MODE;
5748 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5749 } else {
5750 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5751 cntl |= CURSOR_MODE_DISABLE;
5752 }
5753 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5754
5755 intel_crtc->cursor_visible = visible;
5756 }
5757 /* and commit changes on next vblank */
5758 I915_WRITE(CURBASE_IVB(pipe), base);
5759}
5760
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005761/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005762static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5763 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005764{
5765 struct drm_device *dev = crtc->dev;
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5768 int pipe = intel_crtc->pipe;
5769 int x = intel_crtc->cursor_x;
5770 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005771 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005772 bool visible;
5773
5774 pos = 0;
5775
Chris Wilson6b383a72010-09-13 13:54:26 +01005776 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005777 base = intel_crtc->cursor_addr;
5778 if (x > (int) crtc->fb->width)
5779 base = 0;
5780
5781 if (y > (int) crtc->fb->height)
5782 base = 0;
5783 } else
5784 base = 0;
5785
5786 if (x < 0) {
5787 if (x + intel_crtc->cursor_width < 0)
5788 base = 0;
5789
5790 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5791 x = -x;
5792 }
5793 pos |= x << CURSOR_X_SHIFT;
5794
5795 if (y < 0) {
5796 if (y + intel_crtc->cursor_height < 0)
5797 base = 0;
5798
5799 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5800 y = -y;
5801 }
5802 pos |= y << CURSOR_Y_SHIFT;
5803
5804 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005805 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005806 return;
5807
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03005808 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005809 I915_WRITE(CURPOS_IVB(pipe), pos);
5810 ivb_update_cursor(crtc, base);
5811 } else {
5812 I915_WRITE(CURPOS(pipe), pos);
5813 if (IS_845G(dev) || IS_I865G(dev))
5814 i845_update_cursor(crtc, base);
5815 else
5816 i9xx_update_cursor(crtc, base);
5817 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005818}
5819
Jesse Barnes79e53942008-11-07 14:24:08 -08005820static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005821 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005822 uint32_t handle,
5823 uint32_t width, uint32_t height)
5824{
5825 struct drm_device *dev = crtc->dev;
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005828 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005829 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005830 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005831
Jesse Barnes79e53942008-11-07 14:24:08 -08005832 /* if we want to turn off the cursor ignore width and height */
5833 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005834 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005835 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005836 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005837 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005838 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005839 }
5840
5841 /* Currently we only support 64x64 cursors */
5842 if (width != 64 || height != 64) {
5843 DRM_ERROR("we currently only support 64x64 cursors\n");
5844 return -EINVAL;
5845 }
5846
Chris Wilson05394f32010-11-08 19:18:58 +00005847 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00005848 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08005849 return -ENOENT;
5850
Chris Wilson05394f32010-11-08 19:18:58 +00005851 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005852 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005853 ret = -ENOMEM;
5854 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005855 }
5856
Dave Airlie71acb5e2008-12-30 20:31:46 +10005857 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005858 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005859 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005860 if (obj->tiling_mode) {
5861 DRM_ERROR("cursor cannot be tiled\n");
5862 ret = -EINVAL;
5863 goto fail_locked;
5864 }
5865
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005866 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005867 if (ret) {
5868 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005869 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005870 }
5871
Chris Wilsond9e86c02010-11-10 16:40:20 +00005872 ret = i915_gem_object_put_fence(obj);
5873 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005874 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00005875 goto fail_unpin;
5876 }
5877
Chris Wilson05394f32010-11-08 19:18:58 +00005878 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005879 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005880 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005881 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005882 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5883 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005884 if (ret) {
5885 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005886 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005887 }
Chris Wilson05394f32010-11-08 19:18:58 +00005888 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005889 }
5890
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005891 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005892 I915_WRITE(CURSIZE, (height << 12) | width);
5893
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005894 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005895 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005896 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005897 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005898 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5899 } else
5900 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005901 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005902 }
Jesse Barnes80824002009-09-10 15:28:06 -07005903
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005904 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005905
5906 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005907 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005908 intel_crtc->cursor_width = width;
5909 intel_crtc->cursor_height = height;
5910
Chris Wilson6b383a72010-09-13 13:54:26 +01005911 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005912
Jesse Barnes79e53942008-11-07 14:24:08 -08005913 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005914fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005915 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005916fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005917 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005918fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005919 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005920 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005921}
5922
5923static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5924{
Jesse Barnes79e53942008-11-07 14:24:08 -08005925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005926
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005927 intel_crtc->cursor_x = x;
5928 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005929
Chris Wilson6b383a72010-09-13 13:54:26 +01005930 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005931
5932 return 0;
5933}
5934
5935/** Sets the color ramps on behalf of RandR */
5936void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5937 u16 blue, int regno)
5938{
5939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940
5941 intel_crtc->lut_r[regno] = red >> 8;
5942 intel_crtc->lut_g[regno] = green >> 8;
5943 intel_crtc->lut_b[regno] = blue >> 8;
5944}
5945
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005946void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5947 u16 *blue, int regno)
5948{
5949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5950
5951 *red = intel_crtc->lut_r[regno] << 8;
5952 *green = intel_crtc->lut_g[regno] << 8;
5953 *blue = intel_crtc->lut_b[regno] << 8;
5954}
5955
Jesse Barnes79e53942008-11-07 14:24:08 -08005956static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005957 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005958{
James Simmons72034252010-08-03 01:33:19 +01005959 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005961
James Simmons72034252010-08-03 01:33:19 +01005962 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005963 intel_crtc->lut_r[i] = red[i] >> 8;
5964 intel_crtc->lut_g[i] = green[i] >> 8;
5965 intel_crtc->lut_b[i] = blue[i] >> 8;
5966 }
5967
5968 intel_crtc_load_lut(crtc);
5969}
5970
5971/**
5972 * Get a pipe with a simple mode set on it for doing load-based monitor
5973 * detection.
5974 *
5975 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005976 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005977 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005978 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005979 * configured for it. In the future, it could choose to temporarily disable
5980 * some outputs to free up a pipe for its use.
5981 *
5982 * \return crtc, or NULL if no pipes are available.
5983 */
5984
5985/* VESA 640x480x72Hz mode to set on the pipe */
5986static struct drm_display_mode load_detect_mode = {
5987 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5988 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5989};
5990
Chris Wilsond2dff872011-04-19 08:36:26 +01005991static struct drm_framebuffer *
5992intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005993 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01005994 struct drm_i915_gem_object *obj)
5995{
5996 struct intel_framebuffer *intel_fb;
5997 int ret;
5998
5999 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6000 if (!intel_fb) {
6001 drm_gem_object_unreference_unlocked(&obj->base);
6002 return ERR_PTR(-ENOMEM);
6003 }
6004
6005 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6006 if (ret) {
6007 drm_gem_object_unreference_unlocked(&obj->base);
6008 kfree(intel_fb);
6009 return ERR_PTR(ret);
6010 }
6011
6012 return &intel_fb->base;
6013}
6014
6015static u32
6016intel_framebuffer_pitch_for_width(int width, int bpp)
6017{
6018 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6019 return ALIGN(pitch, 64);
6020}
6021
6022static u32
6023intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6024{
6025 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6026 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6027}
6028
6029static struct drm_framebuffer *
6030intel_framebuffer_create_for_mode(struct drm_device *dev,
6031 struct drm_display_mode *mode,
6032 int depth, int bpp)
6033{
6034 struct drm_i915_gem_object *obj;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006035 struct drm_mode_fb_cmd2 mode_cmd;
Chris Wilsond2dff872011-04-19 08:36:26 +01006036
6037 obj = i915_gem_alloc_object(dev,
6038 intel_framebuffer_size_for_mode(mode, bpp));
6039 if (obj == NULL)
6040 return ERR_PTR(-ENOMEM);
6041
6042 mode_cmd.width = mode->hdisplay;
6043 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006044 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6045 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00006046 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01006047
6048 return intel_framebuffer_create(dev, &mode_cmd, obj);
6049}
6050
6051static struct drm_framebuffer *
6052mode_fits_in_fbdev(struct drm_device *dev,
6053 struct drm_display_mode *mode)
6054{
6055 struct drm_i915_private *dev_priv = dev->dev_private;
6056 struct drm_i915_gem_object *obj;
6057 struct drm_framebuffer *fb;
6058
6059 if (dev_priv->fbdev == NULL)
6060 return NULL;
6061
6062 obj = dev_priv->fbdev->ifb.obj;
6063 if (obj == NULL)
6064 return NULL;
6065
6066 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006067 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6068 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006069 return NULL;
6070
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006071 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006072 return NULL;
6073
6074 return fb;
6075}
6076
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006077bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01006078 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006079 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006080{
6081 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006082 struct intel_encoder *intel_encoder =
6083 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08006084 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006085 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006086 struct drm_crtc *crtc = NULL;
6087 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02006088 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006089 int i = -1;
6090
Chris Wilsond2dff872011-04-19 08:36:26 +01006091 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6092 connector->base.id, drm_get_connector_name(connector),
6093 encoder->base.id, drm_get_encoder_name(encoder));
6094
Jesse Barnes79e53942008-11-07 14:24:08 -08006095 /*
6096 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006097 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006098 * - if the connector already has an assigned crtc, use it (but make
6099 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006100 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006101 * - try to find the first unused crtc that can drive this connector,
6102 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006103 */
6104
6105 /* See if we already have a CRTC for this connector */
6106 if (encoder->crtc) {
6107 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006108
Daniel Vetter24218aa2012-08-12 19:27:11 +02006109 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006110 old->load_detect_temp = false;
6111
6112 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006113 if (connector->dpms != DRM_MODE_DPMS_ON)
6114 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01006115
Chris Wilson71731882011-04-19 23:10:58 +01006116 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006117 }
6118
6119 /* Find an unused one (if possible) */
6120 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6121 i++;
6122 if (!(encoder->possible_crtcs & (1 << i)))
6123 continue;
6124 if (!possible_crtc->enabled) {
6125 crtc = possible_crtc;
6126 break;
6127 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006128 }
6129
6130 /*
6131 * If we didn't find an unused CRTC, don't use any.
6132 */
6133 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006134 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6135 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006136 }
6137
Daniel Vetterfc303102012-07-09 10:40:58 +02006138 intel_encoder->new_crtc = to_intel_crtc(crtc);
6139 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006140
6141 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006142 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006143 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006144 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006145
Chris Wilson64927112011-04-20 07:25:26 +01006146 if (!mode)
6147 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006148
Chris Wilsond2dff872011-04-19 08:36:26 +01006149 /* We need a framebuffer large enough to accommodate all accesses
6150 * that the plane may generate whilst we perform load detection.
6151 * We can not rely on the fbcon either being present (we get called
6152 * during its initialisation to detect all boot displays, or it may
6153 * not even exist) or that it is large enough to satisfy the
6154 * requested mode.
6155 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02006156 fb = mode_fits_in_fbdev(dev, mode);
6157 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006158 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006159 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6160 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01006161 } else
6162 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006163 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006164 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter24218aa2012-08-12 19:27:11 +02006165 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006166 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006167
Daniel Vetter94352cf2012-07-05 22:51:56 +02006168 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006169 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006170 if (old->release_fb)
6171 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006172 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006173 }
Chris Wilson71731882011-04-19 23:10:58 +01006174
Jesse Barnes79e53942008-11-07 14:24:08 -08006175 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006176 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006177
Chris Wilson71731882011-04-19 23:10:58 +01006178 return true;
Daniel Vetter24218aa2012-08-12 19:27:11 +02006179fail:
6180 connector->encoder = NULL;
6181 encoder->crtc = NULL;
Daniel Vetter24218aa2012-08-12 19:27:11 +02006182 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006183}
6184
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006185void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01006186 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006187{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006188 struct intel_encoder *intel_encoder =
6189 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01006190 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006191
Chris Wilsond2dff872011-04-19 08:36:26 +01006192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6193 connector->base.id, drm_get_connector_name(connector),
6194 encoder->base.id, drm_get_encoder_name(encoder));
6195
Chris Wilson8261b192011-04-19 23:18:09 +01006196 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02006197 struct drm_crtc *crtc = encoder->crtc;
6198
6199 to_intel_connector(connector)->new_encoder = NULL;
6200 intel_encoder->new_crtc = NULL;
6201 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01006202
6203 if (old->release_fb)
6204 old->release_fb->funcs->destroy(old->release_fb);
6205
Chris Wilson0622a532011-04-21 09:32:11 +01006206 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006207 }
6208
Eric Anholtc751ce42010-03-25 11:48:48 -07006209 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006210 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6211 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006212}
6213
6214/* Returns the clock of the currently programmed mode of the given pipe. */
6215static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6216{
6217 struct drm_i915_private *dev_priv = dev->dev_private;
6218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006220 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006221 u32 fp;
6222 intel_clock_t clock;
6223
6224 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006225 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006226 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006227 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006228
6229 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006230 if (IS_PINEVIEW(dev)) {
6231 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6232 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006233 } else {
6234 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6235 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6236 }
6237
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006238 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006239 if (IS_PINEVIEW(dev))
6240 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6241 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006242 else
6243 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006244 DPLL_FPA01_P1_POST_DIV_SHIFT);
6245
6246 switch (dpll & DPLL_MODE_MASK) {
6247 case DPLLB_MODE_DAC_SERIAL:
6248 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6249 5 : 10;
6250 break;
6251 case DPLLB_MODE_LVDS:
6252 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6253 7 : 14;
6254 break;
6255 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006256 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006257 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6258 return 0;
6259 }
6260
6261 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08006262 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006263 } else {
6264 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6265
6266 if (is_lvds) {
6267 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6268 DPLL_FPA01_P1_POST_DIV_SHIFT);
6269 clock.p2 = 14;
6270
6271 if ((dpll & PLL_REF_INPUT_MASK) ==
6272 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6273 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08006274 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006275 } else
Shaohua Li21778322009-02-23 15:19:16 +08006276 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006277 } else {
6278 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6279 clock.p1 = 2;
6280 else {
6281 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6282 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6283 }
6284 if (dpll & PLL_P2_DIVIDE_BY_4)
6285 clock.p2 = 4;
6286 else
6287 clock.p2 = 2;
6288
Shaohua Li21778322009-02-23 15:19:16 +08006289 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006290 }
6291 }
6292
6293 /* XXX: It would be nice to validate the clocks, but we can't reuse
6294 * i830PllIsValid() because it relies on the xf86_config connector
6295 * configuration being accurate, which it isn't necessarily.
6296 */
6297
6298 return clock.dot;
6299}
6300
6301/** Returns the currently programmed mode of the given pipe. */
6302struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6303 struct drm_crtc *crtc)
6304{
Jesse Barnes548f2452011-02-17 10:40:53 -08006305 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 int pipe = intel_crtc->pipe;
6308 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08006309 int htot = I915_READ(HTOTAL(pipe));
6310 int hsync = I915_READ(HSYNC(pipe));
6311 int vtot = I915_READ(VTOTAL(pipe));
6312 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006313
6314 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6315 if (!mode)
6316 return NULL;
6317
6318 mode->clock = intel_crtc_clock_get(dev, crtc);
6319 mode->hdisplay = (htot & 0xffff) + 1;
6320 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6321 mode->hsync_start = (hsync & 0xffff) + 1;
6322 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6323 mode->vdisplay = (vtot & 0xffff) + 1;
6324 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6325 mode->vsync_start = (vsync & 0xffff) + 1;
6326 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6327
6328 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006329
6330 return mode;
6331}
6332
Daniel Vetter3dec0092010-08-20 21:40:52 +02006333static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006334{
6335 struct drm_device *dev = crtc->dev;
6336 drm_i915_private_t *dev_priv = dev->dev_private;
6337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006339 int dpll_reg = DPLL(pipe);
6340 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006341
Eric Anholtbad720f2009-10-22 16:11:14 -07006342 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006343 return;
6344
6345 if (!dev_priv->lvds_downclock_avail)
6346 return;
6347
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006348 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006349 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006350 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006351
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006352 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006353
6354 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6355 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006356 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006357
Jesse Barnes652c3932009-08-17 13:31:43 -07006358 dpll = I915_READ(dpll_reg);
6359 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006360 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006361 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006362}
6363
6364static void intel_decrease_pllclock(struct drm_crtc *crtc)
6365{
6366 struct drm_device *dev = crtc->dev;
6367 drm_i915_private_t *dev_priv = dev->dev_private;
6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006369
Eric Anholtbad720f2009-10-22 16:11:14 -07006370 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006371 return;
6372
6373 if (!dev_priv->lvds_downclock_avail)
6374 return;
6375
6376 /*
6377 * Since this is called by a timer, we should never get here in
6378 * the manual case.
6379 */
6380 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01006381 int pipe = intel_crtc->pipe;
6382 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02006383 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01006384
Zhao Yakui44d98a62009-10-09 11:39:40 +08006385 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006386
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006387 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006388
Chris Wilson074b5e12012-05-02 12:07:06 +01006389 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006390 dpll |= DISPLAY_RATE_SELECT_FPA1;
6391 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006392 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006393 dpll = I915_READ(dpll_reg);
6394 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08006395 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006396 }
6397
6398}
6399
Chris Wilsonf047e392012-07-21 12:31:41 +01006400void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07006401{
Chris Wilsonf047e392012-07-21 12:31:41 +01006402 i915_update_gfx_val(dev->dev_private);
6403}
6404
6405void intel_mark_idle(struct drm_device *dev)
6406{
Chris Wilsonf047e392012-07-21 12:31:41 +01006407}
6408
6409void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6410{
6411 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07006412 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07006413
6414 if (!i915_powersave)
6415 return;
6416
Jesse Barnes652c3932009-08-17 13:31:43 -07006417 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006418 if (!crtc->fb)
6419 continue;
6420
Chris Wilsonf047e392012-07-21 12:31:41 +01006421 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6422 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006423 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006424}
6425
Chris Wilsonf047e392012-07-21 12:31:41 +01006426void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07006427{
Chris Wilsonf047e392012-07-21 12:31:41 +01006428 struct drm_device *dev = obj->base.dev;
6429 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07006430
Chris Wilsonf047e392012-07-21 12:31:41 +01006431 if (!i915_powersave)
Chris Wilsonacb87df2012-05-03 15:47:57 +01006432 return;
6433
Jesse Barnes652c3932009-08-17 13:31:43 -07006434 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6435 if (!crtc->fb)
6436 continue;
6437
Chris Wilsonf047e392012-07-21 12:31:41 +01006438 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6439 intel_decrease_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006440 }
6441}
6442
Jesse Barnes79e53942008-11-07 14:24:08 -08006443static void intel_crtc_destroy(struct drm_crtc *crtc)
6444{
6445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006446 struct drm_device *dev = crtc->dev;
6447 struct intel_unpin_work *work;
6448 unsigned long flags;
6449
6450 spin_lock_irqsave(&dev->event_lock, flags);
6451 work = intel_crtc->unpin_work;
6452 intel_crtc->unpin_work = NULL;
6453 spin_unlock_irqrestore(&dev->event_lock, flags);
6454
6455 if (work) {
6456 cancel_work_sync(&work->work);
6457 kfree(work);
6458 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006459
6460 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006461
Jesse Barnes79e53942008-11-07 14:24:08 -08006462 kfree(intel_crtc);
6463}
6464
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006465static void intel_unpin_work_fn(struct work_struct *__work)
6466{
6467 struct intel_unpin_work *work =
6468 container_of(__work, struct intel_unpin_work, work);
6469
6470 mutex_lock(&work->dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01006471 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00006472 drm_gem_object_unreference(&work->pending_flip_obj->base);
6473 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006474
Chris Wilson7782de32011-07-08 12:22:41 +01006475 intel_update_fbc(work->dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006476 mutex_unlock(&work->dev->struct_mutex);
6477 kfree(work);
6478}
6479
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006480static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01006481 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006482{
6483 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6485 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00006486 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006487 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006488 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006489 unsigned long flags;
6490
6491 /* Ignore early vblank irqs */
6492 if (intel_crtc == NULL)
6493 return;
6494
Mario Kleiner49b14a52010-12-09 07:00:07 +01006495 do_gettimeofday(&tnow);
6496
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006497 spin_lock_irqsave(&dev->event_lock, flags);
6498 work = intel_crtc->unpin_work;
6499 if (work == NULL || !work->pending) {
6500 spin_unlock_irqrestore(&dev->event_lock, flags);
6501 return;
6502 }
6503
6504 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006505
6506 if (work->event) {
6507 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006508 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006509
6510 /* Called before vblank count and timestamps have
6511 * been updated for the vblank interval of flip
6512 * completion? Need to increment vblank count and
6513 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01006514 * to account for this. We assume this happened if we
6515 * get called over 0.9 frame durations after the last
6516 * timestamped vblank.
6517 *
6518 * This calculation can not be used with vrefresh rates
6519 * below 5Hz (10Hz to be on the safe side) without
6520 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006521 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01006522 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6523 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006524 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006525 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6526 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006527 }
6528
Mario Kleiner49b14a52010-12-09 07:00:07 +01006529 e->event.tv_sec = tvbl.tv_sec;
6530 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006531
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006532 list_add_tail(&e->base.link,
6533 &e->base.file_priv->event_list);
6534 wake_up_interruptible(&e->base.file_priv->event_wait);
6535 }
6536
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006537 drm_vblank_put(dev, intel_crtc->pipe);
6538
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006539 spin_unlock_irqrestore(&dev->event_lock, flags);
6540
Chris Wilson05394f32010-11-08 19:18:58 +00006541 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006542
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006543 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006544 &obj->pending_flip.counter);
6545 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006546 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006547
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006548 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006549
6550 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006551}
6552
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006553void intel_finish_page_flip(struct drm_device *dev, int pipe)
6554{
6555 drm_i915_private_t *dev_priv = dev->dev_private;
6556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6557
Mario Kleiner49b14a52010-12-09 07:00:07 +01006558 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006559}
6560
6561void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6562{
6563 drm_i915_private_t *dev_priv = dev->dev_private;
6564 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6565
Mario Kleiner49b14a52010-12-09 07:00:07 +01006566 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006567}
6568
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006569void intel_prepare_page_flip(struct drm_device *dev, int plane)
6570{
6571 drm_i915_private_t *dev_priv = dev->dev_private;
6572 struct intel_crtc *intel_crtc =
6573 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6574 unsigned long flags;
6575
6576 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006577 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006578 if ((++intel_crtc->unpin_work->pending) > 1)
6579 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006580 } else {
6581 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6582 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006583 spin_unlock_irqrestore(&dev->event_lock, flags);
6584}
6585
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006586static int intel_gen2_queue_flip(struct drm_device *dev,
6587 struct drm_crtc *crtc,
6588 struct drm_framebuffer *fb,
6589 struct drm_i915_gem_object *obj)
6590{
6591 struct drm_i915_private *dev_priv = dev->dev_private;
6592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006593 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006594 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006595 int ret;
6596
Daniel Vetter6d90c952012-04-26 23:28:05 +02006597 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006598 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006599 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006600
Daniel Vetter6d90c952012-04-26 23:28:05 +02006601 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006602 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006603 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006604
6605 /* Can't queue multiple flips, so wait for the previous
6606 * one to finish before executing the next.
6607 */
6608 if (intel_crtc->plane)
6609 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6610 else
6611 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006612 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6613 intel_ring_emit(ring, MI_NOOP);
6614 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6615 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6616 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006617 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006618 intel_ring_emit(ring, 0); /* aux display base address, unused */
6619 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006620 return 0;
6621
6622err_unpin:
6623 intel_unpin_fb_obj(obj);
6624err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006625 return ret;
6626}
6627
6628static int intel_gen3_queue_flip(struct drm_device *dev,
6629 struct drm_crtc *crtc,
6630 struct drm_framebuffer *fb,
6631 struct drm_i915_gem_object *obj)
6632{
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006635 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006636 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006637 int ret;
6638
Daniel Vetter6d90c952012-04-26 23:28:05 +02006639 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006640 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006641 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006642
Daniel Vetter6d90c952012-04-26 23:28:05 +02006643 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006644 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006645 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006646
6647 if (intel_crtc->plane)
6648 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6649 else
6650 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006651 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6652 intel_ring_emit(ring, MI_NOOP);
6653 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6654 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6655 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006656 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006657 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006658
Daniel Vetter6d90c952012-04-26 23:28:05 +02006659 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006660 return 0;
6661
6662err_unpin:
6663 intel_unpin_fb_obj(obj);
6664err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006665 return ret;
6666}
6667
6668static int intel_gen4_queue_flip(struct drm_device *dev,
6669 struct drm_crtc *crtc,
6670 struct drm_framebuffer *fb,
6671 struct drm_i915_gem_object *obj)
6672{
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006676 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006677 int ret;
6678
Daniel Vetter6d90c952012-04-26 23:28:05 +02006679 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006680 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006681 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006682
Daniel Vetter6d90c952012-04-26 23:28:05 +02006683 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006684 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006685 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006686
6687 /* i965+ uses the linear or tiled offsets from the
6688 * Display Registers (which do not change across a page-flip)
6689 * so we need only reprogram the base address.
6690 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02006691 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6692 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6693 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006694 intel_ring_emit(ring,
6695 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6696 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006697
6698 /* XXX Enabling the panel-fitter across page-flip is so far
6699 * untested on non-native modes, so ignore it for now.
6700 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6701 */
6702 pf = 0;
6703 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006704 intel_ring_emit(ring, pf | pipesrc);
6705 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006706 return 0;
6707
6708err_unpin:
6709 intel_unpin_fb_obj(obj);
6710err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006711 return ret;
6712}
6713
6714static int intel_gen6_queue_flip(struct drm_device *dev,
6715 struct drm_crtc *crtc,
6716 struct drm_framebuffer *fb,
6717 struct drm_i915_gem_object *obj)
6718{
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006721 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006722 uint32_t pf, pipesrc;
6723 int ret;
6724
Daniel Vetter6d90c952012-04-26 23:28:05 +02006725 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006726 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006727 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006728
Daniel Vetter6d90c952012-04-26 23:28:05 +02006729 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006730 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006731 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006732
Daniel Vetter6d90c952012-04-26 23:28:05 +02006733 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6734 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6735 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006736 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006737
Chris Wilson99d9acd2012-04-17 20:37:00 +01006738 /* Contrary to the suggestions in the documentation,
6739 * "Enable Panel Fitter" does not seem to be required when page
6740 * flipping with a non-native mode, and worse causes a normal
6741 * modeset to fail.
6742 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6743 */
6744 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006745 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006746 intel_ring_emit(ring, pf | pipesrc);
6747 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006748 return 0;
6749
6750err_unpin:
6751 intel_unpin_fb_obj(obj);
6752err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006753 return ret;
6754}
6755
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006756/*
6757 * On gen7 we currently use the blit ring because (in early silicon at least)
6758 * the render ring doesn't give us interrpts for page flip completion, which
6759 * means clients will hang after the first flip is queued. Fortunately the
6760 * blit ring generates interrupts properly, so use it instead.
6761 */
6762static int intel_gen7_queue_flip(struct drm_device *dev,
6763 struct drm_crtc *crtc,
6764 struct drm_framebuffer *fb,
6765 struct drm_i915_gem_object *obj)
6766{
6767 struct drm_i915_private *dev_priv = dev->dev_private;
6768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6769 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006770 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006771 int ret;
6772
6773 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6774 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006775 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006776
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006777 switch(intel_crtc->plane) {
6778 case PLANE_A:
6779 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6780 break;
6781 case PLANE_B:
6782 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6783 break;
6784 case PLANE_C:
6785 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6786 break;
6787 default:
6788 WARN_ONCE(1, "unknown plane in flip command\n");
6789 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03006790 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006791 }
6792
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006793 ret = intel_ring_begin(ring, 4);
6794 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006795 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006796
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006797 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006798 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02006799 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006800 intel_ring_emit(ring, (MI_NOOP));
6801 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006802 return 0;
6803
6804err_unpin:
6805 intel_unpin_fb_obj(obj);
6806err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006807 return ret;
6808}
6809
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006810static int intel_default_queue_flip(struct drm_device *dev,
6811 struct drm_crtc *crtc,
6812 struct drm_framebuffer *fb,
6813 struct drm_i915_gem_object *obj)
6814{
6815 return -ENODEV;
6816}
6817
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006818static int intel_crtc_page_flip(struct drm_crtc *crtc,
6819 struct drm_framebuffer *fb,
6820 struct drm_pending_vblank_event *event)
6821{
6822 struct drm_device *dev = crtc->dev;
6823 struct drm_i915_private *dev_priv = dev->dev_private;
6824 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00006825 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6827 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006828 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01006829 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006830
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03006831 /* Can't change pixel format via MI display flips. */
6832 if (fb->pixel_format != crtc->fb->pixel_format)
6833 return -EINVAL;
6834
6835 /*
6836 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6837 * Note that pitch changes could also affect these register.
6838 */
6839 if (INTEL_INFO(dev)->gen > 3 &&
6840 (fb->offsets[0] != crtc->fb->offsets[0] ||
6841 fb->pitches[0] != crtc->fb->pitches[0]))
6842 return -EINVAL;
6843
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006844 work = kzalloc(sizeof *work, GFP_KERNEL);
6845 if (work == NULL)
6846 return -ENOMEM;
6847
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006848 work->event = event;
6849 work->dev = crtc->dev;
6850 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006851 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006852 INIT_WORK(&work->work, intel_unpin_work_fn);
6853
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006854 ret = drm_vblank_get(dev, intel_crtc->pipe);
6855 if (ret)
6856 goto free_work;
6857
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006858 /* We borrow the event spin lock for protecting unpin_work */
6859 spin_lock_irqsave(&dev->event_lock, flags);
6860 if (intel_crtc->unpin_work) {
6861 spin_unlock_irqrestore(&dev->event_lock, flags);
6862 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006863 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01006864
6865 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006866 return -EBUSY;
6867 }
6868 intel_crtc->unpin_work = work;
6869 spin_unlock_irqrestore(&dev->event_lock, flags);
6870
6871 intel_fb = to_intel_framebuffer(fb);
6872 obj = intel_fb->obj;
6873
Chris Wilson79158102012-05-23 11:13:58 +01006874 ret = i915_mutex_lock_interruptible(dev);
6875 if (ret)
6876 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006877
Jesse Barnes75dfca82010-02-10 15:09:44 -08006878 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00006879 drm_gem_object_reference(&work->old_fb_obj->base);
6880 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006881
6882 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01006883
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006884 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006885
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006886 work->enable_stall_check = true;
6887
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006888 /* Block clients from rendering to the new back buffer until
6889 * the flip occurs and the object is no longer visible.
6890 */
Chris Wilson05394f32010-11-08 19:18:58 +00006891 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006892
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006893 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6894 if (ret)
6895 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006896
Chris Wilson7782de32011-07-08 12:22:41 +01006897 intel_disable_fbc(dev);
Chris Wilsonf047e392012-07-21 12:31:41 +01006898 intel_mark_fb_busy(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006899 mutex_unlock(&dev->struct_mutex);
6900
Jesse Barnese5510fa2010-07-01 16:48:37 -07006901 trace_i915_flip_request(intel_crtc->plane, obj);
6902
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006903 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006904
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006905cleanup_pending:
6906 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson05394f32010-11-08 19:18:58 +00006907 drm_gem_object_unreference(&work->old_fb_obj->base);
6908 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006909 mutex_unlock(&dev->struct_mutex);
6910
Chris Wilson79158102012-05-23 11:13:58 +01006911cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01006912 spin_lock_irqsave(&dev->event_lock, flags);
6913 intel_crtc->unpin_work = NULL;
6914 spin_unlock_irqrestore(&dev->event_lock, flags);
6915
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006916 drm_vblank_put(dev, intel_crtc->pipe);
6917free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01006918 kfree(work);
6919
6920 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006921}
6922
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006923static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006924 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6925 .load_lut = intel_crtc_load_lut,
Daniel Vetter976f8a22012-07-08 22:34:21 +02006926 .disable = intel_crtc_noop,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006927};
6928
Daniel Vetter6ed0f792012-07-08 19:41:43 +02006929bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6930{
6931 struct intel_encoder *other_encoder;
6932 struct drm_crtc *crtc = &encoder->new_crtc->base;
6933
6934 if (WARN_ON(!crtc))
6935 return false;
6936
6937 list_for_each_entry(other_encoder,
6938 &crtc->dev->mode_config.encoder_list,
6939 base.head) {
6940
6941 if (&other_encoder->new_crtc->base != crtc ||
6942 encoder == other_encoder)
6943 continue;
6944 else
6945 return true;
6946 }
6947
6948 return false;
6949}
6950
Daniel Vetter50f56112012-07-02 09:35:43 +02006951static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6952 struct drm_crtc *crtc)
6953{
6954 struct drm_device *dev;
6955 struct drm_crtc *tmp;
6956 int crtc_mask = 1;
6957
6958 WARN(!crtc, "checking null crtc?\n");
6959
6960 dev = crtc->dev;
6961
6962 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6963 if (tmp == crtc)
6964 break;
6965 crtc_mask <<= 1;
6966 }
6967
6968 if (encoder->possible_crtcs & crtc_mask)
6969 return true;
6970 return false;
6971}
6972
Daniel Vetter9a935852012-07-05 22:34:27 +02006973/**
6974 * intel_modeset_update_staged_output_state
6975 *
6976 * Updates the staged output configuration state, e.g. after we've read out the
6977 * current hw state.
6978 */
6979static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6980{
6981 struct intel_encoder *encoder;
6982 struct intel_connector *connector;
6983
6984 list_for_each_entry(connector, &dev->mode_config.connector_list,
6985 base.head) {
6986 connector->new_encoder =
6987 to_intel_encoder(connector->base.encoder);
6988 }
6989
6990 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6991 base.head) {
6992 encoder->new_crtc =
6993 to_intel_crtc(encoder->base.crtc);
6994 }
6995}
6996
6997/**
6998 * intel_modeset_commit_output_state
6999 *
7000 * This function copies the stage display pipe configuration to the real one.
7001 */
7002static void intel_modeset_commit_output_state(struct drm_device *dev)
7003{
7004 struct intel_encoder *encoder;
7005 struct intel_connector *connector;
7006
7007 list_for_each_entry(connector, &dev->mode_config.connector_list,
7008 base.head) {
7009 connector->base.encoder = &connector->new_encoder->base;
7010 }
7011
7012 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7013 base.head) {
7014 encoder->base.crtc = &encoder->new_crtc->base;
7015 }
7016}
7017
Daniel Vetter7758a112012-07-08 19:40:39 +02007018static struct drm_display_mode *
7019intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7020 struct drm_display_mode *mode)
7021{
7022 struct drm_device *dev = crtc->dev;
7023 struct drm_display_mode *adjusted_mode;
7024 struct drm_encoder_helper_funcs *encoder_funcs;
7025 struct intel_encoder *encoder;
7026
7027 adjusted_mode = drm_mode_duplicate(dev, mode);
7028 if (!adjusted_mode)
7029 return ERR_PTR(-ENOMEM);
7030
7031 /* Pass our mode to the connectors and the CRTC to give them a chance to
7032 * adjust it according to limitations or connector properties, and also
7033 * a chance to reject the mode entirely.
7034 */
7035 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7036 base.head) {
7037
7038 if (&encoder->new_crtc->base != crtc)
7039 continue;
7040 encoder_funcs = encoder->base.helper_private;
7041 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7042 adjusted_mode))) {
7043 DRM_DEBUG_KMS("Encoder fixup failed\n");
7044 goto fail;
7045 }
7046 }
7047
7048 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7049 DRM_DEBUG_KMS("CRTC fixup failed\n");
7050 goto fail;
7051 }
7052 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7053
7054 return adjusted_mode;
7055fail:
7056 drm_mode_destroy(dev, adjusted_mode);
7057 return ERR_PTR(-EINVAL);
7058}
7059
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007060/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7061 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7062static void
7063intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7064 unsigned *prepare_pipes, unsigned *disable_pipes)
7065{
7066 struct intel_crtc *intel_crtc;
7067 struct drm_device *dev = crtc->dev;
7068 struct intel_encoder *encoder;
7069 struct intel_connector *connector;
7070 struct drm_crtc *tmp_crtc;
7071
7072 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7073
7074 /* Check which crtcs have changed outputs connected to them, these need
7075 * to be part of the prepare_pipes mask. We don't (yet) support global
7076 * modeset across multiple crtcs, so modeset_pipes will only have one
7077 * bit set at most. */
7078 list_for_each_entry(connector, &dev->mode_config.connector_list,
7079 base.head) {
7080 if (connector->base.encoder == &connector->new_encoder->base)
7081 continue;
7082
7083 if (connector->base.encoder) {
7084 tmp_crtc = connector->base.encoder->crtc;
7085
7086 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7087 }
7088
7089 if (connector->new_encoder)
7090 *prepare_pipes |=
7091 1 << connector->new_encoder->new_crtc->pipe;
7092 }
7093
7094 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7095 base.head) {
7096 if (encoder->base.crtc == &encoder->new_crtc->base)
7097 continue;
7098
7099 if (encoder->base.crtc) {
7100 tmp_crtc = encoder->base.crtc;
7101
7102 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7103 }
7104
7105 if (encoder->new_crtc)
7106 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7107 }
7108
7109 /* Check for any pipes that will be fully disabled ... */
7110 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7111 base.head) {
7112 bool used = false;
7113
7114 /* Don't try to disable disabled crtcs. */
7115 if (!intel_crtc->base.enabled)
7116 continue;
7117
7118 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7119 base.head) {
7120 if (encoder->new_crtc == intel_crtc)
7121 used = true;
7122 }
7123
7124 if (!used)
7125 *disable_pipes |= 1 << intel_crtc->pipe;
7126 }
7127
7128
7129 /* set_mode is also used to update properties on life display pipes. */
7130 intel_crtc = to_intel_crtc(crtc);
7131 if (crtc->enabled)
7132 *prepare_pipes |= 1 << intel_crtc->pipe;
7133
7134 /* We only support modeset on one single crtc, hence we need to do that
7135 * only for the passed in crtc iff we change anything else than just
7136 * disable crtcs.
7137 *
7138 * This is actually not true, to be fully compatible with the old crtc
7139 * helper we automatically disable _any_ output (i.e. doesn't need to be
7140 * connected to the crtc we're modesetting on) if it's disconnected.
7141 * Which is a rather nutty api (since changed the output configuration
7142 * without userspace's explicit request can lead to confusion), but
7143 * alas. Hence we currently need to modeset on all pipes we prepare. */
7144 if (*prepare_pipes)
7145 *modeset_pipes = *prepare_pipes;
7146
7147 /* ... and mask these out. */
7148 *modeset_pipes &= ~(*disable_pipes);
7149 *prepare_pipes &= ~(*disable_pipes);
7150}
7151
Daniel Vetterea9d7582012-07-10 10:42:52 +02007152static bool intel_crtc_in_use(struct drm_crtc *crtc)
7153{
7154 struct drm_encoder *encoder;
7155 struct drm_device *dev = crtc->dev;
7156
7157 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7158 if (encoder->crtc == crtc)
7159 return true;
7160
7161 return false;
7162}
7163
7164static void
7165intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7166{
7167 struct intel_encoder *intel_encoder;
7168 struct intel_crtc *intel_crtc;
7169 struct drm_connector *connector;
7170
7171 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7172 base.head) {
7173 if (!intel_encoder->base.crtc)
7174 continue;
7175
7176 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7177
7178 if (prepare_pipes & (1 << intel_crtc->pipe))
7179 intel_encoder->connectors_active = false;
7180 }
7181
7182 intel_modeset_commit_output_state(dev);
7183
7184 /* Update computed state. */
7185 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7186 base.head) {
7187 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7188 }
7189
7190 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7191 if (!connector->encoder || !connector->encoder->crtc)
7192 continue;
7193
7194 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7195
7196 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02007197 struct drm_property *dpms_property =
7198 dev->mode_config.dpms_property;
7199
Daniel Vetterea9d7582012-07-10 10:42:52 +02007200 connector->dpms = DRM_MODE_DPMS_ON;
Daniel Vetter68d34722012-09-06 22:08:35 +02007201 drm_connector_property_set_value(connector,
7202 dpms_property,
7203 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02007204
7205 intel_encoder = to_intel_encoder(connector->encoder);
7206 intel_encoder->connectors_active = true;
7207 }
7208 }
7209
7210}
7211
Daniel Vetter25c5b262012-07-08 22:08:04 +02007212#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7213 list_for_each_entry((intel_crtc), \
7214 &(dev)->mode_config.crtc_list, \
7215 base.head) \
7216 if (mask & (1 <<(intel_crtc)->pipe)) \
7217
Daniel Vetterb9805142012-08-31 17:37:33 +02007218void
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007219intel_modeset_check_state(struct drm_device *dev)
7220{
7221 struct intel_crtc *crtc;
7222 struct intel_encoder *encoder;
7223 struct intel_connector *connector;
7224
7225 list_for_each_entry(connector, &dev->mode_config.connector_list,
7226 base.head) {
7227 /* This also checks the encoder/connector hw state with the
7228 * ->get_hw_state callbacks. */
7229 intel_connector_check_state(connector);
7230
7231 WARN(&connector->new_encoder->base != connector->base.encoder,
7232 "connector's staged encoder doesn't match current encoder\n");
7233 }
7234
7235 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7236 base.head) {
7237 bool enabled = false;
7238 bool active = false;
7239 enum pipe pipe, tracked_pipe;
7240
7241 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7242 encoder->base.base.id,
7243 drm_get_encoder_name(&encoder->base));
7244
7245 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7246 "encoder's stage crtc doesn't match current crtc\n");
7247 WARN(encoder->connectors_active && !encoder->base.crtc,
7248 "encoder's active_connectors set, but no crtc\n");
7249
7250 list_for_each_entry(connector, &dev->mode_config.connector_list,
7251 base.head) {
7252 if (connector->base.encoder != &encoder->base)
7253 continue;
7254 enabled = true;
7255 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7256 active = true;
7257 }
7258 WARN(!!encoder->base.crtc != enabled,
7259 "encoder's enabled state mismatch "
7260 "(expected %i, found %i)\n",
7261 !!encoder->base.crtc, enabled);
7262 WARN(active && !encoder->base.crtc,
7263 "active encoder with no crtc\n");
7264
7265 WARN(encoder->connectors_active != active,
7266 "encoder's computed active state doesn't match tracked active state "
7267 "(expected %i, found %i)\n", active, encoder->connectors_active);
7268
7269 active = encoder->get_hw_state(encoder, &pipe);
7270 WARN(active != encoder->connectors_active,
7271 "encoder's hw state doesn't match sw tracking "
7272 "(expected %i, found %i)\n",
7273 encoder->connectors_active, active);
7274
7275 if (!encoder->base.crtc)
7276 continue;
7277
7278 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7279 WARN(active && pipe != tracked_pipe,
7280 "active encoder's pipe doesn't match"
7281 "(expected %i, found %i)\n",
7282 tracked_pipe, pipe);
7283
7284 }
7285
7286 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7287 base.head) {
7288 bool enabled = false;
7289 bool active = false;
7290
7291 DRM_DEBUG_KMS("[CRTC:%d]\n",
7292 crtc->base.base.id);
7293
7294 WARN(crtc->active && !crtc->base.enabled,
7295 "active crtc, but not enabled in sw tracking\n");
7296
7297 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7298 base.head) {
7299 if (encoder->base.crtc != &crtc->base)
7300 continue;
7301 enabled = true;
7302 if (encoder->connectors_active)
7303 active = true;
7304 }
7305 WARN(active != crtc->active,
7306 "crtc's computed active state doesn't match tracked active state "
7307 "(expected %i, found %i)\n", active, crtc->active);
7308 WARN(enabled != crtc->base.enabled,
7309 "crtc's computed enabled state doesn't match tracked enabled state "
7310 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7311
7312 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7313 }
7314}
7315
Daniel Vettera6778b32012-07-02 09:56:42 +02007316bool intel_set_mode(struct drm_crtc *crtc,
7317 struct drm_display_mode *mode,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007318 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02007319{
7320 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02007321 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vettera6778b32012-07-02 09:56:42 +02007322 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007323 struct drm_encoder_helper_funcs *encoder_funcs;
Daniel Vettera6778b32012-07-02 09:56:42 +02007324 struct drm_encoder *encoder;
Daniel Vetter25c5b262012-07-08 22:08:04 +02007325 struct intel_crtc *intel_crtc;
7326 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Daniel Vettera6778b32012-07-02 09:56:42 +02007327 bool ret = true;
7328
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007329 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02007330 &prepare_pipes, &disable_pipes);
7331
7332 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7333 modeset_pipes, prepare_pipes, disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007334
Daniel Vetter976f8a22012-07-08 22:34:21 +02007335 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7336 intel_crtc_disable(&intel_crtc->base);
7337
Daniel Vettera6778b32012-07-02 09:56:42 +02007338 saved_hwmode = crtc->hwmode;
7339 saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007340
Daniel Vetter25c5b262012-07-08 22:08:04 +02007341 /* Hack: Because we don't (yet) support global modeset on multiple
7342 * crtcs, we don't keep track of the new mode for more than one crtc.
7343 * Hence simply check whether any bit is set in modeset_pipes in all the
7344 * pieces of code that are not yet converted to deal with mutliple crtcs
7345 * changing their mode at the same time. */
7346 adjusted_mode = NULL;
7347 if (modeset_pipes) {
7348 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7349 if (IS_ERR(adjusted_mode)) {
7350 return false;
7351 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007352 }
7353
Daniel Vetterea9d7582012-07-10 10:42:52 +02007354 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7355 if (intel_crtc->base.enabled)
7356 dev_priv->display.crtc_disable(&intel_crtc->base);
7357 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007358
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02007359 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7360 * to set it here already despite that we pass it down the callchain.
7361 */
7362 if (modeset_pipes)
Daniel Vetter25c5b262012-07-08 22:08:04 +02007363 crtc->mode = *mode;
Daniel Vetter7758a112012-07-08 19:40:39 +02007364
Daniel Vetterea9d7582012-07-10 10:42:52 +02007365 /* Only after disabling all output pipelines that will be changed can we
7366 * update the the output configuration. */
7367 intel_modeset_update_state(dev, prepare_pipes);
7368
Daniel Vettera6778b32012-07-02 09:56:42 +02007369 /* Set up the DPLL and any encoders state that needs to adjust or depend
7370 * on the DPLL.
7371 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007372 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7373 ret = !intel_crtc_mode_set(&intel_crtc->base,
7374 mode, adjusted_mode,
7375 x, y, fb);
7376 if (!ret)
7377 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02007378
Daniel Vetter25c5b262012-07-08 22:08:04 +02007379 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vettera6778b32012-07-02 09:56:42 +02007380
Daniel Vetter25c5b262012-07-08 22:08:04 +02007381 if (encoder->crtc != &intel_crtc->base)
7382 continue;
Daniel Vettera6778b32012-07-02 09:56:42 +02007383
Daniel Vetter25c5b262012-07-08 22:08:04 +02007384 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7385 encoder->base.id, drm_get_encoder_name(encoder),
7386 mode->base.id, mode->name);
7387 encoder_funcs = encoder->helper_private;
7388 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7389 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007390 }
7391
7392 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007393 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7394 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02007395
Daniel Vetter25c5b262012-07-08 22:08:04 +02007396 if (modeset_pipes) {
7397 /* Store real post-adjustment hardware mode. */
7398 crtc->hwmode = *adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007399
Daniel Vetter25c5b262012-07-08 22:08:04 +02007400 /* Calculate and store various constants which
7401 * are later needed by vblank and swap-completion
7402 * timestamping. They are derived from true hwmode.
7403 */
7404 drm_calc_timestamping_constants(crtc);
7405 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007406
7407 /* FIXME: add subpixel order */
7408done:
7409 drm_mode_destroy(dev, adjusted_mode);
Daniel Vetter25c5b262012-07-08 22:08:04 +02007410 if (!ret && crtc->enabled) {
Daniel Vettera6778b32012-07-02 09:56:42 +02007411 crtc->hwmode = saved_hwmode;
7412 crtc->mode = saved_mode;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007413 } else {
7414 intel_modeset_check_state(dev);
Daniel Vettera6778b32012-07-02 09:56:42 +02007415 }
7416
7417 return ret;
7418}
7419
Daniel Vetter25c5b262012-07-08 22:08:04 +02007420#undef for_each_intel_crtc_masked
7421
Daniel Vetterd9e55602012-07-04 22:16:09 +02007422static void intel_set_config_free(struct intel_set_config *config)
7423{
7424 if (!config)
7425 return;
7426
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007427 kfree(config->save_connector_encoders);
7428 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02007429 kfree(config);
7430}
7431
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007432static int intel_set_config_save_state(struct drm_device *dev,
7433 struct intel_set_config *config)
7434{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007435 struct drm_encoder *encoder;
7436 struct drm_connector *connector;
7437 int count;
7438
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007439 config->save_encoder_crtcs =
7440 kcalloc(dev->mode_config.num_encoder,
7441 sizeof(struct drm_crtc *), GFP_KERNEL);
7442 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007443 return -ENOMEM;
7444
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007445 config->save_connector_encoders =
7446 kcalloc(dev->mode_config.num_connector,
7447 sizeof(struct drm_encoder *), GFP_KERNEL);
7448 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007449 return -ENOMEM;
7450
7451 /* Copy data. Note that driver private data is not affected.
7452 * Should anything bad happen only the expected state is
7453 * restored, not the drivers personal bookkeeping.
7454 */
7455 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007456 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007457 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007458 }
7459
7460 count = 0;
7461 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02007462 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007463 }
7464
7465 return 0;
7466}
7467
7468static void intel_set_config_restore_state(struct drm_device *dev,
7469 struct intel_set_config *config)
7470{
Daniel Vetter9a935852012-07-05 22:34:27 +02007471 struct intel_encoder *encoder;
7472 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007473 int count;
7474
7475 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02007476 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7477 encoder->new_crtc =
7478 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007479 }
7480
7481 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02007482 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7483 connector->new_encoder =
7484 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007485 }
7486}
7487
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007488static void
7489intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7490 struct intel_set_config *config)
7491{
7492
7493 /* We should be able to check here if the fb has the same properties
7494 * and then just flip_or_move it */
7495 if (set->crtc->fb != set->fb) {
7496 /* If we have no fb then treat it as a full mode set */
7497 if (set->crtc->fb == NULL) {
7498 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7499 config->mode_changed = true;
7500 } else if (set->fb == NULL) {
7501 config->mode_changed = true;
7502 } else if (set->fb->depth != set->crtc->fb->depth) {
7503 config->mode_changed = true;
7504 } else if (set->fb->bits_per_pixel !=
7505 set->crtc->fb->bits_per_pixel) {
7506 config->mode_changed = true;
7507 } else
7508 config->fb_changed = true;
7509 }
7510
Daniel Vetter835c5872012-07-10 18:11:08 +02007511 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007512 config->fb_changed = true;
7513
7514 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7515 DRM_DEBUG_KMS("modes are different, full mode set\n");
7516 drm_mode_debug_printmodeline(&set->crtc->mode);
7517 drm_mode_debug_printmodeline(set->mode);
7518 config->mode_changed = true;
7519 }
7520}
7521
Daniel Vetter2e431052012-07-04 22:42:15 +02007522static int
Daniel Vetter9a935852012-07-05 22:34:27 +02007523intel_modeset_stage_output_state(struct drm_device *dev,
7524 struct drm_mode_set *set,
7525 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02007526{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007527 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02007528 struct intel_connector *connector;
7529 struct intel_encoder *encoder;
Daniel Vetter2e431052012-07-04 22:42:15 +02007530 int count, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02007531
Daniel Vetter9a935852012-07-05 22:34:27 +02007532 /* The upper layers ensure that we either disabl a crtc or have a list
7533 * of connectors. For paranoia, double-check this. */
7534 WARN_ON(!set->fb && (set->num_connectors != 0));
7535 WARN_ON(set->fb && (set->num_connectors == 0));
7536
Daniel Vetter50f56112012-07-02 09:35:43 +02007537 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02007538 list_for_each_entry(connector, &dev->mode_config.connector_list,
7539 base.head) {
7540 /* Otherwise traverse passed in connector list and get encoders
7541 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02007542 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02007543 if (set->connectors[ro] == &connector->base) {
7544 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02007545 break;
7546 }
7547 }
7548
Daniel Vetter9a935852012-07-05 22:34:27 +02007549 /* If we disable the crtc, disable all its connectors. Also, if
7550 * the connector is on the changing crtc but not on the new
7551 * connector list, disable it. */
7552 if ((!set->fb || ro == set->num_connectors) &&
7553 connector->base.encoder &&
7554 connector->base.encoder->crtc == set->crtc) {
7555 connector->new_encoder = NULL;
7556
7557 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7558 connector->base.base.id,
7559 drm_get_connector_name(&connector->base));
7560 }
7561
7562
7563 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02007564 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007565 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02007566 }
Daniel Vetter50f56112012-07-02 09:35:43 +02007567
Daniel Vetter9a935852012-07-05 22:34:27 +02007568 /* Disable all disconnected encoders. */
7569 if (connector->base.status == connector_status_disconnected)
7570 connector->new_encoder = NULL;
7571 }
7572 /* connector->new_encoder is now updated for all connectors. */
7573
7574 /* Update crtc of enabled connectors. */
Daniel Vetter50f56112012-07-02 09:35:43 +02007575 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02007576 list_for_each_entry(connector, &dev->mode_config.connector_list,
7577 base.head) {
7578 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02007579 continue;
7580
Daniel Vetter9a935852012-07-05 22:34:27 +02007581 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02007582
7583 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02007584 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02007585 new_crtc = set->crtc;
7586 }
7587
7588 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02007589 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7590 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007591 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02007592 }
Daniel Vetter9a935852012-07-05 22:34:27 +02007593 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7594
7595 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7596 connector->base.base.id,
7597 drm_get_connector_name(&connector->base),
7598 new_crtc->base.id);
7599 }
7600
7601 /* Check for any encoders that needs to be disabled. */
7602 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7603 base.head) {
7604 list_for_each_entry(connector,
7605 &dev->mode_config.connector_list,
7606 base.head) {
7607 if (connector->new_encoder == encoder) {
7608 WARN_ON(!connector->new_encoder->new_crtc);
7609
7610 goto next_encoder;
7611 }
7612 }
7613 encoder->new_crtc = NULL;
7614next_encoder:
7615 /* Only now check for crtc changes so we don't miss encoders
7616 * that will be disabled. */
7617 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02007618 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007619 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02007620 }
7621 }
Daniel Vetter9a935852012-07-05 22:34:27 +02007622 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02007623
Daniel Vetter2e431052012-07-04 22:42:15 +02007624 return 0;
7625}
7626
7627static int intel_crtc_set_config(struct drm_mode_set *set)
7628{
7629 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02007630 struct drm_mode_set save_set;
7631 struct intel_set_config *config;
7632 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02007633
Daniel Vetter8d3e3752012-07-05 16:09:09 +02007634 BUG_ON(!set);
7635 BUG_ON(!set->crtc);
7636 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02007637
7638 if (!set->mode)
7639 set->fb = NULL;
7640
Daniel Vetter431e50f2012-07-10 17:53:42 +02007641 /* The fb helper likes to play gross jokes with ->mode_set_config.
7642 * Unfortunately the crtc helper doesn't do much at all for this case,
7643 * so we have to cope with this madness until the fb helper is fixed up. */
7644 if (set->fb && set->num_connectors == 0)
7645 return 0;
7646
Daniel Vetter2e431052012-07-04 22:42:15 +02007647 if (set->fb) {
7648 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7649 set->crtc->base.id, set->fb->base.id,
7650 (int)set->num_connectors, set->x, set->y);
7651 } else {
7652 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02007653 }
7654
7655 dev = set->crtc->dev;
7656
7657 ret = -ENOMEM;
7658 config = kzalloc(sizeof(*config), GFP_KERNEL);
7659 if (!config)
7660 goto out_config;
7661
7662 ret = intel_set_config_save_state(dev, config);
7663 if (ret)
7664 goto out_config;
7665
7666 save_set.crtc = set->crtc;
7667 save_set.mode = &set->crtc->mode;
7668 save_set.x = set->crtc->x;
7669 save_set.y = set->crtc->y;
7670 save_set.fb = set->crtc->fb;
7671
7672 /* Compute whether we need a full modeset, only an fb base update or no
7673 * change at all. In the future we might also check whether only the
7674 * mode changed, e.g. for LVDS where we only change the panel fitter in
7675 * such cases. */
7676 intel_set_config_compute_mode_changes(set, config);
7677
Daniel Vetter9a935852012-07-05 22:34:27 +02007678 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02007679 if (ret)
7680 goto fail;
7681
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007682 if (config->mode_changed) {
Daniel Vetter87f1faa2012-07-05 23:36:17 +02007683 if (set->mode) {
Daniel Vetter50f56112012-07-02 09:35:43 +02007684 DRM_DEBUG_KMS("attempting to set mode from"
7685 " userspace\n");
7686 drm_mode_debug_printmodeline(set->mode);
Daniel Vetter87f1faa2012-07-05 23:36:17 +02007687 }
7688
7689 if (!intel_set_mode(set->crtc, set->mode,
7690 set->x, set->y, set->fb)) {
7691 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7692 set->crtc->base.id);
7693 ret = -EINVAL;
7694 goto fail;
7695 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007696 } else if (config->fb_changed) {
Daniel Vetter4f660f42012-07-02 09:47:37 +02007697 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007698 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02007699 }
7700
Daniel Vetterd9e55602012-07-04 22:16:09 +02007701 intel_set_config_free(config);
7702
Daniel Vetter50f56112012-07-02 09:35:43 +02007703 return 0;
7704
7705fail:
Daniel Vetter85f9eb72012-07-04 22:24:08 +02007706 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02007707
7708 /* Try to restore the config */
Daniel Vetter5e2b5842012-07-04 22:41:29 +02007709 if (config->mode_changed &&
Daniel Vettera6778b32012-07-02 09:56:42 +02007710 !intel_set_mode(save_set.crtc, save_set.mode,
7711 save_set.x, save_set.y, save_set.fb))
Daniel Vetter50f56112012-07-02 09:35:43 +02007712 DRM_ERROR("failed to restore config after modeset failure\n");
7713
Daniel Vetterd9e55602012-07-04 22:16:09 +02007714out_config:
7715 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02007716 return ret;
7717}
7718
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007719static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007720 .cursor_set = intel_crtc_cursor_set,
7721 .cursor_move = intel_crtc_cursor_move,
7722 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02007723 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007724 .destroy = intel_crtc_destroy,
7725 .page_flip = intel_crtc_page_flip,
7726};
7727
Paulo Zanoni79f689a2012-10-05 12:05:52 -03007728static void intel_cpu_pll_init(struct drm_device *dev)
7729{
7730 if (IS_HASWELL(dev))
7731 intel_ddi_pll_init(dev);
7732}
7733
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007734static void intel_pch_pll_init(struct drm_device *dev)
7735{
7736 drm_i915_private_t *dev_priv = dev->dev_private;
7737 int i;
7738
7739 if (dev_priv->num_pch_pll == 0) {
7740 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7741 return;
7742 }
7743
7744 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7745 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7746 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7747 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7748 }
7749}
7750
Hannes Ederb358d0a2008-12-18 21:18:47 +01007751static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08007752{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007753 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007754 struct intel_crtc *intel_crtc;
7755 int i;
7756
7757 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7758 if (intel_crtc == NULL)
7759 return;
7760
7761 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7762
7763 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08007764 for (i = 0; i < 256; i++) {
7765 intel_crtc->lut_r[i] = i;
7766 intel_crtc->lut_g[i] = i;
7767 intel_crtc->lut_b[i] = i;
7768 }
7769
Jesse Barnes80824002009-09-10 15:28:06 -07007770 /* Swap pipes & planes for FBC on pre-965 */
7771 intel_crtc->pipe = pipe;
7772 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01007773 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007774 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01007775 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07007776 }
7777
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007778 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7779 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7780 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7781 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7782
Jesse Barnes5a354202011-06-24 12:19:22 -07007783 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07007784
Jesse Barnes79e53942008-11-07 14:24:08 -08007785 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08007786}
7787
Carl Worth08d7b3d2009-04-29 14:43:54 -07007788int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00007789 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07007790{
Carl Worth08d7b3d2009-04-29 14:43:54 -07007791 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02007792 struct drm_mode_object *drmmode_obj;
7793 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007794
Daniel Vetter1cff8f62012-04-24 09:55:08 +02007795 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7796 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007797
Daniel Vetterc05422d2009-08-11 16:05:30 +02007798 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7799 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07007800
Daniel Vetterc05422d2009-08-11 16:05:30 +02007801 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07007802 DRM_ERROR("no such CRTC id\n");
7803 return -EINVAL;
7804 }
7805
Daniel Vetterc05422d2009-08-11 16:05:30 +02007806 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7807 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007808
Daniel Vetterc05422d2009-08-11 16:05:30 +02007809 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007810}
7811
Daniel Vetter66a92782012-07-12 20:08:18 +02007812static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08007813{
Daniel Vetter66a92782012-07-12 20:08:18 +02007814 struct drm_device *dev = encoder->base.dev;
7815 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007816 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007817 int entry = 0;
7818
Daniel Vetter66a92782012-07-12 20:08:18 +02007819 list_for_each_entry(source_encoder,
7820 &dev->mode_config.encoder_list, base.head) {
7821
7822 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08007823 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02007824
7825 /* Intel hw has only one MUX where enocoders could be cloned. */
7826 if (encoder->cloneable && source_encoder->cloneable)
7827 index_mask |= (1 << entry);
7828
Jesse Barnes79e53942008-11-07 14:24:08 -08007829 entry++;
7830 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01007831
Jesse Barnes79e53942008-11-07 14:24:08 -08007832 return index_mask;
7833}
7834
Chris Wilson4d302442010-12-14 19:21:29 +00007835static bool has_edp_a(struct drm_device *dev)
7836{
7837 struct drm_i915_private *dev_priv = dev->dev_private;
7838
7839 if (!IS_MOBILE(dev))
7840 return false;
7841
7842 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7843 return false;
7844
7845 if (IS_GEN5(dev) &&
7846 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7847 return false;
7848
7849 return true;
7850}
7851
Jesse Barnes79e53942008-11-07 14:24:08 -08007852static void intel_setup_outputs(struct drm_device *dev)
7853{
Eric Anholt725e30a2009-01-22 13:01:02 -08007854 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007855 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007856 bool dpd_is_edp = false;
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00007857 bool has_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08007858
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00007859 has_lvds = intel_lvds_init(dev);
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007860 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7861 /* disable the panel fitter on everything but LVDS */
7862 I915_WRITE(PFIT_CONTROL, 0);
7863 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007864
Eric Anholtbad720f2009-10-22 16:11:14 -07007865 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007866 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007867
Chris Wilson4d302442010-12-14 19:21:29 +00007868 if (has_edp_a(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007869 intel_dp_init(dev, DP_A, PORT_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08007870
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007871 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007872 intel_dp_init(dev, PCH_DP_D, PORT_D);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007873 }
7874
7875 intel_crt_init(dev);
7876
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03007877 if (IS_HASWELL(dev)) {
7878 int found;
7879
7880 /* Haswell uses DDI functions to detect digital outputs */
7881 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7882 /* DDI A only supports eDP */
7883 if (found)
7884 intel_ddi_init(dev, PORT_A);
7885
7886 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7887 * register */
7888 found = I915_READ(SFUSE_STRAP);
7889
7890 if (found & SFUSE_STRAP_DDIB_DETECTED)
7891 intel_ddi_init(dev, PORT_B);
7892 if (found & SFUSE_STRAP_DDIC_DETECTED)
7893 intel_ddi_init(dev, PORT_C);
7894 if (found & SFUSE_STRAP_DDID_DETECTED)
7895 intel_ddi_init(dev, PORT_D);
7896 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007897 int found;
7898
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007899 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08007900 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01007901 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007902 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007903 intel_hdmi_init(dev, HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007904 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007905 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007906 }
7907
7908 if (I915_READ(HDMIC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007909 intel_hdmi_init(dev, HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007910
Jesse Barnesb708a1d2012-06-11 14:39:56 -04007911 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007912 intel_hdmi_init(dev, HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007913
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007914 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007915 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007916
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007917 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007918 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007919 } else if (IS_VALLEYVIEW(dev)) {
7920 int found;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007921
Gajanan Bhat19c03922012-09-27 19:13:07 +05307922 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7923 if (I915_READ(DP_C) & DP_DETECTED)
7924 intel_dp_init(dev, DP_C, PORT_C);
7925
Jesse Barnes4a87d652012-06-15 11:55:16 -07007926 if (I915_READ(SDVOB) & PORT_DETECTED) {
7927 /* SDVOB multiplex with HDMIB */
7928 found = intel_sdvo_init(dev, SDVOB, true);
7929 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007930 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007931 if (!found && (I915_READ(DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007932 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007933 }
7934
7935 if (I915_READ(SDVOC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007936 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007937
Zhenyu Wang103a1962009-11-27 11:44:36 +08007938 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08007939 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08007940
Eric Anholt725e30a2009-01-22 13:01:02 -08007941 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007942 DRM_DEBUG_KMS("probing SDVOB\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01007943 found = intel_sdvo_init(dev, SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007944 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7945 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02007946 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007947 }
Ma Ling27185ae2009-08-24 13:50:23 +08007948
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007949 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7950 DRM_DEBUG_KMS("probing DP_B\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007951 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007952 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007953 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007954
7955 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007956
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007957 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7958 DRM_DEBUG_KMS("probing SDVOC\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01007959 found = intel_sdvo_init(dev, SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007960 }
Ma Ling27185ae2009-08-24 13:50:23 +08007961
7962 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7963
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007964 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7965 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02007966 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007967 }
7968 if (SUPPORTS_INTEGRATED_DP(dev)) {
7969 DRM_DEBUG_KMS("probing DP_C\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007970 intel_dp_init(dev, DP_C, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007971 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007972 }
Ma Ling27185ae2009-08-24 13:50:23 +08007973
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007974 if (SUPPORTS_INTEGRATED_DP(dev) &&
7975 (I915_READ(DP_D) & DP_DETECTED)) {
7976 DRM_DEBUG_KMS("probing DP_D\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007977 intel_dp_init(dev, DP_D, PORT_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007978 }
Eric Anholtbad720f2009-10-22 16:11:14 -07007979 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007980 intel_dvo_init(dev);
7981
Zhenyu Wang103a1962009-11-27 11:44:36 +08007982 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007983 intel_tv_init(dev);
7984
Chris Wilson4ef69c72010-09-09 15:14:28 +01007985 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7986 encoder->base.possible_crtcs = encoder->crtc_mask;
7987 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02007988 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08007989 }
Chris Wilson47356eb2011-01-11 17:06:04 +00007990
Paulo Zanoni40579ab2012-07-03 15:57:33 -03007991 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Keith Packard9fb526d2011-09-26 22:24:57 -07007992 ironlake_init_pch_refclk(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007993}
7994
7995static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7996{
7997 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08007998
7999 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008000 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008001
8002 kfree(intel_fb);
8003}
8004
8005static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00008006 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008007 unsigned int *handle)
8008{
8009 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008010 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008011
Chris Wilson05394f32010-11-08 19:18:58 +00008012 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08008013}
8014
8015static const struct drm_framebuffer_funcs intel_fb_funcs = {
8016 .destroy = intel_user_framebuffer_destroy,
8017 .create_handle = intel_user_framebuffer_create_handle,
8018};
8019
Dave Airlie38651672010-03-30 05:34:13 +00008020int intel_framebuffer_init(struct drm_device *dev,
8021 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008022 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00008023 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08008024{
Jesse Barnes79e53942008-11-07 14:24:08 -08008025 int ret;
8026
Chris Wilson05394f32010-11-08 19:18:58 +00008027 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01008028 return -EINVAL;
8029
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008030 if (mode_cmd->pitches[0] & 63)
Chris Wilson57cd6502010-08-08 12:34:44 +01008031 return -EINVAL;
8032
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008033 switch (mode_cmd->pixel_format) {
Ville Syrjälä04b39242011-11-17 18:05:13 +02008034 case DRM_FORMAT_RGB332:
8035 case DRM_FORMAT_RGB565:
8036 case DRM_FORMAT_XRGB8888:
Jesse Barnesb250da72012-03-07 08:49:29 -08008037 case DRM_FORMAT_XBGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02008038 case DRM_FORMAT_ARGB8888:
8039 case DRM_FORMAT_XRGB2101010:
8040 case DRM_FORMAT_ARGB2101010:
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008041 /* RGB formats are common across chipsets */
Jesse Barnesb5626742011-06-24 12:19:27 -07008042 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02008043 case DRM_FORMAT_YUYV:
8044 case DRM_FORMAT_UYVY:
8045 case DRM_FORMAT_YVYU:
8046 case DRM_FORMAT_VYUY:
Chris Wilson57cd6502010-08-08 12:34:44 +01008047 break;
8048 default:
Eugeni Dodonovaca25842012-01-17 15:25:45 -02008049 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8050 mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01008051 return -EINVAL;
8052 }
8053
Jesse Barnes79e53942008-11-07 14:24:08 -08008054 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8055 if (ret) {
8056 DRM_ERROR("framebuffer init failed %d\n", ret);
8057 return ret;
8058 }
8059
8060 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08008061 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008062 return 0;
8063}
8064
Jesse Barnes79e53942008-11-07 14:24:08 -08008065static struct drm_framebuffer *
8066intel_user_framebuffer_create(struct drm_device *dev,
8067 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008068 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08008069{
Chris Wilson05394f32010-11-08 19:18:58 +00008070 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008071
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008072 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8073 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00008074 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01008075 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08008076
Chris Wilsond2dff872011-04-19 08:36:26 +01008077 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08008078}
8079
Jesse Barnes79e53942008-11-07 14:24:08 -08008080static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08008081 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00008082 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08008083};
8084
Jesse Barnese70236a2009-09-21 10:42:27 -07008085/* Set up chip specific display functions */
8086static void intel_init_display(struct drm_device *dev)
8087{
8088 struct drm_i915_private *dev_priv = dev->dev_private;
8089
8090 /* We always want a DPMS function */
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008091 if (IS_HASWELL(dev)) {
8092 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8093 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8094 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008095 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008096 dev_priv->display.update_plane = ironlake_update_plane;
8097 } else if (HAS_PCH_SPLIT(dev)) {
Eric Anholtf564048e2011-03-30 13:01:02 -07008098 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008099 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8100 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008101 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008102 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008103 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07008104 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008105 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8106 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008107 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008108 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008109 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008110
Jesse Barnese70236a2009-09-21 10:42:27 -07008111 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07008112 if (IS_VALLEYVIEW(dev))
8113 dev_priv->display.get_display_clock_speed =
8114 valleyview_get_display_clock_speed;
8115 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07008116 dev_priv->display.get_display_clock_speed =
8117 i945_get_display_clock_speed;
8118 else if (IS_I915G(dev))
8119 dev_priv->display.get_display_clock_speed =
8120 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008121 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008122 dev_priv->display.get_display_clock_speed =
8123 i9xx_misc_get_display_clock_speed;
8124 else if (IS_I915GM(dev))
8125 dev_priv->display.get_display_clock_speed =
8126 i915gm_get_display_clock_speed;
8127 else if (IS_I865G(dev))
8128 dev_priv->display.get_display_clock_speed =
8129 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02008130 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008131 dev_priv->display.get_display_clock_speed =
8132 i855_get_display_clock_speed;
8133 else /* 852, 830 */
8134 dev_priv->display.get_display_clock_speed =
8135 i830_get_display_clock_speed;
8136
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008137 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01008138 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008139 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008140 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08008141 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008142 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008143 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07008144 } else if (IS_IVYBRIDGE(dev)) {
8145 /* FIXME: detect B0+ stepping and use auto training */
8146 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008147 dev_priv->display.write_eld = ironlake_write_eld;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03008148 } else if (IS_HASWELL(dev)) {
8149 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08008150 dev_priv->display.write_eld = haswell_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008151 } else
8152 dev_priv->display.update_wm = NULL;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008153 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08008154 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07008155 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008156
8157 /* Default just returns -ENODEV to indicate unsupported */
8158 dev_priv->display.queue_flip = intel_default_queue_flip;
8159
8160 switch (INTEL_INFO(dev)->gen) {
8161 case 2:
8162 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8163 break;
8164
8165 case 3:
8166 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8167 break;
8168
8169 case 4:
8170 case 5:
8171 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8172 break;
8173
8174 case 6:
8175 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8176 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008177 case 7:
8178 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8179 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008180 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008181}
8182
Jesse Barnesb690e962010-07-19 13:53:12 -07008183/*
8184 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8185 * resume, or other times. This quirk makes sure that's the case for
8186 * affected systems.
8187 */
Akshay Joshi0206e352011-08-16 15:34:10 -04008188static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07008189{
8190 struct drm_i915_private *dev_priv = dev->dev_private;
8191
8192 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008193 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008194}
8195
Keith Packard435793d2011-07-12 14:56:22 -07008196/*
8197 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8198 */
8199static void quirk_ssc_force_disable(struct drm_device *dev)
8200{
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008203 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07008204}
8205
Carsten Emde4dca20e2012-03-15 15:56:26 +01008206/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01008207 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8208 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01008209 */
8210static void quirk_invert_brightness(struct drm_device *dev)
8211{
8212 struct drm_i915_private *dev_priv = dev->dev_private;
8213 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008214 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008215}
8216
8217struct intel_quirk {
8218 int device;
8219 int subsystem_vendor;
8220 int subsystem_device;
8221 void (*hook)(struct drm_device *dev);
8222};
8223
Ben Widawskyc43b5632012-04-16 14:07:40 -07008224static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07008225 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04008226 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07008227
Jesse Barnesb690e962010-07-19 13:53:12 -07008228 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8229 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8230
Jesse Barnesb690e962010-07-19 13:53:12 -07008231 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8232 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8233
8234 /* 855 & before need to leave pipe A & dpll A up */
8235 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8236 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02008237 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07008238
8239 /* Lenovo U160 cannot use SSC on LVDS */
8240 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02008241
8242 /* Sony Vaio Y cannot use SSC on LVDS */
8243 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01008244
8245 /* Acer Aspire 5734Z must invert backlight brightness */
8246 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07008247};
8248
8249static void intel_init_quirks(struct drm_device *dev)
8250{
8251 struct pci_dev *d = dev->pdev;
8252 int i;
8253
8254 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8255 struct intel_quirk *q = &intel_quirks[i];
8256
8257 if (d->device == q->device &&
8258 (d->subsystem_vendor == q->subsystem_vendor ||
8259 q->subsystem_vendor == PCI_ANY_ID) &&
8260 (d->subsystem_device == q->subsystem_device ||
8261 q->subsystem_device == PCI_ANY_ID))
8262 q->hook(dev);
8263 }
8264}
8265
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008266/* Disable the VGA plane that we never use */
8267static void i915_disable_vga(struct drm_device *dev)
8268{
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8270 u8 sr1;
8271 u32 vga_reg;
8272
8273 if (HAS_PCH_SPLIT(dev))
8274 vga_reg = CPU_VGACNTRL;
8275 else
8276 vga_reg = VGACNTRL;
8277
8278 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07008279 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008280 sr1 = inb(VGA_SR_DATA);
8281 outb(sr1 | 1<<5, VGA_SR_DATA);
8282 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8283 udelay(300);
8284
8285 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8286 POSTING_READ(vga_reg);
8287}
8288
Daniel Vetterf8175862012-04-10 15:50:11 +02008289void intel_modeset_init_hw(struct drm_device *dev)
8290{
Eugeni Dodonov0232e922012-07-06 15:42:36 -03008291 /* We attempt to init the necessary power wells early in the initialization
8292 * time, so the subsystems that expect power to be enabled can work.
8293 */
8294 intel_init_power_wells(dev);
8295
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03008296 intel_prepare_ddi(dev);
8297
Daniel Vetterf8175862012-04-10 15:50:11 +02008298 intel_init_clock_gating(dev);
8299
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008300 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02008301 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008302 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02008303}
8304
Jesse Barnes79e53942008-11-07 14:24:08 -08008305void intel_modeset_init(struct drm_device *dev)
8306{
Jesse Barnes652c3932009-08-17 13:31:43 -07008307 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08008308 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008309
8310 drm_mode_config_init(dev);
8311
8312 dev->mode_config.min_width = 0;
8313 dev->mode_config.min_height = 0;
8314
Dave Airlie019d96c2011-09-29 16:20:42 +01008315 dev->mode_config.preferred_depth = 24;
8316 dev->mode_config.prefer_shadow = 1;
8317
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02008318 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08008319
Jesse Barnesb690e962010-07-19 13:53:12 -07008320 intel_init_quirks(dev);
8321
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03008322 intel_init_pm(dev);
8323
Jesse Barnese70236a2009-09-21 10:42:27 -07008324 intel_init_display(dev);
8325
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008326 if (IS_GEN2(dev)) {
8327 dev->mode_config.max_width = 2048;
8328 dev->mode_config.max_height = 2048;
8329 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07008330 dev->mode_config.max_width = 4096;
8331 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08008332 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008333 dev->mode_config.max_width = 8192;
8334 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08008335 }
Daniel Vetterdd2757f2012-06-07 15:55:57 +02008336 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
Jesse Barnes79e53942008-11-07 14:24:08 -08008337
Zhao Yakui28c97732009-10-09 11:39:41 +08008338 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10008339 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08008340
Dave Airliea3524f12010-06-06 18:59:41 +10008341 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008342 intel_crtc_init(dev, i);
Jesse Barnes00c2064b2012-01-13 15:48:39 -08008343 ret = intel_plane_init(dev, i);
8344 if (ret)
8345 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08008346 }
8347
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008348 intel_cpu_pll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008349 intel_pch_pll_init(dev);
8350
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008351 /* Just disable it once at startup */
8352 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008353 intel_setup_outputs(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01008354}
8355
Daniel Vetter24929352012-07-02 20:28:59 +02008356static void
8357intel_connector_break_all_links(struct intel_connector *connector)
8358{
8359 connector->base.dpms = DRM_MODE_DPMS_OFF;
8360 connector->base.encoder = NULL;
8361 connector->encoder->connectors_active = false;
8362 connector->encoder->base.crtc = NULL;
8363}
8364
Daniel Vetter7fad7982012-07-04 17:51:47 +02008365static void intel_enable_pipe_a(struct drm_device *dev)
8366{
8367 struct intel_connector *connector;
8368 struct drm_connector *crt = NULL;
8369 struct intel_load_detect_pipe load_detect_temp;
8370
8371 /* We can't just switch on the pipe A, we need to set things up with a
8372 * proper mode and output configuration. As a gross hack, enable pipe A
8373 * by enabling the load detect pipe once. */
8374 list_for_each_entry(connector,
8375 &dev->mode_config.connector_list,
8376 base.head) {
8377 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8378 crt = &connector->base;
8379 break;
8380 }
8381 }
8382
8383 if (!crt)
8384 return;
8385
8386 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8387 intel_release_load_detect_pipe(crt, &load_detect_temp);
8388
8389
8390}
8391
Daniel Vetter24929352012-07-02 20:28:59 +02008392static void intel_sanitize_crtc(struct intel_crtc *crtc)
8393{
8394 struct drm_device *dev = crtc->base.dev;
8395 struct drm_i915_private *dev_priv = dev->dev_private;
8396 u32 reg, val;
8397
Daniel Vetter24929352012-07-02 20:28:59 +02008398 /* Clear any frame start delays used for debugging left by the BIOS */
8399 reg = PIPECONF(crtc->pipe);
8400 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8401
8402 /* We need to sanitize the plane -> pipe mapping first because this will
8403 * disable the crtc (and hence change the state) if it is wrong. */
8404 if (!HAS_PCH_SPLIT(dev)) {
8405 struct intel_connector *connector;
8406 bool plane;
8407
8408 reg = DSPCNTR(crtc->plane);
8409 val = I915_READ(reg);
8410
8411 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8412 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8413 goto ok;
8414
8415 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8416 crtc->base.base.id);
8417
8418 /* Pipe has the wrong plane attached and the plane is active.
8419 * Temporarily change the plane mapping and disable everything
8420 * ... */
8421 plane = crtc->plane;
8422 crtc->plane = !plane;
8423 dev_priv->display.crtc_disable(&crtc->base);
8424 crtc->plane = plane;
8425
8426 /* ... and break all links. */
8427 list_for_each_entry(connector, &dev->mode_config.connector_list,
8428 base.head) {
8429 if (connector->encoder->base.crtc != &crtc->base)
8430 continue;
8431
8432 intel_connector_break_all_links(connector);
8433 }
8434
8435 WARN_ON(crtc->active);
8436 crtc->base.enabled = false;
8437 }
8438ok:
8439
Daniel Vetter7fad7982012-07-04 17:51:47 +02008440 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8441 crtc->pipe == PIPE_A && !crtc->active) {
8442 /* BIOS forgot to enable pipe A, this mostly happens after
8443 * resume. Force-enable the pipe to fix this, the update_dpms
8444 * call below we restore the pipe to the right state, but leave
8445 * the required bits on. */
8446 intel_enable_pipe_a(dev);
8447 }
8448
Daniel Vetter24929352012-07-02 20:28:59 +02008449 /* Adjust the state of the output pipe according to whether we
8450 * have active connectors/encoders. */
8451 intel_crtc_update_dpms(&crtc->base);
8452
8453 if (crtc->active != crtc->base.enabled) {
8454 struct intel_encoder *encoder;
8455
8456 /* This can happen either due to bugs in the get_hw_state
8457 * functions or because the pipe is force-enabled due to the
8458 * pipe A quirk. */
8459 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8460 crtc->base.base.id,
8461 crtc->base.enabled ? "enabled" : "disabled",
8462 crtc->active ? "enabled" : "disabled");
8463
8464 crtc->base.enabled = crtc->active;
8465
8466 /* Because we only establish the connector -> encoder ->
8467 * crtc links if something is active, this means the
8468 * crtc is now deactivated. Break the links. connector
8469 * -> encoder links are only establish when things are
8470 * actually up, hence no need to break them. */
8471 WARN_ON(crtc->active);
8472
8473 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8474 WARN_ON(encoder->connectors_active);
8475 encoder->base.crtc = NULL;
8476 }
8477 }
8478}
8479
8480static void intel_sanitize_encoder(struct intel_encoder *encoder)
8481{
8482 struct intel_connector *connector;
8483 struct drm_device *dev = encoder->base.dev;
8484
8485 /* We need to check both for a crtc link (meaning that the
8486 * encoder is active and trying to read from a pipe) and the
8487 * pipe itself being active. */
8488 bool has_active_crtc = encoder->base.crtc &&
8489 to_intel_crtc(encoder->base.crtc)->active;
8490
8491 if (encoder->connectors_active && !has_active_crtc) {
8492 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8493 encoder->base.base.id,
8494 drm_get_encoder_name(&encoder->base));
8495
8496 /* Connector is active, but has no active pipe. This is
8497 * fallout from our resume register restoring. Disable
8498 * the encoder manually again. */
8499 if (encoder->base.crtc) {
8500 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8501 encoder->base.base.id,
8502 drm_get_encoder_name(&encoder->base));
8503 encoder->disable(encoder);
8504 }
8505
8506 /* Inconsistent output/port/pipe state happens presumably due to
8507 * a bug in one of the get_hw_state functions. Or someplace else
8508 * in our code, like the register restore mess on resume. Clamp
8509 * things to off as a safer default. */
8510 list_for_each_entry(connector,
8511 &dev->mode_config.connector_list,
8512 base.head) {
8513 if (connector->encoder != encoder)
8514 continue;
8515
8516 intel_connector_break_all_links(connector);
8517 }
8518 }
8519 /* Enabled encoders without active connectors will be fixed in
8520 * the crtc fixup. */
8521}
8522
8523/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8524 * and i915 state tracking structures. */
8525void intel_modeset_setup_hw_state(struct drm_device *dev)
8526{
8527 struct drm_i915_private *dev_priv = dev->dev_private;
8528 enum pipe pipe;
8529 u32 tmp;
8530 struct intel_crtc *crtc;
8531 struct intel_encoder *encoder;
8532 struct intel_connector *connector;
8533
8534 for_each_pipe(pipe) {
8535 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8536
8537 tmp = I915_READ(PIPECONF(pipe));
8538 if (tmp & PIPECONF_ENABLE)
8539 crtc->active = true;
8540 else
8541 crtc->active = false;
8542
8543 crtc->base.enabled = crtc->active;
8544
8545 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8546 crtc->base.base.id,
8547 crtc->active ? "enabled" : "disabled");
8548 }
8549
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008550 if (IS_HASWELL(dev))
8551 intel_ddi_setup_hw_pll_state(dev);
8552
Daniel Vetter24929352012-07-02 20:28:59 +02008553 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8554 base.head) {
8555 pipe = 0;
8556
8557 if (encoder->get_hw_state(encoder, &pipe)) {
8558 encoder->base.crtc =
8559 dev_priv->pipe_to_crtc_mapping[pipe];
8560 } else {
8561 encoder->base.crtc = NULL;
8562 }
8563
8564 encoder->connectors_active = false;
8565 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8566 encoder->base.base.id,
8567 drm_get_encoder_name(&encoder->base),
8568 encoder->base.crtc ? "enabled" : "disabled",
8569 pipe);
8570 }
8571
8572 list_for_each_entry(connector, &dev->mode_config.connector_list,
8573 base.head) {
8574 if (connector->get_hw_state(connector)) {
8575 connector->base.dpms = DRM_MODE_DPMS_ON;
8576 connector->encoder->connectors_active = true;
8577 connector->base.encoder = &connector->encoder->base;
8578 } else {
8579 connector->base.dpms = DRM_MODE_DPMS_OFF;
8580 connector->base.encoder = NULL;
8581 }
8582 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8583 connector->base.base.id,
8584 drm_get_connector_name(&connector->base),
8585 connector->base.encoder ? "enabled" : "disabled");
8586 }
8587
8588 /* HW state is read out, now we need to sanitize this mess. */
8589 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8590 base.head) {
8591 intel_sanitize_encoder(encoder);
8592 }
8593
8594 for_each_pipe(pipe) {
8595 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8596 intel_sanitize_crtc(crtc);
8597 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008598
8599 intel_modeset_update_staged_output_state(dev);
Daniel Vetter8af6cf82012-07-10 09:50:11 +02008600
8601 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +02008602
8603 drm_mode_config_reset(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02008604}
8605
Chris Wilson2c7111d2011-03-29 10:40:27 +01008606void intel_modeset_gem_init(struct drm_device *dev)
8607{
Chris Wilson1833b132012-05-09 11:56:28 +01008608 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02008609
8610 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02008611
8612 intel_modeset_setup_hw_state(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008613}
8614
8615void intel_modeset_cleanup(struct drm_device *dev)
8616{
Jesse Barnes652c3932009-08-17 13:31:43 -07008617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 struct drm_crtc *crtc;
8619 struct intel_crtc *intel_crtc;
8620
Keith Packardf87ea762010-10-03 19:36:26 -07008621 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07008622 mutex_lock(&dev->struct_mutex);
8623
Jesse Barnes723bfd72010-10-07 16:01:13 -07008624 intel_unregister_dsm_handler();
8625
8626
Jesse Barnes652c3932009-08-17 13:31:43 -07008627 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8628 /* Skip inactive CRTCs */
8629 if (!crtc->fb)
8630 continue;
8631
8632 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02008633 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008634 }
8635
Chris Wilson973d04f2011-07-08 12:22:37 +01008636 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07008637
Daniel Vetter8090c6b2012-06-24 16:42:32 +02008638 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00008639
Daniel Vetter930ebb42012-06-29 23:32:16 +02008640 ironlake_teardown_rc6(dev);
8641
Jesse Barnes57f350b2012-03-28 13:39:25 -07008642 if (IS_VALLEYVIEW(dev))
8643 vlv_init_dpio(dev);
8644
Kristian Høgsberg69341a52009-11-11 12:19:17 -05008645 mutex_unlock(&dev->struct_mutex);
8646
Daniel Vetter6c0d93502010-08-20 18:26:46 +02008647 /* Disable the irq before mode object teardown, for the irq might
8648 * enqueue unpin/hotplug work. */
8649 drm_irq_uninstall(dev);
8650 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02008651 cancel_work_sync(&dev_priv->rps.work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02008652
Chris Wilson1630fe72011-07-08 12:22:42 +01008653 /* flush any delayed tasks or pending work */
8654 flush_scheduled_work();
8655
Jesse Barnes79e53942008-11-07 14:24:08 -08008656 drm_mode_config_cleanup(dev);
8657}
8658
Dave Airlie28d52042009-09-21 14:33:58 +10008659/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08008660 * Return which encoder is currently attached for connector.
8661 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01008662struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08008663{
Chris Wilsondf0e9242010-09-09 16:20:55 +01008664 return &intel_attached_encoder(connector)->base;
8665}
Jesse Barnes79e53942008-11-07 14:24:08 -08008666
Chris Wilsondf0e9242010-09-09 16:20:55 +01008667void intel_connector_attach_encoder(struct intel_connector *connector,
8668 struct intel_encoder *encoder)
8669{
8670 connector->encoder = encoder;
8671 drm_mode_connector_attach_encoder(&connector->base,
8672 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008673}
Dave Airlie28d52042009-09-21 14:33:58 +10008674
8675/*
8676 * set vga decode state - true == enable VGA decode
8677 */
8678int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8679{
8680 struct drm_i915_private *dev_priv = dev->dev_private;
8681 u16 gmch_ctrl;
8682
8683 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8684 if (state)
8685 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8686 else
8687 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8688 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8689 return 0;
8690}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008691
8692#ifdef CONFIG_DEBUG_FS
8693#include <linux/seq_file.h>
8694
8695struct intel_display_error_state {
8696 struct intel_cursor_error_state {
8697 u32 control;
8698 u32 position;
8699 u32 base;
8700 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +01008701 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008702
8703 struct intel_pipe_error_state {
8704 u32 conf;
8705 u32 source;
8706
8707 u32 htotal;
8708 u32 hblank;
8709 u32 hsync;
8710 u32 vtotal;
8711 u32 vblank;
8712 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +01008713 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008714
8715 struct intel_plane_error_state {
8716 u32 control;
8717 u32 stride;
8718 u32 size;
8719 u32 pos;
8720 u32 addr;
8721 u32 surface;
8722 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +01008723 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008724};
8725
8726struct intel_display_error_state *
8727intel_display_capture_error_state(struct drm_device *dev)
8728{
Akshay Joshi0206e352011-08-16 15:34:10 -04008729 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008730 struct intel_display_error_state *error;
8731 int i;
8732
8733 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8734 if (error == NULL)
8735 return NULL;
8736
Damien Lespiau52331302012-08-15 19:23:25 +01008737 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008738 error->cursor[i].control = I915_READ(CURCNTR(i));
8739 error->cursor[i].position = I915_READ(CURPOS(i));
8740 error->cursor[i].base = I915_READ(CURBASE(i));
8741
8742 error->plane[i].control = I915_READ(DSPCNTR(i));
8743 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8744 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04008745 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008746 error->plane[i].addr = I915_READ(DSPADDR(i));
8747 if (INTEL_INFO(dev)->gen >= 4) {
8748 error->plane[i].surface = I915_READ(DSPSURF(i));
8749 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8750 }
8751
8752 error->pipe[i].conf = I915_READ(PIPECONF(i));
8753 error->pipe[i].source = I915_READ(PIPESRC(i));
8754 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8755 error->pipe[i].hblank = I915_READ(HBLANK(i));
8756 error->pipe[i].hsync = I915_READ(HSYNC(i));
8757 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8758 error->pipe[i].vblank = I915_READ(VBLANK(i));
8759 error->pipe[i].vsync = I915_READ(VSYNC(i));
8760 }
8761
8762 return error;
8763}
8764
8765void
8766intel_display_print_error_state(struct seq_file *m,
8767 struct drm_device *dev,
8768 struct intel_display_error_state *error)
8769{
Damien Lespiau52331302012-08-15 19:23:25 +01008770 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008771 int i;
8772
Damien Lespiau52331302012-08-15 19:23:25 +01008773 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8774 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008775 seq_printf(m, "Pipe [%d]:\n", i);
8776 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8777 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8778 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8779 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8780 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8781 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8782 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8783 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8784
8785 seq_printf(m, "Plane [%d]:\n", i);
8786 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8787 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8788 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8789 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8790 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8791 if (INTEL_INFO(dev)->gen >= 4) {
8792 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8793 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8794 }
8795
8796 seq_printf(m, "Cursor [%d]:\n", i);
8797 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8798 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8799 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8800 }
8801}
8802#endif