blob: 63f81416033e0e6377a7007de94415f4cb4270b8 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnes23b2f8b2011-06-28 13:04:16 -070027#include <linux/cpufreq.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100040#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080041
42#include "drm_crtc_helper.h"
43
Zhenyu Wang32f9d652009-07-24 01:00:32 +080044#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
Akshay Joshi0206e352011-08-16 15:34:10 -040046bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080047static void intel_update_watermarks(struct drm_device *dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +020048static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010049static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080050
51typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040052 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080061} intel_clock_t;
62
63typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040064 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080065} intel_range_t;
66
67typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040068 int dot_limit;
69 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080070} intel_p2_t;
71
72#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080073typedef struct intel_limit intel_limit_t;
74struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040075 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080079};
Jesse Barnes79e53942008-11-07 14:24:08 -080080
Jesse Barnes2377b742010-07-07 14:06:43 -070081/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
Ma Lingd4906092009-03-18 20:13:27 +080084static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080090
Keith Packarda4fc5ed2009-04-07 16:16:42 -070091static bool
92intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080094static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050095intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -070097
Chris Wilson021357a2010-09-07 20:54:59 +010098static inline u32 /* units of 100MHz */
99intel_fdi_link_freq(struct drm_device *dev)
100{
Chris Wilson8b99e682010-10-13 09:59:17 +0100101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100106}
107
Keith Packarde4b36692009-06-05 19:22:17 -0700108static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800119 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700120};
121
122static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800133 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700134};
Eric Anholt273e27c2011-03-30 13:01:10 -0700135
Keith Packarde4b36692009-06-05 19:22:17 -0700136static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800147 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700148};
149
150static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800161 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700162};
163
Eric Anholt273e27c2011-03-30 13:01:10 -0700164
Keith Packarde4b36692009-06-05 19:22:17 -0700165static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800177 },
Ma Lingd4906092009-03-18 20:13:27 +0800178 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700179};
180
181static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800192 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700193};
194
195static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800206 },
Ma Lingd4906092009-03-18 20:13:27 +0800207 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700208};
209
210static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800221 },
Ma Lingd4906092009-03-18 20:13:27 +0800222 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700223};
224
225static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700235 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400236 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700237};
238
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500239static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700242 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700245 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800252 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700253};
254
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500255static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800266 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700267};
268
Eric Anholt273e27c2011-03-30 13:01:10 -0700269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800274static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800285 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700286};
287
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800288static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800313 .find_pll = intel_g4x_find_best_PLL,
314};
315
Eric Anholt273e27c2011-03-30 13:01:10 -0700316/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400325 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400339 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800342 .find_pll = intel_g4x_find_best_PLL,
343};
344
345static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700355 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400356 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800357};
358
Chris Wilson1b894b52010-12-14 20:04:54 +0000359static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800361{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800364 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000370 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000375 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800383 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800384 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800385
386 return limit;
387}
388
Ma Ling044c7c42009-03-18 20:13:23 +0800389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700399 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800400 else
401 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700402 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700405 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700407 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700409 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800410 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700411 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800412
413 return limit;
414}
415
Chris Wilson1b894b52010-12-14 20:04:54 +0000416static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800417{
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
Eric Anholtbad720f2009-10-22 16:11:14 -0700421 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000422 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800423 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800424 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500425 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500427 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800428 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500429 limit = &intel_limits_pineview_sdvo;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700437 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800438 else
Keith Packarde4b36692009-06-05 19:22:17 -0700439 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800440 }
441 return limit;
442}
443
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500444/* m1 is reserved as 0 in Pineview, n is a ring counter */
445static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800446{
Shaohua Li21778322009-02-23 15:19:16 +0800447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451}
452
453static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800457 return;
458 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463}
464
Jesse Barnes79e53942008-11-07 14:24:08 -0800465/**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100468bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800469{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800473
Chris Wilson4ef69c72010-09-09 15:14:28 +0100474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800479}
480
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800481#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800482/**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
Chris Wilson1b894b52010-12-14 20:04:54 +0000487static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800490{
Jesse Barnes79e53942008-11-07 14:24:08 -0800491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400492 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800493 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400494 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400496 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400498 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400500 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400502 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800503 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400504 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400506 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400511 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800512
513 return true;
514}
515
Ma Lingd4906092009-03-18 20:13:27 +0800516static bool
517intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
Jesse Barnes79e53942008-11-07 14:24:08 -0800520{
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800524 int err = target;
525
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800527 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
Akshay Joshi0206e352011-08-16 15:34:10 -0400546 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800547
Zhao Yakui42158662009-11-20 11:24:18 +0800548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800559 int this_err;
560
Shaohua Li21778322009-02-23 15:19:16 +0800561 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577}
578
Ma Lingd4906092009-03-18 20:13:27 +0800579static bool
580intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800593 int lvds_reg;
594
Eric Anholtc619eed2010-01-28 16:45:52 -0800595 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200613 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200615 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
Shaohua Li21778322009-02-23 15:19:16 +0800624 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800627 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000628
629 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800640 return found;
641}
Ma Lingd4906092009-03-18 20:13:27 +0800642
Zhenyu Wang2c072452009-06-05 15:38:42 +0800643static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500644intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800646{
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800649
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666}
667
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700668/* DisplayPort has only two frequencies, 162MHz and 270MHz */
669static bool
670intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672{
Chris Wilson5eddb702010-09-11 13:48:45 +0100673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700693}
694
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700695/**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800704{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700705 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800706 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700707
Chris Wilson300387c2010-09-05 20:25:43 +0100708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700724 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700728 DRM_DEBUG_KMS("vblank wait timed out\n");
729}
730
Keith Packardab7ad7f2010-10-03 00:33:06 -0700731/*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100746 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700747 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100748void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700751
Keith Packardab7ad7f2010-10-03 00:33:06 -0700752 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100753 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700754
Keith Packardab7ad7f2010-10-03 00:33:06 -0700755 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -0700758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100761 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100766 last_line = I915_READ(reg) & DSL_LINEMASK;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700767 mdelay(5);
Chris Wilson58e10eb2010-10-03 10:56:11 +0100768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800773}
774
Jesse Barnesb24e7172011-01-04 15:09:30 -0800775static const char *state_string(bool enabled)
776{
777 return enabled ? "on" : "off";
778}
779
780/* Only for pre-ILK configs */
781static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783{
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794}
795#define assert_pll_enabled(d, p) assert_pll(d, p, true)
796#define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
Jesse Barnes040484a2011-01-03 12:14:26 -0800798/* For ILK+ */
799static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801{
802 int reg;
803 u32 val;
804 bool cur_state;
805
Jesse Barnesd3ccbe82011-10-12 09:27:42 -0700806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
Jesse Barnes040484a2011-01-03 12:14:26 -0800819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825}
826#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831{
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842}
843#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848{
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859}
860#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876}
877
878static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880{
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887}
888
Jesse Barnesea0760c2011-01-04 15:09:32 -0800889static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +0200895 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -0800896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800915 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -0800916}
917
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800918static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800920{
921 int reg;
922 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800923 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -0800924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800930 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800931}
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800932#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800934
935static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936 enum plane plane)
937{
938 int reg;
939 u32 val;
940
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800945 plane_name(plane));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800946}
947
948static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 int reg, i;
952 u32 val;
953 int cur_pipe;
954
Jesse Barnes19ec1352011-02-02 12:28:02 -0800955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
957 return;
958
Jesse Barnesb24e7172011-01-04 15:09:30 -0800959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
961 reg = DSPCNTR(i);
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800968 }
969}
970
Jesse Barnes92f25842011-01-04 15:09:34 -0800971static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972{
973 u32 val;
974 bool enabled;
975
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980}
981
982static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe)
984{
985 int reg;
986 u32 val;
987 bool enabled;
988
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800992 WARN(enabled,
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
994 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -0800995}
996
Keith Packard4e634382011-08-06 10:39:45 -0700997static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -0700999{
1000 if ((val & DP_PORT_EN) == 0)
1001 return false;
1002
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 return false;
1008 } else {
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010 return false;
1011 }
1012 return true;
1013}
1014
Keith Packard1519b992011-08-06 10:35:34 -07001015static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1017{
1018 if ((val & PORT_ENABLE) == 0)
1019 return false;
1020
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 return false;
1024 } else {
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026 return false;
1027 }
1028 return true;
1029}
1030
1031static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1033{
1034 if ((val & LVDS_PORT_EN) == 0)
1035 return false;
1036
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 return false;
1040 } else {
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042 return false;
1043 }
1044 return true;
1045}
1046
1047static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1049{
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1051 return false;
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 return false;
1055 } else {
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057 return false;
1058 }
1059 return true;
1060}
1061
Jesse Barnes291906f2011-02-02 12:28:03 -08001062static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001063 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001064{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001065 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001068 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001069}
1070
1071static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1073{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001074 u32 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001075 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001076 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001077 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001078}
1079
1080static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe)
1082{
1083 int reg;
1084 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001085
Keith Packardf0575e92011-07-25 22:12:43 -07001086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001089
1090 reg = PCH_ADPA;
1091 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001092 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001093 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001094 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001095
1096 reg = PCH_LVDS;
1097 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001098 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001100 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001101
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105}
1106
Jesse Barnesb24e7172011-01-04 15:09:30 -08001107/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1111 *
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1115 *
1116 * Note! This is for pre-ILK only.
1117 */
1118static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119{
1120 int reg;
1121 u32 val;
1122
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1125
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1133
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1142 POSTING_READ(reg);
1143 udelay(150); /* wait for warmup */
1144}
1145
1146/**
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1150 *
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1152 *
1153 * Note! This is for pre-ILK only.
1154 */
1155static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156{
1157 int reg;
1158 u32 val;
1159
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 return;
1163
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1166
1167 reg = DPLL(pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1171 POSTING_READ(reg);
1172}
1173
1174/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1178 *
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1181 */
1182static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001188 if (pipe > 1)
1189 return;
1190
Jesse Barnes92f25842011-01-04 15:09:34 -08001191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1193
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1196
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1201 POSTING_READ(reg);
1202 udelay(200);
1203}
1204
1205static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
1208 int reg;
1209 u32 val;
1210
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001211 if (pipe > 1)
1212 return;
1213
Jesse Barnes92f25842011-01-04 15:09:34 -08001214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226}
1227
Jesse Barnes040484a2011-01-03 12:14:26 -08001228static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1236
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1239
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
Jesse Barnese9bcff52011-06-24 12:19:20 -07001246
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1248 /*
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1251 */
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258}
1259
1260static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg;
1264 u32 val;
1265
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1269
Jesse Barnes291906f2011-02-02 12:28:03 -08001270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1272
Jesse Barnes040484a2011-01-03 12:14:26 -08001273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279 DRM_ERROR("failed to disable transcoder\n");
1280}
1281
Jesse Barnes92f25842011-01-04 15:09:34 -08001282/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001283 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001287 *
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290 *
1291 * @pipe should be %PIPE_A or %PIPE_B.
1292 *
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1294 * returning.
1295 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001296static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001298{
1299 int reg;
1300 u32 val;
1301
1302 /*
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1305 * need the check.
1306 */
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001309 else {
1310 if (pch_port) {
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314 }
1315 /* FIXME: assert CPU port conditions for SNB+ */
1316 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001317
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001320 if (val & PIPECONF_ENABLE)
1321 return;
1322
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001324 intel_wait_for_vblank(dev_priv->dev, pipe);
1325}
1326
1327/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001328 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1331 *
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334 *
1335 * @pipe should be %PIPE_A or %PIPE_B.
1336 *
1337 * Will wait until the pipe has shut down before returning.
1338 */
1339static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 /*
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1348 */
1349 assert_planes_disabled(dev_priv, pipe);
1350
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353 return;
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001357 if ((val & PIPECONF_ENABLE) == 0)
1358 return;
1359
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362}
1363
Keith Packardd74362c2011-07-28 14:47:14 -07001364/*
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1367 */
1368static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane)
1370{
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373}
1374
Jesse Barnesb24e7172011-01-04 15:09:30 -08001375/**
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1380 *
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1382 */
1383static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1385{
1386 int reg;
1387 u32 val;
1388
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1391
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001394 if (val & DISPLAY_PLANE_ENABLE)
1395 return;
1396
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001398 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001399 intel_wait_for_vblank(dev_priv->dev, pipe);
1400}
1401
Jesse Barnesb24e7172011-01-04 15:09:30 -08001402/**
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1407 *
1408 * Disable @plane; should be an independent operation.
1409 */
1410static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419 return;
1420
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1424}
1425
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001426static void disable_pch_dp(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001427 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001428{
1429 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001432 I915_WRITE(reg, val & ~DP_PORT_EN);
Keith Packardf0575e92011-07-25 22:12:43 -07001433 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001434}
1435
1436static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1438{
1439 u32 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001440 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442 reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001443 I915_WRITE(reg, val & ~PORT_ENABLE);
Keith Packardf0575e92011-07-25 22:12:43 -07001444 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001445}
1446
1447/* Disable any ports connected to this transcoder */
1448static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 u32 reg, val;
1452
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
Keith Packardf0575e92011-07-25 22:12:43 -07001456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001459
1460 reg = PCH_ADPA;
1461 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001462 if (adpa_pipe_enabled(dev_priv, val, pipe))
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465 reg = PCH_LVDS;
1466 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001467 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470 POSTING_READ(reg);
1471 udelay(100);
1472 }
1473
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1477}
1478
Chris Wilson43a95392011-07-08 12:22:36 +01001479static void i8xx_disable_fbc(struct drm_device *dev)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 fbc_ctl;
1483
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1487 return;
1488
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1495 return;
1496 }
1497
1498 DRM_DEBUG_KMS("disabled FBC\n");
1499}
1500
Jesse Barnes80824002009-09-10 15:28:06 -07001501static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502{
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001507 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes80824002009-09-10 15:28:06 -07001508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson016b9b62011-07-08 12:22:43 +01001509 int cfb_pitch;
Jesse Barnes80824002009-09-10 15:28:06 -07001510 int plane, i;
1511 u32 fbc_ctl, fbc_ctl2;
1512
Chris Wilson016b9b62011-07-08 12:22:43 +01001513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
Jesse Barnes80824002009-09-10 15:28:06 -07001516
1517 /* FBC_CTL wants 64B units */
Chris Wilson016b9b62011-07-08 12:22:43 +01001518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
Jesse Barnes80824002009-09-10 15:28:06 -07001520
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525 /* Set it up... */
Chris Wilsonde568512011-07-08 12:22:39 +01001526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527 fbc_ctl2 |= plane;
Jesse Barnes80824002009-09-10 15:28:06 -07001528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531 /* enable it... */
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001533 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Chris Wilson016b9b62011-07-08 12:22:43 +01001535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
Jesse Barnes80824002009-09-10 15:28:06 -07001536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
Chris Wilson016b9b62011-07-08 12:22:43 +01001537 fbc_ctl |= obj->fence_reg;
Jesse Barnes80824002009-09-10 15:28:06 -07001538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
Chris Wilson016b9b62011-07-08 12:22:43 +01001540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
Jesse Barnes80824002009-09-10 15:28:06 -07001542}
1543
Adam Jacksonee5382a2010-04-23 11:17:39 -04001544static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001545{
Jesse Barnes80824002009-09-10 15:28:06 -07001546 struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549}
1550
Jesse Barnes74dff282009-09-14 15:39:40 -07001551static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001557 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes74dff282009-09-14 15:39:40 -07001558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Jesse Barnes74dff282009-09-14 15:39:40 -07001560 unsigned long stall_watermark = 200;
1561 u32 dpfc_ctl;
1562
Jesse Barnes74dff282009-09-14 15:39:40 -07001563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
Chris Wilson016b9b62011-07-08 12:22:43 +01001564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
Chris Wilsonde568512011-07-08 12:22:39 +01001565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
Jesse Barnes74dff282009-09-14 15:39:40 -07001566
Jesse Barnes74dff282009-09-14 15:39:40 -07001567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572 /* enable it... */
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
Zhao Yakui28c97732009-10-09 11:39:41 +08001575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001576}
1577
Chris Wilson43a95392011-07-08 12:22:36 +01001578static void g4x_disable_fbc(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 u32 dpfc_ctl;
1582
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Jesse Barnes74dff282009-09-14 15:39:40 -07001588
Chris Wilsonbed4a672010-09-11 10:47:47 +01001589 DRM_DEBUG_KMS("disabled FBC\n");
1590 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001591}
1592
Adam Jacksonee5382a2010-04-23 11:17:39 -04001593static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001594{
Jesse Barnes74dff282009-09-14 15:39:40 -07001595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598}
1599
Jesse Barnes4efe0702011-01-18 11:25:41 -08001600static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601{
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 blt_ecoskpd;
1604
1605 /* Make sure blitter notifies FBC of writes */
Ben Widawskyfcca7922011-04-25 11:23:07 -07001606 gen6_gt_force_wake_get(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
Ben Widawskyfcca7922011-04-25 11:23:07 -07001617 gen6_gt_force_wake_put(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001618}
1619
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001620static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621{
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001626 struct drm_i915_gem_object *obj = intel_fb->obj;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001629 unsigned long stall_watermark = 200;
1630 u32 dpfc_ctl;
1631
Chris Wilsonbed4a672010-09-11 10:47:47 +01001632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
Chris Wilson9ce9d062011-07-08 12:22:40 +01001635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
Chris Wilson016b9b62011-07-08 12:22:43 +01001637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
Chris Wilsonde568512011-07-08 12:22:39 +01001638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001639
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
Chris Wilson05394f32010-11-08 19:18:58 +00001644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001645 /* enable it... */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001647
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001648 if (IS_GEN6(dev)) {
1649 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilson016b9b62011-07-08 12:22:43 +01001650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001652 sandybridge_blit_fbc_update(dev);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001653 }
1654
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656}
1657
Chris Wilson43a95392011-07-08 12:22:36 +01001658static void ironlake_disable_fbc(struct drm_device *dev)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001659{
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 u32 dpfc_ctl;
1662
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001668
Chris Wilsonbed4a672010-09-11 10:47:47 +01001669 DRM_DEBUG_KMS("disabled FBC\n");
1670 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001671}
1672
1673static bool ironlake_fbc_enabled(struct drm_device *dev)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678}
1679
Adam Jacksonee5382a2010-04-23 11:17:39 -04001680bool intel_fbc_enabled(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.fbc_enabled)
1685 return false;
1686
1687 return dev_priv->display.fbc_enabled(dev);
1688}
1689
Chris Wilson1630fe72011-07-08 12:22:42 +01001690static void intel_fbc_work_fn(struct work_struct *__work)
1691{
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1701 * the prior work.
1702 */
Chris Wilson016b9b62011-07-08 12:22:43 +01001703 if (work->crtc->fb == work->fb) {
Chris Wilson1630fe72011-07-08 12:22:42 +01001704 dev_priv->display.enable_fbc(work->crtc,
1705 work->interval);
1706
Chris Wilson016b9b62011-07-08 12:22:43 +01001707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1710 }
1711
Chris Wilson1630fe72011-07-08 12:22:42 +01001712 dev_priv->fbc_work = NULL;
1713 }
1714 mutex_unlock(&dev->struct_mutex);
1715
1716 kfree(work);
1717}
1718
1719static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720{
1721 if (dev_priv->fbc_work == NULL)
1722 return;
1723
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1729 */
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1733
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1737 * necessary to run.
1738 */
1739 dev_priv->fbc_work = NULL;
1740}
1741
Chris Wilson43a95392011-07-08 12:22:36 +01001742static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
Adam Jacksonee5382a2010-04-23 11:17:39 -04001743{
Chris Wilson1630fe72011-07-08 12:22:42 +01001744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
Adam Jacksonee5382a2010-04-23 11:17:39 -04001747
1748 if (!dev_priv->display.enable_fbc)
1749 return;
1750
Chris Wilson1630fe72011-07-08 12:22:42 +01001751 intel_cancel_fbc_work(dev_priv);
1752
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1754 if (work == NULL) {
1755 dev_priv->display.enable_fbc(crtc, interval);
1756 return;
1757 }
1758
1759 work->crtc = crtc;
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764 dev_priv->fbc_work = work;
1765
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768 /* Delay the actual enabling to let pageflipping cease and the
Chris Wilson016b9b62011-07-08 12:22:43 +01001769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
Chris Wilson1630fe72011-07-08 12:22:42 +01001773 *
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1778 */
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
Adam Jacksonee5382a2010-04-23 11:17:39 -04001780}
1781
1782void intel_disable_fbc(struct drm_device *dev)
1783{
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785
Chris Wilson1630fe72011-07-08 12:22:42 +01001786 intel_cancel_fbc_work(dev_priv);
1787
Adam Jacksonee5382a2010-04-23 11:17:39 -04001788 if (!dev_priv->display.disable_fbc)
1789 return;
1790
1791 dev_priv->display.disable_fbc(dev);
Chris Wilson016b9b62011-07-08 12:22:43 +01001792 dev_priv->cfb_plane = -1;
Adam Jacksonee5382a2010-04-23 11:17:39 -04001793}
1794
Jesse Barnes80824002009-09-10 15:28:06 -07001795/**
1796 * intel_update_fbc - enable/disable FBC as needed
Chris Wilsonbed4a672010-09-11 10:47:47 +01001797 * @dev: the drm_device
Jesse Barnes80824002009-09-10 15:28:06 -07001798 *
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1804 * - no dual wide
1805 * - framebuffer <= 2048 in width, 1536 in height
1806 *
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1810 * stolen memory.
1811 *
1812 * We need to enable/disable FBC on a global basis.
1813 */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001814static void intel_update_fbc(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001815{
Jesse Barnes80824002009-09-10 15:28:06 -07001816 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
Jesse Barnes80824002009-09-10 15:28:06 -07001820 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001821 struct drm_i915_gem_object *obj;
Keith Packardcd0de032011-09-19 21:34:19 -07001822 int enable_fbc;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001823
1824 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001825
1826 if (!i915_powersave)
1827 return;
1828
Adam Jacksonee5382a2010-04-23 11:17:39 -04001829 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001830 return;
1831
Jesse Barnes80824002009-09-10 15:28:06 -07001832 /*
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001836 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1840 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsond2102462011-01-24 17:43:27 +00001842 if (tmp_crtc->enabled && tmp_crtc->fb) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001843 if (crtc) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846 goto out_disable;
1847 }
1848 crtc = tmp_crtc;
1849 }
Jesse Barnes9c928d12010-07-23 15:20:00 -07001850 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001851
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001855 goto out_disable;
1856 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001857
1858 intel_crtc = to_intel_crtc(crtc);
1859 fb = crtc->fb;
1860 intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001861 obj = intel_fb->obj;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001862
Keith Packardcd0de032011-09-19 21:34:19 -07001863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866 enable_fbc = 1;
1867 if (INTEL_INFO(dev)->gen <= 5)
1868 enable_fbc = 0;
1869 }
1870 if (!enable_fbc) {
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873 goto out_disable;
1874 }
Chris Wilson05394f32010-11-08 19:18:58 +00001875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001876 DRM_DEBUG_KMS("framebuffer too large, disabling "
Chris Wilson5eddb702010-09-11 13:48:45 +01001877 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001879 goto out_disable;
1880 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001883 DRM_DEBUG_KMS("mode incompatible with compression, "
Chris Wilson5eddb702010-09-11 13:48:45 +01001884 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001886 goto out_disable;
1887 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001892 goto out_disable;
1893 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001897 goto out_disable;
1898 }
Chris Wilsonde568512011-07-08 12:22:39 +01001899
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1902 */
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001907 goto out_disable;
1908 }
1909
Jason Wesselc924b932010-08-05 09:22:32 -05001910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1912 goto out_disable;
1913
Chris Wilson016b9b62011-07-08 12:22:43 +01001914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1918 */
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1922 return;
1923
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1930 *
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1939 * callback.
1940 *
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1947 */
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1950 }
1951
Chris Wilsonbed4a672010-09-11 10:47:47 +01001952 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001953 return;
1954
1955out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001956 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001959 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001960 }
Jesse Barnes80824002009-09-10 15:28:06 -07001961}
1962
Chris Wilson127bd2a2010-07-23 23:32:05 +01001963int
Chris Wilson48b956c2010-09-14 12:50:34 +01001964intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001965 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001966 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001967{
Chris Wilsonce453d82011-02-21 14:43:56 +00001968 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001969 u32 alignment;
1970 int ret;
1971
Chris Wilson05394f32010-11-08 19:18:58 +00001972 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001973 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001976 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
Chris Wilsonce453d82011-02-21 14:43:56 +00001993 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001995 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001996 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001997
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2002 */
Chris Wilson05394f32010-11-08 19:18:58 +00002003 if (obj->tiling_mode != I915_TILING_NONE) {
Chris Wilsonce453d82011-02-21 14:43:56 +00002004 ret = i915_gem_object_get_fence(obj, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002005 if (ret)
2006 goto err_unpin;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002007 }
2008
Chris Wilsonce453d82011-02-21 14:43:56 +00002009 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002010 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002011
2012err_unpin:
2013 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002014err_interruptible:
2015 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002016 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002017}
2018
Jesse Barnes17638cd2011-06-24 12:19:23 -07002019static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002021{
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002026 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002029 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002030 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002031
2032 switch (plane) {
2033 case 0:
2034 case 1:
2035 break;
2036 default:
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002043
Chris Wilson5eddb702010-09-11 13:48:45 +01002044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2049 case 8:
2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
2052 case 16:
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2055 else
2056 dspcntr |= DISPPLANE_16BPP;
2057 break;
2058 case 24:
2059 case 32:
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061 break;
2062 default:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
Jesse Barnes81255562010-08-02 12:07:50 -07002064 return -EINVAL;
2065 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002066 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002067 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002068 dspcntr |= DISPPLANE_TILED;
2069 else
2070 dspcntr &= ~DISPPLANE_TILED;
2071 }
2072
Chris Wilson5eddb702010-09-11 13:48:45 +01002073 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002074
Chris Wilson05394f32010-11-08 19:18:58 +00002075 Start = obj->gtt_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
Chris Wilson5eddb702010-09-11 13:48:45 +01002080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002081 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2085 } else
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2087 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002088
Jesse Barnes17638cd2011-06-24 12:19:23 -07002089 return 0;
2090}
2091
2092static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2102 u32 dspcntr;
2103 u32 reg;
2104
2105 switch (plane) {
2106 case 0:
2107 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002108 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002109 break;
2110 default:
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112 return -EINVAL;
2113 }
2114
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2117
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2123 case 8:
2124 dspcntr |= DISPPLANE_8BPP;
2125 break;
2126 case 16:
2127 if (fb->depth != 16)
2128 return -EINVAL;
2129
2130 dspcntr |= DISPPLANE_16BPP;
2131 break;
2132 case 24:
2133 case 32:
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138 else
2139 return -EINVAL;
2140 break;
2141 default:
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143 return -EINVAL;
2144 }
2145
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2148 else
2149 dspcntr &= ~DISPPLANE_TILED;
2150
2151 /* must disable */
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154 I915_WRITE(reg, dspcntr);
2155
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2165 POSTING_READ(reg);
2166
2167 return 0;
2168}
2169
2170/* Assume fb object is pinned & idle & fenced and just update base pointers */
2171static int
2172intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180 if (ret)
2181 return ret;
2182
Chris Wilsonbed4a672010-09-11 10:47:47 +01002183 intel_update_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002184 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002185
2186 return 0;
2187}
2188
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002189static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002190intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002192{
2193 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002194 struct drm_i915_master_private *master_priv;
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002196 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002197
2198 /* no fb bound */
2199 if (!crtc->fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002200 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002201 return 0;
2202 }
2203
Chris Wilson265db952010-09-20 15:41:01 +01002204 switch (intel_crtc->plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002205 case 0:
2206 case 1:
2207 break;
Jesse Barnes27f82272011-09-02 12:54:37 -07002208 case 2:
2209 if (IS_IVYBRIDGE(dev))
2210 break;
2211 /* fall through otherwise */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002212 default:
Jesse Barnesa5071c22011-07-19 15:38:56 -07002213 DRM_ERROR("no plane for crtc\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002214 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002215 }
2216
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002217 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002218 ret = intel_pin_and_fence_fb_obj(dev,
2219 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002220 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002221 if (ret != 0) {
2222 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002223 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002224 return ret;
2225 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002226
Chris Wilson265db952010-09-20 15:41:01 +01002227 if (old_fb) {
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002228 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00002229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
Chris Wilson265db952010-09-20 15:41:01 +01002230
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002231 wait_event(dev_priv->pending_flip_queue,
Chris Wilson01eec722011-02-11 20:47:45 +00002232 atomic_read(&dev_priv->mm.wedged) ||
Chris Wilson05394f32010-11-08 19:18:58 +00002233 atomic_read(&obj->pending_flip) == 0);
Chris Wilson85345512010-11-13 09:49:11 +00002234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
Chris Wilson01eec722011-02-11 20:47:45 +00002239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
Chris Wilson85345512010-11-13 09:49:11 +00002242 */
Chris Wilsona8198ee2011-04-13 22:04:09 +01002243 ret = i915_gem_object_finish_gpu(obj);
Chris Wilson01eec722011-02-11 20:47:45 +00002244 (void) ret;
Chris Wilson265db952010-09-20 15:41:01 +01002245 }
2246
Jason Wessel21c74a82010-10-13 14:09:44 -05002247 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248 LEAVE_ATOMIC_MODE_SET);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002249 if (ret) {
Chris Wilson265db952010-09-20 15:41:01 +01002250 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002251 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002252 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002253 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002254 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002255
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002256 if (old_fb) {
2257 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson265db952010-09-20 15:41:01 +01002258 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002259 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002260
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002261 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002262
2263 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002264 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002268 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002269
Chris Wilson265db952010-09-20 15:41:01 +01002270 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002273 } else {
2274 master_priv->sarea_priv->pipeA_x = x;
2275 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002276 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002277
2278 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002279}
2280
Chris Wilson5eddb702010-09-11 13:48:45 +01002281static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002282{
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 u32 dpa_ctl;
2286
Zhao Yakui28c97732009-10-09 11:39:41 +08002287 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002288 dpa_ctl = I915_READ(DP_A);
2289 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291 if (clock < 200000) {
2292 u32 temp;
2293 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294 /* workaround for 160Mhz:
2295 1) program 0x4600c bits 15:0 = 0x8124
2296 2) program 0x46010 bit 0 = 1
2297 3) program 0x46034 bit 24 = 1
2298 4) program 0x64000 bit 14 = 1
2299 */
2300 temp = I915_READ(0x4600c);
2301 temp &= 0xffff0000;
2302 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304 temp = I915_READ(0x46010);
2305 I915_WRITE(0x46010, temp | 1);
2306
2307 temp = I915_READ(0x46034);
2308 I915_WRITE(0x46034, temp | (1 << 24));
2309 } else {
2310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311 }
2312 I915_WRITE(DP_A, dpa_ctl);
2313
Chris Wilson5eddb702010-09-11 13:48:45 +01002314 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002315 udelay(500);
2316}
2317
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002318static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 u32 reg, temp;
2325
2326 /* enable normal train */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002329 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002335 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002352
2353 /* IVB wants error correction enabled */
2354 if (IS_IVYBRIDGE(dev))
2355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002357}
2358
Jesse Barnes291427f2011-07-29 12:42:37 -07002359static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364 flags |= FDI_PHASE_SYNC_OVR(pipe);
2365 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366 flags |= FDI_PHASE_SYNC_EN(pipe);
2367 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368 POSTING_READ(SOUTH_CHICKEN1);
2369}
2370
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002371/* The FDI link training functions for ILK/Ibexpeak. */
2372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373{
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002378 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002379 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002380
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002381 /* FDI needs bits from pipe & plane first */
2382 assert_pipe_enabled(dev_priv, pipe);
2383 assert_plane_enabled(dev_priv, plane);
2384
Adam Jacksone1a44742010-06-25 15:32:14 -04002385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002387 reg = FDI_RX_IMR(pipe);
2388 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002389 temp &= ~FDI_RX_SYMBOL_LOCK;
2390 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002391 I915_WRITE(reg, temp);
2392 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002393 udelay(150);
2394
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002395 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002398 temp &= ~(7 << 19);
2399 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002403
Chris Wilson5eddb702010-09-11 13:48:45 +01002404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002411 udelay(150);
2412
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002413 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002414 if (HAS_PCH_IBX(dev)) {
2415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417 FDI_RX_PHASE_SYNC_POINTER_EN);
2418 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002419
Chris Wilson5eddb702010-09-11 13:48:45 +01002420 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002421 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002422 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002428 break;
2429 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002430 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002431 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002432 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002433
2434 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002439 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002440
Chris Wilson5eddb702010-09-11 13:48:45 +01002441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002445 I915_WRITE(reg, temp);
2446
2447 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002448 udelay(150);
2449
Chris Wilson5eddb702010-09-11 13:48:45 +01002450 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002451 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002452 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002460 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002461 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002462 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002463
2464 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002465
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002466}
2467
Akshay Joshi0206e352011-08-16 15:34:10 -04002468static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473};
2474
2475/* The FDI link training functions for SNB/Cougarpoint. */
2476static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002482 u32 reg, temp, i;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002483
Adam Jacksone1a44742010-06-25 15:32:14 -04002484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002493 udelay(150);
2494
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002495 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002506
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002519 udelay(150);
2520
Jesse Barnes291427f2011-07-29 12:42:37 -07002521 if (HAS_PCH_CPT(dev))
2522 cpt_phase_pointer_enable(dev, pipe);
2523
Akshay Joshi0206e352011-08-16 15:34:10 -04002524 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002529 I915_WRITE(reg, temp);
2530
2531 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002532 udelay(500);
2533
Chris Wilson5eddb702010-09-11 13:48:45 +01002534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_BIT_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002539 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 break;
2542 }
2543 }
2544 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002545 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002546
2547 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002548 reg = FDI_TX_CTL(pipe);
2549 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 if (IS_GEN6(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 /* SNB-B */
2555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002557 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002558
Chris Wilson5eddb702010-09-11 13:48:45 +01002559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002561 if (HAS_PCH_CPT(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 } else {
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002571 udelay(150);
2572
Akshay Joshi0206e352011-08-16 15:34:10 -04002573 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002578 I915_WRITE(reg, temp);
2579
2580 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002581 udelay(500);
2582
Chris Wilson5eddb702010-09-11 13:48:45 +01002583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002589 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 break;
2591 }
2592 }
2593 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002594 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002595
2596 DRM_DEBUG_KMS("FDI train done.\n");
2597}
2598
Jesse Barnes357555c2011-04-28 15:09:55 -07002599/* Manual link training for Ivy Bridge A0 parts */
2600static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601{
2602 struct drm_device *dev = crtc->dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605 int pipe = intel_crtc->pipe;
2606 u32 reg, temp, i;
2607
2608 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 for train result */
2610 reg = FDI_RX_IMR(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_RX_SYMBOL_LOCK;
2613 temp &= ~FDI_RX_BIT_LOCK;
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~(7 << 19);
2623 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002628 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002629 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002636 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
Jesse Barnes291427f2011-07-29 12:42:37 -07002642 if (HAS_PCH_CPT(dev))
2643 cpt_phase_pointer_enable(dev, pipe);
2644
Akshay Joshi0206e352011-08-16 15:34:10 -04002645 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659 if (temp & FDI_RX_BIT_LOCK ||
2660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 break;
2664 }
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
Akshay Joshi0206e352011-08-16 15:34:10 -04002687 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691 temp |= snb_b_fdi_train_param[i];
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(500);
2696
2697 reg = FDI_RX_IIR(pipe);
2698 temp = I915_READ(reg);
2699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701 if (temp & FDI_RX_SYMBOL_LOCK) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711}
2712
2713static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002714{
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002719 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002720
Jesse Barnesc64e3112010-09-10 11:27:03 -07002721 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002722 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002724
Jesse Barnes0e23b992010-09-10 11:10:00 -07002725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002729 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002730 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002741 udelay(200);
2742
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
Chris Wilson5eddb702010-09-11 13:48:45 +01002744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002750 udelay(100);
2751 }
2752}
2753
Jesse Barnes291427f2011-07-29 12:42:37 -07002754static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755{
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1);
2764}
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002765static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766{
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777 POSTING_READ(reg);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(0x7 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002789 if (HAS_PCH_IBX(dev)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002791 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002793 ~FDI_RX_PHASE_SYNC_POINTER_EN));
Jesse Barnes291427f2011-07-29 12:42:37 -07002794 } else if (HAS_PCH_CPT(dev)) {
2795 cpt_phase_pointer_disable(dev, pipe);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002796 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002797
2798 /* still set train pattern 1 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 if (HAS_PCH_CPT(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810 } else {
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 }
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp &= ~(0x07 << 16);
2816 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817 I915_WRITE(reg, temp);
2818
2819 POSTING_READ(reg);
2820 udelay(100);
2821}
2822
Chris Wilson6b383a72010-09-13 13:54:26 +01002823/*
2824 * When we disable a pipe, we need to clear any pending scanline wait events
2825 * to avoid hanging the ring, which we assume we are waiting on.
2826 */
2827static void intel_clear_scanline_wait(struct drm_device *dev)
2828{
2829 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8168bd42010-11-11 17:54:52 +00002830 struct intel_ring_buffer *ring;
Chris Wilson6b383a72010-09-13 13:54:26 +01002831 u32 tmp;
2832
2833 if (IS_GEN2(dev))
2834 /* Can't break the hang on i8xx */
2835 return;
2836
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002837 ring = LP_RING(dev_priv);
Chris Wilson8168bd42010-11-11 17:54:52 +00002838 tmp = I915_READ_CTL(ring);
2839 if (tmp & RING_WAIT)
2840 I915_WRITE_CTL(ring, tmp);
Chris Wilson6b383a72010-09-13 13:54:26 +01002841}
2842
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002843static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844{
Chris Wilson05394f32010-11-08 19:18:58 +00002845 struct drm_i915_gem_object *obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002846 struct drm_i915_private *dev_priv;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
Chris Wilson05394f32010-11-08 19:18:58 +00002851 obj = to_intel_framebuffer(crtc->fb)->obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002852 dev_priv = crtc->dev->dev_private;
2853 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002854 atomic_read(&obj->pending_flip) == 0);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002855}
2856
Jesse Barnes040484a2011-01-03 12:14:26 -08002857static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858{
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_mode_config *mode_config = &dev->mode_config;
2861 struct intel_encoder *encoder;
2862
2863 /*
2864 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865 * must be driven by its own crtc; no sharing is possible.
2866 */
2867 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868 if (encoder->base.crtc != crtc)
2869 continue;
2870
2871 switch (encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 if (!intel_encoder_is_pch_edp(&encoder->base))
2874 return false;
2875 continue;
2876 }
2877 }
2878
2879 return true;
2880}
2881
Jesse Barnesf67a5592011-01-05 10:31:48 -08002882/*
2883 * Enable PCH resources required for PCH ports:
2884 * - PCH PLLs
2885 * - FDI training & RX/TX
2886 * - update transcoder timings
2887 * - DP transcoding bits
2888 * - transcoder
2889 */
2890static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002891{
2892 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002896 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002897
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002898 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002899 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002900
Jesse Barnes92f25842011-01-04 15:09:34 -08002901 intel_enable_pch_pll(dev_priv, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002902
2903 if (HAS_PCH_CPT(dev)) {
2904 /* Be sure PCH DPLL SEL is set */
2905 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002906 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002907 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002908 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002909 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes27f82272011-09-02 12:54:37 -07002910 else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
2911 temp |= (TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002912 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002913 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002914
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002915 /* set transcoder timing, panel must allow it */
2916 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01002917 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2918 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2919 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2920
2921 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2922 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2923 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002924
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002925 intel_fdi_normal_train(crtc);
2926
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002927 /* For PCH DP, enable TRANS_DP_CTL */
2928 if (HAS_PCH_CPT(dev) &&
2929 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07002930 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01002931 reg = TRANS_DP_CTL(pipe);
2932 temp = I915_READ(reg);
2933 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002934 TRANS_DP_SYNC_MASK |
2935 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01002936 temp |= (TRANS_DP_OUTPUT_ENABLE |
2937 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07002938 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002939
2940 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002941 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002942 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002943 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002944
2945 switch (intel_trans_dp_port_sel(crtc)) {
2946 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01002947 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002948 break;
2949 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01002950 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002951 break;
2952 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01002953 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002954 break;
2955 default:
2956 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002957 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002958 break;
2959 }
2960
Chris Wilson5eddb702010-09-11 13:48:45 +01002961 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002962 }
2963
Jesse Barnes040484a2011-01-03 12:14:26 -08002964 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002965}
2966
2967static void ironlake_crtc_enable(struct drm_crtc *crtc)
2968{
2969 struct drm_device *dev = crtc->dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
2973 int plane = intel_crtc->plane;
2974 u32 temp;
2975 bool is_pch_port;
2976
2977 if (intel_crtc->active)
2978 return;
2979
2980 intel_crtc->active = true;
2981 intel_update_watermarks(dev);
2982
2983 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2984 temp = I915_READ(PCH_LVDS);
2985 if ((temp & LVDS_PORT_EN) == 0)
2986 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2987 }
2988
2989 is_pch_port = intel_crtc_driving_pch(crtc);
2990
2991 if (is_pch_port)
Jesse Barnes357555c2011-04-28 15:09:55 -07002992 ironlake_fdi_pll_enable(crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002993 else
2994 ironlake_fdi_disable(crtc);
2995
2996 /* Enable panel fitting for LVDS */
2997 if (dev_priv->pch_pf_size &&
2998 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2999 /* Force use of hard-coded filter coefficients
3000 * as some pre-programmed values are broken,
3001 * e.g. x201.
3002 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003003 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3004 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3005 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003006 }
3007
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003008 /*
3009 * On ILK+ LUT must be loaded before the pipe is running but with
3010 * clocks enabled
3011 */
3012 intel_crtc_load_lut(crtc);
3013
Jesse Barnesf67a5592011-01-05 10:31:48 -08003014 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3015 intel_enable_plane(dev_priv, plane, pipe);
3016
3017 if (is_pch_port)
3018 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003019
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003020 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003021 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003022 mutex_unlock(&dev->struct_mutex);
3023
Chris Wilson6b383a72010-09-13 13:54:26 +01003024 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003025}
3026
3027static void ironlake_crtc_disable(struct drm_crtc *crtc)
3028{
3029 struct drm_device *dev = crtc->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032 int pipe = intel_crtc->pipe;
3033 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003034 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003035
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003036 if (!intel_crtc->active)
3037 return;
3038
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003039 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003040 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003041 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003042
Jesse Barnesb24e7172011-01-04 15:09:30 -08003043 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003044
Chris Wilson973d04f2011-07-08 12:22:37 +01003045 if (dev_priv->cfb_plane == plane)
3046 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003047
Jesse Barnesb24e7172011-01-04 15:09:30 -08003048 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003049
Jesse Barnes6be4a602010-09-10 10:26:01 -07003050 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003051 I915_WRITE(PF_CTL(pipe), 0);
3052 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003053
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003054 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003055
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003056 /* This is a horrible layering violation; we should be doing this in
3057 * the connector/encoder ->prepare instead, but we don't always have
3058 * enough information there about the config to know whether it will
3059 * actually be necessary or just cause undesired flicker.
3060 */
3061 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003062
Jesse Barnes040484a2011-01-03 12:14:26 -08003063 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003064
Jesse Barnes6be4a602010-09-10 10:26:01 -07003065 if (HAS_PCH_CPT(dev)) {
3066 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003067 reg = TRANS_DP_CTL(pipe);
3068 temp = I915_READ(reg);
3069 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003070 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003071 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003072
3073 /* disable DPLL_SEL */
3074 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003075 switch (pipe) {
3076 case 0:
3077 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3078 break;
3079 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003080 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003081 break;
3082 case 2:
3083 /* FIXME: manage transcoder PLLs? */
3084 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3085 break;
3086 default:
3087 BUG(); /* wtf */
3088 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003089 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003090 }
3091
3092 /* disable PCH DPLL */
Jesse Barnes92f25842011-01-04 15:09:34 -08003093 intel_disable_pch_pll(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003094
3095 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003096 reg = FDI_RX_CTL(pipe);
3097 temp = I915_READ(reg);
3098 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003099
3100 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003101 reg = FDI_TX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3104
3105 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003106 udelay(100);
3107
Chris Wilson5eddb702010-09-11 13:48:45 +01003108 reg = FDI_RX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003111
3112 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01003113 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003114 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01003115
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003116 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003117 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003118
3119 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003120 intel_update_fbc(dev);
3121 intel_clear_scanline_wait(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003122 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003123}
3124
3125static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3126{
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128 int pipe = intel_crtc->pipe;
3129 int plane = intel_crtc->plane;
3130
Zhenyu Wang2c072452009-06-05 15:38:42 +08003131 /* XXX: When our outputs are all unaware of DPMS modes other than off
3132 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3133 */
3134 switch (mode) {
3135 case DRM_MODE_DPMS_ON:
3136 case DRM_MODE_DPMS_STANDBY:
3137 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01003138 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003139 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01003140 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003141
Zhenyu Wang2c072452009-06-05 15:38:42 +08003142 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01003143 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003144 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08003145 break;
3146 }
3147}
3148
Daniel Vetter02e792f2009-09-15 22:57:34 +02003149static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3150{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003151 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003152 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003153 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003154
Chris Wilson23f09ce2010-08-12 13:53:37 +01003155 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003156 dev_priv->mm.interruptible = false;
3157 (void) intel_overlay_switch_off(intel_crtc->overlay);
3158 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003159 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003160 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003161
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003162 /* Let userspace switch the overlay on again. In most cases userspace
3163 * has to recompute where to put it anyway.
3164 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003165}
3166
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003167static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003168{
3169 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003173 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003174
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003179 intel_update_watermarks(dev);
3180
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003181 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003182 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003183 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003184
3185 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003186 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003187
3188 /* Give the overlay scaler a chance to enable if it's on this pipe */
3189 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003190 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003191}
3192
3193static void i9xx_crtc_disable(struct drm_crtc *crtc)
3194{
3195 struct drm_device *dev = crtc->dev;
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198 int pipe = intel_crtc->pipe;
3199 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003200
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003201 if (!intel_crtc->active)
3202 return;
3203
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003204 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003205 intel_crtc_wait_for_pending_flips(crtc);
3206 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003207 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003208 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003209
Chris Wilson973d04f2011-07-08 12:22:37 +01003210 if (dev_priv->cfb_plane == plane)
3211 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003212
Jesse Barnesb24e7172011-01-04 15:09:30 -08003213 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003214 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003215 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003216
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003217 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003218 intel_update_fbc(dev);
3219 intel_update_watermarks(dev);
3220 intel_clear_scanline_wait(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003221}
3222
3223static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3224{
Jesse Barnes79e53942008-11-07 14:24:08 -08003225 /* XXX: When our outputs are all unaware of DPMS modes other than off
3226 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3227 */
3228 switch (mode) {
3229 case DRM_MODE_DPMS_ON:
3230 case DRM_MODE_DPMS_STANDBY:
3231 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003232 i9xx_crtc_enable(crtc);
3233 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003234 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003235 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003236 break;
3237 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003238}
3239
3240/**
3241 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08003242 */
3243static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3244{
3245 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07003246 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003247 struct drm_i915_master_private *master_priv;
3248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3249 int pipe = intel_crtc->pipe;
3250 bool enabled;
3251
Chris Wilson032d2a02010-09-06 16:17:22 +01003252 if (intel_crtc->dpms_mode == mode)
3253 return;
3254
Chris Wilsondebcadd2010-08-07 11:01:33 +01003255 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01003256
Jesse Barnese70236a2009-09-21 10:42:27 -07003257 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08003258
3259 if (!dev->primary->master)
3260 return;
3261
3262 master_priv = dev->primary->master->driver_priv;
3263 if (!master_priv->sarea_priv)
3264 return;
3265
3266 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3267
3268 switch (pipe) {
3269 case 0:
3270 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3271 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3272 break;
3273 case 1:
3274 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3275 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3276 break;
3277 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003278 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003279 break;
3280 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003281}
3282
Chris Wilsoncdd59982010-09-08 16:30:16 +01003283static void intel_crtc_disable(struct drm_crtc *crtc)
3284{
3285 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3286 struct drm_device *dev = crtc->dev;
3287
3288 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3289
3290 if (crtc->fb) {
3291 mutex_lock(&dev->struct_mutex);
3292 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3293 mutex_unlock(&dev->struct_mutex);
3294 }
3295}
3296
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003297/* Prepare for a mode set.
3298 *
3299 * Note we could be a lot smarter here. We need to figure out which outputs
3300 * will be enabled, which disabled (in short, how the config will changes)
3301 * and perform the minimum necessary steps to accomplish that, e.g. updating
3302 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3303 * panel fitting is in the proper state, etc.
3304 */
3305static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003306{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003307 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003308}
3309
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003310static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003311{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003312 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003313}
3314
3315static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3316{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003317 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003318}
3319
3320static void ironlake_crtc_commit(struct drm_crtc *crtc)
3321{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003322 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003323}
3324
Akshay Joshi0206e352011-08-16 15:34:10 -04003325void intel_encoder_prepare(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003326{
3327 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3328 /* lvds has its own version of prepare see intel_lvds_prepare */
3329 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3330}
3331
Akshay Joshi0206e352011-08-16 15:34:10 -04003332void intel_encoder_commit(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003333{
3334 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3335 /* lvds has its own version of commit see intel_lvds_commit */
3336 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3337}
3338
Chris Wilsonea5b2132010-08-04 13:50:23 +01003339void intel_encoder_destroy(struct drm_encoder *encoder)
3340{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003341 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003342
Chris Wilsonea5b2132010-08-04 13:50:23 +01003343 drm_encoder_cleanup(encoder);
3344 kfree(intel_encoder);
3345}
3346
Jesse Barnes79e53942008-11-07 14:24:08 -08003347static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3348 struct drm_display_mode *mode,
3349 struct drm_display_mode *adjusted_mode)
3350{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003351 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003352
Eric Anholtbad720f2009-10-22 16:11:14 -07003353 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003354 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003355 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3356 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003357 }
Chris Wilson89749352010-09-12 18:25:19 +01003358
3359 /* XXX some encoders set the crtcinfo, others don't.
3360 * Obviously we need some form of conflict resolution here...
3361 */
3362 if (adjusted_mode->crtc_htotal == 0)
3363 drm_mode_set_crtcinfo(adjusted_mode, 0);
3364
Jesse Barnes79e53942008-11-07 14:24:08 -08003365 return true;
3366}
3367
Jesse Barnese70236a2009-09-21 10:42:27 -07003368static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003369{
Jesse Barnese70236a2009-09-21 10:42:27 -07003370 return 400000;
3371}
Jesse Barnes79e53942008-11-07 14:24:08 -08003372
Jesse Barnese70236a2009-09-21 10:42:27 -07003373static int i915_get_display_clock_speed(struct drm_device *dev)
3374{
3375 return 333000;
3376}
Jesse Barnes79e53942008-11-07 14:24:08 -08003377
Jesse Barnese70236a2009-09-21 10:42:27 -07003378static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3379{
3380 return 200000;
3381}
Jesse Barnes79e53942008-11-07 14:24:08 -08003382
Jesse Barnese70236a2009-09-21 10:42:27 -07003383static int i915gm_get_display_clock_speed(struct drm_device *dev)
3384{
3385 u16 gcfgc = 0;
3386
3387 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3388
3389 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003390 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003391 else {
3392 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3393 case GC_DISPLAY_CLOCK_333_MHZ:
3394 return 333000;
3395 default:
3396 case GC_DISPLAY_CLOCK_190_200_MHZ:
3397 return 190000;
3398 }
3399 }
3400}
Jesse Barnes79e53942008-11-07 14:24:08 -08003401
Jesse Barnese70236a2009-09-21 10:42:27 -07003402static int i865_get_display_clock_speed(struct drm_device *dev)
3403{
3404 return 266000;
3405}
3406
3407static int i855_get_display_clock_speed(struct drm_device *dev)
3408{
3409 u16 hpllcc = 0;
3410 /* Assume that the hardware is in the high speed state. This
3411 * should be the default.
3412 */
3413 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3414 case GC_CLOCK_133_200:
3415 case GC_CLOCK_100_200:
3416 return 200000;
3417 case GC_CLOCK_166_250:
3418 return 250000;
3419 case GC_CLOCK_100_133:
3420 return 133000;
3421 }
3422
3423 /* Shouldn't happen */
3424 return 0;
3425}
3426
3427static int i830_get_display_clock_speed(struct drm_device *dev)
3428{
3429 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003430}
3431
Zhenyu Wang2c072452009-06-05 15:38:42 +08003432struct fdi_m_n {
3433 u32 tu;
3434 u32 gmch_m;
3435 u32 gmch_n;
3436 u32 link_m;
3437 u32 link_n;
3438};
3439
3440static void
3441fdi_reduce_ratio(u32 *num, u32 *den)
3442{
3443 while (*num > 0xffffff || *den > 0xffffff) {
3444 *num >>= 1;
3445 *den >>= 1;
3446 }
3447}
3448
Zhenyu Wang2c072452009-06-05 15:38:42 +08003449static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003450ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3451 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003452{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003453 m_n->tu = 64; /* default size */
3454
Chris Wilson22ed1112010-12-04 01:01:29 +00003455 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3456 m_n->gmch_m = bits_per_pixel * pixel_clock;
3457 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003458 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3459
Chris Wilson22ed1112010-12-04 01:01:29 +00003460 m_n->link_m = pixel_clock;
3461 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003462 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3463}
3464
3465
Shaohua Li7662c8b2009-06-26 11:23:55 +08003466struct intel_watermark_params {
3467 unsigned long fifo_size;
3468 unsigned long max_wm;
3469 unsigned long default_wm;
3470 unsigned long guard_size;
3471 unsigned long cacheline_size;
3472};
3473
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003474/* Pineview has different values for various configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003475static const struct intel_watermark_params pineview_display_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003476 PINEVIEW_DISPLAY_FIFO,
3477 PINEVIEW_MAX_WM,
3478 PINEVIEW_DFT_WM,
3479 PINEVIEW_GUARD_WM,
3480 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003481};
Chris Wilsond2102462011-01-24 17:43:27 +00003482static const struct intel_watermark_params pineview_display_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003483 PINEVIEW_DISPLAY_FIFO,
3484 PINEVIEW_MAX_WM,
3485 PINEVIEW_DFT_HPLLOFF_WM,
3486 PINEVIEW_GUARD_WM,
3487 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003488};
Chris Wilsond2102462011-01-24 17:43:27 +00003489static const struct intel_watermark_params pineview_cursor_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003490 PINEVIEW_CURSOR_FIFO,
3491 PINEVIEW_CURSOR_MAX_WM,
3492 PINEVIEW_CURSOR_DFT_WM,
3493 PINEVIEW_CURSOR_GUARD_WM,
3494 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003495};
Chris Wilsond2102462011-01-24 17:43:27 +00003496static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003497 PINEVIEW_CURSOR_FIFO,
3498 PINEVIEW_CURSOR_MAX_WM,
3499 PINEVIEW_CURSOR_DFT_WM,
3500 PINEVIEW_CURSOR_GUARD_WM,
3501 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003502};
Chris Wilsond2102462011-01-24 17:43:27 +00003503static const struct intel_watermark_params g4x_wm_info = {
Jesse Barnes0e442c62009-10-19 10:09:33 +09003504 G4X_FIFO_SIZE,
3505 G4X_MAX_WM,
3506 G4X_MAX_WM,
3507 2,
3508 G4X_FIFO_LINE_SIZE,
3509};
Chris Wilsond2102462011-01-24 17:43:27 +00003510static const struct intel_watermark_params g4x_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003511 I965_CURSOR_FIFO,
3512 I965_CURSOR_MAX_WM,
3513 I965_CURSOR_DFT_WM,
3514 2,
3515 G4X_FIFO_LINE_SIZE,
3516};
Chris Wilsond2102462011-01-24 17:43:27 +00003517static const struct intel_watermark_params i965_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003518 I965_CURSOR_FIFO,
3519 I965_CURSOR_MAX_WM,
3520 I965_CURSOR_DFT_WM,
3521 2,
3522 I915_FIFO_LINE_SIZE,
3523};
Chris Wilsond2102462011-01-24 17:43:27 +00003524static const struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003525 I945_FIFO_SIZE,
3526 I915_MAX_WM,
3527 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003528 2,
3529 I915_FIFO_LINE_SIZE
3530};
Chris Wilsond2102462011-01-24 17:43:27 +00003531static const struct intel_watermark_params i915_wm_info = {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003532 I915_FIFO_SIZE,
3533 I915_MAX_WM,
3534 1,
3535 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003536 I915_FIFO_LINE_SIZE
3537};
Chris Wilsond2102462011-01-24 17:43:27 +00003538static const struct intel_watermark_params i855_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003539 I855GM_FIFO_SIZE,
3540 I915_MAX_WM,
3541 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003542 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003543 I830_FIFO_LINE_SIZE
3544};
Chris Wilsond2102462011-01-24 17:43:27 +00003545static const struct intel_watermark_params i830_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003546 I830_FIFO_SIZE,
3547 I915_MAX_WM,
3548 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003549 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003550 I830_FIFO_LINE_SIZE
3551};
3552
Chris Wilsond2102462011-01-24 17:43:27 +00003553static const struct intel_watermark_params ironlake_display_wm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003554 ILK_DISPLAY_FIFO,
3555 ILK_DISPLAY_MAXWM,
3556 ILK_DISPLAY_DFTWM,
3557 2,
3558 ILK_FIFO_LINE_SIZE
3559};
Chris Wilsond2102462011-01-24 17:43:27 +00003560static const struct intel_watermark_params ironlake_cursor_wm_info = {
Zhao Yakuic936f442010-06-12 14:32:26 +08003561 ILK_CURSOR_FIFO,
3562 ILK_CURSOR_MAXWM,
3563 ILK_CURSOR_DFTWM,
3564 2,
3565 ILK_FIFO_LINE_SIZE
3566};
Chris Wilsond2102462011-01-24 17:43:27 +00003567static const struct intel_watermark_params ironlake_display_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003568 ILK_DISPLAY_SR_FIFO,
3569 ILK_DISPLAY_MAX_SRWM,
3570 ILK_DISPLAY_DFT_SRWM,
3571 2,
3572 ILK_FIFO_LINE_SIZE
3573};
Chris Wilsond2102462011-01-24 17:43:27 +00003574static const struct intel_watermark_params ironlake_cursor_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003575 ILK_CURSOR_SR_FIFO,
3576 ILK_CURSOR_MAX_SRWM,
3577 ILK_CURSOR_DFT_SRWM,
3578 2,
3579 ILK_FIFO_LINE_SIZE
3580};
3581
Chris Wilsond2102462011-01-24 17:43:27 +00003582static const struct intel_watermark_params sandybridge_display_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003583 SNB_DISPLAY_FIFO,
3584 SNB_DISPLAY_MAXWM,
3585 SNB_DISPLAY_DFTWM,
3586 2,
3587 SNB_FIFO_LINE_SIZE
3588};
Chris Wilsond2102462011-01-24 17:43:27 +00003589static const struct intel_watermark_params sandybridge_cursor_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003590 SNB_CURSOR_FIFO,
3591 SNB_CURSOR_MAXWM,
3592 SNB_CURSOR_DFTWM,
3593 2,
3594 SNB_FIFO_LINE_SIZE
3595};
Chris Wilsond2102462011-01-24 17:43:27 +00003596static const struct intel_watermark_params sandybridge_display_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003597 SNB_DISPLAY_SR_FIFO,
3598 SNB_DISPLAY_MAX_SRWM,
3599 SNB_DISPLAY_DFT_SRWM,
3600 2,
3601 SNB_FIFO_LINE_SIZE
3602};
Chris Wilsond2102462011-01-24 17:43:27 +00003603static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003604 SNB_CURSOR_SR_FIFO,
3605 SNB_CURSOR_MAX_SRWM,
3606 SNB_CURSOR_DFT_SRWM,
3607 2,
3608 SNB_FIFO_LINE_SIZE
3609};
3610
3611
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003612/**
3613 * intel_calculate_wm - calculate watermark level
3614 * @clock_in_khz: pixel clock
3615 * @wm: chip FIFO params
3616 * @pixel_size: display pixel size
3617 * @latency_ns: memory latency for the platform
3618 *
3619 * Calculate the watermark level (the level at which the display plane will
3620 * start fetching from memory again). Each chip has a different display
3621 * FIFO size and allocation, so the caller needs to figure that out and pass
3622 * in the correct intel_watermark_params structure.
3623 *
3624 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3625 * on the pixel size. When it reaches the watermark level, it'll start
3626 * fetching FIFO line sized based chunks from memory until the FIFO fills
3627 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3628 * will occur, and a display engine hang could result.
3629 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003630static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
Chris Wilsond2102462011-01-24 17:43:27 +00003631 const struct intel_watermark_params *wm,
3632 int fifo_size,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003633 int pixel_size,
3634 unsigned long latency_ns)
3635{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003636 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003637
Jesse Barnesd6604672009-09-11 12:25:56 -07003638 /*
3639 * Note: we need to make sure we don't overflow for various clock &
3640 * latency values.
3641 * clocks go from a few thousand to several hundred thousand.
3642 * latency is usually a few thousand
3643 */
3644 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3645 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003646 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003647
Joe Perchesbbb0aef52011-04-17 20:35:52 -07003648 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003649
Chris Wilsond2102462011-01-24 17:43:27 +00003650 wm_size = fifo_size - (entries_required + wm->guard_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003651
Joe Perchesbbb0aef52011-04-17 20:35:52 -07003652 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003653
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003654 /* Don't promote wm_size to unsigned... */
3655 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003656 wm_size = wm->max_wm;
Chris Wilsonc3add4b2010-09-08 09:14:08 +01003657 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003658 wm_size = wm->default_wm;
3659 return wm_size;
3660}
3661
3662struct cxsr_latency {
3663 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08003664 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003665 unsigned long fsb_freq;
3666 unsigned long mem_freq;
3667 unsigned long display_sr;
3668 unsigned long display_hpll_disable;
3669 unsigned long cursor_sr;
3670 unsigned long cursor_hpll_disable;
3671};
3672
Chris Wilson403c89f2010-08-04 15:25:31 +01003673static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08003674 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3675 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3676 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3677 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3678 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003679
Li Peng95534262010-05-18 18:58:44 +08003680 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3681 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3682 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3683 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3684 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003685
Li Peng95534262010-05-18 18:58:44 +08003686 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3687 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3688 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3689 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3690 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003691
Li Peng95534262010-05-18 18:58:44 +08003692 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3693 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3694 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3695 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3696 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003697
Li Peng95534262010-05-18 18:58:44 +08003698 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3699 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3700 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3701 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3702 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003703
Li Peng95534262010-05-18 18:58:44 +08003704 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3705 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3706 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3707 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3708 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003709};
3710
Chris Wilson403c89f2010-08-04 15:25:31 +01003711static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3712 int is_ddr3,
3713 int fsb,
3714 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003715{
Chris Wilson403c89f2010-08-04 15:25:31 +01003716 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003717 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003718
3719 if (fsb == 0 || mem == 0)
3720 return NULL;
3721
3722 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3723 latency = &cxsr_latency_table[i];
3724 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08003725 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303726 fsb == latency->fsb_freq && mem == latency->mem_freq)
3727 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003728 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303729
Zhao Yakui28c97732009-10-09 11:39:41 +08003730 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303731
3732 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003733}
3734
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003735static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003738
3739 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003740 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003741}
3742
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07003743/*
3744 * Latency for FIFO fetches is dependent on several factors:
3745 * - memory configuration (speed, channels)
3746 * - chipset
3747 * - current MCH state
3748 * It can be fairly high in some situations, so here we assume a fairly
3749 * pessimal value. It's a tradeoff between extra memory fetches (if we
3750 * set this value too high, the FIFO will fetch frequently to stay full)
3751 * and power consumption (set it too low to save power and we might see
3752 * FIFO underruns and display "flicker").
3753 *
3754 * A value of 5us seems to be a good balance; safe for very low end
3755 * platforms but not overly aggressive on lower latency configs.
3756 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003757static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003758
Jesse Barnese70236a2009-09-21 10:42:27 -07003759static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003760{
3761 struct drm_i915_private *dev_priv = dev->dev_private;
3762 uint32_t dsparb = I915_READ(DSPARB);
3763 int size;
3764
Chris Wilson8de9b312010-07-19 19:59:52 +01003765 size = dsparb & 0x7f;
3766 if (plane)
3767 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003768
Zhao Yakui28c97732009-10-09 11:39:41 +08003769 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003770 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003771
3772 return size;
3773}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003774
Jesse Barnese70236a2009-09-21 10:42:27 -07003775static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3776{
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778 uint32_t dsparb = I915_READ(DSPARB);
3779 int size;
3780
Chris Wilson8de9b312010-07-19 19:59:52 +01003781 size = dsparb & 0x1ff;
3782 if (plane)
3783 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07003784 size >>= 1; /* Convert to cachelines */
3785
Zhao Yakui28c97732009-10-09 11:39:41 +08003786 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003787 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003788
3789 return size;
3790}
3791
3792static int i845_get_fifo_size(struct drm_device *dev, int plane)
3793{
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 uint32_t dsparb = I915_READ(DSPARB);
3796 int size;
3797
3798 size = dsparb & 0x7f;
3799 size >>= 2; /* Convert to cachelines */
3800
Zhao Yakui28c97732009-10-09 11:39:41 +08003801 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003802 plane ? "B" : "A",
3803 size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003804
3805 return size;
3806}
3807
3808static int i830_get_fifo_size(struct drm_device *dev, int plane)
3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 uint32_t dsparb = I915_READ(DSPARB);
3812 int size;
3813
3814 size = dsparb & 0x7f;
3815 size >>= 1; /* Convert to cachelines */
3816
Zhao Yakui28c97732009-10-09 11:39:41 +08003817 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003818 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003819
3820 return size;
3821}
3822
Chris Wilsond2102462011-01-24 17:43:27 +00003823static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3824{
3825 struct drm_crtc *crtc, *enabled = NULL;
3826
3827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3828 if (crtc->enabled && crtc->fb) {
3829 if (enabled)
3830 return NULL;
3831 enabled = crtc;
3832 }
3833 }
3834
3835 return enabled;
3836}
3837
3838static void pineview_update_wm(struct drm_device *dev)
Zhao Yakuid4294342010-03-22 22:45:36 +08003839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003841 struct drm_crtc *crtc;
Chris Wilson403c89f2010-08-04 15:25:31 +01003842 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003843 u32 reg;
3844 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003845
Chris Wilson403c89f2010-08-04 15:25:31 +01003846 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003847 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003848 if (!latency) {
3849 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3850 pineview_disable_cxsr(dev);
3851 return;
3852 }
3853
Chris Wilsond2102462011-01-24 17:43:27 +00003854 crtc = single_enabled_crtc(dev);
3855 if (crtc) {
3856 int clock = crtc->mode.clock;
3857 int pixel_size = crtc->fb->bits_per_pixel / 8;
Zhao Yakuid4294342010-03-22 22:45:36 +08003858
3859 /* Display SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003860 wm = intel_calculate_wm(clock, &pineview_display_wm,
3861 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003862 pixel_size, latency->display_sr);
3863 reg = I915_READ(DSPFW1);
3864 reg &= ~DSPFW_SR_MASK;
3865 reg |= wm << DSPFW_SR_SHIFT;
3866 I915_WRITE(DSPFW1, reg);
3867 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3868
3869 /* cursor SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003870 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3871 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003872 pixel_size, latency->cursor_sr);
3873 reg = I915_READ(DSPFW3);
3874 reg &= ~DSPFW_CURSOR_SR_MASK;
3875 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3876 I915_WRITE(DSPFW3, reg);
3877
3878 /* Display HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003879 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3880 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003881 pixel_size, latency->display_hpll_disable);
3882 reg = I915_READ(DSPFW3);
3883 reg &= ~DSPFW_HPLL_SR_MASK;
3884 reg |= wm & DSPFW_HPLL_SR_MASK;
3885 I915_WRITE(DSPFW3, reg);
3886
3887 /* cursor HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003888 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3889 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003890 pixel_size, latency->cursor_hpll_disable);
3891 reg = I915_READ(DSPFW3);
3892 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3893 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3894 I915_WRITE(DSPFW3, reg);
3895 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3896
3897 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003898 I915_WRITE(DSPFW3,
3899 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003900 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3901 } else {
3902 pineview_disable_cxsr(dev);
3903 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3904 }
3905}
3906
Chris Wilson417ae142011-01-19 15:04:42 +00003907static bool g4x_compute_wm0(struct drm_device *dev,
3908 int plane,
3909 const struct intel_watermark_params *display,
3910 int display_latency_ns,
3911 const struct intel_watermark_params *cursor,
3912 int cursor_latency_ns,
3913 int *plane_wm,
3914 int *cursor_wm)
Jesse Barnes652c3932009-08-17 13:31:43 -07003915{
Chris Wilson417ae142011-01-19 15:04:42 +00003916 struct drm_crtc *crtc;
3917 int htotal, hdisplay, clock, pixel_size;
3918 int line_time_us, line_count;
3919 int entries, tlb_miss;
Jesse Barnes652c3932009-08-17 13:31:43 -07003920
Chris Wilson417ae142011-01-19 15:04:42 +00003921 crtc = intel_get_crtc_for_plane(dev, plane);
Chris Wilson5c72d062011-04-13 09:28:23 +01003922 if (crtc->fb == NULL || !crtc->enabled) {
3923 *cursor_wm = cursor->guard_size;
3924 *plane_wm = display->guard_size;
Chris Wilson417ae142011-01-19 15:04:42 +00003925 return false;
Chris Wilson5c72d062011-04-13 09:28:23 +01003926 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003927
Chris Wilson417ae142011-01-19 15:04:42 +00003928 htotal = crtc->mode.htotal;
3929 hdisplay = crtc->mode.hdisplay;
3930 clock = crtc->mode.clock;
3931 pixel_size = crtc->fb->bits_per_pixel / 8;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003932
Chris Wilson417ae142011-01-19 15:04:42 +00003933 /* Use the small buffer method to calculate plane watermark */
3934 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3935 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3936 if (tlb_miss > 0)
3937 entries += tlb_miss;
3938 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3939 *plane_wm = entries + display->guard_size;
3940 if (*plane_wm > (int)display->max_wm)
3941 *plane_wm = display->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003942
Chris Wilson417ae142011-01-19 15:04:42 +00003943 /* Use the large buffer method to calculate cursor watermark */
3944 line_time_us = ((htotal * 1000) / clock);
3945 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3946 entries = line_count * 64 * pixel_size;
3947 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3948 if (tlb_miss > 0)
3949 entries += tlb_miss;
3950 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3951 *cursor_wm = entries + cursor->guard_size;
3952 if (*cursor_wm > (int)cursor->max_wm)
3953 *cursor_wm = (int)cursor->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003954
Chris Wilson417ae142011-01-19 15:04:42 +00003955 return true;
3956}
Jesse Barnes0e442c62009-10-19 10:09:33 +09003957
Chris Wilson417ae142011-01-19 15:04:42 +00003958/*
3959 * Check the wm result.
3960 *
3961 * If any calculated watermark values is larger than the maximum value that
3962 * can be programmed into the associated watermark register, that watermark
3963 * must be disabled.
3964 */
3965static bool g4x_check_srwm(struct drm_device *dev,
3966 int display_wm, int cursor_wm,
3967 const struct intel_watermark_params *display,
3968 const struct intel_watermark_params *cursor)
3969{
3970 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3971 display_wm, cursor_wm);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003972
Chris Wilson417ae142011-01-19 15:04:42 +00003973 if (display_wm > display->max_wm) {
Joe Perchesbbb0aef52011-04-17 20:35:52 -07003974 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00003975 display_wm, display->max_wm);
3976 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003977 }
3978
Chris Wilson417ae142011-01-19 15:04:42 +00003979 if (cursor_wm > cursor->max_wm) {
Joe Perchesbbb0aef52011-04-17 20:35:52 -07003980 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00003981 cursor_wm, cursor->max_wm);
3982 return false;
3983 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003984
Chris Wilson417ae142011-01-19 15:04:42 +00003985 if (!(display_wm || cursor_wm)) {
3986 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3987 return false;
3988 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003989
Chris Wilson417ae142011-01-19 15:04:42 +00003990 return true;
3991}
3992
3993static bool g4x_compute_srwm(struct drm_device *dev,
Chris Wilsond2102462011-01-24 17:43:27 +00003994 int plane,
3995 int latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00003996 const struct intel_watermark_params *display,
3997 const struct intel_watermark_params *cursor,
3998 int *display_wm, int *cursor_wm)
3999{
Chris Wilsond2102462011-01-24 17:43:27 +00004000 struct drm_crtc *crtc;
4001 int hdisplay, htotal, pixel_size, clock;
Chris Wilson417ae142011-01-19 15:04:42 +00004002 unsigned long line_time_us;
4003 int line_count, line_size;
4004 int small, large;
4005 int entries;
4006
4007 if (!latency_ns) {
4008 *display_wm = *cursor_wm = 0;
4009 return false;
4010 }
4011
Chris Wilsond2102462011-01-24 17:43:27 +00004012 crtc = intel_get_crtc_for_plane(dev, plane);
4013 hdisplay = crtc->mode.hdisplay;
4014 htotal = crtc->mode.htotal;
4015 clock = crtc->mode.clock;
4016 pixel_size = crtc->fb->bits_per_pixel / 8;
4017
Chris Wilson417ae142011-01-19 15:04:42 +00004018 line_time_us = (htotal * 1000) / clock;
4019 line_count = (latency_ns / line_time_us + 1000) / 1000;
4020 line_size = hdisplay * pixel_size;
4021
4022 /* Use the minimum of the small and large buffer method for primary */
4023 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4024 large = line_count * line_size;
4025
4026 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4027 *display_wm = entries + display->guard_size;
4028
4029 /* calculate the self-refresh watermark for display cursor */
4030 entries = line_count * pixel_size * 64;
4031 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4032 *cursor_wm = entries + cursor->guard_size;
4033
4034 return g4x_check_srwm(dev,
4035 *display_wm, *cursor_wm,
4036 display, cursor);
4037}
4038
Yuanhan Liu7ccb4a52011-03-18 07:37:35 +00004039#define single_plane_enabled(mask) is_power_of_2(mask)
Chris Wilsond2102462011-01-24 17:43:27 +00004040
4041static void g4x_update_wm(struct drm_device *dev)
Chris Wilson417ae142011-01-19 15:04:42 +00004042{
4043 static const int sr_latency_ns = 12000;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00004046 int plane_sr, cursor_sr;
4047 unsigned int enabled = 0;
Chris Wilson417ae142011-01-19 15:04:42 +00004048
4049 if (g4x_compute_wm0(dev, 0,
4050 &g4x_wm_info, latency_ns,
4051 &g4x_cursor_wm_info, latency_ns,
4052 &planea_wm, &cursora_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00004053 enabled |= 1;
Chris Wilson417ae142011-01-19 15:04:42 +00004054
4055 if (g4x_compute_wm0(dev, 1,
4056 &g4x_wm_info, latency_ns,
4057 &g4x_cursor_wm_info, latency_ns,
4058 &planeb_wm, &cursorb_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00004059 enabled |= 2;
Chris Wilson417ae142011-01-19 15:04:42 +00004060
4061 plane_sr = cursor_sr = 0;
Chris Wilsond2102462011-01-24 17:43:27 +00004062 if (single_plane_enabled(enabled) &&
4063 g4x_compute_srwm(dev, ffs(enabled) - 1,
4064 sr_latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00004065 &g4x_wm_info,
4066 &g4x_cursor_wm_info,
4067 &plane_sr, &cursor_sr))
4068 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4069 else
4070 I915_WRITE(FW_BLC_SELF,
4071 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4072
Chris Wilson308977a2011-02-02 10:41:20 +00004073 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4074 planea_wm, cursora_wm,
4075 planeb_wm, cursorb_wm,
4076 plane_sr, cursor_sr);
Chris Wilson417ae142011-01-19 15:04:42 +00004077
4078 I915_WRITE(DSPFW1,
4079 (plane_sr << DSPFW_SR_SHIFT) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004080 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
Chris Wilson417ae142011-01-19 15:04:42 +00004081 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4082 planea_wm);
4083 I915_WRITE(DSPFW2,
4084 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004085 (cursora_wm << DSPFW_CURSORA_SHIFT));
4086 /* HPLL off in SR has some issues on G4x... disable it */
Chris Wilson417ae142011-01-19 15:04:42 +00004087 I915_WRITE(DSPFW3,
4088 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004089 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07004090}
4091
Chris Wilsond2102462011-01-24 17:43:27 +00004092static void i965_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004093{
4094 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004095 struct drm_crtc *crtc;
4096 int srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004097 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004098
Jesse Barnes1dc75462009-10-19 10:08:17 +09004099 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00004100 crtc = single_enabled_crtc(dev);
4101 if (crtc) {
Jesse Barnes1dc75462009-10-19 10:08:17 +09004102 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01004103 static const int sr_latency_ns = 12000;
Chris Wilsond2102462011-01-24 17:43:27 +00004104 int clock = crtc->mode.clock;
4105 int htotal = crtc->mode.htotal;
4106 int hdisplay = crtc->mode.hdisplay;
4107 int pixel_size = crtc->fb->bits_per_pixel / 8;
4108 unsigned long line_time_us;
4109 int entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09004110
Chris Wilsond2102462011-01-24 17:43:27 +00004111 line_time_us = ((htotal * 1000) / clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09004112
4113 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00004114 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4115 pixel_size * hdisplay;
4116 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
Chris Wilsond2102462011-01-24 17:43:27 +00004117 srwm = I965_FIFO_SIZE - entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09004118 if (srwm < 0)
4119 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08004120 srwm &= 0x1ff;
Chris Wilson308977a2011-02-02 10:41:20 +00004121 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4122 entries, srwm);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004123
Chris Wilsond2102462011-01-24 17:43:27 +00004124 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01004125 pixel_size * 64;
Chris Wilsond2102462011-01-24 17:43:27 +00004126 entries = DIV_ROUND_UP(entries,
Chris Wilson8de9b312010-07-19 19:59:52 +01004127 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004128 cursor_sr = i965_cursor_wm_info.fifo_size -
Chris Wilsond2102462011-01-24 17:43:27 +00004129 (entries + i965_cursor_wm_info.guard_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004130
4131 if (cursor_sr > i965_cursor_wm_info.max_wm)
4132 cursor_sr = i965_cursor_wm_info.max_wm;
4133
4134 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4135 "cursor %d\n", srwm, cursor_sr);
4136
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004137 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07004138 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05304139 } else {
4140 /* Turn off self refresh if both pipes are enabled */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004141 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07004142 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4143 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09004144 }
4145
4146 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4147 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004148
4149 /* 965 has limitations... */
Chris Wilson417ae142011-01-19 15:04:42 +00004150 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4151 (8 << 16) | (8 << 8) | (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08004152 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004153 /* update cursor SR watermark */
4154 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08004155}
4156
Chris Wilsond2102462011-01-24 17:43:27 +00004157static void i9xx_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004158{
4159 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004160 const struct intel_watermark_params *wm_info;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004161 uint32_t fwater_lo;
4162 uint32_t fwater_hi;
Chris Wilsond2102462011-01-24 17:43:27 +00004163 int cwm, srwm = 1;
4164 int fifo_size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004165 int planea_wm, planeb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00004166 struct drm_crtc *crtc, *enabled = NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004167
Chris Wilson72557b42011-01-31 10:29:55 +00004168 if (IS_I945GM(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004169 wm_info = &i945_wm_info;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004170 else if (!IS_GEN2(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004171 wm_info = &i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004172 else
Chris Wilsond2102462011-01-24 17:43:27 +00004173 wm_info = &i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004174
Chris Wilsond2102462011-01-24 17:43:27 +00004175 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4176 crtc = intel_get_crtc_for_plane(dev, 0);
4177 if (crtc->enabled && crtc->fb) {
4178 planea_wm = intel_calculate_wm(crtc->mode.clock,
4179 wm_info, fifo_size,
4180 crtc->fb->bits_per_pixel / 8,
4181 latency_ns);
4182 enabled = crtc;
4183 } else
4184 planea_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004185
Chris Wilsond2102462011-01-24 17:43:27 +00004186 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4187 crtc = intel_get_crtc_for_plane(dev, 1);
4188 if (crtc->enabled && crtc->fb) {
4189 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4190 wm_info, fifo_size,
4191 crtc->fb->bits_per_pixel / 8,
4192 latency_ns);
4193 if (enabled == NULL)
4194 enabled = crtc;
4195 else
4196 enabled = NULL;
4197 } else
4198 planeb_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004199
Zhao Yakui28c97732009-10-09 11:39:41 +08004200 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004201
4202 /*
4203 * Overlay gets an aggressive default since video jitter is bad.
4204 */
4205 cwm = 2;
4206
Alexander Lam18b21902011-01-03 13:28:56 -05004207 /* Play safe and disable self-refresh before adjusting watermarks. */
4208 if (IS_I945G(dev) || IS_I945GM(dev))
4209 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4210 else if (IS_I915GM(dev))
4211 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4212
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004213 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00004214 if (HAS_FW_BLC(dev) && enabled) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004215 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01004216 static const int sr_latency_ns = 6000;
Chris Wilsond2102462011-01-24 17:43:27 +00004217 int clock = enabled->mode.clock;
4218 int htotal = enabled->mode.htotal;
4219 int hdisplay = enabled->mode.hdisplay;
4220 int pixel_size = enabled->fb->bits_per_pixel / 8;
4221 unsigned long line_time_us;
4222 int entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004223
Chris Wilsond2102462011-01-24 17:43:27 +00004224 line_time_us = (htotal * 1000) / clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004225
4226 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00004227 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4228 pixel_size * hdisplay;
4229 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4230 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4231 srwm = wm_info->fifo_size - entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004232 if (srwm < 0)
4233 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08004234
4235 if (IS_I945G(dev) || IS_I945GM(dev))
Alexander Lam18b21902011-01-03 13:28:56 -05004236 I915_WRITE(FW_BLC_SELF,
4237 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4238 else if (IS_I915GM(dev))
Li Pengee980b82010-01-27 19:01:11 +08004239 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004240 }
4241
Zhao Yakui28c97732009-10-09 11:39:41 +08004242 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004243 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004244
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004245 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4246 fwater_hi = (cwm & 0x1f);
4247
4248 /* Set request length to 8 cachelines per fetch */
4249 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4250 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004251
4252 I915_WRITE(FW_BLC, fwater_lo);
4253 I915_WRITE(FW_BLC2, fwater_hi);
Alexander Lam18b21902011-01-03 13:28:56 -05004254
Chris Wilsond2102462011-01-24 17:43:27 +00004255 if (HAS_FW_BLC(dev)) {
4256 if (enabled) {
4257 if (IS_I945G(dev) || IS_I945GM(dev))
4258 I915_WRITE(FW_BLC_SELF,
4259 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4260 else if (IS_I915GM(dev))
4261 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4262 DRM_DEBUG_KMS("memory self refresh enabled\n");
4263 } else
4264 DRM_DEBUG_KMS("memory self refresh disabled\n");
4265 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08004266}
4267
Chris Wilsond2102462011-01-24 17:43:27 +00004268static void i830_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004269{
4270 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004271 struct drm_crtc *crtc;
4272 uint32_t fwater_lo;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004273 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004274
Chris Wilsond2102462011-01-24 17:43:27 +00004275 crtc = single_enabled_crtc(dev);
4276 if (crtc == NULL)
4277 return;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004278
Chris Wilsond2102462011-01-24 17:43:27 +00004279 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4280 dev_priv->display.get_fifo_size(dev, 0),
4281 crtc->fb->bits_per_pixel / 8,
4282 latency_ns);
4283 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesf3601322009-07-22 12:54:59 -07004284 fwater_lo |= (3<<8) | planea_wm;
4285
Zhao Yakui28c97732009-10-09 11:39:41 +08004286 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004287
4288 I915_WRITE(FW_BLC, fwater_lo);
4289}
4290
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004291#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08004292#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004293
Jesse Barnesb79d4992010-12-21 13:10:23 -08004294/*
4295 * Check the wm result.
4296 *
4297 * If any calculated watermark values is larger than the maximum value that
4298 * can be programmed into the associated watermark register, that watermark
4299 * must be disabled.
4300 */
4301static bool ironlake_check_srwm(struct drm_device *dev, int level,
4302 int fbc_wm, int display_wm, int cursor_wm,
4303 const struct intel_watermark_params *display,
4304 const struct intel_watermark_params *cursor)
4305{
4306 struct drm_i915_private *dev_priv = dev->dev_private;
4307
4308 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4309 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4310
4311 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4312 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4313 fbc_wm, SNB_FBC_MAX_SRWM, level);
4314
4315 /* fbc has it's own way to disable FBC WM */
4316 I915_WRITE(DISP_ARB_CTL,
4317 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4318 return false;
4319 }
4320
4321 if (display_wm > display->max_wm) {
4322 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4323 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4324 return false;
4325 }
4326
4327 if (cursor_wm > cursor->max_wm) {
4328 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4329 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4330 return false;
4331 }
4332
4333 if (!(fbc_wm || display_wm || cursor_wm)) {
4334 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4335 return false;
4336 }
4337
4338 return true;
4339}
4340
4341/*
4342 * Compute watermark values of WM[1-3],
4343 */
Chris Wilsond2102462011-01-24 17:43:27 +00004344static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4345 int latency_ns,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004346 const struct intel_watermark_params *display,
4347 const struct intel_watermark_params *cursor,
4348 int *fbc_wm, int *display_wm, int *cursor_wm)
4349{
Chris Wilsond2102462011-01-24 17:43:27 +00004350 struct drm_crtc *crtc;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004351 unsigned long line_time_us;
Chris Wilsond2102462011-01-24 17:43:27 +00004352 int hdisplay, htotal, pixel_size, clock;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004353 int line_count, line_size;
4354 int small, large;
4355 int entries;
4356
4357 if (!latency_ns) {
4358 *fbc_wm = *display_wm = *cursor_wm = 0;
4359 return false;
4360 }
4361
Chris Wilsond2102462011-01-24 17:43:27 +00004362 crtc = intel_get_crtc_for_plane(dev, plane);
4363 hdisplay = crtc->mode.hdisplay;
4364 htotal = crtc->mode.htotal;
4365 clock = crtc->mode.clock;
4366 pixel_size = crtc->fb->bits_per_pixel / 8;
4367
Jesse Barnesb79d4992010-12-21 13:10:23 -08004368 line_time_us = (htotal * 1000) / clock;
4369 line_count = (latency_ns / line_time_us + 1000) / 1000;
4370 line_size = hdisplay * pixel_size;
4371
4372 /* Use the minimum of the small and large buffer method for primary */
4373 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4374 large = line_count * line_size;
4375
4376 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4377 *display_wm = entries + display->guard_size;
4378
4379 /*
4380 * Spec says:
4381 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4382 */
4383 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4384
4385 /* calculate the self-refresh watermark for display cursor */
4386 entries = line_count * pixel_size * 64;
4387 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4388 *cursor_wm = entries + cursor->guard_size;
4389
4390 return ironlake_check_srwm(dev, level,
4391 *fbc_wm, *display_wm, *cursor_wm,
4392 display, cursor);
4393}
4394
Chris Wilsond2102462011-01-24 17:43:27 +00004395static void ironlake_update_wm(struct drm_device *dev)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004396{
4397 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004398 int fbc_wm, plane_wm, cursor_wm;
4399 unsigned int enabled;
Zhao Yakuic936f442010-06-12 14:32:26 +08004400
Chris Wilson4ed765f2010-09-11 10:46:47 +01004401 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004402 if (g4x_compute_wm0(dev, 0,
4403 &ironlake_display_wm_info,
4404 ILK_LP0_PLANE_LATENCY,
4405 &ironlake_cursor_wm_info,
4406 ILK_LP0_CURSOR_LATENCY,
4407 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004408 I915_WRITE(WM0_PIPEA_ILK,
4409 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4410 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4411 " plane %d, " "cursor: %d\n",
4412 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004413 enabled |= 1;
Zhao Yakuic936f442010-06-12 14:32:26 +08004414 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004415
Chris Wilson9f405102011-05-12 22:17:14 +01004416 if (g4x_compute_wm0(dev, 1,
4417 &ironlake_display_wm_info,
4418 ILK_LP0_PLANE_LATENCY,
4419 &ironlake_cursor_wm_info,
4420 ILK_LP0_CURSOR_LATENCY,
4421 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004422 I915_WRITE(WM0_PIPEB_ILK,
4423 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4424 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4425 " plane %d, cursor: %d\n",
4426 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004427 enabled |= 2;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004428 }
4429
4430 /*
4431 * Calculate and update the self-refresh watermark only when one
4432 * display plane is used.
4433 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004434 I915_WRITE(WM3_LP_ILK, 0);
4435 I915_WRITE(WM2_LP_ILK, 0);
4436 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004437
Chris Wilsond2102462011-01-24 17:43:27 +00004438 if (!single_plane_enabled(enabled))
Jesse Barnesb79d4992010-12-21 13:10:23 -08004439 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004440 enabled = ffs(enabled) - 1;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004441
Jesse Barnesb79d4992010-12-21 13:10:23 -08004442 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004443 if (!ironlake_compute_srwm(dev, 1, enabled,
4444 ILK_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004445 &ironlake_display_srwm_info,
4446 &ironlake_cursor_srwm_info,
4447 &fbc_wm, &plane_wm, &cursor_wm))
4448 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004449
Jesse Barnesb79d4992010-12-21 13:10:23 -08004450 I915_WRITE(WM1_LP_ILK,
4451 WM1_LP_SR_EN |
4452 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4453 (fbc_wm << WM1_LP_FBC_SHIFT) |
4454 (plane_wm << WM1_LP_SR_SHIFT) |
4455 cursor_wm);
Chris Wilson4ed765f2010-09-11 10:46:47 +01004456
Jesse Barnesb79d4992010-12-21 13:10:23 -08004457 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004458 if (!ironlake_compute_srwm(dev, 2, enabled,
4459 ILK_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004460 &ironlake_display_srwm_info,
4461 &ironlake_cursor_srwm_info,
4462 &fbc_wm, &plane_wm, &cursor_wm))
4463 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004464
Jesse Barnesb79d4992010-12-21 13:10:23 -08004465 I915_WRITE(WM2_LP_ILK,
4466 WM2_LP_EN |
4467 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4468 (fbc_wm << WM1_LP_FBC_SHIFT) |
4469 (plane_wm << WM1_LP_SR_SHIFT) |
4470 cursor_wm);
Yuanhan Liu13982612010-12-15 15:42:31 +08004471
4472 /*
Jesse Barnesb79d4992010-12-21 13:10:23 -08004473 * WM3 is unsupported on ILK, probably because we don't have latency
4474 * data for that power state
Yuanhan Liu13982612010-12-15 15:42:31 +08004475 */
Yuanhan Liu13982612010-12-15 15:42:31 +08004476}
4477
Chris Wilsond2102462011-01-24 17:43:27 +00004478static void sandybridge_update_wm(struct drm_device *dev)
Yuanhan Liu13982612010-12-15 15:42:31 +08004479{
4480 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004481 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Chris Wilsond2102462011-01-24 17:43:27 +00004482 int fbc_wm, plane_wm, cursor_wm;
4483 unsigned int enabled;
Yuanhan Liu13982612010-12-15 15:42:31 +08004484
4485 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004486 if (g4x_compute_wm0(dev, 0,
4487 &sandybridge_display_wm_info, latency,
4488 &sandybridge_cursor_wm_info, latency,
4489 &plane_wm, &cursor_wm)) {
Yuanhan Liu13982612010-12-15 15:42:31 +08004490 I915_WRITE(WM0_PIPEA_ILK,
4491 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4492 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4493 " plane %d, " "cursor: %d\n",
4494 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004495 enabled |= 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004496 }
4497
Chris Wilson9f405102011-05-12 22:17:14 +01004498 if (g4x_compute_wm0(dev, 1,
4499 &sandybridge_display_wm_info, latency,
4500 &sandybridge_cursor_wm_info, latency,
4501 &plane_wm, &cursor_wm)) {
Yuanhan Liu13982612010-12-15 15:42:31 +08004502 I915_WRITE(WM0_PIPEB_ILK,
4503 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4504 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4505 " plane %d, cursor: %d\n",
4506 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004507 enabled |= 2;
Yuanhan Liu13982612010-12-15 15:42:31 +08004508 }
4509
4510 /*
4511 * Calculate and update the self-refresh watermark only when one
4512 * display plane is used.
4513 *
4514 * SNB support 3 levels of watermark.
4515 *
4516 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4517 * and disabled in the descending order
4518 *
4519 */
4520 I915_WRITE(WM3_LP_ILK, 0);
4521 I915_WRITE(WM2_LP_ILK, 0);
4522 I915_WRITE(WM1_LP_ILK, 0);
4523
Chris Wilsond2102462011-01-24 17:43:27 +00004524 if (!single_plane_enabled(enabled))
Yuanhan Liu13982612010-12-15 15:42:31 +08004525 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004526 enabled = ffs(enabled) - 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004527
4528 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004529 if (!ironlake_compute_srwm(dev, 1, enabled,
4530 SNB_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004531 &sandybridge_display_srwm_info,
4532 &sandybridge_cursor_srwm_info,
4533 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004534 return;
4535
4536 I915_WRITE(WM1_LP_ILK,
4537 WM1_LP_SR_EN |
4538 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4539 (fbc_wm << WM1_LP_FBC_SHIFT) |
4540 (plane_wm << WM1_LP_SR_SHIFT) |
4541 cursor_wm);
4542
4543 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004544 if (!ironlake_compute_srwm(dev, 2, enabled,
4545 SNB_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004546 &sandybridge_display_srwm_info,
4547 &sandybridge_cursor_srwm_info,
4548 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004549 return;
4550
4551 I915_WRITE(WM2_LP_ILK,
4552 WM2_LP_EN |
4553 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4554 (fbc_wm << WM1_LP_FBC_SHIFT) |
4555 (plane_wm << WM1_LP_SR_SHIFT) |
4556 cursor_wm);
4557
4558 /* WM3 */
Chris Wilsond2102462011-01-24 17:43:27 +00004559 if (!ironlake_compute_srwm(dev, 3, enabled,
4560 SNB_READ_WM3_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004561 &sandybridge_display_srwm_info,
4562 &sandybridge_cursor_srwm_info,
4563 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004564 return;
4565
4566 I915_WRITE(WM3_LP_ILK,
4567 WM3_LP_EN |
4568 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4569 (fbc_wm << WM1_LP_FBC_SHIFT) |
4570 (plane_wm << WM1_LP_SR_SHIFT) |
4571 cursor_wm);
4572}
4573
Shaohua Li7662c8b2009-06-26 11:23:55 +08004574/**
4575 * intel_update_watermarks - update FIFO watermark values based on current modes
4576 *
4577 * Calculate watermark values for the various WM regs based on current mode
4578 * and plane configuration.
4579 *
4580 * There are several cases to deal with here:
4581 * - normal (i.e. non-self-refresh)
4582 * - self-refresh (SR) mode
4583 * - lines are large relative to FIFO size (buffer can hold up to 2)
4584 * - lines are small relative to FIFO size (buffer can hold more than 2
4585 * lines), so need to account for TLB latency
4586 *
4587 * The normal calculation is:
4588 * watermark = dotclock * bytes per pixel * latency
4589 * where latency is platform & configuration dependent (we assume pessimal
4590 * values here).
4591 *
4592 * The SR calculation is:
4593 * watermark = (trunc(latency/line time)+1) * surface width *
4594 * bytes per pixel
4595 * where
4596 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08004597 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08004598 * and latency is assumed to be high, as above.
4599 *
4600 * The final value programmed to the register should always be rounded up,
4601 * and include an extra 2 entries to account for clock crossings.
4602 *
4603 * We don't use the sprite, so we can ignore that. And on Crestline we have
4604 * to set the non-SR watermarks to 8.
Chris Wilson5eddb702010-09-11 13:48:45 +01004605 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004606static void intel_update_watermarks(struct drm_device *dev)
4607{
Jesse Barnese70236a2009-09-21 10:42:27 -07004608 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004609
Chris Wilsond2102462011-01-24 17:43:27 +00004610 if (dev_priv->display.update_wm)
4611 dev_priv->display.update_wm(dev);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004612}
4613
Chris Wilsona7615032011-01-12 17:04:08 +00004614static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4615{
Keith Packard72bbe582011-09-26 16:09:45 -07004616 if (i915_panel_use_ssc >= 0)
4617 return i915_panel_use_ssc != 0;
4618 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004619 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004620}
4621
Jesse Barnes5a354202011-06-24 12:19:22 -07004622/**
4623 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4624 * @crtc: CRTC structure
4625 *
4626 * A pipe may be connected to one or more outputs. Based on the depth of the
4627 * attached framebuffer, choose a good color depth to use on the pipe.
4628 *
4629 * If possible, match the pipe depth to the fb depth. In some cases, this
4630 * isn't ideal, because the connected output supports a lesser or restricted
4631 * set of depths. Resolve that here:
4632 * LVDS typically supports only 6bpc, so clamp down in that case
4633 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4634 * Displays may support a restricted set as well, check EDID and clamp as
4635 * appropriate.
4636 *
4637 * RETURNS:
4638 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4639 * true if they don't match).
4640 */
4641static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4642 unsigned int *pipe_bpp)
4643{
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct drm_encoder *encoder;
4647 struct drm_connector *connector;
4648 unsigned int display_bpc = UINT_MAX, bpc;
4649
4650 /* Walk the encoders & connectors on this crtc, get min bpc */
4651 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4652 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4653
4654 if (encoder->crtc != crtc)
4655 continue;
4656
4657 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4658 unsigned int lvds_bpc;
4659
4660 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4661 LVDS_A3_POWER_UP)
4662 lvds_bpc = 8;
4663 else
4664 lvds_bpc = 6;
4665
4666 if (lvds_bpc < display_bpc) {
4667 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4668 display_bpc = lvds_bpc;
4669 }
4670 continue;
4671 }
4672
4673 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4674 /* Use VBT settings if we have an eDP panel */
4675 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4676
4677 if (edp_bpc < display_bpc) {
4678 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4679 display_bpc = edp_bpc;
4680 }
4681 continue;
4682 }
4683
4684 /* Not one of the known troublemakers, check the EDID */
4685 list_for_each_entry(connector, &dev->mode_config.connector_list,
4686 head) {
4687 if (connector->encoder != encoder)
4688 continue;
4689
Jesse Barnes62ac41a2011-07-28 12:55:14 -07004690 /* Don't use an invalid EDID bpc value */
4691 if (connector->display_info.bpc &&
4692 connector->display_info.bpc < display_bpc) {
Jesse Barnes5a354202011-06-24 12:19:22 -07004693 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4694 display_bpc = connector->display_info.bpc;
4695 }
4696 }
4697
4698 /*
4699 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4700 * through, clamp it down. (Note: >12bpc will be caught below.)
4701 */
4702 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4703 if (display_bpc > 8 && display_bpc < 12) {
4704 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4705 display_bpc = 12;
4706 } else {
4707 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4708 display_bpc = 8;
4709 }
4710 }
4711 }
4712
4713 /*
4714 * We could just drive the pipe at the highest bpc all the time and
4715 * enable dithering as needed, but that costs bandwidth. So choose
4716 * the minimum value that expresses the full color range of the fb but
4717 * also stays within the max display bpc discovered above.
4718 */
4719
4720 switch (crtc->fb->depth) {
4721 case 8:
4722 bpc = 8; /* since we go through a colormap */
4723 break;
4724 case 15:
4725 case 16:
4726 bpc = 6; /* min is 18bpp */
4727 break;
4728 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07004729 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07004730 break;
4731 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07004732 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07004733 break;
4734 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07004735 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07004736 break;
4737 default:
4738 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4739 bpc = min((unsigned int)8, display_bpc);
4740 break;
4741 }
4742
Keith Packard578393c2011-09-05 11:53:21 -07004743 display_bpc = min(display_bpc, bpc);
4744
Jesse Barnes5a354202011-06-24 12:19:22 -07004745 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4746 bpc, display_bpc);
4747
Keith Packard578393c2011-09-05 11:53:21 -07004748 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07004749
4750 return display_bpc != bpc;
4751}
4752
Eric Anholtf564048e2011-03-30 13:01:02 -07004753static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4754 struct drm_display_mode *mode,
4755 struct drm_display_mode *adjusted_mode,
4756 int x, int y,
4757 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004758{
4759 struct drm_device *dev = crtc->dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4762 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004763 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004764 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004765 intel_clock_t clock, reduced_clock;
Chris Wilson5eddb702010-09-11 13:48:45 +01004766 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Jesse Barnes652c3932009-08-17 13:31:43 -07004767 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004768 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004769 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson5eddb702010-09-11 13:48:45 +01004770 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004771 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004772 int ret;
Eric Anholtfae14982011-03-30 13:01:09 -07004773 u32 temp;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004774 u32 lvds_sync = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08004775
Chris Wilson5eddb702010-09-11 13:48:45 +01004776 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4777 if (encoder->base.crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004778 continue;
4779
Chris Wilson5eddb702010-09-11 13:48:45 +01004780 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004781 case INTEL_OUTPUT_LVDS:
4782 is_lvds = true;
4783 break;
4784 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004785 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004786 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004787 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004788 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004789 break;
4790 case INTEL_OUTPUT_DVO:
4791 is_dvo = true;
4792 break;
4793 case INTEL_OUTPUT_TVOUT:
4794 is_tv = true;
4795 break;
4796 case INTEL_OUTPUT_ANALOG:
4797 is_crt = true;
4798 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004799 case INTEL_OUTPUT_DISPLAYPORT:
4800 is_dp = true;
4801 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004802 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004803
Eric Anholtc751ce42010-03-25 11:48:48 -07004804 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004805 }
4806
Chris Wilsona7615032011-01-12 17:04:08 +00004807 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004808 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08004809 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004810 refclk / 1000);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004811 } else if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004812 refclk = 96000;
4813 } else {
4814 refclk = 48000;
4815 }
4816
Ma Lingd4906092009-03-18 20:13:27 +08004817 /*
4818 * Returns a set of divisors for the desired target clock with the given
4819 * refclk, or FALSE. The returned values represent the clock equation:
4820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4821 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004822 limit = intel_limit(crtc, refclk);
Ma Lingd4906092009-03-18 20:13:27 +08004823 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004824 if (!ok) {
4825 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004826 return -EINVAL;
4827 }
4828
4829 /* Ensure that the cursor is valid for the new mode before changing... */
4830 intel_crtc_update_cursor(crtc, true);
4831
4832 if (is_lvds && dev_priv->lvds_downclock_avail) {
4833 has_reduced_clock = limit->find_pll(limit, crtc,
4834 dev_priv->lvds_downclock,
4835 refclk,
4836 &reduced_clock);
4837 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4838 /*
4839 * If the different P is found, it means that we can't
4840 * switch the display clock by using the FP0/FP1.
4841 * In such case we will disable the LVDS downclock
4842 * feature.
4843 */
4844 DRM_DEBUG_KMS("Different P is found for "
4845 "LVDS clock/downclock\n");
4846 has_reduced_clock = 0;
4847 }
4848 }
4849 /* SDVO TV has fixed PLL values depend on its clock range,
4850 this mirrors vbios setting. */
4851 if (is_sdvo && is_tv) {
4852 if (adjusted_mode->clock >= 100000
4853 && adjusted_mode->clock < 140500) {
4854 clock.p1 = 2;
4855 clock.p2 = 10;
4856 clock.n = 3;
4857 clock.m1 = 16;
4858 clock.m2 = 8;
4859 } else if (adjusted_mode->clock >= 140500
4860 && adjusted_mode->clock <= 200000) {
4861 clock.p1 = 1;
4862 clock.p2 = 10;
4863 clock.n = 6;
4864 clock.m1 = 12;
4865 clock.m2 = 8;
4866 }
4867 }
4868
Eric Anholtf564048e2011-03-30 13:01:02 -07004869 if (IS_PINEVIEW(dev)) {
4870 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4871 if (has_reduced_clock)
4872 fp2 = (1 << reduced_clock.n) << 16 |
4873 reduced_clock.m1 << 8 | reduced_clock.m2;
4874 } else {
4875 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4876 if (has_reduced_clock)
4877 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4878 reduced_clock.m2;
4879 }
4880
Eric Anholt929c77f2011-03-30 13:01:04 -07004881 dpll = DPLL_VGA_MODE_DIS;
Eric Anholtf564048e2011-03-30 13:01:02 -07004882
4883 if (!IS_GEN2(dev)) {
4884 if (is_lvds)
4885 dpll |= DPLLB_MODE_LVDS;
4886 else
4887 dpll |= DPLLB_MODE_DAC_SERIAL;
4888 if (is_sdvo) {
4889 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4890 if (pixel_multiplier > 1) {
4891 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4892 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Eric Anholtf564048e2011-03-30 13:01:02 -07004893 }
4894 dpll |= DPLL_DVO_HIGH_SPEED;
4895 }
Eric Anholt929c77f2011-03-30 13:01:04 -07004896 if (is_dp)
Eric Anholtf564048e2011-03-30 13:01:02 -07004897 dpll |= DPLL_DVO_HIGH_SPEED;
4898
4899 /* compute bitmask from p1 value */
4900 if (IS_PINEVIEW(dev))
4901 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4902 else {
4903 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004904 if (IS_G4X(dev) && has_reduced_clock)
4905 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4906 }
4907 switch (clock.p2) {
4908 case 5:
4909 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4910 break;
4911 case 7:
4912 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4913 break;
4914 case 10:
4915 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4916 break;
4917 case 14:
4918 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4919 break;
4920 }
Eric Anholt929c77f2011-03-30 13:01:04 -07004921 if (INTEL_INFO(dev)->gen >= 4)
Eric Anholtf564048e2011-03-30 13:01:02 -07004922 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4923 } else {
4924 if (is_lvds) {
4925 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4926 } else {
4927 if (clock.p1 == 2)
4928 dpll |= PLL_P1_DIVIDE_BY_TWO;
4929 else
4930 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4931 if (clock.p2 == 4)
4932 dpll |= PLL_P2_DIVIDE_BY_4;
4933 }
4934 }
4935
4936 if (is_sdvo && is_tv)
4937 dpll |= PLL_REF_INPUT_TVCLKINBC;
4938 else if (is_tv)
4939 /* XXX: just matching BIOS for now */
4940 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4941 dpll |= 3;
4942 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4943 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4944 else
4945 dpll |= PLL_REF_INPUT_DREFCLK;
4946
4947 /* setup pipeconf */
4948 pipeconf = I915_READ(PIPECONF(pipe));
4949
4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
4953 /* Ironlake's plane is forced to pipe, bit 24 is to
4954 enable color space conversion */
Eric Anholt929c77f2011-03-30 13:01:04 -07004955 if (pipe == 0)
4956 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4957 else
4958 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004959
4960 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4961 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4962 * core speed.
4963 *
4964 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4965 * pipe == 0 check?
4966 */
4967 if (mode->clock >
4968 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4969 pipeconf |= PIPECONF_DOUBLE_WIDE;
4970 else
4971 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4972 }
4973
Eric Anholt929c77f2011-03-30 13:01:04 -07004974 dpll |= DPLL_VCO_ENABLE;
Eric Anholtf564048e2011-03-30 13:01:02 -07004975
4976 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4977 drm_mode_debug_printmodeline(mode);
4978
Eric Anholtfae14982011-03-30 13:01:09 -07004979 I915_WRITE(FP0(pipe), fp);
4980 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Eric Anholtf564048e2011-03-30 13:01:02 -07004981
Eric Anholtfae14982011-03-30 13:01:09 -07004982 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07004983 udelay(150);
Eric Anholtf564048e2011-03-30 13:01:02 -07004984
Eric Anholtf564048e2011-03-30 13:01:02 -07004985 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4986 * This is an exception to the general rule that mode_set doesn't turn
4987 * things on.
4988 */
4989 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07004990 temp = I915_READ(LVDS);
Eric Anholtf564048e2011-03-30 13:01:02 -07004991 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4992 if (pipe == 1) {
Eric Anholt929c77f2011-03-30 13:01:04 -07004993 temp |= LVDS_PIPEB_SELECT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004994 } else {
Eric Anholt929c77f2011-03-30 13:01:04 -07004995 temp &= ~LVDS_PIPEB_SELECT;
Eric Anholtf564048e2011-03-30 13:01:02 -07004996 }
4997 /* set the corresponsding LVDS_BORDER bit */
4998 temp |= dev_priv->lvds_border_bits;
4999 /* Set the B0-B3 data pairs corresponding to whether we're going to
5000 * set the DPLLs for dual-channel mode or not.
5001 */
5002 if (clock.p2 == 7)
5003 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5004 else
5005 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5006
5007 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5008 * appropriately here, but we need to look more thoroughly into how
5009 * panels behave in the two modes.
5010 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005011 /* set the dithering flag on LVDS as needed */
5012 if (INTEL_INFO(dev)->gen >= 4) {
Eric Anholtf564048e2011-03-30 13:01:02 -07005013 if (dev_priv->lvds_dither)
5014 temp |= LVDS_ENABLE_DITHER;
5015 else
5016 temp &= ~LVDS_ENABLE_DITHER;
5017 }
5018 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5019 lvds_sync |= LVDS_HSYNC_POLARITY;
5020 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5021 lvds_sync |= LVDS_VSYNC_POLARITY;
5022 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5023 != lvds_sync) {
5024 char flags[2] = "-+";
5025 DRM_INFO("Changing LVDS panel from "
5026 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5027 flags[!(temp & LVDS_HSYNC_POLARITY)],
5028 flags[!(temp & LVDS_VSYNC_POLARITY)],
5029 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5030 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5031 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5032 temp |= lvds_sync;
5033 }
Eric Anholtfae14982011-03-30 13:01:09 -07005034 I915_WRITE(LVDS, temp);
Eric Anholtf564048e2011-03-30 13:01:02 -07005035 }
5036
Eric Anholt929c77f2011-03-30 13:01:04 -07005037 if (is_dp) {
Eric Anholtf564048e2011-03-30 13:01:02 -07005038 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholtf564048e2011-03-30 13:01:02 -07005039 }
5040
Eric Anholtfae14982011-03-30 13:01:09 -07005041 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf564048e2011-03-30 13:01:02 -07005042
Eric Anholtc713bb02011-03-30 13:01:05 -07005043 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07005044 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07005045 udelay(150);
Eric Anholtf564048e2011-03-30 13:01:02 -07005046
Eric Anholtc713bb02011-03-30 13:01:05 -07005047 if (INTEL_INFO(dev)->gen >= 4) {
5048 temp = 0;
5049 if (is_sdvo) {
5050 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5051 if (temp > 1)
5052 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5053 else
5054 temp = 0;
Eric Anholtf564048e2011-03-30 13:01:02 -07005055 }
Eric Anholtc713bb02011-03-30 13:01:05 -07005056 I915_WRITE(DPLL_MD(pipe), temp);
5057 } else {
5058 /* The pixel multiplier can only be updated once the
5059 * DPLL is enabled and the clocks are stable.
5060 *
5061 * So write it again.
5062 */
Eric Anholtfae14982011-03-30 13:01:09 -07005063 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf564048e2011-03-30 13:01:02 -07005064 }
5065
5066 intel_crtc->lowfreq_avail = false;
5067 if (is_lvds && has_reduced_clock && i915_powersave) {
Eric Anholtfae14982011-03-30 13:01:09 -07005068 I915_WRITE(FP1(pipe), fp2);
Eric Anholtf564048e2011-03-30 13:01:02 -07005069 intel_crtc->lowfreq_avail = true;
5070 if (HAS_PIPE_CXSR(dev)) {
5071 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5072 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5073 }
5074 } else {
Eric Anholtfae14982011-03-30 13:01:09 -07005075 I915_WRITE(FP1(pipe), fp);
Eric Anholtf564048e2011-03-30 13:01:02 -07005076 if (HAS_PIPE_CXSR(dev)) {
5077 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5078 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5079 }
5080 }
5081
5082 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5083 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5084 /* the chip adds 2 halflines automatically */
5085 adjusted_mode->crtc_vdisplay -= 1;
5086 adjusted_mode->crtc_vtotal -= 1;
5087 adjusted_mode->crtc_vblank_start -= 1;
5088 adjusted_mode->crtc_vblank_end -= 1;
5089 adjusted_mode->crtc_vsync_end -= 1;
5090 adjusted_mode->crtc_vsync_start -= 1;
5091 } else
5092 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5093
5094 I915_WRITE(HTOTAL(pipe),
5095 (adjusted_mode->crtc_hdisplay - 1) |
5096 ((adjusted_mode->crtc_htotal - 1) << 16));
5097 I915_WRITE(HBLANK(pipe),
5098 (adjusted_mode->crtc_hblank_start - 1) |
5099 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5100 I915_WRITE(HSYNC(pipe),
5101 (adjusted_mode->crtc_hsync_start - 1) |
5102 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5103
5104 I915_WRITE(VTOTAL(pipe),
5105 (adjusted_mode->crtc_vdisplay - 1) |
5106 ((adjusted_mode->crtc_vtotal - 1) << 16));
5107 I915_WRITE(VBLANK(pipe),
5108 (adjusted_mode->crtc_vblank_start - 1) |
5109 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5110 I915_WRITE(VSYNC(pipe),
5111 (adjusted_mode->crtc_vsync_start - 1) |
5112 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5113
5114 /* pipesrc and dspsize control the size that is scaled from,
5115 * which should always be the user's requested size.
5116 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005117 I915_WRITE(DSPSIZE(plane),
5118 ((mode->vdisplay - 1) << 16) |
5119 (mode->hdisplay - 1));
5120 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07005121 I915_WRITE(PIPESRC(pipe),
5122 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5123
Eric Anholtf564048e2011-03-30 13:01:02 -07005124 I915_WRITE(PIPECONF(pipe), pipeconf);
5125 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07005126 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07005127
5128 intel_wait_for_vblank(dev, pipe);
5129
Eric Anholtf564048e2011-03-30 13:01:02 -07005130 I915_WRITE(DSPCNTR(plane), dspcntr);
5131 POSTING_READ(DSPCNTR(plane));
Keith Packard284d9522011-06-06 17:12:49 -07005132 intel_enable_plane(dev_priv, plane, pipe);
Eric Anholtf564048e2011-03-30 13:01:02 -07005133
5134 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5135
5136 intel_update_watermarks(dev);
5137
Eric Anholtf564048e2011-03-30 13:01:02 -07005138 return ret;
5139}
5140
Keith Packard9fb526d2011-09-26 22:24:57 -07005141/*
5142 * Initialize reference clocks when the driver loads
5143 */
5144void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07005145{
5146 struct drm_i915_private *dev_priv = dev->dev_private;
5147 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005148 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005149 u32 temp;
5150 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005151 bool has_cpu_edp = false;
5152 bool has_pch_edp = false;
5153 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07005154 bool has_ck505 = false;
5155 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005156
5157 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07005158 list_for_each_entry(encoder, &mode_config->encoder_list,
5159 base.head) {
5160 switch (encoder->type) {
5161 case INTEL_OUTPUT_LVDS:
5162 has_panel = true;
5163 has_lvds = true;
5164 break;
5165 case INTEL_OUTPUT_EDP:
5166 has_panel = true;
5167 if (intel_encoder_is_pch_edp(&encoder->base))
5168 has_pch_edp = true;
5169 else
5170 has_cpu_edp = true;
5171 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005172 }
5173 }
5174
Keith Packard99eb6a02011-09-26 14:29:12 -07005175 if (HAS_PCH_IBX(dev)) {
5176 has_ck505 = dev_priv->display_clock_mode;
5177 can_ssc = has_ck505;
5178 } else {
5179 has_ck505 = false;
5180 can_ssc = true;
5181 }
5182
5183 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5184 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5185 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005186
5187 /* Ironlake: try to setup display ref clock before DPLL
5188 * enabling. This is only under driver's control after
5189 * PCH B stepping, previous chipset stepping should be
5190 * ignoring this setting.
5191 */
5192 temp = I915_READ(PCH_DREF_CONTROL);
5193 /* Always enable nonspread source */
5194 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005195
Keith Packard99eb6a02011-09-26 14:29:12 -07005196 if (has_ck505)
5197 temp |= DREF_NONSPREAD_CK505_ENABLE;
5198 else
5199 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005200
Keith Packard199e5d72011-09-22 12:01:57 -07005201 if (has_panel) {
5202 temp &= ~DREF_SSC_SOURCE_MASK;
5203 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005204
Keith Packard199e5d72011-09-22 12:01:57 -07005205 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005206 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005207 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07005208 temp |= DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005209 }
Keith Packard199e5d72011-09-22 12:01:57 -07005210
5211 /* Get SSC going before enabling the outputs */
5212 I915_WRITE(PCH_DREF_CONTROL, temp);
5213 POSTING_READ(PCH_DREF_CONTROL);
5214 udelay(200);
5215
Jesse Barnes13d83a62011-08-03 12:59:20 -07005216 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5217
5218 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005219 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005220 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005221 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07005222 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005223 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005224 else
5225 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005226 } else
5227 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5228
5229 I915_WRITE(PCH_DREF_CONTROL, temp);
5230 POSTING_READ(PCH_DREF_CONTROL);
5231 udelay(200);
5232 } else {
5233 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5234
5235 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5236
5237 /* Turn off CPU output */
5238 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5239
5240 I915_WRITE(PCH_DREF_CONTROL, temp);
5241 POSTING_READ(PCH_DREF_CONTROL);
5242 udelay(200);
5243
5244 /* Turn off the SSC source */
5245 temp &= ~DREF_SSC_SOURCE_MASK;
5246 temp |= DREF_SSC_SOURCE_DISABLE;
5247
5248 /* Turn off SSC1 */
5249 temp &= ~ DREF_SSC1_ENABLE;
5250
Jesse Barnes13d83a62011-08-03 12:59:20 -07005251 I915_WRITE(PCH_DREF_CONTROL, temp);
5252 POSTING_READ(PCH_DREF_CONTROL);
5253 udelay(200);
5254 }
5255}
5256
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005257static int ironlake_get_refclk(struct drm_crtc *crtc)
5258{
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_encoder *encoder;
5262 struct drm_mode_config *mode_config = &dev->mode_config;
5263 struct intel_encoder *edp_encoder = NULL;
5264 int num_connectors = 0;
5265 bool is_lvds = false;
5266
5267 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5268 if (encoder->base.crtc != crtc)
5269 continue;
5270
5271 switch (encoder->type) {
5272 case INTEL_OUTPUT_LVDS:
5273 is_lvds = true;
5274 break;
5275 case INTEL_OUTPUT_EDP:
5276 edp_encoder = encoder;
5277 break;
5278 }
5279 num_connectors++;
5280 }
5281
5282 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5283 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5284 dev_priv->lvds_ssc_freq);
5285 return dev_priv->lvds_ssc_freq * 1000;
5286 }
5287
5288 return 120000;
5289}
5290
Eric Anholtf564048e2011-03-30 13:01:02 -07005291static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5292 struct drm_display_mode *mode,
5293 struct drm_display_mode *adjusted_mode,
5294 int x, int y,
5295 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005296{
5297 struct drm_device *dev = crtc->dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5300 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005301 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08005302 int refclk, num_connectors = 0;
5303 intel_clock_t clock, reduced_clock;
5304 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Eric Anholta07d6782011-03-30 13:01:08 -07005305 bool ok, has_reduced_clock = false, is_sdvo = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005306 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5307 struct intel_encoder *has_edp_encoder = NULL;
5308 struct drm_mode_config *mode_config = &dev->mode_config;
5309 struct intel_encoder *encoder;
5310 const intel_limit_t *limit;
5311 int ret;
5312 struct fdi_m_n m_n = {0};
Eric Anholtfae14982011-03-30 13:01:09 -07005313 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08005314 u32 lvds_sync = 0;
Jesse Barnes5a354202011-06-24 12:19:22 -07005315 int target_clock, pixel_multiplier, lane, link_bw, factor;
5316 unsigned int pipe_bpp;
5317 bool dither;
Jesse Barnes79e53942008-11-07 14:24:08 -08005318
Jesse Barnes79e53942008-11-07 14:24:08 -08005319 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5320 if (encoder->base.crtc != crtc)
5321 continue;
5322
5323 switch (encoder->type) {
5324 case INTEL_OUTPUT_LVDS:
5325 is_lvds = true;
5326 break;
5327 case INTEL_OUTPUT_SDVO:
5328 case INTEL_OUTPUT_HDMI:
5329 is_sdvo = true;
5330 if (encoder->needs_tv_clock)
5331 is_tv = true;
5332 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005333 case INTEL_OUTPUT_TVOUT:
5334 is_tv = true;
5335 break;
5336 case INTEL_OUTPUT_ANALOG:
5337 is_crt = true;
5338 break;
5339 case INTEL_OUTPUT_DISPLAYPORT:
5340 is_dp = true;
5341 break;
5342 case INTEL_OUTPUT_EDP:
5343 has_edp_encoder = encoder;
5344 break;
5345 }
5346
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005347 num_connectors++;
5348 }
5349
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005350 refclk = ironlake_get_refclk(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005351
5352 /*
5353 * Returns a set of divisors for the desired target clock with the given
5354 * refclk, or FALSE. The returned values represent the clock equation:
5355 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5356 */
5357 limit = intel_limit(crtc, refclk);
5358 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5359 if (!ok) {
5360 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005361 return -EINVAL;
5362 }
5363
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005364 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005365 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005366
Zhao Yakuiddc90032010-01-06 22:05:56 +08005367 if (is_lvds && dev_priv->lvds_downclock_avail) {
5368 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01005369 dev_priv->lvds_downclock,
5370 refclk,
5371 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00005372 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5373 /*
5374 * If the different P is found, it means that we can't
5375 * switch the display clock by using the FP0/FP1.
5376 * In such case we will disable the LVDS downclock
5377 * feature.
5378 */
5379 DRM_DEBUG_KMS("Different P is found for "
Chris Wilson5eddb702010-09-11 13:48:45 +01005380 "LVDS clock/downclock\n");
Zhao Yakui18f9ed12009-11-20 03:24:16 +00005381 has_reduced_clock = 0;
5382 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005383 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005384 /* SDVO TV has fixed PLL values depend on its clock range,
5385 this mirrors vbios setting. */
5386 if (is_sdvo && is_tv) {
5387 if (adjusted_mode->clock >= 100000
Chris Wilson5eddb702010-09-11 13:48:45 +01005388 && adjusted_mode->clock < 140500) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005389 clock.p1 = 2;
5390 clock.p2 = 10;
5391 clock.n = 3;
5392 clock.m1 = 16;
5393 clock.m2 = 8;
5394 } else if (adjusted_mode->clock >= 140500
Chris Wilson5eddb702010-09-11 13:48:45 +01005395 && adjusted_mode->clock <= 200000) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005396 clock.p1 = 1;
5397 clock.p2 = 10;
5398 clock.n = 6;
5399 clock.m1 = 12;
5400 clock.m2 = 8;
5401 }
5402 }
5403
Zhenyu Wang2c072452009-06-05 15:38:42 +08005404 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07005405 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5406 lane = 0;
5407 /* CPU eDP doesn't require FDI link, so just set DP M/N
5408 according to current link config */
5409 if (has_edp_encoder &&
5410 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5411 target_clock = mode->clock;
5412 intel_edp_link_config(has_edp_encoder,
5413 &lane, &link_bw);
5414 } else {
5415 /* [e]DP over FDI requires target mode clock
5416 instead of link clock */
5417 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005418 target_clock = mode->clock;
Eric Anholt8febb292011-03-30 13:01:07 -07005419 else
5420 target_clock = adjusted_mode->clock;
Chris Wilson021357a2010-09-07 20:54:59 +01005421
Eric Anholt8febb292011-03-30 13:01:07 -07005422 /* FDI is a binary signal running at ~2.7GHz, encoding
5423 * each output octet as 10 bits. The actual frequency
5424 * is stored as a divider into a 100MHz clock, and the
5425 * mode pixel clock is stored in units of 1KHz.
5426 * Hence the bw of each lane in terms of the mode signal
5427 * is:
5428 */
5429 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005430 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08005431
Eric Anholt8febb292011-03-30 13:01:07 -07005432 /* determine panel color depth */
5433 temp = I915_READ(PIPECONF(pipe));
5434 temp &= ~PIPE_BPC_MASK;
Jesse Barnes5a354202011-06-24 12:19:22 -07005435 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5436 switch (pipe_bpp) {
5437 case 18:
5438 temp |= PIPE_6BPC;
5439 break;
5440 case 24:
Eric Anholt8febb292011-03-30 13:01:07 -07005441 temp |= PIPE_8BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005442 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07005443 case 30:
5444 temp |= PIPE_10BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005445 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07005446 case 36:
5447 temp |= PIPE_12BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005448 break;
5449 default:
Jesse Barnes62ac41a2011-07-28 12:55:14 -07005450 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5451 pipe_bpp);
Jesse Barnes5a354202011-06-24 12:19:22 -07005452 temp |= PIPE_8BPC;
5453 pipe_bpp = 24;
5454 break;
Eric Anholt8febb292011-03-30 13:01:07 -07005455 }
5456
Jesse Barnes5a354202011-06-24 12:19:22 -07005457 intel_crtc->bpp = pipe_bpp;
5458 I915_WRITE(PIPECONF(pipe), temp);
5459
Eric Anholt8febb292011-03-30 13:01:07 -07005460 if (!lane) {
5461 /*
5462 * Account for spread spectrum to avoid
5463 * oversubscribing the link. Max center spread
5464 * is 2.5%; use 5% for safety's sake.
5465 */
Jesse Barnes5a354202011-06-24 12:19:22 -07005466 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
Eric Anholt8febb292011-03-30 13:01:07 -07005467 lane = bps / (link_bw * 8) + 1;
5468 }
5469
5470 intel_crtc->fdi_lanes = lane;
5471
5472 if (pixel_multiplier > 1)
5473 link_bw *= pixel_multiplier;
Jesse Barnes5a354202011-06-24 12:19:22 -07005474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5475 &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07005476
Eric Anholta07d6782011-03-30 13:01:08 -07005477 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5478 if (has_reduced_clock)
5479 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5480 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08005481
Chris Wilsonc1858122010-12-03 21:35:48 +00005482 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005483 factor = 21;
5484 if (is_lvds) {
5485 if ((intel_panel_use_ssc(dev_priv) &&
5486 dev_priv->lvds_ssc_freq == 100) ||
5487 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5488 factor = 25;
5489 } else if (is_sdvo && is_tv)
5490 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005491
Jesse Barnescb0e0932011-07-28 14:50:30 -07005492 if (clock.m < factor * clock.n)
Eric Anholt8febb292011-03-30 13:01:07 -07005493 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005494
Chris Wilson5eddb702010-09-11 13:48:45 +01005495 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005496
Eric Anholta07d6782011-03-30 13:01:08 -07005497 if (is_lvds)
5498 dpll |= DPLLB_MODE_LVDS;
5499 else
5500 dpll |= DPLLB_MODE_DAC_SERIAL;
5501 if (is_sdvo) {
5502 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5503 if (pixel_multiplier > 1) {
5504 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08005505 }
Eric Anholta07d6782011-03-30 13:01:08 -07005506 dpll |= DPLL_DVO_HIGH_SPEED;
5507 }
5508 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5509 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005510
Eric Anholta07d6782011-03-30 13:01:08 -07005511 /* compute bitmask from p1 value */
5512 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5513 /* also FPA1 */
5514 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5515
5516 switch (clock.p2) {
5517 case 5:
5518 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5519 break;
5520 case 7:
5521 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5522 break;
5523 case 10:
5524 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5525 break;
5526 case 14:
5527 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5528 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005529 }
5530
5531 if (is_sdvo && is_tv)
5532 dpll |= PLL_REF_INPUT_TVCLKINBC;
5533 else if (is_tv)
5534 /* XXX: just matching BIOS for now */
5535 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5536 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00005537 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Jesse Barnes79e53942008-11-07 14:24:08 -08005538 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5539 else
5540 dpll |= PLL_REF_INPUT_DREFCLK;
5541
5542 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01005543 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005544
5545 /* Set up the display plane register */
5546 dspcntr = DISPPLANE_GAMMA_ENABLE;
5547
Zhao Yakui28c97732009-10-09 11:39:41 +08005548 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08005549 drm_mode_debug_printmodeline(mode);
5550
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005551 /* PCH eDP needs FDI, but CPU eDP does not */
5552 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Eric Anholtfae14982011-03-30 13:01:09 -07005553 I915_WRITE(PCH_FP0(pipe), fp);
5554 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01005555
Eric Anholtfae14982011-03-30 13:01:09 -07005556 POSTING_READ(PCH_DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005557 udelay(150);
5558 }
5559
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005560 /* enable transcoder DPLL */
5561 if (HAS_PCH_CPT(dev)) {
5562 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005563 switch (pipe) {
5564 case 0:
Chris Wilson5eddb702010-09-11 13:48:45 +01005565 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005566 break;
5567 case 1:
Chris Wilson5eddb702010-09-11 13:48:45 +01005568 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005569 break;
5570 case 2:
5571 /* FIXME: manage transcoder PLLs? */
5572 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5573 break;
5574 default:
5575 BUG();
5576 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005577 I915_WRITE(PCH_DPLL_SEL, temp);
Chris Wilson5eddb702010-09-11 13:48:45 +01005578
5579 POSTING_READ(PCH_DPLL_SEL);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005580 udelay(150);
5581 }
5582
Jesse Barnes79e53942008-11-07 14:24:08 -08005583 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5584 * This is an exception to the general rule that mode_set doesn't turn
5585 * things on.
5586 */
5587 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005588 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01005589 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005590 if (pipe == 1) {
5591 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01005592 temp |= PORT_TRANS_B_SEL_CPT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005593 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005594 temp |= LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005595 } else {
5596 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01005597 temp &= ~PORT_TRANS_SEL_MASK;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005598 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005599 temp &= ~LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08005600 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005601 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01005602 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08005603 /* Set the B0-B3 data pairs corresponding to whether we're going to
5604 * set the DPLLs for dual-channel mode or not.
5605 */
5606 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01005607 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08005608 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005609 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08005610
5611 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5612 * appropriately here, but we need to look more thoroughly into how
5613 * panels behave in the two modes.
5614 */
Bryan Freedaa9b5002011-01-12 13:43:19 -08005615 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5616 lvds_sync |= LVDS_HSYNC_POLARITY;
5617 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5618 lvds_sync |= LVDS_VSYNC_POLARITY;
5619 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5620 != lvds_sync) {
5621 char flags[2] = "-+";
5622 DRM_INFO("Changing LVDS panel from "
5623 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5624 flags[!(temp & LVDS_HSYNC_POLARITY)],
5625 flags[!(temp & LVDS_VSYNC_POLARITY)],
5626 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5627 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5628 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5629 temp |= lvds_sync;
5630 }
Eric Anholtfae14982011-03-30 13:01:09 -07005631 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005632 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005633
Eric Anholt8febb292011-03-30 13:01:07 -07005634 pipeconf &= ~PIPECONF_DITHER_EN;
5635 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
Jesse Barnes5a354202011-06-24 12:19:22 -07005636 if ((is_lvds && dev_priv->lvds_dither) || dither) {
Eric Anholt8febb292011-03-30 13:01:07 -07005637 pipeconf |= PIPECONF_DITHER_EN;
5638 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
Jesse Barnes434ed092010-09-07 14:48:06 -07005639 }
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005640 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005641 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07005642 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005643 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005644 I915_WRITE(TRANSDATA_M1(pipe), 0);
5645 I915_WRITE(TRANSDATA_N1(pipe), 0);
5646 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5647 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005648 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005649
Eric Anholt8febb292011-03-30 13:01:07 -07005650 if (!has_edp_encoder ||
5651 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Eric Anholtfae14982011-03-30 13:01:09 -07005652 I915_WRITE(PCH_DPLL(pipe), dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005653
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005654 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07005655 POSTING_READ(PCH_DPLL(pipe));
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005656 udelay(150);
5657
Eric Anholt8febb292011-03-30 13:01:07 -07005658 /* The pixel multiplier can only be updated once the
5659 * DPLL is enabled and the clocks are stable.
5660 *
5661 * So write it again.
5662 */
Eric Anholtfae14982011-03-30 13:01:09 -07005663 I915_WRITE(PCH_DPLL(pipe), dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005664 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005665
Chris Wilson5eddb702010-09-11 13:48:45 +01005666 intel_crtc->lowfreq_avail = false;
Jesse Barnes652c3932009-08-17 13:31:43 -07005667 if (is_lvds && has_reduced_clock && i915_powersave) {
Eric Anholtfae14982011-03-30 13:01:09 -07005668 I915_WRITE(PCH_FP1(pipe), fp2);
Jesse Barnes652c3932009-08-17 13:31:43 -07005669 intel_crtc->lowfreq_avail = true;
5670 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005671 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005672 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5673 }
5674 } else {
Eric Anholtfae14982011-03-30 13:01:09 -07005675 I915_WRITE(PCH_FP1(pipe), fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005676 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005677 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005678 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5679 }
5680 }
5681
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005682 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5683 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5684 /* the chip adds 2 halflines automatically */
5685 adjusted_mode->crtc_vdisplay -= 1;
5686 adjusted_mode->crtc_vtotal -= 1;
5687 adjusted_mode->crtc_vblank_start -= 1;
5688 adjusted_mode->crtc_vblank_end -= 1;
5689 adjusted_mode->crtc_vsync_end -= 1;
5690 adjusted_mode->crtc_vsync_start -= 1;
5691 } else
5692 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5693
Chris Wilson5eddb702010-09-11 13:48:45 +01005694 I915_WRITE(HTOTAL(pipe),
5695 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005696 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005697 I915_WRITE(HBLANK(pipe),
5698 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005699 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005700 I915_WRITE(HSYNC(pipe),
5701 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005702 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005703
5704 I915_WRITE(VTOTAL(pipe),
5705 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005706 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005707 I915_WRITE(VBLANK(pipe),
5708 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005709 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005710 I915_WRITE(VSYNC(pipe),
5711 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005712 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005713
Eric Anholt8febb292011-03-30 13:01:07 -07005714 /* pipesrc controls the size that is scaled from, which should
5715 * always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08005716 */
Chris Wilson5eddb702010-09-11 13:48:45 +01005717 I915_WRITE(PIPESRC(pipe),
5718 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08005719
Eric Anholt8febb292011-03-30 13:01:07 -07005720 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5721 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5722 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5723 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005724
Eric Anholt8febb292011-03-30 13:01:07 -07005725 if (has_edp_encoder &&
5726 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5727 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005728 }
5729
Chris Wilson5eddb702010-09-11 13:48:45 +01005730 I915_WRITE(PIPECONF(pipe), pipeconf);
5731 POSTING_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005732
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005733 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005734
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01005735 if (IS_GEN5(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08005736 /* enable address swizzle for tiling buffer */
5737 temp = I915_READ(DISP_ARB_CTL);
5738 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5739 }
5740
Chris Wilson5eddb702010-09-11 13:48:45 +01005741 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005742 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005743
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005744 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005745
5746 intel_update_watermarks(dev);
5747
Chris Wilson1f803ee2009-06-06 09:45:59 +01005748 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005749}
5750
Eric Anholtf564048e2011-03-30 13:01:02 -07005751static int intel_crtc_mode_set(struct drm_crtc *crtc,
5752 struct drm_display_mode *mode,
5753 struct drm_display_mode *adjusted_mode,
5754 int x, int y,
5755 struct drm_framebuffer *old_fb)
5756{
5757 struct drm_device *dev = crtc->dev;
5758 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07005759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005761 int ret;
5762
Eric Anholt0b701d22011-03-30 13:01:03 -07005763 drm_vblank_pre_modeset(dev, pipe);
5764
Eric Anholtf564048e2011-03-30 13:01:02 -07005765 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5766 x, y, old_fb);
5767
Jesse Barnes79e53942008-11-07 14:24:08 -08005768 drm_vblank_post_modeset(dev, pipe);
5769
Keith Packard120eced2011-07-27 01:21:40 -07005770 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5771
Jesse Barnes79e53942008-11-07 14:24:08 -08005772 return ret;
5773}
5774
Wu Fengguange0dac652011-09-05 14:25:34 +08005775static void g4x_write_eld(struct drm_connector *connector,
5776 struct drm_crtc *crtc)
5777{
5778 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5779 uint8_t *eld = connector->eld;
5780 uint32_t eldv;
5781 uint32_t len;
5782 uint32_t i;
5783
5784 i = I915_READ(G4X_AUD_VID_DID);
5785
5786 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5787 eldv = G4X_ELDV_DEVCL_DEVBLC;
5788 else
5789 eldv = G4X_ELDV_DEVCTG;
5790
5791 i = I915_READ(G4X_AUD_CNTL_ST);
5792 i &= ~(eldv | G4X_ELD_ADDR);
5793 len = (i >> 9) & 0x1f; /* ELD buffer size */
5794 I915_WRITE(G4X_AUD_CNTL_ST, i);
5795
5796 if (!eld[0])
5797 return;
5798
5799 len = min_t(uint8_t, eld[2], len);
5800 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5801 for (i = 0; i < len; i++)
5802 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5803
5804 i = I915_READ(G4X_AUD_CNTL_ST);
5805 i |= eldv;
5806 I915_WRITE(G4X_AUD_CNTL_ST, i);
5807}
5808
5809static void ironlake_write_eld(struct drm_connector *connector,
5810 struct drm_crtc *crtc)
5811{
5812 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5813 uint8_t *eld = connector->eld;
5814 uint32_t eldv;
5815 uint32_t i;
5816 int len;
5817 int hdmiw_hdmiedid;
5818 int aud_cntl_st;
5819 int aud_cntrl_st2;
5820
5821 if (IS_IVYBRIDGE(connector->dev)) {
5822 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5823 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5824 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5825 } else {
5826 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5827 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5828 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5829 }
5830
5831 i = to_intel_crtc(crtc)->pipe;
5832 hdmiw_hdmiedid += i * 0x100;
5833 aud_cntl_st += i * 0x100;
5834
5835 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5836
5837 i = I915_READ(aud_cntl_st);
5838 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5839 if (!i) {
5840 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5841 /* operate blindly on all ports */
5842 eldv = GEN5_ELD_VALIDB;
5843 eldv |= GEN5_ELD_VALIDB << 4;
5844 eldv |= GEN5_ELD_VALIDB << 8;
5845 } else {
5846 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5847 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5848 }
5849
5850 i = I915_READ(aud_cntrl_st2);
5851 i &= ~eldv;
5852 I915_WRITE(aud_cntrl_st2, i);
5853
5854 if (!eld[0])
5855 return;
5856
5857 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5858 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5859 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5860 }
5861
5862 i = I915_READ(aud_cntl_st);
5863 i &= ~GEN5_ELD_ADDRESS;
5864 I915_WRITE(aud_cntl_st, i);
5865
5866 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5867 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5868 for (i = 0; i < len; i++)
5869 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5870
5871 i = I915_READ(aud_cntrl_st2);
5872 i |= eldv;
5873 I915_WRITE(aud_cntrl_st2, i);
5874}
5875
5876void intel_write_eld(struct drm_encoder *encoder,
5877 struct drm_display_mode *mode)
5878{
5879 struct drm_crtc *crtc = encoder->crtc;
5880 struct drm_connector *connector;
5881 struct drm_device *dev = encoder->dev;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883
5884 connector = drm_select_eld(encoder, mode);
5885 if (!connector)
5886 return;
5887
5888 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5889 connector->base.id,
5890 drm_get_connector_name(connector),
5891 connector->encoder->base.id,
5892 drm_get_encoder_name(connector->encoder));
5893
5894 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5895
5896 if (dev_priv->display.write_eld)
5897 dev_priv->display.write_eld(connector, crtc);
5898}
5899
Jesse Barnes79e53942008-11-07 14:24:08 -08005900/** Loads the palette/gamma unit for the CRTC with the prepared values */
5901void intel_crtc_load_lut(struct drm_crtc *crtc)
5902{
5903 struct drm_device *dev = crtc->dev;
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005906 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005907 int i;
5908
5909 /* The clocks have to be on to load the palette. */
5910 if (!crtc->enabled)
5911 return;
5912
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005913 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005914 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005915 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005916
Jesse Barnes79e53942008-11-07 14:24:08 -08005917 for (i = 0; i < 256; i++) {
5918 I915_WRITE(palreg + 4 * i,
5919 (intel_crtc->lut_r[i] << 16) |
5920 (intel_crtc->lut_g[i] << 8) |
5921 intel_crtc->lut_b[i]);
5922 }
5923}
5924
Chris Wilson560b85b2010-08-07 11:01:38 +01005925static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5926{
5927 struct drm_device *dev = crtc->dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5930 bool visible = base != 0;
5931 u32 cntl;
5932
5933 if (intel_crtc->cursor_visible == visible)
5934 return;
5935
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005936 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005937 if (visible) {
5938 /* On these chipsets we can only modify the base whilst
5939 * the cursor is disabled.
5940 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005941 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005942
5943 cntl &= ~(CURSOR_FORMAT_MASK);
5944 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5945 cntl |= CURSOR_ENABLE |
5946 CURSOR_GAMMA_ENABLE |
5947 CURSOR_FORMAT_ARGB;
5948 } else
5949 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005950 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005951
5952 intel_crtc->cursor_visible = visible;
5953}
5954
5955static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5956{
5957 struct drm_device *dev = crtc->dev;
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960 int pipe = intel_crtc->pipe;
5961 bool visible = base != 0;
5962
5963 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005964 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005965 if (base) {
5966 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5967 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5968 cntl |= pipe << 28; /* Connect to correct pipe */
5969 } else {
5970 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5971 cntl |= CURSOR_MODE_DISABLE;
5972 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005973 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005974
5975 intel_crtc->cursor_visible = visible;
5976 }
5977 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005978 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005979}
5980
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005981/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005982static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5983 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005984{
5985 struct drm_device *dev = crtc->dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
5989 int x = intel_crtc->cursor_x;
5990 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005991 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005992 bool visible;
5993
5994 pos = 0;
5995
Chris Wilson6b383a72010-09-13 13:54:26 +01005996 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005997 base = intel_crtc->cursor_addr;
5998 if (x > (int) crtc->fb->width)
5999 base = 0;
6000
6001 if (y > (int) crtc->fb->height)
6002 base = 0;
6003 } else
6004 base = 0;
6005
6006 if (x < 0) {
6007 if (x + intel_crtc->cursor_width < 0)
6008 base = 0;
6009
6010 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6011 x = -x;
6012 }
6013 pos |= x << CURSOR_X_SHIFT;
6014
6015 if (y < 0) {
6016 if (y + intel_crtc->cursor_height < 0)
6017 base = 0;
6018
6019 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6020 y = -y;
6021 }
6022 pos |= y << CURSOR_Y_SHIFT;
6023
6024 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006025 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006026 return;
6027
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006028 I915_WRITE(CURPOS(pipe), pos);
Chris Wilson560b85b2010-08-07 11:01:38 +01006029 if (IS_845G(dev) || IS_I865G(dev))
6030 i845_update_cursor(crtc, base);
6031 else
6032 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006033
6034 if (visible)
6035 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6036}
6037
Jesse Barnes79e53942008-11-07 14:24:08 -08006038static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006039 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006040 uint32_t handle,
6041 uint32_t width, uint32_t height)
6042{
6043 struct drm_device *dev = crtc->dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006046 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006047 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006048 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006049
Zhao Yakui28c97732009-10-09 11:39:41 +08006050 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08006051
6052 /* if we want to turn off the cursor ignore width and height */
6053 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006054 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006055 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006056 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006057 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006058 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006059 }
6060
6061 /* Currently we only support 64x64 cursors */
6062 if (width != 64 || height != 64) {
6063 DRM_ERROR("we currently only support 64x64 cursors\n");
6064 return -EINVAL;
6065 }
6066
Chris Wilson05394f32010-11-08 19:18:58 +00006067 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006068 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006069 return -ENOENT;
6070
Chris Wilson05394f32010-11-08 19:18:58 +00006071 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006072 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006073 ret = -ENOMEM;
6074 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006075 }
6076
Dave Airlie71acb5e2008-12-30 20:31:46 +10006077 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006078 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006079 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00006080 if (obj->tiling_mode) {
6081 DRM_ERROR("cursor cannot be tiled\n");
6082 ret = -EINVAL;
6083 goto fail_locked;
6084 }
6085
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006086 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006087 if (ret) {
6088 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006089 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006090 }
6091
Chris Wilsond9e86c02010-11-10 16:40:20 +00006092 ret = i915_gem_object_put_fence(obj);
6093 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006094 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006095 goto fail_unpin;
6096 }
6097
Chris Wilson05394f32010-11-08 19:18:58 +00006098 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006099 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006100 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006101 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006102 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6103 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006104 if (ret) {
6105 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006106 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006107 }
Chris Wilson05394f32010-11-08 19:18:58 +00006108 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006109 }
6110
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006111 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006112 I915_WRITE(CURSIZE, (height << 12) | width);
6113
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006114 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006115 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006116 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006117 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006118 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6119 } else
6120 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006121 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006122 }
Jesse Barnes80824002009-09-10 15:28:06 -07006123
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006124 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006125
6126 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006127 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006128 intel_crtc->cursor_width = width;
6129 intel_crtc->cursor_height = height;
6130
Chris Wilson6b383a72010-09-13 13:54:26 +01006131 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006132
Jesse Barnes79e53942008-11-07 14:24:08 -08006133 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006134fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006135 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006136fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006137 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006138fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006139 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006140 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006141}
6142
6143static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6144{
Jesse Barnes79e53942008-11-07 14:24:08 -08006145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006146
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006147 intel_crtc->cursor_x = x;
6148 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006149
Chris Wilson6b383a72010-09-13 13:54:26 +01006150 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08006151
6152 return 0;
6153}
6154
6155/** Sets the color ramps on behalf of RandR */
6156void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6157 u16 blue, int regno)
6158{
6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160
6161 intel_crtc->lut_r[regno] = red >> 8;
6162 intel_crtc->lut_g[regno] = green >> 8;
6163 intel_crtc->lut_b[regno] = blue >> 8;
6164}
6165
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006166void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6167 u16 *blue, int regno)
6168{
6169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6170
6171 *red = intel_crtc->lut_r[regno] << 8;
6172 *green = intel_crtc->lut_g[regno] << 8;
6173 *blue = intel_crtc->lut_b[regno] << 8;
6174}
6175
Jesse Barnes79e53942008-11-07 14:24:08 -08006176static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006177 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006178{
James Simmons72034252010-08-03 01:33:19 +01006179 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006181
James Simmons72034252010-08-03 01:33:19 +01006182 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006183 intel_crtc->lut_r[i] = red[i] >> 8;
6184 intel_crtc->lut_g[i] = green[i] >> 8;
6185 intel_crtc->lut_b[i] = blue[i] >> 8;
6186 }
6187
6188 intel_crtc_load_lut(crtc);
6189}
6190
6191/**
6192 * Get a pipe with a simple mode set on it for doing load-based monitor
6193 * detection.
6194 *
6195 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07006196 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08006197 *
Eric Anholtc751ce42010-03-25 11:48:48 -07006198 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08006199 * configured for it. In the future, it could choose to temporarily disable
6200 * some outputs to free up a pipe for its use.
6201 *
6202 * \return crtc, or NULL if no pipes are available.
6203 */
6204
6205/* VESA 640x480x72Hz mode to set on the pipe */
6206static struct drm_display_mode load_detect_mode = {
6207 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6208 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6209};
6210
Chris Wilsond2dff872011-04-19 08:36:26 +01006211static struct drm_framebuffer *
6212intel_framebuffer_create(struct drm_device *dev,
6213 struct drm_mode_fb_cmd *mode_cmd,
6214 struct drm_i915_gem_object *obj)
6215{
6216 struct intel_framebuffer *intel_fb;
6217 int ret;
6218
6219 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6220 if (!intel_fb) {
6221 drm_gem_object_unreference_unlocked(&obj->base);
6222 return ERR_PTR(-ENOMEM);
6223 }
6224
6225 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6226 if (ret) {
6227 drm_gem_object_unreference_unlocked(&obj->base);
6228 kfree(intel_fb);
6229 return ERR_PTR(ret);
6230 }
6231
6232 return &intel_fb->base;
6233}
6234
6235static u32
6236intel_framebuffer_pitch_for_width(int width, int bpp)
6237{
6238 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6239 return ALIGN(pitch, 64);
6240}
6241
6242static u32
6243intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6244{
6245 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6246 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6247}
6248
6249static struct drm_framebuffer *
6250intel_framebuffer_create_for_mode(struct drm_device *dev,
6251 struct drm_display_mode *mode,
6252 int depth, int bpp)
6253{
6254 struct drm_i915_gem_object *obj;
6255 struct drm_mode_fb_cmd mode_cmd;
6256
6257 obj = i915_gem_alloc_object(dev,
6258 intel_framebuffer_size_for_mode(mode, bpp));
6259 if (obj == NULL)
6260 return ERR_PTR(-ENOMEM);
6261
6262 mode_cmd.width = mode->hdisplay;
6263 mode_cmd.height = mode->vdisplay;
6264 mode_cmd.depth = depth;
6265 mode_cmd.bpp = bpp;
6266 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6267
6268 return intel_framebuffer_create(dev, &mode_cmd, obj);
6269}
6270
6271static struct drm_framebuffer *
6272mode_fits_in_fbdev(struct drm_device *dev,
6273 struct drm_display_mode *mode)
6274{
6275 struct drm_i915_private *dev_priv = dev->dev_private;
6276 struct drm_i915_gem_object *obj;
6277 struct drm_framebuffer *fb;
6278
6279 if (dev_priv->fbdev == NULL)
6280 return NULL;
6281
6282 obj = dev_priv->fbdev->ifb.obj;
6283 if (obj == NULL)
6284 return NULL;
6285
6286 fb = &dev_priv->fbdev->ifb.base;
6287 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6288 fb->bits_per_pixel))
6289 return NULL;
6290
6291 if (obj->base.size < mode->vdisplay * fb->pitch)
6292 return NULL;
6293
6294 return fb;
6295}
6296
Chris Wilson71731882011-04-19 23:10:58 +01006297bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6298 struct drm_connector *connector,
6299 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006300 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006301{
6302 struct intel_crtc *intel_crtc;
6303 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006304 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006305 struct drm_crtc *crtc = NULL;
6306 struct drm_device *dev = encoder->dev;
Chris Wilsond2dff872011-04-19 08:36:26 +01006307 struct drm_framebuffer *old_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006308 int i = -1;
6309
Chris Wilsond2dff872011-04-19 08:36:26 +01006310 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6311 connector->base.id, drm_get_connector_name(connector),
6312 encoder->base.id, drm_get_encoder_name(encoder));
6313
Jesse Barnes79e53942008-11-07 14:24:08 -08006314 /*
6315 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006316 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006317 * - if the connector already has an assigned crtc, use it (but make
6318 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006319 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006320 * - try to find the first unused crtc that can drive this connector,
6321 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006322 */
6323
6324 /* See if we already have a CRTC for this connector */
6325 if (encoder->crtc) {
6326 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006327
Jesse Barnes79e53942008-11-07 14:24:08 -08006328 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01006329 old->dpms_mode = intel_crtc->dpms_mode;
6330 old->load_detect_temp = false;
6331
6332 /* Make sure the crtc and connector are running */
Jesse Barnes79e53942008-11-07 14:24:08 -08006333 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
Chris Wilson64927112011-04-20 07:25:26 +01006334 struct drm_encoder_helper_funcs *encoder_funcs;
6335 struct drm_crtc_helper_funcs *crtc_funcs;
6336
Jesse Barnes79e53942008-11-07 14:24:08 -08006337 crtc_funcs = crtc->helper_private;
6338 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
Chris Wilson64927112011-04-20 07:25:26 +01006339
6340 encoder_funcs = encoder->helper_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006341 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6342 }
Chris Wilson8261b192011-04-19 23:18:09 +01006343
Chris Wilson71731882011-04-19 23:10:58 +01006344 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006345 }
6346
6347 /* Find an unused one (if possible) */
6348 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6349 i++;
6350 if (!(encoder->possible_crtcs & (1 << i)))
6351 continue;
6352 if (!possible_crtc->enabled) {
6353 crtc = possible_crtc;
6354 break;
6355 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006356 }
6357
6358 /*
6359 * If we didn't find an unused CRTC, don't use any.
6360 */
6361 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006362 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6363 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006364 }
6365
6366 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006367 connector->encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006368
6369 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01006370 old->dpms_mode = intel_crtc->dpms_mode;
6371 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006372 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006373
Chris Wilson64927112011-04-20 07:25:26 +01006374 if (!mode)
6375 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006376
Chris Wilsond2dff872011-04-19 08:36:26 +01006377 old_fb = crtc->fb;
6378
6379 /* We need a framebuffer large enough to accommodate all accesses
6380 * that the plane may generate whilst we perform load detection.
6381 * We can not rely on the fbcon either being present (we get called
6382 * during its initialisation to detect all boot displays, or it may
6383 * not even exist) or that it is large enough to satisfy the
6384 * requested mode.
6385 */
6386 crtc->fb = mode_fits_in_fbdev(dev, mode);
6387 if (crtc->fb == NULL) {
6388 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6389 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6390 old->release_fb = crtc->fb;
6391 } else
6392 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6393 if (IS_ERR(crtc->fb)) {
6394 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6395 crtc->fb = old_fb;
6396 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006397 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006398
6399 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006400 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006401 if (old->release_fb)
6402 old->release_fb->funcs->destroy(old->release_fb);
6403 crtc->fb = old_fb;
Chris Wilson64927112011-04-20 07:25:26 +01006404 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006405 }
Chris Wilson71731882011-04-19 23:10:58 +01006406
Jesse Barnes79e53942008-11-07 14:24:08 -08006407 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006408 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006409
Chris Wilson71731882011-04-19 23:10:58 +01006410 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006411}
6412
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006413void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
Chris Wilson8261b192011-04-19 23:18:09 +01006414 struct drm_connector *connector,
6415 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006416{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006417 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006418 struct drm_device *dev = encoder->dev;
6419 struct drm_crtc *crtc = encoder->crtc;
6420 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6421 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6422
Chris Wilsond2dff872011-04-19 08:36:26 +01006423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6424 connector->base.id, drm_get_connector_name(connector),
6425 encoder->base.id, drm_get_encoder_name(encoder));
6426
Chris Wilson8261b192011-04-19 23:18:09 +01006427 if (old->load_detect_temp) {
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006428 connector->encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006429 drm_helper_disable_unused_functions(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +01006430
6431 if (old->release_fb)
6432 old->release_fb->funcs->destroy(old->release_fb);
6433
Chris Wilson0622a532011-04-21 09:32:11 +01006434 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006435 }
6436
Eric Anholtc751ce42010-03-25 11:48:48 -07006437 /* Switch crtc and encoder back off if necessary */
Chris Wilson0622a532011-04-21 09:32:11 +01006438 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6439 encoder_funcs->dpms(encoder, old->dpms_mode);
Chris Wilson8261b192011-04-19 23:18:09 +01006440 crtc_funcs->dpms(crtc, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006441 }
6442}
6443
6444/* Returns the clock of the currently programmed mode of the given pipe. */
6445static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6446{
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006450 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006451 u32 fp;
6452 intel_clock_t clock;
6453
6454 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006455 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006456 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006457 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006458
6459 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006460 if (IS_PINEVIEW(dev)) {
6461 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6462 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006463 } else {
6464 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6465 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6466 }
6467
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006468 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006469 if (IS_PINEVIEW(dev))
6470 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6471 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006472 else
6473 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006474 DPLL_FPA01_P1_POST_DIV_SHIFT);
6475
6476 switch (dpll & DPLL_MODE_MASK) {
6477 case DPLLB_MODE_DAC_SERIAL:
6478 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6479 5 : 10;
6480 break;
6481 case DPLLB_MODE_LVDS:
6482 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6483 7 : 14;
6484 break;
6485 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006486 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006487 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6488 return 0;
6489 }
6490
6491 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08006492 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006493 } else {
6494 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6495
6496 if (is_lvds) {
6497 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6498 DPLL_FPA01_P1_POST_DIV_SHIFT);
6499 clock.p2 = 14;
6500
6501 if ((dpll & PLL_REF_INPUT_MASK) ==
6502 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6503 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08006504 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006505 } else
Shaohua Li21778322009-02-23 15:19:16 +08006506 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006507 } else {
6508 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6509 clock.p1 = 2;
6510 else {
6511 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6512 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6513 }
6514 if (dpll & PLL_P2_DIVIDE_BY_4)
6515 clock.p2 = 4;
6516 else
6517 clock.p2 = 2;
6518
Shaohua Li21778322009-02-23 15:19:16 +08006519 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006520 }
6521 }
6522
6523 /* XXX: It would be nice to validate the clocks, but we can't reuse
6524 * i830PllIsValid() because it relies on the xf86_config connector
6525 * configuration being accurate, which it isn't necessarily.
6526 */
6527
6528 return clock.dot;
6529}
6530
6531/** Returns the currently programmed mode of the given pipe. */
6532struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6533 struct drm_crtc *crtc)
6534{
Jesse Barnes548f2452011-02-17 10:40:53 -08006535 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537 int pipe = intel_crtc->pipe;
6538 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08006539 int htot = I915_READ(HTOTAL(pipe));
6540 int hsync = I915_READ(HSYNC(pipe));
6541 int vtot = I915_READ(VTOTAL(pipe));
6542 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006543
6544 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6545 if (!mode)
6546 return NULL;
6547
6548 mode->clock = intel_crtc_clock_get(dev, crtc);
6549 mode->hdisplay = (htot & 0xffff) + 1;
6550 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6551 mode->hsync_start = (hsync & 0xffff) + 1;
6552 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6553 mode->vdisplay = (vtot & 0xffff) + 1;
6554 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6555 mode->vsync_start = (vsync & 0xffff) + 1;
6556 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6557
6558 drm_mode_set_name(mode);
6559 drm_mode_set_crtcinfo(mode, 0);
6560
6561 return mode;
6562}
6563
Jesse Barnes652c3932009-08-17 13:31:43 -07006564#define GPU_IDLE_TIMEOUT 500 /* ms */
6565
6566/* When this timer fires, we've been idle for awhile */
6567static void intel_gpu_idle_timer(unsigned long arg)
6568{
6569 struct drm_device *dev = (struct drm_device *)arg;
6570 drm_i915_private_t *dev_priv = dev->dev_private;
6571
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006572 if (!list_empty(&dev_priv->mm.active_list)) {
6573 /* Still processing requests, so just re-arm the timer. */
6574 mod_timer(&dev_priv->idle_timer, jiffies +
6575 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6576 return;
6577 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006578
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006579 dev_priv->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07006580 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07006581}
6582
Jesse Barnes652c3932009-08-17 13:31:43 -07006583#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6584
6585static void intel_crtc_idle_timer(unsigned long arg)
6586{
6587 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6588 struct drm_crtc *crtc = &intel_crtc->base;
6589 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006590 struct intel_framebuffer *intel_fb;
6591
6592 intel_fb = to_intel_framebuffer(crtc->fb);
6593 if (intel_fb && intel_fb->obj->active) {
6594 /* The framebuffer is still being accessed by the GPU. */
6595 mod_timer(&intel_crtc->idle_timer, jiffies +
6596 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6597 return;
6598 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006599
Jesse Barnes652c3932009-08-17 13:31:43 -07006600 intel_crtc->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07006601 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07006602}
6603
Daniel Vetter3dec0092010-08-20 21:40:52 +02006604static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006605{
6606 struct drm_device *dev = crtc->dev;
6607 drm_i915_private_t *dev_priv = dev->dev_private;
6608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6609 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006610 int dpll_reg = DPLL(pipe);
6611 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006612
Eric Anholtbad720f2009-10-22 16:11:14 -07006613 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006614 return;
6615
6616 if (!dev_priv->lvds_downclock_avail)
6617 return;
6618
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006619 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006620 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006621 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006622
6623 /* Unlock panel regs */
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006624 I915_WRITE(PP_CONTROL,
6625 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07006626
6627 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6628 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006629 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006630
Jesse Barnes652c3932009-08-17 13:31:43 -07006631 dpll = I915_READ(dpll_reg);
6632 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006633 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006634
6635 /* ...and lock them again */
6636 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6637 }
6638
6639 /* Schedule downclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02006640 mod_timer(&intel_crtc->idle_timer, jiffies +
6641 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07006642}
6643
6644static void intel_decrease_pllclock(struct drm_crtc *crtc)
6645{
6646 struct drm_device *dev = crtc->dev;
6647 drm_i915_private_t *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 int pipe = intel_crtc->pipe;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006650 int dpll_reg = DPLL(pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006651 int dpll = I915_READ(dpll_reg);
6652
Eric Anholtbad720f2009-10-22 16:11:14 -07006653 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006654 return;
6655
6656 if (!dev_priv->lvds_downclock_avail)
6657 return;
6658
6659 /*
6660 * Since this is called by a timer, we should never get here in
6661 * the manual case.
6662 */
6663 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006664 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006665
6666 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07006667 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6668 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07006669
6670 dpll |= DISPLAY_RATE_SELECT_FPA1;
6671 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006672 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006673 dpll = I915_READ(dpll_reg);
6674 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08006675 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006676
6677 /* ...and lock them again */
6678 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6679 }
6680
6681}
6682
6683/**
6684 * intel_idle_update - adjust clocks for idleness
6685 * @work: work struct
6686 *
6687 * Either the GPU or display (or both) went idle. Check the busy status
6688 * here and adjust the CRTC and GPU clocks as necessary.
6689 */
6690static void intel_idle_update(struct work_struct *work)
6691{
6692 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6693 idle_work);
6694 struct drm_device *dev = dev_priv->dev;
6695 struct drm_crtc *crtc;
6696 struct intel_crtc *intel_crtc;
6697
6698 if (!i915_powersave)
6699 return;
6700
6701 mutex_lock(&dev->struct_mutex);
6702
Jesse Barnes7648fa92010-05-20 14:28:11 -07006703 i915_update_gfx_val(dev_priv);
6704
Jesse Barnes652c3932009-08-17 13:31:43 -07006705 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6706 /* Skip inactive CRTCs */
6707 if (!crtc->fb)
6708 continue;
6709
6710 intel_crtc = to_intel_crtc(crtc);
6711 if (!intel_crtc->busy)
6712 intel_decrease_pllclock(crtc);
6713 }
6714
Li Peng45ac22c2010-06-12 23:38:35 +08006715
Jesse Barnes652c3932009-08-17 13:31:43 -07006716 mutex_unlock(&dev->struct_mutex);
6717}
6718
6719/**
6720 * intel_mark_busy - mark the GPU and possibly the display busy
6721 * @dev: drm device
6722 * @obj: object we're operating on
6723 *
6724 * Callers can use this function to indicate that the GPU is busy processing
6725 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6726 * buffer), we'll also mark the display as busy, so we know to increase its
6727 * clock frequency.
6728 */
Chris Wilson05394f32010-11-08 19:18:58 +00006729void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07006730{
6731 drm_i915_private_t *dev_priv = dev->dev_private;
6732 struct drm_crtc *crtc = NULL;
6733 struct intel_framebuffer *intel_fb;
6734 struct intel_crtc *intel_crtc;
6735
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08006736 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6737 return;
6738
Alexander Lam18b21902011-01-03 13:28:56 -05006739 if (!dev_priv->busy)
Chris Wilson28cf7982009-11-30 01:08:56 +00006740 dev_priv->busy = true;
Alexander Lam18b21902011-01-03 13:28:56 -05006741 else
Chris Wilson28cf7982009-11-30 01:08:56 +00006742 mod_timer(&dev_priv->idle_timer, jiffies +
6743 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07006744
6745 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6746 if (!crtc->fb)
6747 continue;
6748
6749 intel_crtc = to_intel_crtc(crtc);
6750 intel_fb = to_intel_framebuffer(crtc->fb);
6751 if (intel_fb->obj == obj) {
6752 if (!intel_crtc->busy) {
6753 /* Non-busy -> busy, upclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02006754 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006755 intel_crtc->busy = true;
6756 } else {
6757 /* Busy -> busy, put off timer */
6758 mod_timer(&intel_crtc->idle_timer, jiffies +
6759 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6760 }
6761 }
6762 }
6763}
6764
Jesse Barnes79e53942008-11-07 14:24:08 -08006765static void intel_crtc_destroy(struct drm_crtc *crtc)
6766{
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006768 struct drm_device *dev = crtc->dev;
6769 struct intel_unpin_work *work;
6770 unsigned long flags;
6771
6772 spin_lock_irqsave(&dev->event_lock, flags);
6773 work = intel_crtc->unpin_work;
6774 intel_crtc->unpin_work = NULL;
6775 spin_unlock_irqrestore(&dev->event_lock, flags);
6776
6777 if (work) {
6778 cancel_work_sync(&work->work);
6779 kfree(work);
6780 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006781
6782 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006783
Jesse Barnes79e53942008-11-07 14:24:08 -08006784 kfree(intel_crtc);
6785}
6786
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006787static void intel_unpin_work_fn(struct work_struct *__work)
6788{
6789 struct intel_unpin_work *work =
6790 container_of(__work, struct intel_unpin_work, work);
6791
6792 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006793 i915_gem_object_unpin(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00006794 drm_gem_object_unreference(&work->pending_flip_obj->base);
6795 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006796
Chris Wilson7782de32011-07-08 12:22:41 +01006797 intel_update_fbc(work->dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006798 mutex_unlock(&work->dev->struct_mutex);
6799 kfree(work);
6800}
6801
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006802static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01006803 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006804{
6805 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00006808 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006809 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006810 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006811 unsigned long flags;
6812
6813 /* Ignore early vblank irqs */
6814 if (intel_crtc == NULL)
6815 return;
6816
Mario Kleiner49b14a52010-12-09 07:00:07 +01006817 do_gettimeofday(&tnow);
6818
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006819 spin_lock_irqsave(&dev->event_lock, flags);
6820 work = intel_crtc->unpin_work;
6821 if (work == NULL || !work->pending) {
6822 spin_unlock_irqrestore(&dev->event_lock, flags);
6823 return;
6824 }
6825
6826 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006827
6828 if (work->event) {
6829 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006830 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006831
6832 /* Called before vblank count and timestamps have
6833 * been updated for the vblank interval of flip
6834 * completion? Need to increment vblank count and
6835 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01006836 * to account for this. We assume this happened if we
6837 * get called over 0.9 frame durations after the last
6838 * timestamped vblank.
6839 *
6840 * This calculation can not be used with vrefresh rates
6841 * below 5Hz (10Hz to be on the safe side) without
6842 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006843 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01006844 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6845 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006846 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006847 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6848 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006849 }
6850
Mario Kleiner49b14a52010-12-09 07:00:07 +01006851 e->event.tv_sec = tvbl.tv_sec;
6852 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006853
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006854 list_add_tail(&e->base.link,
6855 &e->base.file_priv->event_list);
6856 wake_up_interruptible(&e->base.file_priv->event_wait);
6857 }
6858
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006859 drm_vblank_put(dev, intel_crtc->pipe);
6860
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006861 spin_unlock_irqrestore(&dev->event_lock, flags);
6862
Chris Wilson05394f32010-11-08 19:18:58 +00006863 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006864
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006865 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006866 &obj->pending_flip.counter);
6867 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006868 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006869
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006870 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006871
6872 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006873}
6874
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006875void intel_finish_page_flip(struct drm_device *dev, int pipe)
6876{
6877 drm_i915_private_t *dev_priv = dev->dev_private;
6878 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6879
Mario Kleiner49b14a52010-12-09 07:00:07 +01006880 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006881}
6882
6883void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6884{
6885 drm_i915_private_t *dev_priv = dev->dev_private;
6886 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6887
Mario Kleiner49b14a52010-12-09 07:00:07 +01006888 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006889}
6890
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006891void intel_prepare_page_flip(struct drm_device *dev, int plane)
6892{
6893 drm_i915_private_t *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc =
6895 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6896 unsigned long flags;
6897
6898 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006899 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006900 if ((++intel_crtc->unpin_work->pending) > 1)
6901 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006902 } else {
6903 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6904 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006905 spin_unlock_irqrestore(&dev->event_lock, flags);
6906}
6907
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006908static int intel_gen2_queue_flip(struct drm_device *dev,
6909 struct drm_crtc *crtc,
6910 struct drm_framebuffer *fb,
6911 struct drm_i915_gem_object *obj)
6912{
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915 unsigned long offset;
6916 u32 flip_mask;
6917 int ret;
6918
6919 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6920 if (ret)
6921 goto out;
6922
6923 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6924 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6925
6926 ret = BEGIN_LP_RING(6);
6927 if (ret)
6928 goto out;
6929
6930 /* Can't queue multiple flips, so wait for the previous
6931 * one to finish before executing the next.
6932 */
6933 if (intel_crtc->plane)
6934 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6935 else
6936 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6937 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6938 OUT_RING(MI_NOOP);
6939 OUT_RING(MI_DISPLAY_FLIP |
6940 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6941 OUT_RING(fb->pitch);
6942 OUT_RING(obj->gtt_offset + offset);
6943 OUT_RING(MI_NOOP);
6944 ADVANCE_LP_RING();
6945out:
6946 return ret;
6947}
6948
6949static int intel_gen3_queue_flip(struct drm_device *dev,
6950 struct drm_crtc *crtc,
6951 struct drm_framebuffer *fb,
6952 struct drm_i915_gem_object *obj)
6953{
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956 unsigned long offset;
6957 u32 flip_mask;
6958 int ret;
6959
6960 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6961 if (ret)
6962 goto out;
6963
6964 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6965 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6966
6967 ret = BEGIN_LP_RING(6);
6968 if (ret)
6969 goto out;
6970
6971 if (intel_crtc->plane)
6972 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6973 else
6974 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6975 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6976 OUT_RING(MI_NOOP);
6977 OUT_RING(MI_DISPLAY_FLIP_I915 |
6978 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6979 OUT_RING(fb->pitch);
6980 OUT_RING(obj->gtt_offset + offset);
6981 OUT_RING(MI_NOOP);
6982
6983 ADVANCE_LP_RING();
6984out:
6985 return ret;
6986}
6987
6988static int intel_gen4_queue_flip(struct drm_device *dev,
6989 struct drm_crtc *crtc,
6990 struct drm_framebuffer *fb,
6991 struct drm_i915_gem_object *obj)
6992{
6993 struct drm_i915_private *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 uint32_t pf, pipesrc;
6996 int ret;
6997
6998 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6999 if (ret)
7000 goto out;
7001
7002 ret = BEGIN_LP_RING(4);
7003 if (ret)
7004 goto out;
7005
7006 /* i965+ uses the linear or tiled offsets from the
7007 * Display Registers (which do not change across a page-flip)
7008 * so we need only reprogram the base address.
7009 */
7010 OUT_RING(MI_DISPLAY_FLIP |
7011 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7012 OUT_RING(fb->pitch);
7013 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7014
7015 /* XXX Enabling the panel-fitter across page-flip is so far
7016 * untested on non-native modes, so ignore it for now.
7017 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7018 */
7019 pf = 0;
7020 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7021 OUT_RING(pf | pipesrc);
7022 ADVANCE_LP_RING();
7023out:
7024 return ret;
7025}
7026
7027static int intel_gen6_queue_flip(struct drm_device *dev,
7028 struct drm_crtc *crtc,
7029 struct drm_framebuffer *fb,
7030 struct drm_i915_gem_object *obj)
7031{
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7034 uint32_t pf, pipesrc;
7035 int ret;
7036
7037 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7038 if (ret)
7039 goto out;
7040
7041 ret = BEGIN_LP_RING(4);
7042 if (ret)
7043 goto out;
7044
7045 OUT_RING(MI_DISPLAY_FLIP |
7046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7047 OUT_RING(fb->pitch | obj->tiling_mode);
7048 OUT_RING(obj->gtt_offset);
7049
7050 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7051 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7052 OUT_RING(pf | pipesrc);
7053 ADVANCE_LP_RING();
7054out:
7055 return ret;
7056}
7057
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007058/*
7059 * On gen7 we currently use the blit ring because (in early silicon at least)
7060 * the render ring doesn't give us interrpts for page flip completion, which
7061 * means clients will hang after the first flip is queued. Fortunately the
7062 * blit ring generates interrupts properly, so use it instead.
7063 */
7064static int intel_gen7_queue_flip(struct drm_device *dev,
7065 struct drm_crtc *crtc,
7066 struct drm_framebuffer *fb,
7067 struct drm_i915_gem_object *obj)
7068{
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7071 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7072 int ret;
7073
7074 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7075 if (ret)
7076 goto out;
7077
7078 ret = intel_ring_begin(ring, 4);
7079 if (ret)
7080 goto out;
7081
7082 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7083 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7084 intel_ring_emit(ring, (obj->gtt_offset));
7085 intel_ring_emit(ring, (MI_NOOP));
7086 intel_ring_advance(ring);
7087out:
7088 return ret;
7089}
7090
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007091static int intel_default_queue_flip(struct drm_device *dev,
7092 struct drm_crtc *crtc,
7093 struct drm_framebuffer *fb,
7094 struct drm_i915_gem_object *obj)
7095{
7096 return -ENODEV;
7097}
7098
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007099static int intel_crtc_page_flip(struct drm_crtc *crtc,
7100 struct drm_framebuffer *fb,
7101 struct drm_pending_vblank_event *event)
7102{
7103 struct drm_device *dev = crtc->dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007106 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007109 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007110 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007111
7112 work = kzalloc(sizeof *work, GFP_KERNEL);
7113 if (work == NULL)
7114 return -ENOMEM;
7115
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007116 work->event = event;
7117 work->dev = crtc->dev;
7118 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08007119 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007120 INIT_WORK(&work->work, intel_unpin_work_fn);
7121
7122 /* We borrow the event spin lock for protecting unpin_work */
7123 spin_lock_irqsave(&dev->event_lock, flags);
7124 if (intel_crtc->unpin_work) {
7125 spin_unlock_irqrestore(&dev->event_lock, flags);
7126 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01007127
7128 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007129 return -EBUSY;
7130 }
7131 intel_crtc->unpin_work = work;
7132 spin_unlock_irqrestore(&dev->event_lock, flags);
7133
7134 intel_fb = to_intel_framebuffer(fb);
7135 obj = intel_fb->obj;
7136
Chris Wilson468f0b42010-05-27 13:18:13 +01007137 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007138
Jesse Barnes75dfca82010-02-10 15:09:44 -08007139 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007140 drm_gem_object_reference(&work->old_fb_obj->base);
7141 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007142
7143 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007144
7145 ret = drm_vblank_get(dev, intel_crtc->pipe);
7146 if (ret)
7147 goto cleanup_objs;
7148
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007149 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007150
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007151 work->enable_stall_check = true;
7152
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007153 /* Block clients from rendering to the new back buffer until
7154 * the flip occurs and the object is no longer visible.
7155 */
Chris Wilson05394f32010-11-08 19:18:58 +00007156 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007157
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007158 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7159 if (ret)
7160 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007161
Chris Wilson7782de32011-07-08 12:22:41 +01007162 intel_disable_fbc(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007163 mutex_unlock(&dev->struct_mutex);
7164
Jesse Barnese5510fa2010-07-01 16:48:37 -07007165 trace_i915_flip_request(intel_crtc->plane, obj);
7166
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007167 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007168
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007169cleanup_pending:
7170 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson96b099f2010-06-07 14:03:04 +01007171cleanup_objs:
Chris Wilson05394f32010-11-08 19:18:58 +00007172 drm_gem_object_unreference(&work->old_fb_obj->base);
7173 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007174 mutex_unlock(&dev->struct_mutex);
7175
7176 spin_lock_irqsave(&dev->event_lock, flags);
7177 intel_crtc->unpin_work = NULL;
7178 spin_unlock_irqrestore(&dev->event_lock, flags);
7179
7180 kfree(work);
7181
7182 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007183}
7184
Chris Wilson47f1c6c2010-12-03 15:37:31 +00007185static void intel_sanitize_modesetting(struct drm_device *dev,
7186 int pipe, int plane)
7187{
7188 struct drm_i915_private *dev_priv = dev->dev_private;
7189 u32 reg, val;
7190
7191 if (HAS_PCH_SPLIT(dev))
7192 return;
7193
7194 /* Who knows what state these registers were left in by the BIOS or
7195 * grub?
7196 *
7197 * If we leave the registers in a conflicting state (e.g. with the
7198 * display plane reading from the other pipe than the one we intend
7199 * to use) then when we attempt to teardown the active mode, we will
7200 * not disable the pipes and planes in the correct order -- leaving
7201 * a plane reading from a disabled pipe and possibly leading to
7202 * undefined behaviour.
7203 */
7204
7205 reg = DSPCNTR(plane);
7206 val = I915_READ(reg);
7207
7208 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7209 return;
7210 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7211 return;
7212
7213 /* This display plane is active and attached to the other CPU pipe. */
7214 pipe = !pipe;
7215
7216 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08007217 intel_disable_plane(dev_priv, plane, pipe);
7218 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00007219}
Jesse Barnes79e53942008-11-07 14:24:08 -08007220
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007221static void intel_crtc_reset(struct drm_crtc *crtc)
7222{
7223 struct drm_device *dev = crtc->dev;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225
7226 /* Reset flags back to the 'unknown' status so that they
7227 * will be correctly set on the initial modeset.
7228 */
7229 intel_crtc->dpms_mode = -1;
7230
7231 /* We need to fix up any BIOS configuration that conflicts with
7232 * our expectations.
7233 */
7234 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7235}
7236
7237static struct drm_crtc_helper_funcs intel_helper_funcs = {
7238 .dpms = intel_crtc_dpms,
7239 .mode_fixup = intel_crtc_mode_fixup,
7240 .mode_set = intel_crtc_mode_set,
7241 .mode_set_base = intel_pipe_set_base,
7242 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7243 .load_lut = intel_crtc_load_lut,
7244 .disable = intel_crtc_disable,
7245};
7246
7247static const struct drm_crtc_funcs intel_crtc_funcs = {
7248 .reset = intel_crtc_reset,
7249 .cursor_set = intel_crtc_cursor_set,
7250 .cursor_move = intel_crtc_cursor_move,
7251 .gamma_set = intel_crtc_gamma_set,
7252 .set_config = drm_crtc_helper_set_config,
7253 .destroy = intel_crtc_destroy,
7254 .page_flip = intel_crtc_page_flip,
7255};
7256
Hannes Ederb358d0a2008-12-18 21:18:47 +01007257static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08007258{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007259 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007260 struct intel_crtc *intel_crtc;
7261 int i;
7262
7263 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7264 if (intel_crtc == NULL)
7265 return;
7266
7267 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7268
7269 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08007270 for (i = 0; i < 256; i++) {
7271 intel_crtc->lut_r[i] = i;
7272 intel_crtc->lut_g[i] = i;
7273 intel_crtc->lut_b[i] = i;
7274 }
7275
Jesse Barnes80824002009-09-10 15:28:06 -07007276 /* Swap pipes & planes for FBC on pre-965 */
7277 intel_crtc->pipe = pipe;
7278 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01007279 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007280 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01007281 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07007282 }
7283
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007284 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7285 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7286 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7287 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7288
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00007289 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00007290 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes5a354202011-06-24 12:19:22 -07007291 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07007292
7293 if (HAS_PCH_SPLIT(dev)) {
7294 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7295 intel_helper_funcs.commit = ironlake_crtc_commit;
7296 } else {
7297 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7298 intel_helper_funcs.commit = i9xx_crtc_commit;
7299 }
7300
Jesse Barnes79e53942008-11-07 14:24:08 -08007301 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7302
Jesse Barnes652c3932009-08-17 13:31:43 -07007303 intel_crtc->busy = false;
7304
7305 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7306 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007307}
7308
Carl Worth08d7b3d2009-04-29 14:43:54 -07007309int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00007310 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07007311{
7312 drm_i915_private_t *dev_priv = dev->dev_private;
7313 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02007314 struct drm_mode_object *drmmode_obj;
7315 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007316
7317 if (!dev_priv) {
7318 DRM_ERROR("called with no initialization\n");
7319 return -EINVAL;
7320 }
7321
Daniel Vetterc05422d2009-08-11 16:05:30 +02007322 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7323 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07007324
Daniel Vetterc05422d2009-08-11 16:05:30 +02007325 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07007326 DRM_ERROR("no such CRTC id\n");
7327 return -EINVAL;
7328 }
7329
Daniel Vetterc05422d2009-08-11 16:05:30 +02007330 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7331 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007332
Daniel Vetterc05422d2009-08-11 16:05:30 +02007333 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007334}
7335
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08007336static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08007337{
Chris Wilson4ef69c72010-09-09 15:14:28 +01007338 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007339 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007340 int entry = 0;
7341
Chris Wilson4ef69c72010-09-09 15:14:28 +01007342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7343 if (type_mask & encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08007344 index_mask |= (1 << entry);
7345 entry++;
7346 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01007347
Jesse Barnes79e53942008-11-07 14:24:08 -08007348 return index_mask;
7349}
7350
Chris Wilson4d302442010-12-14 19:21:29 +00007351static bool has_edp_a(struct drm_device *dev)
7352{
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354
7355 if (!IS_MOBILE(dev))
7356 return false;
7357
7358 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7359 return false;
7360
7361 if (IS_GEN5(dev) &&
7362 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7363 return false;
7364
7365 return true;
7366}
7367
Jesse Barnes79e53942008-11-07 14:24:08 -08007368static void intel_setup_outputs(struct drm_device *dev)
7369{
Eric Anholt725e30a2009-01-22 13:01:02 -08007370 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007371 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007372 bool dpd_is_edp = false;
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007373 bool has_lvds = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007374
Zhenyu Wang541998a2009-06-05 15:38:44 +08007375 if (IS_MOBILE(dev) && !IS_I830(dev))
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007376 has_lvds = intel_lvds_init(dev);
7377 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7378 /* disable the panel fitter on everything but LVDS */
7379 I915_WRITE(PFIT_CONTROL, 0);
7380 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007381
Eric Anholtbad720f2009-10-22 16:11:14 -07007382 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007383 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007384
Chris Wilson4d302442010-12-14 19:21:29 +00007385 if (has_edp_a(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08007386 intel_dp_init(dev, DP_A);
7387
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007388 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7389 intel_dp_init(dev, PCH_DP_D);
7390 }
7391
7392 intel_crt_init(dev);
7393
7394 if (HAS_PCH_SPLIT(dev)) {
7395 int found;
7396
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007397 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08007398 /* PCH SDVOB multiplex with HDMIB */
7399 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007400 if (!found)
7401 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007402 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7403 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007404 }
7405
7406 if (I915_READ(HDMIC) & PORT_DETECTED)
7407 intel_hdmi_init(dev, HDMIC);
7408
7409 if (I915_READ(HDMID) & PORT_DETECTED)
7410 intel_hdmi_init(dev, HDMID);
7411
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007412 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7413 intel_dp_init(dev, PCH_DP_C);
7414
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007415 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007416 intel_dp_init(dev, PCH_DP_D);
7417
Zhenyu Wang103a1962009-11-27 11:44:36 +08007418 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08007419 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08007420
Eric Anholt725e30a2009-01-22 13:01:02 -08007421 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007422 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007423 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007424 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7425 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007426 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007427 }
Ma Ling27185ae2009-08-24 13:50:23 +08007428
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007429 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7430 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007431 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007432 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007433 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007434
7435 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007436
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007437 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7438 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007439 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007440 }
Ma Ling27185ae2009-08-24 13:50:23 +08007441
7442 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7443
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007444 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7445 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007446 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007447 }
7448 if (SUPPORTS_INTEGRATED_DP(dev)) {
7449 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007450 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007451 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007452 }
Ma Ling27185ae2009-08-24 13:50:23 +08007453
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007454 if (SUPPORTS_INTEGRATED_DP(dev) &&
7455 (I915_READ(DP_D) & DP_DETECTED)) {
7456 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007457 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007458 }
Eric Anholtbad720f2009-10-22 16:11:14 -07007459 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007460 intel_dvo_init(dev);
7461
Zhenyu Wang103a1962009-11-27 11:44:36 +08007462 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007463 intel_tv_init(dev);
7464
Chris Wilson4ef69c72010-09-09 15:14:28 +01007465 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7466 encoder->base.possible_crtcs = encoder->crtc_mask;
7467 encoder->base.possible_clones =
7468 intel_encoder_clones(dev, encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08007469 }
Chris Wilson47356eb2011-01-11 17:06:04 +00007470
Chris Wilson2c7111d2011-03-29 10:40:27 +01007471 /* disable all the possible outputs/crtcs before entering KMS mode */
7472 drm_helper_disable_unused_functions(dev);
Keith Packard9fb526d2011-09-26 22:24:57 -07007473
7474 if (HAS_PCH_SPLIT(dev))
7475 ironlake_init_pch_refclk(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007476}
7477
7478static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7479{
7480 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08007481
7482 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007483 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007484
7485 kfree(intel_fb);
7486}
7487
7488static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00007489 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08007490 unsigned int *handle)
7491{
7492 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007493 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007494
Chris Wilson05394f32010-11-08 19:18:58 +00007495 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08007496}
7497
7498static const struct drm_framebuffer_funcs intel_fb_funcs = {
7499 .destroy = intel_user_framebuffer_destroy,
7500 .create_handle = intel_user_framebuffer_create_handle,
7501};
7502
Dave Airlie38651672010-03-30 05:34:13 +00007503int intel_framebuffer_init(struct drm_device *dev,
7504 struct intel_framebuffer *intel_fb,
7505 struct drm_mode_fb_cmd *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00007506 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08007507{
Jesse Barnes79e53942008-11-07 14:24:08 -08007508 int ret;
7509
Chris Wilson05394f32010-11-08 19:18:58 +00007510 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01007511 return -EINVAL;
7512
7513 if (mode_cmd->pitch & 63)
7514 return -EINVAL;
7515
7516 switch (mode_cmd->bpp) {
7517 case 8:
7518 case 16:
Jesse Barnesb5626742011-06-24 12:19:27 -07007519 /* Only pre-ILK can handle 5:5:5 */
7520 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7521 return -EINVAL;
7522 break;
7523
Chris Wilson57cd6502010-08-08 12:34:44 +01007524 case 24:
7525 case 32:
7526 break;
7527 default:
7528 return -EINVAL;
7529 }
7530
Jesse Barnes79e53942008-11-07 14:24:08 -08007531 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7532 if (ret) {
7533 DRM_ERROR("framebuffer init failed %d\n", ret);
7534 return ret;
7535 }
7536
7537 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08007538 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007539 return 0;
7540}
7541
Jesse Barnes79e53942008-11-07 14:24:08 -08007542static struct drm_framebuffer *
7543intel_user_framebuffer_create(struct drm_device *dev,
7544 struct drm_file *filp,
7545 struct drm_mode_fb_cmd *mode_cmd)
7546{
Chris Wilson05394f32010-11-08 19:18:58 +00007547 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007548
Chris Wilson05394f32010-11-08 19:18:58 +00007549 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00007550 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01007551 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08007552
Chris Wilsond2dff872011-04-19 08:36:26 +01007553 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08007554}
7555
Jesse Barnes79e53942008-11-07 14:24:08 -08007556static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08007557 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00007558 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08007559};
7560
Chris Wilson05394f32010-11-08 19:18:58 +00007561static struct drm_i915_gem_object *
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007562intel_alloc_context_page(struct drm_device *dev)
Chris Wilson9ea8d052010-01-04 18:57:56 +00007563{
Chris Wilson05394f32010-11-08 19:18:58 +00007564 struct drm_i915_gem_object *ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00007565 int ret;
7566
Ben Widawsky2c34b852011-03-19 18:14:26 -07007567 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7568
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007569 ctx = i915_gem_alloc_object(dev, 4096);
7570 if (!ctx) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00007571 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7572 return NULL;
7573 }
7574
Daniel Vetter75e9e912010-11-04 17:11:09 +01007575 ret = i915_gem_object_pin(ctx, 4096, true);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007576 if (ret) {
7577 DRM_ERROR("failed to pin power context: %d\n", ret);
7578 goto err_unref;
7579 }
7580
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007581 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007582 if (ret) {
7583 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7584 goto err_unpin;
7585 }
Chris Wilson9ea8d052010-01-04 18:57:56 +00007586
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007587 return ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00007588
7589err_unpin:
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007590 i915_gem_object_unpin(ctx);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007591err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00007592 drm_gem_object_unreference(&ctx->base);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007593 mutex_unlock(&dev->struct_mutex);
7594 return NULL;
7595}
7596
Jesse Barnes7648fa92010-05-20 14:28:11 -07007597bool ironlake_set_drps(struct drm_device *dev, u8 val)
7598{
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 u16 rgvswctl;
7601
7602 rgvswctl = I915_READ16(MEMSWCTL);
7603 if (rgvswctl & MEMCTL_CMD_STS) {
7604 DRM_DEBUG("gpu busy, RCS change rejected\n");
7605 return false; /* still busy with another command */
7606 }
7607
7608 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7609 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7610 I915_WRITE16(MEMSWCTL, rgvswctl);
7611 POSTING_READ16(MEMSWCTL);
7612
7613 rgvswctl |= MEMCTL_CMD_STS;
7614 I915_WRITE16(MEMSWCTL, rgvswctl);
7615
7616 return true;
7617}
7618
Jesse Barnesf97108d2010-01-29 11:27:07 -08007619void ironlake_enable_drps(struct drm_device *dev)
7620{
7621 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07007622 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007623 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08007624
Jesse Barnesea056c12010-09-10 10:02:13 -07007625 /* Enable temp reporting */
7626 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7627 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7628
Jesse Barnesf97108d2010-01-29 11:27:07 -08007629 /* 100ms RC evaluation intervals */
7630 I915_WRITE(RCUPEI, 100000);
7631 I915_WRITE(RCDNEI, 100000);
7632
7633 /* Set max/min thresholds to 90ms and 80ms respectively */
7634 I915_WRITE(RCBMAXAVG, 90000);
7635 I915_WRITE(RCBMINAVG, 80000);
7636
7637 I915_WRITE(MEMIHYST, 1);
7638
7639 /* Set up min, max, and cur for interrupt handling */
7640 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7641 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7642 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7643 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07007644
Jesse Barnesf97108d2010-01-29 11:27:07 -08007645 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7646 PXVFREQ_PX_SHIFT;
7647
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007648 dev_priv->fmax = fmax; /* IPS callback will increase this */
Jesse Barnes7648fa92010-05-20 14:28:11 -07007649 dev_priv->fstart = fstart;
7650
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007651 dev_priv->max_delay = fstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08007652 dev_priv->min_delay = fmin;
7653 dev_priv->cur_delay = fstart;
7654
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07007655 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7656 fmax, fmin, fstart);
Jesse Barnes7648fa92010-05-20 14:28:11 -07007657
Jesse Barnesf97108d2010-01-29 11:27:07 -08007658 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7659
7660 /*
7661 * Interrupts will be enabled in ironlake_irq_postinstall
7662 */
7663
7664 I915_WRITE(VIDSTART, vstart);
7665 POSTING_READ(VIDSTART);
7666
7667 rgvmodectl |= MEMMODE_SWMODE_EN;
7668 I915_WRITE(MEMMODECTL, rgvmodectl);
7669
Chris Wilson481b6af2010-08-23 17:43:35 +01007670 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Chris Wilson913d8d12010-08-07 11:01:35 +01007671 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08007672 msleep(1);
7673
Jesse Barnes7648fa92010-05-20 14:28:11 -07007674 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007675
Jesse Barnes7648fa92010-05-20 14:28:11 -07007676 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7677 I915_READ(0x112e0);
7678 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7679 dev_priv->last_count2 = I915_READ(0x112f4);
7680 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007681}
7682
7683void ironlake_disable_drps(struct drm_device *dev)
7684{
7685 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07007686 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007687
7688 /* Ack interrupts, disable EFC interrupt */
7689 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7690 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7691 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7692 I915_WRITE(DEIIR, DE_PCU_EVENT);
7693 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7694
7695 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07007696 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007697 msleep(1);
7698 rgvswctl |= MEMCTL_CMD_STS;
7699 I915_WRITE(MEMSWCTL, rgvswctl);
7700 msleep(1);
7701
7702}
7703
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007704void gen6_set_rps(struct drm_device *dev, u8 val)
7705{
7706 struct drm_i915_private *dev_priv = dev->dev_private;
7707 u32 swreq;
7708
7709 swreq = (val & 0x3ff) << 25;
7710 I915_WRITE(GEN6_RPNSWREQ, swreq);
7711}
7712
7713void gen6_disable_rps(struct drm_device *dev)
7714{
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716
7717 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7718 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7719 I915_WRITE(GEN6_PMIER, 0);
Daniel Vetter6fdd4d92011-09-08 14:00:22 +02007720 /* Complete PM interrupt masking here doesn't race with the rps work
7721 * item again unmasking PM interrupts because that is using a different
7722 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7723 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
Ben Widawsky4912d042011-04-25 11:25:20 -07007724
7725 spin_lock_irq(&dev_priv->rps_lock);
7726 dev_priv->pm_iir = 0;
7727 spin_unlock_irq(&dev_priv->rps_lock);
7728
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007729 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7730}
7731
Jesse Barnes7648fa92010-05-20 14:28:11 -07007732static unsigned long intel_pxfreq(u32 vidfreq)
7733{
7734 unsigned long freq;
7735 int div = (vidfreq & 0x3f0000) >> 16;
7736 int post = (vidfreq & 0x3000) >> 12;
7737 int pre = (vidfreq & 0x7);
7738
7739 if (!pre)
7740 return 0;
7741
7742 freq = ((div * 133333) / ((1<<post) * pre));
7743
7744 return freq;
7745}
7746
7747void intel_init_emon(struct drm_device *dev)
7748{
7749 struct drm_i915_private *dev_priv = dev->dev_private;
7750 u32 lcfuse;
7751 u8 pxw[16];
7752 int i;
7753
7754 /* Disable to program */
7755 I915_WRITE(ECR, 0);
7756 POSTING_READ(ECR);
7757
7758 /* Program energy weights for various events */
7759 I915_WRITE(SDEW, 0x15040d00);
7760 I915_WRITE(CSIEW0, 0x007f0000);
7761 I915_WRITE(CSIEW1, 0x1e220004);
7762 I915_WRITE(CSIEW2, 0x04000004);
7763
7764 for (i = 0; i < 5; i++)
7765 I915_WRITE(PEW + (i * 4), 0);
7766 for (i = 0; i < 3; i++)
7767 I915_WRITE(DEW + (i * 4), 0);
7768
7769 /* Program P-state weights to account for frequency power adjustment */
7770 for (i = 0; i < 16; i++) {
7771 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7772 unsigned long freq = intel_pxfreq(pxvidfreq);
7773 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7774 PXVFREQ_PX_SHIFT;
7775 unsigned long val;
7776
7777 val = vid * vid;
7778 val *= (freq / 1000);
7779 val *= 255;
7780 val /= (127*127*900);
7781 if (val > 0xff)
7782 DRM_ERROR("bad pxval: %ld\n", val);
7783 pxw[i] = val;
7784 }
7785 /* Render standby states get 0 weight */
7786 pxw[14] = 0;
7787 pxw[15] = 0;
7788
7789 for (i = 0; i < 4; i++) {
7790 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7791 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7792 I915_WRITE(PXW + (i * 4), val);
7793 }
7794
7795 /* Adjust magic regs to magic values (more experimental results) */
7796 I915_WRITE(OGW0, 0);
7797 I915_WRITE(OGW1, 0);
7798 I915_WRITE(EG0, 0x00007f00);
7799 I915_WRITE(EG1, 0x0000000e);
7800 I915_WRITE(EG2, 0x000e0000);
7801 I915_WRITE(EG3, 0x68000300);
7802 I915_WRITE(EG4, 0x42000000);
7803 I915_WRITE(EG5, 0x00140031);
7804 I915_WRITE(EG6, 0);
7805 I915_WRITE(EG7, 0);
7806
7807 for (i = 0; i < 8; i++)
7808 I915_WRITE(PXWL + (i * 4), 0);
7809
7810 /* Enable PMON + select events */
7811 I915_WRITE(ECR, 0x80000019);
7812
7813 lcfuse = I915_READ(LCFUSE02);
7814
7815 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7816}
7817
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007818void gen6_enable_rps(struct drm_i915_private *dev_priv)
Chris Wilson8fd26852010-12-08 18:40:43 +00007819{
Jesse Barnesa6044e22010-12-20 11:34:20 -08007820 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7821 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
Jesse Barnes7df87212011-03-30 14:08:56 -07007822 u32 pcu_mbox, rc6_mask = 0;
Jesse Barnesa6044e22010-12-20 11:34:20 -08007823 int cur_freq, min_freq, max_freq;
Chris Wilson8fd26852010-12-08 18:40:43 +00007824 int i;
7825
7826 /* Here begins a magic sequence of register writes to enable
7827 * auto-downclocking.
7828 *
7829 * Perhaps there might be some value in exposing these to
7830 * userspace...
7831 */
7832 I915_WRITE(GEN6_RC_STATE, 0);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01007833 mutex_lock(&dev_priv->dev->struct_mutex);
Ben Widawskyfcca7922011-04-25 11:23:07 -07007834 gen6_gt_force_wake_get(dev_priv);
Chris Wilson8fd26852010-12-08 18:40:43 +00007835
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007836 /* disable the counters and set deterministic thresholds */
Chris Wilson8fd26852010-12-08 18:40:43 +00007837 I915_WRITE(GEN6_RC_CONTROL, 0);
7838
7839 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7840 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7841 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7842 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7843 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7844
7845 for (i = 0; i < I915_NUM_RINGS; i++)
7846 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7847
7848 I915_WRITE(GEN6_RC_SLEEP, 0);
7849 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7850 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7851 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7852 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7853
Jesse Barnes7df87212011-03-30 14:08:56 -07007854 if (i915_enable_rc6)
7855 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7856 GEN6_RC_CTL_RC6_ENABLE;
7857
Chris Wilson8fd26852010-12-08 18:40:43 +00007858 I915_WRITE(GEN6_RC_CONTROL,
Jesse Barnes7df87212011-03-30 14:08:56 -07007859 rc6_mask |
Chris Wilson9c3d2f72010-12-17 10:54:26 +00007860 GEN6_RC_CTL_EI_MODE(1) |
Chris Wilson8fd26852010-12-08 18:40:43 +00007861 GEN6_RC_CTL_HW_ENABLE);
7862
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007863 I915_WRITE(GEN6_RPNSWREQ,
Chris Wilson8fd26852010-12-08 18:40:43 +00007864 GEN6_FREQUENCY(10) |
7865 GEN6_OFFSET(0) |
7866 GEN6_AGGRESSIVE_TURBO);
7867 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7868 GEN6_FREQUENCY(12));
7869
7870 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7871 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7872 18 << 24 |
7873 6 << 16);
Jesse Barnesccab5c82011-01-18 15:49:25 -08007874 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7875 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00007876 I915_WRITE(GEN6_RP_UP_EI, 100000);
Jesse Barnesccab5c82011-01-18 15:49:25 -08007877 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00007878 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7879 I915_WRITE(GEN6_RP_CONTROL,
7880 GEN6_RP_MEDIA_TURBO |
7881 GEN6_RP_USE_NORMAL_FREQ |
7882 GEN6_RP_MEDIA_IS_GFX |
7883 GEN6_RP_ENABLE |
Jesse Barnesccab5c82011-01-18 15:49:25 -08007884 GEN6_RP_UP_BUSY_AVG |
7885 GEN6_RP_DOWN_IDLE_CONT);
Chris Wilson8fd26852010-12-08 18:40:43 +00007886
7887 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7888 500))
7889 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7890
7891 I915_WRITE(GEN6_PCODE_DATA, 0);
7892 I915_WRITE(GEN6_PCODE_MAILBOX,
7893 GEN6_PCODE_READY |
7894 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7895 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7896 500))
7897 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7898
Jesse Barnesa6044e22010-12-20 11:34:20 -08007899 min_freq = (rp_state_cap & 0xff0000) >> 16;
7900 max_freq = rp_state_cap & 0xff;
7901 cur_freq = (gt_perf_status & 0xff00) >> 8;
7902
7903 /* Check for overclock support */
7904 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7905 500))
7906 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7907 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7908 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7910 500))
7911 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7912 if (pcu_mbox & (1<<31)) { /* OC supported */
7913 max_freq = pcu_mbox & 0xff;
Jesse Barnese281fca2011-03-18 10:32:07 -07007914 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
Jesse Barnesa6044e22010-12-20 11:34:20 -08007915 }
7916
7917 /* In units of 100MHz */
7918 dev_priv->max_delay = max_freq;
7919 dev_priv->min_delay = min_freq;
7920 dev_priv->cur_delay = cur_freq;
7921
Chris Wilson8fd26852010-12-08 18:40:43 +00007922 /* requires MSI enabled */
7923 I915_WRITE(GEN6_PMIER,
7924 GEN6_PM_MBOX_EVENT |
7925 GEN6_PM_THERMAL_EVENT |
7926 GEN6_PM_RP_DOWN_TIMEOUT |
7927 GEN6_PM_RP_UP_THRESHOLD |
7928 GEN6_PM_RP_DOWN_THRESHOLD |
7929 GEN6_PM_RP_UP_EI_EXPIRED |
7930 GEN6_PM_RP_DOWN_EI_EXPIRED);
Ben Widawsky4912d042011-04-25 11:25:20 -07007931 spin_lock_irq(&dev_priv->rps_lock);
7932 WARN_ON(dev_priv->pm_iir != 0);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007933 I915_WRITE(GEN6_PMIMR, 0);
Ben Widawsky4912d042011-04-25 11:25:20 -07007934 spin_unlock_irq(&dev_priv->rps_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007935 /* enable all PM interrupts */
7936 I915_WRITE(GEN6_PMINTRMSK, 0);
Chris Wilson8fd26852010-12-08 18:40:43 +00007937
Ben Widawskyfcca7922011-04-25 11:23:07 -07007938 gen6_gt_force_wake_put(dev_priv);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01007939 mutex_unlock(&dev_priv->dev->struct_mutex);
Chris Wilson8fd26852010-12-08 18:40:43 +00007940}
7941
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07007942void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7943{
7944 int min_freq = 15;
7945 int gpu_freq, ia_freq, max_ia_freq;
7946 int scaling_factor = 180;
7947
7948 max_ia_freq = cpufreq_quick_get_max(0);
7949 /*
7950 * Default to measured freq if none found, PCU will ensure we don't go
7951 * over
7952 */
7953 if (!max_ia_freq)
7954 max_ia_freq = tsc_khz;
7955
7956 /* Convert from kHz to MHz */
7957 max_ia_freq /= 1000;
7958
7959 mutex_lock(&dev_priv->dev->struct_mutex);
7960
7961 /*
7962 * For each potential GPU frequency, load a ring frequency we'd like
7963 * to use for memory access. We do this by specifying the IA frequency
7964 * the PCU should use as a reference to determine the ring frequency.
7965 */
7966 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7967 gpu_freq--) {
7968 int diff = dev_priv->max_delay - gpu_freq;
7969
7970 /*
7971 * For GPU frequencies less than 750MHz, just use the lowest
7972 * ring freq.
7973 */
7974 if (gpu_freq < min_freq)
7975 ia_freq = 800;
7976 else
7977 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7978 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7979
7980 I915_WRITE(GEN6_PCODE_DATA,
7981 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7982 gpu_freq);
7983 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7984 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7985 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7986 GEN6_PCODE_READY) == 0, 10)) {
7987 DRM_ERROR("pcode write of freq table timed out\n");
7988 continue;
7989 }
7990 }
7991
7992 mutex_unlock(&dev_priv->dev->struct_mutex);
7993}
7994
Jesse Barnes6067aae2011-04-28 15:04:31 -07007995static void ironlake_init_clock_gating(struct drm_device *dev)
7996{
7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7999
8000 /* Required for FBC */
8001 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8002 DPFCRUNIT_CLOCK_GATE_DISABLE |
8003 DPFDUNIT_CLOCK_GATE_DISABLE;
8004 /* Required for CxSR */
8005 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8006
8007 I915_WRITE(PCH_3DCGDIS0,
8008 MARIUNIT_CLOCK_GATE_DISABLE |
8009 SVSMUNIT_CLOCK_GATE_DISABLE);
8010 I915_WRITE(PCH_3DCGDIS1,
8011 VFMUNIT_CLOCK_GATE_DISABLE);
8012
8013 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8014
8015 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07008016 * According to the spec the following bits should be set in
8017 * order to enable memory self-refresh
8018 * The bit 22/21 of 0x42004
8019 * The bit 5 of 0x42020
8020 * The bit 15 of 0x45000
8021 */
8022 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8023 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8024 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8025 I915_WRITE(ILK_DSPCLK_GATE,
8026 (I915_READ(ILK_DSPCLK_GATE) |
8027 ILK_DPARB_CLK_GATE));
8028 I915_WRITE(DISP_ARB_CTL,
8029 (I915_READ(DISP_ARB_CTL) |
8030 DISP_FBC_WM_DIS));
8031 I915_WRITE(WM3_LP_ILK, 0);
8032 I915_WRITE(WM2_LP_ILK, 0);
8033 I915_WRITE(WM1_LP_ILK, 0);
8034
8035 /*
8036 * Based on the document from hardware guys the following bits
8037 * should be set unconditionally in order to enable FBC.
8038 * The bit 22 of 0x42000
8039 * The bit 22 of 0x42004
8040 * The bit 7,8,9 of 0x42020.
8041 */
8042 if (IS_IRONLAKE_M(dev)) {
8043 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8044 I915_READ(ILK_DISPLAY_CHICKEN1) |
8045 ILK_FBCQ_DIS);
8046 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8047 I915_READ(ILK_DISPLAY_CHICKEN2) |
8048 ILK_DPARB_GATE);
8049 I915_WRITE(ILK_DSPCLK_GATE,
8050 I915_READ(ILK_DSPCLK_GATE) |
8051 ILK_DPFC_DIS1 |
8052 ILK_DPFC_DIS2 |
8053 ILK_CLK_FBC);
8054 }
8055
8056 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8057 I915_READ(ILK_DISPLAY_CHICKEN2) |
8058 ILK_ELPIN_409_SELECT);
8059 I915_WRITE(_3D_CHICKEN2,
8060 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8061 _3D_CHICKEN2_WM_READ_PIPELINED);
8062}
8063
8064static void gen6_init_clock_gating(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008065{
8066 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008067 int pipe;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008068 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8069
8070 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Jesse Barnes652c3932009-08-17 13:31:43 -07008071
Jesse Barnes6067aae2011-04-28 15:04:31 -07008072 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8073 I915_READ(ILK_DISPLAY_CHICKEN2) |
8074 ILK_ELPIN_409_SELECT);
Eric Anholt8956c8b2010-03-18 13:21:14 -07008075
Jesse Barnes6067aae2011-04-28 15:04:31 -07008076 I915_WRITE(WM3_LP_ILK, 0);
8077 I915_WRITE(WM2_LP_ILK, 0);
8078 I915_WRITE(WM1_LP_ILK, 0);
Eric Anholt8956c8b2010-03-18 13:21:14 -07008079
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008080 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07008081 * According to the spec the following bits should be
8082 * set in order to enable memory self-refresh and fbc:
8083 * The bit21 and bit22 of 0x42000
8084 * The bit21 and bit22 of 0x42004
8085 * The bit5 and bit7 of 0x42020
8086 * The bit14 of 0x70180
8087 * The bit14 of 0x71180
Jesse Barnes382b0932010-10-07 16:01:25 -07008088 */
Jesse Barnes6067aae2011-04-28 15:04:31 -07008089 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8090 I915_READ(ILK_DISPLAY_CHICKEN1) |
8091 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8092 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8093 I915_READ(ILK_DISPLAY_CHICKEN2) |
8094 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8095 I915_WRITE(ILK_DSPCLK_GATE,
8096 I915_READ(ILK_DSPCLK_GATE) |
8097 ILK_DPARB_CLK_GATE |
8098 ILK_DPFD_CLK_GATE);
Jesse Barnes382b0932010-10-07 16:01:25 -07008099
Keith Packardd74362c2011-07-28 14:47:14 -07008100 for_each_pipe(pipe) {
Jesse Barnes6067aae2011-04-28 15:04:31 -07008101 I915_WRITE(DSPCNTR(pipe),
8102 I915_READ(DSPCNTR(pipe)) |
8103 DISPPLANE_TRICKLE_FEED_DISABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07008104 intel_flush_display_plane(dev_priv, pipe);
8105 }
Jesse Barnes6067aae2011-04-28 15:04:31 -07008106}
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008107
Jesse Barnes28963a32011-05-11 09:42:30 -07008108static void ivybridge_init_clock_gating(struct drm_device *dev)
8109{
8110 struct drm_i915_private *dev_priv = dev->dev_private;
8111 int pipe;
8112 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
Jesse Barnes652c3932009-08-17 13:31:43 -07008113
Jesse Barnes28963a32011-05-11 09:42:30 -07008114 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008115
Jesse Barnes28963a32011-05-11 09:42:30 -07008116 I915_WRITE(WM3_LP_ILK, 0);
8117 I915_WRITE(WM2_LP_ILK, 0);
8118 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008119
Jesse Barnes28963a32011-05-11 09:42:30 -07008120 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
Eric Anholtde6e2ea2010-11-06 14:53:32 -07008121
Keith Packardd74362c2011-07-28 14:47:14 -07008122 for_each_pipe(pipe) {
Jesse Barnes28963a32011-05-11 09:42:30 -07008123 I915_WRITE(DSPCNTR(pipe),
8124 I915_READ(DSPCNTR(pipe)) |
8125 DISPPLANE_TRICKLE_FEED_DISABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07008126 intel_flush_display_plane(dev_priv, pipe);
8127 }
Jesse Barnes28963a32011-05-11 09:42:30 -07008128}
Eric Anholt67e92af2010-11-06 14:53:33 -07008129
Jesse Barnes6067aae2011-04-28 15:04:31 -07008130static void g4x_init_clock_gating(struct drm_device *dev)
8131{
8132 struct drm_i915_private *dev_priv = dev->dev_private;
8133 uint32_t dspclk_gate;
Chris Wilson8fd26852010-12-08 18:40:43 +00008134
Jesse Barnes6067aae2011-04-28 15:04:31 -07008135 I915_WRITE(RENCLK_GATE_D1, 0);
8136 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8137 GS_UNIT_CLOCK_GATE_DISABLE |
8138 CL_UNIT_CLOCK_GATE_DISABLE);
8139 I915_WRITE(RAMCLK_GATE_D, 0);
8140 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8141 OVRUNIT_CLOCK_GATE_DISABLE |
8142 OVCUNIT_CLOCK_GATE_DISABLE;
8143 if (IS_GM45(dev))
8144 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8145 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8146}
Yuanhan Liu13982612010-12-15 15:42:31 +08008147
Jesse Barnes6067aae2011-04-28 15:04:31 -07008148static void crestline_init_clock_gating(struct drm_device *dev)
8149{
8150 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liu13982612010-12-15 15:42:31 +08008151
Jesse Barnes6067aae2011-04-28 15:04:31 -07008152 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8153 I915_WRITE(RENCLK_GATE_D2, 0);
8154 I915_WRITE(DSPCLK_GATE_D, 0);
8155 I915_WRITE(RAMCLK_GATE_D, 0);
8156 I915_WRITE16(DEUC, 0);
8157}
Jesse Barnes652c3932009-08-17 13:31:43 -07008158
Jesse Barnes6067aae2011-04-28 15:04:31 -07008159static void broadwater_init_clock_gating(struct drm_device *dev)
8160{
8161 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008162
Jesse Barnes6067aae2011-04-28 15:04:31 -07008163 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8164 I965_RCC_CLOCK_GATE_DISABLE |
8165 I965_RCPB_CLOCK_GATE_DISABLE |
8166 I965_ISC_CLOCK_GATE_DISABLE |
8167 I965_FBC_CLOCK_GATE_DISABLE);
8168 I915_WRITE(RENCLK_GATE_D2, 0);
8169}
Jesse Barnes652c3932009-08-17 13:31:43 -07008170
Jesse Barnes6067aae2011-04-28 15:04:31 -07008171static void gen3_init_clock_gating(struct drm_device *dev)
8172{
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 u32 dstate = I915_READ(D_STATE);
8175
8176 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8177 DSTATE_DOT_CLOCK_GATING;
8178 I915_WRITE(D_STATE, dstate);
8179}
8180
8181static void i85x_init_clock_gating(struct drm_device *dev)
8182{
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184
8185 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8186}
8187
8188static void i830_init_clock_gating(struct drm_device *dev)
8189{
8190 struct drm_i915_private *dev_priv = dev->dev_private;
8191
8192 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes652c3932009-08-17 13:31:43 -07008193}
8194
Jesse Barnes645c62a2011-05-11 09:49:31 -07008195static void ibx_init_clock_gating(struct drm_device *dev)
8196{
8197 struct drm_i915_private *dev_priv = dev->dev_private;
8198
8199 /*
8200 * On Ibex Peak and Cougar Point, we need to disable clock
8201 * gating for the panel power sequencer or it will fail to
8202 * start up when no ports are active.
8203 */
8204 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8205}
8206
8207static void cpt_init_clock_gating(struct drm_device *dev)
8208{
8209 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes3bcf6032011-07-27 11:51:40 -07008210 int pipe;
Jesse Barnes645c62a2011-05-11 09:49:31 -07008211
8212 /*
8213 * On Ibex Peak and Cougar Point, we need to disable clock
8214 * gating for the panel power sequencer or it will fail to
8215 * start up when no ports are active.
8216 */
8217 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8218 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8219 DPLS_EDP_PPS_FIX_DIS);
Jesse Barnes3bcf6032011-07-27 11:51:40 -07008220 /* Without this, mode sets may fail silently on FDI */
8221 for_each_pipe(pipe)
8222 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
Jesse Barnes79e53942008-11-07 14:24:08 -08008223}
8224
Chris Wilsonac668082011-02-09 16:15:32 +00008225static void ironlake_teardown_rc6(struct drm_device *dev)
Chris Wilson0cdab212010-12-05 17:27:06 +00008226{
8227 struct drm_i915_private *dev_priv = dev->dev_private;
8228
8229 if (dev_priv->renderctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00008230 i915_gem_object_unpin(dev_priv->renderctx);
8231 drm_gem_object_unreference(&dev_priv->renderctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00008232 dev_priv->renderctx = NULL;
8233 }
8234
8235 if (dev_priv->pwrctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00008236 i915_gem_object_unpin(dev_priv->pwrctx);
8237 drm_gem_object_unreference(&dev_priv->pwrctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00008238 dev_priv->pwrctx = NULL;
8239 }
8240}
8241
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008242static void ironlake_disable_rc6(struct drm_device *dev)
8243{
8244 struct drm_i915_private *dev_priv = dev->dev_private;
8245
Chris Wilsonac668082011-02-09 16:15:32 +00008246 if (I915_READ(PWRCTXA)) {
8247 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8248 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8249 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8250 50);
8251
8252 I915_WRITE(PWRCTXA, 0);
8253 POSTING_READ(PWRCTXA);
8254
8255 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8256 POSTING_READ(RSTDBYCTL);
8257 }
8258
Chris Wilson99507302011-02-24 09:42:52 +00008259 ironlake_teardown_rc6(dev);
Chris Wilsonac668082011-02-09 16:15:32 +00008260}
8261
8262static int ironlake_setup_rc6(struct drm_device *dev)
8263{
8264 struct drm_i915_private *dev_priv = dev->dev_private;
8265
8266 if (dev_priv->renderctx == NULL)
8267 dev_priv->renderctx = intel_alloc_context_page(dev);
8268 if (!dev_priv->renderctx)
8269 return -ENOMEM;
8270
8271 if (dev_priv->pwrctx == NULL)
8272 dev_priv->pwrctx = intel_alloc_context_page(dev);
8273 if (!dev_priv->pwrctx) {
8274 ironlake_teardown_rc6(dev);
8275 return -ENOMEM;
8276 }
8277
8278 return 0;
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008279}
8280
8281void ironlake_enable_rc6(struct drm_device *dev)
8282{
8283 struct drm_i915_private *dev_priv = dev->dev_private;
8284 int ret;
8285
Chris Wilsonac668082011-02-09 16:15:32 +00008286 /* rc6 disabled by default due to repeated reports of hanging during
8287 * boot and resume.
8288 */
8289 if (!i915_enable_rc6)
8290 return;
8291
Ben Widawsky2c34b852011-03-19 18:14:26 -07008292 mutex_lock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00008293 ret = ironlake_setup_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008294 if (ret) {
8295 mutex_unlock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00008296 return;
Ben Widawsky2c34b852011-03-19 18:14:26 -07008297 }
Chris Wilsonac668082011-02-09 16:15:32 +00008298
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008299 /*
8300 * GPU can automatically power down the render unit if given a page
8301 * to save state.
8302 */
8303 ret = BEGIN_LP_RING(6);
8304 if (ret) {
Chris Wilsonac668082011-02-09 16:15:32 +00008305 ironlake_teardown_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008306 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008307 return;
8308 }
Chris Wilsonac668082011-02-09 16:15:32 +00008309
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008310 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8311 OUT_RING(MI_SET_CONTEXT);
8312 OUT_RING(dev_priv->renderctx->gtt_offset |
8313 MI_MM_SPACE_GTT |
8314 MI_SAVE_EXT_STATE_EN |
8315 MI_RESTORE_EXT_STATE_EN |
8316 MI_RESTORE_INHIBIT);
8317 OUT_RING(MI_SUSPEND_FLUSH);
8318 OUT_RING(MI_NOOP);
8319 OUT_RING(MI_FLUSH);
8320 ADVANCE_LP_RING();
8321
Ben Widawsky4a246cf2011-03-19 18:14:28 -07008322 /*
8323 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8324 * does an implicit flush, combined with MI_FLUSH above, it should be
8325 * safe to assume that renderctx is valid
8326 */
8327 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8328 if (ret) {
8329 DRM_ERROR("failed to enable ironlake power power savings\n");
8330 ironlake_teardown_rc6(dev);
8331 mutex_unlock(&dev->struct_mutex);
8332 return;
8333 }
8334
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008335 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8336 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008337 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008338}
8339
Jesse Barnes645c62a2011-05-11 09:49:31 -07008340void intel_init_clock_gating(struct drm_device *dev)
8341{
8342 struct drm_i915_private *dev_priv = dev->dev_private;
8343
8344 dev_priv->display.init_clock_gating(dev);
8345
8346 if (dev_priv->display.init_pch_clock_gating)
8347 dev_priv->display.init_pch_clock_gating(dev);
8348}
Chris Wilsonac668082011-02-09 16:15:32 +00008349
Jesse Barnese70236a2009-09-21 10:42:27 -07008350/* Set up chip specific display functions */
8351static void intel_init_display(struct drm_device *dev)
8352{
8353 struct drm_i915_private *dev_priv = dev->dev_private;
8354
8355 /* We always want a DPMS function */
Eric Anholtf564048e2011-03-30 13:01:02 -07008356 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008357 dev_priv->display.dpms = ironlake_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07008358 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008359 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008360 } else {
Jesse Barnese70236a2009-09-21 10:42:27 -07008361 dev_priv->display.dpms = i9xx_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07008362 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008363 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008364 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008365
Adam Jacksonee5382a2010-04-23 11:17:39 -04008366 if (I915_HAS_FBC(dev)) {
Yuanhan Liu9c04f012010-12-15 15:42:32 +08008367 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08008368 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8369 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8370 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8371 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07008372 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8373 dev_priv->display.enable_fbc = g4x_enable_fbc;
8374 dev_priv->display.disable_fbc = g4x_disable_fbc;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008375 } else if (IS_CRESTLINE(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008376 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8377 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8378 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8379 }
Jesse Barnes74dff282009-09-14 15:39:40 -07008380 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07008381 }
8382
8383 /* Returns the core display clock speed */
Akshay Joshi0206e352011-08-16 15:34:10 -04008384 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07008385 dev_priv->display.get_display_clock_speed =
8386 i945_get_display_clock_speed;
8387 else if (IS_I915G(dev))
8388 dev_priv->display.get_display_clock_speed =
8389 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008390 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008391 dev_priv->display.get_display_clock_speed =
8392 i9xx_misc_get_display_clock_speed;
8393 else if (IS_I915GM(dev))
8394 dev_priv->display.get_display_clock_speed =
8395 i915gm_get_display_clock_speed;
8396 else if (IS_I865G(dev))
8397 dev_priv->display.get_display_clock_speed =
8398 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02008399 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008400 dev_priv->display.get_display_clock_speed =
8401 i855_get_display_clock_speed;
8402 else /* 852, 830 */
8403 dev_priv->display.get_display_clock_speed =
8404 i830_get_display_clock_speed;
8405
8406 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008407 if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes645c62a2011-05-11 09:49:31 -07008408 if (HAS_PCH_IBX(dev))
8409 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8410 else if (HAS_PCH_CPT(dev))
8411 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8412
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01008413 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008414 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8415 dev_priv->display.update_wm = ironlake_update_wm;
8416 else {
8417 DRM_DEBUG_KMS("Failed to get proper latency. "
8418 "Disable CxSR\n");
8419 dev_priv->display.update_wm = NULL;
8420 }
Jesse Barnes674cf962011-04-28 14:27:04 -07008421 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008422 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008423 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08008424 } else if (IS_GEN6(dev)) {
8425 if (SNB_READ_WM0_LATENCY()) {
8426 dev_priv->display.update_wm = sandybridge_update_wm;
8427 } else {
8428 DRM_DEBUG_KMS("Failed to read display plane latency. "
8429 "Disable CxSR\n");
8430 dev_priv->display.update_wm = NULL;
8431 }
Jesse Barnes674cf962011-04-28 14:27:04 -07008432 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008433 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008434 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07008435 } else if (IS_IVYBRIDGE(dev)) {
8436 /* FIXME: detect B0+ stepping and use auto training */
8437 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Jesse Barnesfe100d42011-04-28 14:29:45 -07008438 if (SNB_READ_WM0_LATENCY()) {
8439 dev_priv->display.update_wm = sandybridge_update_wm;
8440 } else {
8441 DRM_DEBUG_KMS("Failed to read display plane latency. "
8442 "Disable CxSR\n");
8443 dev_priv->display.update_wm = NULL;
8444 }
Jesse Barnes28963a32011-05-11 09:42:30 -07008445 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008446 dev_priv->display.write_eld = ironlake_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008447 } else
8448 dev_priv->display.update_wm = NULL;
8449 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08008450 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08008451 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08008452 dev_priv->fsb_freq,
8453 dev_priv->mem_freq)) {
8454 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08008455 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08008456 "disabling CxSR\n",
Akshay Joshi0206e352011-08-16 15:34:10 -04008457 (dev_priv->is_ddr3 == 1) ? "3" : "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08008458 dev_priv->fsb_freq, dev_priv->mem_freq);
8459 /* Disable CxSR and never update its watermark again */
8460 pineview_disable_cxsr(dev);
8461 dev_priv->display.update_wm = NULL;
8462 } else
8463 dev_priv->display.update_wm = pineview_update_wm;
Jason Stubbs95e0ee92011-05-28 14:26:48 +10008464 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008465 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08008466 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07008467 dev_priv->display.update_wm = g4x_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008468 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8469 } else if (IS_GEN4(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008470 dev_priv->display.update_wm = i965_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008471 if (IS_CRESTLINE(dev))
8472 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8473 else if (IS_BROADWATER(dev))
8474 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8475 } else if (IS_GEN3(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008476 dev_priv->display.update_wm = i9xx_update_wm;
8477 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008478 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8479 } else if (IS_I865G(dev)) {
8480 dev_priv->display.update_wm = i830_update_wm;
8481 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8482 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04008483 } else if (IS_I85X(dev)) {
8484 dev_priv->display.update_wm = i9xx_update_wm;
8485 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008486 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
Jesse Barnese70236a2009-09-21 10:42:27 -07008487 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04008488 dev_priv->display.update_wm = i830_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008489 dev_priv->display.init_clock_gating = i830_init_clock_gating;
Adam Jackson8f4695e2010-04-16 18:20:57 -04008490 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008491 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8492 else
8493 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07008494 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008495
8496 /* Default just returns -ENODEV to indicate unsupported */
8497 dev_priv->display.queue_flip = intel_default_queue_flip;
8498
8499 switch (INTEL_INFO(dev)->gen) {
8500 case 2:
8501 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8502 break;
8503
8504 case 3:
8505 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8506 break;
8507
8508 case 4:
8509 case 5:
8510 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8511 break;
8512
8513 case 6:
8514 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8515 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008516 case 7:
8517 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8518 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008519 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008520}
8521
Jesse Barnesb690e962010-07-19 13:53:12 -07008522/*
8523 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8524 * resume, or other times. This quirk makes sure that's the case for
8525 * affected systems.
8526 */
Akshay Joshi0206e352011-08-16 15:34:10 -04008527static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07008528{
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530
8531 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8532 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8533}
8534
Keith Packard435793d2011-07-12 14:56:22 -07008535/*
8536 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8537 */
8538static void quirk_ssc_force_disable(struct drm_device *dev)
8539{
8540 struct drm_i915_private *dev_priv = dev->dev_private;
8541 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8542}
8543
Jesse Barnesb690e962010-07-19 13:53:12 -07008544struct intel_quirk {
8545 int device;
8546 int subsystem_vendor;
8547 int subsystem_device;
8548 void (*hook)(struct drm_device *dev);
8549};
8550
8551struct intel_quirk intel_quirks[] = {
8552 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8553 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8554 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04008555 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07008556
8557 /* Thinkpad R31 needs pipe A force quirk */
8558 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8559 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8560 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8561
8562 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8563 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8564 /* ThinkPad X40 needs pipe A force quirk */
8565
8566 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8567 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8568
8569 /* 855 & before need to leave pipe A & dpll A up */
8570 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8571 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07008572
8573 /* Lenovo U160 cannot use SSC on LVDS */
8574 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02008575
8576 /* Sony Vaio Y cannot use SSC on LVDS */
8577 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Jesse Barnesb690e962010-07-19 13:53:12 -07008578};
8579
8580static void intel_init_quirks(struct drm_device *dev)
8581{
8582 struct pci_dev *d = dev->pdev;
8583 int i;
8584
8585 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8586 struct intel_quirk *q = &intel_quirks[i];
8587
8588 if (d->device == q->device &&
8589 (d->subsystem_vendor == q->subsystem_vendor ||
8590 q->subsystem_vendor == PCI_ANY_ID) &&
8591 (d->subsystem_device == q->subsystem_device ||
8592 q->subsystem_device == PCI_ANY_ID))
8593 q->hook(dev);
8594 }
8595}
8596
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008597/* Disable the VGA plane that we never use */
8598static void i915_disable_vga(struct drm_device *dev)
8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601 u8 sr1;
8602 u32 vga_reg;
8603
8604 if (HAS_PCH_SPLIT(dev))
8605 vga_reg = CPU_VGACNTRL;
8606 else
8607 vga_reg = VGACNTRL;
8608
8609 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8610 outb(1, VGA_SR_INDEX);
8611 sr1 = inb(VGA_SR_DATA);
8612 outb(sr1 | 1<<5, VGA_SR_DATA);
8613 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8614 udelay(300);
8615
8616 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8617 POSTING_READ(vga_reg);
8618}
8619
Jesse Barnes79e53942008-11-07 14:24:08 -08008620void intel_modeset_init(struct drm_device *dev)
8621{
Jesse Barnes652c3932009-08-17 13:31:43 -07008622 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008623 int i;
8624
8625 drm_mode_config_init(dev);
8626
8627 dev->mode_config.min_width = 0;
8628 dev->mode_config.min_height = 0;
8629
8630 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8631
Jesse Barnesb690e962010-07-19 13:53:12 -07008632 intel_init_quirks(dev);
8633
Jesse Barnese70236a2009-09-21 10:42:27 -07008634 intel_init_display(dev);
8635
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008636 if (IS_GEN2(dev)) {
8637 dev->mode_config.max_width = 2048;
8638 dev->mode_config.max_height = 2048;
8639 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07008640 dev->mode_config.max_width = 4096;
8641 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08008642 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008643 dev->mode_config.max_width = 8192;
8644 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08008645 }
Chris Wilson35c30472010-12-22 14:07:12 +00008646 dev->mode_config.fb_base = dev->agp->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08008647
Zhao Yakui28c97732009-10-09 11:39:41 +08008648 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10008649 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08008650
Dave Airliea3524f12010-06-06 18:59:41 +10008651 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008652 intel_crtc_init(dev, i);
8653 }
8654
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008655 /* Just disable it once at startup */
8656 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008657 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07008658
Jesse Barnes645c62a2011-05-11 09:49:31 -07008659 intel_init_clock_gating(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008660
Jesse Barnes7648fa92010-05-20 14:28:11 -07008661 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08008662 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07008663 intel_init_emon(dev);
8664 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08008665
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07008666 if (IS_GEN6(dev) || IS_GEN7(dev)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008667 gen6_enable_rps(dev_priv);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07008668 gen6_update_ring_freq(dev_priv);
8669 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008670
Jesse Barnes652c3932009-08-17 13:31:43 -07008671 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8672 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8673 (unsigned long)dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01008674}
8675
8676void intel_modeset_gem_init(struct drm_device *dev)
8677{
8678 if (IS_IRONLAKE_M(dev))
8679 ironlake_enable_rc6(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02008680
8681 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008682}
8683
8684void intel_modeset_cleanup(struct drm_device *dev)
8685{
Jesse Barnes652c3932009-08-17 13:31:43 -07008686 struct drm_i915_private *dev_priv = dev->dev_private;
8687 struct drm_crtc *crtc;
8688 struct intel_crtc *intel_crtc;
8689
Keith Packardf87ea762010-10-03 19:36:26 -07008690 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07008691 mutex_lock(&dev->struct_mutex);
8692
Jesse Barnes723bfd72010-10-07 16:01:13 -07008693 intel_unregister_dsm_handler();
8694
8695
Jesse Barnes652c3932009-08-17 13:31:43 -07008696 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8697 /* Skip inactive CRTCs */
8698 if (!crtc->fb)
8699 continue;
8700
8701 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02008702 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07008703 }
8704
Chris Wilson973d04f2011-07-08 12:22:37 +01008705 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07008706
Jesse Barnesf97108d2010-01-29 11:27:07 -08008707 if (IS_IRONLAKE_M(dev))
8708 ironlake_disable_drps(dev);
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07008709 if (IS_GEN6(dev) || IS_GEN7(dev))
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008710 gen6_disable_rps(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008711
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008712 if (IS_IRONLAKE_M(dev))
8713 ironlake_disable_rc6(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00008714
Kristian Høgsberg69341a52009-11-11 12:19:17 -05008715 mutex_unlock(&dev->struct_mutex);
8716
Daniel Vetter6c0d93502010-08-20 18:26:46 +02008717 /* Disable the irq before mode object teardown, for the irq might
8718 * enqueue unpin/hotplug work. */
8719 drm_irq_uninstall(dev);
8720 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetter6fdd4d92011-09-08 14:00:22 +02008721 cancel_work_sync(&dev_priv->rps_work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02008722
Chris Wilson1630fe72011-07-08 12:22:42 +01008723 /* flush any delayed tasks or pending work */
8724 flush_scheduled_work();
8725
Daniel Vetter3dec0092010-08-20 21:40:52 +02008726 /* Shut off idle work before the crtcs get freed. */
8727 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8728 intel_crtc = to_intel_crtc(crtc);
8729 del_timer_sync(&intel_crtc->idle_timer);
8730 }
8731 del_timer_sync(&dev_priv->idle_timer);
8732 cancel_work_sync(&dev_priv->idle_work);
8733
Jesse Barnes79e53942008-11-07 14:24:08 -08008734 drm_mode_config_cleanup(dev);
8735}
8736
Dave Airlie28d52042009-09-21 14:33:58 +10008737/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08008738 * Return which encoder is currently attached for connector.
8739 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01008740struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08008741{
Chris Wilsondf0e9242010-09-09 16:20:55 +01008742 return &intel_attached_encoder(connector)->base;
8743}
Jesse Barnes79e53942008-11-07 14:24:08 -08008744
Chris Wilsondf0e9242010-09-09 16:20:55 +01008745void intel_connector_attach_encoder(struct intel_connector *connector,
8746 struct intel_encoder *encoder)
8747{
8748 connector->encoder = encoder;
8749 drm_mode_connector_attach_encoder(&connector->base,
8750 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008751}
Dave Airlie28d52042009-09-21 14:33:58 +10008752
8753/*
8754 * set vga decode state - true == enable VGA decode
8755 */
8756int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8757{
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 u16 gmch_ctrl;
8760
8761 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8762 if (state)
8763 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8764 else
8765 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8766 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8767 return 0;
8768}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008769
8770#ifdef CONFIG_DEBUG_FS
8771#include <linux/seq_file.h>
8772
8773struct intel_display_error_state {
8774 struct intel_cursor_error_state {
8775 u32 control;
8776 u32 position;
8777 u32 base;
8778 u32 size;
8779 } cursor[2];
8780
8781 struct intel_pipe_error_state {
8782 u32 conf;
8783 u32 source;
8784
8785 u32 htotal;
8786 u32 hblank;
8787 u32 hsync;
8788 u32 vtotal;
8789 u32 vblank;
8790 u32 vsync;
8791 } pipe[2];
8792
8793 struct intel_plane_error_state {
8794 u32 control;
8795 u32 stride;
8796 u32 size;
8797 u32 pos;
8798 u32 addr;
8799 u32 surface;
8800 u32 tile_offset;
8801 } plane[2];
8802};
8803
8804struct intel_display_error_state *
8805intel_display_capture_error_state(struct drm_device *dev)
8806{
Akshay Joshi0206e352011-08-16 15:34:10 -04008807 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008808 struct intel_display_error_state *error;
8809 int i;
8810
8811 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8812 if (error == NULL)
8813 return NULL;
8814
8815 for (i = 0; i < 2; i++) {
8816 error->cursor[i].control = I915_READ(CURCNTR(i));
8817 error->cursor[i].position = I915_READ(CURPOS(i));
8818 error->cursor[i].base = I915_READ(CURBASE(i));
8819
8820 error->plane[i].control = I915_READ(DSPCNTR(i));
8821 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8822 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04008823 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00008824 error->plane[i].addr = I915_READ(DSPADDR(i));
8825 if (INTEL_INFO(dev)->gen >= 4) {
8826 error->plane[i].surface = I915_READ(DSPSURF(i));
8827 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8828 }
8829
8830 error->pipe[i].conf = I915_READ(PIPECONF(i));
8831 error->pipe[i].source = I915_READ(PIPESRC(i));
8832 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8833 error->pipe[i].hblank = I915_READ(HBLANK(i));
8834 error->pipe[i].hsync = I915_READ(HSYNC(i));
8835 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8836 error->pipe[i].vblank = I915_READ(VBLANK(i));
8837 error->pipe[i].vsync = I915_READ(VSYNC(i));
8838 }
8839
8840 return error;
8841}
8842
8843void
8844intel_display_print_error_state(struct seq_file *m,
8845 struct drm_device *dev,
8846 struct intel_display_error_state *error)
8847{
8848 int i;
8849
8850 for (i = 0; i < 2; i++) {
8851 seq_printf(m, "Pipe [%d]:\n", i);
8852 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8853 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8854 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8855 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8856 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8857 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8858 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8859 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8860
8861 seq_printf(m, "Plane [%d]:\n", i);
8862 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8863 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8864 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8865 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8866 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8867 if (INTEL_INFO(dev)->gen >= 4) {
8868 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8869 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8870 }
8871
8872 seq_printf(m, "Cursor [%d]:\n", i);
8873 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8874 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8875 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8876 }
8877}
8878#endif