blob: b4133fe2f068ffc9bdb3e2908f34472bde161942 [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien Georgeb0785692025-04-02 12:47:48 +110034#if defined(CHECK_DEVID)
35#error "CHECK_DEVID no longer supported, use MICROPY_HW_SPIFLASH_DETECT_DEVICE instead"
36#endif
37
Damien George4e487002018-03-02 16:01:18 +110038#define QSPI_QE_MASK (0x02)
39#define USE_WR_DELAY (1)
40
41#define CMD_WRSR (0x01)
42#define CMD_WRITE (0x02)
43#define CMD_READ (0x03)
44#define CMD_RDSR (0x05)
45#define CMD_WREN (0x06)
46#define CMD_SEC_ERASE (0x20)
47#define CMD_RDCR (0x35)
48#define CMD_RD_DEVID (0x9f)
49#define CMD_CHIP_ERASE (0xc7)
50#define CMD_C4READ (0xeb)
iabdalkaderb5e80fa2024-11-29 16:56:20 +010051#define CMD_RSTEN (0x66)
52#define CMD_RESET (0x99)
Damien George4e487002018-03-02 16:01:18 +110053
Andrew Leech30501d32020-01-28 14:59:05 +110054// 32 bit addressing commands
55#define CMD_WRITE_32 (0x12)
56#define CMD_READ_32 (0x13)
57#define CMD_SEC_ERASE_32 (0x21)
58#define CMD_C4READ_32 (0xec)
59
Damien George784e0232017-01-24 16:56:03 +110060#define WAIT_SR_TIMEOUT (1000000)
61
62#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100063#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110064
Angus Grattondecf8e62024-02-27 15:32:29 +110065static void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110066 const mp_spiflash_config_t *c = self->config;
67 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110068 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE, 0);
Damien George4e487002018-03-02 16:01:18 +110069 }
Damien George784e0232017-01-24 16:56:03 +110070}
71
Angus Grattondecf8e62024-02-27 15:32:29 +110072static void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110073 const mp_spiflash_config_t *c = self->config;
74 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110075 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE, 0);
76 }
77}
78
79static void mp_spiflash_notify_modified(mp_spiflash_t *self, uint32_t addr, uint32_t len) {
80 const mp_spiflash_config_t *c = self->config;
81 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
82 uintptr_t arg[2] = { addr, len };
83 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_MEMORY_MODIFIED, (uintptr_t)&arg[0]);
Damien George4e487002018-03-02 16:01:18 +110084 }
Damien George784e0232017-01-24 16:56:03 +110085}
86
Angus Grattondecf8e62024-02-27 15:32:29 +110087static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110088 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110089 const mp_spiflash_config_t *c = self->config;
90 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
91 // Note: len/data are unused for standard SPI
92 mp_hal_pin_write(c->bus.u_spi.cs, 0);
93 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
94 mp_hal_pin_write(c->bus.u_spi.cs, 1);
95 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110096 ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
Damien George4e487002018-03-02 16:01:18 +110097 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +110098 return ret;
Damien George4e487002018-03-02 16:01:18 +110099}
100
Angus Grattondecf8e62024-02-27 15:32:29 +1100101static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100102 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +1100103 const mp_spiflash_config_t *c = self->config;
104 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Andrew Leech30501d32020-01-28 14:59:05 +1100105 uint8_t buf[5] = {cmd, 0};
106 uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr);
Damien George4e487002018-03-02 16:01:18 +1100107 mp_hal_pin_write(c->bus.u_spi.cs, 0);
Andrew Leech30501d32020-01-28 14:59:05 +1100108 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL);
109 if (len && (src != NULL)) {
Damien George4e487002018-03-02 16:01:18 +1100110 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
Andrew Leech30501d32020-01-28 14:59:05 +1100111 } else if (len && (dest != NULL)) {
112 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
Damien George4e487002018-03-02 16:01:18 +1100113 }
Andrew Leech30501d32020-01-28 14:59:05 +1100114
Damien George4e487002018-03-02 16:01:18 +1100115 mp_hal_pin_write(c->bus.u_spi.cs, 1);
116 } else {
Andrew Leech30501d32020-01-28 14:59:05 +1100117 if (dest != NULL) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100118 ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, len, dest);
Andrew Leech30501d32020-01-28 14:59:05 +1100119 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100120 ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
Andrew Leech30501d32020-01-28 14:59:05 +1100121 }
Damien George4e487002018-03-02 16:01:18 +1100122 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100123 return ret;
Damien George4e487002018-03-02 16:01:18 +1100124}
125
Angus Grattondecf8e62024-02-27 15:32:29 +1100126static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100127 const mp_spiflash_config_t *c = self->config;
128 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George4e487002018-03-02 16:01:18 +1100129 mp_hal_pin_write(c->bus.u_spi.cs, 0);
130 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
Damien Georgeb042fd52022-12-09 12:28:54 +1100131 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)dest, (void*)dest);
Damien George4e487002018-03-02 16:01:18 +1100132 mp_hal_pin_write(c->bus.u_spi.cs, 1);
Damien Georgeb042fd52022-12-09 12:28:54 +1100133 return 0;
Damien George4e487002018-03-02 16:01:18 +1100134 } else {
Damien Georgeb042fd52022-12-09 12:28:54 +1100135 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest);
Damien George4e487002018-03-02 16:01:18 +1100136 }
137}
138
Angus Grattondecf8e62024-02-27 15:32:29 +1100139static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100140 const mp_spiflash_config_t *c = self->config;
Andrew Leech30501d32020-01-28 14:59:05 +1100141 uint8_t cmd;
Damien George4e487002018-03-02 16:01:18 +1100142 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George54f16942022-06-01 18:50:43 +1000143 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ;
Damien George4e487002018-03-02 16:01:18 +1100144 } else {
Damien George54f16942022-06-01 18:50:43 +1000145 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ;
Damien George4e487002018-03-02 16:01:18 +1100146 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100147 return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest);
Damien George4e487002018-03-02 16:01:18 +1100148}
149
Angus Grattondecf8e62024-02-27 15:32:29 +1100150static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100151 return mp_spiflash_write_cmd_data(self, cmd, 0, 0);
Damien George4e487002018-03-02 16:01:18 +1100152}
153
Angus Grattondecf8e62024-02-27 15:32:29 +1100154static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100155 do {
Damien Georgeb042fd52022-12-09 12:28:54 +1100156 uint32_t sr;
157 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
158 if (ret != 0) {
159 return ret;
160 }
Damien George4e487002018-03-02 16:01:18 +1100161 if ((sr & mask) == val) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100162 return 0; // success
Damien George784e0232017-01-24 16:56:03 +1100163 }
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100164 } while (timeout--);
165
166 return -MP_ETIMEDOUT;
Damien George784e0232017-01-24 16:56:03 +1100167}
168
Angus Grattondecf8e62024-02-27 15:32:29 +1100169static int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100170 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
171}
172
Angus Grattondecf8e62024-02-27 15:32:29 +1100173static int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100174 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
175}
176
Damien George8cde5fa2019-07-03 01:03:25 +1000177static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) {
178 mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake
179}
180
Damien George4e487002018-03-02 16:01:18 +1100181void mp_spiflash_init(mp_spiflash_t *self) {
182 self->flags = 0;
183
184 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
185 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
186 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100187 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100188 } else {
Damien Georgec61e8592025-03-19 15:47:35 +1100189 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, 0);
Damien George4e487002018-03-02 16:01:18 +1100190 }
191
192 mp_spiflash_acquire_bus(self);
193
Damien George8cde5fa2019-07-03 01:03:25 +1000194 // Ensure SPI flash is out of sleep mode
195 mp_spiflash_deepsleep_internal(self, 0);
196
iabdalkaderb5e80fa2024-11-29 16:56:20 +0100197 // Software reset.
198 #if MICROPY_HW_SPIFLASH_SOFT_RESET
199 mp_spiflash_write_cmd(self, CMD_RSTEN);
200 mp_spiflash_write_cmd(self, CMD_RESET);
201 mp_spiflash_wait_wip0(self);
202 mp_hal_delay_ms(1);
203 #endif
204
Damien Georgeb0785692025-04-02 12:47:48 +1100205 #if MICROPY_HW_SPIFLASH_DETECT_DEVICE
206 // Attempt to detect SPI flash based on its JEDEC id.
Damien Georgeb042fd52022-12-09 12:28:54 +1100207 uint32_t devid;
208 int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
Damien Georgeb0785692025-04-02 12:47:48 +1100209 ret = mp_spiflash_detect(self, ret, devid);
210 if (ret != 0) {
211 // Could not read device id.
Damien Georgeb042fd52022-12-09 12:28:54 +1100212 mp_spiflash_release_bus(self);
213 return;
Damien George4e487002018-03-02 16:01:18 +1100214 }
215 #endif
216
217 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
218 // Set QE bit
Damien Georgeb042fd52022-12-09 12:28:54 +1100219 uint32_t sr = 0, cr = 0;
220 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
221 if (ret == 0) {
222 ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
223 }
224 uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
225 if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
Damien Georgecc34b082018-03-11 11:25:38 +1100226 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100227 mp_spiflash_write_cmd(self, CMD_WREN);
228 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
229 mp_spiflash_wait_wip0(self);
230 }
231 }
232
233 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100234}
235
Damien George8cde5fa2019-07-03 01:03:25 +1000236void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) {
237 if (value) {
238 mp_spiflash_acquire_bus(self);
239 }
240 mp_spiflash_deepsleep_internal(self, value);
241 if (!value) {
242 mp_spiflash_release_bus(self);
243 }
244}
245
Angus Grattondecf8e62024-02-27 15:32:29 +1100246static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100247 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100248 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100249 ret = mp_spiflash_write_cmd(self, CMD_WREN);
250 if (ret != 0) {
251 return ret;
252 }
Damien George784e0232017-01-24 16:56:03 +1100253
254 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100255 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100256 if (ret != 0) {
257 return ret;
258 }
259
260 // erase the sector
Damien George54f16942022-06-01 18:50:43 +1000261 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100262 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL);
263 if (ret != 0) {
264 return ret;
265 }
Damien George784e0232017-01-24 16:56:03 +1100266
267 // wait WIP=0
268 return mp_spiflash_wait_wip0(self);
269}
270
Angus Grattondecf8e62024-02-27 15:32:29 +1100271static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100272 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100273 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100274 ret = mp_spiflash_write_cmd(self, CMD_WREN);
275 if (ret != 0) {
276 return ret;
277 }
Damien George784e0232017-01-24 16:56:03 +1100278
279 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100280 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100281 if (ret != 0) {
282 return ret;
283 }
284
285 // write the page
Damien George54f16942022-06-01 18:50:43 +1000286 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100287 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL);
288 if (ret != 0) {
289 return ret;
290 }
Damien George784e0232017-01-24 16:56:03 +1100291
292 // wait WIP=0
293 return mp_spiflash_wait_wip0(self);
294}
295
Damien Georgecc5a9402018-06-07 15:36:27 +1000296/******************************************************************************/
Damien Georgeb78ca322018-06-07 15:39:46 +1000297// Interface functions that go direct to the SPI flash device
298
299int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
300 mp_spiflash_acquire_bus(self);
301 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien Georgec61e8592025-03-19 15:47:35 +1100302 mp_spiflash_notify_modified(self, addr, SECTOR_SIZE);
Damien Georgeb78ca322018-06-07 15:39:46 +1000303 mp_spiflash_release_bus(self);
304 return ret;
305}
306
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100307int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000308 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100309 return 0;
Damien Georgeb78ca322018-06-07 15:39:46 +1000310 }
311 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100312 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien Georgeb78ca322018-06-07 15:39:46 +1000313 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100314 return ret;
Damien Georgeb78ca322018-06-07 15:39:46 +1000315}
316
317int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien Georgec61e8592025-03-19 15:47:35 +1100318 uint32_t orig_addr = addr;
319 uint32_t orig_len = len;
Damien Georgeb78ca322018-06-07 15:39:46 +1000320 mp_spiflash_acquire_bus(self);
321 int ret = 0;
322 uint32_t offset = addr & (PAGE_SIZE - 1);
323 while (len) {
324 size_t rest = PAGE_SIZE - offset;
325 if (rest > len) {
326 rest = len;
327 }
328 ret = mp_spiflash_write_page(self, addr, rest, src);
329 if (ret != 0) {
330 break;
331 }
332 len -= rest;
333 addr += rest;
334 src += rest;
335 offset = 0;
336 }
Damien Georgec61e8592025-03-19 15:47:35 +1100337 mp_spiflash_notify_modified(self, orig_addr, orig_len);
Damien Georgeb78ca322018-06-07 15:39:46 +1000338 mp_spiflash_release_bus(self);
339 return ret;
340}
341
342/******************************************************************************/
Damien Georgecc5a9402018-06-07 15:36:27 +1000343// Interface functions that use the cache
Damien Georgec61e8592025-03-19 15:47:35 +1100344//
345// These functions do not call mp_spiflash_notify_modified(), so shouldn't be
346// used for memory-mapped flash (for example).
Damien Georgecc5a9402018-06-07 15:36:27 +1000347
Damien Georgee43a74a2020-12-17 16:59:54 +1100348#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
349
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100350int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100351 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100352 return 0;
Damien George4e487002018-03-02 16:01:18 +1100353 }
Damien George784e0232017-01-24 16:56:03 +1100354 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000355 mp_spiflash_cache_t *cache = self->config->cache;
356 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100357 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100358 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000359 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100360 // Read straddles current buffer
361 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000362 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100363 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000364 rest = cache->block * SECTOR_SIZE - addr;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100365 int ret = mp_spiflash_read_data(self, addr, rest, dest);
366 if (ret != 0) {
367 mp_spiflash_release_bus(self);
368 return ret;
369 }
Damien George4e487002018-03-02 16:01:18 +1100370 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100371 dest += rest;
372 addr += rest;
373 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100374 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100375 rest = SECTOR_SIZE - offset;
376 if (rest > len) {
377 rest = len;
378 }
Damien George86fe73b2018-06-07 14:09:10 +1000379 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100380 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100381 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100382 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100383 return 0;
Damien George4e487002018-03-02 16:01:18 +1100384 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100385 dest += rest;
386 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100387 }
Damien George4e487002018-03-02 16:01:18 +1100388 }
389 // Read rest direct from flash
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100390 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100391 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100392 return ret;
Damien George784e0232017-01-24 16:56:03 +1100393}
394
Angus Grattondecf8e62024-02-27 15:32:29 +1100395static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100396 #if USE_WR_DELAY
397 if (!(self->flags & 1)) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100398 return 0;
Damien George4e487002018-03-02 16:01:18 +1100399 }
Damien George784e0232017-01-24 16:56:03 +1100400
Damien George4e487002018-03-02 16:01:18 +1100401 self->flags &= ~1;
402
Damien George86fe73b2018-06-07 14:09:10 +1000403 mp_spiflash_cache_t *cache = self->config->cache;
404
Damien George4e487002018-03-02 16:01:18 +1100405 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000406 int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100407 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100408 return ret;
Damien George4e487002018-03-02 16:01:18 +1100409 }
410
411 // Write
412 for (int i = 0; i < 16; i += 1) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000413 uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
414 int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100415 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100416 return ret;
Damien George4e487002018-03-02 16:01:18 +1100417 }
418 }
419 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100420 return 0;
Damien George4e487002018-03-02 16:01:18 +1100421}
422
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100423int mp_spiflash_cache_flush(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100424 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100425 int ret = mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100426 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100427 return ret;
Damien George4e487002018-03-02 16:01:18 +1100428}
429
Angus Grattondecf8e62024-02-27 15:32:29 +1100430static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100431 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100432 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100433 uint32_t sec = addr >> 12;
434 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100435
Damien George4e487002018-03-02 16:01:18 +1100436 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000437 if (offset + len > SECTOR_SIZE) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000438 printf("mp_spiflash_cached_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100439 return -MP_EIO;
440 }
441
Damien George86fe73b2018-06-07 14:09:10 +1000442 mp_spiflash_cache_t *cache = self->config->cache;
443
Damien George4e487002018-03-02 16:01:18 +1100444 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000445 if (cache->user != self) {
446 if (cache->user != NULL) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000447 mp_spiflash_cache_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100448 }
Damien George86fe73b2018-06-07 14:09:10 +1000449 cache->user = self;
450 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100451 }
452
Damien George86fe73b2018-06-07 14:09:10 +1000453 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100454 // Read sector
455 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000456 if (cache->block != 0xffffffff) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100457 int ret = mp_spiflash_cache_flush_internal(self);
458 if (ret != 0) {
459 return ret;
460 }
Damien George4e487002018-03-02 16:01:18 +1100461 }
462 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100463 int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
464 if (ret != 0) {
465 return ret;
466 }
Damien George4e487002018-03-02 16:01:18 +1100467 }
Damien George784e0232017-01-24 16:56:03 +1100468
Damien George4e487002018-03-02 16:01:18 +1100469 #if USE_WR_DELAY
470
Damien George86fe73b2018-06-07 14:09:10 +1000471 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100472 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000473 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100474 // And mark dirty
475 self->flags |= 1;
476
477 #else
478
479 uint32_t dirty = 0;
480 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000481 if (cache->buf[offset + i] != src[i]) {
482 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100483 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000484 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien George4e487002018-03-02 16:01:18 +1100485 if (ret != 0) {
486 return ret;
487 }
488 dirty = 0xffff;
489 break;
490 } else {
491 dirty |= (1 << ((offset + i) >> 8));
492 }
Damien George784e0232017-01-24 16:56:03 +1100493 }
494 }
495
Damien George86fe73b2018-06-07 14:09:10 +1000496 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100497 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000498 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100499
500 // Write sector in pages of 256 bytes
501 for (size_t i = 0; i < 16; ++i) {
502 if (dirty & (1 << i)) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000503 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100504 if (ret != 0) {
505 return ret;
506 }
507 }
508 }
509
510 #endif
511
Damien George784e0232017-01-24 16:56:03 +1100512 return 0; // success
513}
Damien George4e487002018-03-02 16:01:18 +1100514
Damien Georgecc5a9402018-06-07 15:36:27 +1000515int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100516 uint32_t bis = addr / SECTOR_SIZE;
517 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
518
519 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100520
Damien George86fe73b2018-06-07 14:09:10 +1000521 mp_spiflash_cache_t *cache = self->config->cache;
522 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100523 // Write straddles current buffer
524 uint32_t pre;
525 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000526 if (cache->block * SECTOR_SIZE >= addr) {
527 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100528 offset = 0;
529 } else {
530 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000531 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100532 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100533
534 // Write buffered part first
535 uint32_t len_in_buf = len - pre;
536 len = 0;
537 if (len_in_buf > SECTOR_SIZE - offset) {
538 len = len_in_buf - (SECTOR_SIZE - offset);
539 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100540 }
Damien George86fe73b2018-06-07 14:09:10 +1000541 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100542 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100543
544 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100545 while (pre) {
546 int rest = pre & (SECTOR_SIZE - 1);
547 if (rest == 0) {
548 rest = SECTOR_SIZE;
549 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000550 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100551 if (ret != 0) {
552 mp_spiflash_release_bus(self);
553 return ret;
554 }
555 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100556 addr += rest;
557 pre -= rest;
558 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100559 src += len_in_buf;
560 addr += len_in_buf;
561
562 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100563 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100564
565 uint32_t offset = addr & (SECTOR_SIZE - 1);
566 while (len) {
567 int rest = SECTOR_SIZE - offset;
568 if (rest > len) {
569 rest = len;
570 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000571 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100572 if (ret != 0) {
573 mp_spiflash_release_bus(self);
574 return ret;
575 }
576 len -= rest;
577 addr += rest;
578 src += rest;
579 offset = 0;
580 }
581
Damien George4e487002018-03-02 16:01:18 +1100582 mp_spiflash_release_bus(self);
583 return 0;
584}
Damien Georgee43a74a2020-12-17 16:59:54 +1100585
586#endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE