blob: c7f333044d2f859ceedd4d6797ac07660746ba5d [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien George4e487002018-03-02 16:01:18 +110034#define QSPI_QE_MASK (0x02)
35#define USE_WR_DELAY (1)
36
37#define CMD_WRSR (0x01)
38#define CMD_WRITE (0x02)
39#define CMD_READ (0x03)
40#define CMD_RDSR (0x05)
41#define CMD_WREN (0x06)
42#define CMD_SEC_ERASE (0x20)
43#define CMD_RDCR (0x35)
44#define CMD_RD_DEVID (0x9f)
45#define CMD_CHIP_ERASE (0xc7)
46#define CMD_C4READ (0xeb)
47
Damien George784e0232017-01-24 16:56:03 +110048#define WAIT_SR_TIMEOUT (1000000)
49
50#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
51#define SECTOR_SIZE (4096) // size of erase sector
52
53// Note: this code is not reentrant with this shared buffer
Damien George4e487002018-03-02 16:01:18 +110054STATIC uint8_t buf[SECTOR_SIZE] __attribute__((aligned(4)));
55STATIC mp_spiflash_t *bufuser; // current user of buf
56STATIC uint32_t bufsec; // current sector stored in buf; 0xffffffff if invalid
Damien George784e0232017-01-24 16:56:03 +110057
58STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110059 const mp_spiflash_config_t *c = self->config;
60 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
61 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
62 }
Damien George784e0232017-01-24 16:56:03 +110063}
64
65STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110066 const mp_spiflash_config_t *c = self->config;
67 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
68 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
69 }
Damien George784e0232017-01-24 16:56:03 +110070}
71
Damien George4e487002018-03-02 16:01:18 +110072STATIC void mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
73 const mp_spiflash_config_t *c = self->config;
74 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
75 // Note: len/data are unused for standard SPI
76 mp_hal_pin_write(c->bus.u_spi.cs, 0);
77 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
78 mp_hal_pin_write(c->bus.u_spi.cs, 1);
79 } else {
80 c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
81 }
82}
83
84STATIC void mp_spiflash_write_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
85 const mp_spiflash_config_t *c = self->config;
86 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
87 uint8_t buf[4] = {cmd, addr >> 16, addr >> 8, addr};
88 mp_hal_pin_write(c->bus.u_spi.cs, 0);
89 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
90 if (len) {
91 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
92 }
93 mp_hal_pin_write(c->bus.u_spi.cs, 1);
94 } else {
95 c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
96 }
97}
98
99STATIC uint32_t mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len) {
100 const mp_spiflash_config_t *c = self->config;
101 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
102 uint32_t buf;
103 mp_hal_pin_write(c->bus.u_spi.cs, 0);
104 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
105 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)&buf, (void*)&buf);
106 mp_hal_pin_write(c->bus.u_spi.cs, 1);
107 return buf;
108 } else {
109 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len);
110 }
111}
112
113STATIC void mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
114 const mp_spiflash_config_t *c = self->config;
115 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
116 uint8_t buf[4] = {CMD_READ, addr >> 16, addr >> 8, addr};
117 mp_hal_pin_write(c->bus.u_spi.cs, 0);
118 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
119 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
120 mp_hal_pin_write(c->bus.u_spi.cs, 1);
121 } else {
122 c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, CMD_C4READ, addr, len, dest);
123 }
124}
125
126STATIC void mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
127 mp_spiflash_write_cmd_data(self, cmd, 0, 0);
128}
129
130STATIC void mp_spiflash_write_cmd_addr(mp_spiflash_t *self, uint8_t cmd, uint32_t addr) {
131 mp_spiflash_write_cmd_addr_data(self, cmd, addr, 0, NULL);
Damien George784e0232017-01-24 16:56:03 +1100132}
133
134STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Damien George4e487002018-03-02 16:01:18 +1100135 uint8_t sr;
Damien George784e0232017-01-24 16:56:03 +1100136 for (; timeout; --timeout) {
Damien George4e487002018-03-02 16:01:18 +1100137 sr = mp_spiflash_read_cmd(self, CMD_RDSR, 1);
138 if ((sr & mask) == val) {
Damien George784e0232017-01-24 16:56:03 +1100139 break;
140 }
141 }
Damien George4e487002018-03-02 16:01:18 +1100142 if ((sr & mask) == val) {
Damien George784e0232017-01-24 16:56:03 +1100143 return 0; // success
144 } else if (timeout == 0) {
145 return -MP_ETIMEDOUT;
146 } else {
147 return -MP_EIO;
148 }
149}
150
151STATIC int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
152 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
153}
154
155STATIC int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
156 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
157}
158
Damien George4e487002018-03-02 16:01:18 +1100159void mp_spiflash_init(mp_spiflash_t *self) {
160 self->flags = 0;
161
162 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
163 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
164 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100165 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100166 } else {
167 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
168 }
169
170 mp_spiflash_acquire_bus(self);
171
172 #if defined(CHECK_DEVID)
173 // Validate device id
174 uint32_t devid = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3);
175 if (devid != CHECK_DEVID) {
176 return 0;
177 }
178 #endif
179
180 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
181 // Set QE bit
182 uint32_t data = (mp_spiflash_read_cmd(self, CMD_RDSR, 1) & 0xff)
183 | (mp_spiflash_read_cmd(self, CMD_RDCR, 1) & 0xff) << 8;
Damien Georgecc34b082018-03-11 11:25:38 +1100184 if (!(data & (QSPI_QE_MASK << 8))) {
185 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100186 mp_spiflash_write_cmd(self, CMD_WREN);
187 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
188 mp_spiflash_wait_wip0(self);
189 }
190 }
191
192 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100193}
194
195STATIC int mp_spiflash_erase_sector(mp_spiflash_t *self, uint32_t addr) {
196 // enable writes
197 mp_spiflash_write_cmd(self, CMD_WREN);
198
199 // wait WEL=1
200 int ret = mp_spiflash_wait_wel1(self);
201 if (ret != 0) {
202 return ret;
203 }
204
205 // erase the sector
Damien George4e487002018-03-02 16:01:18 +1100206 mp_spiflash_write_cmd_addr(self, CMD_SEC_ERASE, addr);
Damien George784e0232017-01-24 16:56:03 +1100207
208 // wait WIP=0
209 return mp_spiflash_wait_wip0(self);
210}
211
212STATIC int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, const uint8_t *src) {
213 // enable writes
214 mp_spiflash_write_cmd(self, CMD_WREN);
215
216 // wait WEL=1
217 int ret = mp_spiflash_wait_wel1(self);
218 if (ret != 0) {
219 return ret;
220 }
221
222 // write the page
Damien George4e487002018-03-02 16:01:18 +1100223 mp_spiflash_write_cmd_addr_data(self, CMD_WRITE, addr, PAGE_SIZE, src);
Damien George784e0232017-01-24 16:56:03 +1100224
225 // wait WIP=0
226 return mp_spiflash_wait_wip0(self);
227}
228
229void mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100230 if (len == 0) {
231 return;
232 }
Damien George784e0232017-01-24 16:56:03 +1100233 mp_spiflash_acquire_bus(self);
Damien George4e487002018-03-02 16:01:18 +1100234 if (bufuser == self && bufsec != 0xffffffff) {
235 uint32_t bis = addr / SECTOR_SIZE;
236 int rest = 0;
237 if (bis < bufsec) {
238 rest = bufsec * SECTOR_SIZE - addr;
239 if (rest > len) {
240 rest = len;
241 }
242 mp_spiflash_read_data(self, addr, rest, dest);
243 len -= rest;
244 if (len <= 0) {
245 mp_spiflash_release_bus(self);
246 return;
247 } else {
248 // Something from buffer...
249 addr = bufsec * SECTOR_SIZE;
250 dest += rest;
251 if (len > SECTOR_SIZE) {
252 rest = SECTOR_SIZE;
253 } else {
254 rest = len;
255 }
256 memcpy(dest, buf, rest);
257 len -= rest;
258 if (len <= 0) {
259 mp_spiflash_release_bus(self);
260 return;
261 }
262 dest += rest;
263 addr += rest;
264 }
265 } else if (bis == bufsec) {
266 uint32_t offset = addr & (SECTOR_SIZE-1);
267 rest = SECTOR_SIZE - offset;
268 if (rest > len) {
269 rest = len;
270 }
271 memcpy(dest, &buf[offset], rest);
272 len -= rest;
273 if (len <= 0) {
274 mp_spiflash_release_bus(self);
275 return;
276 }
277 }
278 dest += rest;
279 addr += rest;
280 }
281 // Read rest direct from flash
282 mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100283 mp_spiflash_release_bus(self);
284}
285
Damien George4e487002018-03-02 16:01:18 +1100286STATIC void mp_spiflash_flush_internal(mp_spiflash_t *self) {
287 #if USE_WR_DELAY
288 if (!(self->flags & 1)) {
289 return;
290 }
Damien George784e0232017-01-24 16:56:03 +1100291
Damien George4e487002018-03-02 16:01:18 +1100292 self->flags &= ~1;
293
294 // Erase sector
295 int ret = mp_spiflash_erase_sector(self, bufsec * SECTOR_SIZE);
296 if (ret != 0) {
297 return;
298 }
299
300 // Write
301 for (int i = 0; i < 16; i += 1) {
302 int ret = mp_spiflash_write_page(self, bufsec * SECTOR_SIZE + i * PAGE_SIZE, buf + i * PAGE_SIZE);
303 if (ret != 0) {
304 return;
305 }
306 }
307 #endif
308}
309
310void mp_spiflash_flush(mp_spiflash_t *self) {
311 mp_spiflash_acquire_bus(self);
312 mp_spiflash_flush_internal(self);
313 mp_spiflash_release_bus(self);
314}
315
316STATIC int mp_spiflash_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
317 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100318 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100319 uint32_t sec = addr >> 12;
320 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100321
Damien George4e487002018-03-02 16:01:18 +1100322 // Restriction for now, so we don't need to erase multiple pages
Damien George784e0232017-01-24 16:56:03 +1100323 if (offset + len > sizeof(buf)) {
Damien George4e487002018-03-02 16:01:18 +1100324 printf("mp_spiflash_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100325 return -MP_EIO;
326 }
327
Damien George4e487002018-03-02 16:01:18 +1100328 // Acquire the sector buffer
329 if (bufuser != self) {
330 if (bufuser != NULL) {
331 mp_spiflash_flush(bufuser);
332 }
333 bufuser = self;
334 bufsec = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100335 }
336
Damien George4e487002018-03-02 16:01:18 +1100337 if (bufsec != sec) {
338 // Read sector
339 #if USE_WR_DELAY
340 if (bufsec != 0xffffffff) {
341 mp_spiflash_flush_internal(self);
342 }
343 #endif
344 mp_spiflash_read_data(self, addr, SECTOR_SIZE, buf);
345 }
Damien George784e0232017-01-24 16:56:03 +1100346
Damien George4e487002018-03-02 16:01:18 +1100347 #if USE_WR_DELAY
348
349 bufsec = sec;
350 // Just copy to buffer
351 memcpy(buf + offset, src, len);
352 // And mark dirty
353 self->flags |= 1;
354
355 #else
356
357 uint32_t dirty = 0;
358 for (size_t i = 0; i < len; ++i) {
359 if (buf[offset + i] != src[i]) {
360 if (buf[offset + i] != 0xff) {
361 // Erase sector
362 int ret = mp_spiflash_erase_sector(self, addr);
363 if (ret != 0) {
364 return ret;
365 }
366 dirty = 0xffff;
367 break;
368 } else {
369 dirty |= (1 << ((offset + i) >> 8));
370 }
Damien George784e0232017-01-24 16:56:03 +1100371 }
372 }
373
Damien George4e487002018-03-02 16:01:18 +1100374 bufsec = sec;
375 // Copy new block into buffer
376 memcpy(buf + offset, src, len);
377
378 // Write sector in pages of 256 bytes
379 for (size_t i = 0; i < 16; ++i) {
380 if (dirty & (1 << i)) {
381 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, buf + i * PAGE_SIZE);
382 if (ret != 0) {
383 return ret;
384 }
385 }
386 }
387
388 #endif
389
Damien George784e0232017-01-24 16:56:03 +1100390 return 0; // success
391}
Damien George4e487002018-03-02 16:01:18 +1100392
393int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
394 uint32_t bis = addr / SECTOR_SIZE;
395 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
396
397 mp_spiflash_acquire_bus(self);
398 if (bufuser == self && bis <= bufsec && bie >= bufsec) {
399 // Current buffer affected, handle this part first
400 uint32_t taddr = (bufsec + 1) * SECTOR_SIZE;
401 int32_t offset = addr - bufsec * SECTOR_SIZE;
402 int32_t pre = bufsec * SECTOR_SIZE - addr;
403 if (offset < 0) {
404 offset = 0;
405 } else {
406 pre = 0;
407 }
408 int32_t rest = len - pre;
409 int32_t trail = 0;
410 if (rest > SECTOR_SIZE - offset) {
411 trail = rest - (SECTOR_SIZE - offset);
412 rest = SECTOR_SIZE - offset;
413 }
414 memcpy(&buf[offset], &src[pre], rest);
415 self->flags |= 1; // Mark dirty
416 if ((pre | trail) == 0) {
417 mp_spiflash_release_bus(self);
418 return 0;
419 }
420 const uint8_t *p = src;
421 while (pre) {
422 int rest = pre & (SECTOR_SIZE - 1);
423 if (rest == 0) {
424 rest = SECTOR_SIZE;
425 }
426 mp_spiflash_write_part(self, addr, rest, p);
427 p += rest;
428 addr += rest;
429 pre -= rest;
430 }
431 while (trail) {
432 int rest = trail;
433 if (rest > SECTOR_SIZE) {
434 rest = SECTOR_SIZE;
435 }
436 mp_spiflash_write_part(self, taddr, rest, src);
437 src += rest;
438 taddr += rest;
439 trail -= rest;
440 }
441 } else {
442 // Current buffer not affected, business as usual
443 uint32_t offset = addr & (SECTOR_SIZE - 1);
444 while (len) {
445 int rest = SECTOR_SIZE - offset;
446 if (rest > len) {
447 rest = len;
448 }
449 mp_spiflash_write_part(self, addr, rest, src);
450 len -= rest;
451 addr += rest;
452 src += rest;
453 offset = 0;
454 }
455 }
456 mp_spiflash_release_bus(self);
457 return 0;
458}