blob: e66153636b1fdf21593663fbf94ea75fe668a169 [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien George4e487002018-03-02 16:01:18 +110034#define QSPI_QE_MASK (0x02)
35#define USE_WR_DELAY (1)
36
37#define CMD_WRSR (0x01)
38#define CMD_WRITE (0x02)
39#define CMD_READ (0x03)
40#define CMD_RDSR (0x05)
41#define CMD_WREN (0x06)
42#define CMD_SEC_ERASE (0x20)
43#define CMD_RDCR (0x35)
44#define CMD_RD_DEVID (0x9f)
45#define CMD_CHIP_ERASE (0xc7)
46#define CMD_C4READ (0xeb)
47
Andrew Leech30501d32020-01-28 14:59:05 +110048// 32 bit addressing commands
49#define CMD_WRITE_32 (0x12)
50#define CMD_READ_32 (0x13)
51#define CMD_SEC_ERASE_32 (0x21)
52#define CMD_C4READ_32 (0xec)
53
Damien George784e0232017-01-24 16:56:03 +110054#define WAIT_SR_TIMEOUT (1000000)
55
56#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100057#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110058
Angus Grattondecf8e62024-02-27 15:32:29 +110059static void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110060 const mp_spiflash_config_t *c = self->config;
61 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
62 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
63 }
Damien George784e0232017-01-24 16:56:03 +110064}
65
Angus Grattondecf8e62024-02-27 15:32:29 +110066static void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110067 const mp_spiflash_config_t *c = self->config;
68 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
69 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
70 }
Damien George784e0232017-01-24 16:56:03 +110071}
72
Angus Grattondecf8e62024-02-27 15:32:29 +110073static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110074 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110075 const mp_spiflash_config_t *c = self->config;
76 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
77 // Note: len/data are unused for standard SPI
78 mp_hal_pin_write(c->bus.u_spi.cs, 0);
79 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
80 mp_hal_pin_write(c->bus.u_spi.cs, 1);
81 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110082 ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
Damien George4e487002018-03-02 16:01:18 +110083 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +110084 return ret;
Damien George4e487002018-03-02 16:01:18 +110085}
86
Angus Grattondecf8e62024-02-27 15:32:29 +110087static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110088 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110089 const mp_spiflash_config_t *c = self->config;
90 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Andrew Leech30501d32020-01-28 14:59:05 +110091 uint8_t buf[5] = {cmd, 0};
92 uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr);
Damien George4e487002018-03-02 16:01:18 +110093 mp_hal_pin_write(c->bus.u_spi.cs, 0);
Andrew Leech30501d32020-01-28 14:59:05 +110094 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL);
95 if (len && (src != NULL)) {
Damien George4e487002018-03-02 16:01:18 +110096 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
Andrew Leech30501d32020-01-28 14:59:05 +110097 } else if (len && (dest != NULL)) {
98 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
Damien George4e487002018-03-02 16:01:18 +110099 }
Andrew Leech30501d32020-01-28 14:59:05 +1100100
Damien George4e487002018-03-02 16:01:18 +1100101 mp_hal_pin_write(c->bus.u_spi.cs, 1);
102 } else {
Andrew Leech30501d32020-01-28 14:59:05 +1100103 if (dest != NULL) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100104 ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, len, dest);
Andrew Leech30501d32020-01-28 14:59:05 +1100105 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100106 ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
Andrew Leech30501d32020-01-28 14:59:05 +1100107 }
Damien George4e487002018-03-02 16:01:18 +1100108 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100109 return ret;
Damien George4e487002018-03-02 16:01:18 +1100110}
111
Angus Grattondecf8e62024-02-27 15:32:29 +1100112static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100113 const mp_spiflash_config_t *c = self->config;
114 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George4e487002018-03-02 16:01:18 +1100115 mp_hal_pin_write(c->bus.u_spi.cs, 0);
116 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
Damien Georgeb042fd52022-12-09 12:28:54 +1100117 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)dest, (void*)dest);
Damien George4e487002018-03-02 16:01:18 +1100118 mp_hal_pin_write(c->bus.u_spi.cs, 1);
Damien Georgeb042fd52022-12-09 12:28:54 +1100119 return 0;
Damien George4e487002018-03-02 16:01:18 +1100120 } else {
Damien Georgeb042fd52022-12-09 12:28:54 +1100121 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest);
Damien George4e487002018-03-02 16:01:18 +1100122 }
123}
124
Angus Grattondecf8e62024-02-27 15:32:29 +1100125static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100126 const mp_spiflash_config_t *c = self->config;
Andrew Leech30501d32020-01-28 14:59:05 +1100127 uint8_t cmd;
Damien George4e487002018-03-02 16:01:18 +1100128 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George54f16942022-06-01 18:50:43 +1000129 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ;
Damien George4e487002018-03-02 16:01:18 +1100130 } else {
Damien George54f16942022-06-01 18:50:43 +1000131 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ;
Damien George4e487002018-03-02 16:01:18 +1100132 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100133 return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest);
Damien George4e487002018-03-02 16:01:18 +1100134}
135
Angus Grattondecf8e62024-02-27 15:32:29 +1100136static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100137 return mp_spiflash_write_cmd_data(self, cmd, 0, 0);
Damien George4e487002018-03-02 16:01:18 +1100138}
139
Angus Grattondecf8e62024-02-27 15:32:29 +1100140static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100141 do {
Damien Georgeb042fd52022-12-09 12:28:54 +1100142 uint32_t sr;
143 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
144 if (ret != 0) {
145 return ret;
146 }
Damien George4e487002018-03-02 16:01:18 +1100147 if ((sr & mask) == val) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100148 return 0; // success
Damien George784e0232017-01-24 16:56:03 +1100149 }
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100150 } while (timeout--);
151
152 return -MP_ETIMEDOUT;
Damien George784e0232017-01-24 16:56:03 +1100153}
154
Angus Grattondecf8e62024-02-27 15:32:29 +1100155static int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100156 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
157}
158
Angus Grattondecf8e62024-02-27 15:32:29 +1100159static int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100160 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
161}
162
Damien George8cde5fa2019-07-03 01:03:25 +1000163static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) {
164 mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake
165}
166
Damien George4e487002018-03-02 16:01:18 +1100167void mp_spiflash_init(mp_spiflash_t *self) {
168 self->flags = 0;
169
170 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
171 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
172 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100173 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100174 } else {
175 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
176 }
177
178 mp_spiflash_acquire_bus(self);
179
Damien George8cde5fa2019-07-03 01:03:25 +1000180 // Ensure SPI flash is out of sleep mode
181 mp_spiflash_deepsleep_internal(self, 0);
182
Damien George4e487002018-03-02 16:01:18 +1100183 #if defined(CHECK_DEVID)
184 // Validate device id
Damien Georgeb042fd52022-12-09 12:28:54 +1100185 uint32_t devid;
186 int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
187 if (ret != 0 || devid != CHECK_DEVID) {
188 mp_spiflash_release_bus(self);
189 return;
Damien George4e487002018-03-02 16:01:18 +1100190 }
191 #endif
192
193 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
194 // Set QE bit
Damien Georgeb042fd52022-12-09 12:28:54 +1100195 uint32_t sr = 0, cr = 0;
196 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
197 if (ret == 0) {
198 ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
199 }
200 uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
201 if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
Damien Georgecc34b082018-03-11 11:25:38 +1100202 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100203 mp_spiflash_write_cmd(self, CMD_WREN);
204 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
205 mp_spiflash_wait_wip0(self);
206 }
207 }
208
209 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100210}
211
Damien George8cde5fa2019-07-03 01:03:25 +1000212void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) {
213 if (value) {
214 mp_spiflash_acquire_bus(self);
215 }
216 mp_spiflash_deepsleep_internal(self, value);
217 if (!value) {
218 mp_spiflash_release_bus(self);
219 }
220}
221
Angus Grattondecf8e62024-02-27 15:32:29 +1100222static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100223 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100224 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100225 ret = mp_spiflash_write_cmd(self, CMD_WREN);
226 if (ret != 0) {
227 return ret;
228 }
Damien George784e0232017-01-24 16:56:03 +1100229
230 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100231 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100232 if (ret != 0) {
233 return ret;
234 }
235
236 // erase the sector
Damien George54f16942022-06-01 18:50:43 +1000237 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100238 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL);
239 if (ret != 0) {
240 return ret;
241 }
Damien George784e0232017-01-24 16:56:03 +1100242
243 // wait WIP=0
244 return mp_spiflash_wait_wip0(self);
245}
246
Angus Grattondecf8e62024-02-27 15:32:29 +1100247static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100248 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100249 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100250 ret = mp_spiflash_write_cmd(self, CMD_WREN);
251 if (ret != 0) {
252 return ret;
253 }
Damien George784e0232017-01-24 16:56:03 +1100254
255 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100256 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100257 if (ret != 0) {
258 return ret;
259 }
260
261 // write the page
Damien George54f16942022-06-01 18:50:43 +1000262 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100263 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL);
264 if (ret != 0) {
265 return ret;
266 }
Damien George784e0232017-01-24 16:56:03 +1100267
268 // wait WIP=0
269 return mp_spiflash_wait_wip0(self);
270}
271
Damien Georgecc5a9402018-06-07 15:36:27 +1000272/******************************************************************************/
Damien Georgeb78ca322018-06-07 15:39:46 +1000273// Interface functions that go direct to the SPI flash device
274
275int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
276 mp_spiflash_acquire_bus(self);
277 int ret = mp_spiflash_erase_block_internal(self, addr);
278 mp_spiflash_release_bus(self);
279 return ret;
280}
281
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100282int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000283 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100284 return 0;
Damien Georgeb78ca322018-06-07 15:39:46 +1000285 }
286 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100287 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien Georgeb78ca322018-06-07 15:39:46 +1000288 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100289 return ret;
Damien Georgeb78ca322018-06-07 15:39:46 +1000290}
291
292int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
293 mp_spiflash_acquire_bus(self);
294 int ret = 0;
295 uint32_t offset = addr & (PAGE_SIZE - 1);
296 while (len) {
297 size_t rest = PAGE_SIZE - offset;
298 if (rest > len) {
299 rest = len;
300 }
301 ret = mp_spiflash_write_page(self, addr, rest, src);
302 if (ret != 0) {
303 break;
304 }
305 len -= rest;
306 addr += rest;
307 src += rest;
308 offset = 0;
309 }
310 mp_spiflash_release_bus(self);
311 return ret;
312}
313
314/******************************************************************************/
Damien Georgecc5a9402018-06-07 15:36:27 +1000315// Interface functions that use the cache
316
Damien Georgee43a74a2020-12-17 16:59:54 +1100317#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
318
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100319int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100320 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100321 return 0;
Damien George4e487002018-03-02 16:01:18 +1100322 }
Damien George784e0232017-01-24 16:56:03 +1100323 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000324 mp_spiflash_cache_t *cache = self->config->cache;
325 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100326 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100327 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000328 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100329 // Read straddles current buffer
330 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000331 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100332 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000333 rest = cache->block * SECTOR_SIZE - addr;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100334 int ret = mp_spiflash_read_data(self, addr, rest, dest);
335 if (ret != 0) {
336 mp_spiflash_release_bus(self);
337 return ret;
338 }
Damien George4e487002018-03-02 16:01:18 +1100339 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100340 dest += rest;
341 addr += rest;
342 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100343 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100344 rest = SECTOR_SIZE - offset;
345 if (rest > len) {
346 rest = len;
347 }
Damien George86fe73b2018-06-07 14:09:10 +1000348 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100349 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100350 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100351 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100352 return 0;
Damien George4e487002018-03-02 16:01:18 +1100353 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100354 dest += rest;
355 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100356 }
Damien George4e487002018-03-02 16:01:18 +1100357 }
358 // Read rest direct from flash
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100359 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100360 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100361 return ret;
Damien George784e0232017-01-24 16:56:03 +1100362}
363
Angus Grattondecf8e62024-02-27 15:32:29 +1100364static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100365 #if USE_WR_DELAY
366 if (!(self->flags & 1)) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100367 return 0;
Damien George4e487002018-03-02 16:01:18 +1100368 }
Damien George784e0232017-01-24 16:56:03 +1100369
Damien George4e487002018-03-02 16:01:18 +1100370 self->flags &= ~1;
371
Damien George86fe73b2018-06-07 14:09:10 +1000372 mp_spiflash_cache_t *cache = self->config->cache;
373
Damien George4e487002018-03-02 16:01:18 +1100374 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000375 int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100376 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100377 return ret;
Damien George4e487002018-03-02 16:01:18 +1100378 }
379
380 // Write
381 for (int i = 0; i < 16; i += 1) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000382 uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
383 int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100384 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100385 return ret;
Damien George4e487002018-03-02 16:01:18 +1100386 }
387 }
388 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100389 return 0;
Damien George4e487002018-03-02 16:01:18 +1100390}
391
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100392int mp_spiflash_cache_flush(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100393 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100394 int ret = mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100395 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100396 return ret;
Damien George4e487002018-03-02 16:01:18 +1100397}
398
Angus Grattondecf8e62024-02-27 15:32:29 +1100399static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100400 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100401 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100402 uint32_t sec = addr >> 12;
403 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100404
Damien George4e487002018-03-02 16:01:18 +1100405 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000406 if (offset + len > SECTOR_SIZE) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000407 printf("mp_spiflash_cached_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100408 return -MP_EIO;
409 }
410
Damien George86fe73b2018-06-07 14:09:10 +1000411 mp_spiflash_cache_t *cache = self->config->cache;
412
Damien George4e487002018-03-02 16:01:18 +1100413 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000414 if (cache->user != self) {
415 if (cache->user != NULL) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000416 mp_spiflash_cache_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100417 }
Damien George86fe73b2018-06-07 14:09:10 +1000418 cache->user = self;
419 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100420 }
421
Damien George86fe73b2018-06-07 14:09:10 +1000422 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100423 // Read sector
424 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000425 if (cache->block != 0xffffffff) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100426 int ret = mp_spiflash_cache_flush_internal(self);
427 if (ret != 0) {
428 return ret;
429 }
Damien George4e487002018-03-02 16:01:18 +1100430 }
431 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100432 int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
433 if (ret != 0) {
434 return ret;
435 }
Damien George4e487002018-03-02 16:01:18 +1100436 }
Damien George784e0232017-01-24 16:56:03 +1100437
Damien George4e487002018-03-02 16:01:18 +1100438 #if USE_WR_DELAY
439
Damien George86fe73b2018-06-07 14:09:10 +1000440 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100441 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000442 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100443 // And mark dirty
444 self->flags |= 1;
445
446 #else
447
448 uint32_t dirty = 0;
449 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000450 if (cache->buf[offset + i] != src[i]) {
451 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100452 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000453 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien George4e487002018-03-02 16:01:18 +1100454 if (ret != 0) {
455 return ret;
456 }
457 dirty = 0xffff;
458 break;
459 } else {
460 dirty |= (1 << ((offset + i) >> 8));
461 }
Damien George784e0232017-01-24 16:56:03 +1100462 }
463 }
464
Damien George86fe73b2018-06-07 14:09:10 +1000465 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100466 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000467 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100468
469 // Write sector in pages of 256 bytes
470 for (size_t i = 0; i < 16; ++i) {
471 if (dirty & (1 << i)) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000472 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100473 if (ret != 0) {
474 return ret;
475 }
476 }
477 }
478
479 #endif
480
Damien George784e0232017-01-24 16:56:03 +1100481 return 0; // success
482}
Damien George4e487002018-03-02 16:01:18 +1100483
Damien Georgecc5a9402018-06-07 15:36:27 +1000484int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100485 uint32_t bis = addr / SECTOR_SIZE;
486 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
487
488 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100489
Damien George86fe73b2018-06-07 14:09:10 +1000490 mp_spiflash_cache_t *cache = self->config->cache;
491 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100492 // Write straddles current buffer
493 uint32_t pre;
494 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000495 if (cache->block * SECTOR_SIZE >= addr) {
496 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100497 offset = 0;
498 } else {
499 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000500 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100501 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100502
503 // Write buffered part first
504 uint32_t len_in_buf = len - pre;
505 len = 0;
506 if (len_in_buf > SECTOR_SIZE - offset) {
507 len = len_in_buf - (SECTOR_SIZE - offset);
508 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100509 }
Damien George86fe73b2018-06-07 14:09:10 +1000510 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100511 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100512
513 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100514 while (pre) {
515 int rest = pre & (SECTOR_SIZE - 1);
516 if (rest == 0) {
517 rest = SECTOR_SIZE;
518 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000519 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100520 if (ret != 0) {
521 mp_spiflash_release_bus(self);
522 return ret;
523 }
524 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100525 addr += rest;
526 pre -= rest;
527 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100528 src += len_in_buf;
529 addr += len_in_buf;
530
531 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100532 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100533
534 uint32_t offset = addr & (SECTOR_SIZE - 1);
535 while (len) {
536 int rest = SECTOR_SIZE - offset;
537 if (rest > len) {
538 rest = len;
539 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000540 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100541 if (ret != 0) {
542 mp_spiflash_release_bus(self);
543 return ret;
544 }
545 len -= rest;
546 addr += rest;
547 src += rest;
548 offset = 0;
549 }
550
Damien George4e487002018-03-02 16:01:18 +1100551 mp_spiflash_release_bus(self);
552 return 0;
553}
Damien Georgee43a74a2020-12-17 16:59:54 +1100554
555#endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE