blob: 22775d5416fc2f8115d7d926a2a55105a1ea727b [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien George4e487002018-03-02 16:01:18 +110034#define QSPI_QE_MASK (0x02)
35#define USE_WR_DELAY (1)
36
37#define CMD_WRSR (0x01)
38#define CMD_WRITE (0x02)
39#define CMD_READ (0x03)
40#define CMD_RDSR (0x05)
41#define CMD_WREN (0x06)
42#define CMD_SEC_ERASE (0x20)
43#define CMD_RDCR (0x35)
44#define CMD_RD_DEVID (0x9f)
45#define CMD_CHIP_ERASE (0xc7)
46#define CMD_C4READ (0xeb)
47
Damien George784e0232017-01-24 16:56:03 +110048#define WAIT_SR_TIMEOUT (1000000)
49
50#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100051#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110052
53STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110054 const mp_spiflash_config_t *c = self->config;
55 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
56 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
57 }
Damien George784e0232017-01-24 16:56:03 +110058}
59
60STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110061 const mp_spiflash_config_t *c = self->config;
62 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
63 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
64 }
Damien George784e0232017-01-24 16:56:03 +110065}
66
Damien George4e487002018-03-02 16:01:18 +110067STATIC void mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
68 const mp_spiflash_config_t *c = self->config;
69 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
70 // Note: len/data are unused for standard SPI
71 mp_hal_pin_write(c->bus.u_spi.cs, 0);
72 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
73 mp_hal_pin_write(c->bus.u_spi.cs, 1);
74 } else {
75 c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
76 }
77}
78
79STATIC void mp_spiflash_write_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
80 const mp_spiflash_config_t *c = self->config;
81 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
82 uint8_t buf[4] = {cmd, addr >> 16, addr >> 8, addr};
83 mp_hal_pin_write(c->bus.u_spi.cs, 0);
84 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
85 if (len) {
86 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
87 }
88 mp_hal_pin_write(c->bus.u_spi.cs, 1);
89 } else {
90 c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
91 }
92}
93
94STATIC uint32_t mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len) {
95 const mp_spiflash_config_t *c = self->config;
96 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
97 uint32_t buf;
98 mp_hal_pin_write(c->bus.u_spi.cs, 0);
99 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
100 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)&buf, (void*)&buf);
101 mp_hal_pin_write(c->bus.u_spi.cs, 1);
102 return buf;
103 } else {
104 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len);
105 }
106}
107
108STATIC void mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
109 const mp_spiflash_config_t *c = self->config;
110 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
111 uint8_t buf[4] = {CMD_READ, addr >> 16, addr >> 8, addr};
112 mp_hal_pin_write(c->bus.u_spi.cs, 0);
113 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
114 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
115 mp_hal_pin_write(c->bus.u_spi.cs, 1);
116 } else {
117 c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, CMD_C4READ, addr, len, dest);
118 }
119}
120
121STATIC void mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
122 mp_spiflash_write_cmd_data(self, cmd, 0, 0);
123}
124
125STATIC void mp_spiflash_write_cmd_addr(mp_spiflash_t *self, uint8_t cmd, uint32_t addr) {
126 mp_spiflash_write_cmd_addr_data(self, cmd, addr, 0, NULL);
Damien George784e0232017-01-24 16:56:03 +1100127}
128
129STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Damien George4e487002018-03-02 16:01:18 +1100130 uint8_t sr;
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100131 do {
Damien George4e487002018-03-02 16:01:18 +1100132 sr = mp_spiflash_read_cmd(self, CMD_RDSR, 1);
133 if ((sr & mask) == val) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100134 return 0; // success
Damien George784e0232017-01-24 16:56:03 +1100135 }
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100136 } while (timeout--);
137
138 return -MP_ETIMEDOUT;
Damien George784e0232017-01-24 16:56:03 +1100139}
140
141STATIC int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
142 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
143}
144
145STATIC int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
146 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
147}
148
Damien George4e487002018-03-02 16:01:18 +1100149void mp_spiflash_init(mp_spiflash_t *self) {
150 self->flags = 0;
151
152 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
153 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
154 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100155 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100156 } else {
157 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
158 }
159
160 mp_spiflash_acquire_bus(self);
161
162 #if defined(CHECK_DEVID)
163 // Validate device id
164 uint32_t devid = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3);
165 if (devid != CHECK_DEVID) {
166 return 0;
167 }
168 #endif
169
170 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
171 // Set QE bit
172 uint32_t data = (mp_spiflash_read_cmd(self, CMD_RDSR, 1) & 0xff)
173 | (mp_spiflash_read_cmd(self, CMD_RDCR, 1) & 0xff) << 8;
Damien Georgecc34b082018-03-11 11:25:38 +1100174 if (!(data & (QSPI_QE_MASK << 8))) {
175 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100176 mp_spiflash_write_cmd(self, CMD_WREN);
177 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
178 mp_spiflash_wait_wip0(self);
179 }
180 }
181
182 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100183}
184
Damien Georgeb78ca322018-06-07 15:39:46 +1000185STATIC int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
Damien George784e0232017-01-24 16:56:03 +1100186 // enable writes
187 mp_spiflash_write_cmd(self, CMD_WREN);
188
189 // wait WEL=1
190 int ret = mp_spiflash_wait_wel1(self);
191 if (ret != 0) {
192 return ret;
193 }
194
195 // erase the sector
Damien George4e487002018-03-02 16:01:18 +1100196 mp_spiflash_write_cmd_addr(self, CMD_SEC_ERASE, addr);
Damien George784e0232017-01-24 16:56:03 +1100197
198 // wait WIP=0
199 return mp_spiflash_wait_wip0(self);
200}
201
Damien Georgeb78ca322018-06-07 15:39:46 +1000202STATIC int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George784e0232017-01-24 16:56:03 +1100203 // enable writes
204 mp_spiflash_write_cmd(self, CMD_WREN);
205
206 // wait WEL=1
207 int ret = mp_spiflash_wait_wel1(self);
208 if (ret != 0) {
209 return ret;
210 }
211
212 // write the page
Damien Georgeb78ca322018-06-07 15:39:46 +1000213 mp_spiflash_write_cmd_addr_data(self, CMD_WRITE, addr, len, src);
Damien George784e0232017-01-24 16:56:03 +1100214
215 // wait WIP=0
216 return mp_spiflash_wait_wip0(self);
217}
218
Damien Georgecc5a9402018-06-07 15:36:27 +1000219/******************************************************************************/
Damien Georgeb78ca322018-06-07 15:39:46 +1000220// Interface functions that go direct to the SPI flash device
221
222int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
223 mp_spiflash_acquire_bus(self);
224 int ret = mp_spiflash_erase_block_internal(self, addr);
225 mp_spiflash_release_bus(self);
226 return ret;
227}
228
229void mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
230 if (len == 0) {
231 return;
232 }
233 mp_spiflash_acquire_bus(self);
234 mp_spiflash_read_data(self, addr, len, dest);
235 mp_spiflash_release_bus(self);
236}
237
238int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
239 mp_spiflash_acquire_bus(self);
240 int ret = 0;
241 uint32_t offset = addr & (PAGE_SIZE - 1);
242 while (len) {
243 size_t rest = PAGE_SIZE - offset;
244 if (rest > len) {
245 rest = len;
246 }
247 ret = mp_spiflash_write_page(self, addr, rest, src);
248 if (ret != 0) {
249 break;
250 }
251 len -= rest;
252 addr += rest;
253 src += rest;
254 offset = 0;
255 }
256 mp_spiflash_release_bus(self);
257 return ret;
258}
259
260/******************************************************************************/
Damien Georgecc5a9402018-06-07 15:36:27 +1000261// Interface functions that use the cache
262
263void mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100264 if (len == 0) {
265 return;
266 }
Damien George784e0232017-01-24 16:56:03 +1100267 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000268 mp_spiflash_cache_t *cache = self->config->cache;
269 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100270 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100271 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000272 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100273 // Read straddles current buffer
274 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000275 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100276 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000277 rest = cache->block * SECTOR_SIZE - addr;
Damien Georgebdc875e2018-03-13 14:13:30 +1100278 mp_spiflash_read_data(self, addr, rest, dest);
Damien George4e487002018-03-02 16:01:18 +1100279 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100280 dest += rest;
281 addr += rest;
282 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100283 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100284 rest = SECTOR_SIZE - offset;
285 if (rest > len) {
286 rest = len;
287 }
Damien George86fe73b2018-06-07 14:09:10 +1000288 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100289 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100290 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100291 mp_spiflash_release_bus(self);
292 return;
293 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100294 dest += rest;
295 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100296 }
Damien George4e487002018-03-02 16:01:18 +1100297 }
298 // Read rest direct from flash
299 mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100300 mp_spiflash_release_bus(self);
301}
302
Damien Georgecc5a9402018-06-07 15:36:27 +1000303STATIC void mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100304 #if USE_WR_DELAY
305 if (!(self->flags & 1)) {
306 return;
307 }
Damien George784e0232017-01-24 16:56:03 +1100308
Damien George4e487002018-03-02 16:01:18 +1100309 self->flags &= ~1;
310
Damien George86fe73b2018-06-07 14:09:10 +1000311 mp_spiflash_cache_t *cache = self->config->cache;
312
Damien George4e487002018-03-02 16:01:18 +1100313 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000314 int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100315 if (ret != 0) {
316 return;
317 }
318
319 // Write
320 for (int i = 0; i < 16; i += 1) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000321 uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
322 int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100323 if (ret != 0) {
324 return;
325 }
326 }
327 #endif
328}
329
Damien Georgecc5a9402018-06-07 15:36:27 +1000330void mp_spiflash_cache_flush(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100331 mp_spiflash_acquire_bus(self);
Damien Georgecc5a9402018-06-07 15:36:27 +1000332 mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100333 mp_spiflash_release_bus(self);
334}
335
Damien Georgecc5a9402018-06-07 15:36:27 +1000336STATIC int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100337 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100338 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100339 uint32_t sec = addr >> 12;
340 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100341
Damien George4e487002018-03-02 16:01:18 +1100342 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000343 if (offset + len > SECTOR_SIZE) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000344 printf("mp_spiflash_cached_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100345 return -MP_EIO;
346 }
347
Damien George86fe73b2018-06-07 14:09:10 +1000348 mp_spiflash_cache_t *cache = self->config->cache;
349
Damien George4e487002018-03-02 16:01:18 +1100350 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000351 if (cache->user != self) {
352 if (cache->user != NULL) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000353 mp_spiflash_cache_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100354 }
Damien George86fe73b2018-06-07 14:09:10 +1000355 cache->user = self;
356 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100357 }
358
Damien George86fe73b2018-06-07 14:09:10 +1000359 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100360 // Read sector
361 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000362 if (cache->block != 0xffffffff) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000363 mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100364 }
365 #endif
Damien George86fe73b2018-06-07 14:09:10 +1000366 mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
Damien George4e487002018-03-02 16:01:18 +1100367 }
Damien George784e0232017-01-24 16:56:03 +1100368
Damien George4e487002018-03-02 16:01:18 +1100369 #if USE_WR_DELAY
370
Damien George86fe73b2018-06-07 14:09:10 +1000371 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100372 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000373 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100374 // And mark dirty
375 self->flags |= 1;
376
377 #else
378
379 uint32_t dirty = 0;
380 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000381 if (cache->buf[offset + i] != src[i]) {
382 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100383 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000384 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien George4e487002018-03-02 16:01:18 +1100385 if (ret != 0) {
386 return ret;
387 }
388 dirty = 0xffff;
389 break;
390 } else {
391 dirty |= (1 << ((offset + i) >> 8));
392 }
Damien George784e0232017-01-24 16:56:03 +1100393 }
394 }
395
Damien George86fe73b2018-06-07 14:09:10 +1000396 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100397 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000398 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100399
400 // Write sector in pages of 256 bytes
401 for (size_t i = 0; i < 16; ++i) {
402 if (dirty & (1 << i)) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000403 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100404 if (ret != 0) {
405 return ret;
406 }
407 }
408 }
409
410 #endif
411
Damien George784e0232017-01-24 16:56:03 +1100412 return 0; // success
413}
Damien George4e487002018-03-02 16:01:18 +1100414
Damien Georgecc5a9402018-06-07 15:36:27 +1000415int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100416 uint32_t bis = addr / SECTOR_SIZE;
417 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
418
419 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100420
Damien George86fe73b2018-06-07 14:09:10 +1000421 mp_spiflash_cache_t *cache = self->config->cache;
422 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100423 // Write straddles current buffer
424 uint32_t pre;
425 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000426 if (cache->block * SECTOR_SIZE >= addr) {
427 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100428 offset = 0;
429 } else {
430 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000431 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100432 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100433
434 // Write buffered part first
435 uint32_t len_in_buf = len - pre;
436 len = 0;
437 if (len_in_buf > SECTOR_SIZE - offset) {
438 len = len_in_buf - (SECTOR_SIZE - offset);
439 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100440 }
Damien George86fe73b2018-06-07 14:09:10 +1000441 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100442 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100443
444 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100445 while (pre) {
446 int rest = pre & (SECTOR_SIZE - 1);
447 if (rest == 0) {
448 rest = SECTOR_SIZE;
449 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000450 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100451 if (ret != 0) {
452 mp_spiflash_release_bus(self);
453 return ret;
454 }
455 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100456 addr += rest;
457 pre -= rest;
458 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100459 src += len_in_buf;
460 addr += len_in_buf;
461
462 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100463 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100464
465 uint32_t offset = addr & (SECTOR_SIZE - 1);
466 while (len) {
467 int rest = SECTOR_SIZE - offset;
468 if (rest > len) {
469 rest = len;
470 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000471 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100472 if (ret != 0) {
473 mp_spiflash_release_bus(self);
474 return ret;
475 }
476 len -= rest;
477 addr += rest;
478 src += rest;
479 offset = 0;
480 }
481
Damien George4e487002018-03-02 16:01:18 +1100482 mp_spiflash_release_bus(self);
483 return 0;
484}