Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the MicroPython project, http://micropython.org/ |
| 3 | * |
| 4 | * The MIT License (MIT) |
| 5 | * |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 6 | * Copyright (c) 2016-2018 Damien P. George |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include <stdio.h> |
| 28 | #include <string.h> |
| 29 | |
| 30 | #include "py/mperrno.h" |
| 31 | #include "py/mphal.h" |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 32 | #include "drivers/memory/spiflash.h" |
| 33 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 34 | #define QSPI_QE_MASK (0x02) |
| 35 | #define USE_WR_DELAY (1) |
| 36 | |
| 37 | #define CMD_WRSR (0x01) |
| 38 | #define CMD_WRITE (0x02) |
| 39 | #define CMD_READ (0x03) |
| 40 | #define CMD_RDSR (0x05) |
| 41 | #define CMD_WREN (0x06) |
| 42 | #define CMD_SEC_ERASE (0x20) |
| 43 | #define CMD_RDCR (0x35) |
| 44 | #define CMD_RD_DEVID (0x9f) |
| 45 | #define CMD_CHIP_ERASE (0xc7) |
| 46 | #define CMD_C4READ (0xeb) |
| 47 | |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 48 | #define WAIT_SR_TIMEOUT (1000000) |
| 49 | |
| 50 | #define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 51 | #define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 52 | |
| 53 | STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 54 | const mp_spiflash_config_t *c = self->config; |
| 55 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
| 56 | c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE); |
| 57 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 61 | const mp_spiflash_config_t *c = self->config; |
| 62 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
| 63 | c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE); |
| 64 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 65 | } |
| 66 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 67 | STATIC void mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) { |
| 68 | const mp_spiflash_config_t *c = self->config; |
| 69 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 70 | // Note: len/data are unused for standard SPI |
| 71 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 72 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL); |
| 73 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 74 | } else { |
| 75 | c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data); |
| 76 | } |
| 77 | } |
| 78 | |
| 79 | STATIC void mp_spiflash_write_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) { |
| 80 | const mp_spiflash_config_t *c = self->config; |
| 81 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 82 | uint8_t buf[4] = {cmd, addr >> 16, addr >> 8, addr}; |
| 83 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 84 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL); |
| 85 | if (len) { |
| 86 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL); |
| 87 | } |
| 88 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 89 | } else { |
| 90 | c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src); |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | STATIC uint32_t mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len) { |
| 95 | const mp_spiflash_config_t *c = self->config; |
| 96 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 97 | uint32_t buf; |
| 98 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 99 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL); |
| 100 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)&buf, (void*)&buf); |
| 101 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 102 | return buf; |
| 103 | } else { |
| 104 | return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | STATIC void mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
| 109 | const mp_spiflash_config_t *c = self->config; |
| 110 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 111 | uint8_t buf[4] = {CMD_READ, addr >> 16, addr >> 8, addr}; |
| 112 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 113 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL); |
| 114 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest); |
| 115 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 116 | } else { |
| 117 | c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, CMD_C4READ, addr, len, dest); |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | STATIC void mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) { |
| 122 | mp_spiflash_write_cmd_data(self, cmd, 0, 0); |
| 123 | } |
| 124 | |
| 125 | STATIC void mp_spiflash_write_cmd_addr(mp_spiflash_t *self, uint8_t cmd, uint32_t addr) { |
| 126 | mp_spiflash_write_cmd_addr_data(self, cmd, addr, 0, NULL); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 130 | uint8_t sr; |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame^] | 131 | do { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 132 | sr = mp_spiflash_read_cmd(self, CMD_RDSR, 1); |
| 133 | if ((sr & mask) == val) { |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame^] | 134 | return 0; // success |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 135 | } |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame^] | 136 | } while (timeout--); |
| 137 | |
| 138 | return -MP_ETIMEDOUT; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | STATIC int mp_spiflash_wait_wel1(mp_spiflash_t *self) { |
| 142 | return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT); |
| 143 | } |
| 144 | |
| 145 | STATIC int mp_spiflash_wait_wip0(mp_spiflash_t *self) { |
| 146 | return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT); |
| 147 | } |
| 148 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 149 | void mp_spiflash_init(mp_spiflash_t *self) { |
| 150 | self->flags = 0; |
| 151 | |
| 152 | if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 153 | mp_hal_pin_write(self->config->bus.u_spi.cs, 1); |
| 154 | mp_hal_pin_output(self->config->bus.u_spi.cs); |
Damien George | a739b35 | 2018-03-09 17:32:28 +1100 | [diff] [blame] | 155 | self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 156 | } else { |
| 157 | self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT); |
| 158 | } |
| 159 | |
| 160 | mp_spiflash_acquire_bus(self); |
| 161 | |
| 162 | #if defined(CHECK_DEVID) |
| 163 | // Validate device id |
| 164 | uint32_t devid = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3); |
| 165 | if (devid != CHECK_DEVID) { |
| 166 | return 0; |
| 167 | } |
| 168 | #endif |
| 169 | |
| 170 | if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
| 171 | // Set QE bit |
| 172 | uint32_t data = (mp_spiflash_read_cmd(self, CMD_RDSR, 1) & 0xff) |
| 173 | | (mp_spiflash_read_cmd(self, CMD_RDCR, 1) & 0xff) << 8; |
Damien George | cc34b08 | 2018-03-11 11:25:38 +1100 | [diff] [blame] | 174 | if (!(data & (QSPI_QE_MASK << 8))) { |
| 175 | data |= QSPI_QE_MASK << 8; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 176 | mp_spiflash_write_cmd(self, CMD_WREN); |
| 177 | mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data); |
| 178 | mp_spiflash_wait_wip0(self); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | mp_spiflash_release_bus(self); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 183 | } |
| 184 | |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 185 | STATIC int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) { |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 186 | // enable writes |
| 187 | mp_spiflash_write_cmd(self, CMD_WREN); |
| 188 | |
| 189 | // wait WEL=1 |
| 190 | int ret = mp_spiflash_wait_wel1(self); |
| 191 | if (ret != 0) { |
| 192 | return ret; |
| 193 | } |
| 194 | |
| 195 | // erase the sector |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 196 | mp_spiflash_write_cmd_addr(self, CMD_SEC_ERASE, addr); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 197 | |
| 198 | // wait WIP=0 |
| 199 | return mp_spiflash_wait_wip0(self); |
| 200 | } |
| 201 | |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 202 | STATIC int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 203 | // enable writes |
| 204 | mp_spiflash_write_cmd(self, CMD_WREN); |
| 205 | |
| 206 | // wait WEL=1 |
| 207 | int ret = mp_spiflash_wait_wel1(self); |
| 208 | if (ret != 0) { |
| 209 | return ret; |
| 210 | } |
| 211 | |
| 212 | // write the page |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 213 | mp_spiflash_write_cmd_addr_data(self, CMD_WRITE, addr, len, src); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 214 | |
| 215 | // wait WIP=0 |
| 216 | return mp_spiflash_wait_wip0(self); |
| 217 | } |
| 218 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 219 | /******************************************************************************/ |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 220 | // Interface functions that go direct to the SPI flash device |
| 221 | |
| 222 | int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) { |
| 223 | mp_spiflash_acquire_bus(self); |
| 224 | int ret = mp_spiflash_erase_block_internal(self, addr); |
| 225 | mp_spiflash_release_bus(self); |
| 226 | return ret; |
| 227 | } |
| 228 | |
| 229 | void mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
| 230 | if (len == 0) { |
| 231 | return; |
| 232 | } |
| 233 | mp_spiflash_acquire_bus(self); |
| 234 | mp_spiflash_read_data(self, addr, len, dest); |
| 235 | mp_spiflash_release_bus(self); |
| 236 | } |
| 237 | |
| 238 | int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
| 239 | mp_spiflash_acquire_bus(self); |
| 240 | int ret = 0; |
| 241 | uint32_t offset = addr & (PAGE_SIZE - 1); |
| 242 | while (len) { |
| 243 | size_t rest = PAGE_SIZE - offset; |
| 244 | if (rest > len) { |
| 245 | rest = len; |
| 246 | } |
| 247 | ret = mp_spiflash_write_page(self, addr, rest, src); |
| 248 | if (ret != 0) { |
| 249 | break; |
| 250 | } |
| 251 | len -= rest; |
| 252 | addr += rest; |
| 253 | src += rest; |
| 254 | offset = 0; |
| 255 | } |
| 256 | mp_spiflash_release_bus(self); |
| 257 | return ret; |
| 258 | } |
| 259 | |
| 260 | /******************************************************************************/ |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 261 | // Interface functions that use the cache |
| 262 | |
| 263 | void mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 264 | if (len == 0) { |
| 265 | return; |
| 266 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 267 | mp_spiflash_acquire_bus(self); |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 268 | mp_spiflash_cache_t *cache = self->config->cache; |
| 269 | if (cache->user == self && cache->block != 0xffffffff) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 270 | uint32_t bis = addr / SECTOR_SIZE; |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 271 | uint32_t bie = (addr + len - 1) / SECTOR_SIZE; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 272 | if (bis <= cache->block && cache->block <= bie) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 273 | // Read straddles current buffer |
| 274 | size_t rest = 0; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 275 | if (bis < cache->block) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 276 | // Read direct from flash for first part |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 277 | rest = cache->block * SECTOR_SIZE - addr; |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 278 | mp_spiflash_read_data(self, addr, rest, dest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 279 | len -= rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 280 | dest += rest; |
| 281 | addr += rest; |
| 282 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 283 | uint32_t offset = addr & (SECTOR_SIZE - 1); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 284 | rest = SECTOR_SIZE - offset; |
| 285 | if (rest > len) { |
| 286 | rest = len; |
| 287 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 288 | memcpy(dest, &cache->buf[offset], rest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 289 | len -= rest; |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 290 | if (len == 0) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 291 | mp_spiflash_release_bus(self); |
| 292 | return; |
| 293 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 294 | dest += rest; |
| 295 | addr += rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 296 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 297 | } |
| 298 | // Read rest direct from flash |
| 299 | mp_spiflash_read_data(self, addr, len, dest); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 300 | mp_spiflash_release_bus(self); |
| 301 | } |
| 302 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 303 | STATIC void mp_spiflash_cache_flush_internal(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 304 | #if USE_WR_DELAY |
| 305 | if (!(self->flags & 1)) { |
| 306 | return; |
| 307 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 308 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 309 | self->flags &= ~1; |
| 310 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 311 | mp_spiflash_cache_t *cache = self->config->cache; |
| 312 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 313 | // Erase sector |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 314 | int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 315 | if (ret != 0) { |
| 316 | return; |
| 317 | } |
| 318 | |
| 319 | // Write |
| 320 | for (int i = 0; i < 16; i += 1) { |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 321 | uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE; |
| 322 | int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 323 | if (ret != 0) { |
| 324 | return; |
| 325 | } |
| 326 | } |
| 327 | #endif |
| 328 | } |
| 329 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 330 | void mp_spiflash_cache_flush(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 331 | mp_spiflash_acquire_bus(self); |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 332 | mp_spiflash_cache_flush_internal(self); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 333 | mp_spiflash_release_bus(self); |
| 334 | } |
| 335 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 336 | STATIC int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 337 | // Align to 4096 sector |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 338 | uint32_t offset = addr & 0xfff; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 339 | uint32_t sec = addr >> 12; |
| 340 | addr = sec << 12; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 341 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 342 | // Restriction for now, so we don't need to erase multiple pages |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 343 | if (offset + len > SECTOR_SIZE) { |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 344 | printf("mp_spiflash_cached_write_part: len is too large\n"); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 345 | return -MP_EIO; |
| 346 | } |
| 347 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 348 | mp_spiflash_cache_t *cache = self->config->cache; |
| 349 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 350 | // Acquire the sector buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 351 | if (cache->user != self) { |
| 352 | if (cache->user != NULL) { |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 353 | mp_spiflash_cache_flush(cache->user); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 354 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 355 | cache->user = self; |
| 356 | cache->block = 0xffffffff; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 357 | } |
| 358 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 359 | if (cache->block != sec) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 360 | // Read sector |
| 361 | #if USE_WR_DELAY |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 362 | if (cache->block != 0xffffffff) { |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 363 | mp_spiflash_cache_flush_internal(self); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 364 | } |
| 365 | #endif |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 366 | mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 367 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 368 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 369 | #if USE_WR_DELAY |
| 370 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 371 | cache->block = sec; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 372 | // Just copy to buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 373 | memcpy(cache->buf + offset, src, len); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 374 | // And mark dirty |
| 375 | self->flags |= 1; |
| 376 | |
| 377 | #else |
| 378 | |
| 379 | uint32_t dirty = 0; |
| 380 | for (size_t i = 0; i < len; ++i) { |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 381 | if (cache->buf[offset + i] != src[i]) { |
| 382 | if (cache->buf[offset + i] != 0xff) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 383 | // Erase sector |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 384 | int ret = mp_spiflash_erase_block_internal(self, addr); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 385 | if (ret != 0) { |
| 386 | return ret; |
| 387 | } |
| 388 | dirty = 0xffff; |
| 389 | break; |
| 390 | } else { |
| 391 | dirty |= (1 << ((offset + i) >> 8)); |
| 392 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 393 | } |
| 394 | } |
| 395 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 396 | cache->block = sec; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 397 | // Copy new block into buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 398 | memcpy(cache->buf + offset, src, len); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 399 | |
| 400 | // Write sector in pages of 256 bytes |
| 401 | for (size_t i = 0; i < 16; ++i) { |
| 402 | if (dirty & (1 << i)) { |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 403 | int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 404 | if (ret != 0) { |
| 405 | return ret; |
| 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | #endif |
| 411 | |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 412 | return 0; // success |
| 413 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 414 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 415 | int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 416 | uint32_t bis = addr / SECTOR_SIZE; |
| 417 | uint32_t bie = (addr + len - 1) / SECTOR_SIZE; |
| 418 | |
| 419 | mp_spiflash_acquire_bus(self); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 420 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 421 | mp_spiflash_cache_t *cache = self->config->cache; |
| 422 | if (cache->user == self && bis <= cache->block && bie >= cache->block) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 423 | // Write straddles current buffer |
| 424 | uint32_t pre; |
| 425 | uint32_t offset; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 426 | if (cache->block * SECTOR_SIZE >= addr) { |
| 427 | pre = cache->block * SECTOR_SIZE - addr; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 428 | offset = 0; |
| 429 | } else { |
| 430 | pre = 0; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 431 | offset = addr - cache->block * SECTOR_SIZE; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 432 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 433 | |
| 434 | // Write buffered part first |
| 435 | uint32_t len_in_buf = len - pre; |
| 436 | len = 0; |
| 437 | if (len_in_buf > SECTOR_SIZE - offset) { |
| 438 | len = len_in_buf - (SECTOR_SIZE - offset); |
| 439 | len_in_buf = SECTOR_SIZE - offset; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 440 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 441 | memcpy(&cache->buf[offset], &src[pre], len_in_buf); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 442 | self->flags |= 1; // Mark dirty |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 443 | |
| 444 | // Write part before buffer sector |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 445 | while (pre) { |
| 446 | int rest = pre & (SECTOR_SIZE - 1); |
| 447 | if (rest == 0) { |
| 448 | rest = SECTOR_SIZE; |
| 449 | } |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 450 | int ret = mp_spiflash_cached_write_part(self, addr, rest, src); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 451 | if (ret != 0) { |
| 452 | mp_spiflash_release_bus(self); |
| 453 | return ret; |
| 454 | } |
| 455 | src += rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 456 | addr += rest; |
| 457 | pre -= rest; |
| 458 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 459 | src += len_in_buf; |
| 460 | addr += len_in_buf; |
| 461 | |
| 462 | // Fall through to write remaining part |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 463 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 464 | |
| 465 | uint32_t offset = addr & (SECTOR_SIZE - 1); |
| 466 | while (len) { |
| 467 | int rest = SECTOR_SIZE - offset; |
| 468 | if (rest > len) { |
| 469 | rest = len; |
| 470 | } |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 471 | int ret = mp_spiflash_cached_write_part(self, addr, rest, src); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 472 | if (ret != 0) { |
| 473 | mp_spiflash_release_bus(self); |
| 474 | return ret; |
| 475 | } |
| 476 | len -= rest; |
| 477 | addr += rest; |
| 478 | src += rest; |
| 479 | offset = 0; |
| 480 | } |
| 481 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 482 | mp_spiflash_release_bus(self); |
| 483 | return 0; |
| 484 | } |