blob: 0cc926b79d61fd5d0881e047bad54d32518d0852 [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien George4e487002018-03-02 16:01:18 +110034#define QSPI_QE_MASK (0x02)
35#define USE_WR_DELAY (1)
36
37#define CMD_WRSR (0x01)
38#define CMD_WRITE (0x02)
39#define CMD_READ (0x03)
40#define CMD_RDSR (0x05)
41#define CMD_WREN (0x06)
42#define CMD_SEC_ERASE (0x20)
43#define CMD_RDCR (0x35)
44#define CMD_RD_DEVID (0x9f)
45#define CMD_CHIP_ERASE (0xc7)
46#define CMD_C4READ (0xeb)
47
Damien George784e0232017-01-24 16:56:03 +110048#define WAIT_SR_TIMEOUT (1000000)
49
50#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100051#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110052
53STATIC void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110054 const mp_spiflash_config_t *c = self->config;
55 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
56 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
57 }
Damien George784e0232017-01-24 16:56:03 +110058}
59
60STATIC void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110061 const mp_spiflash_config_t *c = self->config;
62 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
63 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
64 }
Damien George784e0232017-01-24 16:56:03 +110065}
66
Damien George4e487002018-03-02 16:01:18 +110067STATIC void mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
68 const mp_spiflash_config_t *c = self->config;
69 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
70 // Note: len/data are unused for standard SPI
71 mp_hal_pin_write(c->bus.u_spi.cs, 0);
72 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
73 mp_hal_pin_write(c->bus.u_spi.cs, 1);
74 } else {
75 c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
76 }
77}
78
79STATIC void mp_spiflash_write_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
80 const mp_spiflash_config_t *c = self->config;
81 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
82 uint8_t buf[4] = {cmd, addr >> 16, addr >> 8, addr};
83 mp_hal_pin_write(c->bus.u_spi.cs, 0);
84 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
85 if (len) {
86 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
87 }
88 mp_hal_pin_write(c->bus.u_spi.cs, 1);
89 } else {
90 c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
91 }
92}
93
94STATIC uint32_t mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len) {
95 const mp_spiflash_config_t *c = self->config;
96 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
97 uint32_t buf;
98 mp_hal_pin_write(c->bus.u_spi.cs, 0);
99 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
100 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)&buf, (void*)&buf);
101 mp_hal_pin_write(c->bus.u_spi.cs, 1);
102 return buf;
103 } else {
104 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len);
105 }
106}
107
108STATIC void mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
109 const mp_spiflash_config_t *c = self->config;
110 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
111 uint8_t buf[4] = {CMD_READ, addr >> 16, addr >> 8, addr};
112 mp_hal_pin_write(c->bus.u_spi.cs, 0);
113 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 4, buf, NULL);
114 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
115 mp_hal_pin_write(c->bus.u_spi.cs, 1);
116 } else {
117 c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, CMD_C4READ, addr, len, dest);
118 }
119}
120
121STATIC void mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
122 mp_spiflash_write_cmd_data(self, cmd, 0, 0);
123}
124
125STATIC void mp_spiflash_write_cmd_addr(mp_spiflash_t *self, uint8_t cmd, uint32_t addr) {
126 mp_spiflash_write_cmd_addr_data(self, cmd, addr, 0, NULL);
Damien George784e0232017-01-24 16:56:03 +1100127}
128
129STATIC int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Damien George4e487002018-03-02 16:01:18 +1100130 uint8_t sr;
Damien George784e0232017-01-24 16:56:03 +1100131 for (; timeout; --timeout) {
Damien George4e487002018-03-02 16:01:18 +1100132 sr = mp_spiflash_read_cmd(self, CMD_RDSR, 1);
133 if ((sr & mask) == val) {
Damien George784e0232017-01-24 16:56:03 +1100134 break;
135 }
136 }
Damien George4e487002018-03-02 16:01:18 +1100137 if ((sr & mask) == val) {
Damien George784e0232017-01-24 16:56:03 +1100138 return 0; // success
139 } else if (timeout == 0) {
140 return -MP_ETIMEDOUT;
141 } else {
142 return -MP_EIO;
143 }
144}
145
146STATIC int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
147 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
148}
149
150STATIC int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
151 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
152}
153
Damien George4e487002018-03-02 16:01:18 +1100154void mp_spiflash_init(mp_spiflash_t *self) {
155 self->flags = 0;
156
157 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
158 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
159 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100160 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100161 } else {
162 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
163 }
164
165 mp_spiflash_acquire_bus(self);
166
167 #if defined(CHECK_DEVID)
168 // Validate device id
169 uint32_t devid = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3);
170 if (devid != CHECK_DEVID) {
171 return 0;
172 }
173 #endif
174
175 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
176 // Set QE bit
177 uint32_t data = (mp_spiflash_read_cmd(self, CMD_RDSR, 1) & 0xff)
178 | (mp_spiflash_read_cmd(self, CMD_RDCR, 1) & 0xff) << 8;
Damien Georgecc34b082018-03-11 11:25:38 +1100179 if (!(data & (QSPI_QE_MASK << 8))) {
180 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100181 mp_spiflash_write_cmd(self, CMD_WREN);
182 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
183 mp_spiflash_wait_wip0(self);
184 }
185 }
186
187 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100188}
189
190STATIC int mp_spiflash_erase_sector(mp_spiflash_t *self, uint32_t addr) {
191 // enable writes
192 mp_spiflash_write_cmd(self, CMD_WREN);
193
194 // wait WEL=1
195 int ret = mp_spiflash_wait_wel1(self);
196 if (ret != 0) {
197 return ret;
198 }
199
200 // erase the sector
Damien George4e487002018-03-02 16:01:18 +1100201 mp_spiflash_write_cmd_addr(self, CMD_SEC_ERASE, addr);
Damien George784e0232017-01-24 16:56:03 +1100202
203 // wait WIP=0
204 return mp_spiflash_wait_wip0(self);
205}
206
207STATIC int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, const uint8_t *src) {
208 // enable writes
209 mp_spiflash_write_cmd(self, CMD_WREN);
210
211 // wait WEL=1
212 int ret = mp_spiflash_wait_wel1(self);
213 if (ret != 0) {
214 return ret;
215 }
216
217 // write the page
Damien George4e487002018-03-02 16:01:18 +1100218 mp_spiflash_write_cmd_addr_data(self, CMD_WRITE, addr, PAGE_SIZE, src);
Damien George784e0232017-01-24 16:56:03 +1100219
220 // wait WIP=0
221 return mp_spiflash_wait_wip0(self);
222}
223
224void mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100225 if (len == 0) {
226 return;
227 }
Damien George784e0232017-01-24 16:56:03 +1100228 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000229 mp_spiflash_cache_t *cache = self->config->cache;
230 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100231 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100232 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000233 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100234 // Read straddles current buffer
235 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000236 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100237 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000238 rest = cache->block * SECTOR_SIZE - addr;
Damien Georgebdc875e2018-03-13 14:13:30 +1100239 mp_spiflash_read_data(self, addr, rest, dest);
Damien George4e487002018-03-02 16:01:18 +1100240 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100241 dest += rest;
242 addr += rest;
243 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100244 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100245 rest = SECTOR_SIZE - offset;
246 if (rest > len) {
247 rest = len;
248 }
Damien George86fe73b2018-06-07 14:09:10 +1000249 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100250 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100251 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100252 mp_spiflash_release_bus(self);
253 return;
254 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100255 dest += rest;
256 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100257 }
Damien George4e487002018-03-02 16:01:18 +1100258 }
259 // Read rest direct from flash
260 mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100261 mp_spiflash_release_bus(self);
262}
263
Damien George4e487002018-03-02 16:01:18 +1100264STATIC void mp_spiflash_flush_internal(mp_spiflash_t *self) {
265 #if USE_WR_DELAY
266 if (!(self->flags & 1)) {
267 return;
268 }
Damien George784e0232017-01-24 16:56:03 +1100269
Damien George4e487002018-03-02 16:01:18 +1100270 self->flags &= ~1;
271
Damien George86fe73b2018-06-07 14:09:10 +1000272 mp_spiflash_cache_t *cache = self->config->cache;
273
Damien George4e487002018-03-02 16:01:18 +1100274 // Erase sector
Damien George86fe73b2018-06-07 14:09:10 +1000275 int ret = mp_spiflash_erase_sector(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100276 if (ret != 0) {
277 return;
278 }
279
280 // Write
281 for (int i = 0; i < 16; i += 1) {
Damien George86fe73b2018-06-07 14:09:10 +1000282 int ret = mp_spiflash_write_page(self, cache->block * SECTOR_SIZE + i * PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100283 if (ret != 0) {
284 return;
285 }
286 }
287 #endif
288}
289
290void mp_spiflash_flush(mp_spiflash_t *self) {
291 mp_spiflash_acquire_bus(self);
292 mp_spiflash_flush_internal(self);
293 mp_spiflash_release_bus(self);
294}
295
296STATIC int mp_spiflash_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
297 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100298 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100299 uint32_t sec = addr >> 12;
300 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100301
Damien George4e487002018-03-02 16:01:18 +1100302 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000303 if (offset + len > SECTOR_SIZE) {
Damien George4e487002018-03-02 16:01:18 +1100304 printf("mp_spiflash_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100305 return -MP_EIO;
306 }
307
Damien George86fe73b2018-06-07 14:09:10 +1000308 mp_spiflash_cache_t *cache = self->config->cache;
309
Damien George4e487002018-03-02 16:01:18 +1100310 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000311 if (cache->user != self) {
312 if (cache->user != NULL) {
313 mp_spiflash_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100314 }
Damien George86fe73b2018-06-07 14:09:10 +1000315 cache->user = self;
316 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100317 }
318
Damien George86fe73b2018-06-07 14:09:10 +1000319 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100320 // Read sector
321 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000322 if (cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100323 mp_spiflash_flush_internal(self);
324 }
325 #endif
Damien George86fe73b2018-06-07 14:09:10 +1000326 mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
Damien George4e487002018-03-02 16:01:18 +1100327 }
Damien George784e0232017-01-24 16:56:03 +1100328
Damien George4e487002018-03-02 16:01:18 +1100329 #if USE_WR_DELAY
330
Damien George86fe73b2018-06-07 14:09:10 +1000331 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100332 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000333 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100334 // And mark dirty
335 self->flags |= 1;
336
337 #else
338
339 uint32_t dirty = 0;
340 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000341 if (cache->buf[offset + i] != src[i]) {
342 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100343 // Erase sector
344 int ret = mp_spiflash_erase_sector(self, addr);
345 if (ret != 0) {
346 return ret;
347 }
348 dirty = 0xffff;
349 break;
350 } else {
351 dirty |= (1 << ((offset + i) >> 8));
352 }
Damien George784e0232017-01-24 16:56:03 +1100353 }
354 }
355
Damien George86fe73b2018-06-07 14:09:10 +1000356 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100357 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000358 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100359
360 // Write sector in pages of 256 bytes
361 for (size_t i = 0; i < 16; ++i) {
362 if (dirty & (1 << i)) {
Damien George86fe73b2018-06-07 14:09:10 +1000363 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100364 if (ret != 0) {
365 return ret;
366 }
367 }
368 }
369
370 #endif
371
Damien George784e0232017-01-24 16:56:03 +1100372 return 0; // success
373}
Damien George4e487002018-03-02 16:01:18 +1100374
375int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
376 uint32_t bis = addr / SECTOR_SIZE;
377 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
378
379 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100380
Damien George86fe73b2018-06-07 14:09:10 +1000381 mp_spiflash_cache_t *cache = self->config->cache;
382 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100383 // Write straddles current buffer
384 uint32_t pre;
385 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000386 if (cache->block * SECTOR_SIZE >= addr) {
387 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100388 offset = 0;
389 } else {
390 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000391 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100392 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100393
394 // Write buffered part first
395 uint32_t len_in_buf = len - pre;
396 len = 0;
397 if (len_in_buf > SECTOR_SIZE - offset) {
398 len = len_in_buf - (SECTOR_SIZE - offset);
399 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100400 }
Damien George86fe73b2018-06-07 14:09:10 +1000401 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100402 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100403
404 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100405 while (pre) {
406 int rest = pre & (SECTOR_SIZE - 1);
407 if (rest == 0) {
408 rest = SECTOR_SIZE;
409 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100410 int ret = mp_spiflash_write_part(self, addr, rest, src);
411 if (ret != 0) {
412 mp_spiflash_release_bus(self);
413 return ret;
414 }
415 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100416 addr += rest;
417 pre -= rest;
418 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100419 src += len_in_buf;
420 addr += len_in_buf;
421
422 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100423 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100424
425 uint32_t offset = addr & (SECTOR_SIZE - 1);
426 while (len) {
427 int rest = SECTOR_SIZE - offset;
428 if (rest > len) {
429 rest = len;
430 }
431 int ret = mp_spiflash_write_part(self, addr, rest, src);
432 if (ret != 0) {
433 mp_spiflash_release_bus(self);
434 return ret;
435 }
436 len -= rest;
437 addr += rest;
438 src += rest;
439 offset = 0;
440 }
441
Damien George4e487002018-03-02 16:01:18 +1100442 mp_spiflash_release_bus(self);
443 return 0;
444}