blob: 09ab7157b88eb5504ede7f2be77dadaad43c27d8 [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien George4e487002018-03-02 16:01:18 +110034#define QSPI_QE_MASK (0x02)
35#define USE_WR_DELAY (1)
36
37#define CMD_WRSR (0x01)
38#define CMD_WRITE (0x02)
39#define CMD_READ (0x03)
40#define CMD_RDSR (0x05)
41#define CMD_WREN (0x06)
42#define CMD_SEC_ERASE (0x20)
43#define CMD_RDCR (0x35)
44#define CMD_RD_DEVID (0x9f)
45#define CMD_CHIP_ERASE (0xc7)
46#define CMD_C4READ (0xeb)
iabdalkaderb5e80fa2024-11-29 16:56:20 +010047#define CMD_RSTEN (0x66)
48#define CMD_RESET (0x99)
Damien George4e487002018-03-02 16:01:18 +110049
Andrew Leech30501d32020-01-28 14:59:05 +110050// 32 bit addressing commands
51#define CMD_WRITE_32 (0x12)
52#define CMD_READ_32 (0x13)
53#define CMD_SEC_ERASE_32 (0x21)
54#define CMD_C4READ_32 (0xec)
55
Damien George784e0232017-01-24 16:56:03 +110056#define WAIT_SR_TIMEOUT (1000000)
57
58#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100059#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110060
Angus Grattondecf8e62024-02-27 15:32:29 +110061static void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110062 const mp_spiflash_config_t *c = self->config;
63 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110064 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE, 0);
Damien George4e487002018-03-02 16:01:18 +110065 }
Damien George784e0232017-01-24 16:56:03 +110066}
67
Angus Grattondecf8e62024-02-27 15:32:29 +110068static void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110069 const mp_spiflash_config_t *c = self->config;
70 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110071 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE, 0);
72 }
73}
74
75static void mp_spiflash_notify_modified(mp_spiflash_t *self, uint32_t addr, uint32_t len) {
76 const mp_spiflash_config_t *c = self->config;
77 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
78 uintptr_t arg[2] = { addr, len };
79 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_MEMORY_MODIFIED, (uintptr_t)&arg[0]);
Damien George4e487002018-03-02 16:01:18 +110080 }
Damien George784e0232017-01-24 16:56:03 +110081}
82
Angus Grattondecf8e62024-02-27 15:32:29 +110083static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110084 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110085 const mp_spiflash_config_t *c = self->config;
86 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
87 // Note: len/data are unused for standard SPI
88 mp_hal_pin_write(c->bus.u_spi.cs, 0);
89 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
90 mp_hal_pin_write(c->bus.u_spi.cs, 1);
91 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110092 ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
Damien George4e487002018-03-02 16:01:18 +110093 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +110094 return ret;
Damien George4e487002018-03-02 16:01:18 +110095}
96
Angus Grattondecf8e62024-02-27 15:32:29 +110097static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110098 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110099 const mp_spiflash_config_t *c = self->config;
100 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Andrew Leech30501d32020-01-28 14:59:05 +1100101 uint8_t buf[5] = {cmd, 0};
102 uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr);
Damien George4e487002018-03-02 16:01:18 +1100103 mp_hal_pin_write(c->bus.u_spi.cs, 0);
Andrew Leech30501d32020-01-28 14:59:05 +1100104 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL);
105 if (len && (src != NULL)) {
Damien George4e487002018-03-02 16:01:18 +1100106 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
Andrew Leech30501d32020-01-28 14:59:05 +1100107 } else if (len && (dest != NULL)) {
108 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
Damien George4e487002018-03-02 16:01:18 +1100109 }
Andrew Leech30501d32020-01-28 14:59:05 +1100110
Damien George4e487002018-03-02 16:01:18 +1100111 mp_hal_pin_write(c->bus.u_spi.cs, 1);
112 } else {
Andrew Leech30501d32020-01-28 14:59:05 +1100113 if (dest != NULL) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100114 ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, len, dest);
Andrew Leech30501d32020-01-28 14:59:05 +1100115 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100116 ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
Andrew Leech30501d32020-01-28 14:59:05 +1100117 }
Damien George4e487002018-03-02 16:01:18 +1100118 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100119 return ret;
Damien George4e487002018-03-02 16:01:18 +1100120}
121
Angus Grattondecf8e62024-02-27 15:32:29 +1100122static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100123 const mp_spiflash_config_t *c = self->config;
124 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George4e487002018-03-02 16:01:18 +1100125 mp_hal_pin_write(c->bus.u_spi.cs, 0);
126 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
Damien Georgeb042fd52022-12-09 12:28:54 +1100127 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)dest, (void*)dest);
Damien George4e487002018-03-02 16:01:18 +1100128 mp_hal_pin_write(c->bus.u_spi.cs, 1);
Damien Georgeb042fd52022-12-09 12:28:54 +1100129 return 0;
Damien George4e487002018-03-02 16:01:18 +1100130 } else {
Damien Georgeb042fd52022-12-09 12:28:54 +1100131 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest);
Damien George4e487002018-03-02 16:01:18 +1100132 }
133}
134
Angus Grattondecf8e62024-02-27 15:32:29 +1100135static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100136 const mp_spiflash_config_t *c = self->config;
Andrew Leech30501d32020-01-28 14:59:05 +1100137 uint8_t cmd;
Damien George4e487002018-03-02 16:01:18 +1100138 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George54f16942022-06-01 18:50:43 +1000139 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ;
Damien George4e487002018-03-02 16:01:18 +1100140 } else {
Damien George54f16942022-06-01 18:50:43 +1000141 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ;
Damien George4e487002018-03-02 16:01:18 +1100142 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100143 return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest);
Damien George4e487002018-03-02 16:01:18 +1100144}
145
Angus Grattondecf8e62024-02-27 15:32:29 +1100146static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100147 return mp_spiflash_write_cmd_data(self, cmd, 0, 0);
Damien George4e487002018-03-02 16:01:18 +1100148}
149
Angus Grattondecf8e62024-02-27 15:32:29 +1100150static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100151 do {
Damien Georgeb042fd52022-12-09 12:28:54 +1100152 uint32_t sr;
153 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
154 if (ret != 0) {
155 return ret;
156 }
Damien George4e487002018-03-02 16:01:18 +1100157 if ((sr & mask) == val) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100158 return 0; // success
Damien George784e0232017-01-24 16:56:03 +1100159 }
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100160 } while (timeout--);
161
162 return -MP_ETIMEDOUT;
Damien George784e0232017-01-24 16:56:03 +1100163}
164
Angus Grattondecf8e62024-02-27 15:32:29 +1100165static int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100166 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
167}
168
Angus Grattondecf8e62024-02-27 15:32:29 +1100169static int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100170 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
171}
172
Damien George8cde5fa2019-07-03 01:03:25 +1000173static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) {
174 mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake
175}
176
Damien George4e487002018-03-02 16:01:18 +1100177void mp_spiflash_init(mp_spiflash_t *self) {
178 self->flags = 0;
179
180 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
181 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
182 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100183 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100184 } else {
Damien Georgec61e8592025-03-19 15:47:35 +1100185 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, 0);
Damien George4e487002018-03-02 16:01:18 +1100186 }
187
188 mp_spiflash_acquire_bus(self);
189
Damien George8cde5fa2019-07-03 01:03:25 +1000190 // Ensure SPI flash is out of sleep mode
191 mp_spiflash_deepsleep_internal(self, 0);
192
iabdalkaderb5e80fa2024-11-29 16:56:20 +0100193 // Software reset.
194 #if MICROPY_HW_SPIFLASH_SOFT_RESET
195 mp_spiflash_write_cmd(self, CMD_RSTEN);
196 mp_spiflash_write_cmd(self, CMD_RESET);
197 mp_spiflash_wait_wip0(self);
198 mp_hal_delay_ms(1);
199 #endif
200
Damien George4e487002018-03-02 16:01:18 +1100201 #if defined(CHECK_DEVID)
202 // Validate device id
Damien Georgeb042fd52022-12-09 12:28:54 +1100203 uint32_t devid;
204 int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
205 if (ret != 0 || devid != CHECK_DEVID) {
206 mp_spiflash_release_bus(self);
207 return;
Damien George4e487002018-03-02 16:01:18 +1100208 }
209 #endif
210
211 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
212 // Set QE bit
Damien Georgeb042fd52022-12-09 12:28:54 +1100213 uint32_t sr = 0, cr = 0;
214 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
215 if (ret == 0) {
216 ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
217 }
218 uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
219 if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
Damien Georgecc34b082018-03-11 11:25:38 +1100220 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100221 mp_spiflash_write_cmd(self, CMD_WREN);
222 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
223 mp_spiflash_wait_wip0(self);
224 }
225 }
226
227 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100228}
229
Damien George8cde5fa2019-07-03 01:03:25 +1000230void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) {
231 if (value) {
232 mp_spiflash_acquire_bus(self);
233 }
234 mp_spiflash_deepsleep_internal(self, value);
235 if (!value) {
236 mp_spiflash_release_bus(self);
237 }
238}
239
Angus Grattondecf8e62024-02-27 15:32:29 +1100240static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100241 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100242 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100243 ret = mp_spiflash_write_cmd(self, CMD_WREN);
244 if (ret != 0) {
245 return ret;
246 }
Damien George784e0232017-01-24 16:56:03 +1100247
248 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100249 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100250 if (ret != 0) {
251 return ret;
252 }
253
254 // erase the sector
Damien George54f16942022-06-01 18:50:43 +1000255 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100256 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL);
257 if (ret != 0) {
258 return ret;
259 }
Damien George784e0232017-01-24 16:56:03 +1100260
261 // wait WIP=0
262 return mp_spiflash_wait_wip0(self);
263}
264
Angus Grattondecf8e62024-02-27 15:32:29 +1100265static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100266 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100267 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100268 ret = mp_spiflash_write_cmd(self, CMD_WREN);
269 if (ret != 0) {
270 return ret;
271 }
Damien George784e0232017-01-24 16:56:03 +1100272
273 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100274 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100275 if (ret != 0) {
276 return ret;
277 }
278
279 // write the page
Damien George54f16942022-06-01 18:50:43 +1000280 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100281 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL);
282 if (ret != 0) {
283 return ret;
284 }
Damien George784e0232017-01-24 16:56:03 +1100285
286 // wait WIP=0
287 return mp_spiflash_wait_wip0(self);
288}
289
Damien Georgecc5a9402018-06-07 15:36:27 +1000290/******************************************************************************/
Damien Georgeb78ca322018-06-07 15:39:46 +1000291// Interface functions that go direct to the SPI flash device
292
293int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
294 mp_spiflash_acquire_bus(self);
295 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien Georgec61e8592025-03-19 15:47:35 +1100296 mp_spiflash_notify_modified(self, addr, SECTOR_SIZE);
Damien Georgeb78ca322018-06-07 15:39:46 +1000297 mp_spiflash_release_bus(self);
298 return ret;
299}
300
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100301int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000302 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100303 return 0;
Damien Georgeb78ca322018-06-07 15:39:46 +1000304 }
305 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100306 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien Georgeb78ca322018-06-07 15:39:46 +1000307 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100308 return ret;
Damien Georgeb78ca322018-06-07 15:39:46 +1000309}
310
311int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien Georgec61e8592025-03-19 15:47:35 +1100312 uint32_t orig_addr = addr;
313 uint32_t orig_len = len;
Damien Georgeb78ca322018-06-07 15:39:46 +1000314 mp_spiflash_acquire_bus(self);
315 int ret = 0;
316 uint32_t offset = addr & (PAGE_SIZE - 1);
317 while (len) {
318 size_t rest = PAGE_SIZE - offset;
319 if (rest > len) {
320 rest = len;
321 }
322 ret = mp_spiflash_write_page(self, addr, rest, src);
323 if (ret != 0) {
324 break;
325 }
326 len -= rest;
327 addr += rest;
328 src += rest;
329 offset = 0;
330 }
Damien Georgec61e8592025-03-19 15:47:35 +1100331 mp_spiflash_notify_modified(self, orig_addr, orig_len);
Damien Georgeb78ca322018-06-07 15:39:46 +1000332 mp_spiflash_release_bus(self);
333 return ret;
334}
335
336/******************************************************************************/
Damien Georgecc5a9402018-06-07 15:36:27 +1000337// Interface functions that use the cache
Damien Georgec61e8592025-03-19 15:47:35 +1100338//
339// These functions do not call mp_spiflash_notify_modified(), so shouldn't be
340// used for memory-mapped flash (for example).
Damien Georgecc5a9402018-06-07 15:36:27 +1000341
Damien Georgee43a74a2020-12-17 16:59:54 +1100342#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
343
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100344int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100345 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100346 return 0;
Damien George4e487002018-03-02 16:01:18 +1100347 }
Damien George784e0232017-01-24 16:56:03 +1100348 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000349 mp_spiflash_cache_t *cache = self->config->cache;
350 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100351 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100352 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000353 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100354 // Read straddles current buffer
355 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000356 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100357 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000358 rest = cache->block * SECTOR_SIZE - addr;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100359 int ret = mp_spiflash_read_data(self, addr, rest, dest);
360 if (ret != 0) {
361 mp_spiflash_release_bus(self);
362 return ret;
363 }
Damien George4e487002018-03-02 16:01:18 +1100364 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100365 dest += rest;
366 addr += rest;
367 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100368 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100369 rest = SECTOR_SIZE - offset;
370 if (rest > len) {
371 rest = len;
372 }
Damien George86fe73b2018-06-07 14:09:10 +1000373 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100374 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100375 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100376 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100377 return 0;
Damien George4e487002018-03-02 16:01:18 +1100378 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100379 dest += rest;
380 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100381 }
Damien George4e487002018-03-02 16:01:18 +1100382 }
383 // Read rest direct from flash
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100384 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100385 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100386 return ret;
Damien George784e0232017-01-24 16:56:03 +1100387}
388
Angus Grattondecf8e62024-02-27 15:32:29 +1100389static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100390 #if USE_WR_DELAY
391 if (!(self->flags & 1)) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100392 return 0;
Damien George4e487002018-03-02 16:01:18 +1100393 }
Damien George784e0232017-01-24 16:56:03 +1100394
Damien George4e487002018-03-02 16:01:18 +1100395 self->flags &= ~1;
396
Damien George86fe73b2018-06-07 14:09:10 +1000397 mp_spiflash_cache_t *cache = self->config->cache;
398
Damien George4e487002018-03-02 16:01:18 +1100399 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000400 int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100401 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100402 return ret;
Damien George4e487002018-03-02 16:01:18 +1100403 }
404
405 // Write
406 for (int i = 0; i < 16; i += 1) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000407 uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
408 int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100409 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100410 return ret;
Damien George4e487002018-03-02 16:01:18 +1100411 }
412 }
413 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100414 return 0;
Damien George4e487002018-03-02 16:01:18 +1100415}
416
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100417int mp_spiflash_cache_flush(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100418 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100419 int ret = mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100420 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100421 return ret;
Damien George4e487002018-03-02 16:01:18 +1100422}
423
Angus Grattondecf8e62024-02-27 15:32:29 +1100424static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100425 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100426 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100427 uint32_t sec = addr >> 12;
428 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100429
Damien George4e487002018-03-02 16:01:18 +1100430 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000431 if (offset + len > SECTOR_SIZE) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000432 printf("mp_spiflash_cached_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100433 return -MP_EIO;
434 }
435
Damien George86fe73b2018-06-07 14:09:10 +1000436 mp_spiflash_cache_t *cache = self->config->cache;
437
Damien George4e487002018-03-02 16:01:18 +1100438 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000439 if (cache->user != self) {
440 if (cache->user != NULL) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000441 mp_spiflash_cache_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100442 }
Damien George86fe73b2018-06-07 14:09:10 +1000443 cache->user = self;
444 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100445 }
446
Damien George86fe73b2018-06-07 14:09:10 +1000447 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100448 // Read sector
449 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000450 if (cache->block != 0xffffffff) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100451 int ret = mp_spiflash_cache_flush_internal(self);
452 if (ret != 0) {
453 return ret;
454 }
Damien George4e487002018-03-02 16:01:18 +1100455 }
456 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100457 int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
458 if (ret != 0) {
459 return ret;
460 }
Damien George4e487002018-03-02 16:01:18 +1100461 }
Damien George784e0232017-01-24 16:56:03 +1100462
Damien George4e487002018-03-02 16:01:18 +1100463 #if USE_WR_DELAY
464
Damien George86fe73b2018-06-07 14:09:10 +1000465 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100466 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000467 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100468 // And mark dirty
469 self->flags |= 1;
470
471 #else
472
473 uint32_t dirty = 0;
474 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000475 if (cache->buf[offset + i] != src[i]) {
476 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100477 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000478 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien George4e487002018-03-02 16:01:18 +1100479 if (ret != 0) {
480 return ret;
481 }
482 dirty = 0xffff;
483 break;
484 } else {
485 dirty |= (1 << ((offset + i) >> 8));
486 }
Damien George784e0232017-01-24 16:56:03 +1100487 }
488 }
489
Damien George86fe73b2018-06-07 14:09:10 +1000490 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100491 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000492 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100493
494 // Write sector in pages of 256 bytes
495 for (size_t i = 0; i < 16; ++i) {
496 if (dirty & (1 << i)) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000497 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100498 if (ret != 0) {
499 return ret;
500 }
501 }
502 }
503
504 #endif
505
Damien George784e0232017-01-24 16:56:03 +1100506 return 0; // success
507}
Damien George4e487002018-03-02 16:01:18 +1100508
Damien Georgecc5a9402018-06-07 15:36:27 +1000509int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100510 uint32_t bis = addr / SECTOR_SIZE;
511 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
512
513 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100514
Damien George86fe73b2018-06-07 14:09:10 +1000515 mp_spiflash_cache_t *cache = self->config->cache;
516 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100517 // Write straddles current buffer
518 uint32_t pre;
519 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000520 if (cache->block * SECTOR_SIZE >= addr) {
521 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100522 offset = 0;
523 } else {
524 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000525 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100526 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100527
528 // Write buffered part first
529 uint32_t len_in_buf = len - pre;
530 len = 0;
531 if (len_in_buf > SECTOR_SIZE - offset) {
532 len = len_in_buf - (SECTOR_SIZE - offset);
533 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100534 }
Damien George86fe73b2018-06-07 14:09:10 +1000535 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100536 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100537
538 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100539 while (pre) {
540 int rest = pre & (SECTOR_SIZE - 1);
541 if (rest == 0) {
542 rest = SECTOR_SIZE;
543 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000544 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100545 if (ret != 0) {
546 mp_spiflash_release_bus(self);
547 return ret;
548 }
549 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100550 addr += rest;
551 pre -= rest;
552 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100553 src += len_in_buf;
554 addr += len_in_buf;
555
556 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100557 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100558
559 uint32_t offset = addr & (SECTOR_SIZE - 1);
560 while (len) {
561 int rest = SECTOR_SIZE - offset;
562 if (rest > len) {
563 rest = len;
564 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000565 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100566 if (ret != 0) {
567 mp_spiflash_release_bus(self);
568 return ret;
569 }
570 len -= rest;
571 addr += rest;
572 src += rest;
573 offset = 0;
574 }
575
Damien George4e487002018-03-02 16:01:18 +1100576 mp_spiflash_release_bus(self);
577 return 0;
578}
Damien Georgee43a74a2020-12-17 16:59:54 +1100579
580#endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE