Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the MicroPython project, http://micropython.org/ |
| 3 | * |
| 4 | * The MIT License (MIT) |
| 5 | * |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 6 | * Copyright (c) 2016-2018 Damien P. George |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include <stdio.h> |
| 28 | #include <string.h> |
| 29 | |
| 30 | #include "py/mperrno.h" |
| 31 | #include "py/mphal.h" |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 32 | #include "drivers/memory/spiflash.h" |
| 33 | |
Damien George | b078569 | 2025-04-02 12:47:48 +1100 | [diff] [blame] | 34 | #if defined(CHECK_DEVID) |
| 35 | #error "CHECK_DEVID no longer supported, use MICROPY_HW_SPIFLASH_DETECT_DEVICE instead" |
| 36 | #endif |
| 37 | |
Damien George | 2c0240e | 2025-04-02 12:47:40 +1100 | [diff] [blame] | 38 | // The default number of dummy bytes for quad-read is 2. This can be changed by enabling |
| 39 | // MICROPY_HW_SPIFLASH_CHIP_PARAMS and configuring the value in mp_spiflash_chip_params_t. |
| 40 | #if MICROPY_HW_SPIFLASH_CHIP_PARAMS |
| 41 | #define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (spiflash->chip_params->qread_num_dummy) |
| 42 | #else |
| 43 | #define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (2) |
| 44 | #endif |
| 45 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 46 | #define QSPI_QE_MASK (0x02) |
| 47 | #define USE_WR_DELAY (1) |
| 48 | |
| 49 | #define CMD_WRSR (0x01) |
| 50 | #define CMD_WRITE (0x02) |
| 51 | #define CMD_READ (0x03) |
| 52 | #define CMD_RDSR (0x05) |
| 53 | #define CMD_WREN (0x06) |
| 54 | #define CMD_SEC_ERASE (0x20) |
| 55 | #define CMD_RDCR (0x35) |
| 56 | #define CMD_RD_DEVID (0x9f) |
| 57 | #define CMD_CHIP_ERASE (0xc7) |
| 58 | #define CMD_C4READ (0xeb) |
iabdalkader | b5e80fa | 2024-11-29 16:56:20 +0100 | [diff] [blame] | 59 | #define CMD_RSTEN (0x66) |
| 60 | #define CMD_RESET (0x99) |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 61 | |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 62 | // 32 bit addressing commands |
| 63 | #define CMD_WRITE_32 (0x12) |
| 64 | #define CMD_READ_32 (0x13) |
| 65 | #define CMD_SEC_ERASE_32 (0x21) |
| 66 | #define CMD_C4READ_32 (0xec) |
| 67 | |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 68 | #define WAIT_SR_TIMEOUT (1000000) |
| 69 | |
| 70 | #define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 71 | #define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 72 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 73 | static void mp_spiflash_acquire_bus(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 74 | const mp_spiflash_config_t *c = self->config; |
| 75 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 76 | c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE, 0); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 77 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 78 | } |
| 79 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 80 | static void mp_spiflash_release_bus(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 81 | const mp_spiflash_config_t *c = self->config; |
| 82 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 83 | c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE, 0); |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | static void mp_spiflash_notify_modified(mp_spiflash_t *self, uint32_t addr, uint32_t len) { |
| 88 | const mp_spiflash_config_t *c = self->config; |
| 89 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
| 90 | uintptr_t arg[2] = { addr, len }; |
| 91 | c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_MEMORY_MODIFIED, (uintptr_t)&arg[0]); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 92 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 93 | } |
| 94 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 95 | static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 96 | int ret = 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 97 | const mp_spiflash_config_t *c = self->config; |
| 98 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 99 | // Note: len/data are unused for standard SPI |
| 100 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 101 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL); |
| 102 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 103 | } else { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 104 | ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 105 | } |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 106 | return ret; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 107 | } |
| 108 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 109 | static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 110 | int ret = 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 111 | const mp_spiflash_config_t *c = self->config; |
| 112 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 113 | uint8_t buf[5] = {cmd, 0}; |
| 114 | uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 115 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 116 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL); |
| 117 | if (len && (src != NULL)) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 118 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL); |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 119 | } else if (len && (dest != NULL)) { |
| 120 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 121 | } |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 122 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 123 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
| 124 | } else { |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 125 | if (dest != NULL) { |
Damien George | 2c0240e | 2025-04-02 12:47:40 +1100 | [diff] [blame] | 126 | uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self); |
| 127 | ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, num_dummy, len, dest); |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 128 | } else { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 129 | ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src); |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 130 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 131 | } |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 132 | return ret; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 133 | } |
| 134 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 135 | static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 136 | const mp_spiflash_config_t *c = self->config; |
| 137 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 138 | mp_hal_pin_write(c->bus.u_spi.cs, 0); |
| 139 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL); |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 140 | c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)dest, (void*)dest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 141 | mp_hal_pin_write(c->bus.u_spi.cs, 1); |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 142 | return 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 143 | } else { |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 144 | return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 145 | } |
| 146 | } |
| 147 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 148 | static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 149 | const mp_spiflash_config_t *c = self->config; |
Andrew Leech | 30501d3 | 2020-01-28 14:59:05 +1100 | [diff] [blame] | 150 | uint8_t cmd; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 151 | if (c->bus_kind == MP_SPIFLASH_BUS_SPI) { |
Damien George | 54f1694 | 2022-06-01 18:50:43 +1000 | [diff] [blame] | 152 | cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 153 | } else { |
Damien George | 54f1694 | 2022-06-01 18:50:43 +1000 | [diff] [blame] | 154 | cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 155 | } |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 156 | return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 157 | } |
| 158 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 159 | static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 160 | return mp_spiflash_write_cmd_data(self, cmd, 0, 0); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 161 | } |
| 162 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 163 | static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) { |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame] | 164 | do { |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 165 | uint32_t sr; |
| 166 | int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr); |
| 167 | if (ret != 0) { |
| 168 | return ret; |
| 169 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 170 | if ((sr & mask) == val) { |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame] | 171 | return 0; // success |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 172 | } |
Andrew Leech | 2ed2ec1 | 2019-01-29 15:20:01 +1100 | [diff] [blame] | 173 | } while (timeout--); |
| 174 | |
| 175 | return -MP_ETIMEDOUT; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 176 | } |
| 177 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 178 | static int mp_spiflash_wait_wel1(mp_spiflash_t *self) { |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 179 | return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT); |
| 180 | } |
| 181 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 182 | static int mp_spiflash_wait_wip0(mp_spiflash_t *self) { |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 183 | return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT); |
| 184 | } |
| 185 | |
Damien George | 8cde5fa | 2019-07-03 01:03:25 +1000 | [diff] [blame] | 186 | static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) { |
| 187 | mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake |
| 188 | } |
| 189 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 190 | void mp_spiflash_init(mp_spiflash_t *self) { |
| 191 | self->flags = 0; |
| 192 | |
| 193 | if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) { |
| 194 | mp_hal_pin_write(self->config->bus.u_spi.cs, 1); |
| 195 | mp_hal_pin_output(self->config->bus.u_spi.cs); |
Damien George | a739b35 | 2018-03-09 17:32:28 +1100 | [diff] [blame] | 196 | self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 197 | } else { |
Damien George | 2c0240e | 2025-04-02 12:47:40 +1100 | [diff] [blame] | 198 | uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self); |
| 199 | self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, num_dummy); |
Damien George | 62a674c | 2025-05-01 01:19:52 +1000 | [diff] [blame] | 200 | if (self->config->bus.u_qspi.proto->direct_read != NULL) { |
| 201 | // A bus with a custom read function should not have any further initialisation done. |
| 202 | return; |
| 203 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | mp_spiflash_acquire_bus(self); |
| 207 | |
Damien George | 8cde5fa | 2019-07-03 01:03:25 +1000 | [diff] [blame] | 208 | // Ensure SPI flash is out of sleep mode |
| 209 | mp_spiflash_deepsleep_internal(self, 0); |
| 210 | |
iabdalkader | b5e80fa | 2024-11-29 16:56:20 +0100 | [diff] [blame] | 211 | // Software reset. |
| 212 | #if MICROPY_HW_SPIFLASH_SOFT_RESET |
| 213 | mp_spiflash_write_cmd(self, CMD_RSTEN); |
| 214 | mp_spiflash_write_cmd(self, CMD_RESET); |
| 215 | mp_spiflash_wait_wip0(self); |
| 216 | mp_hal_delay_ms(1); |
| 217 | #endif |
| 218 | |
Damien George | b078569 | 2025-04-02 12:47:48 +1100 | [diff] [blame] | 219 | #if MICROPY_HW_SPIFLASH_DETECT_DEVICE |
| 220 | // Attempt to detect SPI flash based on its JEDEC id. |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 221 | uint32_t devid; |
| 222 | int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid); |
Damien George | b078569 | 2025-04-02 12:47:48 +1100 | [diff] [blame] | 223 | ret = mp_spiflash_detect(self, ret, devid); |
| 224 | if (ret != 0) { |
| 225 | // Could not read device id. |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 226 | mp_spiflash_release_bus(self); |
| 227 | return; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 228 | } |
| 229 | #endif |
| 230 | |
| 231 | if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) { |
| 232 | // Set QE bit |
Damien George | b042fd5 | 2022-12-09 12:28:54 +1100 | [diff] [blame] | 233 | uint32_t sr = 0, cr = 0; |
| 234 | int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr); |
| 235 | if (ret == 0) { |
| 236 | ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr); |
| 237 | } |
| 238 | uint32_t data = (sr & 0xff) | (cr & 0xff) << 8; |
| 239 | if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) { |
Damien George | cc34b08 | 2018-03-11 11:25:38 +1100 | [diff] [blame] | 240 | data |= QSPI_QE_MASK << 8; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 241 | mp_spiflash_write_cmd(self, CMD_WREN); |
| 242 | mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data); |
| 243 | mp_spiflash_wait_wip0(self); |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | mp_spiflash_release_bus(self); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 248 | } |
| 249 | |
Damien George | 8cde5fa | 2019-07-03 01:03:25 +1000 | [diff] [blame] | 250 | void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) { |
| 251 | if (value) { |
| 252 | mp_spiflash_acquire_bus(self); |
| 253 | } |
| 254 | mp_spiflash_deepsleep_internal(self, value); |
| 255 | if (!value) { |
| 256 | mp_spiflash_release_bus(self); |
| 257 | } |
| 258 | } |
| 259 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 260 | static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 261 | int ret = 0; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 262 | // enable writes |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 263 | ret = mp_spiflash_write_cmd(self, CMD_WREN); |
| 264 | if (ret != 0) { |
| 265 | return ret; |
| 266 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 267 | |
| 268 | // wait WEL=1 |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 269 | ret = mp_spiflash_wait_wel1(self); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 270 | if (ret != 0) { |
| 271 | return ret; |
| 272 | } |
| 273 | |
| 274 | // erase the sector |
Damien George | 54f1694 | 2022-06-01 18:50:43 +1000 | [diff] [blame] | 275 | uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE; |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 276 | ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL); |
| 277 | if (ret != 0) { |
| 278 | return ret; |
| 279 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 280 | |
| 281 | // wait WIP=0 |
| 282 | return mp_spiflash_wait_wip0(self); |
| 283 | } |
| 284 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 285 | static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 286 | int ret = 0; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 287 | // enable writes |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 288 | ret = mp_spiflash_write_cmd(self, CMD_WREN); |
| 289 | if (ret != 0) { |
| 290 | return ret; |
| 291 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 292 | |
| 293 | // wait WEL=1 |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 294 | ret = mp_spiflash_wait_wel1(self); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 295 | if (ret != 0) { |
| 296 | return ret; |
| 297 | } |
| 298 | |
| 299 | // write the page |
Damien George | 54f1694 | 2022-06-01 18:50:43 +1000 | [diff] [blame] | 300 | uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE; |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 301 | ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL); |
| 302 | if (ret != 0) { |
| 303 | return ret; |
| 304 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 305 | |
| 306 | // wait WIP=0 |
| 307 | return mp_spiflash_wait_wip0(self); |
| 308 | } |
| 309 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 310 | /******************************************************************************/ |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 311 | // Interface functions that go direct to the SPI flash device |
| 312 | |
| 313 | int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) { |
| 314 | mp_spiflash_acquire_bus(self); |
| 315 | int ret = mp_spiflash_erase_block_internal(self, addr); |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 316 | mp_spiflash_notify_modified(self, addr, SECTOR_SIZE); |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 317 | mp_spiflash_release_bus(self); |
| 318 | return ret; |
| 319 | } |
| 320 | |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 321 | int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 322 | if (len == 0) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 323 | return 0; |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 324 | } |
Damien George | 62a674c | 2025-05-01 01:19:52 +1000 | [diff] [blame] | 325 | const mp_spiflash_config_t *c = self->config; |
| 326 | if (c->bus_kind == MP_SPIFLASH_BUS_QSPI && c->bus.u_qspi.proto->direct_read != NULL) { |
| 327 | return c->bus.u_qspi.proto->direct_read(c->bus.u_qspi.data, addr, len, dest); |
| 328 | } |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 329 | mp_spiflash_acquire_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 330 | int ret = mp_spiflash_read_data(self, addr, len, dest); |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 331 | mp_spiflash_release_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 332 | return ret; |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 336 | uint32_t orig_addr = addr; |
| 337 | uint32_t orig_len = len; |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 338 | mp_spiflash_acquire_bus(self); |
| 339 | int ret = 0; |
| 340 | uint32_t offset = addr & (PAGE_SIZE - 1); |
| 341 | while (len) { |
| 342 | size_t rest = PAGE_SIZE - offset; |
| 343 | if (rest > len) { |
| 344 | rest = len; |
| 345 | } |
| 346 | ret = mp_spiflash_write_page(self, addr, rest, src); |
| 347 | if (ret != 0) { |
| 348 | break; |
| 349 | } |
| 350 | len -= rest; |
| 351 | addr += rest; |
| 352 | src += rest; |
| 353 | offset = 0; |
| 354 | } |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 355 | mp_spiflash_notify_modified(self, orig_addr, orig_len); |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 356 | mp_spiflash_release_bus(self); |
| 357 | return ret; |
| 358 | } |
| 359 | |
| 360 | /******************************************************************************/ |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 361 | // Interface functions that use the cache |
Damien George | c61e859 | 2025-03-19 15:47:35 +1100 | [diff] [blame] | 362 | // |
| 363 | // These functions do not call mp_spiflash_notify_modified(), so shouldn't be |
| 364 | // used for memory-mapped flash (for example). |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 365 | |
Damien George | e43a74a | 2020-12-17 16:59:54 +1100 | [diff] [blame] | 366 | #if MICROPY_HW_SPIFLASH_ENABLE_CACHE |
| 367 | |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 368 | int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 369 | if (len == 0) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 370 | return 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 371 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 372 | mp_spiflash_acquire_bus(self); |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 373 | mp_spiflash_cache_t *cache = self->config->cache; |
| 374 | if (cache->user == self && cache->block != 0xffffffff) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 375 | uint32_t bis = addr / SECTOR_SIZE; |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 376 | uint32_t bie = (addr + len - 1) / SECTOR_SIZE; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 377 | if (bis <= cache->block && cache->block <= bie) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 378 | // Read straddles current buffer |
| 379 | size_t rest = 0; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 380 | if (bis < cache->block) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 381 | // Read direct from flash for first part |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 382 | rest = cache->block * SECTOR_SIZE - addr; |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 383 | int ret = mp_spiflash_read_data(self, addr, rest, dest); |
| 384 | if (ret != 0) { |
| 385 | mp_spiflash_release_bus(self); |
| 386 | return ret; |
| 387 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 388 | len -= rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 389 | dest += rest; |
| 390 | addr += rest; |
| 391 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 392 | uint32_t offset = addr & (SECTOR_SIZE - 1); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 393 | rest = SECTOR_SIZE - offset; |
| 394 | if (rest > len) { |
| 395 | rest = len; |
| 396 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 397 | memcpy(dest, &cache->buf[offset], rest); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 398 | len -= rest; |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 399 | if (len == 0) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 400 | mp_spiflash_release_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 401 | return 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 402 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 403 | dest += rest; |
| 404 | addr += rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 405 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 406 | } |
| 407 | // Read rest direct from flash |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 408 | int ret = mp_spiflash_read_data(self, addr, len, dest); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 409 | mp_spiflash_release_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 410 | return ret; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 411 | } |
| 412 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 413 | static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 414 | #if USE_WR_DELAY |
| 415 | if (!(self->flags & 1)) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 416 | return 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 417 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 418 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 419 | self->flags &= ~1; |
| 420 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 421 | mp_spiflash_cache_t *cache = self->config->cache; |
| 422 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 423 | // Erase sector |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 424 | int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 425 | if (ret != 0) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 426 | return ret; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | // Write |
| 430 | for (int i = 0; i < 16; i += 1) { |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 431 | uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE; |
| 432 | int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 433 | if (ret != 0) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 434 | return ret; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 435 | } |
| 436 | } |
| 437 | #endif |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 438 | return 0; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 439 | } |
| 440 | |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 441 | int mp_spiflash_cache_flush(mp_spiflash_t *self) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 442 | mp_spiflash_acquire_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 443 | int ret = mp_spiflash_cache_flush_internal(self); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 444 | mp_spiflash_release_bus(self); |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 445 | return ret; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 446 | } |
| 447 | |
Angus Gratton | decf8e6 | 2024-02-27 15:32:29 +1100 | [diff] [blame] | 448 | static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 449 | // Align to 4096 sector |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 450 | uint32_t offset = addr & 0xfff; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 451 | uint32_t sec = addr >> 12; |
| 452 | addr = sec << 12; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 453 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 454 | // Restriction for now, so we don't need to erase multiple pages |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 455 | if (offset + len > SECTOR_SIZE) { |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 456 | printf("mp_spiflash_cached_write_part: len is too large\n"); |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 457 | return -MP_EIO; |
| 458 | } |
| 459 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 460 | mp_spiflash_cache_t *cache = self->config->cache; |
| 461 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 462 | // Acquire the sector buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 463 | if (cache->user != self) { |
| 464 | if (cache->user != NULL) { |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 465 | mp_spiflash_cache_flush(cache->user); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 466 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 467 | cache->user = self; |
| 468 | cache->block = 0xffffffff; |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 469 | } |
| 470 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 471 | if (cache->block != sec) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 472 | // Read sector |
| 473 | #if USE_WR_DELAY |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 474 | if (cache->block != 0xffffffff) { |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 475 | int ret = mp_spiflash_cache_flush_internal(self); |
| 476 | if (ret != 0) { |
| 477 | return ret; |
| 478 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 479 | } |
| 480 | #endif |
Andrew Leech | 7ee5afe | 2021-03-05 10:15:29 +1100 | [diff] [blame] | 481 | int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf); |
| 482 | if (ret != 0) { |
| 483 | return ret; |
| 484 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 485 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 486 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 487 | #if USE_WR_DELAY |
| 488 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 489 | cache->block = sec; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 490 | // Just copy to buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 491 | memcpy(cache->buf + offset, src, len); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 492 | // And mark dirty |
| 493 | self->flags |= 1; |
| 494 | |
| 495 | #else |
| 496 | |
| 497 | uint32_t dirty = 0; |
| 498 | for (size_t i = 0; i < len; ++i) { |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 499 | if (cache->buf[offset + i] != src[i]) { |
| 500 | if (cache->buf[offset + i] != 0xff) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 501 | // Erase sector |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 502 | int ret = mp_spiflash_erase_block_internal(self, addr); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 503 | if (ret != 0) { |
| 504 | return ret; |
| 505 | } |
| 506 | dirty = 0xffff; |
| 507 | break; |
| 508 | } else { |
| 509 | dirty |= (1 << ((offset + i) >> 8)); |
| 510 | } |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 514 | cache->block = sec; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 515 | // Copy new block into buffer |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 516 | memcpy(cache->buf + offset, src, len); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 517 | |
| 518 | // Write sector in pages of 256 bytes |
| 519 | for (size_t i = 0; i < 16; ++i) { |
| 520 | if (dirty & (1 << i)) { |
Damien George | b78ca32 | 2018-06-07 15:39:46 +1000 | [diff] [blame] | 521 | int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 522 | if (ret != 0) { |
| 523 | return ret; |
| 524 | } |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | #endif |
| 529 | |
Damien George | 784e023 | 2017-01-24 16:56:03 +1100 | [diff] [blame] | 530 | return 0; // success |
| 531 | } |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 532 | |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 533 | int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) { |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 534 | uint32_t bis = addr / SECTOR_SIZE; |
| 535 | uint32_t bie = (addr + len - 1) / SECTOR_SIZE; |
| 536 | |
| 537 | mp_spiflash_acquire_bus(self); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 538 | |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 539 | mp_spiflash_cache_t *cache = self->config->cache; |
| 540 | if (cache->user == self && bis <= cache->block && bie >= cache->block) { |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 541 | // Write straddles current buffer |
| 542 | uint32_t pre; |
| 543 | uint32_t offset; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 544 | if (cache->block * SECTOR_SIZE >= addr) { |
| 545 | pre = cache->block * SECTOR_SIZE - addr; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 546 | offset = 0; |
| 547 | } else { |
| 548 | pre = 0; |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 549 | offset = addr - cache->block * SECTOR_SIZE; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 550 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 551 | |
| 552 | // Write buffered part first |
| 553 | uint32_t len_in_buf = len - pre; |
| 554 | len = 0; |
| 555 | if (len_in_buf > SECTOR_SIZE - offset) { |
| 556 | len = len_in_buf - (SECTOR_SIZE - offset); |
| 557 | len_in_buf = SECTOR_SIZE - offset; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 558 | } |
Damien George | 86fe73b | 2018-06-07 14:09:10 +1000 | [diff] [blame] | 559 | memcpy(&cache->buf[offset], &src[pre], len_in_buf); |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 560 | self->flags |= 1; // Mark dirty |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 561 | |
| 562 | // Write part before buffer sector |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 563 | while (pre) { |
| 564 | int rest = pre & (SECTOR_SIZE - 1); |
| 565 | if (rest == 0) { |
| 566 | rest = SECTOR_SIZE; |
| 567 | } |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 568 | int ret = mp_spiflash_cached_write_part(self, addr, rest, src); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 569 | if (ret != 0) { |
| 570 | mp_spiflash_release_bus(self); |
| 571 | return ret; |
| 572 | } |
| 573 | src += rest; |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 574 | addr += rest; |
| 575 | pre -= rest; |
| 576 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 577 | src += len_in_buf; |
| 578 | addr += len_in_buf; |
| 579 | |
| 580 | // Fall through to write remaining part |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 581 | } |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 582 | |
| 583 | uint32_t offset = addr & (SECTOR_SIZE - 1); |
| 584 | while (len) { |
| 585 | int rest = SECTOR_SIZE - offset; |
| 586 | if (rest > len) { |
| 587 | rest = len; |
| 588 | } |
Damien George | cc5a940 | 2018-06-07 15:36:27 +1000 | [diff] [blame] | 589 | int ret = mp_spiflash_cached_write_part(self, addr, rest, src); |
Damien George | bdc875e | 2018-03-13 14:13:30 +1100 | [diff] [blame] | 590 | if (ret != 0) { |
| 591 | mp_spiflash_release_bus(self); |
| 592 | return ret; |
| 593 | } |
| 594 | len -= rest; |
| 595 | addr += rest; |
| 596 | src += rest; |
| 597 | offset = 0; |
| 598 | } |
| 599 | |
Damien George | 4e48700 | 2018-03-02 16:01:18 +1100 | [diff] [blame] | 600 | mp_spiflash_release_bus(self); |
| 601 | return 0; |
| 602 | } |
Damien George | e43a74a | 2020-12-17 16:59:54 +1100 | [diff] [blame] | 603 | |
| 604 | #endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE |