blob: 7cd1d18a3f941a3358d160dcb84c71d61981db09 [file] [log] [blame]
Damien George784e0232017-01-24 16:56:03 +11001/*
2 * This file is part of the MicroPython project, http://micropython.org/
3 *
4 * The MIT License (MIT)
5 *
Damien George4e487002018-03-02 16:01:18 +11006 * Copyright (c) 2016-2018 Damien P. George
Damien George784e0232017-01-24 16:56:03 +11007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include <stdio.h>
28#include <string.h>
29
30#include "py/mperrno.h"
31#include "py/mphal.h"
Damien George784e0232017-01-24 16:56:03 +110032#include "drivers/memory/spiflash.h"
33
Damien Georgeb0785692025-04-02 12:47:48 +110034#if defined(CHECK_DEVID)
35#error "CHECK_DEVID no longer supported, use MICROPY_HW_SPIFLASH_DETECT_DEVICE instead"
36#endif
37
Damien George2c0240e2025-04-02 12:47:40 +110038// The default number of dummy bytes for quad-read is 2. This can be changed by enabling
39// MICROPY_HW_SPIFLASH_CHIP_PARAMS and configuring the value in mp_spiflash_chip_params_t.
40#if MICROPY_HW_SPIFLASH_CHIP_PARAMS
41#define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (spiflash->chip_params->qread_num_dummy)
42#else
43#define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (2)
44#endif
45
Damien George4e487002018-03-02 16:01:18 +110046#define QSPI_QE_MASK (0x02)
47#define USE_WR_DELAY (1)
48
49#define CMD_WRSR (0x01)
50#define CMD_WRITE (0x02)
51#define CMD_READ (0x03)
52#define CMD_RDSR (0x05)
53#define CMD_WREN (0x06)
54#define CMD_SEC_ERASE (0x20)
55#define CMD_RDCR (0x35)
56#define CMD_RD_DEVID (0x9f)
57#define CMD_CHIP_ERASE (0xc7)
58#define CMD_C4READ (0xeb)
iabdalkaderb5e80fa2024-11-29 16:56:20 +010059#define CMD_RSTEN (0x66)
60#define CMD_RESET (0x99)
Damien George4e487002018-03-02 16:01:18 +110061
Andrew Leech30501d32020-01-28 14:59:05 +110062// 32 bit addressing commands
63#define CMD_WRITE_32 (0x12)
64#define CMD_READ_32 (0x13)
65#define CMD_SEC_ERASE_32 (0x21)
66#define CMD_C4READ_32 (0xec)
67
Damien George784e0232017-01-24 16:56:03 +110068#define WAIT_SR_TIMEOUT (1000000)
69
70#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
Damien George86fe73b2018-06-07 14:09:10 +100071#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
Damien George784e0232017-01-24 16:56:03 +110072
Angus Grattondecf8e62024-02-27 15:32:29 +110073static void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110074 const mp_spiflash_config_t *c = self->config;
75 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110076 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE, 0);
Damien George4e487002018-03-02 16:01:18 +110077 }
Damien George784e0232017-01-24 16:56:03 +110078}
79
Angus Grattondecf8e62024-02-27 15:32:29 +110080static void mp_spiflash_release_bus(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +110081 const mp_spiflash_config_t *c = self->config;
82 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
Damien Georgec61e8592025-03-19 15:47:35 +110083 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE, 0);
84 }
85}
86
87static void mp_spiflash_notify_modified(mp_spiflash_t *self, uint32_t addr, uint32_t len) {
88 const mp_spiflash_config_t *c = self->config;
89 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
90 uintptr_t arg[2] = { addr, len };
91 c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_MEMORY_MODIFIED, (uintptr_t)&arg[0]);
Damien George4e487002018-03-02 16:01:18 +110092 }
Damien George784e0232017-01-24 16:56:03 +110093}
94
Angus Grattondecf8e62024-02-27 15:32:29 +110095static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +110096 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +110097 const mp_spiflash_config_t *c = self->config;
98 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
99 // Note: len/data are unused for standard SPI
100 mp_hal_pin_write(c->bus.u_spi.cs, 0);
101 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
102 mp_hal_pin_write(c->bus.u_spi.cs, 1);
103 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100104 ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
Damien George4e487002018-03-02 16:01:18 +1100105 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100106 return ret;
Damien George4e487002018-03-02 16:01:18 +1100107}
108
Angus Grattondecf8e62024-02-27 15:32:29 +1100109static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100110 int ret = 0;
Damien George4e487002018-03-02 16:01:18 +1100111 const mp_spiflash_config_t *c = self->config;
112 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Andrew Leech30501d32020-01-28 14:59:05 +1100113 uint8_t buf[5] = {cmd, 0};
114 uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr);
Damien George4e487002018-03-02 16:01:18 +1100115 mp_hal_pin_write(c->bus.u_spi.cs, 0);
Andrew Leech30501d32020-01-28 14:59:05 +1100116 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL);
117 if (len && (src != NULL)) {
Damien George4e487002018-03-02 16:01:18 +1100118 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
Andrew Leech30501d32020-01-28 14:59:05 +1100119 } else if (len && (dest != NULL)) {
120 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
Damien George4e487002018-03-02 16:01:18 +1100121 }
Andrew Leech30501d32020-01-28 14:59:05 +1100122
Damien George4e487002018-03-02 16:01:18 +1100123 mp_hal_pin_write(c->bus.u_spi.cs, 1);
124 } else {
Andrew Leech30501d32020-01-28 14:59:05 +1100125 if (dest != NULL) {
Damien George2c0240e2025-04-02 12:47:40 +1100126 uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self);
127 ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, num_dummy, len, dest);
Andrew Leech30501d32020-01-28 14:59:05 +1100128 } else {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100129 ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
Andrew Leech30501d32020-01-28 14:59:05 +1100130 }
Damien George4e487002018-03-02 16:01:18 +1100131 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100132 return ret;
Damien George4e487002018-03-02 16:01:18 +1100133}
134
Angus Grattondecf8e62024-02-27 15:32:29 +1100135static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100136 const mp_spiflash_config_t *c = self->config;
137 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George4e487002018-03-02 16:01:18 +1100138 mp_hal_pin_write(c->bus.u_spi.cs, 0);
139 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
Damien Georgeb042fd52022-12-09 12:28:54 +1100140 c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void*)dest, (void*)dest);
Damien George4e487002018-03-02 16:01:18 +1100141 mp_hal_pin_write(c->bus.u_spi.cs, 1);
Damien Georgeb042fd52022-12-09 12:28:54 +1100142 return 0;
Damien George4e487002018-03-02 16:01:18 +1100143 } else {
Damien Georgeb042fd52022-12-09 12:28:54 +1100144 return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest);
Damien George4e487002018-03-02 16:01:18 +1100145 }
146}
147
Angus Grattondecf8e62024-02-27 15:32:29 +1100148static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100149 const mp_spiflash_config_t *c = self->config;
Andrew Leech30501d32020-01-28 14:59:05 +1100150 uint8_t cmd;
Damien George4e487002018-03-02 16:01:18 +1100151 if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
Damien George54f16942022-06-01 18:50:43 +1000152 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ;
Damien George4e487002018-03-02 16:01:18 +1100153 } else {
Damien George54f16942022-06-01 18:50:43 +1000154 cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ;
Damien George4e487002018-03-02 16:01:18 +1100155 }
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100156 return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest);
Damien George4e487002018-03-02 16:01:18 +1100157}
158
Angus Grattondecf8e62024-02-27 15:32:29 +1100159static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100160 return mp_spiflash_write_cmd_data(self, cmd, 0, 0);
Damien George4e487002018-03-02 16:01:18 +1100161}
162
Angus Grattondecf8e62024-02-27 15:32:29 +1100163static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100164 do {
Damien Georgeb042fd52022-12-09 12:28:54 +1100165 uint32_t sr;
166 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
167 if (ret != 0) {
168 return ret;
169 }
Damien George4e487002018-03-02 16:01:18 +1100170 if ((sr & mask) == val) {
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100171 return 0; // success
Damien George784e0232017-01-24 16:56:03 +1100172 }
Andrew Leech2ed2ec12019-01-29 15:20:01 +1100173 } while (timeout--);
174
175 return -MP_ETIMEDOUT;
Damien George784e0232017-01-24 16:56:03 +1100176}
177
Angus Grattondecf8e62024-02-27 15:32:29 +1100178static int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100179 return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
180}
181
Angus Grattondecf8e62024-02-27 15:32:29 +1100182static int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
Damien George784e0232017-01-24 16:56:03 +1100183 return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
184}
185
Damien George8cde5fa2019-07-03 01:03:25 +1000186static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) {
187 mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake
188}
189
Damien George4e487002018-03-02 16:01:18 +1100190void mp_spiflash_init(mp_spiflash_t *self) {
191 self->flags = 0;
192
193 if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
194 mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
195 mp_hal_pin_output(self->config->bus.u_spi.cs);
Damien Georgea739b352018-03-09 17:32:28 +1100196 self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
Damien George4e487002018-03-02 16:01:18 +1100197 } else {
Damien George2c0240e2025-04-02 12:47:40 +1100198 uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self);
199 self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, num_dummy);
Damien George62a674c2025-05-01 01:19:52 +1000200 if (self->config->bus.u_qspi.proto->direct_read != NULL) {
201 // A bus with a custom read function should not have any further initialisation done.
202 return;
203 }
Damien George4e487002018-03-02 16:01:18 +1100204 }
205
206 mp_spiflash_acquire_bus(self);
207
Damien George8cde5fa2019-07-03 01:03:25 +1000208 // Ensure SPI flash is out of sleep mode
209 mp_spiflash_deepsleep_internal(self, 0);
210
iabdalkaderb5e80fa2024-11-29 16:56:20 +0100211 // Software reset.
212 #if MICROPY_HW_SPIFLASH_SOFT_RESET
213 mp_spiflash_write_cmd(self, CMD_RSTEN);
214 mp_spiflash_write_cmd(self, CMD_RESET);
215 mp_spiflash_wait_wip0(self);
216 mp_hal_delay_ms(1);
217 #endif
218
Damien Georgeb0785692025-04-02 12:47:48 +1100219 #if MICROPY_HW_SPIFLASH_DETECT_DEVICE
220 // Attempt to detect SPI flash based on its JEDEC id.
Damien Georgeb042fd52022-12-09 12:28:54 +1100221 uint32_t devid;
222 int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
Damien Georgeb0785692025-04-02 12:47:48 +1100223 ret = mp_spiflash_detect(self, ret, devid);
224 if (ret != 0) {
225 // Could not read device id.
Damien Georgeb042fd52022-12-09 12:28:54 +1100226 mp_spiflash_release_bus(self);
227 return;
Damien George4e487002018-03-02 16:01:18 +1100228 }
229 #endif
230
231 if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
232 // Set QE bit
Damien Georgeb042fd52022-12-09 12:28:54 +1100233 uint32_t sr = 0, cr = 0;
234 int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
235 if (ret == 0) {
236 ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
237 }
238 uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
239 if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) {
Damien Georgecc34b082018-03-11 11:25:38 +1100240 data |= QSPI_QE_MASK << 8;
Damien George4e487002018-03-02 16:01:18 +1100241 mp_spiflash_write_cmd(self, CMD_WREN);
242 mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
243 mp_spiflash_wait_wip0(self);
244 }
245 }
246
247 mp_spiflash_release_bus(self);
Damien George784e0232017-01-24 16:56:03 +1100248}
249
Damien George8cde5fa2019-07-03 01:03:25 +1000250void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) {
251 if (value) {
252 mp_spiflash_acquire_bus(self);
253 }
254 mp_spiflash_deepsleep_internal(self, value);
255 if (!value) {
256 mp_spiflash_release_bus(self);
257 }
258}
259
Angus Grattondecf8e62024-02-27 15:32:29 +1100260static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100261 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100262 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100263 ret = mp_spiflash_write_cmd(self, CMD_WREN);
264 if (ret != 0) {
265 return ret;
266 }
Damien George784e0232017-01-24 16:56:03 +1100267
268 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100269 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100270 if (ret != 0) {
271 return ret;
272 }
273
274 // erase the sector
Damien George54f16942022-06-01 18:50:43 +1000275 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100276 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL);
277 if (ret != 0) {
278 return ret;
279 }
Damien George784e0232017-01-24 16:56:03 +1100280
281 // wait WIP=0
282 return mp_spiflash_wait_wip0(self);
283}
284
Angus Grattondecf8e62024-02-27 15:32:29 +1100285static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100286 int ret = 0;
Damien George784e0232017-01-24 16:56:03 +1100287 // enable writes
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100288 ret = mp_spiflash_write_cmd(self, CMD_WREN);
289 if (ret != 0) {
290 return ret;
291 }
Damien George784e0232017-01-24 16:56:03 +1100292
293 // wait WEL=1
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100294 ret = mp_spiflash_wait_wel1(self);
Damien George784e0232017-01-24 16:56:03 +1100295 if (ret != 0) {
296 return ret;
297 }
298
299 // write the page
Damien George54f16942022-06-01 18:50:43 +1000300 uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100301 ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL);
302 if (ret != 0) {
303 return ret;
304 }
Damien George784e0232017-01-24 16:56:03 +1100305
306 // wait WIP=0
307 return mp_spiflash_wait_wip0(self);
308}
309
Damien Georgecc5a9402018-06-07 15:36:27 +1000310/******************************************************************************/
Damien Georgeb78ca322018-06-07 15:39:46 +1000311// Interface functions that go direct to the SPI flash device
312
313int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
314 mp_spiflash_acquire_bus(self);
315 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien Georgec61e8592025-03-19 15:47:35 +1100316 mp_spiflash_notify_modified(self, addr, SECTOR_SIZE);
Damien Georgeb78ca322018-06-07 15:39:46 +1000317 mp_spiflash_release_bus(self);
318 return ret;
319}
320
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100321int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000322 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100323 return 0;
Damien Georgeb78ca322018-06-07 15:39:46 +1000324 }
Damien George62a674c2025-05-01 01:19:52 +1000325 const mp_spiflash_config_t *c = self->config;
326 if (c->bus_kind == MP_SPIFLASH_BUS_QSPI && c->bus.u_qspi.proto->direct_read != NULL) {
327 return c->bus.u_qspi.proto->direct_read(c->bus.u_qspi.data, addr, len, dest);
328 }
Damien Georgeb78ca322018-06-07 15:39:46 +1000329 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100330 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien Georgeb78ca322018-06-07 15:39:46 +1000331 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100332 return ret;
Damien Georgeb78ca322018-06-07 15:39:46 +1000333}
334
335int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien Georgec61e8592025-03-19 15:47:35 +1100336 uint32_t orig_addr = addr;
337 uint32_t orig_len = len;
Damien Georgeb78ca322018-06-07 15:39:46 +1000338 mp_spiflash_acquire_bus(self);
339 int ret = 0;
340 uint32_t offset = addr & (PAGE_SIZE - 1);
341 while (len) {
342 size_t rest = PAGE_SIZE - offset;
343 if (rest > len) {
344 rest = len;
345 }
346 ret = mp_spiflash_write_page(self, addr, rest, src);
347 if (ret != 0) {
348 break;
349 }
350 len -= rest;
351 addr += rest;
352 src += rest;
353 offset = 0;
354 }
Damien Georgec61e8592025-03-19 15:47:35 +1100355 mp_spiflash_notify_modified(self, orig_addr, orig_len);
Damien Georgeb78ca322018-06-07 15:39:46 +1000356 mp_spiflash_release_bus(self);
357 return ret;
358}
359
360/******************************************************************************/
Damien Georgecc5a9402018-06-07 15:36:27 +1000361// Interface functions that use the cache
Damien Georgec61e8592025-03-19 15:47:35 +1100362//
363// These functions do not call mp_spiflash_notify_modified(), so shouldn't be
364// used for memory-mapped flash (for example).
Damien Georgecc5a9402018-06-07 15:36:27 +1000365
Damien Georgee43a74a2020-12-17 16:59:54 +1100366#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
367
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100368int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
Damien George4e487002018-03-02 16:01:18 +1100369 if (len == 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100370 return 0;
Damien George4e487002018-03-02 16:01:18 +1100371 }
Damien George784e0232017-01-24 16:56:03 +1100372 mp_spiflash_acquire_bus(self);
Damien George86fe73b2018-06-07 14:09:10 +1000373 mp_spiflash_cache_t *cache = self->config->cache;
374 if (cache->user == self && cache->block != 0xffffffff) {
Damien George4e487002018-03-02 16:01:18 +1100375 uint32_t bis = addr / SECTOR_SIZE;
Damien Georgebdc875e2018-03-13 14:13:30 +1100376 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
Damien George86fe73b2018-06-07 14:09:10 +1000377 if (bis <= cache->block && cache->block <= bie) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100378 // Read straddles current buffer
379 size_t rest = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000380 if (bis < cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100381 // Read direct from flash for first part
Damien George86fe73b2018-06-07 14:09:10 +1000382 rest = cache->block * SECTOR_SIZE - addr;
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100383 int ret = mp_spiflash_read_data(self, addr, rest, dest);
384 if (ret != 0) {
385 mp_spiflash_release_bus(self);
386 return ret;
387 }
Damien George4e487002018-03-02 16:01:18 +1100388 len -= rest;
Damien George4e487002018-03-02 16:01:18 +1100389 dest += rest;
390 addr += rest;
391 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100392 uint32_t offset = addr & (SECTOR_SIZE - 1);
Damien George4e487002018-03-02 16:01:18 +1100393 rest = SECTOR_SIZE - offset;
394 if (rest > len) {
395 rest = len;
396 }
Damien George86fe73b2018-06-07 14:09:10 +1000397 memcpy(dest, &cache->buf[offset], rest);
Damien George4e487002018-03-02 16:01:18 +1100398 len -= rest;
Damien Georgebdc875e2018-03-13 14:13:30 +1100399 if (len == 0) {
Damien George4e487002018-03-02 16:01:18 +1100400 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100401 return 0;
Damien George4e487002018-03-02 16:01:18 +1100402 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100403 dest += rest;
404 addr += rest;
Damien George4e487002018-03-02 16:01:18 +1100405 }
Damien George4e487002018-03-02 16:01:18 +1100406 }
407 // Read rest direct from flash
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100408 int ret = mp_spiflash_read_data(self, addr, len, dest);
Damien George784e0232017-01-24 16:56:03 +1100409 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100410 return ret;
Damien George784e0232017-01-24 16:56:03 +1100411}
412
Angus Grattondecf8e62024-02-27 15:32:29 +1100413static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100414 #if USE_WR_DELAY
415 if (!(self->flags & 1)) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100416 return 0;
Damien George4e487002018-03-02 16:01:18 +1100417 }
Damien George784e0232017-01-24 16:56:03 +1100418
Damien George4e487002018-03-02 16:01:18 +1100419 self->flags &= ~1;
420
Damien George86fe73b2018-06-07 14:09:10 +1000421 mp_spiflash_cache_t *cache = self->config->cache;
422
Damien George4e487002018-03-02 16:01:18 +1100423 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000424 int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100425 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100426 return ret;
Damien George4e487002018-03-02 16:01:18 +1100427 }
428
429 // Write
430 for (int i = 0; i < 16; i += 1) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000431 uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
432 int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100433 if (ret != 0) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100434 return ret;
Damien George4e487002018-03-02 16:01:18 +1100435 }
436 }
437 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100438 return 0;
Damien George4e487002018-03-02 16:01:18 +1100439}
440
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100441int mp_spiflash_cache_flush(mp_spiflash_t *self) {
Damien George4e487002018-03-02 16:01:18 +1100442 mp_spiflash_acquire_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100443 int ret = mp_spiflash_cache_flush_internal(self);
Damien George4e487002018-03-02 16:01:18 +1100444 mp_spiflash_release_bus(self);
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100445 return ret;
Damien George4e487002018-03-02 16:01:18 +1100446}
447
Angus Grattondecf8e62024-02-27 15:32:29 +1100448static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100449 // Align to 4096 sector
Damien George784e0232017-01-24 16:56:03 +1100450 uint32_t offset = addr & 0xfff;
Damien George4e487002018-03-02 16:01:18 +1100451 uint32_t sec = addr >> 12;
452 addr = sec << 12;
Damien George784e0232017-01-24 16:56:03 +1100453
Damien George4e487002018-03-02 16:01:18 +1100454 // Restriction for now, so we don't need to erase multiple pages
Damien George86fe73b2018-06-07 14:09:10 +1000455 if (offset + len > SECTOR_SIZE) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000456 printf("mp_spiflash_cached_write_part: len is too large\n");
Damien George784e0232017-01-24 16:56:03 +1100457 return -MP_EIO;
458 }
459
Damien George86fe73b2018-06-07 14:09:10 +1000460 mp_spiflash_cache_t *cache = self->config->cache;
461
Damien George4e487002018-03-02 16:01:18 +1100462 // Acquire the sector buffer
Damien George86fe73b2018-06-07 14:09:10 +1000463 if (cache->user != self) {
464 if (cache->user != NULL) {
Damien Georgecc5a9402018-06-07 15:36:27 +1000465 mp_spiflash_cache_flush(cache->user);
Damien George4e487002018-03-02 16:01:18 +1100466 }
Damien George86fe73b2018-06-07 14:09:10 +1000467 cache->user = self;
468 cache->block = 0xffffffff;
Damien George784e0232017-01-24 16:56:03 +1100469 }
470
Damien George86fe73b2018-06-07 14:09:10 +1000471 if (cache->block != sec) {
Damien George4e487002018-03-02 16:01:18 +1100472 // Read sector
473 #if USE_WR_DELAY
Damien George86fe73b2018-06-07 14:09:10 +1000474 if (cache->block != 0xffffffff) {
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100475 int ret = mp_spiflash_cache_flush_internal(self);
476 if (ret != 0) {
477 return ret;
478 }
Damien George4e487002018-03-02 16:01:18 +1100479 }
480 #endif
Andrew Leech7ee5afe2021-03-05 10:15:29 +1100481 int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
482 if (ret != 0) {
483 return ret;
484 }
Damien George4e487002018-03-02 16:01:18 +1100485 }
Damien George784e0232017-01-24 16:56:03 +1100486
Damien George4e487002018-03-02 16:01:18 +1100487 #if USE_WR_DELAY
488
Damien George86fe73b2018-06-07 14:09:10 +1000489 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100490 // Just copy to buffer
Damien George86fe73b2018-06-07 14:09:10 +1000491 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100492 // And mark dirty
493 self->flags |= 1;
494
495 #else
496
497 uint32_t dirty = 0;
498 for (size_t i = 0; i < len; ++i) {
Damien George86fe73b2018-06-07 14:09:10 +1000499 if (cache->buf[offset + i] != src[i]) {
500 if (cache->buf[offset + i] != 0xff) {
Damien George4e487002018-03-02 16:01:18 +1100501 // Erase sector
Damien Georgeb78ca322018-06-07 15:39:46 +1000502 int ret = mp_spiflash_erase_block_internal(self, addr);
Damien George4e487002018-03-02 16:01:18 +1100503 if (ret != 0) {
504 return ret;
505 }
506 dirty = 0xffff;
507 break;
508 } else {
509 dirty |= (1 << ((offset + i) >> 8));
510 }
Damien George784e0232017-01-24 16:56:03 +1100511 }
512 }
513
Damien George86fe73b2018-06-07 14:09:10 +1000514 cache->block = sec;
Damien George4e487002018-03-02 16:01:18 +1100515 // Copy new block into buffer
Damien George86fe73b2018-06-07 14:09:10 +1000516 memcpy(cache->buf + offset, src, len);
Damien George4e487002018-03-02 16:01:18 +1100517
518 // Write sector in pages of 256 bytes
519 for (size_t i = 0; i < 16; ++i) {
520 if (dirty & (1 << i)) {
Damien Georgeb78ca322018-06-07 15:39:46 +1000521 int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
Damien George4e487002018-03-02 16:01:18 +1100522 if (ret != 0) {
523 return ret;
524 }
525 }
526 }
527
528 #endif
529
Damien George784e0232017-01-24 16:56:03 +1100530 return 0; // success
531}
Damien George4e487002018-03-02 16:01:18 +1100532
Damien Georgecc5a9402018-06-07 15:36:27 +1000533int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
Damien George4e487002018-03-02 16:01:18 +1100534 uint32_t bis = addr / SECTOR_SIZE;
535 uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
536
537 mp_spiflash_acquire_bus(self);
Damien Georgebdc875e2018-03-13 14:13:30 +1100538
Damien George86fe73b2018-06-07 14:09:10 +1000539 mp_spiflash_cache_t *cache = self->config->cache;
540 if (cache->user == self && bis <= cache->block && bie >= cache->block) {
Damien Georgebdc875e2018-03-13 14:13:30 +1100541 // Write straddles current buffer
542 uint32_t pre;
543 uint32_t offset;
Damien George86fe73b2018-06-07 14:09:10 +1000544 if (cache->block * SECTOR_SIZE >= addr) {
545 pre = cache->block * SECTOR_SIZE - addr;
Damien George4e487002018-03-02 16:01:18 +1100546 offset = 0;
547 } else {
548 pre = 0;
Damien George86fe73b2018-06-07 14:09:10 +1000549 offset = addr - cache->block * SECTOR_SIZE;
Damien George4e487002018-03-02 16:01:18 +1100550 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100551
552 // Write buffered part first
553 uint32_t len_in_buf = len - pre;
554 len = 0;
555 if (len_in_buf > SECTOR_SIZE - offset) {
556 len = len_in_buf - (SECTOR_SIZE - offset);
557 len_in_buf = SECTOR_SIZE - offset;
Damien George4e487002018-03-02 16:01:18 +1100558 }
Damien George86fe73b2018-06-07 14:09:10 +1000559 memcpy(&cache->buf[offset], &src[pre], len_in_buf);
Damien George4e487002018-03-02 16:01:18 +1100560 self->flags |= 1; // Mark dirty
Damien Georgebdc875e2018-03-13 14:13:30 +1100561
562 // Write part before buffer sector
Damien George4e487002018-03-02 16:01:18 +1100563 while (pre) {
564 int rest = pre & (SECTOR_SIZE - 1);
565 if (rest == 0) {
566 rest = SECTOR_SIZE;
567 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000568 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100569 if (ret != 0) {
570 mp_spiflash_release_bus(self);
571 return ret;
572 }
573 src += rest;
Damien George4e487002018-03-02 16:01:18 +1100574 addr += rest;
575 pre -= rest;
576 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100577 src += len_in_buf;
578 addr += len_in_buf;
579
580 // Fall through to write remaining part
Damien George4e487002018-03-02 16:01:18 +1100581 }
Damien Georgebdc875e2018-03-13 14:13:30 +1100582
583 uint32_t offset = addr & (SECTOR_SIZE - 1);
584 while (len) {
585 int rest = SECTOR_SIZE - offset;
586 if (rest > len) {
587 rest = len;
588 }
Damien Georgecc5a9402018-06-07 15:36:27 +1000589 int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
Damien Georgebdc875e2018-03-13 14:13:30 +1100590 if (ret != 0) {
591 mp_spiflash_release_bus(self);
592 return ret;
593 }
594 len -= rest;
595 addr += rest;
596 src += rest;
597 offset = 0;
598 }
599
Damien George4e487002018-03-02 16:01:18 +1100600 mp_spiflash_release_bus(self);
601 return 0;
602}
Damien Georgee43a74a2020-12-17 16:59:54 +1100603
604#endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE