blob: e504fdb4ae318b8fe8c5253ff738245a7a7a272b [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080032#include "drmP.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100036#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080037
38#include "drm_crtc_helper.h"
39
Zhenyu Wang32f9d652009-07-24 01:00:32 +080040#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
Jesse Barnes79e53942008-11-07 14:24:08 -080042bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080043static void intel_update_watermarks(struct drm_device *dev);
Jesse Barnes652c3932009-08-17 13:31:43 -070044static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
Jesse Barnes79e53942008-11-07 14:24:08 -080045
46typedef struct {
47 /* given values */
48 int n;
49 int m1, m2;
50 int p1, p2;
51 /* derived values */
52 int dot;
53 int vco;
54 int m;
55 int p;
56} intel_clock_t;
57
58typedef struct {
59 int min, max;
60} intel_range_t;
61
62typedef struct {
63 int dot_limit;
64 int p2_slow, p2_fast;
65} intel_p2_t;
66
67#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080068typedef struct intel_limit intel_limit_t;
69struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080070 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080072 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73 int, int, intel_clock_t *);
74};
Jesse Barnes79e53942008-11-07 14:24:08 -080075
76#define I8XX_DOT_MIN 25000
77#define I8XX_DOT_MAX 350000
78#define I8XX_VCO_MIN 930000
79#define I8XX_VCO_MAX 1400000
80#define I8XX_N_MIN 3
81#define I8XX_N_MAX 16
82#define I8XX_M_MIN 96
83#define I8XX_M_MAX 140
84#define I8XX_M1_MIN 18
85#define I8XX_M1_MAX 26
86#define I8XX_M2_MIN 6
87#define I8XX_M2_MAX 16
88#define I8XX_P_MIN 4
89#define I8XX_P_MAX 128
90#define I8XX_P1_MIN 2
91#define I8XX_P1_MAX 33
92#define I8XX_P1_LVDS_MIN 1
93#define I8XX_P1_LVDS_MAX 6
94#define I8XX_P2_SLOW 4
95#define I8XX_P2_FAST 2
96#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +080097#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -080098#define I8XX_P2_SLOW_LIMIT 165000
99
100#define I9XX_DOT_MIN 20000
101#define I9XX_DOT_MAX 400000
102#define I9XX_VCO_MIN 1400000
103#define I9XX_VCO_MAX 2800000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500104#define PINEVIEW_VCO_MIN 1700000
105#define PINEVIEW_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500106#define I9XX_N_MIN 1
107#define I9XX_N_MAX 6
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500108/* Pineview's Ncounter is a ring counter */
109#define PINEVIEW_N_MIN 3
110#define PINEVIEW_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800111#define I9XX_M_MIN 70
112#define I9XX_M_MAX 120
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500113#define PINEVIEW_M_MIN 2
114#define PINEVIEW_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800115#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500116#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800117#define I9XX_M2_MIN 5
118#define I9XX_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500119/* Pineview M1 is reserved, and must be 0 */
120#define PINEVIEW_M1_MIN 0
121#define PINEVIEW_M1_MAX 0
122#define PINEVIEW_M2_MIN 0
123#define PINEVIEW_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800124#define I9XX_P_SDVO_DAC_MIN 5
125#define I9XX_P_SDVO_DAC_MAX 80
126#define I9XX_P_LVDS_MIN 7
127#define I9XX_P_LVDS_MAX 98
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500128#define PINEVIEW_P_LVDS_MIN 7
129#define PINEVIEW_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800130#define I9XX_P1_MIN 1
131#define I9XX_P1_MAX 8
132#define I9XX_P2_SDVO_DAC_SLOW 10
133#define I9XX_P2_SDVO_DAC_FAST 5
134#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135#define I9XX_P2_LVDS_SLOW 14
136#define I9XX_P2_LVDS_FAST 7
137#define I9XX_P2_LVDS_SLOW_LIMIT 112000
138
Ma Ling044c7c42009-03-18 20:13:23 +0800139/*The parameter is for SDVO on G4x platform*/
140#define G4X_DOT_SDVO_MIN 25000
141#define G4X_DOT_SDVO_MAX 270000
142#define G4X_VCO_MIN 1750000
143#define G4X_VCO_MAX 3500000
144#define G4X_N_SDVO_MIN 1
145#define G4X_N_SDVO_MAX 4
146#define G4X_M_SDVO_MIN 104
147#define G4X_M_SDVO_MAX 138
148#define G4X_M1_SDVO_MIN 17
149#define G4X_M1_SDVO_MAX 23
150#define G4X_M2_SDVO_MIN 5
151#define G4X_M2_SDVO_MAX 11
152#define G4X_P_SDVO_MIN 10
153#define G4X_P_SDVO_MAX 30
154#define G4X_P1_SDVO_MIN 1
155#define G4X_P1_SDVO_MAX 3
156#define G4X_P2_SDVO_SLOW 10
157#define G4X_P2_SDVO_FAST 10
158#define G4X_P2_SDVO_LIMIT 270000
159
160/*The parameter is for HDMI_DAC on G4x platform*/
161#define G4X_DOT_HDMI_DAC_MIN 22000
162#define G4X_DOT_HDMI_DAC_MAX 400000
163#define G4X_N_HDMI_DAC_MIN 1
164#define G4X_N_HDMI_DAC_MAX 4
165#define G4X_M_HDMI_DAC_MIN 104
166#define G4X_M_HDMI_DAC_MAX 138
167#define G4X_M1_HDMI_DAC_MIN 16
168#define G4X_M1_HDMI_DAC_MAX 23
169#define G4X_M2_HDMI_DAC_MIN 5
170#define G4X_M2_HDMI_DAC_MAX 11
171#define G4X_P_HDMI_DAC_MIN 5
172#define G4X_P_HDMI_DAC_MAX 80
173#define G4X_P1_HDMI_DAC_MIN 1
174#define G4X_P1_HDMI_DAC_MAX 8
175#define G4X_P2_HDMI_DAC_SLOW 10
176#define G4X_P2_HDMI_DAC_FAST 5
177#define G4X_P2_HDMI_DAC_LIMIT 165000
178
179/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197
198/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700217/*The parameter is for DISPLAY PORT on G4x platform*/
218#define G4X_DOT_DISPLAY_PORT_MIN 161670
219#define G4X_DOT_DISPLAY_PORT_MAX 227000
220#define G4X_N_DISPLAY_PORT_MIN 1
221#define G4X_N_DISPLAY_PORT_MAX 2
222#define G4X_M_DISPLAY_PORT_MIN 97
223#define G4X_M_DISPLAY_PORT_MAX 108
224#define G4X_M1_DISPLAY_PORT_MIN 0x10
225#define G4X_M1_DISPLAY_PORT_MAX 0x12
226#define G4X_M2_DISPLAY_PORT_MIN 0x05
227#define G4X_M2_DISPLAY_PORT_MAX 0x06
228#define G4X_P_DISPLAY_PORT_MIN 10
229#define G4X_P_DISPLAY_PORT_MAX 20
230#define G4X_P1_DISPLAY_PORT_MIN 1
231#define G4X_P1_DISPLAY_PORT_MAX 2
232#define G4X_P2_DISPLAY_PORT_SLOW 10
233#define G4X_P2_DISPLAY_PORT_FAST 10
234#define G4X_P2_DISPLAY_PORT_LIMIT 0
235
Eric Anholtbad720f2009-10-22 16:11:14 -0700236/* Ironlake / Sandybridge */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800237/* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
239 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500240#define IRONLAKE_DOT_MIN 25000
241#define IRONLAKE_DOT_MAX 350000
242#define IRONLAKE_VCO_MIN 1760000
243#define IRONLAKE_VCO_MAX 3510000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500244#define IRONLAKE_M1_MIN 12
Zhao Yakuia59e3852010-01-06 22:05:57 +0800245#define IRONLAKE_M1_MAX 22
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500246#define IRONLAKE_M2_MIN 5
247#define IRONLAKE_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500248#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800249
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800250/* We have parameter ranges for different type of outputs. */
251
252/* DAC & HDMI Refclk 120Mhz */
253#define IRONLAKE_DAC_N_MIN 1
254#define IRONLAKE_DAC_N_MAX 5
255#define IRONLAKE_DAC_M_MIN 79
256#define IRONLAKE_DAC_M_MAX 127
257#define IRONLAKE_DAC_P_MIN 5
258#define IRONLAKE_DAC_P_MAX 80
259#define IRONLAKE_DAC_P1_MIN 1
260#define IRONLAKE_DAC_P1_MAX 8
261#define IRONLAKE_DAC_P2_SLOW 10
262#define IRONLAKE_DAC_P2_FAST 5
263
264/* LVDS single-channel 120Mhz refclk */
265#define IRONLAKE_LVDS_S_N_MIN 1
266#define IRONLAKE_LVDS_S_N_MAX 3
267#define IRONLAKE_LVDS_S_M_MIN 79
268#define IRONLAKE_LVDS_S_M_MAX 118
269#define IRONLAKE_LVDS_S_P_MIN 28
270#define IRONLAKE_LVDS_S_P_MAX 112
271#define IRONLAKE_LVDS_S_P1_MIN 2
272#define IRONLAKE_LVDS_S_P1_MAX 8
273#define IRONLAKE_LVDS_S_P2_SLOW 14
274#define IRONLAKE_LVDS_S_P2_FAST 14
275
276/* LVDS dual-channel 120Mhz refclk */
277#define IRONLAKE_LVDS_D_N_MIN 1
278#define IRONLAKE_LVDS_D_N_MAX 3
279#define IRONLAKE_LVDS_D_M_MIN 79
280#define IRONLAKE_LVDS_D_M_MAX 127
281#define IRONLAKE_LVDS_D_P_MIN 14
282#define IRONLAKE_LVDS_D_P_MAX 56
283#define IRONLAKE_LVDS_D_P1_MIN 2
284#define IRONLAKE_LVDS_D_P1_MAX 8
285#define IRONLAKE_LVDS_D_P2_SLOW 7
286#define IRONLAKE_LVDS_D_P2_FAST 7
287
288/* LVDS single-channel 100Mhz refclk */
289#define IRONLAKE_LVDS_S_SSC_N_MIN 1
290#define IRONLAKE_LVDS_S_SSC_N_MAX 2
291#define IRONLAKE_LVDS_S_SSC_M_MIN 79
292#define IRONLAKE_LVDS_S_SSC_M_MAX 126
293#define IRONLAKE_LVDS_S_SSC_P_MIN 28
294#define IRONLAKE_LVDS_S_SSC_P_MAX 112
295#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299
300/* LVDS dual-channel 100Mhz refclk */
301#define IRONLAKE_LVDS_D_SSC_N_MIN 1
302#define IRONLAKE_LVDS_D_SSC_N_MAX 3
303#define IRONLAKE_LVDS_D_SSC_M_MIN 79
304#define IRONLAKE_LVDS_D_SSC_M_MAX 126
305#define IRONLAKE_LVDS_D_SSC_P_MIN 14
306#define IRONLAKE_LVDS_D_SSC_P_MAX 42
307#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
311
312/* DisplayPort */
313#define IRONLAKE_DP_N_MIN 1
314#define IRONLAKE_DP_N_MAX 2
315#define IRONLAKE_DP_M_MIN 81
316#define IRONLAKE_DP_M_MAX 90
317#define IRONLAKE_DP_P_MIN 10
318#define IRONLAKE_DP_P_MAX 20
319#define IRONLAKE_DP_P2_FAST 10
320#define IRONLAKE_DP_P2_SLOW 10
321#define IRONLAKE_DP_P2_LIMIT 0
322#define IRONLAKE_DP_P1_MIN 1
323#define IRONLAKE_DP_P1_MAX 2
Zhao Yakui45476682009-12-31 16:06:04 +0800324
Ma Lingd4906092009-03-18 20:13:27 +0800325static bool
326intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327 int target, int refclk, intel_clock_t *best_clock);
328static bool
329intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800331
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700332static bool
333intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800335static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500336intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700338
Keith Packarde4b36692009-06-05 19:22:17 -0700339static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
341 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
342 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
343 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
344 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
345 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
346 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
347 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800350 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700351};
352
353static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800354 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
355 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
356 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
357 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
358 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
359 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
360 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
361 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800364 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700365};
366
367static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800368 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
369 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
370 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
371 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
372 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
373 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
374 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
375 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800378 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700379};
380
381static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800382 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
383 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
384 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
385 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
386 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
387 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
388 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
389 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
392 */
393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800395 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700396};
397
Ma Ling044c7c42009-03-18 20:13:23 +0800398 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700399static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800400 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
401 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
402 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
403 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
404 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
405 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
406 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
407 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
408 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
409 .p2_slow = G4X_P2_SDVO_SLOW,
410 .p2_fast = G4X_P2_SDVO_FAST
411 },
Ma Lingd4906092009-03-18 20:13:27 +0800412 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700413};
414
415static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800416 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
419 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
420 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
421 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
422 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
423 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
424 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426 .p2_fast = G4X_P2_HDMI_DAC_FAST
427 },
Ma Lingd4906092009-03-18 20:13:27 +0800428 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700429};
430
431static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800432 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX },
436 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 },
Ma Lingd4906092009-03-18 20:13:27 +0800452 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700453};
454
455static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800456 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458 .vco = { .min = G4X_VCO_MIN,
459 .max = G4X_VCO_MAX },
460 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 },
Ma Lingd4906092009-03-18 20:13:27 +0800476 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700477};
478
479static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700480 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481 .max = G4X_DOT_DISPLAY_PORT_MAX },
482 .vco = { .min = G4X_VCO_MIN,
483 .max = G4X_VCO_MAX},
484 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
485 .max = G4X_N_DISPLAY_PORT_MAX },
486 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
487 .max = G4X_M_DISPLAY_PORT_MAX },
488 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
489 .max = G4X_M1_DISPLAY_PORT_MAX },
490 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
491 .max = G4X_M2_DISPLAY_PORT_MAX },
492 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
493 .max = G4X_P_DISPLAY_PORT_MAX },
494 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
495 .max = G4X_P1_DISPLAY_PORT_MAX},
496 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700500};
501
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500502static const intel_limit_t intel_limits_pineview_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800513 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700514};
515
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500516static const intel_limit_t intel_limits_pineview_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500525 /* Pineview only supports single-channel mode. */
Shaohua Li21778322009-02-23 15:19:16 +0800526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800528 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700529};
530
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800531static const intel_limit_t intel_limits_ironlake_dac = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
542 .p2_fast = IRONLAKE_DAC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800543 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700544};
545
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800546static const intel_limit_t intel_limits_ironlake_single_lvds = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
559};
560
561static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
574};
575
576static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
589};
590
591static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800603 .find_pll = intel_g4x_find_best_PLL,
604};
605
606static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
Zhao Yakui45476682009-12-31 16:06:04 +0800615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800626 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800627};
628
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500629static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800630{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800633 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800634 int refclk = 120;
635
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638 refclk = 100;
639
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
643 if (refclk == 100)
644 limit = &intel_limits_ironlake_dual_lvds_100m;
645 else
646 limit = &intel_limits_ironlake_dual_lvds;
647 } else {
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_single_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_single_lvds;
652 }
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800654 HAS_eDP)
655 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800656 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800657 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800658
659 return limit;
660}
661
Ma Ling044c7c42009-03-18 20:13:23 +0800662static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663{
664 struct drm_device *dev = crtc->dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 const intel_limit_t *limit;
667
668 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670 LVDS_CLKB_POWER_UP)
671 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700672 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800673 else
674 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700675 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800676 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700678 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800679 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700680 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700681 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700682 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800683 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700684 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800685
686 return limit;
687}
688
Jesse Barnes79e53942008-11-07 14:24:08 -0800689static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690{
691 struct drm_device *dev = crtc->dev;
692 const intel_limit_t *limit;
693
Eric Anholtbad720f2009-10-22 16:11:14 -0700694 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500695 limit = intel_ironlake_limit(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800696 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800697 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700700 limit = &intel_limits_i9xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800701 else
Keith Packarde4b36692009-06-05 19:22:17 -0700702 limit = &intel_limits_i9xx_sdvo;
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500703 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500705 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800706 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500707 limit = &intel_limits_pineview_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800708 } else {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700710 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800711 else
Keith Packarde4b36692009-06-05 19:22:17 -0700712 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800713 }
714 return limit;
715}
716
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500717/* m1 is reserved as 0 in Pineview, n is a ring counter */
718static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800719{
Shaohua Li21778322009-02-23 15:19:16 +0800720 clock->m = clock->m2 + 2;
721 clock->p = clock->p1 * clock->p2;
722 clock->vco = refclk * clock->m / clock->n;
723 clock->dot = clock->vco / clock->p;
724}
725
726static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500728 if (IS_PINEVIEW(dev)) {
729 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800730 return;
731 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733 clock->p = clock->p1 * clock->p2;
734 clock->vco = refclk * clock->m / (clock->n + 2);
735 clock->dot = clock->vco / clock->p;
736}
737
Jesse Barnes79e53942008-11-07 14:24:08 -0800738/**
739 * Returns whether any output on the specified pipe is of the specified type
740 */
741bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742{
743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +0800745 struct drm_encoder *l_entry;
Jesse Barnes79e53942008-11-07 14:24:08 -0800746
Zhenyu Wangc5e4df32010-03-30 14:39:27 +0800747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry && l_entry->crtc == crtc) {
749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
Eric Anholt21d40d32010-03-25 11:11:14 -0700750 if (intel_encoder->type == type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800751 return true;
752 }
753 }
754 return false;
755}
756
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800757#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800758/**
759 * Returns whether the given set of divisors are valid for a given refclk with
760 * the given connectors.
761 */
762
763static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
764{
765 const intel_limit_t *limit = intel_limit (crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800766 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800767
768 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
769 INTELPllInvalid ("p1 out of range\n");
770 if (clock->p < limit->p.min || limit->p.max < clock->p)
771 INTELPllInvalid ("p out of range\n");
772 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
773 INTELPllInvalid ("m2 out of range\n");
774 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
775 INTELPllInvalid ("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500776 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800777 INTELPllInvalid ("m1 <= m2\n");
778 if (clock->m < limit->m.min || limit->m.max < clock->m)
779 INTELPllInvalid ("m out of range\n");
780 if (clock->n < limit->n.min || limit->n.max < clock->n)
781 INTELPllInvalid ("n out of range\n");
782 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
783 INTELPllInvalid ("vco out of range\n");
784 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
785 * connector, etc., rather than just a single range.
786 */
787 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
788 INTELPllInvalid ("dot out of range\n");
789
790 return true;
791}
792
Ma Lingd4906092009-03-18 20:13:27 +0800793static bool
794intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
795 int target, int refclk, intel_clock_t *best_clock)
796
Jesse Barnes79e53942008-11-07 14:24:08 -0800797{
798 struct drm_device *dev = crtc->dev;
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800801 int err = target;
802
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800804 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800805 /*
806 * For LVDS, if the panel is on, just rely on its current
807 * settings for dual-channel. We haven't figured out how to
808 * reliably set up different single/dual channel state, if we
809 * even can.
810 */
811 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
812 LVDS_CLKB_POWER_UP)
813 clock.p2 = limit->p2.p2_fast;
814 else
815 clock.p2 = limit->p2.p2_slow;
816 } else {
817 if (target < limit->p2.dot_limit)
818 clock.p2 = limit->p2.p2_slow;
819 else
820 clock.p2 = limit->p2.p2_fast;
821 }
822
823 memset (best_clock, 0, sizeof (*best_clock));
824
Zhao Yakui42158662009-11-20 11:24:18 +0800825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500829 /* m1 is always 0 in Pineview */
830 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800831 break;
832 for (clock.n = limit->n.min;
833 clock.n <= limit->n.max; clock.n++) {
834 for (clock.p1 = limit->p1.min;
835 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800836 int this_err;
837
Shaohua Li21778322009-02-23 15:19:16 +0800838 intel_clock(dev, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800839
840 if (!intel_PLL_is_valid(crtc, &clock))
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
Ma Lingd4906092009-03-18 20:13:27 +0800856static bool
857intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
858 int target, int refclk, intel_clock_t *best_clock)
859{
860 struct drm_device *dev = crtc->dev;
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 intel_clock_t clock;
863 int max_n;
864 bool found;
865 /* approximately equals target * 0.00488 */
866 int err_most = (target >> 8) + (target >> 10);
867 found = false;
868
869 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800870 int lvds_reg;
871
Eric Anholtc619eed2010-01-28 16:45:52 -0800872 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800873 lvds_reg = PCH_LVDS;
874 else
875 lvds_reg = LVDS;
876 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800877 LVDS_CLKB_POWER_UP)
878 clock.p2 = limit->p2.p2_fast;
879 else
880 clock.p2 = limit->p2.p2_slow;
881 } else {
882 if (target < limit->p2.dot_limit)
883 clock.p2 = limit->p2.p2_slow;
884 else
885 clock.p2 = limit->p2.p2_fast;
886 }
887
888 memset(best_clock, 0, sizeof(*best_clock));
889 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200890 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800891 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200892 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800893 for (clock.m1 = limit->m1.max;
894 clock.m1 >= limit->m1.min; clock.m1--) {
895 for (clock.m2 = limit->m2.max;
896 clock.m2 >= limit->m2.min; clock.m2--) {
897 for (clock.p1 = limit->p1.max;
898 clock.p1 >= limit->p1.min; clock.p1--) {
899 int this_err;
900
Shaohua Li21778322009-02-23 15:19:16 +0800901 intel_clock(dev, refclk, &clock);
Ma Lingd4906092009-03-18 20:13:27 +0800902 if (!intel_PLL_is_valid(crtc, &clock))
903 continue;
904 this_err = abs(clock.dot - target) ;
905 if (this_err < err_most) {
906 *best_clock = clock;
907 err_most = this_err;
908 max_n = clock.n;
909 found = true;
910 }
911 }
912 }
913 }
914 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800915 return found;
916}
Ma Lingd4906092009-03-18 20:13:27 +0800917
Zhenyu Wang2c072452009-06-05 15:38:42 +0800918static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500919intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
920 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800921{
922 struct drm_device *dev = crtc->dev;
923 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800924
925 /* return directly when it is eDP */
926 if (HAS_eDP)
927 return true;
928
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800929 if (target < 200000) {
930 clock.n = 1;
931 clock.p1 = 2;
932 clock.p2 = 10;
933 clock.m1 = 12;
934 clock.m2 = 9;
935 } else {
936 clock.n = 2;
937 clock.p1 = 1;
938 clock.p2 = 10;
939 clock.m1 = 14;
940 clock.m2 = 8;
941 }
942 intel_clock(dev, refclk, &clock);
943 memcpy(best_clock, &clock, sizeof(intel_clock_t));
944 return true;
945}
946
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700947/* DisplayPort has only two frequencies, 162MHz and 270MHz */
948static bool
949intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
950 int target, int refclk, intel_clock_t *best_clock)
951{
952 intel_clock_t clock;
953 if (target < 200000) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700954 clock.p1 = 2;
955 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700956 clock.n = 2;
957 clock.m1 = 23;
958 clock.m2 = 8;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700959 } else {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700960 clock.p1 = 1;
961 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700962 clock.n = 1;
963 clock.m1 = 14;
964 clock.m2 = 2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700965 }
Keith Packardb3d25492009-06-24 23:09:15 -0700966 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
967 clock.p = (clock.p1 * clock.p2);
968 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
Jesse Barnesfe798b92009-10-20 07:55:28 +0900969 clock.vco = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700970 memcpy(best_clock, &clock, sizeof(intel_clock_t));
971 return true;
972}
973
Jesse Barnes79e53942008-11-07 14:24:08 -0800974void
975intel_wait_for_vblank(struct drm_device *dev)
976{
977 /* Wait for 20ms, i.e. one cycle at 50hz. */
Shaohua Li311089d2009-11-26 14:22:41 +0800978 msleep(20);
Jesse Barnes79e53942008-11-07 14:24:08 -0800979}
980
Jesse Barnes80824002009-09-10 15:28:06 -0700981/* Parameters have changed, update FBC info */
982static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
983{
984 struct drm_device *dev = crtc->dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 struct drm_framebuffer *fb = crtc->fb;
987 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +0100988 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes80824002009-09-10 15:28:06 -0700989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990 int plane, i;
991 u32 fbc_ctl, fbc_ctl2;
992
993 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
994
995 if (fb->pitch < dev_priv->cfb_pitch)
996 dev_priv->cfb_pitch = fb->pitch;
997
998 /* FBC_CTL wants 64B units */
999 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1000 dev_priv->cfb_fence = obj_priv->fence_reg;
1001 dev_priv->cfb_plane = intel_crtc->plane;
1002 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1003
1004 /* Clear old tags */
1005 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1006 I915_WRITE(FBC_TAG + (i * 4), 0);
1007
1008 /* Set it up... */
1009 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1010 if (obj_priv->tiling_mode != I915_TILING_NONE)
1011 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1012 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1013 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1014
1015 /* enable it... */
1016 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001017 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001018 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Jesse Barnes80824002009-09-10 15:28:06 -07001019 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1020 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1021 if (obj_priv->tiling_mode != I915_TILING_NONE)
1022 fbc_ctl |= dev_priv->cfb_fence;
1023 I915_WRITE(FBC_CONTROL, fbc_ctl);
1024
Zhao Yakui28c97732009-10-09 11:39:41 +08001025 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
Jesse Barnes80824002009-09-10 15:28:06 -07001026 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1027}
1028
1029void i8xx_disable_fbc(struct drm_device *dev)
1030{
1031 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9517a922010-05-21 09:40:45 -07001032 unsigned long timeout = jiffies + msecs_to_jiffies(1);
Jesse Barnes80824002009-09-10 15:28:06 -07001033 u32 fbc_ctl;
1034
Jesse Barnesc1a1cdc2009-09-16 15:05:00 -07001035 if (!I915_HAS_FBC(dev))
1036 return;
1037
Jesse Barnes9517a922010-05-21 09:40:45 -07001038 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1039 return; /* Already off, just return */
1040
Jesse Barnes80824002009-09-10 15:28:06 -07001041 /* Disable compression */
1042 fbc_ctl = I915_READ(FBC_CONTROL);
1043 fbc_ctl &= ~FBC_CTL_EN;
1044 I915_WRITE(FBC_CONTROL, fbc_ctl);
1045
1046 /* Wait for compressing bit to clear */
Jesse Barnes9517a922010-05-21 09:40:45 -07001047 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1048 if (time_after(jiffies, timeout)) {
1049 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1050 break;
1051 }
1052 ; /* do nothing */
1053 }
Jesse Barnes80824002009-09-10 15:28:06 -07001054
1055 intel_wait_for_vblank(dev);
1056
Zhao Yakui28c97732009-10-09 11:39:41 +08001057 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001058}
1059
Adam Jacksonee5382a2010-04-23 11:17:39 -04001060static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001061{
Jesse Barnes80824002009-09-10 15:28:06 -07001062 struct drm_i915_private *dev_priv = dev->dev_private;
1063
1064 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1065}
1066
Jesse Barnes74dff282009-09-14 15:39:40 -07001067static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1068{
1069 struct drm_device *dev = crtc->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 struct drm_framebuffer *fb = crtc->fb;
1072 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001073 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes74dff282009-09-14 15:39:40 -07001074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1075 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1076 DPFC_CTL_PLANEB);
1077 unsigned long stall_watermark = 200;
1078 u32 dpfc_ctl;
1079
1080 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1081 dev_priv->cfb_fence = obj_priv->fence_reg;
1082 dev_priv->cfb_plane = intel_crtc->plane;
1083
1084 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1085 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1086 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1087 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1088 } else {
1089 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1090 }
1091
1092 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1093 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1094 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1095 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1096 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1097
1098 /* enable it... */
1099 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1100
Zhao Yakui28c97732009-10-09 11:39:41 +08001101 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001102}
1103
1104void g4x_disable_fbc(struct drm_device *dev)
1105{
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 u32 dpfc_ctl;
1108
1109 /* Disable compression */
1110 dpfc_ctl = I915_READ(DPFC_CONTROL);
1111 dpfc_ctl &= ~DPFC_CTL_EN;
1112 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1113 intel_wait_for_vblank(dev);
1114
Zhao Yakui28c97732009-10-09 11:39:41 +08001115 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes74dff282009-09-14 15:39:40 -07001116}
1117
Adam Jacksonee5382a2010-04-23 11:17:39 -04001118static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001119{
Jesse Barnes74dff282009-09-14 15:39:40 -07001120 struct drm_i915_private *dev_priv = dev->dev_private;
1121
1122 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1123}
1124
Adam Jacksonee5382a2010-04-23 11:17:39 -04001125bool intel_fbc_enabled(struct drm_device *dev)
1126{
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 if (!dev_priv->display.fbc_enabled)
1130 return false;
1131
1132 return dev_priv->display.fbc_enabled(dev);
1133}
1134
1135void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1136{
1137 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1138
1139 if (!dev_priv->display.enable_fbc)
1140 return;
1141
1142 dev_priv->display.enable_fbc(crtc, interval);
1143}
1144
1145void intel_disable_fbc(struct drm_device *dev)
1146{
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149 if (!dev_priv->display.disable_fbc)
1150 return;
1151
1152 dev_priv->display.disable_fbc(dev);
1153}
1154
Jesse Barnes80824002009-09-10 15:28:06 -07001155/**
1156 * intel_update_fbc - enable/disable FBC as needed
1157 * @crtc: CRTC to point the compressor at
1158 * @mode: mode in use
1159 *
1160 * Set up the framebuffer compression hardware at mode set time. We
1161 * enable it if possible:
1162 * - plane A only (on pre-965)
1163 * - no pixel mulitply/line duplication
1164 * - no alpha buffer discard
1165 * - no dual wide
1166 * - framebuffer <= 2048 in width, 1536 in height
1167 *
1168 * We can't assume that any compression will take place (worst case),
1169 * so the compressed buffer has to be the same size as the uncompressed
1170 * one. It also must reside (along with the line length buffer) in
1171 * stolen memory.
1172 *
1173 * We need to enable/disable FBC on a global basis.
1174 */
1175static void intel_update_fbc(struct drm_crtc *crtc,
1176 struct drm_display_mode *mode)
1177{
1178 struct drm_device *dev = crtc->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct drm_framebuffer *fb = crtc->fb;
1181 struct intel_framebuffer *intel_fb;
1182 struct drm_i915_gem_object *obj_priv;
1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1184 int plane = intel_crtc->plane;
1185
1186 if (!i915_powersave)
1187 return;
1188
Adam Jacksonee5382a2010-04-23 11:17:39 -04001189 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001190 return;
1191
Jesse Barnes80824002009-09-10 15:28:06 -07001192 if (!crtc->fb)
1193 return;
1194
1195 intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001196 obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes80824002009-09-10 15:28:06 -07001197
1198 /*
1199 * If FBC is already on, we just have to verify that we can
1200 * keep it that way...
1201 * Need to disable if:
1202 * - changing FBC params (stride, fence, mode)
1203 * - new fb is too large to fit in compressed buffer
1204 * - going to an unsupported config (interlace, pixel multiply, etc.)
1205 */
1206 if (intel_fb->obj->size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001207 DRM_DEBUG_KMS("framebuffer too large, disabling "
1208 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001209 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001210 goto out_disable;
1211 }
1212 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1213 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001214 DRM_DEBUG_KMS("mode incompatible with compression, "
1215 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001216 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001217 goto out_disable;
1218 }
1219 if ((mode->hdisplay > 2048) ||
1220 (mode->vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001221 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001222 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001223 goto out_disable;
1224 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001225 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001226 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001227 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001228 goto out_disable;
1229 }
1230 if (obj_priv->tiling_mode != I915_TILING_X) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001231 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001232 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001233 goto out_disable;
1234 }
1235
Adam Jacksonee5382a2010-04-23 11:17:39 -04001236 if (intel_fbc_enabled(dev)) {
Jesse Barnes80824002009-09-10 15:28:06 -07001237 /* We can re-enable it in this case, but need to update pitch */
Adam Jacksonee5382a2010-04-23 11:17:39 -04001238 if ((fb->pitch > dev_priv->cfb_pitch) ||
1239 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1240 (plane != dev_priv->cfb_plane))
1241 intel_disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001242 }
1243
Adam Jacksonee5382a2010-04-23 11:17:39 -04001244 /* Now try to turn it back on if possible */
1245 if (!intel_fbc_enabled(dev))
1246 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001247
1248 return;
1249
1250out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001251 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001252 if (intel_fbc_enabled(dev)) {
1253 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001254 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001255 }
Jesse Barnes80824002009-09-10 15:28:06 -07001256}
1257
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001258static int
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001259intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1260{
Daniel Vetter23010e42010-03-08 13:35:02 +01001261 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001262 u32 alignment;
1263 int ret;
1264
1265 switch (obj_priv->tiling_mode) {
1266 case I915_TILING_NONE:
1267 alignment = 64 * 1024;
1268 break;
1269 case I915_TILING_X:
1270 /* pin() will align the object as required by fence */
1271 alignment = 0;
1272 break;
1273 case I915_TILING_Y:
1274 /* FIXME: Is this true? */
1275 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1276 return -EINVAL;
1277 default:
1278 BUG();
1279 }
1280
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001281 ret = i915_gem_object_pin(obj, alignment);
1282 if (ret != 0)
1283 return ret;
1284
1285 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1286 * fence, whereas 965+ only requires a fence if using
1287 * framebuffer compression. For simplicity, we always install
1288 * a fence as the cost is not that onerous.
1289 */
1290 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1291 obj_priv->tiling_mode != I915_TILING_NONE) {
1292 ret = i915_gem_object_get_fence_reg(obj);
1293 if (ret != 0) {
1294 i915_gem_object_unpin(obj);
1295 return ret;
1296 }
1297 }
1298
1299 return 0;
1300}
1301
1302static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001303intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1304 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08001305{
1306 struct drm_device *dev = crtc->dev;
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 struct drm_i915_master_private *master_priv;
1309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1310 struct intel_framebuffer *intel_fb;
1311 struct drm_i915_gem_object *obj_priv;
1312 struct drm_gem_object *obj;
1313 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07001314 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08001315 unsigned long Start, Offset;
Jesse Barnes80824002009-09-10 15:28:06 -07001316 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1317 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1318 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1319 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1320 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001321 u32 dspcntr;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001322 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001323
1324 /* no fb bound */
1325 if (!crtc->fb) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001326 DRM_DEBUG_KMS("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001327 return 0;
1328 }
1329
Jesse Barnes80824002009-09-10 15:28:06 -07001330 switch (plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001331 case 0:
1332 case 1:
1333 break;
1334 default:
Jesse Barnes80824002009-09-10 15:28:06 -07001335 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001336 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001337 }
1338
1339 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08001340 obj = intel_fb->obj;
Daniel Vetter23010e42010-03-08 13:35:02 +01001341 obj_priv = to_intel_bo(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08001342
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001343 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001344 ret = intel_pin_and_fence_fb_obj(dev, obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001345 if (ret != 0) {
1346 mutex_unlock(&dev->struct_mutex);
1347 return ret;
1348 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001349
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08001350 ret = i915_gem_object_set_to_display_plane(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001351 if (ret != 0) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001352 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001353 mutex_unlock(&dev->struct_mutex);
1354 return ret;
1355 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001356
1357 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -08001358 /* Mask out pixel format bits in case we change it */
1359 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -08001360 switch (crtc->fb->bits_per_pixel) {
1361 case 8:
1362 dspcntr |= DISPPLANE_8BPP;
1363 break;
1364 case 16:
1365 if (crtc->fb->depth == 15)
1366 dspcntr |= DISPPLANE_15_16BPP;
1367 else
1368 dspcntr |= DISPPLANE_16BPP;
1369 break;
1370 case 24:
1371 case 32:
Kristian Høgsberga4f45cf2009-10-19 14:35:30 -04001372 if (crtc->fb->depth == 30)
1373 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1374 else
1375 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
Jesse Barnes79e53942008-11-07 14:24:08 -08001376 break;
1377 default:
1378 DRM_ERROR("Unknown color depth\n");
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001379 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001380 mutex_unlock(&dev->struct_mutex);
1381 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001382 }
Jesse Barnesf5448472009-04-14 14:17:47 -07001383 if (IS_I965G(dev)) {
1384 if (obj_priv->tiling_mode != I915_TILING_NONE)
1385 dspcntr |= DISPPLANE_TILED;
1386 else
1387 dspcntr &= ~DISPPLANE_TILED;
1388 }
1389
Eric Anholtbad720f2009-10-22 16:11:14 -07001390 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang553bd142009-09-02 10:57:52 +08001391 /* must disable */
1392 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1393
Jesse Barnes79e53942008-11-07 14:24:08 -08001394 I915_WRITE(dspcntr_reg, dspcntr);
1395
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001396 Start = obj_priv->gtt_offset;
1397 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1398
Zhao Yakui28c97732009-10-09 11:39:41 +08001399 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001400 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -08001401 if (IS_I965G(dev)) {
1402 I915_WRITE(dspbase, Offset);
1403 I915_READ(dspbase);
1404 I915_WRITE(dspsurf, Start);
1405 I915_READ(dspsurf);
Jesse Barnesf5448472009-04-14 14:17:47 -07001406 I915_WRITE(dsptileoff, (y << 16) | x);
Jesse Barnes79e53942008-11-07 14:24:08 -08001407 } else {
1408 I915_WRITE(dspbase, Start + Offset);
1409 I915_READ(dspbase);
1410 }
1411
Jesse Barnes74dff282009-09-14 15:39:40 -07001412 if ((IS_I965G(dev) || plane == 0))
Jesse Barnesedb81952009-09-17 17:06:47 -07001413 intel_update_fbc(crtc, &crtc->mode);
1414
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001415 intel_wait_for_vblank(dev);
1416
1417 if (old_fb) {
1418 intel_fb = to_intel_framebuffer(old_fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001419 obj_priv = to_intel_bo(intel_fb->obj);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001420 i915_gem_object_unpin(intel_fb->obj);
1421 }
Jesse Barnes652c3932009-08-17 13:31:43 -07001422 intel_increase_pllclock(crtc, true);
1423
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001424 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001425
1426 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001427 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001428
1429 master_priv = dev->primary->master->driver_priv;
1430 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001431 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001432
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001433 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08001434 master_priv->sarea_priv->pipeB_x = x;
1435 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001436 } else {
1437 master_priv->sarea_priv->pipeA_x = x;
1438 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08001439 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001440
1441 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001442}
1443
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001444/* Disable the VGA plane that we never use */
1445static void i915_disable_vga (struct drm_device *dev)
1446{
1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 u8 sr1;
1449 u32 vga_reg;
1450
Eric Anholtbad720f2009-10-22 16:11:14 -07001451 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001452 vga_reg = CPU_VGACNTRL;
1453 else
1454 vga_reg = VGACNTRL;
1455
1456 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1457 return;
1458
1459 I915_WRITE8(VGA_SR_INDEX, 1);
1460 sr1 = I915_READ8(VGA_SR_DATA);
1461 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1462 udelay(100);
1463
1464 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1465}
1466
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001467static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001468{
1469 struct drm_device *dev = crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 u32 dpa_ctl;
1472
Zhao Yakui28c97732009-10-09 11:39:41 +08001473 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001474 dpa_ctl = I915_READ(DP_A);
1475 dpa_ctl &= ~DP_PLL_ENABLE;
1476 I915_WRITE(DP_A, dpa_ctl);
1477}
1478
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001479static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001480{
1481 struct drm_device *dev = crtc->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 u32 dpa_ctl;
1484
1485 dpa_ctl = I915_READ(DP_A);
1486 dpa_ctl |= DP_PLL_ENABLE;
1487 I915_WRITE(DP_A, dpa_ctl);
1488 udelay(200);
1489}
1490
1491
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001492static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001493{
1494 struct drm_device *dev = crtc->dev;
1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 u32 dpa_ctl;
1497
Zhao Yakui28c97732009-10-09 11:39:41 +08001498 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001499 dpa_ctl = I915_READ(DP_A);
1500 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1501
1502 if (clock < 200000) {
1503 u32 temp;
1504 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1505 /* workaround for 160Mhz:
1506 1) program 0x4600c bits 15:0 = 0x8124
1507 2) program 0x46010 bit 0 = 1
1508 3) program 0x46034 bit 24 = 1
1509 4) program 0x64000 bit 14 = 1
1510 */
1511 temp = I915_READ(0x4600c);
1512 temp &= 0xffff0000;
1513 I915_WRITE(0x4600c, temp | 0x8124);
1514
1515 temp = I915_READ(0x46010);
1516 I915_WRITE(0x46010, temp | 1);
1517
1518 temp = I915_READ(0x46034);
1519 I915_WRITE(0x46034, temp | (1 << 24));
1520 } else {
1521 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1522 }
1523 I915_WRITE(DP_A, dpa_ctl);
1524
1525 udelay(500);
1526}
1527
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001528/* The FDI link training functions for ILK/Ibexpeak. */
1529static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1530{
1531 struct drm_device *dev = crtc->dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1534 int pipe = intel_crtc->pipe;
1535 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1536 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1537 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1538 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1539 u32 temp, tries = 0;
1540
1541 /* enable CPU FDI TX and PCH FDI RX */
1542 temp = I915_READ(fdi_tx_reg);
1543 temp |= FDI_TX_ENABLE;
Adam Jackson77ffb592010-04-12 11:38:44 -04001544 temp &= ~(7 << 19);
1545 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001546 temp &= ~FDI_LINK_TRAIN_NONE;
1547 temp |= FDI_LINK_TRAIN_PATTERN_1;
1548 I915_WRITE(fdi_tx_reg, temp);
1549 I915_READ(fdi_tx_reg);
1550
1551 temp = I915_READ(fdi_rx_reg);
1552 temp &= ~FDI_LINK_TRAIN_NONE;
1553 temp |= FDI_LINK_TRAIN_PATTERN_1;
1554 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1555 I915_READ(fdi_rx_reg);
1556 udelay(150);
1557
1558 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1559 for train result */
1560 temp = I915_READ(fdi_rx_imr_reg);
1561 temp &= ~FDI_RX_SYMBOL_LOCK;
1562 temp &= ~FDI_RX_BIT_LOCK;
1563 I915_WRITE(fdi_rx_imr_reg, temp);
1564 I915_READ(fdi_rx_imr_reg);
1565 udelay(150);
1566
1567 for (;;) {
1568 temp = I915_READ(fdi_rx_iir_reg);
1569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1570
1571 if ((temp & FDI_RX_BIT_LOCK)) {
1572 DRM_DEBUG_KMS("FDI train 1 done.\n");
1573 I915_WRITE(fdi_rx_iir_reg,
1574 temp | FDI_RX_BIT_LOCK);
1575 break;
1576 }
1577
1578 tries++;
1579
1580 if (tries > 5) {
1581 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1582 break;
1583 }
1584 }
1585
1586 /* Train 2 */
1587 temp = I915_READ(fdi_tx_reg);
1588 temp &= ~FDI_LINK_TRAIN_NONE;
1589 temp |= FDI_LINK_TRAIN_PATTERN_2;
1590 I915_WRITE(fdi_tx_reg, temp);
1591
1592 temp = I915_READ(fdi_rx_reg);
1593 temp &= ~FDI_LINK_TRAIN_NONE;
1594 temp |= FDI_LINK_TRAIN_PATTERN_2;
1595 I915_WRITE(fdi_rx_reg, temp);
1596 udelay(150);
1597
1598 tries = 0;
1599
1600 for (;;) {
1601 temp = I915_READ(fdi_rx_iir_reg);
1602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1603
1604 if (temp & FDI_RX_SYMBOL_LOCK) {
1605 I915_WRITE(fdi_rx_iir_reg,
1606 temp | FDI_RX_SYMBOL_LOCK);
1607 DRM_DEBUG_KMS("FDI train 2 done.\n");
1608 break;
1609 }
1610
1611 tries++;
1612
1613 if (tries > 5) {
1614 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1615 break;
1616 }
1617 }
1618
1619 DRM_DEBUG_KMS("FDI train done\n");
1620}
1621
1622static int snb_b_fdi_train_param [] = {
1623 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1624 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1625 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1626 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1627};
1628
1629/* The FDI link training functions for SNB/Cougarpoint. */
1630static void gen6_fdi_link_train(struct drm_crtc *crtc)
1631{
1632 struct drm_device *dev = crtc->dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1635 int pipe = intel_crtc->pipe;
1636 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1637 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1638 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1639 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1640 u32 temp, i;
1641
1642 /* enable CPU FDI TX and PCH FDI RX */
1643 temp = I915_READ(fdi_tx_reg);
1644 temp |= FDI_TX_ENABLE;
Adam Jackson77ffb592010-04-12 11:38:44 -04001645 temp &= ~(7 << 19);
1646 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001647 temp &= ~FDI_LINK_TRAIN_NONE;
1648 temp |= FDI_LINK_TRAIN_PATTERN_1;
1649 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1650 /* SNB-B */
1651 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1652 I915_WRITE(fdi_tx_reg, temp);
1653 I915_READ(fdi_tx_reg);
1654
1655 temp = I915_READ(fdi_rx_reg);
1656 if (HAS_PCH_CPT(dev)) {
1657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1658 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1659 } else {
1660 temp &= ~FDI_LINK_TRAIN_NONE;
1661 temp |= FDI_LINK_TRAIN_PATTERN_1;
1662 }
1663 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1664 I915_READ(fdi_rx_reg);
1665 udelay(150);
1666
1667 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1668 for train result */
1669 temp = I915_READ(fdi_rx_imr_reg);
1670 temp &= ~FDI_RX_SYMBOL_LOCK;
1671 temp &= ~FDI_RX_BIT_LOCK;
1672 I915_WRITE(fdi_rx_imr_reg, temp);
1673 I915_READ(fdi_rx_imr_reg);
1674 udelay(150);
1675
1676 for (i = 0; i < 4; i++ ) {
1677 temp = I915_READ(fdi_tx_reg);
1678 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1679 temp |= snb_b_fdi_train_param[i];
1680 I915_WRITE(fdi_tx_reg, temp);
1681 udelay(500);
1682
1683 temp = I915_READ(fdi_rx_iir_reg);
1684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1685
1686 if (temp & FDI_RX_BIT_LOCK) {
1687 I915_WRITE(fdi_rx_iir_reg,
1688 temp | FDI_RX_BIT_LOCK);
1689 DRM_DEBUG_KMS("FDI train 1 done.\n");
1690 break;
1691 }
1692 }
1693 if (i == 4)
1694 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1695
1696 /* Train 2 */
1697 temp = I915_READ(fdi_tx_reg);
1698 temp &= ~FDI_LINK_TRAIN_NONE;
1699 temp |= FDI_LINK_TRAIN_PATTERN_2;
1700 if (IS_GEN6(dev)) {
1701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1702 /* SNB-B */
1703 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1704 }
1705 I915_WRITE(fdi_tx_reg, temp);
1706
1707 temp = I915_READ(fdi_rx_reg);
1708 if (HAS_PCH_CPT(dev)) {
1709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1710 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1711 } else {
1712 temp &= ~FDI_LINK_TRAIN_NONE;
1713 temp |= FDI_LINK_TRAIN_PATTERN_2;
1714 }
1715 I915_WRITE(fdi_rx_reg, temp);
1716 udelay(150);
1717
1718 for (i = 0; i < 4; i++ ) {
1719 temp = I915_READ(fdi_tx_reg);
1720 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1721 temp |= snb_b_fdi_train_param[i];
1722 I915_WRITE(fdi_tx_reg, temp);
1723 udelay(500);
1724
1725 temp = I915_READ(fdi_rx_iir_reg);
1726 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1727
1728 if (temp & FDI_RX_SYMBOL_LOCK) {
1729 I915_WRITE(fdi_rx_iir_reg,
1730 temp | FDI_RX_SYMBOL_LOCK);
1731 DRM_DEBUG_KMS("FDI train 2 done.\n");
1732 break;
1733 }
1734 }
1735 if (i == 4)
1736 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1737
1738 DRM_DEBUG_KMS("FDI train done.\n");
1739}
1740
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001741static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08001742{
1743 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1746 int pipe = intel_crtc->pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001747 int plane = intel_crtc->plane;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001748 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1749 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1750 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1751 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1752 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1753 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001754 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1755 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001756 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001757 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001758 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1759 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1760 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1761 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1762 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1763 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1764 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1765 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1766 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1767 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1768 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1769 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001770 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001771 u32 temp;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001772 int n;
Zhao Yakui8faf3b32010-01-04 16:29:31 +08001773 u32 pipe_bpc;
1774
1775 temp = I915_READ(pipeconf_reg);
1776 pipe_bpc = temp & PIPE_BPC_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001777
1778 /* XXX: When our outputs are all unaware of DPMS modes other than off
1779 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1780 */
1781 switch (mode) {
1782 case DRM_MODE_DPMS_ON:
1783 case DRM_MODE_DPMS_STANDBY:
1784 case DRM_MODE_DPMS_SUSPEND:
Zhao Yakui28c97732009-10-09 11:39:41 +08001785 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08001786
1787 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1788 temp = I915_READ(PCH_LVDS);
1789 if ((temp & LVDS_PORT_EN) == 0) {
1790 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1791 POSTING_READ(PCH_LVDS);
1792 }
1793 }
1794
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001795 if (HAS_eDP) {
1796 /* enable eDP PLL */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001797 ironlake_enable_pll_edp(crtc);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001798 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001799
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001800 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1801 temp = I915_READ(fdi_rx_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08001802 /*
1803 * make the BPC in FDI Rx be consistent with that in
1804 * pipeconf reg.
1805 */
1806 temp &= ~(0x7 << 16);
1807 temp |= (pipe_bpc << 11);
Adam Jackson77ffb592010-04-12 11:38:44 -04001808 temp &= ~(7 << 19);
1809 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1810 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001811 I915_READ(fdi_rx_reg);
1812 udelay(200);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001813
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001814 /* Switch from Rawclk to PCDclk */
1815 temp = I915_READ(fdi_rx_reg);
1816 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001817 I915_READ(fdi_rx_reg);
1818 udelay(200);
1819
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001820 /* Enable CPU FDI TX PLL, always on for Ironlake */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001821 temp = I915_READ(fdi_tx_reg);
1822 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1823 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1824 I915_READ(fdi_tx_reg);
1825 udelay(100);
1826 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001827 }
1828
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001829 /* Enable panel fitting for LVDS */
1830 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1831 temp = I915_READ(pf_ctl_reg);
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08001832 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001833
1834 /* currently full aspect */
1835 I915_WRITE(pf_win_pos, 0);
1836
1837 I915_WRITE(pf_win_size,
1838 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1839 (dev_priv->panel_fixed_mode->vdisplay));
1840 }
1841
Zhenyu Wang2c072452009-06-05 15:38:42 +08001842 /* Enable CPU pipe */
1843 temp = I915_READ(pipeconf_reg);
1844 if ((temp & PIPEACONF_ENABLE) == 0) {
1845 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1846 I915_READ(pipeconf_reg);
1847 udelay(100);
1848 }
1849
1850 /* configure and enable CPU plane */
1851 temp = I915_READ(dspcntr_reg);
1852 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1853 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1854 /* Flush the plane changes */
1855 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1856 }
1857
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001858 if (!HAS_eDP) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001859 /* For PCH output, training FDI link */
1860 if (IS_GEN6(dev))
1861 gen6_fdi_link_train(crtc);
1862 else
1863 ironlake_fdi_link_train(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001864
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001865 /* enable PCH DPLL */
1866 temp = I915_READ(pch_dpll_reg);
1867 if ((temp & DPLL_VCO_ENABLE) == 0) {
1868 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1869 I915_READ(pch_dpll_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001870 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001871 udelay(200);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001872
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001873 if (HAS_PCH_CPT(dev)) {
1874 /* Be sure PCH DPLL SEL is set */
1875 temp = I915_READ(PCH_DPLL_SEL);
1876 if (trans_dpll_sel == 0 &&
1877 (temp & TRANSA_DPLL_ENABLE) == 0)
1878 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1879 else if (trans_dpll_sel == 1 &&
1880 (temp & TRANSB_DPLL_ENABLE) == 0)
1881 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1882 I915_WRITE(PCH_DPLL_SEL, temp);
1883 I915_READ(PCH_DPLL_SEL);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001884 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001885
1886 /* set transcoder timing */
1887 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1888 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1889 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1890
1891 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1892 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1893 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1894
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001895 /* enable normal train */
1896 temp = I915_READ(fdi_tx_reg);
1897 temp &= ~FDI_LINK_TRAIN_NONE;
1898 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1899 FDI_TX_ENHANCE_FRAME_ENABLE);
1900 I915_READ(fdi_tx_reg);
1901
1902 temp = I915_READ(fdi_rx_reg);
1903 if (HAS_PCH_CPT(dev)) {
1904 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1905 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1906 } else {
1907 temp &= ~FDI_LINK_TRAIN_NONE;
1908 temp |= FDI_LINK_TRAIN_NONE;
1909 }
1910 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1911 I915_READ(fdi_rx_reg);
1912
1913 /* wait one idle pattern time */
1914 udelay(100);
1915
Zhenyu Wange3421a12010-04-08 09:43:27 +08001916 /* For PCH DP, enable TRANS_DP_CTL */
1917 if (HAS_PCH_CPT(dev) &&
1918 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1919 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1920 int reg;
1921
1922 reg = I915_READ(trans_dp_ctl);
1923 reg &= ~TRANS_DP_PORT_SEL_MASK;
1924 reg = TRANS_DP_OUTPUT_ENABLE |
1925 TRANS_DP_ENH_FRAMING |
1926 TRANS_DP_VSYNC_ACTIVE_HIGH |
1927 TRANS_DP_HSYNC_ACTIVE_HIGH;
1928
1929 switch (intel_trans_dp_port_sel(crtc)) {
1930 case PCH_DP_B:
1931 reg |= TRANS_DP_PORT_SEL_B;
1932 break;
1933 case PCH_DP_C:
1934 reg |= TRANS_DP_PORT_SEL_C;
1935 break;
1936 case PCH_DP_D:
1937 reg |= TRANS_DP_PORT_SEL_D;
1938 break;
1939 default:
1940 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1941 reg |= TRANS_DP_PORT_SEL_B;
1942 break;
1943 }
1944
1945 I915_WRITE(trans_dp_ctl, reg);
1946 POSTING_READ(trans_dp_ctl);
1947 }
1948
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001949 /* enable PCH transcoder */
1950 temp = I915_READ(transconf_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08001951 /*
1952 * make the BPC in transcoder be consistent with
1953 * that in pipeconf reg.
1954 */
1955 temp &= ~PIPE_BPC_MASK;
1956 temp |= pipe_bpc;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001957 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1958 I915_READ(transconf_reg);
1959
1960 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1961 ;
1962
Zhenyu Wang2c072452009-06-05 15:38:42 +08001963 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001964
1965 intel_crtc_load_lut(crtc);
1966
1967 break;
1968 case DRM_MODE_DPMS_OFF:
Zhao Yakui28c97732009-10-09 11:39:41 +08001969 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001970
Li Pengc062df62010-01-23 00:12:58 +08001971 drm_vblank_off(dev, pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001972 /* Disable display plane */
1973 temp = I915_READ(dspcntr_reg);
1974 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1975 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1976 /* Flush the plane changes */
1977 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1978 I915_READ(dspbase_reg);
1979 }
1980
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08001981 i915_disable_vga(dev);
1982
Zhenyu Wang2c072452009-06-05 15:38:42 +08001983 /* disable cpu pipe, disable after all planes disabled */
1984 temp = I915_READ(pipeconf_reg);
1985 if ((temp & PIPEACONF_ENABLE) != 0) {
1986 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1987 I915_READ(pipeconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001988 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001989 /* wait for cpu pipe off, pipe state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001990 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1991 n++;
1992 if (n < 60) {
1993 udelay(500);
1994 continue;
1995 } else {
Zhao Yakui28c97732009-10-09 11:39:41 +08001996 DRM_DEBUG_KMS("pipe %d off delay\n",
1997 pipe);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001998 break;
1999 }
2000 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002001 } else
Zhao Yakui28c97732009-10-09 11:39:41 +08002002 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002003
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002004 udelay(100);
2005
2006 /* Disable PF */
2007 temp = I915_READ(pf_ctl_reg);
2008 if ((temp & PF_ENABLE) != 0) {
2009 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2010 I915_READ(pf_ctl_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002011 }
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002012 I915_WRITE(pf_win_size, 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002013 POSTING_READ(pf_win_size);
2014
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002015
Zhenyu Wang2c072452009-06-05 15:38:42 +08002016 /* disable CPU FDI tx and PCH FDI rx */
2017 temp = I915_READ(fdi_tx_reg);
2018 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2019 I915_READ(fdi_tx_reg);
2020
2021 temp = I915_READ(fdi_rx_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08002022 /* BPC in FDI rx is consistent with that in pipeconf */
2023 temp &= ~(0x07 << 16);
2024 temp |= (pipe_bpc << 11);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002025 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2026 I915_READ(fdi_rx_reg);
2027
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002028 udelay(100);
2029
Zhenyu Wang2c072452009-06-05 15:38:42 +08002030 /* still set train pattern 1 */
2031 temp = I915_READ(fdi_tx_reg);
2032 temp &= ~FDI_LINK_TRAIN_NONE;
2033 temp |= FDI_LINK_TRAIN_PATTERN_1;
2034 I915_WRITE(fdi_tx_reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002035 POSTING_READ(fdi_tx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002036
2037 temp = I915_READ(fdi_rx_reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002038 if (HAS_PCH_CPT(dev)) {
2039 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2040 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2041 } else {
2042 temp &= ~FDI_LINK_TRAIN_NONE;
2043 temp |= FDI_LINK_TRAIN_PATTERN_1;
2044 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002045 I915_WRITE(fdi_rx_reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002046 POSTING_READ(fdi_rx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002047
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002048 udelay(100);
2049
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002050 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2051 temp = I915_READ(PCH_LVDS);
2052 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2053 I915_READ(PCH_LVDS);
2054 udelay(100);
2055 }
2056
Zhenyu Wang2c072452009-06-05 15:38:42 +08002057 /* disable PCH transcoder */
2058 temp = I915_READ(transconf_reg);
2059 if ((temp & TRANS_ENABLE) != 0) {
2060 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2061 I915_READ(transconf_reg);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002062 n = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002063 /* wait for PCH transcoder off, transcoder state */
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002064 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2065 n++;
2066 if (n < 60) {
2067 udelay(500);
2068 continue;
2069 } else {
Zhao Yakui28c97732009-10-09 11:39:41 +08002070 DRM_DEBUG_KMS("transcoder %d off "
2071 "delay\n", pipe);
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002072 break;
2073 }
2074 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002075 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002076
Zhao Yakui8faf3b32010-01-04 16:29:31 +08002077 temp = I915_READ(transconf_reg);
2078 /* BPC in transcoder is consistent with that in pipeconf */
2079 temp &= ~PIPE_BPC_MASK;
2080 temp |= pipe_bpc;
2081 I915_WRITE(transconf_reg, temp);
2082 I915_READ(transconf_reg);
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002083 udelay(100);
2084
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002085 if (HAS_PCH_CPT(dev)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002086 /* disable TRANS_DP_CTL */
2087 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2088 int reg;
2089
2090 reg = I915_READ(trans_dp_ctl);
2091 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2092 I915_WRITE(trans_dp_ctl, reg);
2093 POSTING_READ(trans_dp_ctl);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002094
2095 /* disable DPLL_SEL */
2096 temp = I915_READ(PCH_DPLL_SEL);
2097 if (trans_dpll_sel == 0)
2098 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2099 else
2100 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2101 I915_WRITE(PCH_DPLL_SEL, temp);
2102 I915_READ(PCH_DPLL_SEL);
2103
2104 }
2105
Zhenyu Wang2c072452009-06-05 15:38:42 +08002106 /* disable PCH DPLL */
2107 temp = I915_READ(pch_dpll_reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002108 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2109 I915_READ(pch_dpll_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002110
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002111 if (HAS_eDP) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002112 ironlake_disable_pll_edp(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002113 }
2114
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002115 /* Switch from PCDclk to Rawclk */
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002116 temp = I915_READ(fdi_rx_reg);
2117 temp &= ~FDI_SEL_PCDCLK;
2118 I915_WRITE(fdi_rx_reg, temp);
2119 I915_READ(fdi_rx_reg);
2120
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002121 /* Disable CPU FDI TX PLL */
2122 temp = I915_READ(fdi_tx_reg);
2123 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2124 I915_READ(fdi_tx_reg);
2125 udelay(100);
2126
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002127 temp = I915_READ(fdi_rx_reg);
2128 temp &= ~FDI_RX_PLL_ENABLE;
2129 I915_WRITE(fdi_rx_reg, temp);
2130 I915_READ(fdi_rx_reg);
2131
Zhenyu Wang2c072452009-06-05 15:38:42 +08002132 /* Wait for the clocks to turn off. */
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002133 udelay(100);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002134 break;
2135 }
2136}
2137
Daniel Vetter02e792f2009-09-15 22:57:34 +02002138static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2139{
2140 struct intel_overlay *overlay;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002141 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +02002142
2143 if (!enable && intel_crtc->overlay) {
2144 overlay = intel_crtc->overlay;
2145 mutex_lock(&overlay->dev->struct_mutex);
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002146 for (;;) {
2147 ret = intel_overlay_switch_off(overlay);
2148 if (ret == 0)
2149 break;
2150
2151 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2152 if (ret != 0) {
2153 /* overlay doesn't react anymore. Usually
2154 * results in a black screen and an unkillable
2155 * X server. */
2156 BUG();
2157 overlay->hw_wedged = HW_WEDGED;
2158 break;
2159 }
2160 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02002161 mutex_unlock(&overlay->dev->struct_mutex);
2162 }
2163 /* Let userspace switch the overlay on again. In most cases userspace
2164 * has to recompute where to put it anyway. */
2165
2166 return;
2167}
2168
Zhenyu Wang2c072452009-06-05 15:38:42 +08002169static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2170{
2171 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07002175 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08002176 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
Jesse Barnes80824002009-09-10 15:28:06 -07002177 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2178 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
Jesse Barnes79e53942008-11-07 14:24:08 -08002179 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2180 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08002181
2182 /* XXX: When our outputs are all unaware of DPMS modes other than off
2183 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2184 */
2185 switch (mode) {
2186 case DRM_MODE_DPMS_ON:
2187 case DRM_MODE_DPMS_STANDBY:
2188 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes629598d2009-10-20 07:37:32 +09002189 intel_update_watermarks(dev);
2190
Jesse Barnes79e53942008-11-07 14:24:08 -08002191 /* Enable the DPLL */
2192 temp = I915_READ(dpll_reg);
2193 if ((temp & DPLL_VCO_ENABLE) == 0) {
2194 I915_WRITE(dpll_reg, temp);
2195 I915_READ(dpll_reg);
2196 /* Wait for the clocks to stabilize. */
2197 udelay(150);
2198 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2199 I915_READ(dpll_reg);
2200 /* Wait for the clocks to stabilize. */
2201 udelay(150);
2202 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2203 I915_READ(dpll_reg);
2204 /* Wait for the clocks to stabilize. */
2205 udelay(150);
2206 }
2207
2208 /* Enable the pipe */
2209 temp = I915_READ(pipeconf_reg);
2210 if ((temp & PIPEACONF_ENABLE) == 0)
2211 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2212
2213 /* Enable the plane */
2214 temp = I915_READ(dspcntr_reg);
2215 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2216 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2217 /* Flush the plane changes */
2218 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2219 }
2220
2221 intel_crtc_load_lut(crtc);
2222
Jesse Barnes74dff282009-09-14 15:39:40 -07002223 if ((IS_I965G(dev) || plane == 0))
2224 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnes80824002009-09-10 15:28:06 -07002225
Jesse Barnes79e53942008-11-07 14:24:08 -08002226 /* Give the overlay scaler a chance to enable if it's on this pipe */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002227 intel_crtc_dpms_overlay(intel_crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08002228 break;
2229 case DRM_MODE_DPMS_OFF:
Shaohua Li7662c8b2009-06-26 11:23:55 +08002230 intel_update_watermarks(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02002231
Jesse Barnes79e53942008-11-07 14:24:08 -08002232 /* Give the overlay scaler a chance to disable if it's on this pipe */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002233 intel_crtc_dpms_overlay(intel_crtc, false);
Li Peng778c9022009-11-09 12:51:22 +08002234 drm_vblank_off(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08002235
Jesse Barnese70236a2009-09-21 10:42:27 -07002236 if (dev_priv->cfb_plane == plane &&
2237 dev_priv->display.disable_fbc)
2238 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07002239
Jesse Barnes79e53942008-11-07 14:24:08 -08002240 /* Disable the VGA plane that we never use */
Zhenyu Wang24f119c2009-07-24 01:00:28 +08002241 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002242
2243 /* Disable display plane */
2244 temp = I915_READ(dspcntr_reg);
2245 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2246 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2247 /* Flush the plane changes */
2248 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2249 I915_READ(dspbase_reg);
2250 }
2251
2252 if (!IS_I9XX(dev)) {
2253 /* Wait for vblank for the disable to take effect */
2254 intel_wait_for_vblank(dev);
2255 }
2256
2257 /* Next, disable display pipes */
2258 temp = I915_READ(pipeconf_reg);
2259 if ((temp & PIPEACONF_ENABLE) != 0) {
2260 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2261 I915_READ(pipeconf_reg);
2262 }
2263
2264 /* Wait for vblank for the disable to take effect. */
2265 intel_wait_for_vblank(dev);
2266
2267 temp = I915_READ(dpll_reg);
2268 if ((temp & DPLL_VCO_ENABLE) != 0) {
2269 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2270 I915_READ(dpll_reg);
2271 }
2272
2273 /* Wait for the clocks to turn off. */
2274 udelay(150);
2275 break;
2276 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002277}
2278
2279/**
2280 * Sets the power management mode of the pipe and plane.
2281 *
2282 * This code should probably grow support for turning the cursor off and back
2283 * on appropriately at the same time as we're turning the pipe off/on.
2284 */
2285static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2286{
2287 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07002288 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002289 struct drm_i915_master_private *master_priv;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 bool enabled;
2293
Jesse Barnese70236a2009-09-21 10:42:27 -07002294 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002295
Daniel Vetter65655d42009-08-11 16:05:31 +02002296 intel_crtc->dpms_mode = mode;
2297
Jesse Barnes79e53942008-11-07 14:24:08 -08002298 if (!dev->primary->master)
2299 return;
2300
2301 master_priv = dev->primary->master->driver_priv;
2302 if (!master_priv->sarea_priv)
2303 return;
2304
2305 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2306
2307 switch (pipe) {
2308 case 0:
2309 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2310 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2311 break;
2312 case 1:
2313 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2314 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2315 break;
2316 default:
2317 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2318 break;
2319 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002320}
2321
2322static void intel_crtc_prepare (struct drm_crtc *crtc)
2323{
2324 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2325 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2326}
2327
2328static void intel_crtc_commit (struct drm_crtc *crtc)
2329{
2330 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2331 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2332}
2333
2334void intel_encoder_prepare (struct drm_encoder *encoder)
2335{
2336 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2337 /* lvds has its own version of prepare see intel_lvds_prepare */
2338 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2339}
2340
2341void intel_encoder_commit (struct drm_encoder *encoder)
2342{
2343 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2344 /* lvds has its own version of commit see intel_lvds_commit */
2345 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2346}
2347
2348static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2349 struct drm_display_mode *mode,
2350 struct drm_display_mode *adjusted_mode)
2351{
Zhenyu Wang2c072452009-06-05 15:38:42 +08002352 struct drm_device *dev = crtc->dev;
Eric Anholtbad720f2009-10-22 16:11:14 -07002353 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08002354 /* FDI link clock is fixed at 2.7G */
2355 if (mode->clock * 3 > 27000 * 4)
2356 return MODE_CLOCK_HIGH;
2357 }
Krzysztof Halasa734b4152010-05-25 18:41:46 +02002358
2359 drm_mode_set_crtcinfo(adjusted_mode, 0);
Jesse Barnes79e53942008-11-07 14:24:08 -08002360 return true;
2361}
2362
Jesse Barnese70236a2009-09-21 10:42:27 -07002363static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08002364{
Jesse Barnese70236a2009-09-21 10:42:27 -07002365 return 400000;
2366}
Jesse Barnes79e53942008-11-07 14:24:08 -08002367
Jesse Barnese70236a2009-09-21 10:42:27 -07002368static int i915_get_display_clock_speed(struct drm_device *dev)
2369{
2370 return 333000;
2371}
Jesse Barnes79e53942008-11-07 14:24:08 -08002372
Jesse Barnese70236a2009-09-21 10:42:27 -07002373static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2374{
2375 return 200000;
2376}
Jesse Barnes79e53942008-11-07 14:24:08 -08002377
Jesse Barnese70236a2009-09-21 10:42:27 -07002378static int i915gm_get_display_clock_speed(struct drm_device *dev)
2379{
2380 u16 gcfgc = 0;
2381
2382 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2383
2384 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08002385 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07002386 else {
2387 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2388 case GC_DISPLAY_CLOCK_333_MHZ:
2389 return 333000;
2390 default:
2391 case GC_DISPLAY_CLOCK_190_200_MHZ:
2392 return 190000;
2393 }
2394 }
2395}
Jesse Barnes79e53942008-11-07 14:24:08 -08002396
Jesse Barnese70236a2009-09-21 10:42:27 -07002397static int i865_get_display_clock_speed(struct drm_device *dev)
2398{
2399 return 266000;
2400}
2401
2402static int i855_get_display_clock_speed(struct drm_device *dev)
2403{
2404 u16 hpllcc = 0;
2405 /* Assume that the hardware is in the high speed state. This
2406 * should be the default.
2407 */
2408 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2409 case GC_CLOCK_133_200:
2410 case GC_CLOCK_100_200:
2411 return 200000;
2412 case GC_CLOCK_166_250:
2413 return 250000;
2414 case GC_CLOCK_100_133:
2415 return 133000;
2416 }
2417
2418 /* Shouldn't happen */
2419 return 0;
2420}
2421
2422static int i830_get_display_clock_speed(struct drm_device *dev)
2423{
2424 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08002425}
2426
Jesse Barnes79e53942008-11-07 14:24:08 -08002427/**
2428 * Return the pipe currently connected to the panel fitter,
2429 * or -1 if the panel fitter is not present or not in use
2430 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002431int intel_panel_fitter_pipe (struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08002432{
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 u32 pfit_control;
2435
2436 /* i830 doesn't have a panel fitter */
2437 if (IS_I830(dev))
2438 return -1;
2439
2440 pfit_control = I915_READ(PFIT_CONTROL);
2441
2442 /* See if the panel fitter is in use */
2443 if ((pfit_control & PFIT_ENABLE) == 0)
2444 return -1;
2445
2446 /* 965 can place panel fitter on either pipe */
2447 if (IS_I965G(dev))
2448 return (pfit_control >> 29) & 0x3;
2449
2450 /* older chips can only use pipe 1 */
2451 return 1;
2452}
2453
Zhenyu Wang2c072452009-06-05 15:38:42 +08002454struct fdi_m_n {
2455 u32 tu;
2456 u32 gmch_m;
2457 u32 gmch_n;
2458 u32 link_m;
2459 u32 link_n;
2460};
2461
2462static void
2463fdi_reduce_ratio(u32 *num, u32 *den)
2464{
2465 while (*num > 0xffffff || *den > 0xffffff) {
2466 *num >>= 1;
2467 *den >>= 1;
2468 }
2469}
2470
2471#define DATA_N 0x800000
2472#define LINK_N 0x80000
2473
2474static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002475ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2476 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08002477{
2478 u64 temp;
2479
2480 m_n->tu = 64; /* default size */
2481
2482 temp = (u64) DATA_N * pixel_clock;
2483 temp = div_u64(temp, link_clock);
Zhenyu Wang58a27472009-09-25 08:01:28 +00002484 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2485 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002486 m_n->gmch_n = DATA_N;
2487 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2488
2489 temp = (u64) LINK_N * pixel_clock;
2490 m_n->link_m = div_u64(temp, link_clock);
2491 m_n->link_n = LINK_N;
2492 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2493}
2494
2495
Shaohua Li7662c8b2009-06-26 11:23:55 +08002496struct intel_watermark_params {
2497 unsigned long fifo_size;
2498 unsigned long max_wm;
2499 unsigned long default_wm;
2500 unsigned long guard_size;
2501 unsigned long cacheline_size;
2502};
2503
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002504/* Pineview has different values for various configs */
2505static struct intel_watermark_params pineview_display_wm = {
2506 PINEVIEW_DISPLAY_FIFO,
2507 PINEVIEW_MAX_WM,
2508 PINEVIEW_DFT_WM,
2509 PINEVIEW_GUARD_WM,
2510 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002511};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002512static struct intel_watermark_params pineview_display_hplloff_wm = {
2513 PINEVIEW_DISPLAY_FIFO,
2514 PINEVIEW_MAX_WM,
2515 PINEVIEW_DFT_HPLLOFF_WM,
2516 PINEVIEW_GUARD_WM,
2517 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002518};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002519static struct intel_watermark_params pineview_cursor_wm = {
2520 PINEVIEW_CURSOR_FIFO,
2521 PINEVIEW_CURSOR_MAX_WM,
2522 PINEVIEW_CURSOR_DFT_WM,
2523 PINEVIEW_CURSOR_GUARD_WM,
2524 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002525};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002526static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2527 PINEVIEW_CURSOR_FIFO,
2528 PINEVIEW_CURSOR_MAX_WM,
2529 PINEVIEW_CURSOR_DFT_WM,
2530 PINEVIEW_CURSOR_GUARD_WM,
2531 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002532};
Jesse Barnes0e442c62009-10-19 10:09:33 +09002533static struct intel_watermark_params g4x_wm_info = {
2534 G4X_FIFO_SIZE,
2535 G4X_MAX_WM,
2536 G4X_MAX_WM,
2537 2,
2538 G4X_FIFO_LINE_SIZE,
2539};
Shaohua Li7662c8b2009-06-26 11:23:55 +08002540static struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08002541 I945_FIFO_SIZE,
2542 I915_MAX_WM,
2543 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002544 2,
2545 I915_FIFO_LINE_SIZE
2546};
2547static struct intel_watermark_params i915_wm_info = {
2548 I915_FIFO_SIZE,
2549 I915_MAX_WM,
2550 1,
2551 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002552 I915_FIFO_LINE_SIZE
2553};
2554static struct intel_watermark_params i855_wm_info = {
2555 I855GM_FIFO_SIZE,
2556 I915_MAX_WM,
2557 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002558 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002559 I830_FIFO_LINE_SIZE
2560};
2561static struct intel_watermark_params i830_wm_info = {
2562 I830_FIFO_SIZE,
2563 I915_MAX_WM,
2564 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002565 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002566 I830_FIFO_LINE_SIZE
2567};
2568
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002569static struct intel_watermark_params ironlake_display_wm_info = {
2570 ILK_DISPLAY_FIFO,
2571 ILK_DISPLAY_MAXWM,
2572 ILK_DISPLAY_DFTWM,
2573 2,
2574 ILK_FIFO_LINE_SIZE
2575};
2576
2577static struct intel_watermark_params ironlake_display_srwm_info = {
2578 ILK_DISPLAY_SR_FIFO,
2579 ILK_DISPLAY_MAX_SRWM,
2580 ILK_DISPLAY_DFT_SRWM,
2581 2,
2582 ILK_FIFO_LINE_SIZE
2583};
2584
2585static struct intel_watermark_params ironlake_cursor_srwm_info = {
2586 ILK_CURSOR_SR_FIFO,
2587 ILK_CURSOR_MAX_SRWM,
2588 ILK_CURSOR_DFT_SRWM,
2589 2,
2590 ILK_FIFO_LINE_SIZE
2591};
2592
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002593/**
2594 * intel_calculate_wm - calculate watermark level
2595 * @clock_in_khz: pixel clock
2596 * @wm: chip FIFO params
2597 * @pixel_size: display pixel size
2598 * @latency_ns: memory latency for the platform
2599 *
2600 * Calculate the watermark level (the level at which the display plane will
2601 * start fetching from memory again). Each chip has a different display
2602 * FIFO size and allocation, so the caller needs to figure that out and pass
2603 * in the correct intel_watermark_params structure.
2604 *
2605 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2606 * on the pixel size. When it reaches the watermark level, it'll start
2607 * fetching FIFO line sized based chunks from memory until the FIFO fills
2608 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2609 * will occur, and a display engine hang could result.
2610 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002611static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2612 struct intel_watermark_params *wm,
2613 int pixel_size,
2614 unsigned long latency_ns)
2615{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002616 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002617
Jesse Barnesd6604672009-09-11 12:25:56 -07002618 /*
2619 * Note: we need to make sure we don't overflow for various clock &
2620 * latency values.
2621 * clocks go from a few thousand to several hundred thousand.
2622 * latency is usually a few thousand
2623 */
2624 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2625 1000;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002626 entries_required /= wm->cacheline_size;
2627
Zhao Yakui28c97732009-10-09 11:39:41 +08002628 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002629
2630 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2631
Zhao Yakui28c97732009-10-09 11:39:41 +08002632 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002633
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002634 /* Don't promote wm_size to unsigned... */
2635 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002636 wm_size = wm->max_wm;
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002637 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002638 wm_size = wm->default_wm;
2639 return wm_size;
2640}
2641
2642struct cxsr_latency {
2643 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08002644 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002645 unsigned long fsb_freq;
2646 unsigned long mem_freq;
2647 unsigned long display_sr;
2648 unsigned long display_hpll_disable;
2649 unsigned long cursor_sr;
2650 unsigned long cursor_hpll_disable;
2651};
2652
2653static struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08002654 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2655 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2656 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2657 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2658 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002659
Li Peng95534262010-05-18 18:58:44 +08002660 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2661 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2662 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2663 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2664 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002665
Li Peng95534262010-05-18 18:58:44 +08002666 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2667 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2668 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2669 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2670 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002671
Li Peng95534262010-05-18 18:58:44 +08002672 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2673 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2674 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2675 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2676 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002677
Li Peng95534262010-05-18 18:58:44 +08002678 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2679 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2680 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2681 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2682 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002683
Li Peng95534262010-05-18 18:58:44 +08002684 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2685 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2686 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2687 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2688 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002689};
2690
Li Peng95534262010-05-18 18:58:44 +08002691static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2692 int fsb, int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002693{
2694 int i;
2695 struct cxsr_latency *latency;
2696
2697 if (fsb == 0 || mem == 0)
2698 return NULL;
2699
2700 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2701 latency = &cxsr_latency_table[i];
2702 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08002703 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302704 fsb == latency->fsb_freq && mem == latency->mem_freq)
2705 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002706 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302707
Zhao Yakui28c97732009-10-09 11:39:41 +08002708 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302709
2710 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002711}
2712
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002713static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002714{
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 u32 reg;
2717
2718 /* deactivate cxsr */
2719 reg = I915_READ(DSPFW3);
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002720 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002721 I915_WRITE(DSPFW3, reg);
2722 DRM_INFO("Big FIFO is disabled\n");
2723}
2724
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07002725/*
2726 * Latency for FIFO fetches is dependent on several factors:
2727 * - memory configuration (speed, channels)
2728 * - chipset
2729 * - current MCH state
2730 * It can be fairly high in some situations, so here we assume a fairly
2731 * pessimal value. It's a tradeoff between extra memory fetches (if we
2732 * set this value too high, the FIFO will fetch frequently to stay full)
2733 * and power consumption (set it too low to save power and we might see
2734 * FIFO underruns and display "flicker").
2735 *
2736 * A value of 5us seems to be a good balance; safe for very low end
2737 * platforms but not overly aggressive on lower latency configs.
2738 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01002739static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002740
Jesse Barnese70236a2009-09-21 10:42:27 -07002741static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002742{
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 uint32_t dsparb = I915_READ(DSPARB);
2745 int size;
2746
Jesse Barnese70236a2009-09-21 10:42:27 -07002747 if (plane == 0)
Jesse Barnesf3601322009-07-22 12:54:59 -07002748 size = dsparb & 0x7f;
Jesse Barnese70236a2009-09-21 10:42:27 -07002749 else
2750 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2751 (dsparb & 0x7f);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002752
Zhao Yakui28c97732009-10-09 11:39:41 +08002753 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2754 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002755
2756 return size;
2757}
Shaohua Li7662c8b2009-06-26 11:23:55 +08002758
Jesse Barnese70236a2009-09-21 10:42:27 -07002759static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2760{
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 uint32_t dsparb = I915_READ(DSPARB);
2763 int size;
2764
2765 if (plane == 0)
2766 size = dsparb & 0x1ff;
2767 else
2768 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2769 (dsparb & 0x1ff);
2770 size >>= 1; /* Convert to cachelines */
2771
Zhao Yakui28c97732009-10-09 11:39:41 +08002772 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2773 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07002774
2775 return size;
2776}
2777
2778static int i845_get_fifo_size(struct drm_device *dev, int plane)
2779{
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 uint32_t dsparb = I915_READ(DSPARB);
2782 int size;
2783
2784 size = dsparb & 0x7f;
2785 size >>= 2; /* Convert to cachelines */
2786
Zhao Yakui28c97732009-10-09 11:39:41 +08002787 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2788 plane ? "B" : "A",
Jesse Barnese70236a2009-09-21 10:42:27 -07002789 size);
2790
2791 return size;
2792}
2793
2794static int i830_get_fifo_size(struct drm_device *dev, int plane)
2795{
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 uint32_t dsparb = I915_READ(DSPARB);
2798 int size;
2799
2800 size = dsparb & 0x7f;
2801 size >>= 1; /* Convert to cachelines */
2802
Zhao Yakui28c97732009-10-09 11:39:41 +08002803 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2804 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07002805
2806 return size;
2807}
2808
Zhao Yakuid4294342010-03-22 22:45:36 +08002809static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2810 int planeb_clock, int sr_hdisplay, int pixel_size)
2811{
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 u32 reg;
2814 unsigned long wm;
2815 struct cxsr_latency *latency;
2816 int sr_clock;
2817
Li Peng95534262010-05-18 18:58:44 +08002818 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2819 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08002820 if (!latency) {
2821 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2822 pineview_disable_cxsr(dev);
2823 return;
2824 }
2825
2826 if (!planea_clock || !planeb_clock) {
2827 sr_clock = planea_clock ? planea_clock : planeb_clock;
2828
2829 /* Display SR */
2830 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2831 pixel_size, latency->display_sr);
2832 reg = I915_READ(DSPFW1);
2833 reg &= ~DSPFW_SR_MASK;
2834 reg |= wm << DSPFW_SR_SHIFT;
2835 I915_WRITE(DSPFW1, reg);
2836 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2837
2838 /* cursor SR */
2839 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2840 pixel_size, latency->cursor_sr);
2841 reg = I915_READ(DSPFW3);
2842 reg &= ~DSPFW_CURSOR_SR_MASK;
2843 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2844 I915_WRITE(DSPFW3, reg);
2845
2846 /* Display HPLL off SR */
2847 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2848 pixel_size, latency->display_hpll_disable);
2849 reg = I915_READ(DSPFW3);
2850 reg &= ~DSPFW_HPLL_SR_MASK;
2851 reg |= wm & DSPFW_HPLL_SR_MASK;
2852 I915_WRITE(DSPFW3, reg);
2853
2854 /* cursor HPLL off SR */
2855 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2856 pixel_size, latency->cursor_hpll_disable);
2857 reg = I915_READ(DSPFW3);
2858 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2859 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2860 I915_WRITE(DSPFW3, reg);
2861 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2862
2863 /* activate cxsr */
2864 reg = I915_READ(DSPFW3);
2865 reg |= PINEVIEW_SELF_REFRESH_EN;
2866 I915_WRITE(DSPFW3, reg);
2867 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2868 } else {
2869 pineview_disable_cxsr(dev);
2870 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2871 }
2872}
2873
Jesse Barnes0e442c62009-10-19 10:09:33 +09002874static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2875 int planeb_clock, int sr_hdisplay, int pixel_size)
Jesse Barnes652c3932009-08-17 13:31:43 -07002876{
2877 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e442c62009-10-19 10:09:33 +09002878 int total_size, cacheline_size;
2879 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2880 struct intel_watermark_params planea_params, planeb_params;
2881 unsigned long line_time_us;
2882 int sr_clock, sr_entries = 0, entries_required;
Jesse Barnes652c3932009-08-17 13:31:43 -07002883
Jesse Barnes0e442c62009-10-19 10:09:33 +09002884 /* Create copies of the base settings for each pipe */
2885 planea_params = planeb_params = g4x_wm_info;
2886
2887 /* Grab a couple of global values before we overwrite them */
2888 total_size = planea_params.fifo_size;
2889 cacheline_size = planea_params.cacheline_size;
2890
2891 /*
2892 * Note: we need to make sure we don't overflow for various clock &
2893 * latency values.
2894 * clocks go from a few thousand to several hundred thousand.
2895 * latency is usually a few thousand
2896 */
2897 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2898 1000;
2899 entries_required /= G4X_FIFO_LINE_SIZE;
2900 planea_wm = entries_required + planea_params.guard_size;
2901
2902 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2903 1000;
2904 entries_required /= G4X_FIFO_LINE_SIZE;
2905 planeb_wm = entries_required + planeb_params.guard_size;
2906
2907 cursora_wm = cursorb_wm = 16;
2908 cursor_sr = 32;
2909
2910 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2911
2912 /* Calc sr entries for one plane configs */
2913 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2914 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01002915 static const int sr_latency_ns = 12000;
Jesse Barnes0e442c62009-10-19 10:09:33 +09002916
2917 sr_clock = planea_clock ? planea_clock : planeb_clock;
2918 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2919
2920 /* Use ns/us then divide to preserve precision */
2921 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2922 pixel_size * sr_hdisplay) / 1000;
2923 sr_entries = roundup(sr_entries / cacheline_size, 1);
2924 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2925 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05302926 } else {
2927 /* Turn off self refresh if both pipes are enabled */
2928 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2929 & ~FW_BLC_SELF_EN);
Jesse Barnes0e442c62009-10-19 10:09:33 +09002930 }
2931
2932 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2933 planea_wm, planeb_wm, sr_entries);
2934
2935 planea_wm &= 0x3f;
2936 planeb_wm &= 0x3f;
2937
2938 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2939 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2940 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2941 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2942 (cursora_wm << DSPFW_CURSORA_SHIFT));
2943 /* HPLL off in SR has some issues on G4x... disable it */
2944 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2945 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07002946}
2947
Jesse Barnes1dc75462009-10-19 10:08:17 +09002948static void i965_update_wm(struct drm_device *dev, int planea_clock,
2949 int planeb_clock, int sr_hdisplay, int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002950{
2951 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1dc75462009-10-19 10:08:17 +09002952 unsigned long line_time_us;
2953 int sr_clock, sr_entries, srwm = 1;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002954
Jesse Barnes1dc75462009-10-19 10:08:17 +09002955 /* Calc sr entries for one plane configs */
2956 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2957 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01002958 static const int sr_latency_ns = 12000;
Jesse Barnes1dc75462009-10-19 10:08:17 +09002959
2960 sr_clock = planea_clock ? planea_clock : planeb_clock;
2961 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2962
2963 /* Use ns/us then divide to preserve precision */
2964 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2965 pixel_size * sr_hdisplay) / 1000;
2966 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2967 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2968 srwm = I945_FIFO_SIZE - sr_entries;
2969 if (srwm < 0)
2970 srwm = 1;
2971 srwm &= 0x3f;
2972 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05302973 } else {
2974 /* Turn off self refresh if both pipes are enabled */
2975 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2976 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09002977 }
2978
2979 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2980 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002981
2982 /* 965 has limitations... */
Jesse Barnes1dc75462009-10-19 10:08:17 +09002983 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2984 (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08002985 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2986}
2987
2988static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2989 int planeb_clock, int sr_hdisplay, int pixel_size)
2990{
2991 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002992 uint32_t fwater_lo;
2993 uint32_t fwater_hi;
2994 int total_size, cacheline_size, cwm, srwm = 1;
2995 int planea_wm, planeb_wm;
2996 struct intel_watermark_params planea_params, planeb_params;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002997 unsigned long line_time_us;
2998 int sr_clock, sr_entries = 0;
2999
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003000 /* Create copies of the base settings for each pipe */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003001 if (IS_I965GM(dev) || IS_I945GM(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003002 planea_params = planeb_params = i945_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003003 else if (IS_I9XX(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003004 planea_params = planeb_params = i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003005 else
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003006 planea_params = planeb_params = i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003007
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003008 /* Grab a couple of global values before we overwrite them */
3009 total_size = planea_params.fifo_size;
3010 cacheline_size = planea_params.cacheline_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003011
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003012 /* Update per-plane FIFO sizes */
Jesse Barnese70236a2009-09-21 10:42:27 -07003013 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3014 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003015
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003016 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3017 pixel_size, latency_ns);
3018 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3019 pixel_size, latency_ns);
Zhao Yakui28c97732009-10-09 11:39:41 +08003020 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003021
3022 /*
3023 * Overlay gets an aggressive default since video jitter is bad.
3024 */
3025 cwm = 2;
3026
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003027 /* Calc sr entries for one plane configs */
Jesse Barnes652c3932009-08-17 13:31:43 -07003028 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3029 (!planea_clock || !planeb_clock)) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003030 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003031 static const int sr_latency_ns = 6000;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003032
Shaohua Li7662c8b2009-06-26 11:23:55 +08003033 sr_clock = planea_clock ? planea_clock : planeb_clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003034 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3035
3036 /* Use ns/us then divide to preserve precision */
3037 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
3038 pixel_size * sr_hdisplay) / 1000;
3039 sr_entries = roundup(sr_entries / cacheline_size, 1);
Zhao Yakui28c97732009-10-09 11:39:41 +08003040 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003041 srwm = total_size - sr_entries;
3042 if (srwm < 0)
3043 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08003044
3045 if (IS_I945G(dev) || IS_I945GM(dev))
3046 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3047 else if (IS_I915GM(dev)) {
3048 /* 915M has a smaller SRWM field */
3049 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3050 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3051 }
David John33c5fd12010-01-27 15:19:08 +05303052 } else {
3053 /* Turn off self refresh if both pipes are enabled */
Li Pengee980b82010-01-27 19:01:11 +08003054 if (IS_I945G(dev) || IS_I945GM(dev)) {
3055 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3056 & ~FW_BLC_SELF_EN);
3057 } else if (IS_I915GM(dev)) {
3058 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3059 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08003060 }
3061
Zhao Yakui28c97732009-10-09 11:39:41 +08003062 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003063 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003064
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003065 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3066 fwater_hi = (cwm & 0x1f);
3067
3068 /* Set request length to 8 cachelines per fetch */
3069 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3070 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003071
3072 I915_WRITE(FW_BLC, fwater_lo);
3073 I915_WRITE(FW_BLC2, fwater_hi);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003074}
3075
Jesse Barnese70236a2009-09-21 10:42:27 -07003076static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3077 int unused2, int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003078{
3079 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf3601322009-07-22 12:54:59 -07003080 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003081 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003082
Jesse Barnese70236a2009-09-21 10:42:27 -07003083 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003084
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003085 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3086 pixel_size, latency_ns);
Jesse Barnesf3601322009-07-22 12:54:59 -07003087 fwater_lo |= (3<<8) | planea_wm;
3088
Zhao Yakui28c97732009-10-09 11:39:41 +08003089 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003090
3091 I915_WRITE(FW_BLC, fwater_lo);
3092}
3093
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003094#define ILK_LP0_PLANE_LATENCY 700
3095
3096static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3097 int planeb_clock, int sr_hdisplay, int pixel_size)
3098{
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3101 int sr_wm, cursor_wm;
3102 unsigned long line_time_us;
3103 int sr_clock, entries_required;
3104 u32 reg_value;
3105
3106 /* Calculate and update the watermark for plane A */
3107 if (planea_clock) {
3108 entries_required = ((planea_clock / 1000) * pixel_size *
3109 ILK_LP0_PLANE_LATENCY) / 1000;
3110 entries_required = DIV_ROUND_UP(entries_required,
3111 ironlake_display_wm_info.cacheline_size);
3112 planea_wm = entries_required +
3113 ironlake_display_wm_info.guard_size;
3114
3115 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3116 planea_wm = ironlake_display_wm_info.max_wm;
3117
3118 cursora_wm = 16;
3119 reg_value = I915_READ(WM0_PIPEA_ILK);
3120 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3121 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3122 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3123 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3124 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3125 "cursor: %d\n", planea_wm, cursora_wm);
3126 }
3127 /* Calculate and update the watermark for plane B */
3128 if (planeb_clock) {
3129 entries_required = ((planeb_clock / 1000) * pixel_size *
3130 ILK_LP0_PLANE_LATENCY) / 1000;
3131 entries_required = DIV_ROUND_UP(entries_required,
3132 ironlake_display_wm_info.cacheline_size);
3133 planeb_wm = entries_required +
3134 ironlake_display_wm_info.guard_size;
3135
3136 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3137 planeb_wm = ironlake_display_wm_info.max_wm;
3138
3139 cursorb_wm = 16;
3140 reg_value = I915_READ(WM0_PIPEB_ILK);
3141 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3142 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3143 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3144 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3145 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3146 "cursor: %d\n", planeb_wm, cursorb_wm);
3147 }
3148
3149 /*
3150 * Calculate and update the self-refresh watermark only when one
3151 * display plane is used.
3152 */
3153 if (!planea_clock || !planeb_clock) {
3154 int line_count;
3155 /* Read the self-refresh latency. The unit is 0.5us */
3156 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3157
3158 sr_clock = planea_clock ? planea_clock : planeb_clock;
3159 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3160
3161 /* Use ns/us then divide to preserve precision */
3162 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3163 / 1000;
3164
3165 /* calculate the self-refresh watermark for display plane */
3166 entries_required = line_count * sr_hdisplay * pixel_size;
3167 entries_required = DIV_ROUND_UP(entries_required,
3168 ironlake_display_srwm_info.cacheline_size);
3169 sr_wm = entries_required +
3170 ironlake_display_srwm_info.guard_size;
3171
3172 /* calculate the self-refresh watermark for display cursor */
3173 entries_required = line_count * pixel_size * 64;
3174 entries_required = DIV_ROUND_UP(entries_required,
3175 ironlake_cursor_srwm_info.cacheline_size);
3176 cursor_wm = entries_required +
3177 ironlake_cursor_srwm_info.guard_size;
3178
3179 /* configure watermark and enable self-refresh */
3180 reg_value = I915_READ(WM1_LP_ILK);
3181 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3182 WM1_LP_CURSOR_MASK);
3183 reg_value |= WM1_LP_SR_EN |
3184 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3185 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3186
3187 I915_WRITE(WM1_LP_ILK, reg_value);
3188 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3189 "cursor %d\n", sr_wm, cursor_wm);
3190
3191 } else {
3192 /* Turn off self refresh if both pipes are enabled */
3193 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3194 }
3195}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003196/**
3197 * intel_update_watermarks - update FIFO watermark values based on current modes
3198 *
3199 * Calculate watermark values for the various WM regs based on current mode
3200 * and plane configuration.
3201 *
3202 * There are several cases to deal with here:
3203 * - normal (i.e. non-self-refresh)
3204 * - self-refresh (SR) mode
3205 * - lines are large relative to FIFO size (buffer can hold up to 2)
3206 * - lines are small relative to FIFO size (buffer can hold more than 2
3207 * lines), so need to account for TLB latency
3208 *
3209 * The normal calculation is:
3210 * watermark = dotclock * bytes per pixel * latency
3211 * where latency is platform & configuration dependent (we assume pessimal
3212 * values here).
3213 *
3214 * The SR calculation is:
3215 * watermark = (trunc(latency/line time)+1) * surface width *
3216 * bytes per pixel
3217 * where
3218 * line time = htotal / dotclock
3219 * and latency is assumed to be high, as above.
3220 *
3221 * The final value programmed to the register should always be rounded up,
3222 * and include an extra 2 entries to account for clock crossings.
3223 *
3224 * We don't use the sprite, so we can ignore that. And on Crestline we have
3225 * to set the non-SR watermarks to 8.
3226 */
3227static void intel_update_watermarks(struct drm_device *dev)
3228{
Jesse Barnese70236a2009-09-21 10:42:27 -07003229 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003230 struct drm_crtc *crtc;
3231 struct intel_crtc *intel_crtc;
3232 int sr_hdisplay = 0;
3233 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3234 int enabled = 0, pixel_size = 0;
3235
Zhenyu Wangc03342f2009-09-29 11:01:23 +08003236 if (!dev_priv->display.update_wm)
3237 return;
3238
Shaohua Li7662c8b2009-06-26 11:23:55 +08003239 /* Get the clock config from both planes */
3240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3241 intel_crtc = to_intel_crtc(crtc);
3242 if (crtc->enabled) {
3243 enabled++;
3244 if (intel_crtc->plane == 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08003245 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
Shaohua Li7662c8b2009-06-26 11:23:55 +08003246 intel_crtc->pipe, crtc->mode.clock);
3247 planea_clock = crtc->mode.clock;
3248 } else {
Zhao Yakui28c97732009-10-09 11:39:41 +08003249 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
Shaohua Li7662c8b2009-06-26 11:23:55 +08003250 intel_crtc->pipe, crtc->mode.clock);
3251 planeb_clock = crtc->mode.clock;
3252 }
3253 sr_hdisplay = crtc->mode.hdisplay;
3254 sr_clock = crtc->mode.clock;
3255 if (crtc->fb)
3256 pixel_size = crtc->fb->bits_per_pixel / 8;
3257 else
3258 pixel_size = 4; /* by default */
3259 }
3260 }
3261
3262 if (enabled <= 0)
3263 return;
3264
Jesse Barnese70236a2009-09-21 10:42:27 -07003265 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3266 sr_hdisplay, pixel_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003267}
3268
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003269static int intel_crtc_mode_set(struct drm_crtc *crtc,
3270 struct drm_display_mode *mode,
3271 struct drm_display_mode *adjusted_mode,
3272 int x, int y,
3273 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08003274{
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3278 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003279 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003280 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3281 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3282 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
Jesse Barnes80824002009-09-10 15:28:06 -07003283 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Jesse Barnes79e53942008-11-07 14:24:08 -08003284 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3285 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3286 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3287 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3288 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3289 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3290 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
Jesse Barnes80824002009-09-10 15:28:06 -07003291 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3292 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
Jesse Barnes79e53942008-11-07 14:24:08 -08003293 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Eric Anholtc751ce42010-03-25 11:48:48 -07003294 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07003295 intel_clock_t clock, reduced_clock;
3296 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3297 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003298 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003299 bool is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08003300 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003301 struct drm_encoder *encoder;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003302 struct intel_encoder *intel_encoder = NULL;
Ma Lingd4906092009-03-18 20:13:27 +08003303 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003304 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003305 struct fdi_m_n m_n = {0};
3306 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3307 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3308 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3309 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3310 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3311 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3312 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003313 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3314 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
Zhenyu Wang541998a2009-06-05 15:38:44 +08003315 int lvds_reg = LVDS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003316 u32 temp;
3317 int sdvo_pixel_multiply;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003318 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08003319
3320 drm_vblank_pre_modeset(dev, pipe);
3321
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003322 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003323
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003324 if (!encoder || encoder->crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003325 continue;
3326
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003327 intel_encoder = enc_to_intel_encoder(encoder);
3328
Eric Anholt21d40d32010-03-25 11:11:14 -07003329 switch (intel_encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003330 case INTEL_OUTPUT_LVDS:
3331 is_lvds = true;
3332 break;
3333 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08003334 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08003335 is_sdvo = true;
Eric Anholt21d40d32010-03-25 11:11:14 -07003336 if (intel_encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08003337 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08003338 break;
3339 case INTEL_OUTPUT_DVO:
3340 is_dvo = true;
3341 break;
3342 case INTEL_OUTPUT_TVOUT:
3343 is_tv = true;
3344 break;
3345 case INTEL_OUTPUT_ANALOG:
3346 is_crt = true;
3347 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003348 case INTEL_OUTPUT_DISPLAYPORT:
3349 is_dp = true;
3350 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003351 case INTEL_OUTPUT_EDP:
3352 is_edp = true;
3353 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003354 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003355
Eric Anholtc751ce42010-03-25 11:48:48 -07003356 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08003357 }
3358
Eric Anholtc751ce42010-03-25 11:48:48 -07003359 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003360 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08003361 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3362 refclk / 1000);
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003363 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003364 refclk = 96000;
Eric Anholtbad720f2009-10-22 16:11:14 -07003365 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003366 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08003367 } else {
3368 refclk = 48000;
3369 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003370
Jesse Barnes79e53942008-11-07 14:24:08 -08003371
Ma Lingd4906092009-03-18 20:13:27 +08003372 /*
3373 * Returns a set of divisors for the desired target clock with the given
3374 * refclk, or FALSE. The returned values represent the clock equation:
3375 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3376 */
3377 limit = intel_limit(crtc);
3378 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003379 if (!ok) {
3380 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01003381 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003382 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08003383 }
3384
Zhao Yakuiddc90032010-01-06 22:05:56 +08003385 if (is_lvds && dev_priv->lvds_downclock_avail) {
3386 has_reduced_clock = limit->find_pll(limit, crtc,
Zhao Yakui18f9ed12009-11-20 03:24:16 +00003387 dev_priv->lvds_downclock,
Jesse Barnes652c3932009-08-17 13:31:43 -07003388 refclk,
3389 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00003390 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3391 /*
3392 * If the different P is found, it means that we can't
3393 * switch the display clock by using the FP0/FP1.
3394 * In such case we will disable the LVDS downclock
3395 * feature.
3396 */
3397 DRM_DEBUG_KMS("Different P is found for "
3398 "LVDS clock/downclock\n");
3399 has_reduced_clock = 0;
3400 }
Jesse Barnes652c3932009-08-17 13:31:43 -07003401 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08003402 /* SDVO TV has fixed PLL values depend on its clock range,
3403 this mirrors vbios setting. */
3404 if (is_sdvo && is_tv) {
3405 if (adjusted_mode->clock >= 100000
3406 && adjusted_mode->clock < 140500) {
3407 clock.p1 = 2;
3408 clock.p2 = 10;
3409 clock.n = 3;
3410 clock.m1 = 16;
3411 clock.m2 = 8;
3412 } else if (adjusted_mode->clock >= 140500
3413 && adjusted_mode->clock <= 200000) {
3414 clock.p1 = 1;
3415 clock.p2 = 10;
3416 clock.n = 6;
3417 clock.m1 = 12;
3418 clock.m2 = 8;
3419 }
3420 }
3421
Zhenyu Wang2c072452009-06-05 15:38:42 +08003422 /* FDI link */
Eric Anholtbad720f2009-10-22 16:11:14 -07003423 if (HAS_PCH_SPLIT(dev)) {
Adam Jackson77ffb592010-04-12 11:38:44 -04003424 int lane = 0, link_bw, bpp;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003425 /* eDP doesn't require FDI link, so just set DP M/N
3426 according to current link config */
3427 if (is_edp) {
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003428 target_clock = mode->clock;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003429 intel_edp_link_config(intel_encoder,
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003430 &lane, &link_bw);
3431 } else {
3432 /* DP over FDI requires target mode clock
3433 instead of link clock */
3434 if (is_dp)
3435 target_clock = mode->clock;
3436 else
3437 target_clock = adjusted_mode->clock;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003438 link_bw = 270000;
3439 }
Zhenyu Wang58a27472009-09-25 08:01:28 +00003440
3441 /* determine panel color depth */
3442 temp = I915_READ(pipeconf_reg);
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08003443 temp &= ~PIPE_BPC_MASK;
3444 if (is_lvds) {
3445 int lvds_reg = I915_READ(PCH_LVDS);
3446 /* the BPC will be 6 if it is 18-bit LVDS panel */
3447 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3448 temp |= PIPE_8BPC;
3449 else
3450 temp |= PIPE_6BPC;
Zhenyu Wang885a5fb2010-01-12 05:38:31 +08003451 } else if (is_edp) {
3452 switch (dev_priv->edp_bpp/3) {
3453 case 8:
3454 temp |= PIPE_8BPC;
3455 break;
3456 case 10:
3457 temp |= PIPE_10BPC;
3458 break;
3459 case 6:
3460 temp |= PIPE_6BPC;
3461 break;
3462 case 12:
3463 temp |= PIPE_12BPC;
3464 break;
3465 }
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08003466 } else
3467 temp |= PIPE_8BPC;
3468 I915_WRITE(pipeconf_reg, temp);
3469 I915_READ(pipeconf_reg);
Zhenyu Wang58a27472009-09-25 08:01:28 +00003470
3471 switch (temp & PIPE_BPC_MASK) {
3472 case PIPE_8BPC:
3473 bpp = 24;
3474 break;
3475 case PIPE_10BPC:
3476 bpp = 30;
3477 break;
3478 case PIPE_6BPC:
3479 bpp = 18;
3480 break;
3481 case PIPE_12BPC:
3482 bpp = 36;
3483 break;
3484 default:
3485 DRM_ERROR("unknown pipe bpc value\n");
3486 bpp = 24;
3487 }
3488
Adam Jackson77ffb592010-04-12 11:38:44 -04003489 if (!lane) {
3490 /*
3491 * Account for spread spectrum to avoid
3492 * oversubscribing the link. Max center spread
3493 * is 2.5%; use 5% for safety's sake.
3494 */
3495 u32 bps = target_clock * bpp * 21 / 20;
3496 lane = bps / (link_bw * 8) + 1;
3497 }
3498
3499 intel_crtc->fdi_lanes = lane;
3500
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003501 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003502 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003503
Zhenyu Wangc038e512009-10-19 15:43:48 +08003504 /* Ironlake: try to setup display ref clock before DPLL
3505 * enabling. This is only under driver's control after
3506 * PCH B stepping, previous chipset stepping should be
3507 * ignoring this setting.
3508 */
Eric Anholtbad720f2009-10-22 16:11:14 -07003509 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wangc038e512009-10-19 15:43:48 +08003510 temp = I915_READ(PCH_DREF_CONTROL);
3511 /* Always enable nonspread source */
3512 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3513 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3514 I915_WRITE(PCH_DREF_CONTROL, temp);
3515 POSTING_READ(PCH_DREF_CONTROL);
3516
3517 temp &= ~DREF_SSC_SOURCE_MASK;
3518 temp |= DREF_SSC_SOURCE_ENABLE;
3519 I915_WRITE(PCH_DREF_CONTROL, temp);
3520 POSTING_READ(PCH_DREF_CONTROL);
3521
3522 udelay(200);
3523
3524 if (is_edp) {
3525 if (dev_priv->lvds_use_ssc) {
3526 temp |= DREF_SSC1_ENABLE;
3527 I915_WRITE(PCH_DREF_CONTROL, temp);
3528 POSTING_READ(PCH_DREF_CONTROL);
3529
3530 udelay(200);
3531
3532 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3533 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3534 I915_WRITE(PCH_DREF_CONTROL, temp);
3535 POSTING_READ(PCH_DREF_CONTROL);
3536 } else {
3537 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3538 I915_WRITE(PCH_DREF_CONTROL, temp);
3539 POSTING_READ(PCH_DREF_CONTROL);
3540 }
3541 }
3542 }
3543
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003544 if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08003545 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07003546 if (has_reduced_clock)
3547 fp2 = (1 << reduced_clock.n) << 16 |
3548 reduced_clock.m1 << 8 | reduced_clock.m2;
3549 } else {
Shaohua Li21778322009-02-23 15:19:16 +08003550 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07003551 if (has_reduced_clock)
3552 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3553 reduced_clock.m2;
3554 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003555
Eric Anholtbad720f2009-10-22 16:11:14 -07003556 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003557 dpll = DPLL_VGA_MODE_DIS;
3558
Jesse Barnes79e53942008-11-07 14:24:08 -08003559 if (IS_I9XX(dev)) {
3560 if (is_lvds)
3561 dpll |= DPLLB_MODE_LVDS;
3562 else
3563 dpll |= DPLLB_MODE_DAC_SERIAL;
3564 if (is_sdvo) {
3565 dpll |= DPLL_DVO_HIGH_SPEED;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003566 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
Sean Young942642a2009-08-06 17:35:50 +08003567 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003568 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Eric Anholtbad720f2009-10-22 16:11:14 -07003569 else if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003570 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08003571 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003572 if (is_dp)
3573 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08003574
3575 /* compute bitmask from p1 value */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003576 if (IS_PINEVIEW(dev))
3577 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003578 else {
Shaohua Li21778322009-02-23 15:19:16 +08003579 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003580 /* also FPA1 */
Eric Anholtbad720f2009-10-22 16:11:14 -07003581 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003582 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07003583 if (IS_G4X(dev) && has_reduced_clock)
3584 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003585 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003586 switch (clock.p2) {
3587 case 5:
3588 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3589 break;
3590 case 7:
3591 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3592 break;
3593 case 10:
3594 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3595 break;
3596 case 14:
3597 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3598 break;
3599 }
Eric Anholtbad720f2009-10-22 16:11:14 -07003600 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003601 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3602 } else {
3603 if (is_lvds) {
3604 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3605 } else {
3606 if (clock.p1 == 2)
3607 dpll |= PLL_P1_DIVIDE_BY_TWO;
3608 else
3609 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3610 if (clock.p2 == 4)
3611 dpll |= PLL_P2_DIVIDE_BY_4;
3612 }
3613 }
3614
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003615 if (is_sdvo && is_tv)
3616 dpll |= PLL_REF_INPUT_TVCLKINBC;
3617 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08003618 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003619 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08003620 dpll |= 3;
Eric Anholtc751ce42010-03-25 11:48:48 -07003621 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08003623 else
3624 dpll |= PLL_REF_INPUT_DREFCLK;
3625
3626 /* setup pipeconf */
3627 pipeconf = I915_READ(pipeconf_reg);
3628
3629 /* Set up the display plane register */
3630 dspcntr = DISPPLANE_GAMMA_ENABLE;
3631
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003632 /* Ironlake's plane is forced to pipe, bit 24 is to
Zhenyu Wang2c072452009-06-05 15:38:42 +08003633 enable color space conversion */
Eric Anholtbad720f2009-10-22 16:11:14 -07003634 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003635 if (pipe == 0)
Jesse Barnes80824002009-09-10 15:28:06 -07003636 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003637 else
3638 dspcntr |= DISPPLANE_SEL_PIPE_B;
3639 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003640
3641 if (pipe == 0 && !IS_I965G(dev)) {
3642 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3643 * core speed.
3644 *
3645 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3646 * pipe == 0 check?
3647 */
Jesse Barnese70236a2009-09-21 10:42:27 -07003648 if (mode->clock >
3649 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
Jesse Barnes79e53942008-11-07 14:24:08 -08003650 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3651 else
3652 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3653 }
3654
Jesse Barnes79e53942008-11-07 14:24:08 -08003655 /* Disable the panel fitter if it was on our pipe */
Eric Anholtbad720f2009-10-22 16:11:14 -07003656 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08003657 I915_WRITE(PFIT_CONTROL, 0);
3658
Zhao Yakui28c97732009-10-09 11:39:41 +08003659 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08003660 drm_mode_debug_printmodeline(mode);
3661
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003662 /* assign to Ironlake registers */
Eric Anholtbad720f2009-10-22 16:11:14 -07003663 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003664 fp_reg = pch_fp_reg;
3665 dpll_reg = pch_dpll_reg;
3666 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003667
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003668 if (is_edp) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003669 ironlake_disable_pll_edp(crtc);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003670 } else if ((dpll & DPLL_VCO_ENABLE)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003671 I915_WRITE(fp_reg, fp);
3672 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3673 I915_READ(dpll_reg);
3674 udelay(150);
3675 }
3676
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003677 /* enable transcoder DPLL */
3678 if (HAS_PCH_CPT(dev)) {
3679 temp = I915_READ(PCH_DPLL_SEL);
3680 if (trans_dpll_sel == 0)
3681 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3682 else
3683 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3684 I915_WRITE(PCH_DPLL_SEL, temp);
3685 I915_READ(PCH_DPLL_SEL);
3686 udelay(150);
3687 }
3688
Jesse Barnes79e53942008-11-07 14:24:08 -08003689 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3690 * This is an exception to the general rule that mode_set doesn't turn
3691 * things on.
3692 */
3693 if (is_lvds) {
Zhenyu Wang541998a2009-06-05 15:38:44 +08003694 u32 lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08003695
Eric Anholtbad720f2009-10-22 16:11:14 -07003696 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang541998a2009-06-05 15:38:44 +08003697 lvds_reg = PCH_LVDS;
3698
3699 lvds = I915_READ(lvds_reg);
Adam Jackson0f3ee802010-03-31 11:41:51 -04003700 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08003701 if (pipe == 1) {
3702 if (HAS_PCH_CPT(dev))
3703 lvds |= PORT_TRANS_B_SEL_CPT;
3704 else
3705 lvds |= LVDS_PIPEB_SELECT;
3706 } else {
3707 if (HAS_PCH_CPT(dev))
3708 lvds &= ~PORT_TRANS_SEL_MASK;
3709 else
3710 lvds &= ~LVDS_PIPEB_SELECT;
3711 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08003712 /* set the corresponsding LVDS_BORDER bit */
3713 lvds |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08003714 /* Set the B0-B3 data pairs corresponding to whether we're going to
3715 * set the DPLLs for dual-channel mode or not.
3716 */
3717 if (clock.p2 == 7)
3718 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3719 else
3720 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3721
3722 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3723 * appropriately here, but we need to look more thoroughly into how
3724 * panels behave in the two modes.
3725 */
Zhao Yakui898822c2010-01-04 16:29:30 +08003726 /* set the dithering flag */
3727 if (IS_I965G(dev)) {
3728 if (dev_priv->lvds_dither) {
Adam Jackson0a31a442010-04-19 15:57:25 -04003729 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakui898822c2010-01-04 16:29:30 +08003730 pipeconf |= PIPE_ENABLE_DITHER;
Adam Jackson0a31a442010-04-19 15:57:25 -04003731 pipeconf |= PIPE_DITHER_TYPE_ST01;
3732 } else
Zhao Yakui898822c2010-01-04 16:29:30 +08003733 lvds |= LVDS_ENABLE_DITHER;
3734 } else {
Adam Jackson0a31a442010-04-19 15:57:25 -04003735 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakui898822c2010-01-04 16:29:30 +08003736 pipeconf &= ~PIPE_ENABLE_DITHER;
Adam Jackson0a31a442010-04-19 15:57:25 -04003737 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3738 } else
Zhao Yakui898822c2010-01-04 16:29:30 +08003739 lvds &= ~LVDS_ENABLE_DITHER;
3740 }
3741 }
Zhenyu Wang541998a2009-06-05 15:38:44 +08003742 I915_WRITE(lvds_reg, lvds);
3743 I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08003744 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003745 if (is_dp)
3746 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003747 else if (HAS_PCH_SPLIT(dev)) {
3748 /* For non-DP output, clear any trans DP clock recovery setting.*/
3749 if (pipe == 0) {
3750 I915_WRITE(TRANSA_DATA_M1, 0);
3751 I915_WRITE(TRANSA_DATA_N1, 0);
3752 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3753 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3754 } else {
3755 I915_WRITE(TRANSB_DATA_M1, 0);
3756 I915_WRITE(TRANSB_DATA_N1, 0);
3757 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3758 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3759 }
3760 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003761
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003762 if (!is_edp) {
3763 I915_WRITE(fp_reg, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08003764 I915_WRITE(dpll_reg, dpll);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003765 I915_READ(dpll_reg);
3766 /* Wait for the clocks to stabilize. */
3767 udelay(150);
3768
Eric Anholtbad720f2009-10-22 16:11:14 -07003769 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
Zhao Yakuibb66c512009-09-10 15:45:49 +08003770 if (is_sdvo) {
3771 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3772 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003773 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
Zhao Yakuibb66c512009-09-10 15:45:49 +08003774 } else
3775 I915_WRITE(dpll_md_reg, 0);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003776 } else {
3777 /* write it again -- the BIOS does, after all */
3778 I915_WRITE(dpll_reg, dpll);
3779 }
3780 I915_READ(dpll_reg);
3781 /* Wait for the clocks to stabilize. */
3782 udelay(150);
Jesse Barnes79e53942008-11-07 14:24:08 -08003783 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003784
Jesse Barnes652c3932009-08-17 13:31:43 -07003785 if (is_lvds && has_reduced_clock && i915_powersave) {
3786 I915_WRITE(fp_reg + 4, fp2);
3787 intel_crtc->lowfreq_avail = true;
3788 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08003789 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003790 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3791 }
3792 } else {
3793 I915_WRITE(fp_reg + 4, fp);
3794 intel_crtc->lowfreq_avail = false;
3795 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08003796 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07003797 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3798 }
3799 }
3800
Krzysztof Halasa734b4152010-05-25 18:41:46 +02003801 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3802 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3803 /* the chip adds 2 halflines automatically */
3804 adjusted_mode->crtc_vdisplay -= 1;
3805 adjusted_mode->crtc_vtotal -= 1;
3806 adjusted_mode->crtc_vblank_start -= 1;
3807 adjusted_mode->crtc_vblank_end -= 1;
3808 adjusted_mode->crtc_vsync_end -= 1;
3809 adjusted_mode->crtc_vsync_start -= 1;
3810 } else
3811 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
3812
Jesse Barnes79e53942008-11-07 14:24:08 -08003813 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3814 ((adjusted_mode->crtc_htotal - 1) << 16));
3815 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3816 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3817 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3818 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3819 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3820 ((adjusted_mode->crtc_vtotal - 1) << 16));
3821 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3822 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3823 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3824 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3825 /* pipesrc and dspsize control the size that is scaled from, which should
3826 * always be the user's requested size.
3827 */
Eric Anholtbad720f2009-10-22 16:11:14 -07003828 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003829 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3830 (mode->hdisplay - 1));
3831 I915_WRITE(dsppos_reg, 0);
3832 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003833 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08003834
Eric Anholtbad720f2009-10-22 16:11:14 -07003835 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003836 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3837 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3838 I915_WRITE(link_m1_reg, m_n.link_m);
3839 I915_WRITE(link_n1_reg, m_n.link_n);
3840
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003841 if (is_edp) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003842 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003843 } else {
3844 /* enable FDI RX PLL too */
3845 temp = I915_READ(fdi_rx_reg);
3846 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003847 I915_READ(fdi_rx_reg);
3848 udelay(200);
3849
3850 /* enable FDI TX PLL too */
3851 temp = I915_READ(fdi_tx_reg);
3852 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3853 I915_READ(fdi_tx_reg);
3854
3855 /* enable FDI RX PCDCLK */
3856 temp = I915_READ(fdi_rx_reg);
3857 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3858 I915_READ(fdi_rx_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003859 udelay(200);
3860 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003861 }
3862
Jesse Barnes79e53942008-11-07 14:24:08 -08003863 I915_WRITE(pipeconf_reg, pipeconf);
3864 I915_READ(pipeconf_reg);
3865
3866 intel_wait_for_vblank(dev);
3867
Eric Anholtc2416fc2009-11-05 15:30:35 -08003868 if (IS_IRONLAKE(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08003869 /* enable address swizzle for tiling buffer */
3870 temp = I915_READ(DISP_ARB_CTL);
3871 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3872 }
3873
Jesse Barnes79e53942008-11-07 14:24:08 -08003874 I915_WRITE(dspcntr_reg, dspcntr);
3875
3876 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003877 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003878
Jesse Barnes74dff282009-09-14 15:39:40 -07003879 if ((IS_I965G(dev) || plane == 0))
3880 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnese70236a2009-09-21 10:42:27 -07003881
Shaohua Li7662c8b2009-06-26 11:23:55 +08003882 intel_update_watermarks(dev);
3883
Jesse Barnes79e53942008-11-07 14:24:08 -08003884 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003885
Chris Wilson1f803ee2009-06-06 09:45:59 +01003886 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08003887}
3888
3889/** Loads the palette/gamma unit for the CRTC with the prepared values */
3890void intel_crtc_load_lut(struct drm_crtc *crtc)
3891{
3892 struct drm_device *dev = crtc->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3896 int i;
3897
3898 /* The clocks have to be on to load the palette. */
3899 if (!crtc->enabled)
3900 return;
3901
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003902 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07003903 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003904 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3905 LGC_PALETTE_B;
3906
Jesse Barnes79e53942008-11-07 14:24:08 -08003907 for (i = 0; i < 256; i++) {
3908 I915_WRITE(palreg + 4 * i,
3909 (intel_crtc->lut_r[i] << 16) |
3910 (intel_crtc->lut_g[i] << 8) |
3911 intel_crtc->lut_b[i]);
3912 }
3913}
3914
3915static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3916 struct drm_file *file_priv,
3917 uint32_t handle,
3918 uint32_t width, uint32_t height)
3919{
3920 struct drm_device *dev = crtc->dev;
3921 struct drm_i915_private *dev_priv = dev->dev_private;
3922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3923 struct drm_gem_object *bo;
3924 struct drm_i915_gem_object *obj_priv;
3925 int pipe = intel_crtc->pipe;
3926 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3927 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
Jesse Barnes14b60392009-05-20 16:47:08 -04003928 uint32_t temp = I915_READ(control);
Jesse Barnes79e53942008-11-07 14:24:08 -08003929 size_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003930 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08003931
Zhao Yakui28c97732009-10-09 11:39:41 +08003932 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08003933
3934 /* if we want to turn off the cursor ignore width and height */
3935 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08003936 DRM_DEBUG_KMS("cursor off\n");
Jesse Barnes14b60392009-05-20 16:47:08 -04003937 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3938 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3939 temp |= CURSOR_MODE_DISABLE;
3940 } else {
3941 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3942 }
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003943 addr = 0;
3944 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10003945 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003946 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08003947 }
3948
3949 /* Currently we only support 64x64 cursors */
3950 if (width != 64 || height != 64) {
3951 DRM_ERROR("we currently only support 64x64 cursors\n");
3952 return -EINVAL;
3953 }
3954
3955 bo = drm_gem_object_lookup(dev, file_priv, handle);
3956 if (!bo)
3957 return -ENOENT;
3958
Daniel Vetter23010e42010-03-08 13:35:02 +01003959 obj_priv = to_intel_bo(bo);
Jesse Barnes79e53942008-11-07 14:24:08 -08003960
3961 if (bo->size < width * height * 4) {
3962 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10003963 ret = -ENOMEM;
3964 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08003965 }
3966
Dave Airlie71acb5e2008-12-30 20:31:46 +10003967 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003968 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05003969 if (!dev_priv->info->cursor_needs_physical) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10003970 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3971 if (ret) {
3972 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003973 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003974 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003975 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003976 } else {
3977 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3978 if (ret) {
3979 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05003980 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10003981 }
3982 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003983 }
3984
Jesse Barnes14b60392009-05-20 16:47:08 -04003985 if (!IS_I9XX(dev))
3986 I915_WRITE(CURSIZE, (height << 12) | width);
3987
3988 /* Hooray for CUR*CNTR differences */
3989 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3990 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3991 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3992 temp |= (pipe << 28); /* Connect to correct pipe */
3993 } else {
3994 temp &= ~(CURSOR_FORMAT_MASK);
3995 temp |= CURSOR_ENABLE;
3996 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3997 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003998
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05003999 finish:
Jesse Barnes79e53942008-11-07 14:24:08 -08004000 I915_WRITE(control, temp);
4001 I915_WRITE(base, addr);
4002
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004003 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05004004 if (dev_priv->info->cursor_needs_physical) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10004005 if (intel_crtc->cursor_bo != bo)
4006 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4007 } else
4008 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004009 drm_gem_object_unreference(intel_crtc->cursor_bo);
4010 }
Jesse Barnes80824002009-09-10 15:28:06 -07004011
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004012 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004013
4014 intel_crtc->cursor_addr = addr;
4015 intel_crtc->cursor_bo = bo;
4016
Jesse Barnes79e53942008-11-07 14:24:08 -08004017 return 0;
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004018fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10004019 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00004020fail:
4021 drm_gem_object_unreference_unlocked(bo);
Dave Airlie34b8686e2009-01-15 14:03:07 +10004022 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004023}
4024
4025static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4026{
4027 struct drm_device *dev = crtc->dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07004030 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08004031 int pipe = intel_crtc->pipe;
4032 uint32_t temp = 0;
4033 uint32_t adder;
4034
Jesse Barnes652c3932009-08-17 13:31:43 -07004035 if (crtc->fb) {
4036 intel_fb = to_intel_framebuffer(crtc->fb);
4037 intel_mark_busy(dev, intel_fb->obj);
4038 }
4039
Jesse Barnes79e53942008-11-07 14:24:08 -08004040 if (x < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07004041 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08004042 x = -x;
4043 }
4044 if (y < 0) {
Keith Packard2245fda2009-05-30 20:42:29 -07004045 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08004046 y = -y;
4047 }
4048
Keith Packard2245fda2009-05-30 20:42:29 -07004049 temp |= x << CURSOR_X_SHIFT;
4050 temp |= y << CURSOR_Y_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08004051
4052 adder = intel_crtc->cursor_addr;
4053 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
4054 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
4055
4056 return 0;
4057}
4058
4059/** Sets the color ramps on behalf of RandR */
4060void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4061 u16 blue, int regno)
4062{
4063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4064
4065 intel_crtc->lut_r[regno] = red >> 8;
4066 intel_crtc->lut_g[regno] = green >> 8;
4067 intel_crtc->lut_b[regno] = blue >> 8;
4068}
4069
Dave Airlieb8c00ac2009-10-06 13:54:01 +10004070void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4071 u16 *blue, int regno)
4072{
4073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4074
4075 *red = intel_crtc->lut_r[regno] << 8;
4076 *green = intel_crtc->lut_g[regno] << 8;
4077 *blue = intel_crtc->lut_b[regno] << 8;
4078}
4079
Jesse Barnes79e53942008-11-07 14:24:08 -08004080static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4081 u16 *blue, uint32_t size)
4082{
4083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4084 int i;
4085
4086 if (size != 256)
4087 return;
4088
4089 for (i = 0; i < 256; i++) {
4090 intel_crtc->lut_r[i] = red[i] >> 8;
4091 intel_crtc->lut_g[i] = green[i] >> 8;
4092 intel_crtc->lut_b[i] = blue[i] >> 8;
4093 }
4094
4095 intel_crtc_load_lut(crtc);
4096}
4097
4098/**
4099 * Get a pipe with a simple mode set on it for doing load-based monitor
4100 * detection.
4101 *
4102 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07004103 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08004104 *
Eric Anholtc751ce42010-03-25 11:48:48 -07004105 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08004106 * configured for it. In the future, it could choose to temporarily disable
4107 * some outputs to free up a pipe for its use.
4108 *
4109 * \return crtc, or NULL if no pipes are available.
4110 */
4111
4112/* VESA 640x480x72Hz mode to set on the pipe */
4113static struct drm_display_mode load_detect_mode = {
4114 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4115 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4116};
4117
Eric Anholt21d40d32010-03-25 11:11:14 -07004118struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004119 struct drm_connector *connector,
Jesse Barnes79e53942008-11-07 14:24:08 -08004120 struct drm_display_mode *mode,
4121 int *dpms_mode)
4122{
4123 struct intel_crtc *intel_crtc;
4124 struct drm_crtc *possible_crtc;
4125 struct drm_crtc *supported_crtc =NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07004126 struct drm_encoder *encoder = &intel_encoder->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08004127 struct drm_crtc *crtc = NULL;
4128 struct drm_device *dev = encoder->dev;
4129 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4130 struct drm_crtc_helper_funcs *crtc_funcs;
4131 int i = -1;
4132
4133 /*
4134 * Algorithm gets a little messy:
4135 * - if the connector already has an assigned crtc, use it (but make
4136 * sure it's on first)
4137 * - try to find the first unused crtc that can drive this connector,
4138 * and use that if we find one
4139 * - if there are no unused crtcs available, try to use the first
4140 * one we found that supports the connector
4141 */
4142
4143 /* See if we already have a CRTC for this connector */
4144 if (encoder->crtc) {
4145 crtc = encoder->crtc;
4146 /* Make sure the crtc and connector are running */
4147 intel_crtc = to_intel_crtc(crtc);
4148 *dpms_mode = intel_crtc->dpms_mode;
4149 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4150 crtc_funcs = crtc->helper_private;
4151 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4152 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4153 }
4154 return crtc;
4155 }
4156
4157 /* Find an unused one (if possible) */
4158 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4159 i++;
4160 if (!(encoder->possible_crtcs & (1 << i)))
4161 continue;
4162 if (!possible_crtc->enabled) {
4163 crtc = possible_crtc;
4164 break;
4165 }
4166 if (!supported_crtc)
4167 supported_crtc = possible_crtc;
4168 }
4169
4170 /*
4171 * If we didn't find an unused CRTC, don't use any.
4172 */
4173 if (!crtc) {
4174 return NULL;
4175 }
4176
4177 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004178 connector->encoder = encoder;
Eric Anholt21d40d32010-03-25 11:11:14 -07004179 intel_encoder->load_detect_temp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004180
4181 intel_crtc = to_intel_crtc(crtc);
4182 *dpms_mode = intel_crtc->dpms_mode;
4183
4184 if (!crtc->enabled) {
4185 if (!mode)
4186 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05004187 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08004188 } else {
4189 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4190 crtc_funcs = crtc->helper_private;
4191 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4192 }
4193
4194 /* Add this connector to the crtc */
4195 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4196 encoder_funcs->commit(encoder);
4197 }
4198 /* let the connector get through one full cycle before testing */
4199 intel_wait_for_vblank(dev);
4200
4201 return crtc;
4202}
4203
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004204void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4205 struct drm_connector *connector, int dpms_mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08004206{
Eric Anholt21d40d32010-03-25 11:11:14 -07004207 struct drm_encoder *encoder = &intel_encoder->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08004208 struct drm_device *dev = encoder->dev;
4209 struct drm_crtc *crtc = encoder->crtc;
4210 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4211 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4212
Eric Anholt21d40d32010-03-25 11:11:14 -07004213 if (intel_encoder->load_detect_temp) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004214 encoder->crtc = NULL;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004215 connector->encoder = NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07004216 intel_encoder->load_detect_temp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004217 crtc->enabled = drm_helper_crtc_in_use(crtc);
4218 drm_helper_disable_unused_functions(dev);
4219 }
4220
Eric Anholtc751ce42010-03-25 11:48:48 -07004221 /* Switch crtc and encoder back off if necessary */
Jesse Barnes79e53942008-11-07 14:24:08 -08004222 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4223 if (encoder->crtc == crtc)
4224 encoder_funcs->dpms(encoder, dpms_mode);
4225 crtc_funcs->dpms(crtc, dpms_mode);
4226 }
4227}
4228
4229/* Returns the clock of the currently programmed mode of the given pipe. */
4230static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4231{
4232 struct drm_i915_private *dev_priv = dev->dev_private;
4233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234 int pipe = intel_crtc->pipe;
4235 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4236 u32 fp;
4237 intel_clock_t clock;
4238
4239 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4240 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4241 else
4242 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4243
4244 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004245 if (IS_PINEVIEW(dev)) {
4246 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4247 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08004248 } else {
4249 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4250 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4251 }
4252
Jesse Barnes79e53942008-11-07 14:24:08 -08004253 if (IS_I9XX(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004254 if (IS_PINEVIEW(dev))
4255 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4256 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08004257 else
4258 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08004259 DPLL_FPA01_P1_POST_DIV_SHIFT);
4260
4261 switch (dpll & DPLL_MODE_MASK) {
4262 case DPLLB_MODE_DAC_SERIAL:
4263 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4264 5 : 10;
4265 break;
4266 case DPLLB_MODE_LVDS:
4267 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4268 7 : 14;
4269 break;
4270 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08004271 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08004272 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4273 return 0;
4274 }
4275
4276 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08004277 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004278 } else {
4279 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4280
4281 if (is_lvds) {
4282 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4283 DPLL_FPA01_P1_POST_DIV_SHIFT);
4284 clock.p2 = 14;
4285
4286 if ((dpll & PLL_REF_INPUT_MASK) ==
4287 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4288 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08004289 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004290 } else
Shaohua Li21778322009-02-23 15:19:16 +08004291 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004292 } else {
4293 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4294 clock.p1 = 2;
4295 else {
4296 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4297 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4298 }
4299 if (dpll & PLL_P2_DIVIDE_BY_4)
4300 clock.p2 = 4;
4301 else
4302 clock.p2 = 2;
4303
Shaohua Li21778322009-02-23 15:19:16 +08004304 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004305 }
4306 }
4307
4308 /* XXX: It would be nice to validate the clocks, but we can't reuse
4309 * i830PllIsValid() because it relies on the xf86_config connector
4310 * configuration being accurate, which it isn't necessarily.
4311 */
4312
4313 return clock.dot;
4314}
4315
4316/** Returns the currently programmed mode of the given pipe. */
4317struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4318 struct drm_crtc *crtc)
4319{
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 int pipe = intel_crtc->pipe;
4323 struct drm_display_mode *mode;
4324 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4325 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4326 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4327 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4328
4329 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4330 if (!mode)
4331 return NULL;
4332
4333 mode->clock = intel_crtc_clock_get(dev, crtc);
4334 mode->hdisplay = (htot & 0xffff) + 1;
4335 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4336 mode->hsync_start = (hsync & 0xffff) + 1;
4337 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4338 mode->vdisplay = (vtot & 0xffff) + 1;
4339 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4340 mode->vsync_start = (vsync & 0xffff) + 1;
4341 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4342
4343 drm_mode_set_name(mode);
4344 drm_mode_set_crtcinfo(mode, 0);
4345
4346 return mode;
4347}
4348
Jesse Barnes652c3932009-08-17 13:31:43 -07004349#define GPU_IDLE_TIMEOUT 500 /* ms */
4350
4351/* When this timer fires, we've been idle for awhile */
4352static void intel_gpu_idle_timer(unsigned long arg)
4353{
4354 struct drm_device *dev = (struct drm_device *)arg;
4355 drm_i915_private_t *dev_priv = dev->dev_private;
4356
Zhao Yakui44d98a62009-10-09 11:39:40 +08004357 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004358
4359 dev_priv->busy = false;
4360
Eric Anholt01dfba92009-09-06 15:18:53 -07004361 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07004362}
4363
Jesse Barnes652c3932009-08-17 13:31:43 -07004364#define CRTC_IDLE_TIMEOUT 1000 /* ms */
4365
4366static void intel_crtc_idle_timer(unsigned long arg)
4367{
4368 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4369 struct drm_crtc *crtc = &intel_crtc->base;
4370 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4371
Zhao Yakui44d98a62009-10-09 11:39:40 +08004372 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004373
4374 intel_crtc->busy = false;
4375
Eric Anholt01dfba92009-09-06 15:18:53 -07004376 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07004377}
4378
4379static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4380{
4381 struct drm_device *dev = crtc->dev;
4382 drm_i915_private_t *dev_priv = dev->dev_private;
4383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4384 int pipe = intel_crtc->pipe;
4385 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4386 int dpll = I915_READ(dpll_reg);
4387
Eric Anholtbad720f2009-10-22 16:11:14 -07004388 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07004389 return;
4390
4391 if (!dev_priv->lvds_downclock_avail)
4392 return;
4393
4394 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08004395 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004396
4397 /* Unlock panel regs */
4398 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4399
4400 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4401 I915_WRITE(dpll_reg, dpll);
4402 dpll = I915_READ(dpll_reg);
4403 intel_wait_for_vblank(dev);
4404 dpll = I915_READ(dpll_reg);
4405 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08004406 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004407
4408 /* ...and lock them again */
4409 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4410 }
4411
4412 /* Schedule downclock */
4413 if (schedule)
4414 mod_timer(&intel_crtc->idle_timer, jiffies +
4415 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4416}
4417
4418static void intel_decrease_pllclock(struct drm_crtc *crtc)
4419{
4420 struct drm_device *dev = crtc->dev;
4421 drm_i915_private_t *dev_priv = dev->dev_private;
4422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423 int pipe = intel_crtc->pipe;
4424 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4425 int dpll = I915_READ(dpll_reg);
4426
Eric Anholtbad720f2009-10-22 16:11:14 -07004427 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07004428 return;
4429
4430 if (!dev_priv->lvds_downclock_avail)
4431 return;
4432
4433 /*
4434 * Since this is called by a timer, we should never get here in
4435 * the manual case.
4436 */
4437 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08004438 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004439
4440 /* Unlock panel regs */
4441 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
4442
4443 dpll |= DISPLAY_RATE_SELECT_FPA1;
4444 I915_WRITE(dpll_reg, dpll);
4445 dpll = I915_READ(dpll_reg);
4446 intel_wait_for_vblank(dev);
4447 dpll = I915_READ(dpll_reg);
4448 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08004449 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004450
4451 /* ...and lock them again */
4452 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4453 }
4454
4455}
4456
4457/**
4458 * intel_idle_update - adjust clocks for idleness
4459 * @work: work struct
4460 *
4461 * Either the GPU or display (or both) went idle. Check the busy status
4462 * here and adjust the CRTC and GPU clocks as necessary.
4463 */
4464static void intel_idle_update(struct work_struct *work)
4465{
4466 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4467 idle_work);
4468 struct drm_device *dev = dev_priv->dev;
4469 struct drm_crtc *crtc;
4470 struct intel_crtc *intel_crtc;
4471
4472 if (!i915_powersave)
4473 return;
4474
4475 mutex_lock(&dev->struct_mutex);
4476
Jesse Barnes7648fa92010-05-20 14:28:11 -07004477 i915_update_gfx_val(dev_priv);
4478
Li Pengee980b82010-01-27 19:01:11 +08004479 if (IS_I945G(dev) || IS_I945GM(dev)) {
4480 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4481 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4482 }
4483
Jesse Barnes652c3932009-08-17 13:31:43 -07004484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4485 /* Skip inactive CRTCs */
4486 if (!crtc->fb)
4487 continue;
4488
4489 intel_crtc = to_intel_crtc(crtc);
4490 if (!intel_crtc->busy)
4491 intel_decrease_pllclock(crtc);
4492 }
4493
4494 mutex_unlock(&dev->struct_mutex);
4495}
4496
4497/**
4498 * intel_mark_busy - mark the GPU and possibly the display busy
4499 * @dev: drm device
4500 * @obj: object we're operating on
4501 *
4502 * Callers can use this function to indicate that the GPU is busy processing
4503 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4504 * buffer), we'll also mark the display as busy, so we know to increase its
4505 * clock frequency.
4506 */
4507void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4508{
4509 drm_i915_private_t *dev_priv = dev->dev_private;
4510 struct drm_crtc *crtc = NULL;
4511 struct intel_framebuffer *intel_fb;
4512 struct intel_crtc *intel_crtc;
4513
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08004514 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4515 return;
4516
Li Peng060e6452010-02-10 01:54:24 +08004517 if (!dev_priv->busy) {
4518 if (IS_I945G(dev) || IS_I945GM(dev)) {
4519 u32 fw_blc_self;
Li Pengee980b82010-01-27 19:01:11 +08004520
Li Peng060e6452010-02-10 01:54:24 +08004521 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4522 fw_blc_self = I915_READ(FW_BLC_SELF);
4523 fw_blc_self &= ~FW_BLC_SELF_EN;
4524 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4525 }
Chris Wilson28cf7982009-11-30 01:08:56 +00004526 dev_priv->busy = true;
Li Peng060e6452010-02-10 01:54:24 +08004527 } else
Chris Wilson28cf7982009-11-30 01:08:56 +00004528 mod_timer(&dev_priv->idle_timer, jiffies +
4529 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07004530
4531 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4532 if (!crtc->fb)
4533 continue;
4534
4535 intel_crtc = to_intel_crtc(crtc);
4536 intel_fb = to_intel_framebuffer(crtc->fb);
4537 if (intel_fb->obj == obj) {
4538 if (!intel_crtc->busy) {
Li Peng060e6452010-02-10 01:54:24 +08004539 if (IS_I945G(dev) || IS_I945GM(dev)) {
4540 u32 fw_blc_self;
4541
4542 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4543 fw_blc_self = I915_READ(FW_BLC_SELF);
4544 fw_blc_self &= ~FW_BLC_SELF_EN;
4545 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4546 }
Jesse Barnes652c3932009-08-17 13:31:43 -07004547 /* Non-busy -> busy, upclock */
4548 intel_increase_pllclock(crtc, true);
4549 intel_crtc->busy = true;
4550 } else {
4551 /* Busy -> busy, put off timer */
4552 mod_timer(&intel_crtc->idle_timer, jiffies +
4553 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4554 }
4555 }
4556 }
4557}
4558
Jesse Barnes79e53942008-11-07 14:24:08 -08004559static void intel_crtc_destroy(struct drm_crtc *crtc)
4560{
4561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562
4563 drm_crtc_cleanup(crtc);
4564 kfree(intel_crtc);
4565}
4566
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004567struct intel_unpin_work {
4568 struct work_struct work;
4569 struct drm_device *dev;
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004570 struct drm_gem_object *old_fb_obj;
4571 struct drm_gem_object *pending_flip_obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004572 struct drm_pending_vblank_event *event;
4573 int pending;
4574};
4575
4576static void intel_unpin_work_fn(struct work_struct *__work)
4577{
4578 struct intel_unpin_work *work =
4579 container_of(__work, struct intel_unpin_work, work);
4580
4581 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004582 i915_gem_object_unpin(work->old_fb_obj);
Jesse Barnes75dfca82010-02-10 15:09:44 -08004583 drm_gem_object_unreference(work->pending_flip_obj);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004584 drm_gem_object_unreference(work->old_fb_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004585 mutex_unlock(&work->dev->struct_mutex);
4586 kfree(work);
4587}
4588
4589void intel_finish_page_flip(struct drm_device *dev, int pipe)
4590{
4591 drm_i915_private_t *dev_priv = dev->dev_private;
4592 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4594 struct intel_unpin_work *work;
4595 struct drm_i915_gem_object *obj_priv;
4596 struct drm_pending_vblank_event *e;
4597 struct timeval now;
4598 unsigned long flags;
4599
4600 /* Ignore early vblank irqs */
4601 if (intel_crtc == NULL)
4602 return;
4603
4604 spin_lock_irqsave(&dev->event_lock, flags);
4605 work = intel_crtc->unpin_work;
4606 if (work == NULL || !work->pending) {
4607 spin_unlock_irqrestore(&dev->event_lock, flags);
4608 return;
4609 }
4610
4611 intel_crtc->unpin_work = NULL;
4612 drm_vblank_put(dev, intel_crtc->pipe);
4613
4614 if (work->event) {
4615 e = work->event;
4616 do_gettimeofday(&now);
4617 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4618 e->event.tv_sec = now.tv_sec;
4619 e->event.tv_usec = now.tv_usec;
4620 list_add_tail(&e->base.link,
4621 &e->base.file_priv->event_list);
4622 wake_up_interruptible(&e->base.file_priv->event_wait);
4623 }
4624
4625 spin_unlock_irqrestore(&dev->event_lock, flags);
4626
Daniel Vetter23010e42010-03-08 13:35:02 +01004627 obj_priv = to_intel_bo(work->pending_flip_obj);
Jesse Barnesde3f4402010-01-14 13:18:02 -08004628
4629 /* Initial scanout buffer will have a 0 pending flip count */
4630 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4631 atomic_dec_and_test(&obj_priv->pending_flip))
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004632 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4633 schedule_work(&work->work);
4634}
4635
4636void intel_prepare_page_flip(struct drm_device *dev, int plane)
4637{
4638 drm_i915_private_t *dev_priv = dev->dev_private;
4639 struct intel_crtc *intel_crtc =
4640 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4641 unsigned long flags;
4642
4643 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08004644 if (intel_crtc->unpin_work) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004645 intel_crtc->unpin_work->pending = 1;
Jesse Barnesde3f4402010-01-14 13:18:02 -08004646 } else {
4647 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4648 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004649 spin_unlock_irqrestore(&dev->event_lock, flags);
4650}
4651
4652static int intel_crtc_page_flip(struct drm_crtc *crtc,
4653 struct drm_framebuffer *fb,
4654 struct drm_pending_vblank_event *event)
4655{
4656 struct drm_device *dev = crtc->dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_framebuffer *intel_fb;
4659 struct drm_i915_gem_object *obj_priv;
4660 struct drm_gem_object *obj;
4661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 struct intel_unpin_work *work;
4663 unsigned long flags;
Zhenyu Wangaacef092010-02-09 09:46:20 +08004664 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4665 int ret, pipesrc;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004666
4667 work = kzalloc(sizeof *work, GFP_KERNEL);
4668 if (work == NULL)
4669 return -ENOMEM;
4670
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004671 work->event = event;
4672 work->dev = crtc->dev;
4673 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004674 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004675 INIT_WORK(&work->work, intel_unpin_work_fn);
4676
4677 /* We borrow the event spin lock for protecting unpin_work */
4678 spin_lock_irqsave(&dev->event_lock, flags);
4679 if (intel_crtc->unpin_work) {
4680 spin_unlock_irqrestore(&dev->event_lock, flags);
4681 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01004682
4683 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004684 return -EBUSY;
4685 }
4686 intel_crtc->unpin_work = work;
4687 spin_unlock_irqrestore(&dev->event_lock, flags);
4688
4689 intel_fb = to_intel_framebuffer(fb);
4690 obj = intel_fb->obj;
4691
Chris Wilson468f0b42010-05-27 13:18:13 +01004692 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004693 ret = intel_pin_and_fence_fb_obj(dev, obj);
4694 if (ret != 0) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004695 mutex_unlock(&dev->struct_mutex);
Chris Wilson468f0b42010-05-27 13:18:13 +01004696
4697 spin_lock_irqsave(&dev->event_lock, flags);
4698 intel_crtc->unpin_work = NULL;
4699 spin_unlock_irqrestore(&dev->event_lock, flags);
4700
4701 kfree(work);
4702
4703 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4704 to_intel_bo(obj));
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004705 return ret;
4706 }
4707
Jesse Barnes75dfca82010-02-10 15:09:44 -08004708 /* Reference the objects for the scheduled work. */
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004709 drm_gem_object_reference(work->old_fb_obj);
Jesse Barnes75dfca82010-02-10 15:09:44 -08004710 drm_gem_object_reference(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004711
4712 crtc->fb = fb;
4713 i915_gem_object_flush_write_domain(obj);
4714 drm_vblank_get(dev, intel_crtc->pipe);
Daniel Vetter23010e42010-03-08 13:35:02 +01004715 obj_priv = to_intel_bo(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004716 atomic_inc(&obj_priv->pending_flip);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004717 work->pending_flip_obj = obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004718
4719 BEGIN_LP_RING(4);
4720 OUT_RING(MI_DISPLAY_FLIP |
4721 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4722 OUT_RING(fb->pitch);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08004723 if (IS_I965G(dev)) {
4724 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
Zhenyu Wangaacef092010-02-09 09:46:20 +08004725 pipesrc = I915_READ(pipesrc_reg);
4726 OUT_RING(pipesrc & 0x0fff0fff);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08004727 } else {
4728 OUT_RING(obj_priv->gtt_offset);
4729 OUT_RING(MI_NOOP);
4730 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004731 ADVANCE_LP_RING();
4732
4733 mutex_unlock(&dev->struct_mutex);
4734
4735 return 0;
4736}
4737
Jesse Barnes79e53942008-11-07 14:24:08 -08004738static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4739 .dpms = intel_crtc_dpms,
4740 .mode_fixup = intel_crtc_mode_fixup,
4741 .mode_set = intel_crtc_mode_set,
4742 .mode_set_base = intel_pipe_set_base,
4743 .prepare = intel_crtc_prepare,
4744 .commit = intel_crtc_commit,
Dave Airlie068143d2009-10-05 09:58:02 +10004745 .load_lut = intel_crtc_load_lut,
Jesse Barnes79e53942008-11-07 14:24:08 -08004746};
4747
4748static const struct drm_crtc_funcs intel_crtc_funcs = {
4749 .cursor_set = intel_crtc_cursor_set,
4750 .cursor_move = intel_crtc_cursor_move,
4751 .gamma_set = intel_crtc_gamma_set,
4752 .set_config = drm_crtc_helper_set_config,
4753 .destroy = intel_crtc_destroy,
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004754 .page_flip = intel_crtc_page_flip,
Jesse Barnes79e53942008-11-07 14:24:08 -08004755};
4756
4757
Hannes Ederb358d0a2008-12-18 21:18:47 +01004758static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08004759{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08004760 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08004761 struct intel_crtc *intel_crtc;
4762 int i;
4763
4764 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4765 if (intel_crtc == NULL)
4766 return;
4767
4768 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4769
4770 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4771 intel_crtc->pipe = pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004772 intel_crtc->plane = pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08004773 for (i = 0; i < 256; i++) {
4774 intel_crtc->lut_r[i] = i;
4775 intel_crtc->lut_g[i] = i;
4776 intel_crtc->lut_b[i] = i;
4777 }
4778
Jesse Barnes80824002009-09-10 15:28:06 -07004779 /* Swap pipes & planes for FBC on pre-965 */
4780 intel_crtc->pipe = pipe;
4781 intel_crtc->plane = pipe;
4782 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004783 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07004784 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4785 }
4786
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08004787 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4788 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4789 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4790 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4791
Jesse Barnes79e53942008-11-07 14:24:08 -08004792 intel_crtc->cursor_addr = 0;
4793 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4794 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4795
Jesse Barnes652c3932009-08-17 13:31:43 -07004796 intel_crtc->busy = false;
4797
4798 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4799 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004800}
4801
Carl Worth08d7b3d2009-04-29 14:43:54 -07004802int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4803 struct drm_file *file_priv)
4804{
4805 drm_i915_private_t *dev_priv = dev->dev_private;
4806 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02004807 struct drm_mode_object *drmmode_obj;
4808 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07004809
4810 if (!dev_priv) {
4811 DRM_ERROR("called with no initialization\n");
4812 return -EINVAL;
4813 }
4814
Daniel Vetterc05422d2009-08-11 16:05:30 +02004815 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4816 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07004817
Daniel Vetterc05422d2009-08-11 16:05:30 +02004818 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07004819 DRM_ERROR("no such CRTC id\n");
4820 return -EINVAL;
4821 }
4822
Daniel Vetterc05422d2009-08-11 16:05:30 +02004823 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4824 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07004825
Daniel Vetterc05422d2009-08-11 16:05:30 +02004826 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07004827}
4828
Jesse Barnes79e53942008-11-07 14:24:08 -08004829struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4830{
4831 struct drm_crtc *crtc = NULL;
4832
4833 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835 if (intel_crtc->pipe == pipe)
4836 break;
4837 }
4838 return crtc;
4839}
4840
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004841static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08004842{
4843 int index_mask = 0;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004844 struct drm_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004845 int entry = 0;
4846
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4848 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Eric Anholt21d40d32010-03-25 11:11:14 -07004849 if (type_mask & intel_encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08004850 index_mask |= (1 << entry);
4851 entry++;
4852 }
4853 return index_mask;
4854}
4855
4856
4857static void intel_setup_outputs(struct drm_device *dev)
4858{
Eric Anholt725e30a2009-01-22 13:01:02 -08004859 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004860 struct drm_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004861
4862 intel_crt_init(dev);
4863
4864 /* Set up integrated LVDS */
Zhenyu Wang541998a2009-06-05 15:38:44 +08004865 if (IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004866 intel_lvds_init(dev);
4867
Eric Anholtbad720f2009-10-22 16:11:14 -07004868 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08004869 int found;
4870
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004871 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4872 intel_dp_init(dev, DP_A);
4873
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08004874 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08004875 /* PCH SDVOB multiplex with HDMIB */
4876 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08004877 if (!found)
4878 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004879 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4880 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08004881 }
4882
4883 if (I915_READ(HDMIC) & PORT_DETECTED)
4884 intel_hdmi_init(dev, HDMIC);
4885
4886 if (I915_READ(HDMID) & PORT_DETECTED)
4887 intel_hdmi_init(dev, HDMID);
4888
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004889 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4890 intel_dp_init(dev, PCH_DP_C);
4891
4892 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4893 intel_dp_init(dev, PCH_DP_D);
4894
Zhenyu Wang103a1962009-11-27 11:44:36 +08004895 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08004896 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08004897
Eric Anholt725e30a2009-01-22 13:01:02 -08004898 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004899 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08004900 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004901 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4902 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08004903 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004904 }
Ma Ling27185ae2009-08-24 13:50:23 +08004905
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004906 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4907 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004908 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004909 }
Eric Anholt725e30a2009-01-22 13:01:02 -08004910 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04004911
4912 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04004913
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004914 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4915 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08004916 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004917 }
Ma Ling27185ae2009-08-24 13:50:23 +08004918
4919 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4920
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004921 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4922 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08004923 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004924 }
4925 if (SUPPORTS_INTEGRATED_DP(dev)) {
4926 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004927 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004928 }
Eric Anholt725e30a2009-01-22 13:01:02 -08004929 }
Ma Ling27185ae2009-08-24 13:50:23 +08004930
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004931 if (SUPPORTS_INTEGRATED_DP(dev) &&
4932 (I915_READ(DP_D) & DP_DETECTED)) {
4933 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004934 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08004935 }
Eric Anholtbad720f2009-10-22 16:11:14 -07004936 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004937 intel_dvo_init(dev);
4938
Zhenyu Wang103a1962009-11-27 11:44:36 +08004939 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004940 intel_tv_init(dev);
4941
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004942 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4943 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08004944
Eric Anholt21d40d32010-03-25 11:11:14 -07004945 encoder->possible_crtcs = intel_encoder->crtc_mask;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08004946 encoder->possible_clones = intel_encoder_clones(dev,
Eric Anholt21d40d32010-03-25 11:11:14 -07004947 intel_encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08004948 }
4949}
4950
4951static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4952{
4953 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08004954
4955 drm_framebuffer_cleanup(fb);
Luca Barbieribc9025b2010-02-09 05:49:12 +00004956 drm_gem_object_unreference_unlocked(intel_fb->obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08004957
4958 kfree(intel_fb);
4959}
4960
4961static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4962 struct drm_file *file_priv,
4963 unsigned int *handle)
4964{
4965 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4966 struct drm_gem_object *object = intel_fb->obj;
4967
4968 return drm_gem_handle_create(file_priv, object, handle);
4969}
4970
4971static const struct drm_framebuffer_funcs intel_fb_funcs = {
4972 .destroy = intel_user_framebuffer_destroy,
4973 .create_handle = intel_user_framebuffer_create_handle,
4974};
4975
Dave Airlie38651672010-03-30 05:34:13 +00004976int intel_framebuffer_init(struct drm_device *dev,
4977 struct intel_framebuffer *intel_fb,
4978 struct drm_mode_fb_cmd *mode_cmd,
4979 struct drm_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08004980{
Jesse Barnes79e53942008-11-07 14:24:08 -08004981 int ret;
4982
Jesse Barnes79e53942008-11-07 14:24:08 -08004983 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4984 if (ret) {
4985 DRM_ERROR("framebuffer init failed %d\n", ret);
4986 return ret;
4987 }
4988
4989 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08004990 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08004991 return 0;
4992}
4993
Jesse Barnes79e53942008-11-07 14:24:08 -08004994static struct drm_framebuffer *
4995intel_user_framebuffer_create(struct drm_device *dev,
4996 struct drm_file *filp,
4997 struct drm_mode_fb_cmd *mode_cmd)
4998{
4999 struct drm_gem_object *obj;
Dave Airlie38651672010-03-30 05:34:13 +00005000 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08005001 int ret;
5002
5003 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5004 if (!obj)
5005 return NULL;
5006
Dave Airlie38651672010-03-30 05:34:13 +00005007 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5008 if (!intel_fb)
5009 return NULL;
5010
5011 ret = intel_framebuffer_init(dev, intel_fb,
5012 mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08005013 if (ret) {
Luca Barbieribc9025b2010-02-09 05:49:12 +00005014 drm_gem_object_unreference_unlocked(obj);
Dave Airlie38651672010-03-30 05:34:13 +00005015 kfree(intel_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005016 return NULL;
5017 }
5018
Dave Airlie38651672010-03-30 05:34:13 +00005019 return &intel_fb->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005020}
5021
Jesse Barnes79e53942008-11-07 14:24:08 -08005022static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08005023 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00005024 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08005025};
5026
Chris Wilson9ea8d052010-01-04 18:57:56 +00005027static struct drm_gem_object *
5028intel_alloc_power_context(struct drm_device *dev)
5029{
5030 struct drm_gem_object *pwrctx;
5031 int ret;
5032
Daniel Vetterac52bc52010-04-09 19:05:06 +00005033 pwrctx = i915_gem_alloc_object(dev, 4096);
Chris Wilson9ea8d052010-01-04 18:57:56 +00005034 if (!pwrctx) {
5035 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5036 return NULL;
5037 }
5038
5039 mutex_lock(&dev->struct_mutex);
5040 ret = i915_gem_object_pin(pwrctx, 4096);
5041 if (ret) {
5042 DRM_ERROR("failed to pin power context: %d\n", ret);
5043 goto err_unref;
5044 }
5045
5046 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5047 if (ret) {
5048 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5049 goto err_unpin;
5050 }
5051 mutex_unlock(&dev->struct_mutex);
5052
5053 return pwrctx;
5054
5055err_unpin:
5056 i915_gem_object_unpin(pwrctx);
5057err_unref:
5058 drm_gem_object_unreference(pwrctx);
5059 mutex_unlock(&dev->struct_mutex);
5060 return NULL;
5061}
5062
Jesse Barnes7648fa92010-05-20 14:28:11 -07005063bool ironlake_set_drps(struct drm_device *dev, u8 val)
5064{
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066 u16 rgvswctl;
5067
5068 rgvswctl = I915_READ16(MEMSWCTL);
5069 if (rgvswctl & MEMCTL_CMD_STS) {
5070 DRM_DEBUG("gpu busy, RCS change rejected\n");
5071 return false; /* still busy with another command */
5072 }
5073
5074 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5075 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5076 I915_WRITE16(MEMSWCTL, rgvswctl);
5077 POSTING_READ16(MEMSWCTL);
5078
5079 rgvswctl |= MEMCTL_CMD_STS;
5080 I915_WRITE16(MEMSWCTL, rgvswctl);
5081
5082 return true;
5083}
5084
Jesse Barnesf97108d2010-01-29 11:27:07 -08005085void ironlake_enable_drps(struct drm_device *dev)
5086{
5087 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005088 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005089 u8 fmax, fmin, fstart, vstart;
5090 int i = 0;
5091
5092 /* 100ms RC evaluation intervals */
5093 I915_WRITE(RCUPEI, 100000);
5094 I915_WRITE(RCDNEI, 100000);
5095
5096 /* Set max/min thresholds to 90ms and 80ms respectively */
5097 I915_WRITE(RCBMAXAVG, 90000);
5098 I915_WRITE(RCBMINAVG, 80000);
5099
5100 I915_WRITE(MEMIHYST, 1);
5101
5102 /* Set up min, max, and cur for interrupt handling */
5103 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5104 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5105 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5106 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005107 fstart = fmax;
5108
Jesse Barnesf97108d2010-01-29 11:27:07 -08005109 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5110 PXVFREQ_PX_SHIFT;
5111
Jesse Barnes7648fa92010-05-20 14:28:11 -07005112 dev_priv->fmax = fstart; /* IPS callback will increase this */
5113 dev_priv->fstart = fstart;
5114
5115 dev_priv->max_delay = fmax;
Jesse Barnesf97108d2010-01-29 11:27:07 -08005116 dev_priv->min_delay = fmin;
5117 dev_priv->cur_delay = fstart;
5118
Jesse Barnes7648fa92010-05-20 14:28:11 -07005119 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5120 fstart);
5121
Jesse Barnesf97108d2010-01-29 11:27:07 -08005122 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5123
5124 /*
5125 * Interrupts will be enabled in ironlake_irq_postinstall
5126 */
5127
5128 I915_WRITE(VIDSTART, vstart);
5129 POSTING_READ(VIDSTART);
5130
5131 rgvmodectl |= MEMMODE_SWMODE_EN;
5132 I915_WRITE(MEMMODECTL, rgvmodectl);
5133
5134 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5135 if (i++ > 100) {
5136 DRM_ERROR("stuck trying to change perf mode\n");
5137 break;
5138 }
5139 msleep(1);
5140 }
5141 msleep(1);
5142
Jesse Barnes7648fa92010-05-20 14:28:11 -07005143 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005144
Jesse Barnes7648fa92010-05-20 14:28:11 -07005145 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5146 I915_READ(0x112e0);
5147 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5148 dev_priv->last_count2 = I915_READ(0x112f4);
5149 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005150}
5151
5152void ironlake_disable_drps(struct drm_device *dev)
5153{
5154 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005155 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005156
5157 /* Ack interrupts, disable EFC interrupt */
5158 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5159 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5160 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5161 I915_WRITE(DEIIR, DE_PCU_EVENT);
5162 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5163
5164 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07005165 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005166 msleep(1);
5167 rgvswctl |= MEMCTL_CMD_STS;
5168 I915_WRITE(MEMSWCTL, rgvswctl);
5169 msleep(1);
5170
5171}
5172
Jesse Barnes7648fa92010-05-20 14:28:11 -07005173static unsigned long intel_pxfreq(u32 vidfreq)
5174{
5175 unsigned long freq;
5176 int div = (vidfreq & 0x3f0000) >> 16;
5177 int post = (vidfreq & 0x3000) >> 12;
5178 int pre = (vidfreq & 0x7);
5179
5180 if (!pre)
5181 return 0;
5182
5183 freq = ((div * 133333) / ((1<<post) * pre));
5184
5185 return freq;
5186}
5187
5188void intel_init_emon(struct drm_device *dev)
5189{
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 u32 lcfuse;
5192 u8 pxw[16];
5193 int i;
5194
5195 /* Disable to program */
5196 I915_WRITE(ECR, 0);
5197 POSTING_READ(ECR);
5198
5199 /* Program energy weights for various events */
5200 I915_WRITE(SDEW, 0x15040d00);
5201 I915_WRITE(CSIEW0, 0x007f0000);
5202 I915_WRITE(CSIEW1, 0x1e220004);
5203 I915_WRITE(CSIEW2, 0x04000004);
5204
5205 for (i = 0; i < 5; i++)
5206 I915_WRITE(PEW + (i * 4), 0);
5207 for (i = 0; i < 3; i++)
5208 I915_WRITE(DEW + (i * 4), 0);
5209
5210 /* Program P-state weights to account for frequency power adjustment */
5211 for (i = 0; i < 16; i++) {
5212 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5213 unsigned long freq = intel_pxfreq(pxvidfreq);
5214 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5215 PXVFREQ_PX_SHIFT;
5216 unsigned long val;
5217
5218 val = vid * vid;
5219 val *= (freq / 1000);
5220 val *= 255;
5221 val /= (127*127*900);
5222 if (val > 0xff)
5223 DRM_ERROR("bad pxval: %ld\n", val);
5224 pxw[i] = val;
5225 }
5226 /* Render standby states get 0 weight */
5227 pxw[14] = 0;
5228 pxw[15] = 0;
5229
5230 for (i = 0; i < 4; i++) {
5231 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5232 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5233 I915_WRITE(PXW + (i * 4), val);
5234 }
5235
5236 /* Adjust magic regs to magic values (more experimental results) */
5237 I915_WRITE(OGW0, 0);
5238 I915_WRITE(OGW1, 0);
5239 I915_WRITE(EG0, 0x00007f00);
5240 I915_WRITE(EG1, 0x0000000e);
5241 I915_WRITE(EG2, 0x000e0000);
5242 I915_WRITE(EG3, 0x68000300);
5243 I915_WRITE(EG4, 0x42000000);
5244 I915_WRITE(EG5, 0x00140031);
5245 I915_WRITE(EG6, 0);
5246 I915_WRITE(EG7, 0);
5247
5248 for (i = 0; i < 8; i++)
5249 I915_WRITE(PXWL + (i * 4), 0);
5250
5251 /* Enable PMON + select events */
5252 I915_WRITE(ECR, 0x80000019);
5253
5254 lcfuse = I915_READ(LCFUSE02);
5255
5256 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5257}
5258
Jesse Barnes652c3932009-08-17 13:31:43 -07005259void intel_init_clock_gating(struct drm_device *dev)
5260{
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262
5263 /*
5264 * Disable clock gating reported to work incorrectly according to the
5265 * specs, but enable as much else as we can.
5266 */
Eric Anholtbad720f2009-10-22 16:11:14 -07005267 if (HAS_PCH_SPLIT(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07005268 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5269
5270 if (IS_IRONLAKE(dev)) {
5271 /* Required for FBC */
5272 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5273 /* Required for CxSR */
5274 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5275
5276 I915_WRITE(PCH_3DCGDIS0,
5277 MARIUNIT_CLOCK_GATE_DISABLE |
5278 SVSMUNIT_CLOCK_GATE_DISABLE);
5279 }
5280
5281 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005282
5283 /*
5284 * According to the spec the following bits should be set in
5285 * order to enable memory self-refresh
5286 * The bit 22/21 of 0x42004
5287 * The bit 5 of 0x42020
5288 * The bit 15 of 0x45000
5289 */
5290 if (IS_IRONLAKE(dev)) {
5291 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5292 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5293 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5294 I915_WRITE(ILK_DSPCLK_GATE,
5295 (I915_READ(ILK_DSPCLK_GATE) |
5296 ILK_DPARB_CLK_GATE));
5297 I915_WRITE(DISP_ARB_CTL,
5298 (I915_READ(DISP_ARB_CTL) |
5299 DISP_FBC_WM_DIS));
5300 }
Zhenyu Wangc03342f2009-09-29 11:01:23 +08005301 return;
5302 } else if (IS_G4X(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07005303 uint32_t dspclk_gate;
5304 I915_WRITE(RENCLK_GATE_D1, 0);
5305 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5306 GS_UNIT_CLOCK_GATE_DISABLE |
5307 CL_UNIT_CLOCK_GATE_DISABLE);
5308 I915_WRITE(RAMCLK_GATE_D, 0);
5309 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5310 OVRUNIT_CLOCK_GATE_DISABLE |
5311 OVCUNIT_CLOCK_GATE_DISABLE;
5312 if (IS_GM45(dev))
5313 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5314 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5315 } else if (IS_I965GM(dev)) {
5316 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5317 I915_WRITE(RENCLK_GATE_D2, 0);
5318 I915_WRITE(DSPCLK_GATE_D, 0);
5319 I915_WRITE(RAMCLK_GATE_D, 0);
5320 I915_WRITE16(DEUC, 0);
5321 } else if (IS_I965G(dev)) {
5322 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5323 I965_RCC_CLOCK_GATE_DISABLE |
5324 I965_RCPB_CLOCK_GATE_DISABLE |
5325 I965_ISC_CLOCK_GATE_DISABLE |
5326 I965_FBC_CLOCK_GATE_DISABLE);
5327 I915_WRITE(RENCLK_GATE_D2, 0);
5328 } else if (IS_I9XX(dev)) {
5329 u32 dstate = I915_READ(D_STATE);
5330
5331 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5332 DSTATE_DOT_CLOCK_GATING;
5333 I915_WRITE(D_STATE, dstate);
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02005334 } else if (IS_I85X(dev) || IS_I865G(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07005335 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5336 } else if (IS_I830(dev)) {
5337 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5338 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005339
5340 /*
5341 * GPU can automatically power down the render unit if given a page
5342 * to save state.
5343 */
Andrew Lutomirski1d3c36ad2009-12-21 10:10:22 -05005344 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00005345 struct drm_i915_gem_object *obj_priv = NULL;
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005346
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005347 if (dev_priv->pwrctx) {
Daniel Vetter23010e42010-03-08 13:35:02 +01005348 obj_priv = to_intel_bo(dev_priv->pwrctx);
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005349 } else {
Chris Wilson9ea8d052010-01-04 18:57:56 +00005350 struct drm_gem_object *pwrctx;
5351
5352 pwrctx = intel_alloc_power_context(dev);
5353 if (pwrctx) {
5354 dev_priv->pwrctx = pwrctx;
Daniel Vetter23010e42010-03-08 13:35:02 +01005355 obj_priv = to_intel_bo(pwrctx);
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005356 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005357 }
5358
Chris Wilson9ea8d052010-01-04 18:57:56 +00005359 if (obj_priv) {
5360 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5361 I915_WRITE(MCHBAR_RENDER_STANDBY,
5362 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5363 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005364 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005365}
5366
Jesse Barnese70236a2009-09-21 10:42:27 -07005367/* Set up chip specific display functions */
5368static void intel_init_display(struct drm_device *dev)
5369{
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371
5372 /* We always want a DPMS function */
Eric Anholtbad720f2009-10-22 16:11:14 -07005373 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005374 dev_priv->display.dpms = ironlake_crtc_dpms;
Jesse Barnese70236a2009-09-21 10:42:27 -07005375 else
5376 dev_priv->display.dpms = i9xx_crtc_dpms;
5377
Adam Jacksonee5382a2010-04-23 11:17:39 -04005378 if (I915_HAS_FBC(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07005379 if (IS_GM45(dev)) {
5380 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5381 dev_priv->display.enable_fbc = g4x_enable_fbc;
5382 dev_priv->display.disable_fbc = g4x_disable_fbc;
Robert Hooker8d06a1e2010-03-19 15:13:27 -04005383 } else if (IS_I965GM(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07005384 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5385 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5386 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5387 }
Jesse Barnes74dff282009-09-14 15:39:40 -07005388 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07005389 }
5390
5391 /* Returns the core display clock speed */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005392 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07005393 dev_priv->display.get_display_clock_speed =
5394 i945_get_display_clock_speed;
5395 else if (IS_I915G(dev))
5396 dev_priv->display.get_display_clock_speed =
5397 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005398 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005399 dev_priv->display.get_display_clock_speed =
5400 i9xx_misc_get_display_clock_speed;
5401 else if (IS_I915GM(dev))
5402 dev_priv->display.get_display_clock_speed =
5403 i915gm_get_display_clock_speed;
5404 else if (IS_I865G(dev))
5405 dev_priv->display.get_display_clock_speed =
5406 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02005407 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005408 dev_priv->display.get_display_clock_speed =
5409 i855_get_display_clock_speed;
5410 else /* 852, 830 */
5411 dev_priv->display.get_display_clock_speed =
5412 i830_get_display_clock_speed;
5413
5414 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005415 if (HAS_PCH_SPLIT(dev)) {
5416 if (IS_IRONLAKE(dev)) {
5417 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5418 dev_priv->display.update_wm = ironlake_update_wm;
5419 else {
5420 DRM_DEBUG_KMS("Failed to get proper latency. "
5421 "Disable CxSR\n");
5422 dev_priv->display.update_wm = NULL;
5423 }
5424 } else
5425 dev_priv->display.update_wm = NULL;
5426 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08005427 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08005428 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08005429 dev_priv->fsb_freq,
5430 dev_priv->mem_freq)) {
5431 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08005432 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08005433 "disabling CxSR\n",
Li Peng95534262010-05-18 18:58:44 +08005434 (dev_priv->is_ddr3 == 1) ? "3": "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08005435 dev_priv->fsb_freq, dev_priv->mem_freq);
5436 /* Disable CxSR and never update its watermark again */
5437 pineview_disable_cxsr(dev);
5438 dev_priv->display.update_wm = NULL;
5439 } else
5440 dev_priv->display.update_wm = pineview_update_wm;
5441 } else if (IS_G4X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005442 dev_priv->display.update_wm = g4x_update_wm;
5443 else if (IS_I965G(dev))
5444 dev_priv->display.update_wm = i965_update_wm;
Adam Jackson8f4695e2010-04-16 18:20:57 -04005445 else if (IS_I9XX(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07005446 dev_priv->display.update_wm = i9xx_update_wm;
5447 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04005448 } else if (IS_I85X(dev)) {
5449 dev_priv->display.update_wm = i9xx_update_wm;
5450 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07005451 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04005452 dev_priv->display.update_wm = i830_update_wm;
5453 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005454 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5455 else
5456 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07005457 }
5458}
5459
Jesse Barnes79e53942008-11-07 14:24:08 -08005460void intel_modeset_init(struct drm_device *dev)
5461{
Jesse Barnes652c3932009-08-17 13:31:43 -07005462 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005463 int num_pipe;
5464 int i;
5465
5466 drm_mode_config_init(dev);
5467
5468 dev->mode_config.min_width = 0;
5469 dev->mode_config.min_height = 0;
5470
5471 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5472
Jesse Barnese70236a2009-09-21 10:42:27 -07005473 intel_init_display(dev);
5474
Jesse Barnes79e53942008-11-07 14:24:08 -08005475 if (IS_I965G(dev)) {
5476 dev->mode_config.max_width = 8192;
5477 dev->mode_config.max_height = 8192;
Keith Packard5e4d6fa2009-07-12 23:53:17 -07005478 } else if (IS_I9XX(dev)) {
5479 dev->mode_config.max_width = 4096;
5480 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08005481 } else {
5482 dev->mode_config.max_width = 2048;
5483 dev->mode_config.max_height = 2048;
5484 }
5485
5486 /* set memory base */
5487 if (IS_I9XX(dev))
5488 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5489 else
5490 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5491
5492 if (IS_MOBILE(dev) || IS_I9XX(dev))
5493 num_pipe = 2;
5494 else
5495 num_pipe = 1;
Zhao Yakui28c97732009-10-09 11:39:41 +08005496 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Jesse Barnes79e53942008-11-07 14:24:08 -08005497 num_pipe, num_pipe > 1 ? "s" : "");
5498
5499 for (i = 0; i < num_pipe; i++) {
5500 intel_crtc_init(dev, i);
5501 }
5502
5503 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07005504
5505 intel_init_clock_gating(dev);
5506
Jesse Barnes7648fa92010-05-20 14:28:11 -07005507 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08005508 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07005509 intel_init_emon(dev);
5510 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08005511
Jesse Barnes652c3932009-08-17 13:31:43 -07005512 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
5513 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
5514 (unsigned long)dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02005515
5516 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08005517}
5518
5519void intel_modeset_cleanup(struct drm_device *dev)
5520{
Jesse Barnes652c3932009-08-17 13:31:43 -07005521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 struct drm_crtc *crtc;
5523 struct intel_crtc *intel_crtc;
5524
5525 mutex_lock(&dev->struct_mutex);
5526
Dave Airlieeb1f8e42010-05-07 06:42:51 +00005527 drm_kms_helper_poll_fini(dev);
Dave Airlie38651672010-03-30 05:34:13 +00005528 intel_fbdev_fini(dev);
5529
Jesse Barnes652c3932009-08-17 13:31:43 -07005530 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5531 /* Skip inactive CRTCs */
5532 if (!crtc->fb)
5533 continue;
5534
5535 intel_crtc = to_intel_crtc(crtc);
5536 intel_increase_pllclock(crtc, false);
5537 del_timer_sync(&intel_crtc->idle_timer);
5538 }
5539
Jesse Barnes652c3932009-08-17 13:31:43 -07005540 del_timer_sync(&dev_priv->idle_timer);
5541
Jesse Barnese70236a2009-09-21 10:42:27 -07005542 if (dev_priv->display.disable_fbc)
5543 dev_priv->display.disable_fbc(dev);
5544
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005545 if (dev_priv->pwrctx) {
Kristian Høgsbergc1b5dea2009-11-11 12:19:18 -05005546 struct drm_i915_gem_object *obj_priv;
5547
Daniel Vetter23010e42010-03-08 13:35:02 +01005548 obj_priv = to_intel_bo(dev_priv->pwrctx);
Kristian Høgsbergc1b5dea2009-11-11 12:19:18 -05005549 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
5550 I915_READ(PWRCTXA);
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005551 i915_gem_object_unpin(dev_priv->pwrctx);
5552 drm_gem_object_unreference(dev_priv->pwrctx);
5553 }
5554
Jesse Barnesf97108d2010-01-29 11:27:07 -08005555 if (IS_IRONLAKE_M(dev))
5556 ironlake_disable_drps(dev);
5557
Kristian Høgsberg69341a52009-11-11 12:19:17 -05005558 mutex_unlock(&dev->struct_mutex);
5559
Jesse Barnes79e53942008-11-07 14:24:08 -08005560 drm_mode_config_cleanup(dev);
5561}
5562
5563
Dave Airlie28d52042009-09-21 14:33:58 +10005564/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08005565 * Return which encoder is currently attached for connector.
5566 */
5567struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08005568{
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08005569 struct drm_mode_object *obj;
5570 struct drm_encoder *encoder;
5571 int i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005572
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08005573 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5574 if (connector->encoder_ids[i] == 0)
5575 break;
5576
5577 obj = drm_mode_object_find(connector->dev,
5578 connector->encoder_ids[i],
5579 DRM_MODE_OBJECT_ENCODER);
5580 if (!obj)
5581 continue;
5582
5583 encoder = obj_to_encoder(obj);
5584 return encoder;
5585 }
5586 return NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005587}
Dave Airlie28d52042009-09-21 14:33:58 +10005588
5589/*
5590 * set vga decode state - true == enable VGA decode
5591 */
5592int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
5593{
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5595 u16 gmch_ctrl;
5596
5597 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
5598 if (state)
5599 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
5600 else
5601 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5602 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5603 return 0;
5604}