blob: 2a32a7b60c96082d582804b477f90d321745f866 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080032#include "drmP.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070036#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100037#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038
39#include "drm_crtc_helper.h"
40
Zhenyu Wang32f9d652009-07-24 01:00:32 +080041#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
Jesse Barnes79e53942008-11-07 14:24:08 -080043bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080044static void intel_update_watermarks(struct drm_device *dev);
Jesse Barnes652c3932009-08-17 13:31:43 -070045static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +010046static void intel_crtc_update_cursor(struct drm_crtc *crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -080047
48typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58} intel_clock_t;
59
60typedef struct {
61 int min, max;
62} intel_range_t;
63
64typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080070typedef struct intel_limit intel_limit_t;
71struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080072 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080074 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *);
76};
Jesse Barnes79e53942008-11-07 14:24:08 -080077
78#define I8XX_DOT_MIN 25000
79#define I8XX_DOT_MAX 350000
80#define I8XX_VCO_MIN 930000
81#define I8XX_VCO_MAX 1400000
82#define I8XX_N_MIN 3
83#define I8XX_N_MAX 16
84#define I8XX_M_MIN 96
85#define I8XX_M_MAX 140
86#define I8XX_M1_MIN 18
87#define I8XX_M1_MAX 26
88#define I8XX_M2_MIN 6
89#define I8XX_M2_MAX 16
90#define I8XX_P_MIN 4
91#define I8XX_P_MAX 128
92#define I8XX_P1_MIN 2
93#define I8XX_P1_MAX 33
94#define I8XX_P1_LVDS_MIN 1
95#define I8XX_P1_LVDS_MAX 6
96#define I8XX_P2_SLOW 4
97#define I8XX_P2_FAST 2
98#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +080099#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -0800100#define I8XX_P2_SLOW_LIMIT 165000
101
102#define I9XX_DOT_MIN 20000
103#define I9XX_DOT_MAX 400000
104#define I9XX_VCO_MIN 1400000
105#define I9XX_VCO_MAX 2800000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500106#define PINEVIEW_VCO_MIN 1700000
107#define PINEVIEW_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500108#define I9XX_N_MIN 1
109#define I9XX_N_MAX 6
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500110/* Pineview's Ncounter is a ring counter */
111#define PINEVIEW_N_MIN 3
112#define PINEVIEW_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800113#define I9XX_M_MIN 70
114#define I9XX_M_MAX 120
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500115#define PINEVIEW_M_MIN 2
116#define PINEVIEW_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800117#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500118#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800119#define I9XX_M2_MIN 5
120#define I9XX_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500121/* Pineview M1 is reserved, and must be 0 */
122#define PINEVIEW_M1_MIN 0
123#define PINEVIEW_M1_MAX 0
124#define PINEVIEW_M2_MIN 0
125#define PINEVIEW_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800126#define I9XX_P_SDVO_DAC_MIN 5
127#define I9XX_P_SDVO_DAC_MAX 80
128#define I9XX_P_LVDS_MIN 7
129#define I9XX_P_LVDS_MAX 98
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500130#define PINEVIEW_P_LVDS_MIN 7
131#define PINEVIEW_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800132#define I9XX_P1_MIN 1
133#define I9XX_P1_MAX 8
134#define I9XX_P2_SDVO_DAC_SLOW 10
135#define I9XX_P2_SDVO_DAC_FAST 5
136#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
137#define I9XX_P2_LVDS_SLOW 14
138#define I9XX_P2_LVDS_FAST 7
139#define I9XX_P2_LVDS_SLOW_LIMIT 112000
140
Ma Ling044c7c42009-03-18 20:13:23 +0800141/*The parameter is for SDVO on G4x platform*/
142#define G4X_DOT_SDVO_MIN 25000
143#define G4X_DOT_SDVO_MAX 270000
144#define G4X_VCO_MIN 1750000
145#define G4X_VCO_MAX 3500000
146#define G4X_N_SDVO_MIN 1
147#define G4X_N_SDVO_MAX 4
148#define G4X_M_SDVO_MIN 104
149#define G4X_M_SDVO_MAX 138
150#define G4X_M1_SDVO_MIN 17
151#define G4X_M1_SDVO_MAX 23
152#define G4X_M2_SDVO_MIN 5
153#define G4X_M2_SDVO_MAX 11
154#define G4X_P_SDVO_MIN 10
155#define G4X_P_SDVO_MAX 30
156#define G4X_P1_SDVO_MIN 1
157#define G4X_P1_SDVO_MAX 3
158#define G4X_P2_SDVO_SLOW 10
159#define G4X_P2_SDVO_FAST 10
160#define G4X_P2_SDVO_LIMIT 270000
161
162/*The parameter is for HDMI_DAC on G4x platform*/
163#define G4X_DOT_HDMI_DAC_MIN 22000
164#define G4X_DOT_HDMI_DAC_MAX 400000
165#define G4X_N_HDMI_DAC_MIN 1
166#define G4X_N_HDMI_DAC_MAX 4
167#define G4X_M_HDMI_DAC_MIN 104
168#define G4X_M_HDMI_DAC_MAX 138
169#define G4X_M1_HDMI_DAC_MIN 16
170#define G4X_M1_HDMI_DAC_MAX 23
171#define G4X_M2_HDMI_DAC_MIN 5
172#define G4X_M2_HDMI_DAC_MAX 11
173#define G4X_P_HDMI_DAC_MIN 5
174#define G4X_P_HDMI_DAC_MAX 80
175#define G4X_P1_HDMI_DAC_MIN 1
176#define G4X_P1_HDMI_DAC_MAX 8
177#define G4X_P2_HDMI_DAC_SLOW 10
178#define G4X_P2_HDMI_DAC_FAST 5
179#define G4X_P2_HDMI_DAC_LIMIT 165000
180
181/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199
200/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700219/*The parameter is for DISPLAY PORT on G4x platform*/
220#define G4X_DOT_DISPLAY_PORT_MIN 161670
221#define G4X_DOT_DISPLAY_PORT_MAX 227000
222#define G4X_N_DISPLAY_PORT_MIN 1
223#define G4X_N_DISPLAY_PORT_MAX 2
224#define G4X_M_DISPLAY_PORT_MIN 97
225#define G4X_M_DISPLAY_PORT_MAX 108
226#define G4X_M1_DISPLAY_PORT_MIN 0x10
227#define G4X_M1_DISPLAY_PORT_MAX 0x12
228#define G4X_M2_DISPLAY_PORT_MIN 0x05
229#define G4X_M2_DISPLAY_PORT_MAX 0x06
230#define G4X_P_DISPLAY_PORT_MIN 10
231#define G4X_P_DISPLAY_PORT_MAX 20
232#define G4X_P1_DISPLAY_PORT_MIN 1
233#define G4X_P1_DISPLAY_PORT_MAX 2
234#define G4X_P2_DISPLAY_PORT_SLOW 10
235#define G4X_P2_DISPLAY_PORT_FAST 10
236#define G4X_P2_DISPLAY_PORT_LIMIT 0
237
Eric Anholtbad720f2009-10-22 16:11:14 -0700238/* Ironlake / Sandybridge */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800239/* as we calculate clock using (register_value + 2) for
240 N/M1/M2, so here the range value for them is (actual_value-2).
241 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500242#define IRONLAKE_DOT_MIN 25000
243#define IRONLAKE_DOT_MAX 350000
244#define IRONLAKE_VCO_MIN 1760000
245#define IRONLAKE_VCO_MAX 3510000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500246#define IRONLAKE_M1_MIN 12
Zhao Yakuia59e3852010-01-06 22:05:57 +0800247#define IRONLAKE_M1_MAX 22
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500248#define IRONLAKE_M2_MIN 5
249#define IRONLAKE_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500250#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800251
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800252/* We have parameter ranges for different type of outputs. */
253
254/* DAC & HDMI Refclk 120Mhz */
255#define IRONLAKE_DAC_N_MIN 1
256#define IRONLAKE_DAC_N_MAX 5
257#define IRONLAKE_DAC_M_MIN 79
258#define IRONLAKE_DAC_M_MAX 127
259#define IRONLAKE_DAC_P_MIN 5
260#define IRONLAKE_DAC_P_MAX 80
261#define IRONLAKE_DAC_P1_MIN 1
262#define IRONLAKE_DAC_P1_MAX 8
263#define IRONLAKE_DAC_P2_SLOW 10
264#define IRONLAKE_DAC_P2_FAST 5
265
266/* LVDS single-channel 120Mhz refclk */
267#define IRONLAKE_LVDS_S_N_MIN 1
268#define IRONLAKE_LVDS_S_N_MAX 3
269#define IRONLAKE_LVDS_S_M_MIN 79
270#define IRONLAKE_LVDS_S_M_MAX 118
271#define IRONLAKE_LVDS_S_P_MIN 28
272#define IRONLAKE_LVDS_S_P_MAX 112
273#define IRONLAKE_LVDS_S_P1_MIN 2
274#define IRONLAKE_LVDS_S_P1_MAX 8
275#define IRONLAKE_LVDS_S_P2_SLOW 14
276#define IRONLAKE_LVDS_S_P2_FAST 14
277
278/* LVDS dual-channel 120Mhz refclk */
279#define IRONLAKE_LVDS_D_N_MIN 1
280#define IRONLAKE_LVDS_D_N_MAX 3
281#define IRONLAKE_LVDS_D_M_MIN 79
282#define IRONLAKE_LVDS_D_M_MAX 127
283#define IRONLAKE_LVDS_D_P_MIN 14
284#define IRONLAKE_LVDS_D_P_MAX 56
285#define IRONLAKE_LVDS_D_P1_MIN 2
286#define IRONLAKE_LVDS_D_P1_MAX 8
287#define IRONLAKE_LVDS_D_P2_SLOW 7
288#define IRONLAKE_LVDS_D_P2_FAST 7
289
290/* LVDS single-channel 100Mhz refclk */
291#define IRONLAKE_LVDS_S_SSC_N_MIN 1
292#define IRONLAKE_LVDS_S_SSC_N_MAX 2
293#define IRONLAKE_LVDS_S_SSC_M_MIN 79
294#define IRONLAKE_LVDS_S_SSC_M_MAX 126
295#define IRONLAKE_LVDS_S_SSC_P_MIN 28
296#define IRONLAKE_LVDS_S_SSC_P_MAX 112
297#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
298#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
299#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
300#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
301
302/* LVDS dual-channel 100Mhz refclk */
303#define IRONLAKE_LVDS_D_SSC_N_MIN 1
304#define IRONLAKE_LVDS_D_SSC_N_MAX 3
305#define IRONLAKE_LVDS_D_SSC_M_MIN 79
306#define IRONLAKE_LVDS_D_SSC_M_MAX 126
307#define IRONLAKE_LVDS_D_SSC_P_MIN 14
308#define IRONLAKE_LVDS_D_SSC_P_MAX 42
309#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
310#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
311#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
312#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313
314/* DisplayPort */
315#define IRONLAKE_DP_N_MIN 1
316#define IRONLAKE_DP_N_MAX 2
317#define IRONLAKE_DP_M_MIN 81
318#define IRONLAKE_DP_M_MAX 90
319#define IRONLAKE_DP_P_MIN 10
320#define IRONLAKE_DP_P_MAX 20
321#define IRONLAKE_DP_P2_FAST 10
322#define IRONLAKE_DP_P2_SLOW 10
323#define IRONLAKE_DP_P2_LIMIT 0
324#define IRONLAKE_DP_P1_MIN 1
325#define IRONLAKE_DP_P1_MAX 2
Zhao Yakui45476682009-12-31 16:06:04 +0800326
Jesse Barnes2377b742010-07-07 14:06:43 -0700327/* FDI */
328#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
329
Ma Lingd4906092009-03-18 20:13:27 +0800330static bool
331intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
332 int target, int refclk, intel_clock_t *best_clock);
333static bool
334intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
335 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800336
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700337static bool
338intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
339 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800340static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500341intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
342 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700343
Keith Packarde4b36692009-06-05 19:22:17 -0700344static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800345 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
346 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
347 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
348 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
349 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
350 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
351 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
352 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
353 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
354 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800355 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700356};
357
358static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800359 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
360 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
361 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
362 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
363 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
364 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
365 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
366 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
367 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
368 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800369 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700370};
371
372static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800373 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
374 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
375 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
376 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
377 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
378 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
379 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
380 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
381 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
382 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800383 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700384};
385
386static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800387 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
388 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
389 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
390 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
391 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
392 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
393 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
394 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
395 /* The single-channel range is 25-112Mhz, and dual-channel
396 * is 80-224Mhz. Prefer single channel as much as possible.
397 */
398 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
399 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800400 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700401};
402
Ma Ling044c7c42009-03-18 20:13:23 +0800403 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700404static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800405 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
406 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
407 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
408 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
409 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
410 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
411 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
412 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
413 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
414 .p2_slow = G4X_P2_SDVO_SLOW,
415 .p2_fast = G4X_P2_SDVO_FAST
416 },
Ma Lingd4906092009-03-18 20:13:27 +0800417 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700418};
419
420static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800421 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
422 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
423 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
424 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
425 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
426 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
427 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
428 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
429 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
430 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
431 .p2_fast = G4X_P2_HDMI_DAC_FAST
432 },
Ma Lingd4906092009-03-18 20:13:27 +0800433 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700434};
435
436static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800437 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
439 .vco = { .min = G4X_VCO_MIN,
440 .max = G4X_VCO_MAX },
441 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
443 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
445 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
447 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
448 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
449 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
451 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
453 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
454 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
455 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
456 },
Ma Lingd4906092009-03-18 20:13:27 +0800457 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700458};
459
460static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800461 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
463 .vco = { .min = G4X_VCO_MIN,
464 .max = G4X_VCO_MAX },
465 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
467 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
469 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
471 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
472 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
473 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
475 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
477 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
478 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
479 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
480 },
Ma Lingd4906092009-03-18 20:13:27 +0800481 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700482};
483
484static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700485 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
486 .max = G4X_DOT_DISPLAY_PORT_MAX },
487 .vco = { .min = G4X_VCO_MIN,
488 .max = G4X_VCO_MAX},
489 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
490 .max = G4X_N_DISPLAY_PORT_MAX },
491 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
492 .max = G4X_M_DISPLAY_PORT_MAX },
493 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
494 .max = G4X_M1_DISPLAY_PORT_MAX },
495 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
496 .max = G4X_M2_DISPLAY_PORT_MAX },
497 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
498 .max = G4X_P_DISPLAY_PORT_MAX },
499 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
500 .max = G4X_P1_DISPLAY_PORT_MAX},
501 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
502 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
503 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
504 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700505};
506
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500507static const intel_limit_t intel_limits_pineview_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800508 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500509 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
510 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
511 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
512 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
513 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800514 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
515 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
516 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
517 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800518 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700519};
520
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500521static const intel_limit_t intel_limits_pineview_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800522 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500523 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
524 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
525 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
526 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
527 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
528 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800529 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500530 /* Pineview only supports single-channel mode. */
Shaohua Li21778322009-02-23 15:19:16 +0800531 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
532 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800533 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700534};
535
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800536static const intel_limit_t intel_limits_ironlake_dac = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500537 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
538 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800539 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
540 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500541 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
542 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800543 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
544 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500545 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800546 .p2_slow = IRONLAKE_DAC_P2_SLOW,
547 .p2_fast = IRONLAKE_DAC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800548 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700549};
550
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800551static const intel_limit_t intel_limits_ironlake_single_lvds = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500552 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
553 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800554 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
555 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500556 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
557 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800558 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
559 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500560 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800561 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
562 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
563 .find_pll = intel_g4x_find_best_PLL,
564};
565
566static const intel_limit_t intel_limits_ironlake_dual_lvds = {
567 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
568 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
569 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
570 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
571 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
572 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
573 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
574 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
575 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
576 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
577 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
578 .find_pll = intel_g4x_find_best_PLL,
579};
580
581static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
582 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
583 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
584 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
585 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
586 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
587 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
588 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
589 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
590 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
591 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
592 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
593 .find_pll = intel_g4x_find_best_PLL,
594};
595
596static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
597 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
598 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
599 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
600 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
601 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
602 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
603 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
604 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
605 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
606 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
607 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800608 .find_pll = intel_g4x_find_best_PLL,
609};
610
611static const intel_limit_t intel_limits_ironlake_display_port = {
612 .dot = { .min = IRONLAKE_DOT_MIN,
613 .max = IRONLAKE_DOT_MAX },
614 .vco = { .min = IRONLAKE_VCO_MIN,
615 .max = IRONLAKE_VCO_MAX},
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800616 .n = { .min = IRONLAKE_DP_N_MIN,
617 .max = IRONLAKE_DP_N_MAX },
618 .m = { .min = IRONLAKE_DP_M_MIN,
619 .max = IRONLAKE_DP_M_MAX },
Zhao Yakui45476682009-12-31 16:06:04 +0800620 .m1 = { .min = IRONLAKE_M1_MIN,
621 .max = IRONLAKE_M1_MAX },
622 .m2 = { .min = IRONLAKE_M2_MIN,
623 .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800624 .p = { .min = IRONLAKE_DP_P_MIN,
625 .max = IRONLAKE_DP_P_MAX },
626 .p1 = { .min = IRONLAKE_DP_P1_MIN,
627 .max = IRONLAKE_DP_P1_MAX},
628 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
629 .p2_slow = IRONLAKE_DP_P2_SLOW,
630 .p2_fast = IRONLAKE_DP_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800631 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800632};
633
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500634static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800635{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800636 struct drm_device *dev = crtc->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800638 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800639 int refclk = 120;
640
641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
642 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
643 refclk = 100;
644
645 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
646 LVDS_CLKB_POWER_UP) {
647 /* LVDS dual channel */
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_dual_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_dual_lvds;
652 } else {
653 if (refclk == 100)
654 limit = &intel_limits_ironlake_single_lvds_100m;
655 else
656 limit = &intel_limits_ironlake_single_lvds;
657 }
658 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800659 HAS_eDP)
660 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800661 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800662 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800663
664 return limit;
665}
666
Ma Ling044c7c42009-03-18 20:13:23 +0800667static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
668{
669 struct drm_device *dev = crtc->dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
671 const intel_limit_t *limit;
672
673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
674 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
675 LVDS_CLKB_POWER_UP)
676 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700677 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800678 else
679 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700680 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800681 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
682 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700683 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800684 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700685 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700686 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700687 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800688 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700689 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800690
691 return limit;
692}
693
Jesse Barnes79e53942008-11-07 14:24:08 -0800694static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
695{
696 struct drm_device *dev = crtc->dev;
697 const intel_limit_t *limit;
698
Eric Anholtbad720f2009-10-22 16:11:14 -0700699 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500700 limit = intel_ironlake_limit(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800701 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800702 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500703 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700705 limit = &intel_limits_i9xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800706 else
Keith Packarde4b36692009-06-05 19:22:17 -0700707 limit = &intel_limits_i9xx_sdvo;
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500708 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500710 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800711 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500712 limit = &intel_limits_pineview_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800713 } else {
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700715 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800716 else
Keith Packarde4b36692009-06-05 19:22:17 -0700717 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800718 }
719 return limit;
720}
721
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500722/* m1 is reserved as 0 in Pineview, n is a ring counter */
723static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800724{
Shaohua Li21778322009-02-23 15:19:16 +0800725 clock->m = clock->m2 + 2;
726 clock->p = clock->p1 * clock->p2;
727 clock->vco = refclk * clock->m / clock->n;
728 clock->dot = clock->vco / clock->p;
729}
730
731static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
732{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500733 if (IS_PINEVIEW(dev)) {
734 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800735 return;
736 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800737 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
738 clock->p = clock->p1 * clock->p2;
739 clock->vco = refclk * clock->m / (clock->n + 2);
740 clock->dot = clock->vco / clock->p;
741}
742
Jesse Barnes79e53942008-11-07 14:24:08 -0800743/**
744 * Returns whether any output on the specified pipe is of the specified type
745 */
746bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
747{
748 struct drm_device *dev = crtc->dev;
749 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +0800750 struct drm_encoder *l_entry;
Jesse Barnes79e53942008-11-07 14:24:08 -0800751
Zhenyu Wangc5e4df32010-03-30 14:39:27 +0800752 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
753 if (l_entry && l_entry->crtc == crtc) {
754 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
Eric Anholt21d40d32010-03-25 11:11:14 -0700755 if (intel_encoder->type == type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800756 return true;
757 }
758 }
759 return false;
760}
761
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800762#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800763/**
764 * Returns whether the given set of divisors are valid for a given refclk with
765 * the given connectors.
766 */
767
768static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
769{
770 const intel_limit_t *limit = intel_limit (crtc);
Shaohua Li21778322009-02-23 15:19:16 +0800771 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -0800772
773 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
774 INTELPllInvalid ("p1 out of range\n");
775 if (clock->p < limit->p.min || limit->p.max < clock->p)
776 INTELPllInvalid ("p out of range\n");
777 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
778 INTELPllInvalid ("m2 out of range\n");
779 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
780 INTELPllInvalid ("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500781 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800782 INTELPllInvalid ("m1 <= m2\n");
783 if (clock->m < limit->m.min || limit->m.max < clock->m)
784 INTELPllInvalid ("m out of range\n");
785 if (clock->n < limit->n.min || limit->n.max < clock->n)
786 INTELPllInvalid ("n out of range\n");
787 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
788 INTELPllInvalid ("vco out of range\n");
789 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
790 * connector, etc., rather than just a single range.
791 */
792 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
793 INTELPllInvalid ("dot out of range\n");
794
795 return true;
796}
797
Ma Lingd4906092009-03-18 20:13:27 +0800798static bool
799intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
800 int target, int refclk, intel_clock_t *best_clock)
801
Jesse Barnes79e53942008-11-07 14:24:08 -0800802{
803 struct drm_device *dev = crtc->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800806 int err = target;
807
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800809 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800810 /*
811 * For LVDS, if the panel is on, just rely on its current
812 * settings for dual-channel. We haven't figured out how to
813 * reliably set up different single/dual channel state, if we
814 * even can.
815 */
816 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
817 LVDS_CLKB_POWER_UP)
818 clock.p2 = limit->p2.p2_fast;
819 else
820 clock.p2 = limit->p2.p2_slow;
821 } else {
822 if (target < limit->p2.dot_limit)
823 clock.p2 = limit->p2.p2_slow;
824 else
825 clock.p2 = limit->p2.p2_fast;
826 }
827
828 memset (best_clock, 0, sizeof (*best_clock));
829
Zhao Yakui42158662009-11-20 11:24:18 +0800830 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
831 clock.m1++) {
832 for (clock.m2 = limit->m2.min;
833 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500834 /* m1 is always 0 in Pineview */
835 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800836 break;
837 for (clock.n = limit->n.min;
838 clock.n <= limit->n.max; clock.n++) {
839 for (clock.p1 = limit->p1.min;
840 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800841 int this_err;
842
Shaohua Li21778322009-02-23 15:19:16 +0800843 intel_clock(dev, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800844
845 if (!intel_PLL_is_valid(crtc, &clock))
846 continue;
847
848 this_err = abs(clock.dot - target);
849 if (this_err < err) {
850 *best_clock = clock;
851 err = this_err;
852 }
853 }
854 }
855 }
856 }
857
858 return (err != target);
859}
860
Ma Lingd4906092009-03-18 20:13:27 +0800861static bool
862intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *best_clock)
864{
865 struct drm_device *dev = crtc->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 intel_clock_t clock;
868 int max_n;
869 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800872 found = false;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800875 int lvds_reg;
876
Eric Anholtc619eed2010-01-28 16:45:52 -0800877 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800878 lvds_reg = PCH_LVDS;
879 else
880 lvds_reg = LVDS;
881 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800882 LVDS_CLKB_POWER_UP)
883 clock.p2 = limit->p2.p2_fast;
884 else
885 clock.p2 = limit->p2.p2_slow;
886 } else {
887 if (target < limit->p2.dot_limit)
888 clock.p2 = limit->p2.p2_slow;
889 else
890 clock.p2 = limit->p2.p2_fast;
891 }
892
893 memset(best_clock, 0, sizeof(*best_clock));
894 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200895 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200897 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
902 for (clock.p1 = limit->p1.max;
903 clock.p1 >= limit->p1.min; clock.p1--) {
904 int this_err;
905
Shaohua Li21778322009-02-23 15:19:16 +0800906 intel_clock(dev, refclk, &clock);
Ma Lingd4906092009-03-18 20:13:27 +0800907 if (!intel_PLL_is_valid(crtc, &clock))
908 continue;
909 this_err = abs(clock.dot - target) ;
910 if (this_err < err_most) {
911 *best_clock = clock;
912 err_most = this_err;
913 max_n = clock.n;
914 found = true;
915 }
916 }
917 }
918 }
919 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800920 return found;
921}
Ma Lingd4906092009-03-18 20:13:27 +0800922
Zhenyu Wang2c072452009-06-05 15:38:42 +0800923static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500924intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
925 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800926{
927 struct drm_device *dev = crtc->dev;
928 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800929
930 /* return directly when it is eDP */
931 if (HAS_eDP)
932 return true;
933
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800934 if (target < 200000) {
935 clock.n = 1;
936 clock.p1 = 2;
937 clock.p2 = 10;
938 clock.m1 = 12;
939 clock.m2 = 9;
940 } else {
941 clock.n = 2;
942 clock.p1 = 1;
943 clock.p2 = 10;
944 clock.m1 = 14;
945 clock.m2 = 8;
946 }
947 intel_clock(dev, refclk, &clock);
948 memcpy(best_clock, &clock, sizeof(intel_clock_t));
949 return true;
950}
951
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700952/* DisplayPort has only two frequencies, 162MHz and 270MHz */
953static bool
954intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
955 int target, int refclk, intel_clock_t *best_clock)
956{
957 intel_clock_t clock;
958 if (target < 200000) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700959 clock.p1 = 2;
960 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700961 clock.n = 2;
962 clock.m1 = 23;
963 clock.m2 = 8;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700964 } else {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700965 clock.p1 = 1;
966 clock.p2 = 10;
Keith Packardb3d25492009-06-24 23:09:15 -0700967 clock.n = 1;
968 clock.m1 = 14;
969 clock.m2 = 2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700970 }
Keith Packardb3d25492009-06-24 23:09:15 -0700971 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
972 clock.p = (clock.p1 * clock.p2);
973 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
Jesse Barnesfe798b92009-10-20 07:55:28 +0900974 clock.vco = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700975 memcpy(best_clock, &clock, sizeof(intel_clock_t));
976 return true;
977}
978
Jesse Barnes79e53942008-11-07 14:24:08 -0800979void
980intel_wait_for_vblank(struct drm_device *dev)
981{
982 /* Wait for 20ms, i.e. one cycle at 50hz. */
Jesse Barnes81255562010-08-02 12:07:50 -0700983 if (in_dbg_master())
984 mdelay(20); /* The kernel debugger cannot call msleep() */
985 else
986 msleep(20);
Jesse Barnes79e53942008-11-07 14:24:08 -0800987}
988
Jesse Barnes80824002009-09-10 15:28:06 -0700989/* Parameters have changed, update FBC info */
990static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
991{
992 struct drm_device *dev = crtc->dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_framebuffer *fb = crtc->fb;
995 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +0100996 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes80824002009-09-10 15:28:06 -0700997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
998 int plane, i;
999 u32 fbc_ctl, fbc_ctl2;
1000
1001 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003 if (fb->pitch < dev_priv->cfb_pitch)
1004 dev_priv->cfb_pitch = fb->pitch;
1005
1006 /* FBC_CTL wants 64B units */
1007 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008 dev_priv->cfb_fence = obj_priv->fence_reg;
1009 dev_priv->cfb_plane = intel_crtc->plane;
1010 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012 /* Clear old tags */
1013 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016 /* Set it up... */
1017 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018 if (obj_priv->tiling_mode != I915_TILING_NONE)
1019 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023 /* enable it... */
1024 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001025 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001026 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Jesse Barnes80824002009-09-10 15:28:06 -07001027 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029 if (obj_priv->tiling_mode != I915_TILING_NONE)
1030 fbc_ctl |= dev_priv->cfb_fence;
1031 I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
Zhao Yakui28c97732009-10-09 11:39:41 +08001033 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
Jesse Barnes80824002009-09-10 15:28:06 -07001034 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035}
1036
1037void i8xx_disable_fbc(struct drm_device *dev)
1038{
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040 u32 fbc_ctl;
1041
Jesse Barnesc1a1cdc2009-09-16 15:05:00 -07001042 if (!I915_HAS_FBC(dev))
1043 return;
1044
Jesse Barnes9517a922010-05-21 09:40:45 -07001045 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1046 return; /* Already off, just return */
1047
Jesse Barnes80824002009-09-10 15:28:06 -07001048 /* Disable compression */
1049 fbc_ctl = I915_READ(FBC_CONTROL);
1050 fbc_ctl &= ~FBC_CTL_EN;
1051 I915_WRITE(FBC_CONTROL, fbc_ctl);
1052
1053 /* Wait for compressing bit to clear */
Chris Wilson913d8d12010-08-07 11:01:35 +01001054 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1055 DRM_DEBUG_KMS("FBC idle timed out\n");
1056 return;
Jesse Barnes9517a922010-05-21 09:40:45 -07001057 }
Jesse Barnes80824002009-09-10 15:28:06 -07001058
1059 intel_wait_for_vblank(dev);
1060
Zhao Yakui28c97732009-10-09 11:39:41 +08001061 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001062}
1063
Adam Jacksonee5382a2010-04-23 11:17:39 -04001064static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001065{
Jesse Barnes80824002009-09-10 15:28:06 -07001066 struct drm_i915_private *dev_priv = dev->dev_private;
1067
1068 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1069}
1070
Jesse Barnes74dff282009-09-14 15:39:40 -07001071static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1072{
1073 struct drm_device *dev = crtc->dev;
1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075 struct drm_framebuffer *fb = crtc->fb;
1076 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001077 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes74dff282009-09-14 15:39:40 -07001078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1079 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1080 DPFC_CTL_PLANEB);
1081 unsigned long stall_watermark = 200;
1082 u32 dpfc_ctl;
1083
1084 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1085 dev_priv->cfb_fence = obj_priv->fence_reg;
1086 dev_priv->cfb_plane = intel_crtc->plane;
1087
1088 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1089 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1090 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1091 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1092 } else {
1093 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1094 }
1095
1096 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1097 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1098 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1099 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1100 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1101
1102 /* enable it... */
1103 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1104
Zhao Yakui28c97732009-10-09 11:39:41 +08001105 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001106}
1107
1108void g4x_disable_fbc(struct drm_device *dev)
1109{
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 u32 dpfc_ctl;
1112
1113 /* Disable compression */
1114 dpfc_ctl = I915_READ(DPFC_CONTROL);
1115 dpfc_ctl &= ~DPFC_CTL_EN;
1116 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1117 intel_wait_for_vblank(dev);
1118
Zhao Yakui28c97732009-10-09 11:39:41 +08001119 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes74dff282009-09-14 15:39:40 -07001120}
1121
Adam Jacksonee5382a2010-04-23 11:17:39 -04001122static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001123{
Jesse Barnes74dff282009-09-14 15:39:40 -07001124 struct drm_i915_private *dev_priv = dev->dev_private;
1125
1126 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1127}
1128
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001129static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1130{
1131 struct drm_device *dev = crtc->dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 struct drm_framebuffer *fb = crtc->fb;
1134 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1135 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1137 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1138 DPFC_CTL_PLANEB;
1139 unsigned long stall_watermark = 200;
1140 u32 dpfc_ctl;
1141
1142 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1143 dev_priv->cfb_fence = obj_priv->fence_reg;
1144 dev_priv->cfb_plane = intel_crtc->plane;
1145
1146 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1147 dpfc_ctl &= DPFC_RESERVED;
1148 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1149 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1150 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1151 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1152 } else {
1153 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1154 }
1155
1156 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1157 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1158 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1159 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1160 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1161 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1162 /* enable it... */
1163 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1164 DPFC_CTL_EN);
1165
1166 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1167}
1168
1169void ironlake_disable_fbc(struct drm_device *dev)
1170{
1171 struct drm_i915_private *dev_priv = dev->dev_private;
1172 u32 dpfc_ctl;
1173
1174 /* Disable compression */
1175 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1176 dpfc_ctl &= ~DPFC_CTL_EN;
1177 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1178 intel_wait_for_vblank(dev);
1179
1180 DRM_DEBUG_KMS("disabled FBC\n");
1181}
1182
1183static bool ironlake_fbc_enabled(struct drm_device *dev)
1184{
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186
1187 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1188}
1189
Adam Jacksonee5382a2010-04-23 11:17:39 -04001190bool intel_fbc_enabled(struct drm_device *dev)
1191{
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193
1194 if (!dev_priv->display.fbc_enabled)
1195 return false;
1196
1197 return dev_priv->display.fbc_enabled(dev);
1198}
1199
1200void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1201{
1202 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1203
1204 if (!dev_priv->display.enable_fbc)
1205 return;
1206
1207 dev_priv->display.enable_fbc(crtc, interval);
1208}
1209
1210void intel_disable_fbc(struct drm_device *dev)
1211{
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1213
1214 if (!dev_priv->display.disable_fbc)
1215 return;
1216
1217 dev_priv->display.disable_fbc(dev);
1218}
1219
Jesse Barnes80824002009-09-10 15:28:06 -07001220/**
1221 * intel_update_fbc - enable/disable FBC as needed
1222 * @crtc: CRTC to point the compressor at
1223 * @mode: mode in use
1224 *
1225 * Set up the framebuffer compression hardware at mode set time. We
1226 * enable it if possible:
1227 * - plane A only (on pre-965)
1228 * - no pixel mulitply/line duplication
1229 * - no alpha buffer discard
1230 * - no dual wide
1231 * - framebuffer <= 2048 in width, 1536 in height
1232 *
1233 * We can't assume that any compression will take place (worst case),
1234 * so the compressed buffer has to be the same size as the uncompressed
1235 * one. It also must reside (along with the line length buffer) in
1236 * stolen memory.
1237 *
1238 * We need to enable/disable FBC on a global basis.
1239 */
1240static void intel_update_fbc(struct drm_crtc *crtc,
1241 struct drm_display_mode *mode)
1242{
1243 struct drm_device *dev = crtc->dev;
1244 struct drm_i915_private *dev_priv = dev->dev_private;
1245 struct drm_framebuffer *fb = crtc->fb;
1246 struct intel_framebuffer *intel_fb;
1247 struct drm_i915_gem_object *obj_priv;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001248 struct drm_crtc *tmp_crtc;
Jesse Barnes80824002009-09-10 15:28:06 -07001249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1250 int plane = intel_crtc->plane;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001251 int crtcs_enabled = 0;
1252
1253 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001254
1255 if (!i915_powersave)
1256 return;
1257
Adam Jacksonee5382a2010-04-23 11:17:39 -04001258 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001259 return;
1260
Jesse Barnes80824002009-09-10 15:28:06 -07001261 if (!crtc->fb)
1262 return;
1263
1264 intel_fb = to_intel_framebuffer(fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001265 obj_priv = to_intel_bo(intel_fb->obj);
Jesse Barnes80824002009-09-10 15:28:06 -07001266
1267 /*
1268 * If FBC is already on, we just have to verify that we can
1269 * keep it that way...
1270 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001271 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001272 * - changing FBC params (stride, fence, mode)
1273 * - new fb is too large to fit in compressed buffer
1274 * - going to an unsupported config (interlace, pixel multiply, etc.)
1275 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001276 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1277 if (tmp_crtc->enabled)
1278 crtcs_enabled++;
1279 }
1280 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1281 if (crtcs_enabled > 1) {
1282 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1283 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1284 goto out_disable;
1285 }
Jesse Barnes80824002009-09-10 15:28:06 -07001286 if (intel_fb->obj->size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001287 DRM_DEBUG_KMS("framebuffer too large, disabling "
1288 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001289 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001290 goto out_disable;
1291 }
1292 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1293 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001294 DRM_DEBUG_KMS("mode incompatible with compression, "
1295 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001296 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001297 goto out_disable;
1298 }
1299 if ((mode->hdisplay > 2048) ||
1300 (mode->vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001301 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001302 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001303 goto out_disable;
1304 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001305 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001306 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001307 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001308 goto out_disable;
1309 }
1310 if (obj_priv->tiling_mode != I915_TILING_X) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001311 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001312 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001313 goto out_disable;
1314 }
1315
Jason Wesselc924b932010-08-05 09:22:32 -05001316 /* If the kernel debugger is active, always disable compression */
1317 if (in_dbg_master())
1318 goto out_disable;
1319
Adam Jacksonee5382a2010-04-23 11:17:39 -04001320 if (intel_fbc_enabled(dev)) {
Jesse Barnes80824002009-09-10 15:28:06 -07001321 /* We can re-enable it in this case, but need to update pitch */
Adam Jacksonee5382a2010-04-23 11:17:39 -04001322 if ((fb->pitch > dev_priv->cfb_pitch) ||
1323 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1324 (plane != dev_priv->cfb_plane))
1325 intel_disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07001326 }
1327
Adam Jacksonee5382a2010-04-23 11:17:39 -04001328 /* Now try to turn it back on if possible */
1329 if (!intel_fbc_enabled(dev))
1330 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001331
1332 return;
1333
1334out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001335 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001336 if (intel_fbc_enabled(dev)) {
1337 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001338 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001339 }
Jesse Barnes80824002009-09-10 15:28:06 -07001340}
1341
Chris Wilson127bd2a2010-07-23 23:32:05 +01001342int
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001343intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1344{
Daniel Vetter23010e42010-03-08 13:35:02 +01001345 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001346 u32 alignment;
1347 int ret;
1348
1349 switch (obj_priv->tiling_mode) {
1350 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001351 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1352 alignment = 128 * 1024;
1353 else if (IS_I965G(dev))
1354 alignment = 4 * 1024;
1355 else
1356 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001357 break;
1358 case I915_TILING_X:
1359 /* pin() will align the object as required by fence */
1360 alignment = 0;
1361 break;
1362 case I915_TILING_Y:
1363 /* FIXME: Is this true? */
1364 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1365 return -EINVAL;
1366 default:
1367 BUG();
1368 }
1369
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001370 ret = i915_gem_object_pin(obj, alignment);
1371 if (ret != 0)
1372 return ret;
1373
1374 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1375 * fence, whereas 965+ only requires a fence if using
1376 * framebuffer compression. For simplicity, we always install
1377 * a fence as the cost is not that onerous.
1378 */
1379 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1380 obj_priv->tiling_mode != I915_TILING_NONE) {
1381 ret = i915_gem_object_get_fence_reg(obj);
1382 if (ret != 0) {
1383 i915_gem_object_unpin(obj);
1384 return ret;
1385 }
1386 }
1387
1388 return 0;
1389}
1390
Jesse Barnes81255562010-08-02 12:07:50 -07001391/* Assume fb object is pinned & idle & fenced and just update base pointers */
1392static int
1393intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1394 int x, int y)
1395{
1396 struct drm_device *dev = crtc->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1399 struct intel_framebuffer *intel_fb;
1400 struct drm_i915_gem_object *obj_priv;
1401 struct drm_gem_object *obj;
1402 int plane = intel_crtc->plane;
1403 unsigned long Start, Offset;
1404 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1405 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1406 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1407 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1408 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1409 u32 dspcntr;
1410
1411 switch (plane) {
1412 case 0:
1413 case 1:
1414 break;
1415 default:
1416 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1417 return -EINVAL;
1418 }
1419
1420 intel_fb = to_intel_framebuffer(fb);
1421 obj = intel_fb->obj;
1422 obj_priv = to_intel_bo(obj);
1423
1424 dspcntr = I915_READ(dspcntr_reg);
1425 /* Mask out pixel format bits in case we change it */
1426 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1427 switch (fb->bits_per_pixel) {
1428 case 8:
1429 dspcntr |= DISPPLANE_8BPP;
1430 break;
1431 case 16:
1432 if (fb->depth == 15)
1433 dspcntr |= DISPPLANE_15_16BPP;
1434 else
1435 dspcntr |= DISPPLANE_16BPP;
1436 break;
1437 case 24:
1438 case 32:
1439 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1440 break;
1441 default:
1442 DRM_ERROR("Unknown color depth\n");
1443 return -EINVAL;
1444 }
1445 if (IS_I965G(dev)) {
1446 if (obj_priv->tiling_mode != I915_TILING_NONE)
1447 dspcntr |= DISPPLANE_TILED;
1448 else
1449 dspcntr &= ~DISPPLANE_TILED;
1450 }
1451
1452 if (IS_IRONLAKE(dev))
1453 /* must disable */
1454 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1455
1456 I915_WRITE(dspcntr_reg, dspcntr);
1457
1458 Start = obj_priv->gtt_offset;
1459 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1460
1461 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1462 I915_WRITE(dspstride, fb->pitch);
1463 if (IS_I965G(dev)) {
1464 I915_WRITE(dspbase, Offset);
1465 I915_READ(dspbase);
1466 I915_WRITE(dspsurf, Start);
1467 I915_READ(dspsurf);
1468 I915_WRITE(dsptileoff, (y << 16) | x);
1469 } else {
1470 I915_WRITE(dspbase, Start + Offset);
1471 I915_READ(dspbase);
1472 }
1473
1474 if ((IS_I965G(dev) || plane == 0))
1475 intel_update_fbc(crtc, &crtc->mode);
1476
1477 intel_wait_for_vblank(dev);
1478 intel_increase_pllclock(crtc, true);
1479
1480 return 0;
1481}
1482
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001483static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001484intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1485 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08001486{
1487 struct drm_device *dev = crtc->dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct drm_i915_master_private *master_priv;
1490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1491 struct intel_framebuffer *intel_fb;
1492 struct drm_i915_gem_object *obj_priv;
1493 struct drm_gem_object *obj;
1494 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07001495 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08001496 unsigned long Start, Offset;
Jesse Barnes80824002009-09-10 15:28:06 -07001497 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1498 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1499 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1500 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1501 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001502 u32 dspcntr;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001503 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08001504
1505 /* no fb bound */
1506 if (!crtc->fb) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001507 DRM_DEBUG_KMS("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001508 return 0;
1509 }
1510
Jesse Barnes80824002009-09-10 15:28:06 -07001511 switch (plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001512 case 0:
1513 case 1:
1514 break;
1515 default:
Jesse Barnes80824002009-09-10 15:28:06 -07001516 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001517 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001518 }
1519
1520 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08001521 obj = intel_fb->obj;
Daniel Vetter23010e42010-03-08 13:35:02 +01001522 obj_priv = to_intel_bo(obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08001523
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001524 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001525 ret = intel_pin_and_fence_fb_obj(dev, obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001526 if (ret != 0) {
1527 mutex_unlock(&dev->struct_mutex);
1528 return ret;
1529 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001530
Zhenyu Wangb9241ea2009-11-25 13:09:39 +08001531 ret = i915_gem_object_set_to_display_plane(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001532 if (ret != 0) {
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001533 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001534 mutex_unlock(&dev->struct_mutex);
1535 return ret;
1536 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001537
1538 dspcntr = I915_READ(dspcntr_reg);
Jesse Barnes712531b2009-01-09 13:56:14 -08001539 /* Mask out pixel format bits in case we change it */
1540 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Jesse Barnes79e53942008-11-07 14:24:08 -08001541 switch (crtc->fb->bits_per_pixel) {
1542 case 8:
1543 dspcntr |= DISPPLANE_8BPP;
1544 break;
1545 case 16:
1546 if (crtc->fb->depth == 15)
1547 dspcntr |= DISPPLANE_15_16BPP;
1548 else
1549 dspcntr |= DISPPLANE_16BPP;
1550 break;
1551 case 24:
1552 case 32:
Kristian Høgsberga4f45cf2009-10-19 14:35:30 -04001553 if (crtc->fb->depth == 30)
1554 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1555 else
1556 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
Jesse Barnes79e53942008-11-07 14:24:08 -08001557 break;
1558 default:
1559 DRM_ERROR("Unknown color depth\n");
Chris Wilson8c4b8c32009-06-17 22:08:52 +01001560 i915_gem_object_unpin(obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001561 mutex_unlock(&dev->struct_mutex);
1562 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08001563 }
Jesse Barnesf5448472009-04-14 14:17:47 -07001564 if (IS_I965G(dev)) {
1565 if (obj_priv->tiling_mode != I915_TILING_NONE)
1566 dspcntr |= DISPPLANE_TILED;
1567 else
1568 dspcntr &= ~DISPPLANE_TILED;
1569 }
1570
Eric Anholtbad720f2009-10-22 16:11:14 -07001571 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang553bd142009-09-02 10:57:52 +08001572 /* must disable */
1573 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1574
Jesse Barnes79e53942008-11-07 14:24:08 -08001575 I915_WRITE(dspcntr_reg, dspcntr);
1576
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001577 Start = obj_priv->gtt_offset;
1578 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1579
Chris Wilsona7faf322010-05-27 13:18:17 +01001580 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1581 Start, Offset, x, y, crtc->fb->pitch);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001582 I915_WRITE(dspstride, crtc->fb->pitch);
Jesse Barnes79e53942008-11-07 14:24:08 -08001583 if (IS_I965G(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08001584 I915_WRITE(dspsurf, Start);
Jesse Barnesf5448472009-04-14 14:17:47 -07001585 I915_WRITE(dsptileoff, (y << 16) | x);
Chris Wilson20a09452010-08-07 11:01:29 +01001586 I915_WRITE(dspbase, Offset);
Jesse Barnes79e53942008-11-07 14:24:08 -08001587 } else {
1588 I915_WRITE(dspbase, Start + Offset);
Jesse Barnes79e53942008-11-07 14:24:08 -08001589 }
Chris Wilson20a09452010-08-07 11:01:29 +01001590 POSTING_READ(dspbase);
Jesse Barnes79e53942008-11-07 14:24:08 -08001591
Jesse Barnes74dff282009-09-14 15:39:40 -07001592 if ((IS_I965G(dev) || plane == 0))
Jesse Barnesedb81952009-09-17 17:06:47 -07001593 intel_update_fbc(crtc, &crtc->mode);
1594
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001595 intel_wait_for_vblank(dev);
1596
1597 if (old_fb) {
1598 intel_fb = to_intel_framebuffer(old_fb);
Daniel Vetter23010e42010-03-08 13:35:02 +01001599 obj_priv = to_intel_bo(intel_fb->obj);
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05001600 i915_gem_object_unpin(intel_fb->obj);
1601 }
Jesse Barnes652c3932009-08-17 13:31:43 -07001602 intel_increase_pllclock(crtc, true);
1603
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001604 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001605
1606 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001607 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001608
1609 master_priv = dev->primary->master->driver_priv;
1610 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001611 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001612
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001613 if (pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08001614 master_priv->sarea_priv->pipeB_x = x;
1615 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001616 } else {
1617 master_priv->sarea_priv->pipeA_x = x;
1618 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08001619 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00001620
1621 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001622}
1623
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001624/* Disable the VGA plane that we never use */
1625static void i915_disable_vga (struct drm_device *dev)
1626{
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 u8 sr1;
1629 u32 vga_reg;
1630
Eric Anholtbad720f2009-10-22 16:11:14 -07001631 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang24f119c2009-07-24 01:00:28 +08001632 vga_reg = CPU_VGACNTRL;
1633 else
1634 vga_reg = VGACNTRL;
1635
1636 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1637 return;
1638
1639 I915_WRITE8(VGA_SR_INDEX, 1);
1640 sr1 = I915_READ8(VGA_SR_DATA);
1641 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1642 udelay(100);
1643
1644 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1645}
1646
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001647static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001648{
1649 struct drm_device *dev = crtc->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 u32 dpa_ctl;
1652
Zhao Yakui28c97732009-10-09 11:39:41 +08001653 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001654 dpa_ctl = I915_READ(DP_A);
1655 dpa_ctl &= ~DP_PLL_ENABLE;
1656 I915_WRITE(DP_A, dpa_ctl);
1657}
1658
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001659static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001660{
1661 struct drm_device *dev = crtc->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 u32 dpa_ctl;
1664
1665 dpa_ctl = I915_READ(DP_A);
1666 dpa_ctl |= DP_PLL_ENABLE;
1667 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson5ddb9542010-08-07 11:01:36 +01001668 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001669 udelay(200);
1670}
1671
1672
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001673static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001674{
1675 struct drm_device *dev = crtc->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 u32 dpa_ctl;
1678
Zhao Yakui28c97732009-10-09 11:39:41 +08001679 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001680 dpa_ctl = I915_READ(DP_A);
1681 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1682
1683 if (clock < 200000) {
1684 u32 temp;
1685 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1686 /* workaround for 160Mhz:
1687 1) program 0x4600c bits 15:0 = 0x8124
1688 2) program 0x46010 bit 0 = 1
1689 3) program 0x46034 bit 24 = 1
1690 4) program 0x64000 bit 14 = 1
1691 */
1692 temp = I915_READ(0x4600c);
1693 temp &= 0xffff0000;
1694 I915_WRITE(0x4600c, temp | 0x8124);
1695
1696 temp = I915_READ(0x46010);
1697 I915_WRITE(0x46010, temp | 1);
1698
1699 temp = I915_READ(0x46034);
1700 I915_WRITE(0x46034, temp | (1 << 24));
1701 } else {
1702 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1703 }
1704 I915_WRITE(DP_A, dpa_ctl);
1705
1706 udelay(500);
1707}
1708
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001709/* The FDI link training functions for ILK/Ibexpeak. */
1710static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1711{
1712 struct drm_device *dev = crtc->dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1715 int pipe = intel_crtc->pipe;
1716 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1717 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1718 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1719 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1720 u32 temp, tries = 0;
1721
Adam Jacksone1a44742010-06-25 15:32:14 -04001722 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1723 for train result */
1724 temp = I915_READ(fdi_rx_imr_reg);
1725 temp &= ~FDI_RX_SYMBOL_LOCK;
1726 temp &= ~FDI_RX_BIT_LOCK;
1727 I915_WRITE(fdi_rx_imr_reg, temp);
1728 I915_READ(fdi_rx_imr_reg);
1729 udelay(150);
1730
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001731 /* enable CPU FDI TX and PCH FDI RX */
1732 temp = I915_READ(fdi_tx_reg);
1733 temp |= FDI_TX_ENABLE;
Adam Jackson77ffb592010-04-12 11:38:44 -04001734 temp &= ~(7 << 19);
1735 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001736 temp &= ~FDI_LINK_TRAIN_NONE;
1737 temp |= FDI_LINK_TRAIN_PATTERN_1;
1738 I915_WRITE(fdi_tx_reg, temp);
1739 I915_READ(fdi_tx_reg);
1740
1741 temp = I915_READ(fdi_rx_reg);
1742 temp &= ~FDI_LINK_TRAIN_NONE;
1743 temp |= FDI_LINK_TRAIN_PATTERN_1;
1744 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1745 I915_READ(fdi_rx_reg);
1746 udelay(150);
1747
Adam Jacksone1a44742010-06-25 15:32:14 -04001748 for (tries = 0; tries < 5; tries++) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001749 temp = I915_READ(fdi_rx_iir_reg);
1750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1751
1752 if ((temp & FDI_RX_BIT_LOCK)) {
1753 DRM_DEBUG_KMS("FDI train 1 done.\n");
1754 I915_WRITE(fdi_rx_iir_reg,
1755 temp | FDI_RX_BIT_LOCK);
1756 break;
1757 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001758 }
Adam Jacksone1a44742010-06-25 15:32:14 -04001759 if (tries == 5)
1760 DRM_DEBUG_KMS("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001761
1762 /* Train 2 */
1763 temp = I915_READ(fdi_tx_reg);
1764 temp &= ~FDI_LINK_TRAIN_NONE;
1765 temp |= FDI_LINK_TRAIN_PATTERN_2;
1766 I915_WRITE(fdi_tx_reg, temp);
1767
1768 temp = I915_READ(fdi_rx_reg);
1769 temp &= ~FDI_LINK_TRAIN_NONE;
1770 temp |= FDI_LINK_TRAIN_PATTERN_2;
1771 I915_WRITE(fdi_rx_reg, temp);
1772 udelay(150);
1773
1774 tries = 0;
1775
Adam Jacksone1a44742010-06-25 15:32:14 -04001776 for (tries = 0; tries < 5; tries++) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001777 temp = I915_READ(fdi_rx_iir_reg);
1778 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1779
1780 if (temp & FDI_RX_SYMBOL_LOCK) {
1781 I915_WRITE(fdi_rx_iir_reg,
1782 temp | FDI_RX_SYMBOL_LOCK);
1783 DRM_DEBUG_KMS("FDI train 2 done.\n");
1784 break;
1785 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001786 }
Adam Jacksone1a44742010-06-25 15:32:14 -04001787 if (tries == 5)
1788 DRM_DEBUG_KMS("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001789
1790 DRM_DEBUG_KMS("FDI train done\n");
1791}
1792
1793static int snb_b_fdi_train_param [] = {
1794 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1795 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1796 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1797 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1798};
1799
1800/* The FDI link training functions for SNB/Cougarpoint. */
1801static void gen6_fdi_link_train(struct drm_crtc *crtc)
1802{
1803 struct drm_device *dev = crtc->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 int pipe = intel_crtc->pipe;
1807 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1808 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1809 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1810 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1811 u32 temp, i;
1812
Adam Jacksone1a44742010-06-25 15:32:14 -04001813 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1814 for train result */
1815 temp = I915_READ(fdi_rx_imr_reg);
1816 temp &= ~FDI_RX_SYMBOL_LOCK;
1817 temp &= ~FDI_RX_BIT_LOCK;
1818 I915_WRITE(fdi_rx_imr_reg, temp);
1819 I915_READ(fdi_rx_imr_reg);
1820 udelay(150);
1821
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001822 /* enable CPU FDI TX and PCH FDI RX */
1823 temp = I915_READ(fdi_tx_reg);
1824 temp |= FDI_TX_ENABLE;
Adam Jackson77ffb592010-04-12 11:38:44 -04001825 temp &= ~(7 << 19);
1826 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001827 temp &= ~FDI_LINK_TRAIN_NONE;
1828 temp |= FDI_LINK_TRAIN_PATTERN_1;
1829 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1830 /* SNB-B */
1831 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1832 I915_WRITE(fdi_tx_reg, temp);
1833 I915_READ(fdi_tx_reg);
1834
1835 temp = I915_READ(fdi_rx_reg);
1836 if (HAS_PCH_CPT(dev)) {
1837 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1838 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1839 } else {
1840 temp &= ~FDI_LINK_TRAIN_NONE;
1841 temp |= FDI_LINK_TRAIN_PATTERN_1;
1842 }
1843 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1844 I915_READ(fdi_rx_reg);
1845 udelay(150);
1846
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001847 for (i = 0; i < 4; i++ ) {
1848 temp = I915_READ(fdi_tx_reg);
1849 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850 temp |= snb_b_fdi_train_param[i];
1851 I915_WRITE(fdi_tx_reg, temp);
1852 udelay(500);
1853
1854 temp = I915_READ(fdi_rx_iir_reg);
1855 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1856
1857 if (temp & FDI_RX_BIT_LOCK) {
1858 I915_WRITE(fdi_rx_iir_reg,
1859 temp | FDI_RX_BIT_LOCK);
1860 DRM_DEBUG_KMS("FDI train 1 done.\n");
1861 break;
1862 }
1863 }
1864 if (i == 4)
1865 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1866
1867 /* Train 2 */
1868 temp = I915_READ(fdi_tx_reg);
1869 temp &= ~FDI_LINK_TRAIN_NONE;
1870 temp |= FDI_LINK_TRAIN_PATTERN_2;
1871 if (IS_GEN6(dev)) {
1872 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1873 /* SNB-B */
1874 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1875 }
1876 I915_WRITE(fdi_tx_reg, temp);
1877
1878 temp = I915_READ(fdi_rx_reg);
1879 if (HAS_PCH_CPT(dev)) {
1880 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1881 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1882 } else {
1883 temp &= ~FDI_LINK_TRAIN_NONE;
1884 temp |= FDI_LINK_TRAIN_PATTERN_2;
1885 }
1886 I915_WRITE(fdi_rx_reg, temp);
1887 udelay(150);
1888
1889 for (i = 0; i < 4; i++ ) {
1890 temp = I915_READ(fdi_tx_reg);
1891 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1892 temp |= snb_b_fdi_train_param[i];
1893 I915_WRITE(fdi_tx_reg, temp);
1894 udelay(500);
1895
1896 temp = I915_READ(fdi_rx_iir_reg);
1897 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1898
1899 if (temp & FDI_RX_SYMBOL_LOCK) {
1900 I915_WRITE(fdi_rx_iir_reg,
1901 temp | FDI_RX_SYMBOL_LOCK);
1902 DRM_DEBUG_KMS("FDI train 2 done.\n");
1903 break;
1904 }
1905 }
1906 if (i == 4)
1907 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1908
1909 DRM_DEBUG_KMS("FDI train done.\n");
1910}
1911
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001912static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08001913{
1914 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1917 int pipe = intel_crtc->pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08001918 int plane = intel_crtc->plane;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001919 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1920 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1921 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1922 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1923 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1924 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001925 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1926 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
Zhenyu Wang249c0e62009-07-24 01:00:29 +08001927 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001928 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001929 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1930 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1931 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1932 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1933 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1934 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1935 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1936 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1937 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1938 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1939 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1940 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001941 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001942 u32 temp;
Zhao Yakui8faf3b32010-01-04 16:29:31 +08001943 u32 pipe_bpc;
1944
1945 temp = I915_READ(pipeconf_reg);
1946 pipe_bpc = temp & PIPE_BPC_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08001947
1948 /* XXX: When our outputs are all unaware of DPMS modes other than off
1949 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1950 */
1951 switch (mode) {
1952 case DRM_MODE_DPMS_ON:
1953 case DRM_MODE_DPMS_STANDBY:
1954 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01001955 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08001956
1957 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1958 temp = I915_READ(PCH_LVDS);
1959 if ((temp & LVDS_PORT_EN) == 0) {
1960 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1961 POSTING_READ(PCH_LVDS);
1962 }
1963 }
1964
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001965 if (HAS_eDP) {
1966 /* enable eDP PLL */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001967 ironlake_enable_pll_edp(crtc);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001968 } else {
Zhenyu Wang2c072452009-06-05 15:38:42 +08001969
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001970 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1971 temp = I915_READ(fdi_rx_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08001972 /*
1973 * make the BPC in FDI Rx be consistent with that in
1974 * pipeconf reg.
1975 */
1976 temp &= ~(0x7 << 16);
1977 temp |= (pipe_bpc << 11);
Adam Jackson77ffb592010-04-12 11:38:44 -04001978 temp &= ~(7 << 19);
1979 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1980 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001981 I915_READ(fdi_rx_reg);
1982 udelay(200);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001983
Zhenyu Wang8db9d772010-04-07 16:15:54 +08001984 /* Switch from Rawclk to PCDclk */
1985 temp = I915_READ(fdi_rx_reg);
1986 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
Zhenyu Wang2c072452009-06-05 15:38:42 +08001987 I915_READ(fdi_rx_reg);
1988 udelay(200);
1989
Adam Jacksonf2b115e2009-12-03 17:14:42 -05001990 /* Enable CPU FDI TX PLL, always on for Ironlake */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001991 temp = I915_READ(fdi_tx_reg);
1992 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1993 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1994 I915_READ(fdi_tx_reg);
1995 udelay(100);
1996 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08001997 }
1998
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08001999 /* Enable panel fitting for LVDS */
Zhao Yakui1fc79472010-07-19 09:43:12 +01002000 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2001 || HAS_eDP || intel_pch_has_edp(crtc)) {
Chris Wilson1d8e1c72010-08-07 11:01:28 +01002002 if (dev_priv->pch_pf_size) {
2003 temp = I915_READ(pf_ctl_reg);
2004 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2005 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2006 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2007 } else
2008 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
Zhenyu Wang8dd81a32009-09-19 14:54:09 +08002009 }
2010
Zhenyu Wang2c072452009-06-05 15:38:42 +08002011 /* Enable CPU pipe */
2012 temp = I915_READ(pipeconf_reg);
2013 if ((temp & PIPEACONF_ENABLE) == 0) {
2014 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2015 I915_READ(pipeconf_reg);
2016 udelay(100);
2017 }
2018
2019 /* configure and enable CPU plane */
2020 temp = I915_READ(dspcntr_reg);
2021 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2022 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2023 /* Flush the plane changes */
2024 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2025 }
2026
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002027 if (!HAS_eDP) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002028 /* For PCH output, training FDI link */
2029 if (IS_GEN6(dev))
2030 gen6_fdi_link_train(crtc);
2031 else
2032 ironlake_fdi_link_train(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002033
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002034 /* enable PCH DPLL */
2035 temp = I915_READ(pch_dpll_reg);
2036 if ((temp & DPLL_VCO_ENABLE) == 0) {
2037 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2038 I915_READ(pch_dpll_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002039 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002040 udelay(200);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002041
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002042 if (HAS_PCH_CPT(dev)) {
2043 /* Be sure PCH DPLL SEL is set */
2044 temp = I915_READ(PCH_DPLL_SEL);
2045 if (trans_dpll_sel == 0 &&
2046 (temp & TRANSA_DPLL_ENABLE) == 0)
2047 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2048 else if (trans_dpll_sel == 1 &&
2049 (temp & TRANSB_DPLL_ENABLE) == 0)
2050 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2051 I915_WRITE(PCH_DPLL_SEL, temp);
2052 I915_READ(PCH_DPLL_SEL);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002053 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002054
2055 /* set transcoder timing */
2056 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2057 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2058 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2059
2060 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2061 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2062 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2063
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002064 /* enable normal train */
2065 temp = I915_READ(fdi_tx_reg);
2066 temp &= ~FDI_LINK_TRAIN_NONE;
2067 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2068 FDI_TX_ENHANCE_FRAME_ENABLE);
2069 I915_READ(fdi_tx_reg);
2070
2071 temp = I915_READ(fdi_rx_reg);
2072 if (HAS_PCH_CPT(dev)) {
2073 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2074 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2075 } else {
2076 temp &= ~FDI_LINK_TRAIN_NONE;
2077 temp |= FDI_LINK_TRAIN_NONE;
2078 }
2079 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2080 I915_READ(fdi_rx_reg);
2081
2082 /* wait one idle pattern time */
2083 udelay(100);
2084
Zhenyu Wange3421a12010-04-08 09:43:27 +08002085 /* For PCH DP, enable TRANS_DP_CTL */
2086 if (HAS_PCH_CPT(dev) &&
2087 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2088 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2089 int reg;
2090
2091 reg = I915_READ(trans_dp_ctl);
Chris Wilson94113ce2010-08-04 11:25:21 +01002092 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2093 TRANS_DP_SYNC_MASK);
2094 reg |= (TRANS_DP_OUTPUT_ENABLE |
2095 TRANS_DP_ENH_FRAMING);
Adam Jacksond6d95262010-07-16 14:46:30 -04002096
2097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2098 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2100 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002101
2102 switch (intel_trans_dp_port_sel(crtc)) {
2103 case PCH_DP_B:
2104 reg |= TRANS_DP_PORT_SEL_B;
2105 break;
2106 case PCH_DP_C:
2107 reg |= TRANS_DP_PORT_SEL_C;
2108 break;
2109 case PCH_DP_D:
2110 reg |= TRANS_DP_PORT_SEL_D;
2111 break;
2112 default:
2113 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2114 reg |= TRANS_DP_PORT_SEL_B;
2115 break;
2116 }
2117
2118 I915_WRITE(trans_dp_ctl, reg);
2119 POSTING_READ(trans_dp_ctl);
2120 }
2121
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002122 /* enable PCH transcoder */
2123 temp = I915_READ(transconf_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08002124 /*
2125 * make the BPC in transcoder be consistent with
2126 * that in pipeconf reg.
2127 */
2128 temp &= ~PIPE_BPC_MASK;
2129 temp |= pipe_bpc;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002130 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2131 I915_READ(transconf_reg);
2132
Chris Wilson913d8d12010-08-07 11:01:35 +01002133 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2134 DRM_ERROR("failed to enable transcoder\n");
Zhenyu Wang2c072452009-06-05 15:38:42 +08002135 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002136
2137 intel_crtc_load_lut(crtc);
2138
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002139 intel_update_fbc(crtc, &crtc->mode);
Chris Wilson868dc582010-08-07 11:01:31 +01002140 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002141
Zhenyu Wang2c072452009-06-05 15:38:42 +08002142 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01002143 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002144
Li Pengc062df62010-01-23 00:12:58 +08002145 drm_vblank_off(dev, pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002146 /* Disable display plane */
2147 temp = I915_READ(dspcntr_reg);
2148 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2149 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2150 /* Flush the plane changes */
2151 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2152 I915_READ(dspbase_reg);
2153 }
2154
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002155 if (dev_priv->cfb_plane == plane &&
2156 dev_priv->display.disable_fbc)
2157 dev_priv->display.disable_fbc(dev);
2158
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002159 i915_disable_vga(dev);
2160
Zhenyu Wang2c072452009-06-05 15:38:42 +08002161 /* disable cpu pipe, disable after all planes disabled */
2162 temp = I915_READ(pipeconf_reg);
2163 if ((temp & PIPEACONF_ENABLE) != 0) {
2164 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
Chris Wilson913d8d12010-08-07 11:01:35 +01002165
Zhenyu Wang2c072452009-06-05 15:38:42 +08002166 /* wait for cpu pipe off, pipe state */
Chris Wilson913d8d12010-08-07 11:01:35 +01002167 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2168 DRM_ERROR("failed to turn off cpu pipe\n");
Zhenyu Wang2c072452009-06-05 15:38:42 +08002169 } else
Zhao Yakui28c97732009-10-09 11:39:41 +08002170 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002171
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002172 udelay(100);
2173
2174 /* Disable PF */
2175 temp = I915_READ(pf_ctl_reg);
2176 if ((temp & PF_ENABLE) != 0) {
2177 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2178 I915_READ(pf_ctl_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002179 }
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002180 I915_WRITE(pf_win_size, 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002181 POSTING_READ(pf_win_size);
2182
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002183
Zhenyu Wang2c072452009-06-05 15:38:42 +08002184 /* disable CPU FDI tx and PCH FDI rx */
2185 temp = I915_READ(fdi_tx_reg);
2186 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2187 I915_READ(fdi_tx_reg);
2188
2189 temp = I915_READ(fdi_rx_reg);
Zhao Yakui8faf3b32010-01-04 16:29:31 +08002190 /* BPC in FDI rx is consistent with that in pipeconf */
2191 temp &= ~(0x07 << 16);
2192 temp |= (pipe_bpc << 11);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002193 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2194 I915_READ(fdi_rx_reg);
2195
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002196 udelay(100);
2197
Zhenyu Wang2c072452009-06-05 15:38:42 +08002198 /* still set train pattern 1 */
2199 temp = I915_READ(fdi_tx_reg);
2200 temp &= ~FDI_LINK_TRAIN_NONE;
2201 temp |= FDI_LINK_TRAIN_PATTERN_1;
2202 I915_WRITE(fdi_tx_reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002203 POSTING_READ(fdi_tx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002204
2205 temp = I915_READ(fdi_rx_reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002206 if (HAS_PCH_CPT(dev)) {
2207 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2208 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2209 } else {
2210 temp &= ~FDI_LINK_TRAIN_NONE;
2211 temp |= FDI_LINK_TRAIN_PATTERN_1;
2212 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002213 I915_WRITE(fdi_rx_reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002214 POSTING_READ(fdi_rx_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002215
Zhenyu Wang249c0e62009-07-24 01:00:29 +08002216 udelay(100);
2217
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002218 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2219 temp = I915_READ(PCH_LVDS);
2220 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2221 I915_READ(PCH_LVDS);
2222 udelay(100);
2223 }
2224
Zhenyu Wang2c072452009-06-05 15:38:42 +08002225 /* disable PCH transcoder */
2226 temp = I915_READ(transconf_reg);
2227 if ((temp & TRANS_ENABLE) != 0) {
2228 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
Chris Wilson913d8d12010-08-07 11:01:35 +01002229
Zhenyu Wang2c072452009-06-05 15:38:42 +08002230 /* wait for PCH transcoder off, transcoder state */
Chris Wilson913d8d12010-08-07 11:01:35 +01002231 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2232 DRM_ERROR("failed to disable transcoder\n");
Zhenyu Wang2c072452009-06-05 15:38:42 +08002233 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002234
Zhao Yakui8faf3b32010-01-04 16:29:31 +08002235 temp = I915_READ(transconf_reg);
2236 /* BPC in transcoder is consistent with that in pipeconf */
2237 temp &= ~PIPE_BPC_MASK;
2238 temp |= pipe_bpc;
2239 I915_WRITE(transconf_reg, temp);
2240 I915_READ(transconf_reg);
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002241 udelay(100);
2242
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002243 if (HAS_PCH_CPT(dev)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002244 /* disable TRANS_DP_CTL */
2245 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2246 int reg;
2247
2248 reg = I915_READ(trans_dp_ctl);
2249 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2250 I915_WRITE(trans_dp_ctl, reg);
2251 POSTING_READ(trans_dp_ctl);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002252
2253 /* disable DPLL_SEL */
2254 temp = I915_READ(PCH_DPLL_SEL);
2255 if (trans_dpll_sel == 0)
2256 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2257 else
2258 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2259 I915_WRITE(PCH_DPLL_SEL, temp);
2260 I915_READ(PCH_DPLL_SEL);
2261
2262 }
2263
Zhenyu Wang2c072452009-06-05 15:38:42 +08002264 /* disable PCH DPLL */
2265 temp = I915_READ(pch_dpll_reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002266 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2267 I915_READ(pch_dpll_reg);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002268
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002269 if (HAS_eDP) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002270 ironlake_disable_pll_edp(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002271 }
2272
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002273 /* Switch from PCDclk to Rawclk */
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002274 temp = I915_READ(fdi_rx_reg);
2275 temp &= ~FDI_SEL_PCDCLK;
2276 I915_WRITE(fdi_rx_reg, temp);
2277 I915_READ(fdi_rx_reg);
2278
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002279 /* Disable CPU FDI TX PLL */
2280 temp = I915_READ(fdi_tx_reg);
2281 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2282 I915_READ(fdi_tx_reg);
2283 udelay(100);
2284
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002285 temp = I915_READ(fdi_rx_reg);
2286 temp &= ~FDI_RX_PLL_ENABLE;
2287 I915_WRITE(fdi_rx_reg, temp);
2288 I915_READ(fdi_rx_reg);
2289
Zhenyu Wang2c072452009-06-05 15:38:42 +08002290 /* Wait for the clocks to turn off. */
Zhenyu Wang1b3c7a42009-11-25 13:09:38 +08002291 udelay(100);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002292 break;
2293 }
2294}
2295
Daniel Vetter02e792f2009-09-15 22:57:34 +02002296static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2297{
2298 struct intel_overlay *overlay;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002299 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +02002300
2301 if (!enable && intel_crtc->overlay) {
2302 overlay = intel_crtc->overlay;
2303 mutex_lock(&overlay->dev->struct_mutex);
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002304 for (;;) {
2305 ret = intel_overlay_switch_off(overlay);
2306 if (ret == 0)
2307 break;
2308
2309 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2310 if (ret != 0) {
2311 /* overlay doesn't react anymore. Usually
2312 * results in a black screen and an unkillable
2313 * X server. */
2314 BUG();
2315 overlay->hw_wedged = HW_WEDGED;
2316 break;
2317 }
2318 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02002319 mutex_unlock(&overlay->dev->struct_mutex);
2320 }
2321 /* Let userspace switch the overlay on again. In most cases userspace
2322 * has to recompute where to put it anyway. */
2323
2324 return;
2325}
2326
Zhenyu Wang2c072452009-06-05 15:38:42 +08002327static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2328{
2329 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07002333 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08002334 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
Jesse Barnes80824002009-09-10 15:28:06 -07002335 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2336 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
Jesse Barnes79e53942008-11-07 14:24:08 -08002337 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2338 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08002339
2340 /* XXX: When our outputs are all unaware of DPMS modes other than off
2341 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2342 */
2343 switch (mode) {
2344 case DRM_MODE_DPMS_ON:
2345 case DRM_MODE_DPMS_STANDBY:
2346 case DRM_MODE_DPMS_SUSPEND:
2347 /* Enable the DPLL */
2348 temp = I915_READ(dpll_reg);
2349 if ((temp & DPLL_VCO_ENABLE) == 0) {
2350 I915_WRITE(dpll_reg, temp);
2351 I915_READ(dpll_reg);
2352 /* Wait for the clocks to stabilize. */
2353 udelay(150);
2354 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2355 I915_READ(dpll_reg);
2356 /* Wait for the clocks to stabilize. */
2357 udelay(150);
2358 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2359 I915_READ(dpll_reg);
2360 /* Wait for the clocks to stabilize. */
2361 udelay(150);
2362 }
2363
2364 /* Enable the pipe */
2365 temp = I915_READ(pipeconf_reg);
2366 if ((temp & PIPEACONF_ENABLE) == 0)
2367 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2368
2369 /* Enable the plane */
2370 temp = I915_READ(dspcntr_reg);
2371 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2372 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2373 /* Flush the plane changes */
2374 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2375 }
2376
2377 intel_crtc_load_lut(crtc);
2378
Jesse Barnes74dff282009-09-14 15:39:40 -07002379 if ((IS_I965G(dev) || plane == 0))
2380 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnes80824002009-09-10 15:28:06 -07002381
Jesse Barnes79e53942008-11-07 14:24:08 -08002382 /* Give the overlay scaler a chance to enable if it's on this pipe */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002383 intel_crtc_dpms_overlay(intel_crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08002384 break;
2385 case DRM_MODE_DPMS_OFF:
2386 /* Give the overlay scaler a chance to disable if it's on this pipe */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002387 intel_crtc_dpms_overlay(intel_crtc, false);
Li Peng778c9022009-11-09 12:51:22 +08002388 drm_vblank_off(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08002389
Jesse Barnese70236a2009-09-21 10:42:27 -07002390 if (dev_priv->cfb_plane == plane &&
2391 dev_priv->display.disable_fbc)
2392 dev_priv->display.disable_fbc(dev);
Jesse Barnes80824002009-09-10 15:28:06 -07002393
Jesse Barnes79e53942008-11-07 14:24:08 -08002394 /* Disable the VGA plane that we never use */
Zhenyu Wang24f119c2009-07-24 01:00:28 +08002395 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002396
2397 /* Disable display plane */
2398 temp = I915_READ(dspcntr_reg);
2399 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2400 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2401 /* Flush the plane changes */
2402 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2403 I915_READ(dspbase_reg);
2404 }
2405
2406 if (!IS_I9XX(dev)) {
2407 /* Wait for vblank for the disable to take effect */
2408 intel_wait_for_vblank(dev);
2409 }
2410
Jesse Barnesb690e962010-07-19 13:53:12 -07002411 /* Don't disable pipe A or pipe A PLLs if needed */
2412 if (pipeconf_reg == PIPEACONF &&
2413 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2414 goto skip_pipe_off;
2415
Jesse Barnes79e53942008-11-07 14:24:08 -08002416 /* Next, disable display pipes */
2417 temp = I915_READ(pipeconf_reg);
2418 if ((temp & PIPEACONF_ENABLE) != 0) {
2419 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2420 I915_READ(pipeconf_reg);
2421 }
2422
2423 /* Wait for vblank for the disable to take effect. */
2424 intel_wait_for_vblank(dev);
2425
2426 temp = I915_READ(dpll_reg);
2427 if ((temp & DPLL_VCO_ENABLE) != 0) {
2428 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2429 I915_READ(dpll_reg);
2430 }
Jesse Barnesb690e962010-07-19 13:53:12 -07002431 skip_pipe_off:
Jesse Barnes79e53942008-11-07 14:24:08 -08002432 /* Wait for the clocks to turn off. */
2433 udelay(150);
2434 break;
2435 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002436}
2437
2438/**
2439 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08002440 */
2441static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2442{
2443 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07002444 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002445 struct drm_i915_master_private *master_priv;
2446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447 int pipe = intel_crtc->pipe;
2448 bool enabled;
2449
Chris Wilsondebcadd2010-08-07 11:01:33 +01002450 intel_crtc->dpms_mode = mode;
2451 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2452
2453 /* When switching on the display, ensure that SR is disabled
2454 * with multiple pipes prior to enabling to new pipe.
2455 *
2456 * When switching off the display, make sure the cursor is
2457 * properly hidden prior to disabling the pipe.
2458 */
2459 if (mode == DRM_MODE_DPMS_ON)
2460 intel_update_watermarks(dev);
2461 else
2462 intel_crtc_update_cursor(crtc);
2463
Jesse Barnese70236a2009-09-21 10:42:27 -07002464 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002465
Chris Wilsondebcadd2010-08-07 11:01:33 +01002466 if (mode == DRM_MODE_DPMS_ON)
2467 intel_crtc_update_cursor(crtc);
2468 else
2469 intel_update_watermarks(dev);
Chris Wilson87f8ebf2010-08-04 12:24:42 +01002470
Jesse Barnes79e53942008-11-07 14:24:08 -08002471 if (!dev->primary->master)
2472 return;
2473
2474 master_priv = dev->primary->master->driver_priv;
2475 if (!master_priv->sarea_priv)
2476 return;
2477
2478 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2479
2480 switch (pipe) {
2481 case 0:
2482 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2483 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2484 break;
2485 case 1:
2486 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2487 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2488 break;
2489 default:
2490 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2491 break;
2492 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002493}
2494
2495static void intel_crtc_prepare (struct drm_crtc *crtc)
2496{
2497 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2498 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2499}
2500
2501static void intel_crtc_commit (struct drm_crtc *crtc)
2502{
2503 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2504 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2505}
2506
2507void intel_encoder_prepare (struct drm_encoder *encoder)
2508{
2509 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2510 /* lvds has its own version of prepare see intel_lvds_prepare */
2511 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2512}
2513
2514void intel_encoder_commit (struct drm_encoder *encoder)
2515{
2516 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2517 /* lvds has its own version of commit see intel_lvds_commit */
2518 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2519}
2520
Chris Wilsonea5b2132010-08-04 13:50:23 +01002521void intel_encoder_destroy(struct drm_encoder *encoder)
2522{
2523 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2524
2525 if (intel_encoder->ddc_bus)
2526 intel_i2c_destroy(intel_encoder->ddc_bus);
2527
2528 if (intel_encoder->i2c_bus)
2529 intel_i2c_destroy(intel_encoder->i2c_bus);
2530
2531 drm_encoder_cleanup(encoder);
2532 kfree(intel_encoder);
2533}
2534
Jesse Barnes79e53942008-11-07 14:24:08 -08002535static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2536 struct drm_display_mode *mode,
2537 struct drm_display_mode *adjusted_mode)
2538{
Zhenyu Wang2c072452009-06-05 15:38:42 +08002539 struct drm_device *dev = crtc->dev;
Eric Anholtbad720f2009-10-22 16:11:14 -07002540 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08002541 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07002542 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2543 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002544 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002545 return true;
2546}
2547
Jesse Barnese70236a2009-09-21 10:42:27 -07002548static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08002549{
Jesse Barnese70236a2009-09-21 10:42:27 -07002550 return 400000;
2551}
Jesse Barnes79e53942008-11-07 14:24:08 -08002552
Jesse Barnese70236a2009-09-21 10:42:27 -07002553static int i915_get_display_clock_speed(struct drm_device *dev)
2554{
2555 return 333000;
2556}
Jesse Barnes79e53942008-11-07 14:24:08 -08002557
Jesse Barnese70236a2009-09-21 10:42:27 -07002558static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2559{
2560 return 200000;
2561}
Jesse Barnes79e53942008-11-07 14:24:08 -08002562
Jesse Barnese70236a2009-09-21 10:42:27 -07002563static int i915gm_get_display_clock_speed(struct drm_device *dev)
2564{
2565 u16 gcfgc = 0;
2566
2567 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2568
2569 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08002570 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07002571 else {
2572 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2573 case GC_DISPLAY_CLOCK_333_MHZ:
2574 return 333000;
2575 default:
2576 case GC_DISPLAY_CLOCK_190_200_MHZ:
2577 return 190000;
2578 }
2579 }
2580}
Jesse Barnes79e53942008-11-07 14:24:08 -08002581
Jesse Barnese70236a2009-09-21 10:42:27 -07002582static int i865_get_display_clock_speed(struct drm_device *dev)
2583{
2584 return 266000;
2585}
2586
2587static int i855_get_display_clock_speed(struct drm_device *dev)
2588{
2589 u16 hpllcc = 0;
2590 /* Assume that the hardware is in the high speed state. This
2591 * should be the default.
2592 */
2593 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2594 case GC_CLOCK_133_200:
2595 case GC_CLOCK_100_200:
2596 return 200000;
2597 case GC_CLOCK_166_250:
2598 return 250000;
2599 case GC_CLOCK_100_133:
2600 return 133000;
2601 }
2602
2603 /* Shouldn't happen */
2604 return 0;
2605}
2606
2607static int i830_get_display_clock_speed(struct drm_device *dev)
2608{
2609 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08002610}
2611
Jesse Barnes79e53942008-11-07 14:24:08 -08002612/**
2613 * Return the pipe currently connected to the panel fitter,
2614 * or -1 if the panel fitter is not present or not in use
2615 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002616int intel_panel_fitter_pipe (struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08002617{
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 u32 pfit_control;
2620
2621 /* i830 doesn't have a panel fitter */
2622 if (IS_I830(dev))
2623 return -1;
2624
2625 pfit_control = I915_READ(PFIT_CONTROL);
2626
2627 /* See if the panel fitter is in use */
2628 if ((pfit_control & PFIT_ENABLE) == 0)
2629 return -1;
2630
2631 /* 965 can place panel fitter on either pipe */
2632 if (IS_I965G(dev))
2633 return (pfit_control >> 29) & 0x3;
2634
2635 /* older chips can only use pipe 1 */
2636 return 1;
2637}
2638
Zhenyu Wang2c072452009-06-05 15:38:42 +08002639struct fdi_m_n {
2640 u32 tu;
2641 u32 gmch_m;
2642 u32 gmch_n;
2643 u32 link_m;
2644 u32 link_n;
2645};
2646
2647static void
2648fdi_reduce_ratio(u32 *num, u32 *den)
2649{
2650 while (*num > 0xffffff || *den > 0xffffff) {
2651 *num >>= 1;
2652 *den >>= 1;
2653 }
2654}
2655
2656#define DATA_N 0x800000
2657#define LINK_N 0x80000
2658
2659static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002660ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2661 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08002662{
2663 u64 temp;
2664
2665 m_n->tu = 64; /* default size */
2666
2667 temp = (u64) DATA_N * pixel_clock;
2668 temp = div_u64(temp, link_clock);
Zhenyu Wang58a27472009-09-25 08:01:28 +00002669 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2670 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
Zhenyu Wang2c072452009-06-05 15:38:42 +08002671 m_n->gmch_n = DATA_N;
2672 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2673
2674 temp = (u64) LINK_N * pixel_clock;
2675 m_n->link_m = div_u64(temp, link_clock);
2676 m_n->link_n = LINK_N;
2677 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2678}
2679
2680
Shaohua Li7662c8b2009-06-26 11:23:55 +08002681struct intel_watermark_params {
2682 unsigned long fifo_size;
2683 unsigned long max_wm;
2684 unsigned long default_wm;
2685 unsigned long guard_size;
2686 unsigned long cacheline_size;
2687};
2688
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002689/* Pineview has different values for various configs */
2690static struct intel_watermark_params pineview_display_wm = {
2691 PINEVIEW_DISPLAY_FIFO,
2692 PINEVIEW_MAX_WM,
2693 PINEVIEW_DFT_WM,
2694 PINEVIEW_GUARD_WM,
2695 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002696};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002697static struct intel_watermark_params pineview_display_hplloff_wm = {
2698 PINEVIEW_DISPLAY_FIFO,
2699 PINEVIEW_MAX_WM,
2700 PINEVIEW_DFT_HPLLOFF_WM,
2701 PINEVIEW_GUARD_WM,
2702 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002703};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002704static struct intel_watermark_params pineview_cursor_wm = {
2705 PINEVIEW_CURSOR_FIFO,
2706 PINEVIEW_CURSOR_MAX_WM,
2707 PINEVIEW_CURSOR_DFT_WM,
2708 PINEVIEW_CURSOR_GUARD_WM,
2709 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002710};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002711static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2712 PINEVIEW_CURSOR_FIFO,
2713 PINEVIEW_CURSOR_MAX_WM,
2714 PINEVIEW_CURSOR_DFT_WM,
2715 PINEVIEW_CURSOR_GUARD_WM,
2716 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08002717};
Jesse Barnes0e442c62009-10-19 10:09:33 +09002718static struct intel_watermark_params g4x_wm_info = {
2719 G4X_FIFO_SIZE,
2720 G4X_MAX_WM,
2721 G4X_MAX_WM,
2722 2,
2723 G4X_FIFO_LINE_SIZE,
2724};
Zhao Yakui4fe5e612010-06-12 14:32:25 +08002725static struct intel_watermark_params g4x_cursor_wm_info = {
2726 I965_CURSOR_FIFO,
2727 I965_CURSOR_MAX_WM,
2728 I965_CURSOR_DFT_WM,
2729 2,
2730 G4X_FIFO_LINE_SIZE,
2731};
2732static struct intel_watermark_params i965_cursor_wm_info = {
2733 I965_CURSOR_FIFO,
2734 I965_CURSOR_MAX_WM,
2735 I965_CURSOR_DFT_WM,
2736 2,
2737 I915_FIFO_LINE_SIZE,
2738};
Shaohua Li7662c8b2009-06-26 11:23:55 +08002739static struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08002740 I945_FIFO_SIZE,
2741 I915_MAX_WM,
2742 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002743 2,
2744 I915_FIFO_LINE_SIZE
2745};
2746static struct intel_watermark_params i915_wm_info = {
2747 I915_FIFO_SIZE,
2748 I915_MAX_WM,
2749 1,
2750 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002751 I915_FIFO_LINE_SIZE
2752};
2753static struct intel_watermark_params i855_wm_info = {
2754 I855GM_FIFO_SIZE,
2755 I915_MAX_WM,
2756 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002757 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002758 I830_FIFO_LINE_SIZE
2759};
2760static struct intel_watermark_params i830_wm_info = {
2761 I830_FIFO_SIZE,
2762 I915_MAX_WM,
2763 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002764 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08002765 I830_FIFO_LINE_SIZE
2766};
2767
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002768static struct intel_watermark_params ironlake_display_wm_info = {
2769 ILK_DISPLAY_FIFO,
2770 ILK_DISPLAY_MAXWM,
2771 ILK_DISPLAY_DFTWM,
2772 2,
2773 ILK_FIFO_LINE_SIZE
2774};
2775
Zhao Yakuic936f442010-06-12 14:32:26 +08002776static struct intel_watermark_params ironlake_cursor_wm_info = {
2777 ILK_CURSOR_FIFO,
2778 ILK_CURSOR_MAXWM,
2779 ILK_CURSOR_DFTWM,
2780 2,
2781 ILK_FIFO_LINE_SIZE
2782};
2783
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002784static struct intel_watermark_params ironlake_display_srwm_info = {
2785 ILK_DISPLAY_SR_FIFO,
2786 ILK_DISPLAY_MAX_SRWM,
2787 ILK_DISPLAY_DFT_SRWM,
2788 2,
2789 ILK_FIFO_LINE_SIZE
2790};
2791
2792static struct intel_watermark_params ironlake_cursor_srwm_info = {
2793 ILK_CURSOR_SR_FIFO,
2794 ILK_CURSOR_MAX_SRWM,
2795 ILK_CURSOR_DFT_SRWM,
2796 2,
2797 ILK_FIFO_LINE_SIZE
2798};
2799
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002800/**
2801 * intel_calculate_wm - calculate watermark level
2802 * @clock_in_khz: pixel clock
2803 * @wm: chip FIFO params
2804 * @pixel_size: display pixel size
2805 * @latency_ns: memory latency for the platform
2806 *
2807 * Calculate the watermark level (the level at which the display plane will
2808 * start fetching from memory again). Each chip has a different display
2809 * FIFO size and allocation, so the caller needs to figure that out and pass
2810 * in the correct intel_watermark_params structure.
2811 *
2812 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2813 * on the pixel size. When it reaches the watermark level, it'll start
2814 * fetching FIFO line sized based chunks from memory until the FIFO fills
2815 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2816 * will occur, and a display engine hang could result.
2817 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002818static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2819 struct intel_watermark_params *wm,
2820 int pixel_size,
2821 unsigned long latency_ns)
2822{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002823 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002824
Jesse Barnesd6604672009-09-11 12:25:56 -07002825 /*
2826 * Note: we need to make sure we don't overflow for various clock &
2827 * latency values.
2828 * clocks go from a few thousand to several hundred thousand.
2829 * latency is usually a few thousand
2830 */
2831 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2832 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01002833 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002834
Zhao Yakui28c97732009-10-09 11:39:41 +08002835 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002836
2837 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2838
Zhao Yakui28c97732009-10-09 11:39:41 +08002839 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002840
Jesse Barnes390c4dd2009-07-16 13:01:01 -07002841 /* Don't promote wm_size to unsigned... */
2842 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002843 wm_size = wm->max_wm;
Chris Wilsonb9421ae2010-07-19 21:46:08 +01002844 if (wm_size <= 0) {
Shaohua Li7662c8b2009-06-26 11:23:55 +08002845 wm_size = wm->default_wm;
Chris Wilsonb9421ae2010-07-19 21:46:08 +01002846 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2847 " entries required = %ld, available = %lu.\n",
2848 entries_required + wm->guard_size,
2849 wm->fifo_size);
2850 }
2851
Shaohua Li7662c8b2009-06-26 11:23:55 +08002852 return wm_size;
2853}
2854
2855struct cxsr_latency {
2856 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08002857 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002858 unsigned long fsb_freq;
2859 unsigned long mem_freq;
2860 unsigned long display_sr;
2861 unsigned long display_hpll_disable;
2862 unsigned long cursor_sr;
2863 unsigned long cursor_hpll_disable;
2864};
2865
Chris Wilson403c89f2010-08-04 15:25:31 +01002866static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08002867 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2868 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2869 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2870 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2871 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002872
Li Peng95534262010-05-18 18:58:44 +08002873 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2874 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2875 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2876 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2877 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002878
Li Peng95534262010-05-18 18:58:44 +08002879 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2880 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2881 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2882 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2883 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002884
Li Peng95534262010-05-18 18:58:44 +08002885 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2886 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2887 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2888 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2889 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002890
Li Peng95534262010-05-18 18:58:44 +08002891 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2892 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2893 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2894 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2895 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002896
Li Peng95534262010-05-18 18:58:44 +08002897 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2898 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2899 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2900 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2901 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002902};
2903
Chris Wilson403c89f2010-08-04 15:25:31 +01002904static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2905 int is_ddr3,
2906 int fsb,
2907 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002908{
Chris Wilson403c89f2010-08-04 15:25:31 +01002909 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002910 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002911
2912 if (fsb == 0 || mem == 0)
2913 return NULL;
2914
2915 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2916 latency = &cxsr_latency_table[i];
2917 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08002918 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302919 fsb == latency->fsb_freq && mem == latency->mem_freq)
2920 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002921 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302922
Zhao Yakui28c97732009-10-09 11:39:41 +08002923 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05302924
2925 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002926}
2927
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002928static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002929{
2930 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002931
2932 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01002933 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002934}
2935
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07002936/*
2937 * Latency for FIFO fetches is dependent on several factors:
2938 * - memory configuration (speed, channels)
2939 * - chipset
2940 * - current MCH state
2941 * It can be fairly high in some situations, so here we assume a fairly
2942 * pessimal value. It's a tradeoff between extra memory fetches (if we
2943 * set this value too high, the FIFO will fetch frequently to stay full)
2944 * and power consumption (set it too low to save power and we might see
2945 * FIFO underruns and display "flicker").
2946 *
2947 * A value of 5us seems to be a good balance; safe for very low end
2948 * platforms but not overly aggressive on lower latency configs.
2949 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01002950static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08002951
Jesse Barnese70236a2009-09-21 10:42:27 -07002952static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002953{
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 uint32_t dsparb = I915_READ(DSPARB);
2956 int size;
2957
Chris Wilson8de9b312010-07-19 19:59:52 +01002958 size = dsparb & 0x7f;
2959 if (plane)
2960 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002961
Zhao Yakui28c97732009-10-09 11:39:41 +08002962 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2963 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002964
2965 return size;
2966}
Shaohua Li7662c8b2009-06-26 11:23:55 +08002967
Jesse Barnese70236a2009-09-21 10:42:27 -07002968static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2969{
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 uint32_t dsparb = I915_READ(DSPARB);
2972 int size;
2973
Chris Wilson8de9b312010-07-19 19:59:52 +01002974 size = dsparb & 0x1ff;
2975 if (plane)
2976 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07002977 size >>= 1; /* Convert to cachelines */
2978
Zhao Yakui28c97732009-10-09 11:39:41 +08002979 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2980 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07002981
2982 return size;
2983}
2984
2985static int i845_get_fifo_size(struct drm_device *dev, int plane)
2986{
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 uint32_t dsparb = I915_READ(DSPARB);
2989 int size;
2990
2991 size = dsparb & 0x7f;
2992 size >>= 2; /* Convert to cachelines */
2993
Zhao Yakui28c97732009-10-09 11:39:41 +08002994 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2995 plane ? "B" : "A",
Jesse Barnese70236a2009-09-21 10:42:27 -07002996 size);
2997
2998 return size;
2999}
3000
3001static int i830_get_fifo_size(struct drm_device *dev, int plane)
3002{
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 uint32_t dsparb = I915_READ(DSPARB);
3005 int size;
3006
3007 size = dsparb & 0x7f;
3008 size >>= 1; /* Convert to cachelines */
3009
Zhao Yakui28c97732009-10-09 11:39:41 +08003010 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3011 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003012
3013 return size;
3014}
3015
Zhao Yakuid4294342010-03-22 22:45:36 +08003016static void pineview_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003017 int planeb_clock, int sr_hdisplay, int unused,
3018 int pixel_size)
Zhao Yakuid4294342010-03-22 22:45:36 +08003019{
3020 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson403c89f2010-08-04 15:25:31 +01003021 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003022 u32 reg;
3023 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003024 int sr_clock;
3025
Chris Wilson403c89f2010-08-04 15:25:31 +01003026 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003027 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003028 if (!latency) {
3029 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3030 pineview_disable_cxsr(dev);
3031 return;
3032 }
3033
3034 if (!planea_clock || !planeb_clock) {
3035 sr_clock = planea_clock ? planea_clock : planeb_clock;
3036
3037 /* Display SR */
3038 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3039 pixel_size, latency->display_sr);
3040 reg = I915_READ(DSPFW1);
3041 reg &= ~DSPFW_SR_MASK;
3042 reg |= wm << DSPFW_SR_SHIFT;
3043 I915_WRITE(DSPFW1, reg);
3044 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3045
3046 /* cursor SR */
3047 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3048 pixel_size, latency->cursor_sr);
3049 reg = I915_READ(DSPFW3);
3050 reg &= ~DSPFW_CURSOR_SR_MASK;
3051 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3052 I915_WRITE(DSPFW3, reg);
3053
3054 /* Display HPLL off SR */
3055 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3056 pixel_size, latency->display_hpll_disable);
3057 reg = I915_READ(DSPFW3);
3058 reg &= ~DSPFW_HPLL_SR_MASK;
3059 reg |= wm & DSPFW_HPLL_SR_MASK;
3060 I915_WRITE(DSPFW3, reg);
3061
3062 /* cursor HPLL off SR */
3063 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3064 pixel_size, latency->cursor_hpll_disable);
3065 reg = I915_READ(DSPFW3);
3066 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3067 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3068 I915_WRITE(DSPFW3, reg);
3069 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3070
3071 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003072 I915_WRITE(DSPFW3,
3073 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003074 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3075 } else {
3076 pineview_disable_cxsr(dev);
3077 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3078 }
3079}
3080
Jesse Barnes0e442c62009-10-19 10:09:33 +09003081static void g4x_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003082 int planeb_clock, int sr_hdisplay, int sr_htotal,
3083 int pixel_size)
Jesse Barnes652c3932009-08-17 13:31:43 -07003084{
3085 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003086 int total_size, cacheline_size;
3087 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3088 struct intel_watermark_params planea_params, planeb_params;
3089 unsigned long line_time_us;
3090 int sr_clock, sr_entries = 0, entries_required;
Jesse Barnes652c3932009-08-17 13:31:43 -07003091
Jesse Barnes0e442c62009-10-19 10:09:33 +09003092 /* Create copies of the base settings for each pipe */
3093 planea_params = planeb_params = g4x_wm_info;
3094
3095 /* Grab a couple of global values before we overwrite them */
3096 total_size = planea_params.fifo_size;
3097 cacheline_size = planea_params.cacheline_size;
3098
3099 /*
3100 * Note: we need to make sure we don't overflow for various clock &
3101 * latency values.
3102 * clocks go from a few thousand to several hundred thousand.
3103 * latency is usually a few thousand
3104 */
3105 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3106 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003107 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003108 planea_wm = entries_required + planea_params.guard_size;
3109
3110 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3111 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003112 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003113 planeb_wm = entries_required + planeb_params.guard_size;
3114
3115 cursora_wm = cursorb_wm = 16;
3116 cursor_sr = 32;
3117
3118 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3119
3120 /* Calc sr entries for one plane configs */
3121 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3122 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003123 static const int sr_latency_ns = 12000;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003124
3125 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003126 line_time_us = ((sr_htotal * 1000) / sr_clock);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003127
3128 /* Use ns/us then divide to preserve precision */
Zhao Yakuifa143212010-06-12 14:32:23 +08003129 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3130 pixel_size * sr_hdisplay;
Chris Wilson8de9b312010-07-19 19:59:52 +01003131 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003132
3133 entries_required = (((sr_latency_ns / line_time_us) +
3134 1000) / 1000) * pixel_size * 64;
Chris Wilson8de9b312010-07-19 19:59:52 +01003135 entries_required = DIV_ROUND_UP(entries_required,
3136 g4x_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003137 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3138
3139 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3140 cursor_sr = g4x_cursor_wm_info.max_wm;
3141 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3142 "cursor %d\n", sr_entries, cursor_sr);
3143
Jesse Barnes0e442c62009-10-19 10:09:33 +09003144 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05303145 } else {
3146 /* Turn off self refresh if both pipes are enabled */
3147 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3148 & ~FW_BLC_SELF_EN);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003149 }
3150
3151 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3152 planea_wm, planeb_wm, sr_entries);
3153
3154 planea_wm &= 0x3f;
3155 planeb_wm &= 0x3f;
3156
3157 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3158 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3159 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3160 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3161 (cursora_wm << DSPFW_CURSORA_SHIFT));
3162 /* HPLL off in SR has some issues on G4x... disable it */
3163 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3164 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07003165}
3166
Jesse Barnes1dc75462009-10-19 10:08:17 +09003167static void i965_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003168 int planeb_clock, int sr_hdisplay, int sr_htotal,
3169 int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003172 unsigned long line_time_us;
3173 int sr_clock, sr_entries, srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003174 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003175
Jesse Barnes1dc75462009-10-19 10:08:17 +09003176 /* Calc sr entries for one plane configs */
3177 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3178 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003179 static const int sr_latency_ns = 12000;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003180
3181 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003182 line_time_us = ((sr_htotal * 1000) / sr_clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003183
3184 /* Use ns/us then divide to preserve precision */
Zhao Yakuifa143212010-06-12 14:32:23 +08003185 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3186 pixel_size * sr_hdisplay;
Chris Wilson8de9b312010-07-19 19:59:52 +01003187 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003188 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
Zhao Yakui1b07e042010-06-12 14:32:24 +08003189 srwm = I965_FIFO_SIZE - sr_entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003190 if (srwm < 0)
3191 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08003192 srwm &= 0x1ff;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003193
3194 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3195 pixel_size * 64;
Chris Wilson8de9b312010-07-19 19:59:52 +01003196 sr_entries = DIV_ROUND_UP(sr_entries,
3197 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003198 cursor_sr = i965_cursor_wm_info.fifo_size -
3199 (sr_entries + i965_cursor_wm_info.guard_size);
3200
3201 if (cursor_sr > i965_cursor_wm_info.max_wm)
3202 cursor_sr = i965_cursor_wm_info.max_wm;
3203
3204 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3205 "cursor %d\n", srwm, cursor_sr);
3206
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003207 if (IS_I965GM(dev))
3208 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05303209 } else {
3210 /* Turn off self refresh if both pipes are enabled */
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003211 if (IS_I965GM(dev))
3212 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3213 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003214 }
3215
3216 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3217 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003218
3219 /* 965 has limitations... */
Jesse Barnes1dc75462009-10-19 10:08:17 +09003220 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3221 (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003222 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003223 /* update cursor SR watermark */
3224 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003225}
3226
3227static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003228 int planeb_clock, int sr_hdisplay, int sr_htotal,
3229 int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003232 uint32_t fwater_lo;
3233 uint32_t fwater_hi;
3234 int total_size, cacheline_size, cwm, srwm = 1;
3235 int planea_wm, planeb_wm;
3236 struct intel_watermark_params planea_params, planeb_params;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003237 unsigned long line_time_us;
3238 int sr_clock, sr_entries = 0;
3239
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003240 /* Create copies of the base settings for each pipe */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003241 if (IS_I965GM(dev) || IS_I945GM(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003242 planea_params = planeb_params = i945_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003243 else if (IS_I9XX(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003244 planea_params = planeb_params = i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003245 else
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003246 planea_params = planeb_params = i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003247
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003248 /* Grab a couple of global values before we overwrite them */
3249 total_size = planea_params.fifo_size;
3250 cacheline_size = planea_params.cacheline_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003251
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003252 /* Update per-plane FIFO sizes */
Jesse Barnese70236a2009-09-21 10:42:27 -07003253 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3254 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003255
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003256 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3257 pixel_size, latency_ns);
3258 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3259 pixel_size, latency_ns);
Zhao Yakui28c97732009-10-09 11:39:41 +08003260 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003261
3262 /*
3263 * Overlay gets an aggressive default since video jitter is bad.
3264 */
3265 cwm = 2;
3266
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003267 /* Calc sr entries for one plane configs */
Jesse Barnes652c3932009-08-17 13:31:43 -07003268 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3269 (!planea_clock || !planeb_clock)) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003270 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003271 static const int sr_latency_ns = 6000;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003272
Shaohua Li7662c8b2009-06-26 11:23:55 +08003273 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003274 line_time_us = ((sr_htotal * 1000) / sr_clock);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003275
3276 /* Use ns/us then divide to preserve precision */
Zhao Yakuifa143212010-06-12 14:32:23 +08003277 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3278 pixel_size * sr_hdisplay;
Chris Wilson8de9b312010-07-19 19:59:52 +01003279 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
Zhao Yakui28c97732009-10-09 11:39:41 +08003280 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003281 srwm = total_size - sr_entries;
3282 if (srwm < 0)
3283 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08003284
3285 if (IS_I945G(dev) || IS_I945GM(dev))
3286 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3287 else if (IS_I915GM(dev)) {
3288 /* 915M has a smaller SRWM field */
3289 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3290 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3291 }
David John33c5fd12010-01-27 15:19:08 +05303292 } else {
3293 /* Turn off self refresh if both pipes are enabled */
Li Pengee980b82010-01-27 19:01:11 +08003294 if (IS_I945G(dev) || IS_I945GM(dev)) {
3295 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3296 & ~FW_BLC_SELF_EN);
3297 } else if (IS_I915GM(dev)) {
3298 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3299 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08003300 }
3301
Zhao Yakui28c97732009-10-09 11:39:41 +08003302 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003303 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003304
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003305 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3306 fwater_hi = (cwm & 0x1f);
3307
3308 /* Set request length to 8 cachelines per fetch */
3309 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3310 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003311
3312 I915_WRITE(FW_BLC, fwater_lo);
3313 I915_WRITE(FW_BLC2, fwater_hi);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003314}
3315
Jesse Barnese70236a2009-09-21 10:42:27 -07003316static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
Zhao Yakuifa143212010-06-12 14:32:23 +08003317 int unused2, int unused3, int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003318{
3319 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf3601322009-07-22 12:54:59 -07003320 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003321 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003322
Jesse Barnese70236a2009-09-21 10:42:27 -07003323 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003324
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003325 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3326 pixel_size, latency_ns);
Jesse Barnesf3601322009-07-22 12:54:59 -07003327 fwater_lo |= (3<<8) | planea_wm;
3328
Zhao Yakui28c97732009-10-09 11:39:41 +08003329 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003330
3331 I915_WRITE(FW_BLC, fwater_lo);
3332}
3333
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003334#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08003335#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003336
3337static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003338 int planeb_clock, int sr_hdisplay, int sr_htotal,
3339 int pixel_size)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003340{
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3343 int sr_wm, cursor_wm;
3344 unsigned long line_time_us;
3345 int sr_clock, entries_required;
3346 u32 reg_value;
Zhao Yakuic936f442010-06-12 14:32:26 +08003347 int line_count;
3348 int planea_htotal = 0, planeb_htotal = 0;
3349 struct drm_crtc *crtc;
Zhao Yakuic936f442010-06-12 14:32:26 +08003350
3351 /* Need htotal for all active display plane */
3352 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsondebcadd2010-08-07 11:01:33 +01003353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
Zhao Yakuic936f442010-06-12 14:32:26 +08003355 if (intel_crtc->plane == 0)
3356 planea_htotal = crtc->mode.htotal;
3357 else
3358 planeb_htotal = crtc->mode.htotal;
3359 }
3360 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003361
3362 /* Calculate and update the watermark for plane A */
3363 if (planea_clock) {
3364 entries_required = ((planea_clock / 1000) * pixel_size *
3365 ILK_LP0_PLANE_LATENCY) / 1000;
3366 entries_required = DIV_ROUND_UP(entries_required,
Chris Wilson8de9b312010-07-19 19:59:52 +01003367 ironlake_display_wm_info.cacheline_size);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003368 planea_wm = entries_required +
3369 ironlake_display_wm_info.guard_size;
3370
3371 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3372 planea_wm = ironlake_display_wm_info.max_wm;
3373
Zhao Yakuic936f442010-06-12 14:32:26 +08003374 /* Use the large buffer method to calculate cursor watermark */
3375 line_time_us = (planea_htotal * 1000) / planea_clock;
3376
3377 /* Use ns/us then divide to preserve precision */
3378 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3379
3380 /* calculate the cursor watermark for cursor A */
3381 entries_required = line_count * 64 * pixel_size;
3382 entries_required = DIV_ROUND_UP(entries_required,
3383 ironlake_cursor_wm_info.cacheline_size);
3384 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3385 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3386 cursora_wm = ironlake_cursor_wm_info.max_wm;
3387
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003388 reg_value = I915_READ(WM0_PIPEA_ILK);
3389 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3390 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3391 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3392 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3393 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3394 "cursor: %d\n", planea_wm, cursora_wm);
3395 }
3396 /* Calculate and update the watermark for plane B */
3397 if (planeb_clock) {
3398 entries_required = ((planeb_clock / 1000) * pixel_size *
3399 ILK_LP0_PLANE_LATENCY) / 1000;
3400 entries_required = DIV_ROUND_UP(entries_required,
Chris Wilson8de9b312010-07-19 19:59:52 +01003401 ironlake_display_wm_info.cacheline_size);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003402 planeb_wm = entries_required +
3403 ironlake_display_wm_info.guard_size;
3404
3405 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3406 planeb_wm = ironlake_display_wm_info.max_wm;
3407
Zhao Yakuic936f442010-06-12 14:32:26 +08003408 /* Use the large buffer method to calculate cursor watermark */
3409 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3410
3411 /* Use ns/us then divide to preserve precision */
3412 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3413
3414 /* calculate the cursor watermark for cursor B */
3415 entries_required = line_count * 64 * pixel_size;
3416 entries_required = DIV_ROUND_UP(entries_required,
3417 ironlake_cursor_wm_info.cacheline_size);
3418 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3419 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3420 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3421
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003422 reg_value = I915_READ(WM0_PIPEB_ILK);
3423 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3424 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3425 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3426 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3427 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3428 "cursor: %d\n", planeb_wm, cursorb_wm);
3429 }
3430
3431 /*
3432 * Calculate and update the self-refresh watermark only when one
3433 * display plane is used.
3434 */
3435 if (!planea_clock || !planeb_clock) {
Zhao Yakuic936f442010-06-12 14:32:26 +08003436
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003437 /* Read the self-refresh latency. The unit is 0.5us */
3438 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3439
3440 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003441 line_time_us = ((sr_htotal * 1000) / sr_clock);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003442
3443 /* Use ns/us then divide to preserve precision */
3444 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3445 / 1000;
3446
3447 /* calculate the self-refresh watermark for display plane */
3448 entries_required = line_count * sr_hdisplay * pixel_size;
3449 entries_required = DIV_ROUND_UP(entries_required,
Chris Wilson8de9b312010-07-19 19:59:52 +01003450 ironlake_display_srwm_info.cacheline_size);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003451 sr_wm = entries_required +
3452 ironlake_display_srwm_info.guard_size;
3453
3454 /* calculate the self-refresh watermark for display cursor */
3455 entries_required = line_count * pixel_size * 64;
3456 entries_required = DIV_ROUND_UP(entries_required,
Chris Wilson8de9b312010-07-19 19:59:52 +01003457 ironlake_cursor_srwm_info.cacheline_size);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003458 cursor_wm = entries_required +
3459 ironlake_cursor_srwm_info.guard_size;
3460
3461 /* configure watermark and enable self-refresh */
3462 reg_value = I915_READ(WM1_LP_ILK);
3463 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3464 WM1_LP_CURSOR_MASK);
3465 reg_value |= WM1_LP_SR_EN |
3466 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3467 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3468
3469 I915_WRITE(WM1_LP_ILK, reg_value);
3470 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3471 "cursor %d\n", sr_wm, cursor_wm);
3472
3473 } else {
3474 /* Turn off self refresh if both pipes are enabled */
3475 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3476 }
3477}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003478/**
3479 * intel_update_watermarks - update FIFO watermark values based on current modes
3480 *
3481 * Calculate watermark values for the various WM regs based on current mode
3482 * and plane configuration.
3483 *
3484 * There are several cases to deal with here:
3485 * - normal (i.e. non-self-refresh)
3486 * - self-refresh (SR) mode
3487 * - lines are large relative to FIFO size (buffer can hold up to 2)
3488 * - lines are small relative to FIFO size (buffer can hold more than 2
3489 * lines), so need to account for TLB latency
3490 *
3491 * The normal calculation is:
3492 * watermark = dotclock * bytes per pixel * latency
3493 * where latency is platform & configuration dependent (we assume pessimal
3494 * values here).
3495 *
3496 * The SR calculation is:
3497 * watermark = (trunc(latency/line time)+1) * surface width *
3498 * bytes per pixel
3499 * where
3500 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08003501 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08003502 * and latency is assumed to be high, as above.
3503 *
3504 * The final value programmed to the register should always be rounded up,
3505 * and include an extra 2 entries to account for clock crossings.
3506 *
3507 * We don't use the sprite, so we can ignore that. And on Crestline we have
3508 * to set the non-SR watermarks to 8.
3509 */
3510static void intel_update_watermarks(struct drm_device *dev)
3511{
Jesse Barnese70236a2009-09-21 10:42:27 -07003512 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003513 struct drm_crtc *crtc;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003514 int sr_hdisplay = 0;
3515 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3516 int enabled = 0, pixel_size = 0;
Zhao Yakuifa143212010-06-12 14:32:23 +08003517 int sr_htotal = 0;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003518
Zhenyu Wangc03342f2009-09-29 11:01:23 +08003519 if (!dev_priv->display.update_wm)
3520 return;
3521
Shaohua Li7662c8b2009-06-26 11:23:55 +08003522 /* Get the clock config from both planes */
3523 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsondebcadd2010-08-07 11:01:33 +01003524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003526 enabled++;
3527 if (intel_crtc->plane == 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08003528 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
Shaohua Li7662c8b2009-06-26 11:23:55 +08003529 intel_crtc->pipe, crtc->mode.clock);
3530 planea_clock = crtc->mode.clock;
3531 } else {
Zhao Yakui28c97732009-10-09 11:39:41 +08003532 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
Shaohua Li7662c8b2009-06-26 11:23:55 +08003533 intel_crtc->pipe, crtc->mode.clock);
3534 planeb_clock = crtc->mode.clock;
3535 }
3536 sr_hdisplay = crtc->mode.hdisplay;
3537 sr_clock = crtc->mode.clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003538 sr_htotal = crtc->mode.htotal;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003539 if (crtc->fb)
3540 pixel_size = crtc->fb->bits_per_pixel / 8;
3541 else
3542 pixel_size = 4; /* by default */
3543 }
3544 }
3545
3546 if (enabled <= 0)
3547 return;
3548
Jesse Barnese70236a2009-09-21 10:42:27 -07003549 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003550 sr_hdisplay, sr_htotal, pixel_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003551}
3552
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003553static int intel_crtc_mode_set(struct drm_crtc *crtc,
3554 struct drm_display_mode *mode,
3555 struct drm_display_mode *adjusted_mode,
3556 int x, int y,
3557 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08003558{
3559 struct drm_device *dev = crtc->dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003563 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003564 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3565 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3566 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
Jesse Barnes80824002009-09-10 15:28:06 -07003567 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
Jesse Barnes79e53942008-11-07 14:24:08 -08003568 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3569 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3570 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3571 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3572 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3573 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3574 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
Jesse Barnes80824002009-09-10 15:28:06 -07003575 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3576 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
Jesse Barnes79e53942008-11-07 14:24:08 -08003577 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
Eric Anholtc751ce42010-03-25 11:48:48 -07003578 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07003579 intel_clock_t clock, reduced_clock;
3580 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3581 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003582 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003583 bool is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08003584 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003585 struct drm_encoder *encoder;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003586 struct intel_encoder *intel_encoder = NULL;
Ma Lingd4906092009-03-18 20:13:27 +08003587 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003588 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003589 struct fdi_m_n m_n = {0};
3590 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3591 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3592 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3593 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3594 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3595 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3596 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003597 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3598 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
Zhenyu Wang541998a2009-06-05 15:38:44 +08003599 int lvds_reg = LVDS;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003600 u32 temp;
3601 int sdvo_pixel_multiply;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003602 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08003603
3604 drm_vblank_pre_modeset(dev, pipe);
3605
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003606 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003607
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003608 if (!encoder || encoder->crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003609 continue;
3610
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08003611 intel_encoder = enc_to_intel_encoder(encoder);
3612
Eric Anholt21d40d32010-03-25 11:11:14 -07003613 switch (intel_encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003614 case INTEL_OUTPUT_LVDS:
3615 is_lvds = true;
3616 break;
3617 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08003618 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08003619 is_sdvo = true;
Eric Anholt21d40d32010-03-25 11:11:14 -07003620 if (intel_encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08003621 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08003622 break;
3623 case INTEL_OUTPUT_DVO:
3624 is_dvo = true;
3625 break;
3626 case INTEL_OUTPUT_TVOUT:
3627 is_tv = true;
3628 break;
3629 case INTEL_OUTPUT_ANALOG:
3630 is_crt = true;
3631 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003632 case INTEL_OUTPUT_DISPLAYPORT:
3633 is_dp = true;
3634 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003635 case INTEL_OUTPUT_EDP:
3636 is_edp = true;
3637 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003638 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003639
Eric Anholtc751ce42010-03-25 11:48:48 -07003640 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08003641 }
3642
Eric Anholtc751ce42010-03-25 11:48:48 -07003643 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003644 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08003645 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3646 refclk / 1000);
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003647 } else if (IS_I9XX(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003648 refclk = 96000;
Eric Anholtbad720f2009-10-22 16:11:14 -07003649 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003650 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08003651 } else {
3652 refclk = 48000;
3653 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003654
Jesse Barnes79e53942008-11-07 14:24:08 -08003655
Ma Lingd4906092009-03-18 20:13:27 +08003656 /*
3657 * Returns a set of divisors for the desired target clock with the given
3658 * refclk, or FALSE. The returned values represent the clock equation:
3659 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3660 */
3661 limit = intel_limit(crtc);
3662 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08003663 if (!ok) {
3664 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01003665 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00003666 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08003667 }
3668
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01003669 /* Ensure that the cursor is valid for the new mode before changing... */
3670 intel_crtc_update_cursor(crtc);
3671
Zhao Yakuiddc90032010-01-06 22:05:56 +08003672 if (is_lvds && dev_priv->lvds_downclock_avail) {
3673 has_reduced_clock = limit->find_pll(limit, crtc,
Zhao Yakui18f9ed12009-11-20 03:24:16 +00003674 dev_priv->lvds_downclock,
Jesse Barnes652c3932009-08-17 13:31:43 -07003675 refclk,
3676 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00003677 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3678 /*
3679 * If the different P is found, it means that we can't
3680 * switch the display clock by using the FP0/FP1.
3681 * In such case we will disable the LVDS downclock
3682 * feature.
3683 */
3684 DRM_DEBUG_KMS("Different P is found for "
3685 "LVDS clock/downclock\n");
3686 has_reduced_clock = 0;
3687 }
Jesse Barnes652c3932009-08-17 13:31:43 -07003688 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08003689 /* SDVO TV has fixed PLL values depend on its clock range,
3690 this mirrors vbios setting. */
3691 if (is_sdvo && is_tv) {
3692 if (adjusted_mode->clock >= 100000
3693 && adjusted_mode->clock < 140500) {
3694 clock.p1 = 2;
3695 clock.p2 = 10;
3696 clock.n = 3;
3697 clock.m1 = 16;
3698 clock.m2 = 8;
3699 } else if (adjusted_mode->clock >= 140500
3700 && adjusted_mode->clock <= 200000) {
3701 clock.p1 = 1;
3702 clock.p2 = 10;
3703 clock.n = 6;
3704 clock.m1 = 12;
3705 clock.m2 = 8;
3706 }
3707 }
3708
Zhenyu Wang2c072452009-06-05 15:38:42 +08003709 /* FDI link */
Eric Anholtbad720f2009-10-22 16:11:14 -07003710 if (HAS_PCH_SPLIT(dev)) {
Adam Jackson77ffb592010-04-12 11:38:44 -04003711 int lane = 0, link_bw, bpp;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003712 /* eDP doesn't require FDI link, so just set DP M/N
3713 according to current link config */
3714 if (is_edp) {
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003715 target_clock = mode->clock;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003716 intel_edp_link_config(intel_encoder,
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003717 &lane, &link_bw);
3718 } else {
3719 /* DP over FDI requires target mode clock
3720 instead of link clock */
3721 if (is_dp)
3722 target_clock = mode->clock;
3723 else
3724 target_clock = adjusted_mode->clock;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003725 link_bw = 270000;
3726 }
Zhenyu Wang58a27472009-09-25 08:01:28 +00003727
3728 /* determine panel color depth */
3729 temp = I915_READ(pipeconf_reg);
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08003730 temp &= ~PIPE_BPC_MASK;
3731 if (is_lvds) {
3732 int lvds_reg = I915_READ(PCH_LVDS);
3733 /* the BPC will be 6 if it is 18-bit LVDS panel */
3734 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3735 temp |= PIPE_8BPC;
3736 else
3737 temp |= PIPE_6BPC;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003738 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
Zhenyu Wang885a5fb2010-01-12 05:38:31 +08003739 switch (dev_priv->edp_bpp/3) {
3740 case 8:
3741 temp |= PIPE_8BPC;
3742 break;
3743 case 10:
3744 temp |= PIPE_10BPC;
3745 break;
3746 case 6:
3747 temp |= PIPE_6BPC;
3748 break;
3749 case 12:
3750 temp |= PIPE_12BPC;
3751 break;
3752 }
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08003753 } else
3754 temp |= PIPE_8BPC;
3755 I915_WRITE(pipeconf_reg, temp);
3756 I915_READ(pipeconf_reg);
Zhenyu Wang58a27472009-09-25 08:01:28 +00003757
3758 switch (temp & PIPE_BPC_MASK) {
3759 case PIPE_8BPC:
3760 bpp = 24;
3761 break;
3762 case PIPE_10BPC:
3763 bpp = 30;
3764 break;
3765 case PIPE_6BPC:
3766 bpp = 18;
3767 break;
3768 case PIPE_12BPC:
3769 bpp = 36;
3770 break;
3771 default:
3772 DRM_ERROR("unknown pipe bpc value\n");
3773 bpp = 24;
3774 }
3775
Adam Jackson77ffb592010-04-12 11:38:44 -04003776 if (!lane) {
3777 /*
3778 * Account for spread spectrum to avoid
3779 * oversubscribing the link. Max center spread
3780 * is 2.5%; use 5% for safety's sake.
3781 */
3782 u32 bps = target_clock * bpp * 21 / 20;
3783 lane = bps / (link_bw * 8) + 1;
3784 }
3785
3786 intel_crtc->fdi_lanes = lane;
3787
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003788 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003789 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003790
Zhenyu Wangc038e512009-10-19 15:43:48 +08003791 /* Ironlake: try to setup display ref clock before DPLL
3792 * enabling. This is only under driver's control after
3793 * PCH B stepping, previous chipset stepping should be
3794 * ignoring this setting.
3795 */
Eric Anholtbad720f2009-10-22 16:11:14 -07003796 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wangc038e512009-10-19 15:43:48 +08003797 temp = I915_READ(PCH_DREF_CONTROL);
3798 /* Always enable nonspread source */
3799 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3800 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3801 I915_WRITE(PCH_DREF_CONTROL, temp);
3802 POSTING_READ(PCH_DREF_CONTROL);
3803
3804 temp &= ~DREF_SSC_SOURCE_MASK;
3805 temp |= DREF_SSC_SOURCE_ENABLE;
3806 I915_WRITE(PCH_DREF_CONTROL, temp);
3807 POSTING_READ(PCH_DREF_CONTROL);
3808
3809 udelay(200);
3810
3811 if (is_edp) {
3812 if (dev_priv->lvds_use_ssc) {
3813 temp |= DREF_SSC1_ENABLE;
3814 I915_WRITE(PCH_DREF_CONTROL, temp);
3815 POSTING_READ(PCH_DREF_CONTROL);
3816
3817 udelay(200);
3818
3819 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3820 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3821 I915_WRITE(PCH_DREF_CONTROL, temp);
3822 POSTING_READ(PCH_DREF_CONTROL);
3823 } else {
3824 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3825 I915_WRITE(PCH_DREF_CONTROL, temp);
3826 POSTING_READ(PCH_DREF_CONTROL);
3827 }
3828 }
3829 }
3830
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003831 if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08003832 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07003833 if (has_reduced_clock)
3834 fp2 = (1 << reduced_clock.n) << 16 |
3835 reduced_clock.m1 << 8 | reduced_clock.m2;
3836 } else {
Shaohua Li21778322009-02-23 15:19:16 +08003837 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07003838 if (has_reduced_clock)
3839 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3840 reduced_clock.m2;
3841 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003842
Eric Anholtbad720f2009-10-22 16:11:14 -07003843 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003844 dpll = DPLL_VGA_MODE_DIS;
3845
Jesse Barnes79e53942008-11-07 14:24:08 -08003846 if (IS_I9XX(dev)) {
3847 if (is_lvds)
3848 dpll |= DPLLB_MODE_LVDS;
3849 else
3850 dpll |= DPLLB_MODE_DAC_SERIAL;
3851 if (is_sdvo) {
3852 dpll |= DPLL_DVO_HIGH_SPEED;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003853 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
Sean Young942642a2009-08-06 17:35:50 +08003854 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003855 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Eric Anholtbad720f2009-10-22 16:11:14 -07003856 else if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003857 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08003858 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003859 if (is_dp)
3860 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08003861
3862 /* compute bitmask from p1 value */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003863 if (IS_PINEVIEW(dev))
3864 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003865 else {
Shaohua Li21778322009-02-23 15:19:16 +08003866 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003867 /* also FPA1 */
Eric Anholtbad720f2009-10-22 16:11:14 -07003868 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08003869 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07003870 if (IS_G4X(dev) && has_reduced_clock)
3871 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003872 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003873 switch (clock.p2) {
3874 case 5:
3875 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3876 break;
3877 case 7:
3878 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3879 break;
3880 case 10:
3881 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3882 break;
3883 case 14:
3884 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3885 break;
3886 }
Eric Anholtbad720f2009-10-22 16:11:14 -07003887 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08003888 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3889 } else {
3890 if (is_lvds) {
3891 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3892 } else {
3893 if (clock.p1 == 2)
3894 dpll |= PLL_P1_DIVIDE_BY_TWO;
3895 else
3896 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3897 if (clock.p2 == 4)
3898 dpll |= PLL_P2_DIVIDE_BY_4;
3899 }
3900 }
3901
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003902 if (is_sdvo && is_tv)
3903 dpll |= PLL_REF_INPUT_TVCLKINBC;
3904 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08003905 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003906 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08003907 dpll |= 3;
Eric Anholtc751ce42010-03-25 11:48:48 -07003908 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05003909 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08003910 else
3911 dpll |= PLL_REF_INPUT_DREFCLK;
3912
3913 /* setup pipeconf */
3914 pipeconf = I915_READ(pipeconf_reg);
3915
3916 /* Set up the display plane register */
3917 dspcntr = DISPPLANE_GAMMA_ENABLE;
3918
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003919 /* Ironlake's plane is forced to pipe, bit 24 is to
Zhenyu Wang2c072452009-06-05 15:38:42 +08003920 enable color space conversion */
Eric Anholtbad720f2009-10-22 16:11:14 -07003921 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003922 if (pipe == 0)
Jesse Barnes80824002009-09-10 15:28:06 -07003923 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003924 else
3925 dspcntr |= DISPPLANE_SEL_PIPE_B;
3926 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003927
3928 if (pipe == 0 && !IS_I965G(dev)) {
3929 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3930 * core speed.
3931 *
3932 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3933 * pipe == 0 check?
3934 */
Jesse Barnese70236a2009-09-21 10:42:27 -07003935 if (mode->clock >
3936 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
Jesse Barnes79e53942008-11-07 14:24:08 -08003937 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3938 else
3939 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3940 }
3941
Linus Torvalds8d86dc62010-06-08 20:16:28 -07003942 dspcntr |= DISPLAY_PLANE_ENABLE;
3943 pipeconf |= PIPEACONF_ENABLE;
3944 dpll |= DPLL_VCO_ENABLE;
3945
3946
Jesse Barnes79e53942008-11-07 14:24:08 -08003947 /* Disable the panel fitter if it was on our pipe */
Eric Anholtbad720f2009-10-22 16:11:14 -07003948 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08003949 I915_WRITE(PFIT_CONTROL, 0);
3950
Zhao Yakui28c97732009-10-09 11:39:41 +08003951 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08003952 drm_mode_debug_printmodeline(mode);
3953
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003954 /* assign to Ironlake registers */
Eric Anholtbad720f2009-10-22 16:11:14 -07003955 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003956 fp_reg = pch_fp_reg;
3957 dpll_reg = pch_dpll_reg;
3958 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003959
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003960 if (is_edp) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003961 ironlake_disable_pll_edp(crtc);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003962 } else if ((dpll & DPLL_VCO_ENABLE)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08003963 I915_WRITE(fp_reg, fp);
3964 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3965 I915_READ(dpll_reg);
3966 udelay(150);
3967 }
3968
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003969 /* enable transcoder DPLL */
3970 if (HAS_PCH_CPT(dev)) {
3971 temp = I915_READ(PCH_DPLL_SEL);
3972 if (trans_dpll_sel == 0)
3973 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3974 else
3975 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3976 I915_WRITE(PCH_DPLL_SEL, temp);
3977 I915_READ(PCH_DPLL_SEL);
3978 udelay(150);
3979 }
3980
Eric Anholt7b824ec2010-07-26 14:49:07 -07003981 if (HAS_PCH_SPLIT(dev)) {
3982 pipeconf &= ~PIPE_ENABLE_DITHER;
3983 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3984 }
3985
Jesse Barnes79e53942008-11-07 14:24:08 -08003986 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3987 * This is an exception to the general rule that mode_set doesn't turn
3988 * things on.
3989 */
3990 if (is_lvds) {
Zhenyu Wang541998a2009-06-05 15:38:44 +08003991 u32 lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08003992
Eric Anholtbad720f2009-10-22 16:11:14 -07003993 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang541998a2009-06-05 15:38:44 +08003994 lvds_reg = PCH_LVDS;
3995
3996 lvds = I915_READ(lvds_reg);
Adam Jackson0f3ee802010-03-31 11:41:51 -04003997 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08003998 if (pipe == 1) {
3999 if (HAS_PCH_CPT(dev))
4000 lvds |= PORT_TRANS_B_SEL_CPT;
4001 else
4002 lvds |= LVDS_PIPEB_SELECT;
4003 } else {
4004 if (HAS_PCH_CPT(dev))
4005 lvds &= ~PORT_TRANS_SEL_MASK;
4006 else
4007 lvds &= ~LVDS_PIPEB_SELECT;
4008 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004009 /* set the corresponsding LVDS_BORDER bit */
4010 lvds |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08004011 /* Set the B0-B3 data pairs corresponding to whether we're going to
4012 * set the DPLLs for dual-channel mode or not.
4013 */
4014 if (clock.p2 == 7)
4015 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4016 else
4017 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4018
4019 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4020 * appropriately here, but we need to look more thoroughly into how
4021 * panels behave in the two modes.
4022 */
Zhao Yakui898822c2010-01-04 16:29:30 +08004023 /* set the dithering flag */
4024 if (IS_I965G(dev)) {
4025 if (dev_priv->lvds_dither) {
Adam Jackson0a31a442010-04-19 15:57:25 -04004026 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakui898822c2010-01-04 16:29:30 +08004027 pipeconf |= PIPE_ENABLE_DITHER;
Adam Jackson0a31a442010-04-19 15:57:25 -04004028 pipeconf |= PIPE_DITHER_TYPE_ST01;
4029 } else
Zhao Yakui898822c2010-01-04 16:29:30 +08004030 lvds |= LVDS_ENABLE_DITHER;
4031 } else {
Eric Anholt7b824ec2010-07-26 14:49:07 -07004032 if (!HAS_PCH_SPLIT(dev)) {
Zhao Yakui898822c2010-01-04 16:29:30 +08004033 lvds &= ~LVDS_ENABLE_DITHER;
Eric Anholt7b824ec2010-07-26 14:49:07 -07004034 }
Zhao Yakui898822c2010-01-04 16:29:30 +08004035 }
4036 }
Zhenyu Wang541998a2009-06-05 15:38:44 +08004037 I915_WRITE(lvds_reg, lvds);
4038 I915_READ(lvds_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08004039 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004040 if (is_dp)
4041 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004042 else if (HAS_PCH_SPLIT(dev)) {
4043 /* For non-DP output, clear any trans DP clock recovery setting.*/
4044 if (pipe == 0) {
4045 I915_WRITE(TRANSA_DATA_M1, 0);
4046 I915_WRITE(TRANSA_DATA_N1, 0);
4047 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4048 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4049 } else {
4050 I915_WRITE(TRANSB_DATA_M1, 0);
4051 I915_WRITE(TRANSB_DATA_N1, 0);
4052 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4053 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4054 }
4055 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004056
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004057 if (!is_edp) {
4058 I915_WRITE(fp_reg, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08004059 I915_WRITE(dpll_reg, dpll);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004060 I915_READ(dpll_reg);
4061 /* Wait for the clocks to stabilize. */
4062 udelay(150);
4063
Eric Anholtbad720f2009-10-22 16:11:14 -07004064 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
Zhao Yakuibb66c512009-09-10 15:45:49 +08004065 if (is_sdvo) {
4066 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4067 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004068 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
Zhao Yakuibb66c512009-09-10 15:45:49 +08004069 } else
4070 I915_WRITE(dpll_md_reg, 0);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004071 } else {
4072 /* write it again -- the BIOS does, after all */
4073 I915_WRITE(dpll_reg, dpll);
4074 }
4075 I915_READ(dpll_reg);
4076 /* Wait for the clocks to stabilize. */
4077 udelay(150);
Jesse Barnes79e53942008-11-07 14:24:08 -08004078 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004079
Jesse Barnes652c3932009-08-17 13:31:43 -07004080 if (is_lvds && has_reduced_clock && i915_powersave) {
4081 I915_WRITE(fp_reg + 4, fp2);
4082 intel_crtc->lowfreq_avail = true;
4083 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004084 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004085 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4086 }
4087 } else {
4088 I915_WRITE(fp_reg + 4, fp);
4089 intel_crtc->lowfreq_avail = false;
4090 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004091 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004092 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4093 }
4094 }
4095
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004096 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4097 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4098 /* the chip adds 2 halflines automatically */
4099 adjusted_mode->crtc_vdisplay -= 1;
4100 adjusted_mode->crtc_vtotal -= 1;
4101 adjusted_mode->crtc_vblank_start -= 1;
4102 adjusted_mode->crtc_vblank_end -= 1;
4103 adjusted_mode->crtc_vsync_end -= 1;
4104 adjusted_mode->crtc_vsync_start -= 1;
4105 } else
4106 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4107
Jesse Barnes79e53942008-11-07 14:24:08 -08004108 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4109 ((adjusted_mode->crtc_htotal - 1) << 16));
4110 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4111 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4112 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4113 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4114 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4115 ((adjusted_mode->crtc_vtotal - 1) << 16));
4116 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4117 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4118 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4119 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4120 /* pipesrc and dspsize control the size that is scaled from, which should
4121 * always be the user's requested size.
4122 */
Eric Anholtbad720f2009-10-22 16:11:14 -07004123 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004124 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4125 (mode->hdisplay - 1));
4126 I915_WRITE(dsppos_reg, 0);
4127 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004128 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08004129
Eric Anholtbad720f2009-10-22 16:11:14 -07004130 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004131 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4132 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4133 I915_WRITE(link_m1_reg, m_n.link_m);
4134 I915_WRITE(link_n1_reg, m_n.link_n);
4135
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004136 if (is_edp) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004137 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004138 } else {
4139 /* enable FDI RX PLL too */
4140 temp = I915_READ(fdi_rx_reg);
4141 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004142 I915_READ(fdi_rx_reg);
4143 udelay(200);
4144
4145 /* enable FDI TX PLL too */
4146 temp = I915_READ(fdi_tx_reg);
4147 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4148 I915_READ(fdi_tx_reg);
4149
4150 /* enable FDI RX PCDCLK */
4151 temp = I915_READ(fdi_rx_reg);
4152 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4153 I915_READ(fdi_rx_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004154 udelay(200);
4155 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004156 }
4157
Jesse Barnes79e53942008-11-07 14:24:08 -08004158 I915_WRITE(pipeconf_reg, pipeconf);
4159 I915_READ(pipeconf_reg);
4160
4161 intel_wait_for_vblank(dev);
4162
Eric Anholtc2416fc2009-11-05 15:30:35 -08004163 if (IS_IRONLAKE(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08004164 /* enable address swizzle for tiling buffer */
4165 temp = I915_READ(DISP_ARB_CTL);
4166 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4167 }
4168
Jesse Barnes79e53942008-11-07 14:24:08 -08004169 I915_WRITE(dspcntr_reg, dspcntr);
4170
4171 /* Flush the plane changes */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004172 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004173
Jesse Barnes74dff282009-09-14 15:39:40 -07004174 if ((IS_I965G(dev) || plane == 0))
4175 intel_update_fbc(crtc, &crtc->mode);
Jesse Barnese70236a2009-09-21 10:42:27 -07004176
Shaohua Li7662c8b2009-06-26 11:23:55 +08004177 intel_update_watermarks(dev);
4178
Jesse Barnes79e53942008-11-07 14:24:08 -08004179 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004180
Chris Wilson1f803ee2009-06-06 09:45:59 +01004181 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004182}
4183
4184/** Loads the palette/gamma unit for the CRTC with the prepared values */
4185void intel_crtc_load_lut(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4190 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4191 int i;
4192
4193 /* The clocks have to be on to load the palette. */
4194 if (!crtc->enabled)
4195 return;
4196
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004197 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07004198 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004199 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4200 LGC_PALETTE_B;
4201
Jesse Barnes79e53942008-11-07 14:24:08 -08004202 for (i = 0; i < 256; i++) {
4203 I915_WRITE(palreg + 4 * i,
4204 (intel_crtc->lut_r[i] << 16) |
4205 (intel_crtc->lut_g[i] << 8) |
4206 intel_crtc->lut_b[i]);
4207 }
4208}
4209
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004210/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4211static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4212{
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216 int pipe = intel_crtc->pipe;
4217 int x = intel_crtc->cursor_x;
4218 int y = intel_crtc->cursor_y;
4219 uint32_t base, pos;
4220 bool visible;
4221
4222 pos = 0;
4223
Chris Wilson87f8ebf2010-08-04 12:24:42 +01004224 if (intel_crtc->cursor_on && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004225 base = intel_crtc->cursor_addr;
4226 if (x > (int) crtc->fb->width)
4227 base = 0;
4228
4229 if (y > (int) crtc->fb->height)
4230 base = 0;
4231 } else
4232 base = 0;
4233
4234 if (x < 0) {
4235 if (x + intel_crtc->cursor_width < 0)
4236 base = 0;
4237
4238 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4239 x = -x;
4240 }
4241 pos |= x << CURSOR_X_SHIFT;
4242
4243 if (y < 0) {
4244 if (y + intel_crtc->cursor_height < 0)
4245 base = 0;
4246
4247 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4248 y = -y;
4249 }
4250 pos |= y << CURSOR_Y_SHIFT;
4251
4252 visible = base != 0;
4253 if (!visible && !intel_crtc->cursor_visble)
4254 return;
4255
4256 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4257 if (intel_crtc->cursor_visble != visible) {
4258 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4259 if (base) {
4260 /* Hooray for CUR*CNTR differences */
4261 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4262 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4263 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4264 cntl |= pipe << 28; /* Connect to correct pipe */
4265 } else {
4266 cntl &= ~(CURSOR_FORMAT_MASK);
4267 cntl |= CURSOR_ENABLE;
4268 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4269 }
4270 } else {
4271 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4272 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4273 cntl |= CURSOR_MODE_DISABLE;
4274 } else {
4275 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4276 }
4277 }
4278 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4279
4280 intel_crtc->cursor_visble = visible;
4281 }
4282 /* and commit changes on next vblank */
4283 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4284
4285 if (visible)
4286 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4287}
4288
Jesse Barnes79e53942008-11-07 14:24:08 -08004289static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4290 struct drm_file *file_priv,
4291 uint32_t handle,
4292 uint32_t width, uint32_t height)
4293{
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297 struct drm_gem_object *bo;
4298 struct drm_i915_gem_object *obj_priv;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004299 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004300 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004301
Zhao Yakui28c97732009-10-09 11:39:41 +08004302 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08004303
4304 /* if we want to turn off the cursor ignore width and height */
4305 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004306 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004307 addr = 0;
4308 bo = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10004309 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004310 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08004311 }
4312
4313 /* Currently we only support 64x64 cursors */
4314 if (width != 64 || height != 64) {
4315 DRM_ERROR("we currently only support 64x64 cursors\n");
4316 return -EINVAL;
4317 }
4318
4319 bo = drm_gem_object_lookup(dev, file_priv, handle);
4320 if (!bo)
4321 return -ENOENT;
4322
Daniel Vetter23010e42010-03-08 13:35:02 +01004323 obj_priv = to_intel_bo(bo);
Jesse Barnes79e53942008-11-07 14:24:08 -08004324
4325 if (bo->size < width * height * 4) {
4326 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10004327 ret = -ENOMEM;
4328 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08004329 }
4330
Dave Airlie71acb5e2008-12-30 20:31:46 +10004331 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004332 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05004333 if (!dev_priv->info->cursor_needs_physical) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10004334 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4335 if (ret) {
4336 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004337 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10004338 }
Chris Wilsone7b526b2010-06-02 08:30:48 +01004339
4340 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4341 if (ret) {
4342 DRM_ERROR("failed to move cursor bo into the GTT\n");
4343 goto fail_unpin;
4344 }
4345
Jesse Barnes79e53942008-11-07 14:24:08 -08004346 addr = obj_priv->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10004347 } else {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004348 ret = i915_gem_attach_phys_object(dev, bo,
4349 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004350 if (ret) {
4351 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004352 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10004353 }
4354 addr = obj_priv->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004355 }
4356
Jesse Barnes14b60392009-05-20 16:47:08 -04004357 if (!IS_I9XX(dev))
4358 I915_WRITE(CURSIZE, (height << 12) | width);
4359
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004360 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004361 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05004362 if (dev_priv->info->cursor_needs_physical) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10004363 if (intel_crtc->cursor_bo != bo)
4364 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4365 } else
4366 i915_gem_object_unpin(intel_crtc->cursor_bo);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004367 drm_gem_object_unreference(intel_crtc->cursor_bo);
4368 }
Jesse Barnes80824002009-09-10 15:28:06 -07004369
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004370 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004371
4372 intel_crtc->cursor_addr = addr;
4373 intel_crtc->cursor_bo = bo;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004374 intel_crtc->cursor_width = width;
4375 intel_crtc->cursor_height = height;
4376
4377 intel_crtc_update_cursor(crtc);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05004378
Jesse Barnes79e53942008-11-07 14:24:08 -08004379 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01004380fail_unpin:
4381 i915_gem_object_unpin(bo);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05004382fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10004383 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00004384fail:
4385 drm_gem_object_unreference_unlocked(bo);
Dave Airlie34b8686e2009-01-15 14:03:07 +10004386 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004387}
4388
4389static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4390{
Jesse Barnes79e53942008-11-07 14:24:08 -08004391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004392
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004393 intel_crtc->cursor_x = x;
4394 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07004395
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004396 intel_crtc_update_cursor(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004397
4398 return 0;
4399}
4400
4401/** Sets the color ramps on behalf of RandR */
4402void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4403 u16 blue, int regno)
4404{
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4406
4407 intel_crtc->lut_r[regno] = red >> 8;
4408 intel_crtc->lut_g[regno] = green >> 8;
4409 intel_crtc->lut_b[regno] = blue >> 8;
4410}
4411
Dave Airlieb8c00ac2009-10-06 13:54:01 +10004412void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4413 u16 *blue, int regno)
4414{
4415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4416
4417 *red = intel_crtc->lut_r[regno] << 8;
4418 *green = intel_crtc->lut_g[regno] << 8;
4419 *blue = intel_crtc->lut_b[regno] << 8;
4420}
4421
Jesse Barnes79e53942008-11-07 14:24:08 -08004422static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4423 u16 *blue, uint32_t size)
4424{
4425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4426 int i;
4427
4428 if (size != 256)
4429 return;
4430
4431 for (i = 0; i < 256; i++) {
4432 intel_crtc->lut_r[i] = red[i] >> 8;
4433 intel_crtc->lut_g[i] = green[i] >> 8;
4434 intel_crtc->lut_b[i] = blue[i] >> 8;
4435 }
4436
4437 intel_crtc_load_lut(crtc);
4438}
4439
4440/**
4441 * Get a pipe with a simple mode set on it for doing load-based monitor
4442 * detection.
4443 *
4444 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07004445 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08004446 *
Eric Anholtc751ce42010-03-25 11:48:48 -07004447 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08004448 * configured for it. In the future, it could choose to temporarily disable
4449 * some outputs to free up a pipe for its use.
4450 *
4451 * \return crtc, or NULL if no pipes are available.
4452 */
4453
4454/* VESA 640x480x72Hz mode to set on the pipe */
4455static struct drm_display_mode load_detect_mode = {
4456 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4457 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4458};
4459
Eric Anholt21d40d32010-03-25 11:11:14 -07004460struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004461 struct drm_connector *connector,
Jesse Barnes79e53942008-11-07 14:24:08 -08004462 struct drm_display_mode *mode,
4463 int *dpms_mode)
4464{
4465 struct intel_crtc *intel_crtc;
4466 struct drm_crtc *possible_crtc;
4467 struct drm_crtc *supported_crtc =NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07004468 struct drm_encoder *encoder = &intel_encoder->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08004469 struct drm_crtc *crtc = NULL;
4470 struct drm_device *dev = encoder->dev;
4471 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4472 struct drm_crtc_helper_funcs *crtc_funcs;
4473 int i = -1;
4474
4475 /*
4476 * Algorithm gets a little messy:
4477 * - if the connector already has an assigned crtc, use it (but make
4478 * sure it's on first)
4479 * - try to find the first unused crtc that can drive this connector,
4480 * and use that if we find one
4481 * - if there are no unused crtcs available, try to use the first
4482 * one we found that supports the connector
4483 */
4484
4485 /* See if we already have a CRTC for this connector */
4486 if (encoder->crtc) {
4487 crtc = encoder->crtc;
4488 /* Make sure the crtc and connector are running */
4489 intel_crtc = to_intel_crtc(crtc);
4490 *dpms_mode = intel_crtc->dpms_mode;
4491 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4492 crtc_funcs = crtc->helper_private;
4493 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4494 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4495 }
4496 return crtc;
4497 }
4498
4499 /* Find an unused one (if possible) */
4500 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4501 i++;
4502 if (!(encoder->possible_crtcs & (1 << i)))
4503 continue;
4504 if (!possible_crtc->enabled) {
4505 crtc = possible_crtc;
4506 break;
4507 }
4508 if (!supported_crtc)
4509 supported_crtc = possible_crtc;
4510 }
4511
4512 /*
4513 * If we didn't find an unused CRTC, don't use any.
4514 */
4515 if (!crtc) {
4516 return NULL;
4517 }
4518
4519 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004520 connector->encoder = encoder;
Eric Anholt21d40d32010-03-25 11:11:14 -07004521 intel_encoder->load_detect_temp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004522
4523 intel_crtc = to_intel_crtc(crtc);
4524 *dpms_mode = intel_crtc->dpms_mode;
4525
4526 if (!crtc->enabled) {
4527 if (!mode)
4528 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05004529 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08004530 } else {
4531 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4532 crtc_funcs = crtc->helper_private;
4533 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4534 }
4535
4536 /* Add this connector to the crtc */
4537 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4538 encoder_funcs->commit(encoder);
4539 }
4540 /* let the connector get through one full cycle before testing */
4541 intel_wait_for_vblank(dev);
4542
4543 return crtc;
4544}
4545
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004546void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4547 struct drm_connector *connector, int dpms_mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08004548{
Eric Anholt21d40d32010-03-25 11:11:14 -07004549 struct drm_encoder *encoder = &intel_encoder->enc;
Jesse Barnes79e53942008-11-07 14:24:08 -08004550 struct drm_device *dev = encoder->dev;
4551 struct drm_crtc *crtc = encoder->crtc;
4552 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4553 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4554
Eric Anholt21d40d32010-03-25 11:11:14 -07004555 if (intel_encoder->load_detect_temp) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004556 encoder->crtc = NULL;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08004557 connector->encoder = NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07004558 intel_encoder->load_detect_temp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004559 crtc->enabled = drm_helper_crtc_in_use(crtc);
4560 drm_helper_disable_unused_functions(dev);
4561 }
4562
Eric Anholtc751ce42010-03-25 11:48:48 -07004563 /* Switch crtc and encoder back off if necessary */
Jesse Barnes79e53942008-11-07 14:24:08 -08004564 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4565 if (encoder->crtc == crtc)
4566 encoder_funcs->dpms(encoder, dpms_mode);
4567 crtc_funcs->dpms(crtc, dpms_mode);
4568 }
4569}
4570
4571/* Returns the clock of the currently programmed mode of the given pipe. */
4572static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4573{
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4576 int pipe = intel_crtc->pipe;
4577 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4578 u32 fp;
4579 intel_clock_t clock;
4580
4581 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4582 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4583 else
4584 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4585
4586 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004587 if (IS_PINEVIEW(dev)) {
4588 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4589 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08004590 } else {
4591 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4592 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4593 }
4594
Jesse Barnes79e53942008-11-07 14:24:08 -08004595 if (IS_I9XX(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004596 if (IS_PINEVIEW(dev))
4597 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4598 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08004599 else
4600 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08004601 DPLL_FPA01_P1_POST_DIV_SHIFT);
4602
4603 switch (dpll & DPLL_MODE_MASK) {
4604 case DPLLB_MODE_DAC_SERIAL:
4605 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4606 5 : 10;
4607 break;
4608 case DPLLB_MODE_LVDS:
4609 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4610 7 : 14;
4611 break;
4612 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08004613 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08004614 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4615 return 0;
4616 }
4617
4618 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08004619 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004620 } else {
4621 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4622
4623 if (is_lvds) {
4624 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4625 DPLL_FPA01_P1_POST_DIV_SHIFT);
4626 clock.p2 = 14;
4627
4628 if ((dpll & PLL_REF_INPUT_MASK) ==
4629 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4630 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08004631 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004632 } else
Shaohua Li21778322009-02-23 15:19:16 +08004633 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004634 } else {
4635 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4636 clock.p1 = 2;
4637 else {
4638 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4639 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4640 }
4641 if (dpll & PLL_P2_DIVIDE_BY_4)
4642 clock.p2 = 4;
4643 else
4644 clock.p2 = 2;
4645
Shaohua Li21778322009-02-23 15:19:16 +08004646 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004647 }
4648 }
4649
4650 /* XXX: It would be nice to validate the clocks, but we can't reuse
4651 * i830PllIsValid() because it relies on the xf86_config connector
4652 * configuration being accurate, which it isn't necessarily.
4653 */
4654
4655 return clock.dot;
4656}
4657
4658/** Returns the currently programmed mode of the given pipe. */
4659struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4660 struct drm_crtc *crtc)
4661{
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 int pipe = intel_crtc->pipe;
4665 struct drm_display_mode *mode;
4666 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4667 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4668 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4669 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4670
4671 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4672 if (!mode)
4673 return NULL;
4674
4675 mode->clock = intel_crtc_clock_get(dev, crtc);
4676 mode->hdisplay = (htot & 0xffff) + 1;
4677 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4678 mode->hsync_start = (hsync & 0xffff) + 1;
4679 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4680 mode->vdisplay = (vtot & 0xffff) + 1;
4681 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4682 mode->vsync_start = (vsync & 0xffff) + 1;
4683 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4684
4685 drm_mode_set_name(mode);
4686 drm_mode_set_crtcinfo(mode, 0);
4687
4688 return mode;
4689}
4690
Jesse Barnes652c3932009-08-17 13:31:43 -07004691#define GPU_IDLE_TIMEOUT 500 /* ms */
4692
4693/* When this timer fires, we've been idle for awhile */
4694static void intel_gpu_idle_timer(unsigned long arg)
4695{
4696 struct drm_device *dev = (struct drm_device *)arg;
4697 drm_i915_private_t *dev_priv = dev->dev_private;
4698
Zhao Yakui44d98a62009-10-09 11:39:40 +08004699 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004700
4701 dev_priv->busy = false;
4702
Eric Anholt01dfba92009-09-06 15:18:53 -07004703 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07004704}
4705
Jesse Barnes652c3932009-08-17 13:31:43 -07004706#define CRTC_IDLE_TIMEOUT 1000 /* ms */
4707
4708static void intel_crtc_idle_timer(unsigned long arg)
4709{
4710 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4711 struct drm_crtc *crtc = &intel_crtc->base;
4712 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4713
Zhao Yakui44d98a62009-10-09 11:39:40 +08004714 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004715
4716 intel_crtc->busy = false;
4717
Eric Anholt01dfba92009-09-06 15:18:53 -07004718 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07004719}
4720
4721static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4722{
4723 struct drm_device *dev = crtc->dev;
4724 drm_i915_private_t *dev_priv = dev->dev_private;
4725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4726 int pipe = intel_crtc->pipe;
4727 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4728 int dpll = I915_READ(dpll_reg);
4729
Eric Anholtbad720f2009-10-22 16:11:14 -07004730 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07004731 return;
4732
4733 if (!dev_priv->lvds_downclock_avail)
4734 return;
4735
4736 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08004737 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004738
4739 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07004740 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4741 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07004742
4743 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4744 I915_WRITE(dpll_reg, dpll);
4745 dpll = I915_READ(dpll_reg);
4746 intel_wait_for_vblank(dev);
4747 dpll = I915_READ(dpll_reg);
4748 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08004749 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004750
4751 /* ...and lock them again */
4752 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4753 }
4754
4755 /* Schedule downclock */
4756 if (schedule)
4757 mod_timer(&intel_crtc->idle_timer, jiffies +
4758 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4759}
4760
4761static void intel_decrease_pllclock(struct drm_crtc *crtc)
4762{
4763 struct drm_device *dev = crtc->dev;
4764 drm_i915_private_t *dev_priv = dev->dev_private;
4765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4766 int pipe = intel_crtc->pipe;
4767 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4768 int dpll = I915_READ(dpll_reg);
4769
Eric Anholtbad720f2009-10-22 16:11:14 -07004770 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07004771 return;
4772
4773 if (!dev_priv->lvds_downclock_avail)
4774 return;
4775
4776 /*
4777 * Since this is called by a timer, we should never get here in
4778 * the manual case.
4779 */
4780 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08004781 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004782
4783 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07004784 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4785 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07004786
4787 dpll |= DISPLAY_RATE_SELECT_FPA1;
4788 I915_WRITE(dpll_reg, dpll);
4789 dpll = I915_READ(dpll_reg);
4790 intel_wait_for_vblank(dev);
4791 dpll = I915_READ(dpll_reg);
4792 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08004793 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004794
4795 /* ...and lock them again */
4796 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4797 }
4798
4799}
4800
4801/**
4802 * intel_idle_update - adjust clocks for idleness
4803 * @work: work struct
4804 *
4805 * Either the GPU or display (or both) went idle. Check the busy status
4806 * here and adjust the CRTC and GPU clocks as necessary.
4807 */
4808static void intel_idle_update(struct work_struct *work)
4809{
4810 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4811 idle_work);
4812 struct drm_device *dev = dev_priv->dev;
4813 struct drm_crtc *crtc;
4814 struct intel_crtc *intel_crtc;
Li Peng45ac22c2010-06-12 23:38:35 +08004815 int enabled = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004816
4817 if (!i915_powersave)
4818 return;
4819
4820 mutex_lock(&dev->struct_mutex);
4821
Jesse Barnes7648fa92010-05-20 14:28:11 -07004822 i915_update_gfx_val(dev_priv);
4823
Jesse Barnes652c3932009-08-17 13:31:43 -07004824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4825 /* Skip inactive CRTCs */
4826 if (!crtc->fb)
4827 continue;
4828
Li Peng45ac22c2010-06-12 23:38:35 +08004829 enabled++;
Jesse Barnes652c3932009-08-17 13:31:43 -07004830 intel_crtc = to_intel_crtc(crtc);
4831 if (!intel_crtc->busy)
4832 intel_decrease_pllclock(crtc);
4833 }
4834
Li Peng45ac22c2010-06-12 23:38:35 +08004835 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4836 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4837 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4838 }
4839
Jesse Barnes652c3932009-08-17 13:31:43 -07004840 mutex_unlock(&dev->struct_mutex);
4841}
4842
4843/**
4844 * intel_mark_busy - mark the GPU and possibly the display busy
4845 * @dev: drm device
4846 * @obj: object we're operating on
4847 *
4848 * Callers can use this function to indicate that the GPU is busy processing
4849 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4850 * buffer), we'll also mark the display as busy, so we know to increase its
4851 * clock frequency.
4852 */
4853void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4854{
4855 drm_i915_private_t *dev_priv = dev->dev_private;
4856 struct drm_crtc *crtc = NULL;
4857 struct intel_framebuffer *intel_fb;
4858 struct intel_crtc *intel_crtc;
4859
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08004860 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4861 return;
4862
Li Peng060e6452010-02-10 01:54:24 +08004863 if (!dev_priv->busy) {
4864 if (IS_I945G(dev) || IS_I945GM(dev)) {
4865 u32 fw_blc_self;
Li Pengee980b82010-01-27 19:01:11 +08004866
Li Peng060e6452010-02-10 01:54:24 +08004867 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4868 fw_blc_self = I915_READ(FW_BLC_SELF);
4869 fw_blc_self &= ~FW_BLC_SELF_EN;
4870 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4871 }
Chris Wilson28cf7982009-11-30 01:08:56 +00004872 dev_priv->busy = true;
Li Peng060e6452010-02-10 01:54:24 +08004873 } else
Chris Wilson28cf7982009-11-30 01:08:56 +00004874 mod_timer(&dev_priv->idle_timer, jiffies +
4875 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07004876
4877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4878 if (!crtc->fb)
4879 continue;
4880
4881 intel_crtc = to_intel_crtc(crtc);
4882 intel_fb = to_intel_framebuffer(crtc->fb);
4883 if (intel_fb->obj == obj) {
4884 if (!intel_crtc->busy) {
Li Peng060e6452010-02-10 01:54:24 +08004885 if (IS_I945G(dev) || IS_I945GM(dev)) {
4886 u32 fw_blc_self;
4887
4888 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4889 fw_blc_self = I915_READ(FW_BLC_SELF);
4890 fw_blc_self &= ~FW_BLC_SELF_EN;
4891 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4892 }
Jesse Barnes652c3932009-08-17 13:31:43 -07004893 /* Non-busy -> busy, upclock */
4894 intel_increase_pllclock(crtc, true);
4895 intel_crtc->busy = true;
4896 } else {
4897 /* Busy -> busy, put off timer */
4898 mod_timer(&intel_crtc->idle_timer, jiffies +
4899 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4900 }
4901 }
4902 }
4903}
4904
Jesse Barnes79e53942008-11-07 14:24:08 -08004905static void intel_crtc_destroy(struct drm_crtc *crtc)
4906{
4907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4908
4909 drm_crtc_cleanup(crtc);
4910 kfree(intel_crtc);
4911}
4912
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004913struct intel_unpin_work {
4914 struct work_struct work;
4915 struct drm_device *dev;
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004916 struct drm_gem_object *old_fb_obj;
4917 struct drm_gem_object *pending_flip_obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004918 struct drm_pending_vblank_event *event;
4919 int pending;
4920};
4921
4922static void intel_unpin_work_fn(struct work_struct *__work)
4923{
4924 struct intel_unpin_work *work =
4925 container_of(__work, struct intel_unpin_work, work);
4926
4927 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004928 i915_gem_object_unpin(work->old_fb_obj);
Jesse Barnes75dfca82010-02-10 15:09:44 -08004929 drm_gem_object_unreference(work->pending_flip_obj);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08004930 drm_gem_object_unreference(work->old_fb_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004931 mutex_unlock(&work->dev->struct_mutex);
4932 kfree(work);
4933}
4934
Jesse Barnes1afe3e92010-03-26 10:35:20 -07004935static void do_intel_finish_page_flip(struct drm_device *dev,
4936 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004937{
4938 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4940 struct intel_unpin_work *work;
4941 struct drm_i915_gem_object *obj_priv;
4942 struct drm_pending_vblank_event *e;
4943 struct timeval now;
4944 unsigned long flags;
4945
4946 /* Ignore early vblank irqs */
4947 if (intel_crtc == NULL)
4948 return;
4949
4950 spin_lock_irqsave(&dev->event_lock, flags);
4951 work = intel_crtc->unpin_work;
4952 if (work == NULL || !work->pending) {
4953 spin_unlock_irqrestore(&dev->event_lock, flags);
4954 return;
4955 }
4956
4957 intel_crtc->unpin_work = NULL;
4958 drm_vblank_put(dev, intel_crtc->pipe);
4959
4960 if (work->event) {
4961 e = work->event;
4962 do_gettimeofday(&now);
4963 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4964 e->event.tv_sec = now.tv_sec;
4965 e->event.tv_usec = now.tv_usec;
4966 list_add_tail(&e->base.link,
4967 &e->base.file_priv->event_list);
4968 wake_up_interruptible(&e->base.file_priv->event_wait);
4969 }
4970
4971 spin_unlock_irqrestore(&dev->event_lock, flags);
4972
Daniel Vetter23010e42010-03-08 13:35:02 +01004973 obj_priv = to_intel_bo(work->pending_flip_obj);
Jesse Barnesde3f4402010-01-14 13:18:02 -08004974
4975 /* Initial scanout buffer will have a 0 pending flip count */
4976 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4977 atomic_dec_and_test(&obj_priv->pending_flip))
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004978 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4979 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07004980
4981 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05004982}
4983
Jesse Barnes1afe3e92010-03-26 10:35:20 -07004984void intel_finish_page_flip(struct drm_device *dev, int pipe)
4985{
4986 drm_i915_private_t *dev_priv = dev->dev_private;
4987 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4988
4989 do_intel_finish_page_flip(dev, crtc);
4990}
4991
4992void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4993{
4994 drm_i915_private_t *dev_priv = dev->dev_private;
4995 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4996
4997 do_intel_finish_page_flip(dev, crtc);
4998}
4999
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005000void intel_prepare_page_flip(struct drm_device *dev, int plane)
5001{
5002 drm_i915_private_t *dev_priv = dev->dev_private;
5003 struct intel_crtc *intel_crtc =
5004 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5005 unsigned long flags;
5006
5007 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08005008 if (intel_crtc->unpin_work) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005009 intel_crtc->unpin_work->pending = 1;
Jesse Barnesde3f4402010-01-14 13:18:02 -08005010 } else {
5011 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5012 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005013 spin_unlock_irqrestore(&dev->event_lock, flags);
5014}
5015
5016static int intel_crtc_page_flip(struct drm_crtc *crtc,
5017 struct drm_framebuffer *fb,
5018 struct drm_pending_vblank_event *event)
5019{
5020 struct drm_device *dev = crtc->dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 struct intel_framebuffer *intel_fb;
5023 struct drm_i915_gem_object *obj_priv;
5024 struct drm_gem_object *obj;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 struct intel_unpin_work *work;
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07005027 unsigned long flags, offset;
Zhenyu Wangaacef092010-02-09 09:46:20 +08005028 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5029 int ret, pipesrc;
Jesse Barnes83f7fd02010-04-05 14:03:51 -07005030 u32 flip_mask;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005031
5032 work = kzalloc(sizeof *work, GFP_KERNEL);
5033 if (work == NULL)
5034 return -ENOMEM;
5035
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005036 work->event = event;
5037 work->dev = crtc->dev;
5038 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005039 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005040 INIT_WORK(&work->work, intel_unpin_work_fn);
5041
5042 /* We borrow the event spin lock for protecting unpin_work */
5043 spin_lock_irqsave(&dev->event_lock, flags);
5044 if (intel_crtc->unpin_work) {
5045 spin_unlock_irqrestore(&dev->event_lock, flags);
5046 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01005047
5048 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005049 return -EBUSY;
5050 }
5051 intel_crtc->unpin_work = work;
5052 spin_unlock_irqrestore(&dev->event_lock, flags);
5053
5054 intel_fb = to_intel_framebuffer(fb);
5055 obj = intel_fb->obj;
5056
Chris Wilson468f0b42010-05-27 13:18:13 +01005057 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005058 ret = intel_pin_and_fence_fb_obj(dev, obj);
Chris Wilson96b099f2010-06-07 14:03:04 +01005059 if (ret)
5060 goto cleanup_work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005061
Jesse Barnes75dfca82010-02-10 15:09:44 -08005062 /* Reference the objects for the scheduled work. */
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005063 drm_gem_object_reference(work->old_fb_obj);
Jesse Barnes75dfca82010-02-10 15:09:44 -08005064 drm_gem_object_reference(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005065
5066 crtc->fb = fb;
Chris Wilson2dafb1e2010-06-07 14:03:05 +01005067 ret = i915_gem_object_flush_write_domain(obj);
5068 if (ret)
5069 goto cleanup_objs;
Chris Wilson96b099f2010-06-07 14:03:04 +01005070
5071 ret = drm_vblank_get(dev, intel_crtc->pipe);
5072 if (ret)
5073 goto cleanup_objs;
5074
Daniel Vetter23010e42010-03-08 13:35:02 +01005075 obj_priv = to_intel_bo(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005076 atomic_inc(&obj_priv->pending_flip);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005077 work->pending_flip_obj = obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005078
Jesse Barnes83f7fd02010-04-05 14:03:51 -07005079 if (intel_crtc->plane)
Daniel Vetter6146b3d2010-08-04 21:22:10 +02005080 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
Jesse Barnes83f7fd02010-04-05 14:03:51 -07005081 else
Daniel Vetter6146b3d2010-08-04 21:22:10 +02005082 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Jesse Barnes83f7fd02010-04-05 14:03:51 -07005083
Daniel Vetter6146b3d2010-08-04 21:22:10 +02005084 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5085 BEGIN_LP_RING(2);
5086 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5087 OUT_RING(0);
5088 ADVANCE_LP_RING();
5089 }
Jesse Barnes83f7fd02010-04-05 14:03:51 -07005090
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07005091 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5092 offset = obj_priv->gtt_offset;
5093 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5094
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005095 BEGIN_LP_RING(4);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08005096 if (IS_I965G(dev)) {
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005097 OUT_RING(MI_DISPLAY_FLIP |
5098 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5099 OUT_RING(fb->pitch);
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07005100 OUT_RING(offset | obj_priv->tiling_mode);
Zhenyu Wangaacef092010-02-09 09:46:20 +08005101 pipesrc = I915_READ(pipesrc_reg);
5102 OUT_RING(pipesrc & 0x0fff0fff);
Daniel Vetter69d0b962010-08-04 21:22:09 +02005103 } else if (IS_GEN3(dev)) {
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005104 OUT_RING(MI_DISPLAY_FLIP_I915 |
5105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5106 OUT_RING(fb->pitch);
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07005107 OUT_RING(offset);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08005108 OUT_RING(MI_NOOP);
Daniel Vetter69d0b962010-08-04 21:22:09 +02005109 } else {
5110 OUT_RING(MI_DISPLAY_FLIP |
5111 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5112 OUT_RING(fb->pitch);
5113 OUT_RING(offset);
5114 OUT_RING(MI_NOOP);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08005115 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005116 ADVANCE_LP_RING();
5117
5118 mutex_unlock(&dev->struct_mutex);
5119
Jesse Barnese5510fa2010-07-01 16:48:37 -07005120 trace_i915_flip_request(intel_crtc->plane, obj);
5121
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005122 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01005123
5124cleanup_objs:
5125 drm_gem_object_unreference(work->old_fb_obj);
5126 drm_gem_object_unreference(obj);
5127cleanup_work:
5128 mutex_unlock(&dev->struct_mutex);
5129
5130 spin_lock_irqsave(&dev->event_lock, flags);
5131 intel_crtc->unpin_work = NULL;
5132 spin_unlock_irqrestore(&dev->event_lock, flags);
5133
5134 kfree(work);
5135
5136 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005137}
5138
Jesse Barnes79e53942008-11-07 14:24:08 -08005139static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5140 .dpms = intel_crtc_dpms,
5141 .mode_fixup = intel_crtc_mode_fixup,
5142 .mode_set = intel_crtc_mode_set,
5143 .mode_set_base = intel_pipe_set_base,
Jesse Barnes81255562010-08-02 12:07:50 -07005144 .mode_set_base_atomic = intel_pipe_set_base_atomic,
Jesse Barnes79e53942008-11-07 14:24:08 -08005145 .prepare = intel_crtc_prepare,
5146 .commit = intel_crtc_commit,
Dave Airlie068143d2009-10-05 09:58:02 +10005147 .load_lut = intel_crtc_load_lut,
Jesse Barnes79e53942008-11-07 14:24:08 -08005148};
5149
5150static const struct drm_crtc_funcs intel_crtc_funcs = {
5151 .cursor_set = intel_crtc_cursor_set,
5152 .cursor_move = intel_crtc_cursor_move,
5153 .gamma_set = intel_crtc_gamma_set,
5154 .set_config = drm_crtc_helper_set_config,
5155 .destroy = intel_crtc_destroy,
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005156 .page_flip = intel_crtc_page_flip,
Jesse Barnes79e53942008-11-07 14:24:08 -08005157};
5158
5159
Hannes Ederb358d0a2008-12-18 21:18:47 +01005160static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08005161{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08005162 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005163 struct intel_crtc *intel_crtc;
5164 int i;
5165
5166 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5167 if (intel_crtc == NULL)
5168 return;
5169
5170 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5171
5172 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5173 intel_crtc->pipe = pipe;
Shaohua Li7662c8b2009-06-26 11:23:55 +08005174 intel_crtc->plane = pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08005175 for (i = 0; i < 256; i++) {
5176 intel_crtc->lut_r[i] = i;
5177 intel_crtc->lut_g[i] = i;
5178 intel_crtc->lut_b[i] = i;
5179 }
5180
Jesse Barnes80824002009-09-10 15:28:06 -07005181 /* Swap pipes & planes for FBC on pre-965 */
5182 intel_crtc->pipe = pipe;
5183 intel_crtc->plane = pipe;
5184 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005185 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07005186 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5187 }
5188
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08005189 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5190 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5192 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5193
Jesse Barnes79e53942008-11-07 14:24:08 -08005194 intel_crtc->cursor_addr = 0;
5195 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5196 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5197
Jesse Barnes652c3932009-08-17 13:31:43 -07005198 intel_crtc->busy = false;
5199
5200 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5201 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005202}
5203
Carl Worth08d7b3d2009-04-29 14:43:54 -07005204int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5205 struct drm_file *file_priv)
5206{
5207 drm_i915_private_t *dev_priv = dev->dev_private;
5208 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02005209 struct drm_mode_object *drmmode_obj;
5210 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07005211
5212 if (!dev_priv) {
5213 DRM_ERROR("called with no initialization\n");
5214 return -EINVAL;
5215 }
5216
Daniel Vetterc05422d2009-08-11 16:05:30 +02005217 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5218 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07005219
Daniel Vetterc05422d2009-08-11 16:05:30 +02005220 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07005221 DRM_ERROR("no such CRTC id\n");
5222 return -EINVAL;
5223 }
5224
Daniel Vetterc05422d2009-08-11 16:05:30 +02005225 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5226 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07005227
Daniel Vetterc05422d2009-08-11 16:05:30 +02005228 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07005229}
5230
Jesse Barnes79e53942008-11-07 14:24:08 -08005231struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5232{
5233 struct drm_crtc *crtc = NULL;
5234
5235 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 if (intel_crtc->pipe == pipe)
5238 break;
5239 }
5240 return crtc;
5241}
5242
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005243static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08005244{
5245 int index_mask = 0;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005246 struct drm_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005247 int entry = 0;
5248
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005249 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5250 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Eric Anholt21d40d32010-03-25 11:11:14 -07005251 if (type_mask & intel_encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08005252 index_mask |= (1 << entry);
5253 entry++;
5254 }
5255 return index_mask;
5256}
5257
5258
5259static void intel_setup_outputs(struct drm_device *dev)
5260{
Eric Anholt725e30a2009-01-22 13:01:02 -08005261 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005262 struct drm_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04005263 bool dpd_is_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005264
Zhenyu Wang541998a2009-06-05 15:38:44 +08005265 if (IS_MOBILE(dev) && !IS_I830(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08005266 intel_lvds_init(dev);
5267
Eric Anholtbad720f2009-10-22 16:11:14 -07005268 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04005269 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08005270
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005271 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5272 intel_dp_init(dev, DP_A);
5273
Adam Jacksoncb0953d2010-07-16 14:46:29 -04005274 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5275 intel_dp_init(dev, PCH_DP_D);
5276 }
5277
5278 intel_crt_init(dev);
5279
5280 if (HAS_PCH_SPLIT(dev)) {
5281 int found;
5282
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08005283 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08005284 /* PCH SDVOB multiplex with HDMIB */
5285 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08005286 if (!found)
5287 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005288 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5289 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08005290 }
5291
5292 if (I915_READ(HDMIC) & PORT_DETECTED)
5293 intel_hdmi_init(dev, HDMIC);
5294
5295 if (I915_READ(HDMID) & PORT_DETECTED)
5296 intel_hdmi_init(dev, HDMID);
5297
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005298 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5299 intel_dp_init(dev, PCH_DP_C);
5300
Adam Jacksoncb0953d2010-07-16 14:46:29 -04005301 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005302 intel_dp_init(dev, PCH_DP_D);
5303
Zhenyu Wang103a1962009-11-27 11:44:36 +08005304 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08005305 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08005306
Eric Anholt725e30a2009-01-22 13:01:02 -08005307 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005308 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08005309 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005310 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5311 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08005312 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005313 }
Ma Ling27185ae2009-08-24 13:50:23 +08005314
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005315 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5316 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005317 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005318 }
Eric Anholt725e30a2009-01-22 13:01:02 -08005319 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04005320
5321 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04005322
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005323 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5324 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08005325 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005326 }
Ma Ling27185ae2009-08-24 13:50:23 +08005327
5328 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5329
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005330 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5331 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08005332 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005333 }
5334 if (SUPPORTS_INTEGRATED_DP(dev)) {
5335 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005336 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005337 }
Eric Anholt725e30a2009-01-22 13:01:02 -08005338 }
Ma Ling27185ae2009-08-24 13:50:23 +08005339
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005340 if (SUPPORTS_INTEGRATED_DP(dev) &&
5341 (I915_READ(DP_D) & DP_DETECTED)) {
5342 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005343 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08005344 }
Eric Anholtbad720f2009-10-22 16:11:14 -07005345 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08005346 intel_dvo_init(dev);
5347
Zhenyu Wang103a1962009-11-27 11:44:36 +08005348 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08005349 intel_tv_init(dev);
5350
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005351 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5352 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08005353
Eric Anholt21d40d32010-03-25 11:11:14 -07005354 encoder->possible_crtcs = intel_encoder->crtc_mask;
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08005355 encoder->possible_clones = intel_encoder_clones(dev,
Eric Anholt21d40d32010-03-25 11:11:14 -07005356 intel_encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08005357 }
5358}
5359
5360static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5361{
5362 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005363
5364 drm_framebuffer_cleanup(fb);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005365 drm_gem_object_unreference_unlocked(intel_fb->obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08005366
5367 kfree(intel_fb);
5368}
5369
5370static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5371 struct drm_file *file_priv,
5372 unsigned int *handle)
5373{
5374 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5375 struct drm_gem_object *object = intel_fb->obj;
5376
5377 return drm_gem_handle_create(file_priv, object, handle);
5378}
5379
5380static const struct drm_framebuffer_funcs intel_fb_funcs = {
5381 .destroy = intel_user_framebuffer_destroy,
5382 .create_handle = intel_user_framebuffer_create_handle,
5383};
5384
Dave Airlie38651672010-03-30 05:34:13 +00005385int intel_framebuffer_init(struct drm_device *dev,
5386 struct intel_framebuffer *intel_fb,
5387 struct drm_mode_fb_cmd *mode_cmd,
5388 struct drm_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08005389{
Jesse Barnes79e53942008-11-07 14:24:08 -08005390 int ret;
5391
Jesse Barnes79e53942008-11-07 14:24:08 -08005392 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5393 if (ret) {
5394 DRM_ERROR("framebuffer init failed %d\n", ret);
5395 return ret;
5396 }
5397
5398 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08005399 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08005400 return 0;
5401}
5402
Jesse Barnes79e53942008-11-07 14:24:08 -08005403static struct drm_framebuffer *
5404intel_user_framebuffer_create(struct drm_device *dev,
5405 struct drm_file *filp,
5406 struct drm_mode_fb_cmd *mode_cmd)
5407{
5408 struct drm_gem_object *obj;
Dave Airlie38651672010-03-30 05:34:13 +00005409 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08005410 int ret;
5411
5412 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5413 if (!obj)
5414 return NULL;
5415
Dave Airlie38651672010-03-30 05:34:13 +00005416 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5417 if (!intel_fb)
5418 return NULL;
5419
5420 ret = intel_framebuffer_init(dev, intel_fb,
5421 mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08005422 if (ret) {
Luca Barbieribc9025b2010-02-09 05:49:12 +00005423 drm_gem_object_unreference_unlocked(obj);
Dave Airlie38651672010-03-30 05:34:13 +00005424 kfree(intel_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005425 return NULL;
5426 }
5427
Dave Airlie38651672010-03-30 05:34:13 +00005428 return &intel_fb->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005429}
5430
Jesse Barnes79e53942008-11-07 14:24:08 -08005431static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08005432 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00005433 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08005434};
5435
Chris Wilson9ea8d052010-01-04 18:57:56 +00005436static struct drm_gem_object *
5437intel_alloc_power_context(struct drm_device *dev)
5438{
5439 struct drm_gem_object *pwrctx;
5440 int ret;
5441
Daniel Vetterac52bc52010-04-09 19:05:06 +00005442 pwrctx = i915_gem_alloc_object(dev, 4096);
Chris Wilson9ea8d052010-01-04 18:57:56 +00005443 if (!pwrctx) {
5444 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5445 return NULL;
5446 }
5447
5448 mutex_lock(&dev->struct_mutex);
5449 ret = i915_gem_object_pin(pwrctx, 4096);
5450 if (ret) {
5451 DRM_ERROR("failed to pin power context: %d\n", ret);
5452 goto err_unref;
5453 }
5454
5455 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5456 if (ret) {
5457 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5458 goto err_unpin;
5459 }
5460 mutex_unlock(&dev->struct_mutex);
5461
5462 return pwrctx;
5463
5464err_unpin:
5465 i915_gem_object_unpin(pwrctx);
5466err_unref:
5467 drm_gem_object_unreference(pwrctx);
5468 mutex_unlock(&dev->struct_mutex);
5469 return NULL;
5470}
5471
Jesse Barnes7648fa92010-05-20 14:28:11 -07005472bool ironlake_set_drps(struct drm_device *dev, u8 val)
5473{
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 u16 rgvswctl;
5476
5477 rgvswctl = I915_READ16(MEMSWCTL);
5478 if (rgvswctl & MEMCTL_CMD_STS) {
5479 DRM_DEBUG("gpu busy, RCS change rejected\n");
5480 return false; /* still busy with another command */
5481 }
5482
5483 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5484 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5485 I915_WRITE16(MEMSWCTL, rgvswctl);
5486 POSTING_READ16(MEMSWCTL);
5487
5488 rgvswctl |= MEMCTL_CMD_STS;
5489 I915_WRITE16(MEMSWCTL, rgvswctl);
5490
5491 return true;
5492}
5493
Jesse Barnesf97108d2010-01-29 11:27:07 -08005494void ironlake_enable_drps(struct drm_device *dev)
5495{
5496 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005497 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005498 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08005499
5500 /* 100ms RC evaluation intervals */
5501 I915_WRITE(RCUPEI, 100000);
5502 I915_WRITE(RCDNEI, 100000);
5503
5504 /* Set max/min thresholds to 90ms and 80ms respectively */
5505 I915_WRITE(RCBMAXAVG, 90000);
5506 I915_WRITE(RCBMINAVG, 80000);
5507
5508 I915_WRITE(MEMIHYST, 1);
5509
5510 /* Set up min, max, and cur for interrupt handling */
5511 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5512 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5513 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5514 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005515 fstart = fmax;
5516
Jesse Barnesf97108d2010-01-29 11:27:07 -08005517 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5518 PXVFREQ_PX_SHIFT;
5519
Jesse Barnes7648fa92010-05-20 14:28:11 -07005520 dev_priv->fmax = fstart; /* IPS callback will increase this */
5521 dev_priv->fstart = fstart;
5522
5523 dev_priv->max_delay = fmax;
Jesse Barnesf97108d2010-01-29 11:27:07 -08005524 dev_priv->min_delay = fmin;
5525 dev_priv->cur_delay = fstart;
5526
Jesse Barnes7648fa92010-05-20 14:28:11 -07005527 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5528 fstart);
5529
Jesse Barnesf97108d2010-01-29 11:27:07 -08005530 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5531
5532 /*
5533 * Interrupts will be enabled in ironlake_irq_postinstall
5534 */
5535
5536 I915_WRITE(VIDSTART, vstart);
5537 POSTING_READ(VIDSTART);
5538
5539 rgvmodectl |= MEMMODE_SWMODE_EN;
5540 I915_WRITE(MEMMODECTL, rgvmodectl);
5541
Chris Wilson913d8d12010-08-07 11:01:35 +01005542 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5543 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08005544 msleep(1);
5545
Jesse Barnes7648fa92010-05-20 14:28:11 -07005546 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005547
Jesse Barnes7648fa92010-05-20 14:28:11 -07005548 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5549 I915_READ(0x112e0);
5550 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5551 dev_priv->last_count2 = I915_READ(0x112f4);
5552 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005553}
5554
5555void ironlake_disable_drps(struct drm_device *dev)
5556{
5557 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07005558 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005559
5560 /* Ack interrupts, disable EFC interrupt */
5561 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5562 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5563 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5564 I915_WRITE(DEIIR, DE_PCU_EVENT);
5565 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5566
5567 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07005568 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08005569 msleep(1);
5570 rgvswctl |= MEMCTL_CMD_STS;
5571 I915_WRITE(MEMSWCTL, rgvswctl);
5572 msleep(1);
5573
5574}
5575
Jesse Barnes7648fa92010-05-20 14:28:11 -07005576static unsigned long intel_pxfreq(u32 vidfreq)
5577{
5578 unsigned long freq;
5579 int div = (vidfreq & 0x3f0000) >> 16;
5580 int post = (vidfreq & 0x3000) >> 12;
5581 int pre = (vidfreq & 0x7);
5582
5583 if (!pre)
5584 return 0;
5585
5586 freq = ((div * 133333) / ((1<<post) * pre));
5587
5588 return freq;
5589}
5590
5591void intel_init_emon(struct drm_device *dev)
5592{
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 u32 lcfuse;
5595 u8 pxw[16];
5596 int i;
5597
5598 /* Disable to program */
5599 I915_WRITE(ECR, 0);
5600 POSTING_READ(ECR);
5601
5602 /* Program energy weights for various events */
5603 I915_WRITE(SDEW, 0x15040d00);
5604 I915_WRITE(CSIEW0, 0x007f0000);
5605 I915_WRITE(CSIEW1, 0x1e220004);
5606 I915_WRITE(CSIEW2, 0x04000004);
5607
5608 for (i = 0; i < 5; i++)
5609 I915_WRITE(PEW + (i * 4), 0);
5610 for (i = 0; i < 3; i++)
5611 I915_WRITE(DEW + (i * 4), 0);
5612
5613 /* Program P-state weights to account for frequency power adjustment */
5614 for (i = 0; i < 16; i++) {
5615 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5616 unsigned long freq = intel_pxfreq(pxvidfreq);
5617 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5618 PXVFREQ_PX_SHIFT;
5619 unsigned long val;
5620
5621 val = vid * vid;
5622 val *= (freq / 1000);
5623 val *= 255;
5624 val /= (127*127*900);
5625 if (val > 0xff)
5626 DRM_ERROR("bad pxval: %ld\n", val);
5627 pxw[i] = val;
5628 }
5629 /* Render standby states get 0 weight */
5630 pxw[14] = 0;
5631 pxw[15] = 0;
5632
5633 for (i = 0; i < 4; i++) {
5634 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5635 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5636 I915_WRITE(PXW + (i * 4), val);
5637 }
5638
5639 /* Adjust magic regs to magic values (more experimental results) */
5640 I915_WRITE(OGW0, 0);
5641 I915_WRITE(OGW1, 0);
5642 I915_WRITE(EG0, 0x00007f00);
5643 I915_WRITE(EG1, 0x0000000e);
5644 I915_WRITE(EG2, 0x000e0000);
5645 I915_WRITE(EG3, 0x68000300);
5646 I915_WRITE(EG4, 0x42000000);
5647 I915_WRITE(EG5, 0x00140031);
5648 I915_WRITE(EG6, 0);
5649 I915_WRITE(EG7, 0);
5650
5651 for (i = 0; i < 8; i++)
5652 I915_WRITE(PXWL + (i * 4), 0);
5653
5654 /* Enable PMON + select events */
5655 I915_WRITE(ECR, 0x80000019);
5656
5657 lcfuse = I915_READ(LCFUSE02);
5658
5659 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5660}
5661
Jesse Barnes652c3932009-08-17 13:31:43 -07005662void intel_init_clock_gating(struct drm_device *dev)
5663{
5664 struct drm_i915_private *dev_priv = dev->dev_private;
5665
5666 /*
5667 * Disable clock gating reported to work incorrectly according to the
5668 * specs, but enable as much else as we can.
5669 */
Eric Anholtbad720f2009-10-22 16:11:14 -07005670 if (HAS_PCH_SPLIT(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07005671 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5672
5673 if (IS_IRONLAKE(dev)) {
5674 /* Required for FBC */
5675 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5676 /* Required for CxSR */
5677 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5678
5679 I915_WRITE(PCH_3DCGDIS0,
5680 MARIUNIT_CLOCK_GATE_DISABLE |
5681 SVSMUNIT_CLOCK_GATE_DISABLE);
5682 }
5683
5684 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005685
5686 /*
5687 * According to the spec the following bits should be set in
5688 * order to enable memory self-refresh
5689 * The bit 22/21 of 0x42004
5690 * The bit 5 of 0x42020
5691 * The bit 15 of 0x45000
5692 */
5693 if (IS_IRONLAKE(dev)) {
5694 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5695 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5696 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5697 I915_WRITE(ILK_DSPCLK_GATE,
5698 (I915_READ(ILK_DSPCLK_GATE) |
5699 ILK_DPARB_CLK_GATE));
5700 I915_WRITE(DISP_ARB_CTL,
5701 (I915_READ(DISP_ARB_CTL) |
5702 DISP_FBC_WM_DIS));
5703 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08005704 /*
5705 * Based on the document from hardware guys the following bits
5706 * should be set unconditionally in order to enable FBC.
5707 * The bit 22 of 0x42000
5708 * The bit 22 of 0x42004
5709 * The bit 7,8,9 of 0x42020.
5710 */
5711 if (IS_IRONLAKE_M(dev)) {
5712 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5713 I915_READ(ILK_DISPLAY_CHICKEN1) |
5714 ILK_FBCQ_DIS);
5715 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5716 I915_READ(ILK_DISPLAY_CHICKEN2) |
5717 ILK_DPARB_GATE);
5718 I915_WRITE(ILK_DSPCLK_GATE,
5719 I915_READ(ILK_DSPCLK_GATE) |
5720 ILK_DPFC_DIS1 |
5721 ILK_DPFC_DIS2 |
5722 ILK_CLK_FBC);
5723 }
Zhenyu Wangc03342f2009-09-29 11:01:23 +08005724 return;
5725 } else if (IS_G4X(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07005726 uint32_t dspclk_gate;
5727 I915_WRITE(RENCLK_GATE_D1, 0);
5728 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5729 GS_UNIT_CLOCK_GATE_DISABLE |
5730 CL_UNIT_CLOCK_GATE_DISABLE);
5731 I915_WRITE(RAMCLK_GATE_D, 0);
5732 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5733 OVRUNIT_CLOCK_GATE_DISABLE |
5734 OVCUNIT_CLOCK_GATE_DISABLE;
5735 if (IS_GM45(dev))
5736 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5737 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5738 } else if (IS_I965GM(dev)) {
5739 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5740 I915_WRITE(RENCLK_GATE_D2, 0);
5741 I915_WRITE(DSPCLK_GATE_D, 0);
5742 I915_WRITE(RAMCLK_GATE_D, 0);
5743 I915_WRITE16(DEUC, 0);
5744 } else if (IS_I965G(dev)) {
5745 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5746 I965_RCC_CLOCK_GATE_DISABLE |
5747 I965_RCPB_CLOCK_GATE_DISABLE |
5748 I965_ISC_CLOCK_GATE_DISABLE |
5749 I965_FBC_CLOCK_GATE_DISABLE);
5750 I915_WRITE(RENCLK_GATE_D2, 0);
5751 } else if (IS_I9XX(dev)) {
5752 u32 dstate = I915_READ(D_STATE);
5753
5754 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5755 DSTATE_DOT_CLOCK_GATING;
5756 I915_WRITE(D_STATE, dstate);
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02005757 } else if (IS_I85X(dev) || IS_I865G(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07005758 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5759 } else if (IS_I830(dev)) {
5760 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5761 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005762
5763 /*
5764 * GPU can automatically power down the render unit if given a page
5765 * to save state.
5766 */
Andrew Lutomirski1d3c36ad2009-12-21 10:10:22 -05005767 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00005768 struct drm_i915_gem_object *obj_priv = NULL;
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005769
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005770 if (dev_priv->pwrctx) {
Daniel Vetter23010e42010-03-08 13:35:02 +01005771 obj_priv = to_intel_bo(dev_priv->pwrctx);
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005772 } else {
Chris Wilson9ea8d052010-01-04 18:57:56 +00005773 struct drm_gem_object *pwrctx;
5774
5775 pwrctx = intel_alloc_power_context(dev);
5776 if (pwrctx) {
5777 dev_priv->pwrctx = pwrctx;
Daniel Vetter23010e42010-03-08 13:35:02 +01005778 obj_priv = to_intel_bo(pwrctx);
Andrew Lutomirski7e8b60f2009-11-08 13:49:51 -05005779 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005780 }
5781
Chris Wilson9ea8d052010-01-04 18:57:56 +00005782 if (obj_priv) {
5783 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5784 I915_WRITE(MCHBAR_RENDER_STANDBY,
5785 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5786 }
Jesse Barnes97f5ab62009-10-08 10:16:48 -07005787 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005788}
5789
Jesse Barnese70236a2009-09-21 10:42:27 -07005790/* Set up chip specific display functions */
5791static void intel_init_display(struct drm_device *dev)
5792{
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794
5795 /* We always want a DPMS function */
Eric Anholtbad720f2009-10-22 16:11:14 -07005796 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005797 dev_priv->display.dpms = ironlake_crtc_dpms;
Jesse Barnese70236a2009-09-21 10:42:27 -07005798 else
5799 dev_priv->display.dpms = i9xx_crtc_dpms;
5800
Adam Jacksonee5382a2010-04-23 11:17:39 -04005801 if (I915_HAS_FBC(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08005802 if (IS_IRONLAKE_M(dev)) {
5803 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5804 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5805 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5806 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07005807 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5808 dev_priv->display.enable_fbc = g4x_enable_fbc;
5809 dev_priv->display.disable_fbc = g4x_disable_fbc;
Robert Hooker8d06a1e2010-03-19 15:13:27 -04005810 } else if (IS_I965GM(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07005811 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5812 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5813 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5814 }
Jesse Barnes74dff282009-09-14 15:39:40 -07005815 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07005816 }
5817
5818 /* Returns the core display clock speed */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005819 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07005820 dev_priv->display.get_display_clock_speed =
5821 i945_get_display_clock_speed;
5822 else if (IS_I915G(dev))
5823 dev_priv->display.get_display_clock_speed =
5824 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005825 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005826 dev_priv->display.get_display_clock_speed =
5827 i9xx_misc_get_display_clock_speed;
5828 else if (IS_I915GM(dev))
5829 dev_priv->display.get_display_clock_speed =
5830 i915gm_get_display_clock_speed;
5831 else if (IS_I865G(dev))
5832 dev_priv->display.get_display_clock_speed =
5833 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02005834 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005835 dev_priv->display.get_display_clock_speed =
5836 i855_get_display_clock_speed;
5837 else /* 852, 830 */
5838 dev_priv->display.get_display_clock_speed =
5839 i830_get_display_clock_speed;
5840
5841 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08005842 if (HAS_PCH_SPLIT(dev)) {
5843 if (IS_IRONLAKE(dev)) {
5844 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5845 dev_priv->display.update_wm = ironlake_update_wm;
5846 else {
5847 DRM_DEBUG_KMS("Failed to get proper latency. "
5848 "Disable CxSR\n");
5849 dev_priv->display.update_wm = NULL;
5850 }
5851 } else
5852 dev_priv->display.update_wm = NULL;
5853 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08005854 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08005855 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08005856 dev_priv->fsb_freq,
5857 dev_priv->mem_freq)) {
5858 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08005859 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08005860 "disabling CxSR\n",
Li Peng95534262010-05-18 18:58:44 +08005861 (dev_priv->is_ddr3 == 1) ? "3": "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08005862 dev_priv->fsb_freq, dev_priv->mem_freq);
5863 /* Disable CxSR and never update its watermark again */
5864 pineview_disable_cxsr(dev);
5865 dev_priv->display.update_wm = NULL;
5866 } else
5867 dev_priv->display.update_wm = pineview_update_wm;
5868 } else if (IS_G4X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005869 dev_priv->display.update_wm = g4x_update_wm;
5870 else if (IS_I965G(dev))
5871 dev_priv->display.update_wm = i965_update_wm;
Adam Jackson8f4695e2010-04-16 18:20:57 -04005872 else if (IS_I9XX(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07005873 dev_priv->display.update_wm = i9xx_update_wm;
5874 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04005875 } else if (IS_I85X(dev)) {
5876 dev_priv->display.update_wm = i9xx_update_wm;
5877 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07005878 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04005879 dev_priv->display.update_wm = i830_update_wm;
5880 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07005881 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5882 else
5883 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07005884 }
5885}
5886
Jesse Barnesb690e962010-07-19 13:53:12 -07005887/*
5888 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5889 * resume, or other times. This quirk makes sure that's the case for
5890 * affected systems.
5891 */
5892static void quirk_pipea_force (struct drm_device *dev)
5893{
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895
5896 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5897 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5898}
5899
5900struct intel_quirk {
5901 int device;
5902 int subsystem_vendor;
5903 int subsystem_device;
5904 void (*hook)(struct drm_device *dev);
5905};
5906
5907struct intel_quirk intel_quirks[] = {
5908 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5909 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5910 /* HP Mini needs pipe A force quirk (LP: #322104) */
5911 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5912
5913 /* Thinkpad R31 needs pipe A force quirk */
5914 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5915 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5916 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5917
5918 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5919 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5920 /* ThinkPad X40 needs pipe A force quirk */
5921
5922 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5923 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5924
5925 /* 855 & before need to leave pipe A & dpll A up */
5926 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5927 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5928};
5929
5930static void intel_init_quirks(struct drm_device *dev)
5931{
5932 struct pci_dev *d = dev->pdev;
5933 int i;
5934
5935 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5936 struct intel_quirk *q = &intel_quirks[i];
5937
5938 if (d->device == q->device &&
5939 (d->subsystem_vendor == q->subsystem_vendor ||
5940 q->subsystem_vendor == PCI_ANY_ID) &&
5941 (d->subsystem_device == q->subsystem_device ||
5942 q->subsystem_device == PCI_ANY_ID))
5943 q->hook(dev);
5944 }
5945}
5946
Jesse Barnes79e53942008-11-07 14:24:08 -08005947void intel_modeset_init(struct drm_device *dev)
5948{
Jesse Barnes652c3932009-08-17 13:31:43 -07005949 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005950 int i;
5951
5952 drm_mode_config_init(dev);
5953
5954 dev->mode_config.min_width = 0;
5955 dev->mode_config.min_height = 0;
5956
5957 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5958
Jesse Barnesb690e962010-07-19 13:53:12 -07005959 intel_init_quirks(dev);
5960
Jesse Barnese70236a2009-09-21 10:42:27 -07005961 intel_init_display(dev);
5962
Jesse Barnes79e53942008-11-07 14:24:08 -08005963 if (IS_I965G(dev)) {
5964 dev->mode_config.max_width = 8192;
5965 dev->mode_config.max_height = 8192;
Keith Packard5e4d6fa2009-07-12 23:53:17 -07005966 } else if (IS_I9XX(dev)) {
5967 dev->mode_config.max_width = 4096;
5968 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08005969 } else {
5970 dev->mode_config.max_width = 2048;
5971 dev->mode_config.max_height = 2048;
5972 }
5973
5974 /* set memory base */
5975 if (IS_I9XX(dev))
5976 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5977 else
5978 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5979
5980 if (IS_MOBILE(dev) || IS_I9XX(dev))
Dave Airliea3524f12010-06-06 18:59:41 +10005981 dev_priv->num_pipe = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08005982 else
Dave Airliea3524f12010-06-06 18:59:41 +10005983 dev_priv->num_pipe = 1;
Zhao Yakui28c97732009-10-09 11:39:41 +08005984 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10005985 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08005986
Dave Airliea3524f12010-06-06 18:59:41 +10005987 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005988 intel_crtc_init(dev, i);
5989 }
5990
5991 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07005992
5993 intel_init_clock_gating(dev);
5994
Jesse Barnes7648fa92010-05-20 14:28:11 -07005995 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08005996 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07005997 intel_init_emon(dev);
5998 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08005999
Jesse Barnes652c3932009-08-17 13:31:43 -07006000 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6001 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6002 (unsigned long)dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02006003
6004 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006005}
6006
6007void intel_modeset_cleanup(struct drm_device *dev)
6008{
Jesse Barnes652c3932009-08-17 13:31:43 -07006009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 struct drm_crtc *crtc;
6011 struct intel_crtc *intel_crtc;
6012
6013 mutex_lock(&dev->struct_mutex);
6014
Dave Airlieeb1f8e42010-05-07 06:42:51 +00006015 drm_kms_helper_poll_fini(dev);
Dave Airlie38651672010-03-30 05:34:13 +00006016 intel_fbdev_fini(dev);
6017
Jesse Barnes652c3932009-08-17 13:31:43 -07006018 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6019 /* Skip inactive CRTCs */
6020 if (!crtc->fb)
6021 continue;
6022
6023 intel_crtc = to_intel_crtc(crtc);
6024 intel_increase_pllclock(crtc, false);
6025 del_timer_sync(&intel_crtc->idle_timer);
6026 }
6027
Jesse Barnes652c3932009-08-17 13:31:43 -07006028 del_timer_sync(&dev_priv->idle_timer);
6029
Jesse Barnese70236a2009-09-21 10:42:27 -07006030 if (dev_priv->display.disable_fbc)
6031 dev_priv->display.disable_fbc(dev);
6032
Jesse Barnes97f5ab62009-10-08 10:16:48 -07006033 if (dev_priv->pwrctx) {
Kristian Høgsbergc1b5dea2009-11-11 12:19:18 -05006034 struct drm_i915_gem_object *obj_priv;
6035
Daniel Vetter23010e42010-03-08 13:35:02 +01006036 obj_priv = to_intel_bo(dev_priv->pwrctx);
Kristian Høgsbergc1b5dea2009-11-11 12:19:18 -05006037 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6038 I915_READ(PWRCTXA);
Jesse Barnes97f5ab62009-10-08 10:16:48 -07006039 i915_gem_object_unpin(dev_priv->pwrctx);
6040 drm_gem_object_unreference(dev_priv->pwrctx);
6041 }
6042
Jesse Barnesf97108d2010-01-29 11:27:07 -08006043 if (IS_IRONLAKE_M(dev))
6044 ironlake_disable_drps(dev);
6045
Kristian Høgsberg69341a52009-11-11 12:19:17 -05006046 mutex_unlock(&dev->struct_mutex);
6047
Jesse Barnes79e53942008-11-07 14:24:08 -08006048 drm_mode_config_cleanup(dev);
6049}
6050
6051
Dave Airlie28d52042009-09-21 14:33:58 +10006052/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08006053 * Return which encoder is currently attached for connector.
6054 */
6055struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08006056{
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08006057 struct drm_mode_object *obj;
6058 struct drm_encoder *encoder;
6059 int i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006060
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08006061 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6062 if (connector->encoder_ids[i] == 0)
6063 break;
6064
6065 obj = drm_mode_object_find(connector->dev,
6066 connector->encoder_ids[i],
6067 DRM_MODE_OBJECT_ENCODER);
6068 if (!obj)
6069 continue;
6070
6071 encoder = obj_to_encoder(obj);
6072 return encoder;
6073 }
6074 return NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006075}
Dave Airlie28d52042009-09-21 14:33:58 +10006076
6077/*
6078 * set vga decode state - true == enable VGA decode
6079 */
6080int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6081{
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 u16 gmch_ctrl;
6084
6085 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6086 if (state)
6087 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6088 else
6089 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6090 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6091 return 0;
6092}