| commit | 5ddb954b9ee50824977d2931e0ff58b3050b337d | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Sat Aug 07 11:01:36 2010 +0100 |
| committer | Eric Anholt <eric@anholt.net> | Mon Aug 09 11:24:35 2010 -0700 |
| tree | 11812f1a8d79c2a6dedf9091250810f600e74683 | |
| parent | 913d8d110078788c14812dce8bb62c37946821d2 [diff] [blame] |
drm/i915/edp: Flush the write before waiting for PLLs Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0bf683d..2a32a7b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1665,6 +1665,7 @@ dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); + POSTING_READ(DP_A); udelay(200); }