blob: ca1701081c56c00652c916c75bd98848bbf68e0e [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100040#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080041#include "drm_crtc_helper.h"
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Zhenyu Wang32f9d652009-07-24 01:00:32 +080044#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
Akshay Joshi0206e352011-08-16 15:34:10 -040046bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
50typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040051 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080060} intel_clock_t;
61
62typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040063 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080064} intel_range_t;
65
66typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040067 int dot_limit;
68 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080069} intel_p2_t;
70
71#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080072typedef struct intel_limit intel_limit_t;
73struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040074 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
Sean Paulcec2f352012-01-10 15:09:36 -080077 int, int, intel_clock_t *, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080078};
Jesse Barnes79e53942008-11-07 14:24:08 -080079
Jesse Barnes2377b742010-07-07 14:06:43 -070080/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
Ma Lingd4906092009-03-18 20:13:27 +080083static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080085 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080087static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080089 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080091
Keith Packarda4fc5ed2009-04-07 16:16:42 -070092static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080094 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080096static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050097intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080098 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700100
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
Chris Wilson021357a2010-09-07 20:54:59 +0100106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
Chris Wilson8b99e682010-10-13 09:59:17 +0100109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100114}
115
Keith Packarde4b36692009-06-05 19:22:17 -0700116static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800127 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800141 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700142};
Eric Anholt273e27c2011-03-30 13:01:10 -0700143
Keith Packarde4b36692009-06-05 19:22:17 -0700144static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800155 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800169 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700170};
171
Eric Anholt273e27c2011-03-30 13:01:10 -0700172
Keith Packarde4b36692009-06-05 19:22:17 -0700173static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800185 },
Ma Lingd4906092009-03-18 20:13:27 +0800186 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800200 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800214 },
Ma Lingd4906092009-03-18 20:13:27 +0800215 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800229 },
Ma Lingd4906092009-03-18 20:13:27 +0800230 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700245};
246
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500247static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700250 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700253 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800260 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700261};
262
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500263static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800274 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700275};
276
Eric Anholt273e27c2011-03-30 13:01:10 -0700277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800282static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800293 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700294};
295
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800296static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800321 .find_pll = intel_g4x_find_best_PLL,
322};
323
Eric Anholt273e27c2011-03-30 13:01:10 -0700324/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400333 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400347 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700363 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800365};
366
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
Jesse Barnes57f350b2012-03-28 13:39:25 -0700409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
Jesse Barnes57f350b2012-03-28 13:39:25 -0700456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
Daniel Vetter618563e2012-04-01 13:38:50 +0200467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
Takashi Iwaib0354382012-03-20 13:07:05 +0100485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
Takashi Iwai121d5272012-03-20 13:07:06 +0100490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
Daniel Vetter618563e2012-04-01 13:38:50 +0200494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
Takashi Iwaib0354382012-03-20 13:07:05 +0100497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
Seth Forshee14d94a32012-06-13 13:46:58 -0500506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
Takashi Iwaib0354382012-03-20 13:07:05 +0100507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
Chris Wilson1b894b52010-12-14 20:04:54 +0000513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800515{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800518 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800522 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000523 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000528 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800536 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800537 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800538
539 return limit;
540}
541
Ma Ling044c7c42009-03-18 20:13:23 +0800542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100549 if (is_dual_link_lvds(dev_priv, LVDS))
Ma Ling044c7c42009-03-18 20:13:23 +0800550 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700551 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800552 else
553 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700554 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700557 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700559 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700561 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800562 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700563 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800564
565 return limit;
566}
567
Chris Wilson1b894b52010-12-14 20:04:54 +0000568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
Eric Anholtbad720f2009-10-22 16:11:14 -0700573 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000574 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800575 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800576 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500577 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500579 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800580 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500581 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700596 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 else
Keith Packarde4b36692009-06-05 19:22:17 -0700598 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 }
600 return limit;
601}
602
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800605{
Shaohua Li21778322009-02-23 15:19:16 +0800606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800616 return;
617 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
Jesse Barnes79e53942008-11-07 14:24:08 -0800624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800628{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100629 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100630 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800631
Daniel Vetter6c2b7c12012-07-05 09:50:24 +0200632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100634 return true;
635
636 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800637}
638
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
Chris Wilson1b894b52010-12-14 20:04:54 +0000645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800648{
Jesse Barnes79e53942008-11-07 14:24:08 -0800649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400650 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800651 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400652 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400654 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400656 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400658 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400660 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400662 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400664 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400669 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800670
671 return true;
672}
673
Ma Lingd4906092009-03-18 20:13:27 +0800674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800678
Jesse Barnes79e53942008-11-07 14:24:08 -0800679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 int err = target;
684
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800686 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
Takashi Iwaib0354382012-03-20 13:07:05 +0100693 if (is_dual_link_lvds(dev_priv, LVDS))
Jesse Barnes79e53942008-11-07 14:24:08 -0800694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
Akshay Joshi0206e352011-08-16 15:34:10 -0400704 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800705
Zhao Yakui42158662009-11-20 11:24:18 +0800706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800717 int this_err;
718
Shaohua Li21778322009-02-23 15:19:16 +0800719 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800722 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
Ma Lingd4906092009-03-18 20:13:27 +0800740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800755 int lvds_reg;
756
Eric Anholtc619eed2010-01-28 16:45:52 -0800757 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200775 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200777 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
Shaohua Li21778322009-02-23 15:19:16 +0800786 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800789 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000793
794 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800805 return found;
806}
Ma Lingd4906092009-03-18 20:13:27 +0800807
Zhenyu Wang2c072452009-06-05 15:38:42 +0800808static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800815
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700839{
Chris Wilson5eddb702010-09-11 13:48:45 +0100840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700860}
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
Alan Coxaf447bd2012-07-25 13:49:18 +0100872 flag = 0;
Jesse Barnesa0c4da242012-06-15 11:55:13 -0700873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700929
Paulo Zanonia928d532012-05-04 17:18:15 -0300930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800950{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800952 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700953
Paulo Zanonia928d532012-05-04 17:18:15 -0300954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
Chris Wilson300387c2010-09-05 20:25:43 +0100959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700975 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
Keith Packardab7ad7f2010-10-03 00:33:06 -0700982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100997 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700998 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001002
Keith Packardab7ad7f2010-10-03 00:33:06 -07001003 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001004 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001005
Keith Packardab7ad7f2010-10-03 00:33:06 -07001006 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -07001009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001011 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001012 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
Paulo Zanoni837ba002012-05-04 17:18:14 -03001015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
Keith Packardab7ad7f2010-10-03 00:33:06 -07001020 /* Wait for the display line to settle */
1021 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001022 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001023 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -03001024 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001029}
1030
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
Jesse Barnes040484a2011-01-03 12:14:26 -08001054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
Chris Wilson92b27b02012-05-20 18:10:50 +01001056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001059{
Jesse Barnes040484a2011-01-03 12:14:26 -08001060 u32 val;
1061 bool cur_state;
1062
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
Chris Wilson92b27b02012-05-20 18:10:50 +01001068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001070 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071
Chris Wilson92b27b02012-05-20 18:10:50 +01001072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
Chris Wilson92b27b02012-05-20 18:10:50 +01001083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001095 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001096}
Chris Wilson92b27b02012-05-20 18:10:50 +01001097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
Jesse Barnes040484a2011-01-03 12:14:26 -08001099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
Jesse Barnes040484a2011-01-03 12:14:26 -08001160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
Jesse Barnesea0760c2011-01-04 15:09:32 -08001180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001186 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001206 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001207}
1208
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211{
1212 int reg;
1213 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001214 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001215
Daniel Vetter8e636782012-01-22 01:36:48 +01001216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
Jesse Barnesb24e7172011-01-04 15:09:30 -08001220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001225 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001226}
1227
Chris Wilson931872f2012-01-16 23:01:13 +00001228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001230{
1231 int reg;
1232 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001233 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001241}
1242
Chris Wilson931872f2012-01-16 23:01:13 +00001243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
Jesse Barnes19ec1352011-02-02 12:28:02 -08001253 /* Planes are fixed to pipes on ILK+ */
Adam Jackson28c057942011-10-07 14:38:42 -04001254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001260 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001261 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001262
Jesse Barnesb24e7172011-01-04 15:09:30 -08001263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001272 }
1273}
1274
Jesse Barnes92f25842011-01-04 15:09:34 -08001275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
Jesse Barnes92f25842011-01-04 15:09:34 -08001285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001304}
1305
Keith Packard4e634382011-08-06 10:39:45 -07001306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
Keith Packard1519b992011-08-06 10:35:34 -07001324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
Jesse Barnes291906f2011-02-02 12:28:03 -08001371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001372 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001373{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001374 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001377 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001386 u32 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001389 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001400
Keith Packardf0575e92011-07-25 22:12:43 -07001401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001408 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001409 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001415 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
Jesse Barnesb24e7172011-01-04 15:09:30 -08001422/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
Thomas Richter7434a252012-07-18 19:22:30 +02001432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001434 */
Daniel Vettera37b9b32012-08-12 19:27:09 +02001435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
Jesse Barnesa0c4da242012-06-15 11:55:13 -07001441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001526 u32 value = 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001554/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001563{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Chris Wilson48da64a2012-05-13 20:16:12 +01001565 struct intel_pch_pll *pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001566 int reg;
1567 u32 val;
1568
Chris Wilson48da64a2012-05-13 20:16:12 +01001569 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001570 BUG_ON(dev_priv->info->gen < 5);
Chris Wilson48da64a2012-05-13 20:16:12 +01001571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001585 if (pll->active++ && pll->on) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001586 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001598
1599 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001600}
1601
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001603{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001606 int reg;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001607 u32 val;
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001608
Jesse Barnes92f25842011-01-04 15:09:34 -08001609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001611 if (pll == NULL)
1612 return;
1613
Chris Wilson48da64a2012-05-13 20:16:12 +01001614 if (WARN_ON(pll->refcount == 0))
1615 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
Chris Wilson48da64a2012-05-13 20:16:12 +01001621 if (WARN_ON(pll->active == 0)) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001622 assert_pch_pll_disabled(dev_priv, pll, NULL);
Chris Wilson48da64a2012-05-13 20:16:12 +01001623 return;
1624 }
1625
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001626 if (--pll->active) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001627 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
Jesse Barnes92f25842011-01-04 15:09:34 -08001632
1633 /* Make sure transcoder isn't still depending on us */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001635
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001636 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001642
1643 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001644}
1645
Jesse Barnes040484a2011-01-03 12:14:26 -08001646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001650 u32 val, pipeconf_val;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Jesse Barnes040484a2011-01-03 12:14:26 -08001652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
Chris Wilson92b27b02012-05-20 18:10:50 +01001657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001671 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001679 val |= pipeconf_val & PIPE_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001680 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001689 else
1690 val |= TRANS_PROGRESSIVE;
1691
Jesse Barnes040484a2011-01-03 12:14:26 -08001692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
Jesse Barnes291906f2011-02-02 12:28:03 -08001707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
Jesse Barnes040484a2011-01-03 12:14:26 -08001710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001717}
1718
Jesse Barnes92f25842011-01-04 15:09:34 -08001719/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001720 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001765 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
Keith Packardd74362c2011-07-28 14:47:14 -07001801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
Jesse Barnesb24e7172011-01-04 15:09:30 -08001812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001835 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
Jesse Barnesb24e7172011-01-04 15:09:30 -08001839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001863static void disable_pch_dp(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001864 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001865{
1866 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001869 I915_WRITE(reg, val & ~DP_PORT_EN);
Keith Packardf0575e92011-07-25 22:12:43 -07001870 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001880 I915_WRITE(reg, val & ~PORT_ENABLE);
Keith Packardf0575e92011-07-25 22:12:43 -07001881 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
Keith Packardf0575e92011-07-25 22:12:43 -07001893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001899 if (adpa_pipe_enabled(dev_priv, pipe, val))
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
Keith Packard1519b992011-08-06 10:35:34 -07001905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
Chris Wilson127bd2a2010-07-23 23:32:05 +01001916int
Chris Wilson48b956c2010-09-14 12:50:34 +01001917intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001918 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001919 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001920{
Chris Wilsonce453d82011-02-21 14:43:56 +00001921 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001922 u32 alignment;
1923 int ret;
1924
Chris Wilson05394f32010-11-08 19:18:58 +00001925 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001926 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001929 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
Chris Wilsonce453d82011-02-21 14:43:56 +00001946 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001948 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001949 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
Chris Wilson06d98132012-04-17 15:31:24 +01001956 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001957 if (ret)
1958 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001959
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001960 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001961
Chris Wilsonce453d82011-02-21 14:43:56 +00001962 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001963 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001967err_interruptible:
1968 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001969 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001970}
1971
Chris Wilson1690e1e2011-12-14 13:57:08 +01001972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
Daniel Vetterc2c75132012-07-05 12:17:30 +02001978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
Jesse Barnes17638cd2011-06-24 12:19:23 -07001994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002001 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002002 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002003 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002004 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002005 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002018
Chris Wilson5eddb702010-09-11 13:48:45 +01002019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
Jesse Barnes81255562010-08-02 12:07:50 -07002039 return -EINVAL;
2040 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002041 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002042 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
Chris Wilson5eddb702010-09-11 13:48:45 +01002048 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002049
Daniel Vettere506a0c2012-07-05 12:17:29 +02002050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002051
Daniel Vetterc2c75132012-07-05 12:17:30 +02002052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002059 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002060 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002065 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002069 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002070 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02002071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002072 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002073
Jesse Barnes17638cd2011-06-24 12:19:23 -07002074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002086 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002093 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
Daniel Vettere506a0c2012-07-05 12:17:29 +02002141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002147
Daniel Vettere506a0c2012-07-05 12:17:29 +02002148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002154 I915_WRITE(DSPLINOFF(plane), linear_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002167
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002170 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002171
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002172 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002173}
2174
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002175static int
Chris Wilson14667a42012-04-03 17:58:35 +01002176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
2202static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002205{
2206 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002207 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002210 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002211
2212 /* no fb bound */
2213 if (!crtc->fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002214 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002215 return 0;
2216 }
2217
Eugeni Dodonov5826eca2012-05-09 15:37:12 -03002218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002222 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002223 }
2224
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002225 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002228 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002231 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002232 return ret;
2233 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002234
Chris Wilson14667a42012-04-03 17:58:35 +01002235 if (old_fb)
2236 intel_finish_fb(old_fb);
Chris Wilson265db952010-09-20 15:41:01 +01002237
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002239 if (ret) {
Chris Wilson1690e1e2011-12-14 13:57:08 +01002240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002241 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002242 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002243 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002244 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002245
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002249 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002250
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002251 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002252 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002253
2254 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002255 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002259 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002260
Chris Wilson265db952010-09-20 15:41:01 +01002261 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002267 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002268
2269 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002270}
2271
Chris Wilson5eddb702010-09-11 13:48:45 +01002272static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002273{
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
Zhao Yakui28c97732009-10-09 11:39:41 +08002278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
Chris Wilson5eddb702010-09-11 13:48:45 +01002305 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002306 udelay(500);
2307}
2308
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002309static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310{
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002320 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002326 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002348}
2349
Jesse Barnes291427f2011-07-29 12:42:37 -07002350static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360}
2361
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002362/* The FDI link training functions for ILK/Ibexpeak. */
2363static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002369 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002370 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002371
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
Adam Jacksone1a44742010-06-25 15:32:14 -04002376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002384 udelay(150);
2385
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002386 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002394
Chris Wilson5eddb702010-09-11 13:48:45 +01002395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002402 udelay(150);
2403
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002404 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002410
Chris Wilson5eddb702010-09-11 13:48:45 +01002411 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002412 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002413 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002419 break;
2420 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002421 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002422 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002423 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002424
2425 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002430 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002431
Chris Wilson5eddb702010-09-11 13:48:45 +01002432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002439 udelay(150);
2440
Chris Wilson5eddb702010-09-11 13:48:45 +01002441 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002442 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002443 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002451 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002452 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002453 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002454
2455 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002456
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002457}
2458
Akshay Joshi0206e352011-08-16 15:34:10 -04002459static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002473 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002474
Adam Jacksone1a44742010-06-25 15:32:14 -04002475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002484 udelay(150);
2485
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002486 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002497
Chris Wilson5eddb702010-09-11 13:48:45 +01002498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002510 udelay(150);
2511
Jesse Barnes291427f2011-07-29 12:42:37 -07002512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
Akshay Joshi0206e352011-08-16 15:34:10 -04002515 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002523 udelay(500);
2524
Sean Paulfa37d392012-03-02 12:53:39 -05002525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002535 }
Sean Paulfa37d392012-03-02 12:53:39 -05002536 if (retry < 5)
2537 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002538 }
2539 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002540 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002541
2542 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002552 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002553
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002566 udelay(150);
2567
Akshay Joshi0206e352011-08-16 15:34:10 -04002568 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002576 udelay(500);
2577
Sean Paulfa37d392012-03-02 12:53:39 -05002578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002588 }
Sean Paulfa37d392012-03-02 12:53:39 -05002589 if (retry < 5)
2590 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002591 }
2592 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002593 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
Jesse Barnes357555c2011-04-28 15:09:55 -07002598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002627 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002635 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
Jesse Barnes291427f2011-07-29 12:42:37 -07002641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
Akshay Joshi0206e352011-08-16 15:34:10 -04002644 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
Akshay Joshi0206e352011-08-16 15:34:10 -04002686 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
Daniel Vetter88cefb62012-08-12 19:27:14 +02002712static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002713{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002714 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002715 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002716 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002717 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002718
Jesse Barnesc64e3112010-09-10 11:27:03 -07002719 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002722
Jesse Barnes0e23b992010-09-10 11:10:00 -07002723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002739 udelay(200);
2740
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002749
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002750 POSTING_READ(reg);
2751 udelay(100);
2752 }
Jesse Barnes0e23b992010-09-10 11:10:00 -07002753 }
2754}
2755
Daniel Vetter88cefb62012-08-12 19:27:14 +02002756static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757{
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783}
2784
Jesse Barnes291427f2011-07-29 12:42:37 -07002785static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786{
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795}
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002796static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797{
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
Jesse Barnes291427f2011-07-29 12:42:37 -07002825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002827 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002854static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855{
Chris Wilson0f911282012-04-17 10:05:38 +01002856 struct drm_device *dev = crtc->dev;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002857
2858 if (crtc->fb == NULL)
2859 return;
2860
Chris Wilson0f911282012-04-17 10:05:38 +01002861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002864}
2865
Jesse Barnes040484a2011-01-03 12:14:26 -08002866static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867{
2868 struct drm_device *dev = crtc->dev;
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002869 struct intel_encoder *intel_encoder;
Jesse Barnes040484a2011-01-03 12:14:26 -08002870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002876
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002888 intel_encoder->type);
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002889 return false;
2890 }
2891 }
2892
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002893 switch (intel_encoder->type) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002894 case INTEL_OUTPUT_EDP:
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnes040484a2011-01-03 12:14:26 -08002896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902}
2903
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993}
2994
Jesse Barnesf67a5592011-01-05 10:31:48 -08002995/*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003004{
3005 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003009 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003010
Chris Wilsone7e164d2012-05-11 09:21:25 +01003011 assert_transcoder_disabled(dev_priv, pipe);
3012
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003013 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003014 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003015
Chris Wilson6f13b7b2012-05-13 09:54:09 +01003016 intel_enable_pch_pll(intel_crtc);
3017
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003022 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003023
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003024 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
Jesse Barnesd64311a2011-10-12 15:01:33 -07003039 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003044 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003045 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003046
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01003049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3052
3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003057
Eugeni Dodonovf57e1e32012-05-09 15:37:14 -03003058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003060
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003073 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003082 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003083 break;
3084 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003085 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003086 break;
3087 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003088 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003092 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003093 break;
3094 }
3095
Chris Wilson5eddb702010-09-11 13:48:45 +01003096 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003097 }
3098
Jesse Barnes040484a2011-01-03 12:14:26 -08003099 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003100}
3101
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003102static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103{
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116}
3117
3118static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119{
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003177
Chris Wilsone04c7352012-05-02 20:43:56 +01003178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
Chris Wilsone04c7352012-05-02 20:43:56 +01003182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003185 pll->on = false;
3186 return pll;
3187}
3188
Jesse Barnesd4270e52011-10-11 10:43:02 -07003189void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205}
3206
Jesse Barnesf67a5592011-01-05 10:31:48 -08003207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003212 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003218 /* XXX: For compatability with the crtc helper code, call the encoder's
3219 * enable function unconditionally for now. */
Jesse Barnesf67a5592011-01-05 10:31:48 -08003220 if (intel_crtc->active)
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003221 goto encoders;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003222
3223 intel_crtc->active = true;
3224 intel_update_watermarks(dev);
3225
3226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227 temp = I915_READ(PCH_LVDS);
3228 if ((temp & LVDS_PORT_EN) == 0)
3229 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230 }
3231
3232 is_pch_port = intel_crtc_driving_pch(crtc);
3233
3234 if (is_pch_port)
Daniel Vetter88cefb62012-08-12 19:27:14 +02003235 ironlake_fdi_pll_enable(intel_crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003236 else
3237 ironlake_fdi_disable(crtc);
3238
3239 /* Enable panel fitting for LVDS */
3240 if (dev_priv->pch_pf_size &&
3241 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3242 /* Force use of hard-coded filter coefficients
3243 * as some pre-programmed values are broken,
3244 * e.g. x201.
3245 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003246 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3247 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3248 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003249 }
3250
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003251 /*
3252 * On ILK+ LUT must be loaded before the pipe is running but with
3253 * clocks enabled
3254 */
3255 intel_crtc_load_lut(crtc);
3256
Jesse Barnesf67a5592011-01-05 10:31:48 -08003257 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258 intel_enable_plane(dev_priv, plane, pipe);
3259
3260 if (is_pch_port)
3261 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003262
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003263 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003264 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003265 mutex_unlock(&dev->struct_mutex);
3266
Chris Wilson6b383a72010-09-13 13:54:26 +01003267 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003268
3269encoders:
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003272
3273 if (HAS_PCH_CPT(dev))
3274 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003275}
3276
3277static void ironlake_crtc_disable(struct drm_crtc *crtc)
3278{
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003282 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003283 int pipe = intel_crtc->pipe;
3284 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003285 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003286
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003287 /* XXX: For compatability with the crtc helper code, call the encoder's
3288 * disable function unconditionally for now. */
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 encoder->disable(encoder);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003291
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003292 if (!intel_crtc->active)
3293 return;
3294
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003295 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003296 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003297 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003298
Jesse Barnesb24e7172011-01-04 15:09:30 -08003299 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003300
Chris Wilson973d04f2011-07-08 12:22:37 +01003301 if (dev_priv->cfb_plane == plane)
3302 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003303
Jesse Barnesb24e7172011-01-04 15:09:30 -08003304 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003305
Jesse Barnes6be4a602010-09-10 10:26:01 -07003306 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003307 I915_WRITE(PF_CTL(pipe), 0);
3308 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003309
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003310 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003311
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003312 /* This is a horrible layering violation; we should be doing this in
3313 * the connector/encoder ->prepare instead, but we don't always have
3314 * enough information there about the config to know whether it will
3315 * actually be necessary or just cause undesired flicker.
3316 */
3317 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003318
Jesse Barnes040484a2011-01-03 12:14:26 -08003319 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003320
Jesse Barnes6be4a602010-09-10 10:26:01 -07003321 if (HAS_PCH_CPT(dev)) {
3322 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003323 reg = TRANS_DP_CTL(pipe);
3324 temp = I915_READ(reg);
3325 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003326 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003327 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003328
3329 /* disable DPLL_SEL */
3330 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003331 switch (pipe) {
3332 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003333 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003334 break;
3335 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003336 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003337 break;
3338 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003339 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003340 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003341 break;
3342 default:
3343 BUG(); /* wtf */
3344 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003345 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003346 }
3347
3348 /* disable PCH DPLL */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003349 intel_disable_pch_pll(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003350
Daniel Vetter88cefb62012-08-12 19:27:14 +02003351 ironlake_fdi_pll_disable(intel_crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +01003352
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003353 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003354 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003355
3356 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003357 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003358 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003359}
3360
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003361static void ironlake_crtc_off(struct drm_crtc *crtc)
3362{
3363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364 intel_put_pch_pll(intel_crtc);
3365}
3366
Daniel Vetter02e792f2009-09-15 22:57:34 +02003367static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3368{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003369 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003370 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003371 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003372
Chris Wilson23f09ce2010-08-12 13:53:37 +01003373 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003374 dev_priv->mm.interruptible = false;
3375 (void) intel_overlay_switch_off(intel_crtc->overlay);
3376 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003377 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003378 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003379
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003380 /* Let userspace switch the overlay on again. In most cases userspace
3381 * has to recompute where to put it anyway.
3382 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003383}
3384
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003385static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003386{
3387 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003390 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003391 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003392 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003393
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003394 /* XXX: For compatability with the crtc helper code, call the encoder's
3395 * enable function unconditionally for now. */
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003396 if (intel_crtc->active)
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003397 goto encoders;
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003398
3399 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003400 intel_update_watermarks(dev);
3401
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003402 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003403 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003404 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003405
3406 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003407 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003408
3409 /* Give the overlay scaler a chance to enable if it's on this pipe */
3410 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003411 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003412
3413encoders:
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003414 for_each_encoder_on_crtc(dev, crtc, encoder)
3415 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003416}
3417
3418static void i9xx_crtc_disable(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003423 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003426
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003427 /* XXX: For compatability with the crtc helper code, call the encoder's
3428 * disable function unconditionally for now. */
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003429 for_each_encoder_on_crtc(dev, crtc, encoder)
3430 encoder->disable(encoder);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003431
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003432 if (!intel_crtc->active)
3433 return;
3434
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003435 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003436 intel_crtc_wait_for_pending_flips(crtc);
3437 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003438 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003439 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003440
Chris Wilson973d04f2011-07-08 12:22:37 +01003441 if (dev_priv->cfb_plane == plane)
3442 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003443
Jesse Barnesb24e7172011-01-04 15:09:30 -08003444 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003445 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003446 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003447
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003448 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003449 intel_update_fbc(dev);
3450 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003451}
3452
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003453static void i9xx_crtc_off(struct drm_crtc *crtc)
3454{
3455}
3456
Zhenyu Wang2c072452009-06-05 15:38:42 +08003457/**
3458 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08003459 */
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003460void intel_crtc_update_dpms(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003461{
3462 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07003463 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003464 struct drm_i915_master_private *master_priv;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003466 struct intel_encoder *intel_encoder;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003467 int pipe = intel_crtc->pipe;
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003468 bool enabled, enable = false;
3469 int mode;
3470
3471 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3472 enable |= intel_encoder->connectors_active;
3473
3474 mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003475
Chris Wilson032d2a02010-09-06 16:17:22 +01003476 if (intel_crtc->dpms_mode == mode)
3477 return;
3478
Chris Wilsondebcadd2010-08-07 11:01:33 +01003479 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01003480
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003481 if (enable)
Daniel Vetter76e5a892012-06-29 22:39:33 +02003482 dev_priv->display.crtc_enable(crtc);
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003483 else
Daniel Vetter76e5a892012-06-29 22:39:33 +02003484 dev_priv->display.crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003485
3486 if (!dev->primary->master)
3487 return;
3488
3489 master_priv = dev->primary->master->driver_priv;
3490 if (!master_priv->sarea_priv)
3491 return;
3492
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003493 enabled = crtc->enabled && enable;
Jesse Barnes79e53942008-11-07 14:24:08 -08003494
3495 switch (pipe) {
3496 case 0:
3497 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3499 break;
3500 case 1:
3501 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3503 break;
3504 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003505 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003506 break;
3507 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003508}
3509
Chris Wilsoncdd59982010-09-08 16:30:16 +01003510static void intel_crtc_disable(struct drm_crtc *crtc)
3511{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003512 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003513 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003514
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003515 /* crtc->disable is only called when we have no encoders, hence this
3516 * will disable the pipe. */
3517 intel_crtc_update_dpms(crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003518 dev_priv->display.off(crtc);
3519
Chris Wilson931872f2012-01-16 23:01:13 +00003520 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003522
3523 if (crtc->fb) {
3524 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003525 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003526 mutex_unlock(&dev->struct_mutex);
3527 }
3528}
3529
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003530void intel_encoder_disable(struct drm_encoder *encoder)
3531{
3532 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3533
3534 intel_encoder->disable(intel_encoder);
3535}
3536
Chris Wilsonea5b2132010-08-04 13:50:23 +01003537void intel_encoder_destroy(struct drm_encoder *encoder)
3538{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003540
Chris Wilsonea5b2132010-08-04 13:50:23 +01003541 drm_encoder_cleanup(encoder);
3542 kfree(intel_encoder);
3543}
3544
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003545/* Simple dpms helper for encodres with just one connector, no cloning and only
3546 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547 * state of the entire output pipe. */
3548void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3549{
3550 if (mode == DRM_MODE_DPMS_ON) {
3551 encoder->connectors_active = true;
3552
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003553 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003554 } else {
3555 encoder->connectors_active = false;
3556
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003557 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003558 }
3559}
3560
3561/* Even simpler default implementation, if there's really no special case to
3562 * consider. */
3563void intel_connector_dpms(struct drm_connector *connector, int mode)
3564{
3565 struct intel_encoder *encoder = intel_attached_encoder(connector);
3566
3567 /* All the simple cases only support two dpms states. */
3568 if (mode != DRM_MODE_DPMS_ON)
3569 mode = DRM_MODE_DPMS_OFF;
3570
3571 if (mode == connector->dpms)
3572 return;
3573
3574 connector->dpms = mode;
3575
3576 /* Only need to change hw state when actually enabled */
3577 if (encoder->base.crtc)
3578 intel_encoder_dpms(encoder, mode);
3579 else
3580 encoder->connectors_active = false;
3581}
3582
Jesse Barnes79e53942008-11-07 14:24:08 -08003583static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
Daniel Vetter35313cd2012-07-20 10:30:45 +02003584 const struct drm_display_mode *mode,
Jesse Barnes79e53942008-11-07 14:24:08 -08003585 struct drm_display_mode *adjusted_mode)
3586{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003587 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003588
Eric Anholtbad720f2009-10-22 16:11:14 -07003589 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003590 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003591 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3592 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003593 }
Chris Wilson89749352010-09-12 18:25:19 +01003594
Daniel Vetterf9bef082012-04-15 19:53:19 +02003595 /* All interlaced capable intel hw wants timings in frames. Note though
3596 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3597 * timings, so we need to be careful not to clobber these.*/
3598 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3599 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01003600
Jesse Barnes79e53942008-11-07 14:24:08 -08003601 return true;
3602}
3603
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003604static int valleyview_get_display_clock_speed(struct drm_device *dev)
3605{
3606 return 400000; /* FIXME */
3607}
3608
Jesse Barnese70236a2009-09-21 10:42:27 -07003609static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003610{
Jesse Barnese70236a2009-09-21 10:42:27 -07003611 return 400000;
3612}
Jesse Barnes79e53942008-11-07 14:24:08 -08003613
Jesse Barnese70236a2009-09-21 10:42:27 -07003614static int i915_get_display_clock_speed(struct drm_device *dev)
3615{
3616 return 333000;
3617}
Jesse Barnes79e53942008-11-07 14:24:08 -08003618
Jesse Barnese70236a2009-09-21 10:42:27 -07003619static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3620{
3621 return 200000;
3622}
Jesse Barnes79e53942008-11-07 14:24:08 -08003623
Jesse Barnese70236a2009-09-21 10:42:27 -07003624static int i915gm_get_display_clock_speed(struct drm_device *dev)
3625{
3626 u16 gcfgc = 0;
3627
3628 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3629
3630 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003631 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003632 else {
3633 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3634 case GC_DISPLAY_CLOCK_333_MHZ:
3635 return 333000;
3636 default:
3637 case GC_DISPLAY_CLOCK_190_200_MHZ:
3638 return 190000;
3639 }
3640 }
3641}
Jesse Barnes79e53942008-11-07 14:24:08 -08003642
Jesse Barnese70236a2009-09-21 10:42:27 -07003643static int i865_get_display_clock_speed(struct drm_device *dev)
3644{
3645 return 266000;
3646}
3647
3648static int i855_get_display_clock_speed(struct drm_device *dev)
3649{
3650 u16 hpllcc = 0;
3651 /* Assume that the hardware is in the high speed state. This
3652 * should be the default.
3653 */
3654 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3655 case GC_CLOCK_133_200:
3656 case GC_CLOCK_100_200:
3657 return 200000;
3658 case GC_CLOCK_166_250:
3659 return 250000;
3660 case GC_CLOCK_100_133:
3661 return 133000;
3662 }
3663
3664 /* Shouldn't happen */
3665 return 0;
3666}
3667
3668static int i830_get_display_clock_speed(struct drm_device *dev)
3669{
3670 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003671}
3672
Zhenyu Wang2c072452009-06-05 15:38:42 +08003673struct fdi_m_n {
3674 u32 tu;
3675 u32 gmch_m;
3676 u32 gmch_n;
3677 u32 link_m;
3678 u32 link_n;
3679};
3680
3681static void
3682fdi_reduce_ratio(u32 *num, u32 *den)
3683{
3684 while (*num > 0xffffff || *den > 0xffffff) {
3685 *num >>= 1;
3686 *den >>= 1;
3687 }
3688}
3689
Zhenyu Wang2c072452009-06-05 15:38:42 +08003690static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003691ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3692 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003693{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003694 m_n->tu = 64; /* default size */
3695
Chris Wilson22ed1112010-12-04 01:01:29 +00003696 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3697 m_n->gmch_m = bits_per_pixel * pixel_clock;
3698 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003699 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3700
Chris Wilson22ed1112010-12-04 01:01:29 +00003701 m_n->link_m = pixel_clock;
3702 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003703 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3704}
3705
Chris Wilsona7615032011-01-12 17:04:08 +00003706static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3707{
Keith Packard72bbe582011-09-26 16:09:45 -07003708 if (i915_panel_use_ssc >= 0)
3709 return i915_panel_use_ssc != 0;
3710 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07003711 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00003712}
3713
Jesse Barnes5a354202011-06-24 12:19:22 -07003714/**
3715 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3716 * @crtc: CRTC structure
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003717 * @mode: requested mode
Jesse Barnes5a354202011-06-24 12:19:22 -07003718 *
3719 * A pipe may be connected to one or more outputs. Based on the depth of the
3720 * attached framebuffer, choose a good color depth to use on the pipe.
3721 *
3722 * If possible, match the pipe depth to the fb depth. In some cases, this
3723 * isn't ideal, because the connected output supports a lesser or restricted
3724 * set of depths. Resolve that here:
3725 * LVDS typically supports only 6bpc, so clamp down in that case
3726 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3727 * Displays may support a restricted set as well, check EDID and clamp as
3728 * appropriate.
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003729 * DP may want to dither down to 6bpc to fit larger modes
Jesse Barnes5a354202011-06-24 12:19:22 -07003730 *
3731 * RETURNS:
3732 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3733 * true if they don't match).
3734 */
3735static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003736 unsigned int *pipe_bpp,
3737 struct drm_display_mode *mode)
Jesse Barnes5a354202011-06-24 12:19:22 -07003738{
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes5a354202011-06-24 12:19:22 -07003741 struct drm_connector *connector;
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003742 struct intel_encoder *intel_encoder;
Jesse Barnes5a354202011-06-24 12:19:22 -07003743 unsigned int display_bpc = UINT_MAX, bpc;
3744
3745 /* Walk the encoders & connectors on this crtc, get min bpc */
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes5a354202011-06-24 12:19:22 -07003747
3748 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3749 unsigned int lvds_bpc;
3750
3751 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3752 LVDS_A3_POWER_UP)
3753 lvds_bpc = 8;
3754 else
3755 lvds_bpc = 6;
3756
3757 if (lvds_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003758 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003759 display_bpc = lvds_bpc;
3760 }
3761 continue;
3762 }
3763
Jesse Barnes5a354202011-06-24 12:19:22 -07003764 /* Not one of the known troublemakers, check the EDID */
3765 list_for_each_entry(connector, &dev->mode_config.connector_list,
3766 head) {
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02003767 if (connector->encoder != &intel_encoder->base)
Jesse Barnes5a354202011-06-24 12:19:22 -07003768 continue;
3769
Jesse Barnes62ac41a2011-07-28 12:55:14 -07003770 /* Don't use an invalid EDID bpc value */
3771 if (connector->display_info.bpc &&
3772 connector->display_info.bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003773 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003774 display_bpc = connector->display_info.bpc;
3775 }
3776 }
3777
3778 /*
3779 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3780 * through, clamp it down. (Note: >12bpc will be caught below.)
3781 */
3782 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3783 if (display_bpc > 8 && display_bpc < 12) {
Adam Jackson82820492011-10-10 16:33:34 -04003784 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003785 display_bpc = 12;
3786 } else {
Adam Jackson82820492011-10-10 16:33:34 -04003787 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003788 display_bpc = 8;
3789 }
3790 }
3791 }
3792
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003793 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3794 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3795 display_bpc = 6;
3796 }
3797
Jesse Barnes5a354202011-06-24 12:19:22 -07003798 /*
3799 * We could just drive the pipe at the highest bpc all the time and
3800 * enable dithering as needed, but that costs bandwidth. So choose
3801 * the minimum value that expresses the full color range of the fb but
3802 * also stays within the max display bpc discovered above.
3803 */
3804
3805 switch (crtc->fb->depth) {
3806 case 8:
3807 bpc = 8; /* since we go through a colormap */
3808 break;
3809 case 15:
3810 case 16:
3811 bpc = 6; /* min is 18bpp */
3812 break;
3813 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07003814 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07003815 break;
3816 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07003817 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07003818 break;
3819 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07003820 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07003821 break;
3822 default:
3823 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3824 bpc = min((unsigned int)8, display_bpc);
3825 break;
3826 }
3827
Keith Packard578393c2011-09-05 11:53:21 -07003828 display_bpc = min(display_bpc, bpc);
3829
Adam Jackson82820492011-10-10 16:33:34 -04003830 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3831 bpc, display_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003832
Keith Packard578393c2011-09-05 11:53:21 -07003833 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07003834
3835 return display_bpc != bpc;
3836}
3837
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003838static int vlv_get_refclk(struct drm_crtc *crtc)
3839{
3840 struct drm_device *dev = crtc->dev;
3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 int refclk = 27000; /* for DP & HDMI */
3843
3844 return 100000; /* only one validated so far */
3845
3846 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3847 refclk = 96000;
3848 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3849 if (intel_panel_use_ssc(dev_priv))
3850 refclk = 100000;
3851 else
3852 refclk = 96000;
3853 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3854 refclk = 100000;
3855 }
3856
3857 return refclk;
3858}
3859
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003860static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3861{
3862 struct drm_device *dev = crtc->dev;
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 int refclk;
3865
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003866 if (IS_VALLEYVIEW(dev)) {
3867 refclk = vlv_get_refclk(crtc);
3868 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003869 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3870 refclk = dev_priv->lvds_ssc_freq * 1000;
3871 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3872 refclk / 1000);
3873 } else if (!IS_GEN2(dev)) {
3874 refclk = 96000;
3875 } else {
3876 refclk = 48000;
3877 }
3878
3879 return refclk;
3880}
3881
3882static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3883 intel_clock_t *clock)
3884{
3885 /* SDVO TV has fixed PLL values depend on its clock range,
3886 this mirrors vbios setting. */
3887 if (adjusted_mode->clock >= 100000
3888 && adjusted_mode->clock < 140500) {
3889 clock->p1 = 2;
3890 clock->p2 = 10;
3891 clock->n = 3;
3892 clock->m1 = 16;
3893 clock->m2 = 8;
3894 } else if (adjusted_mode->clock >= 140500
3895 && adjusted_mode->clock <= 200000) {
3896 clock->p1 = 1;
3897 clock->p2 = 10;
3898 clock->n = 6;
3899 clock->m1 = 12;
3900 clock->m2 = 8;
3901 }
3902}
3903
Jesse Barnesa7516a02011-12-15 12:30:37 -08003904static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3905 intel_clock_t *clock,
3906 intel_clock_t *reduced_clock)
3907{
3908 struct drm_device *dev = crtc->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3911 int pipe = intel_crtc->pipe;
3912 u32 fp, fp2 = 0;
3913
3914 if (IS_PINEVIEW(dev)) {
3915 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3916 if (reduced_clock)
3917 fp2 = (1 << reduced_clock->n) << 16 |
3918 reduced_clock->m1 << 8 | reduced_clock->m2;
3919 } else {
3920 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3921 if (reduced_clock)
3922 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3923 reduced_clock->m2;
3924 }
3925
3926 I915_WRITE(FP0(pipe), fp);
3927
3928 intel_crtc->lowfreq_avail = false;
3929 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3930 reduced_clock && i915_powersave) {
3931 I915_WRITE(FP1(pipe), fp2);
3932 intel_crtc->lowfreq_avail = true;
3933 } else {
3934 I915_WRITE(FP1(pipe), fp);
3935 }
3936}
3937
Daniel Vetter93e537a2012-03-28 23:11:26 +02003938static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3939 struct drm_display_mode *adjusted_mode)
3940{
3941 struct drm_device *dev = crtc->dev;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944 int pipe = intel_crtc->pipe;
Chris Wilson284d5df2012-04-14 17:41:59 +01003945 u32 temp;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003946
3947 temp = I915_READ(LVDS);
3948 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3949 if (pipe == 1) {
3950 temp |= LVDS_PIPEB_SELECT;
3951 } else {
3952 temp &= ~LVDS_PIPEB_SELECT;
3953 }
3954 /* set the corresponsding LVDS_BORDER bit */
3955 temp |= dev_priv->lvds_border_bits;
3956 /* Set the B0-B3 data pairs corresponding to whether we're going to
3957 * set the DPLLs for dual-channel mode or not.
3958 */
3959 if (clock->p2 == 7)
3960 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3961 else
3962 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3963
3964 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3965 * appropriately here, but we need to look more thoroughly into how
3966 * panels behave in the two modes.
3967 */
3968 /* set the dithering flag on LVDS as needed */
3969 if (INTEL_INFO(dev)->gen >= 4) {
3970 if (dev_priv->lvds_dither)
3971 temp |= LVDS_ENABLE_DITHER;
3972 else
3973 temp &= ~LVDS_ENABLE_DITHER;
3974 }
Chris Wilson284d5df2012-04-14 17:41:59 +01003975 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Daniel Vetter93e537a2012-03-28 23:11:26 +02003976 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01003977 temp |= LVDS_HSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003978 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01003979 temp |= LVDS_VSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003980 I915_WRITE(LVDS, temp);
3981}
3982
Jesse Barnesa0c4da242012-06-15 11:55:13 -07003983static void vlv_update_pll(struct drm_crtc *crtc,
3984 struct drm_display_mode *mode,
3985 struct drm_display_mode *adjusted_mode,
3986 intel_clock_t *clock, intel_clock_t *reduced_clock,
3987 int refclk, int num_connectors)
3988{
3989 struct drm_device *dev = crtc->dev;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
3991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992 int pipe = intel_crtc->pipe;
3993 u32 dpll, mdiv, pdiv;
3994 u32 bestn, bestm1, bestm2, bestp1, bestp2;
3995 bool is_hdmi;
3996
3997 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3998
3999 bestn = clock->n;
4000 bestm1 = clock->m1;
4001 bestm2 = clock->m2;
4002 bestp1 = clock->p1;
4003 bestp2 = clock->p2;
4004
4005 /* Enable DPIO clock input */
4006 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4007 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4008 I915_WRITE(DPLL(pipe), dpll);
4009 POSTING_READ(DPLL(pipe));
4010
4011 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4012 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4013 mdiv |= ((bestn << DPIO_N_SHIFT));
4014 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4015 mdiv |= (1 << DPIO_K_SHIFT);
4016 mdiv |= DPIO_ENABLE_CALIBRATION;
4017 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4018
4019 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4020
4021 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4022 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4023 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4024 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4025
4026 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4027
4028 dpll |= DPLL_VCO_ENABLE;
4029 I915_WRITE(DPLL(pipe), dpll);
4030 POSTING_READ(DPLL(pipe));
4031 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4032 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4033
4034 if (is_hdmi) {
4035 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4036
4037 if (temp > 1)
4038 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4039 else
4040 temp = 0;
4041
4042 I915_WRITE(DPLL_MD(pipe), temp);
4043 POSTING_READ(DPLL_MD(pipe));
4044 }
4045
4046 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4047}
4048
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004049static void i9xx_update_pll(struct drm_crtc *crtc,
4050 struct drm_display_mode *mode,
4051 struct drm_display_mode *adjusted_mode,
4052 intel_clock_t *clock, intel_clock_t *reduced_clock,
4053 int num_connectors)
4054{
4055 struct drm_device *dev = crtc->dev;
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058 int pipe = intel_crtc->pipe;
4059 u32 dpll;
4060 bool is_sdvo;
4061
4062 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4063 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4064
4065 dpll = DPLL_VGA_MODE_DIS;
4066
4067 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4068 dpll |= DPLLB_MODE_LVDS;
4069 else
4070 dpll |= DPLLB_MODE_DAC_SERIAL;
4071 if (is_sdvo) {
4072 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4073 if (pixel_multiplier > 1) {
4074 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4075 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4076 }
4077 dpll |= DPLL_DVO_HIGH_SPEED;
4078 }
4079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4080 dpll |= DPLL_DVO_HIGH_SPEED;
4081
4082 /* compute bitmask from p1 value */
4083 if (IS_PINEVIEW(dev))
4084 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4085 else {
4086 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4087 if (IS_G4X(dev) && reduced_clock)
4088 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4089 }
4090 switch (clock->p2) {
4091 case 5:
4092 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4093 break;
4094 case 7:
4095 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4096 break;
4097 case 10:
4098 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4099 break;
4100 case 14:
4101 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4102 break;
4103 }
4104 if (INTEL_INFO(dev)->gen >= 4)
4105 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4106
4107 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4108 dpll |= PLL_REF_INPUT_TVCLKINBC;
4109 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4110 /* XXX: just matching BIOS for now */
4111 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4112 dpll |= 3;
4113 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4114 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4115 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4116 else
4117 dpll |= PLL_REF_INPUT_DREFCLK;
4118
4119 dpll |= DPLL_VCO_ENABLE;
4120 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4121 POSTING_READ(DPLL(pipe));
4122 udelay(150);
4123
4124 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4125 * This is an exception to the general rule that mode_set doesn't turn
4126 * things on.
4127 */
4128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4129 intel_update_lvds(crtc, clock, adjusted_mode);
4130
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4132 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4133
4134 I915_WRITE(DPLL(pipe), dpll);
4135
4136 /* Wait for the clocks to stabilize. */
4137 POSTING_READ(DPLL(pipe));
4138 udelay(150);
4139
4140 if (INTEL_INFO(dev)->gen >= 4) {
4141 u32 temp = 0;
4142 if (is_sdvo) {
4143 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4144 if (temp > 1)
4145 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4146 else
4147 temp = 0;
4148 }
4149 I915_WRITE(DPLL_MD(pipe), temp);
4150 } else {
4151 /* The pixel multiplier can only be updated once the
4152 * DPLL is enabled and the clocks are stable.
4153 *
4154 * So write it again.
4155 */
4156 I915_WRITE(DPLL(pipe), dpll);
4157 }
4158}
4159
4160static void i8xx_update_pll(struct drm_crtc *crtc,
4161 struct drm_display_mode *adjusted_mode,
4162 intel_clock_t *clock,
4163 int num_connectors)
4164{
4165 struct drm_device *dev = crtc->dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4168 int pipe = intel_crtc->pipe;
4169 u32 dpll;
4170
4171 dpll = DPLL_VGA_MODE_DIS;
4172
4173 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175 } else {
4176 if (clock->p1 == 2)
4177 dpll |= PLL_P1_DIVIDE_BY_TWO;
4178 else
4179 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4180 if (clock->p2 == 4)
4181 dpll |= PLL_P2_DIVIDE_BY_4;
4182 }
4183
4184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4185 /* XXX: just matching BIOS for now */
4186 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4187 dpll |= 3;
4188 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4189 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4190 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4191 else
4192 dpll |= PLL_REF_INPUT_DREFCLK;
4193
4194 dpll |= DPLL_VCO_ENABLE;
4195 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4196 POSTING_READ(DPLL(pipe));
4197 udelay(150);
4198
4199 I915_WRITE(DPLL(pipe), dpll);
4200
4201 /* Wait for the clocks to stabilize. */
4202 POSTING_READ(DPLL(pipe));
4203 udelay(150);
4204
4205 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4206 * This is an exception to the general rule that mode_set doesn't turn
4207 * things on.
4208 */
4209 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4210 intel_update_lvds(crtc, clock, adjusted_mode);
4211
4212 /* The pixel multiplier can only be updated once the
4213 * DPLL is enabled and the clocks are stable.
4214 *
4215 * So write it again.
4216 */
4217 I915_WRITE(DPLL(pipe), dpll);
4218}
4219
Eric Anholtf564048e2011-03-30 13:01:02 -07004220static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4221 struct drm_display_mode *mode,
4222 struct drm_display_mode *adjusted_mode,
4223 int x, int y,
4224 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004230 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004231 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004232 intel_clock_t clock, reduced_clock;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004233 u32 dspcntr, pipeconf, vsyncshift;
4234 bool ok, has_reduced_clock = false, is_sdvo = false;
4235 bool is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004236 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004237 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004238 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004239
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02004240 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004241 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004242 case INTEL_OUTPUT_LVDS:
4243 is_lvds = true;
4244 break;
4245 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004246 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004247 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004248 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004249 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004250 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004251 case INTEL_OUTPUT_TVOUT:
4252 is_tv = true;
4253 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004254 case INTEL_OUTPUT_DISPLAYPORT:
4255 is_dp = true;
4256 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004257 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004258
Eric Anholtc751ce42010-03-25 11:48:48 -07004259 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004260 }
4261
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004262 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004263
Ma Lingd4906092009-03-18 20:13:27 +08004264 /*
4265 * Returns a set of divisors for the desired target clock with the given
4266 * refclk, or FALSE. The returned values represent the clock equation:
4267 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4268 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004269 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004270 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4271 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004272 if (!ok) {
4273 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004274 return -EINVAL;
4275 }
4276
4277 /* Ensure that the cursor is valid for the new mode before changing... */
4278 intel_crtc_update_cursor(crtc, true);
4279
4280 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004281 /*
4282 * Ensure we match the reduced clock's P to the target clock.
4283 * If the clocks don't match, we can't switch the display clock
4284 * by using the FP0/FP1. In such case we will disable the LVDS
4285 * downclock feature.
4286 */
Eric Anholtf564048e2011-03-30 13:01:02 -07004287 has_reduced_clock = limit->find_pll(limit, crtc,
4288 dev_priv->lvds_downclock,
4289 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004290 &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004291 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004292 }
4293
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004294 if (is_sdvo && is_tv)
4295 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004296
Jesse Barnesa7516a02011-12-15 12:30:37 -08004297 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4298 &reduced_clock : NULL);
Eric Anholtf564048e2011-03-30 13:01:02 -07004299
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004300 if (IS_GEN2(dev))
4301 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
Jesse Barnesa0c4da242012-06-15 11:55:13 -07004302 else if (IS_VALLEYVIEW(dev))
4303 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4304 refclk, num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004305 else
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004306 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4307 has_reduced_clock ? &reduced_clock : NULL,
4308 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004309
4310 /* setup pipeconf */
4311 pipeconf = I915_READ(PIPECONF(pipe));
4312
4313 /* Set up the display plane register */
4314 dspcntr = DISPPLANE_GAMMA_ENABLE;
4315
Eric Anholt929c77f2011-03-30 13:01:04 -07004316 if (pipe == 0)
4317 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4318 else
4319 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004320
4321 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4322 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4323 * core speed.
4324 *
4325 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4326 * pipe == 0 check?
4327 */
4328 if (mode->clock >
4329 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4330 pipeconf |= PIPECONF_DOUBLE_WIDE;
4331 else
4332 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4333 }
4334
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004335 /* default to 8bpc */
4336 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4337 if (is_dp) {
4338 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4339 pipeconf |= PIPECONF_BPP_6 |
4340 PIPECONF_DITHER_EN |
4341 PIPECONF_DITHER_TYPE_SP;
4342 }
4343 }
4344
Eric Anholtf564048e2011-03-30 13:01:02 -07004345 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4346 drm_mode_debug_printmodeline(mode);
4347
Jesse Barnesa7516a02011-12-15 12:30:37 -08004348 if (HAS_PIPE_CXSR(dev)) {
4349 if (intel_crtc->lowfreq_avail) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004350 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4351 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004352 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07004353 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4354 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4355 }
4356 }
4357
Keith Packard617cf882012-02-08 13:53:38 -08004358 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Daniel Vetterdbb02572012-01-28 14:49:23 +01004359 if (!IS_GEN2(dev) &&
4360 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004361 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4362 /* the chip adds 2 halflines automatically */
Eric Anholtf564048e2011-03-30 13:01:02 -07004363 adjusted_mode->crtc_vtotal -= 1;
Eric Anholtf564048e2011-03-30 13:01:02 -07004364 adjusted_mode->crtc_vblank_end -= 1;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004365 vsyncshift = adjusted_mode->crtc_hsync_start
4366 - adjusted_mode->crtc_htotal/2;
4367 } else {
Keith Packard617cf882012-02-08 13:53:38 -08004368 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004369 vsyncshift = 0;
4370 }
4371
4372 if (!IS_GEN3(dev))
4373 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
Eric Anholtf564048e2011-03-30 13:01:02 -07004374
4375 I915_WRITE(HTOTAL(pipe),
4376 (adjusted_mode->crtc_hdisplay - 1) |
4377 ((adjusted_mode->crtc_htotal - 1) << 16));
4378 I915_WRITE(HBLANK(pipe),
4379 (adjusted_mode->crtc_hblank_start - 1) |
4380 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4381 I915_WRITE(HSYNC(pipe),
4382 (adjusted_mode->crtc_hsync_start - 1) |
4383 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4384
4385 I915_WRITE(VTOTAL(pipe),
4386 (adjusted_mode->crtc_vdisplay - 1) |
4387 ((adjusted_mode->crtc_vtotal - 1) << 16));
4388 I915_WRITE(VBLANK(pipe),
4389 (adjusted_mode->crtc_vblank_start - 1) |
4390 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4391 I915_WRITE(VSYNC(pipe),
4392 (adjusted_mode->crtc_vsync_start - 1) |
4393 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4394
4395 /* pipesrc and dspsize control the size that is scaled from,
4396 * which should always be the user's requested size.
4397 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004398 I915_WRITE(DSPSIZE(plane),
4399 ((mode->vdisplay - 1) << 16) |
4400 (mode->hdisplay - 1));
4401 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004402 I915_WRITE(PIPESRC(pipe),
4403 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4404
Eric Anholtf564048e2011-03-30 13:01:02 -07004405 I915_WRITE(PIPECONF(pipe), pipeconf);
4406 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004407 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004408
4409 intel_wait_for_vblank(dev, pipe);
4410
Eric Anholtf564048e2011-03-30 13:01:02 -07004411 I915_WRITE(DSPCNTR(plane), dspcntr);
4412 POSTING_READ(DSPCNTR(plane));
4413
4414 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4415
4416 intel_update_watermarks(dev);
4417
Eric Anholtf564048e2011-03-30 13:01:02 -07004418 return ret;
4419}
4420
Keith Packard9fb526d2011-09-26 22:24:57 -07004421/*
4422 * Initialize reference clocks when the driver loads
4423 */
4424void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004425{
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004428 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004429 u32 temp;
4430 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004431 bool has_cpu_edp = false;
4432 bool has_pch_edp = false;
4433 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004434 bool has_ck505 = false;
4435 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004436
4437 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004438 list_for_each_entry(encoder, &mode_config->encoder_list,
4439 base.head) {
4440 switch (encoder->type) {
4441 case INTEL_OUTPUT_LVDS:
4442 has_panel = true;
4443 has_lvds = true;
4444 break;
4445 case INTEL_OUTPUT_EDP:
4446 has_panel = true;
4447 if (intel_encoder_is_pch_edp(&encoder->base))
4448 has_pch_edp = true;
4449 else
4450 has_cpu_edp = true;
4451 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004452 }
4453 }
4454
Keith Packard99eb6a02011-09-26 14:29:12 -07004455 if (HAS_PCH_IBX(dev)) {
4456 has_ck505 = dev_priv->display_clock_mode;
4457 can_ssc = has_ck505;
4458 } else {
4459 has_ck505 = false;
4460 can_ssc = true;
4461 }
4462
4463 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4464 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4465 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004466
4467 /* Ironlake: try to setup display ref clock before DPLL
4468 * enabling. This is only under driver's control after
4469 * PCH B stepping, previous chipset stepping should be
4470 * ignoring this setting.
4471 */
4472 temp = I915_READ(PCH_DREF_CONTROL);
4473 /* Always enable nonspread source */
4474 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004475
Keith Packard99eb6a02011-09-26 14:29:12 -07004476 if (has_ck505)
4477 temp |= DREF_NONSPREAD_CK505_ENABLE;
4478 else
4479 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004480
Keith Packard199e5d72011-09-22 12:01:57 -07004481 if (has_panel) {
4482 temp &= ~DREF_SSC_SOURCE_MASK;
4483 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004484
Keith Packard199e5d72011-09-22 12:01:57 -07004485 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07004486 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004487 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004488 temp |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02004489 } else
4490 temp &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004491
4492 /* Get SSC going before enabling the outputs */
4493 I915_WRITE(PCH_DREF_CONTROL, temp);
4494 POSTING_READ(PCH_DREF_CONTROL);
4495 udelay(200);
4496
Jesse Barnes13d83a62011-08-03 12:59:20 -07004497 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4498
4499 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07004500 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07004501 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004502 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004503 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004504 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07004505 else
4506 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004507 } else
4508 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4509
4510 I915_WRITE(PCH_DREF_CONTROL, temp);
4511 POSTING_READ(PCH_DREF_CONTROL);
4512 udelay(200);
4513 } else {
4514 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4515
4516 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4517
4518 /* Turn off CPU output */
4519 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4520
4521 I915_WRITE(PCH_DREF_CONTROL, temp);
4522 POSTING_READ(PCH_DREF_CONTROL);
4523 udelay(200);
4524
4525 /* Turn off the SSC source */
4526 temp &= ~DREF_SSC_SOURCE_MASK;
4527 temp |= DREF_SSC_SOURCE_DISABLE;
4528
4529 /* Turn off SSC1 */
4530 temp &= ~ DREF_SSC1_ENABLE;
4531
Jesse Barnes13d83a62011-08-03 12:59:20 -07004532 I915_WRITE(PCH_DREF_CONTROL, temp);
4533 POSTING_READ(PCH_DREF_CONTROL);
4534 udelay(200);
4535 }
4536}
4537
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004538static int ironlake_get_refclk(struct drm_crtc *crtc)
4539{
4540 struct drm_device *dev = crtc->dev;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004543 struct intel_encoder *edp_encoder = NULL;
4544 int num_connectors = 0;
4545 bool is_lvds = false;
4546
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02004547 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004548 switch (encoder->type) {
4549 case INTEL_OUTPUT_LVDS:
4550 is_lvds = true;
4551 break;
4552 case INTEL_OUTPUT_EDP:
4553 edp_encoder = encoder;
4554 break;
4555 }
4556 num_connectors++;
4557 }
4558
4559 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4561 dev_priv->lvds_ssc_freq);
4562 return dev_priv->lvds_ssc_freq * 1000;
4563 }
4564
4565 return 120000;
4566}
4567
Eric Anholtf564048e2011-03-30 13:01:02 -07004568static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4569 struct drm_display_mode *mode,
4570 struct drm_display_mode *adjusted_mode,
4571 int x, int y,
4572 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004573{
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004578 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08004579 int refclk, num_connectors = 0;
4580 intel_clock_t clock, reduced_clock;
4581 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Eric Anholta07d6782011-03-30 13:01:08 -07004582 bool ok, has_reduced_clock = false, is_sdvo = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004583 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnese3aef172012-04-10 11:58:03 -07004584 struct intel_encoder *encoder, *edp_encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004585 const intel_limit_t *limit;
4586 int ret;
4587 struct fdi_m_n m_n = {0};
Eric Anholtfae14982011-03-30 13:01:09 -07004588 u32 temp;
Jesse Barnes5a354202011-06-24 12:19:22 -07004589 int target_clock, pixel_multiplier, lane, link_bw, factor;
4590 unsigned int pipe_bpp;
4591 bool dither;
Jesse Barnese3aef172012-04-10 11:58:03 -07004592 bool is_cpu_edp = false, is_pch_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004593
Daniel Vetter6c2b7c12012-07-05 09:50:24 +02004594 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004595 switch (encoder->type) {
4596 case INTEL_OUTPUT_LVDS:
4597 is_lvds = true;
4598 break;
4599 case INTEL_OUTPUT_SDVO:
4600 case INTEL_OUTPUT_HDMI:
4601 is_sdvo = true;
4602 if (encoder->needs_tv_clock)
4603 is_tv = true;
4604 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004605 case INTEL_OUTPUT_TVOUT:
4606 is_tv = true;
4607 break;
4608 case INTEL_OUTPUT_ANALOG:
4609 is_crt = true;
4610 break;
4611 case INTEL_OUTPUT_DISPLAYPORT:
4612 is_dp = true;
4613 break;
4614 case INTEL_OUTPUT_EDP:
Jesse Barnese3aef172012-04-10 11:58:03 -07004615 is_dp = true;
4616 if (intel_encoder_is_pch_edp(&encoder->base))
4617 is_pch_edp = true;
4618 else
4619 is_cpu_edp = true;
4620 edp_encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004621 break;
4622 }
4623
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004624 num_connectors++;
4625 }
4626
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004627 refclk = ironlake_get_refclk(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004628
4629 /*
4630 * Returns a set of divisors for the desired target clock with the given
4631 * refclk, or FALSE. The returned values represent the clock equation:
4632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4633 */
4634 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004635 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4636 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004637 if (!ok) {
4638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4639 return -EINVAL;
4640 }
4641
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004642 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01004643 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004644
Zhao Yakuiddc90032010-01-06 22:05:56 +08004645 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004646 /*
4647 * Ensure we match the reduced clock's P to the target clock.
4648 * If the clocks don't match, we can't switch the display clock
4649 * by using the FP0/FP1. In such case we will disable the LVDS
4650 * downclock feature.
4651 */
Zhao Yakuiddc90032010-01-06 22:05:56 +08004652 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01004653 dev_priv->lvds_downclock,
4654 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004655 &clock,
Chris Wilson5eddb702010-09-11 13:48:45 +01004656 &reduced_clock);
Jesse Barnes652c3932009-08-17 13:31:43 -07004657 }
Daniel Vetter61e96532012-05-30 14:52:26 +02004658
4659 if (is_sdvo && is_tv)
4660 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4661
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004662
Zhenyu Wang2c072452009-06-05 15:38:42 +08004663 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07004664 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4665 lane = 0;
4666 /* CPU eDP doesn't require FDI link, so just set DP M/N
4667 according to current link config */
Jesse Barnese3aef172012-04-10 11:58:03 -07004668 if (is_cpu_edp) {
Jesse Barnese3aef172012-04-10 11:58:03 -07004669 intel_edp_link_config(edp_encoder, &lane, &link_bw);
Eric Anholt8febb292011-03-30 13:01:07 -07004670 } else {
Eric Anholt8febb292011-03-30 13:01:07 -07004671 /* FDI is a binary signal running at ~2.7GHz, encoding
4672 * each output octet as 10 bits. The actual frequency
4673 * is stored as a divider into a 100MHz clock, and the
4674 * mode pixel clock is stored in units of 1KHz.
4675 * Hence the bw of each lane in terms of the mode signal
4676 * is:
4677 */
4678 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004679 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004680
Daniel Vetter94bf2ce2012-06-04 18:39:19 +02004681 /* [e]DP over FDI requires target mode clock instead of link clock. */
4682 if (edp_encoder)
4683 target_clock = intel_edp_target_clock(edp_encoder, mode);
4684 else if (is_dp)
4685 target_clock = mode->clock;
4686 else
4687 target_clock = adjusted_mode->clock;
4688
Eric Anholt8febb292011-03-30 13:01:07 -07004689 /* determine panel color depth */
4690 temp = I915_READ(PIPECONF(pipe));
4691 temp &= ~PIPE_BPC_MASK;
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004692 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
Jesse Barnes5a354202011-06-24 12:19:22 -07004693 switch (pipe_bpp) {
4694 case 18:
4695 temp |= PIPE_6BPC;
4696 break;
4697 case 24:
Eric Anholt8febb292011-03-30 13:01:07 -07004698 temp |= PIPE_8BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004699 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07004700 case 30:
4701 temp |= PIPE_10BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004702 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07004703 case 36:
4704 temp |= PIPE_12BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004705 break;
4706 default:
Jesse Barnes62ac41a2011-07-28 12:55:14 -07004707 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4708 pipe_bpp);
Jesse Barnes5a354202011-06-24 12:19:22 -07004709 temp |= PIPE_8BPC;
4710 pipe_bpp = 24;
4711 break;
Eric Anholt8febb292011-03-30 13:01:07 -07004712 }
4713
Jesse Barnes5a354202011-06-24 12:19:22 -07004714 intel_crtc->bpp = pipe_bpp;
4715 I915_WRITE(PIPECONF(pipe), temp);
4716
Eric Anholt8febb292011-03-30 13:01:07 -07004717 if (!lane) {
4718 /*
4719 * Account for spread spectrum to avoid
4720 * oversubscribing the link. Max center spread
4721 * is 2.5%; use 5% for safety's sake.
4722 */
Jesse Barnes5a354202011-06-24 12:19:22 -07004723 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
Eric Anholt8febb292011-03-30 13:01:07 -07004724 lane = bps / (link_bw * 8) + 1;
4725 }
4726
4727 intel_crtc->fdi_lanes = lane;
4728
4729 if (pixel_multiplier > 1)
4730 link_bw *= pixel_multiplier;
Jesse Barnes5a354202011-06-24 12:19:22 -07004731 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4732 &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07004733
Eric Anholta07d6782011-03-30 13:01:08 -07004734 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4735 if (has_reduced_clock)
4736 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4737 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08004738
Chris Wilsonc1858122010-12-03 21:35:48 +00004739 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07004740 factor = 21;
4741 if (is_lvds) {
4742 if ((intel_panel_use_ssc(dev_priv) &&
4743 dev_priv->lvds_ssc_freq == 100) ||
4744 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4745 factor = 25;
4746 } else if (is_sdvo && is_tv)
4747 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00004748
Jesse Barnescb0e0932011-07-28 14:50:30 -07004749 if (clock.m < factor * clock.n)
Eric Anholt8febb292011-03-30 13:01:07 -07004750 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00004751
Chris Wilson5eddb702010-09-11 13:48:45 +01004752 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004753
Eric Anholta07d6782011-03-30 13:01:08 -07004754 if (is_lvds)
4755 dpll |= DPLLB_MODE_LVDS;
4756 else
4757 dpll |= DPLLB_MODE_DAC_SERIAL;
4758 if (is_sdvo) {
4759 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4760 if (pixel_multiplier > 1) {
4761 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08004762 }
Eric Anholta07d6782011-03-30 13:01:08 -07004763 dpll |= DPLL_DVO_HIGH_SPEED;
4764 }
Jesse Barnese3aef172012-04-10 11:58:03 -07004765 if (is_dp && !is_cpu_edp)
Eric Anholta07d6782011-03-30 13:01:08 -07004766 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004767
Eric Anholta07d6782011-03-30 13:01:08 -07004768 /* compute bitmask from p1 value */
4769 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4770 /* also FPA1 */
4771 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4772
4773 switch (clock.p2) {
4774 case 5:
4775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4776 break;
4777 case 7:
4778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4779 break;
4780 case 10:
4781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4782 break;
4783 case 14:
4784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4785 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004786 }
4787
4788 if (is_sdvo && is_tv)
4789 dpll |= PLL_REF_INPUT_TVCLKINBC;
4790 else if (is_tv)
4791 /* XXX: just matching BIOS for now */
4792 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4793 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00004794 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Jesse Barnes79e53942008-11-07 14:24:08 -08004795 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4796 else
4797 dpll |= PLL_REF_INPUT_DREFCLK;
4798
4799 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01004800 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004801
4802 /* Set up the display plane register */
4803 dspcntr = DISPPLANE_GAMMA_ENABLE;
4804
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07004805 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08004806 drm_mode_debug_printmodeline(mode);
4807
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03004808 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4809 * pre-Haswell/LPT generation */
4810 if (HAS_PCH_LPT(dev)) {
4811 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4812 pipe);
4813 } else if (!is_cpu_edp) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004814 struct intel_pch_pll *pll;
Chris Wilson5eddb702010-09-11 13:48:45 +01004815
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004816 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4817 if (pll == NULL) {
4818 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4819 pipe);
Jesse Barnes4b645f12011-10-12 09:51:31 -07004820 return -EINVAL;
4821 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004822 } else
4823 intel_put_pch_pll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004824
4825 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4826 * This is an exception to the general rule that mode_set doesn't turn
4827 * things on.
4828 */
4829 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07004830 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01004831 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Jesse Barnes7885d202012-01-12 14:51:17 -08004832 if (HAS_PCH_CPT(dev)) {
4833 temp &= ~PORT_TRANS_SEL_MASK;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004834 temp |= PORT_TRANS_SEL_CPT(pipe);
Jesse Barnes7885d202012-01-12 14:51:17 -08004835 } else {
4836 if (pipe == 1)
4837 temp |= LVDS_PIPEB_SELECT;
4838 else
4839 temp &= ~LVDS_PIPEB_SELECT;
4840 }
Jesse Barnes4b645f12011-10-12 09:51:31 -07004841
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004842 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01004843 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08004844 /* Set the B0-B3 data pairs corresponding to whether we're going to
4845 * set the DPLLs for dual-channel mode or not.
4846 */
4847 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01004848 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08004849 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004850 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08004851
4852 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4853 * appropriately here, but we need to look more thoroughly into how
4854 * panels behave in the two modes.
4855 */
Chris Wilson284d5df2012-04-14 17:41:59 +01004856 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Bryan Freedaa9b5002011-01-12 13:43:19 -08004857 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004858 temp |= LVDS_HSYNC_POLARITY;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004859 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004860 temp |= LVDS_VSYNC_POLARITY;
Eric Anholtfae14982011-03-30 13:01:09 -07004861 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08004862 }
Jesse Barnes434ed092010-09-07 14:48:06 -07004863
Eric Anholt8febb292011-03-30 13:01:07 -07004864 pipeconf &= ~PIPECONF_DITHER_EN;
4865 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
Jesse Barnes5a354202011-06-24 12:19:22 -07004866 if ((is_lvds && dev_priv->lvds_dither) || dither) {
Eric Anholt8febb292011-03-30 13:01:07 -07004867 pipeconf |= PIPECONF_DITHER_EN;
Daniel Vetterf74974c2011-10-11 17:27:51 +02004868 pipeconf |= PIPECONF_DITHER_TYPE_SP;
Jesse Barnes434ed092010-09-07 14:48:06 -07004869 }
Jesse Barnese3aef172012-04-10 11:58:03 -07004870 if (is_dp && !is_cpu_edp) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004871 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07004872 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004873 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004874 I915_WRITE(TRANSDATA_M1(pipe), 0);
4875 I915_WRITE(TRANSDATA_N1(pipe), 0);
4876 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4877 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004878 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004879
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004880 if (intel_crtc->pch_pll) {
4881 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01004882
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004883 /* Wait for the clocks to stabilize. */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004884 POSTING_READ(intel_crtc->pch_pll->pll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004885 udelay(150);
4886
Eric Anholt8febb292011-03-30 13:01:07 -07004887 /* The pixel multiplier can only be updated once the
4888 * DPLL is enabled and the clocks are stable.
4889 *
4890 * So write it again.
4891 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004892 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08004893 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004894
Chris Wilson5eddb702010-09-11 13:48:45 +01004895 intel_crtc->lowfreq_avail = false;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004896 if (intel_crtc->pch_pll) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07004897 if (is_lvds && has_reduced_clock && i915_powersave) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004898 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
Jesse Barnes4b645f12011-10-12 09:51:31 -07004899 intel_crtc->lowfreq_avail = true;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004900 } else {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004901 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07004902 }
4903 }
4904
Keith Packard617cf882012-02-08 13:53:38 -08004905 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004906 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Daniel Vetter5def4742012-01-28 14:49:22 +01004907 pipeconf |= PIPECONF_INTERLACED_ILK;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004908 /* the chip adds 2 halflines automatically */
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004909 adjusted_mode->crtc_vtotal -= 1;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004910 adjusted_mode->crtc_vblank_end -= 1;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004911 I915_WRITE(VSYNCSHIFT(pipe),
4912 adjusted_mode->crtc_hsync_start
4913 - adjusted_mode->crtc_htotal/2);
4914 } else {
Keith Packard617cf882012-02-08 13:53:38 -08004915 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004916 I915_WRITE(VSYNCSHIFT(pipe), 0);
4917 }
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004918
Chris Wilson5eddb702010-09-11 13:48:45 +01004919 I915_WRITE(HTOTAL(pipe),
4920 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004921 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004922 I915_WRITE(HBLANK(pipe),
4923 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004924 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004925 I915_WRITE(HSYNC(pipe),
4926 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004927 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004928
4929 I915_WRITE(VTOTAL(pipe),
4930 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004931 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004932 I915_WRITE(VBLANK(pipe),
4933 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004934 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004935 I915_WRITE(VSYNC(pipe),
4936 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004937 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004938
Eric Anholt8febb292011-03-30 13:01:07 -07004939 /* pipesrc controls the size that is scaled from, which should
4940 * always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08004941 */
Chris Wilson5eddb702010-09-11 13:48:45 +01004942 I915_WRITE(PIPESRC(pipe),
4943 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08004944
Eric Anholt8febb292011-03-30 13:01:07 -07004945 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4946 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4947 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4948 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004949
Jesse Barnese3aef172012-04-10 11:58:03 -07004950 if (is_cpu_edp)
Eric Anholt8febb292011-03-30 13:01:07 -07004951 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004952
Chris Wilson5eddb702010-09-11 13:48:45 +01004953 I915_WRITE(PIPECONF(pipe), pipeconf);
4954 POSTING_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004955
Jesse Barnes9d0498a2010-08-18 13:20:54 -07004956 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08004957
Chris Wilson5eddb702010-09-11 13:48:45 +01004958 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08004959 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08004960
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004961 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004962
4963 intel_update_watermarks(dev);
4964
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03004965 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4966
Chris Wilson1f803ee2009-06-06 09:45:59 +01004967 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004968}
4969
Eric Anholtf564048e2011-03-30 13:01:02 -07004970static int intel_crtc_mode_set(struct drm_crtc *crtc,
4971 struct drm_display_mode *mode,
4972 struct drm_display_mode *adjusted_mode,
4973 int x, int y,
4974 struct drm_framebuffer *old_fb)
4975{
4976 struct drm_device *dev = crtc->dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07004978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4979 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07004980 int ret;
4981
Eric Anholt0b701d22011-03-30 13:01:03 -07004982 drm_vblank_pre_modeset(dev, pipe);
4983
Eric Anholtf564048e2011-03-30 13:01:02 -07004984 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4985 x, y, old_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08004986 drm_vblank_post_modeset(dev, pipe);
4987
Jesse Barnesd8e70a22011-11-15 10:28:54 -08004988 if (ret)
4989 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4990 else
4991 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
Keith Packard120eced2011-07-27 01:21:40 -07004992
Jesse Barnes79e53942008-11-07 14:24:08 -08004993 return ret;
4994}
4995
Wu Fengguang3a9627f2011-12-09 20:42:19 +08004996static bool intel_eld_uptodate(struct drm_connector *connector,
4997 int reg_eldv, uint32_t bits_eldv,
4998 int reg_elda, uint32_t bits_elda,
4999 int reg_edid)
5000{
5001 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5002 uint8_t *eld = connector->eld;
5003 uint32_t i;
5004
5005 i = I915_READ(reg_eldv);
5006 i &= bits_eldv;
5007
5008 if (!eld[0])
5009 return !i;
5010
5011 if (!i)
5012 return false;
5013
5014 i = I915_READ(reg_elda);
5015 i &= ~bits_elda;
5016 I915_WRITE(reg_elda, i);
5017
5018 for (i = 0; i < eld[2]; i++)
5019 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5020 return false;
5021
5022 return true;
5023}
5024
Wu Fengguange0dac652011-09-05 14:25:34 +08005025static void g4x_write_eld(struct drm_connector *connector,
5026 struct drm_crtc *crtc)
5027{
5028 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5029 uint8_t *eld = connector->eld;
5030 uint32_t eldv;
5031 uint32_t len;
5032 uint32_t i;
5033
5034 i = I915_READ(G4X_AUD_VID_DID);
5035
5036 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5037 eldv = G4X_ELDV_DEVCL_DEVBLC;
5038 else
5039 eldv = G4X_ELDV_DEVCTG;
5040
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005041 if (intel_eld_uptodate(connector,
5042 G4X_AUD_CNTL_ST, eldv,
5043 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5044 G4X_HDMIW_HDMIEDID))
5045 return;
5046
Wu Fengguange0dac652011-09-05 14:25:34 +08005047 i = I915_READ(G4X_AUD_CNTL_ST);
5048 i &= ~(eldv | G4X_ELD_ADDR);
5049 len = (i >> 9) & 0x1f; /* ELD buffer size */
5050 I915_WRITE(G4X_AUD_CNTL_ST, i);
5051
5052 if (!eld[0])
5053 return;
5054
5055 len = min_t(uint8_t, eld[2], len);
5056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5057 for (i = 0; i < len; i++)
5058 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5059
5060 i = I915_READ(G4X_AUD_CNTL_ST);
5061 i |= eldv;
5062 I915_WRITE(G4X_AUD_CNTL_ST, i);
5063}
5064
Wang Xingchao83358c852012-08-16 22:43:37 +08005065static void haswell_write_eld(struct drm_connector *connector,
5066 struct drm_crtc *crtc)
5067{
5068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5069 uint8_t *eld = connector->eld;
5070 struct drm_device *dev = crtc->dev;
5071 uint32_t eldv;
5072 uint32_t i;
5073 int len;
5074 int pipe = to_intel_crtc(crtc)->pipe;
5075 int tmp;
5076
5077 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5078 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5079 int aud_config = HSW_AUD_CFG(pipe);
5080 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5081
5082
5083 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5084
5085 /* Audio output enable */
5086 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5087 tmp = I915_READ(aud_cntrl_st2);
5088 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5089 I915_WRITE(aud_cntrl_st2, tmp);
5090
5091 /* Wait for 1 vertical blank */
5092 intel_wait_for_vblank(dev, pipe);
5093
5094 /* Set ELD valid state */
5095 tmp = I915_READ(aud_cntrl_st2);
5096 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5097 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5098 I915_WRITE(aud_cntrl_st2, tmp);
5099 tmp = I915_READ(aud_cntrl_st2);
5100 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5101
5102 /* Enable HDMI mode */
5103 tmp = I915_READ(aud_config);
5104 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5105 /* clear N_programing_enable and N_value_index */
5106 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5107 I915_WRITE(aud_config, tmp);
5108
5109 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5110
5111 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5112
5113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5114 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5115 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5116 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5117 } else
5118 I915_WRITE(aud_config, 0);
5119
5120 if (intel_eld_uptodate(connector,
5121 aud_cntrl_st2, eldv,
5122 aud_cntl_st, IBX_ELD_ADDRESS,
5123 hdmiw_hdmiedid))
5124 return;
5125
5126 i = I915_READ(aud_cntrl_st2);
5127 i &= ~eldv;
5128 I915_WRITE(aud_cntrl_st2, i);
5129
5130 if (!eld[0])
5131 return;
5132
5133 i = I915_READ(aud_cntl_st);
5134 i &= ~IBX_ELD_ADDRESS;
5135 I915_WRITE(aud_cntl_st, i);
5136 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5137 DRM_DEBUG_DRIVER("port num:%d\n", i);
5138
5139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5141 for (i = 0; i < len; i++)
5142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5143
5144 i = I915_READ(aud_cntrl_st2);
5145 i |= eldv;
5146 I915_WRITE(aud_cntrl_st2, i);
5147
5148}
5149
Wu Fengguange0dac652011-09-05 14:25:34 +08005150static void ironlake_write_eld(struct drm_connector *connector,
5151 struct drm_crtc *crtc)
5152{
5153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5154 uint8_t *eld = connector->eld;
5155 uint32_t eldv;
5156 uint32_t i;
5157 int len;
5158 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005159 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08005160 int aud_cntl_st;
5161 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08005162 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08005163
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08005164 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08005165 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5166 aud_config = IBX_AUD_CFG(pipe);
5167 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005168 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005169 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08005170 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5171 aud_config = CPT_AUD_CFG(pipe);
5172 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005173 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005174 }
5175
Wang Xingchao9b138a82012-08-09 16:52:18 +08005176 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08005177
5178 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08005179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08005180 if (!i) {
5181 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5182 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005183 eldv = IBX_ELD_VALIDB;
5184 eldv |= IBX_ELD_VALIDB << 4;
5185 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08005186 } else {
5187 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005188 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08005189 }
5190
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06005194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5195 } else
5196 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005197
5198 if (intel_eld_uptodate(connector,
5199 aud_cntrl_st2, eldv,
5200 aud_cntl_st, IBX_ELD_ADDRESS,
5201 hdmiw_hdmiedid))
5202 return;
5203
Wu Fengguange0dac652011-09-05 14:25:34 +08005204 i = I915_READ(aud_cntrl_st2);
5205 i &= ~eldv;
5206 I915_WRITE(aud_cntrl_st2, i);
5207
5208 if (!eld[0])
5209 return;
5210
Wu Fengguange0dac652011-09-05 14:25:34 +08005211 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005212 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08005213 I915_WRITE(aud_cntl_st, i);
5214
5215 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5216 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5217 for (i = 0; i < len; i++)
5218 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5219
5220 i = I915_READ(aud_cntrl_st2);
5221 i |= eldv;
5222 I915_WRITE(aud_cntrl_st2, i);
5223}
5224
5225void intel_write_eld(struct drm_encoder *encoder,
5226 struct drm_display_mode *mode)
5227{
5228 struct drm_crtc *crtc = encoder->crtc;
5229 struct drm_connector *connector;
5230 struct drm_device *dev = encoder->dev;
5231 struct drm_i915_private *dev_priv = dev->dev_private;
5232
5233 connector = drm_select_eld(encoder, mode);
5234 if (!connector)
5235 return;
5236
5237 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5238 connector->base.id,
5239 drm_get_connector_name(connector),
5240 connector->encoder->base.id,
5241 drm_get_encoder_name(connector->encoder));
5242
5243 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5244
5245 if (dev_priv->display.write_eld)
5246 dev_priv->display.write_eld(connector, crtc);
5247}
5248
Jesse Barnes79e53942008-11-07 14:24:08 -08005249/** Loads the palette/gamma unit for the CRTC with the prepared values */
5250void intel_crtc_load_lut(struct drm_crtc *crtc)
5251{
5252 struct drm_device *dev = crtc->dev;
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005255 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005256 int i;
5257
5258 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00005259 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08005260 return;
5261
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005262 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005263 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005264 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005265
Jesse Barnes79e53942008-11-07 14:24:08 -08005266 for (i = 0; i < 256; i++) {
5267 I915_WRITE(palreg + 4 * i,
5268 (intel_crtc->lut_r[i] << 16) |
5269 (intel_crtc->lut_g[i] << 8) |
5270 intel_crtc->lut_b[i]);
5271 }
5272}
5273
Chris Wilson560b85b2010-08-07 11:01:38 +01005274static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5275{
5276 struct drm_device *dev = crtc->dev;
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5279 bool visible = base != 0;
5280 u32 cntl;
5281
5282 if (intel_crtc->cursor_visible == visible)
5283 return;
5284
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005285 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005286 if (visible) {
5287 /* On these chipsets we can only modify the base whilst
5288 * the cursor is disabled.
5289 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005290 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005291
5292 cntl &= ~(CURSOR_FORMAT_MASK);
5293 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5294 cntl |= CURSOR_ENABLE |
5295 CURSOR_GAMMA_ENABLE |
5296 CURSOR_FORMAT_ARGB;
5297 } else
5298 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005299 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005300
5301 intel_crtc->cursor_visible = visible;
5302}
5303
5304static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 int pipe = intel_crtc->pipe;
5310 bool visible = base != 0;
5311
5312 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005313 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005314 if (base) {
5315 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5316 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5317 cntl |= pipe << 28; /* Connect to correct pipe */
5318 } else {
5319 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5320 cntl |= CURSOR_MODE_DISABLE;
5321 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005322 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005323
5324 intel_crtc->cursor_visible = visible;
5325 }
5326 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005327 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005328}
5329
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005330static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5331{
5332 struct drm_device *dev = crtc->dev;
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5335 int pipe = intel_crtc->pipe;
5336 bool visible = base != 0;
5337
5338 if (intel_crtc->cursor_visible != visible) {
5339 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5340 if (base) {
5341 cntl &= ~CURSOR_MODE;
5342 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5343 } else {
5344 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5345 cntl |= CURSOR_MODE_DISABLE;
5346 }
5347 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5348
5349 intel_crtc->cursor_visible = visible;
5350 }
5351 /* and commit changes on next vblank */
5352 I915_WRITE(CURBASE_IVB(pipe), base);
5353}
5354
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005355/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005356static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5357 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005358{
5359 struct drm_device *dev = crtc->dev;
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5362 int pipe = intel_crtc->pipe;
5363 int x = intel_crtc->cursor_x;
5364 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005365 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005366 bool visible;
5367
5368 pos = 0;
5369
Chris Wilson6b383a72010-09-13 13:54:26 +01005370 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005371 base = intel_crtc->cursor_addr;
5372 if (x > (int) crtc->fb->width)
5373 base = 0;
5374
5375 if (y > (int) crtc->fb->height)
5376 base = 0;
5377 } else
5378 base = 0;
5379
5380 if (x < 0) {
5381 if (x + intel_crtc->cursor_width < 0)
5382 base = 0;
5383
5384 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5385 x = -x;
5386 }
5387 pos |= x << CURSOR_X_SHIFT;
5388
5389 if (y < 0) {
5390 if (y + intel_crtc->cursor_height < 0)
5391 base = 0;
5392
5393 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5394 y = -y;
5395 }
5396 pos |= y << CURSOR_Y_SHIFT;
5397
5398 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005399 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005400 return;
5401
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03005402 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005403 I915_WRITE(CURPOS_IVB(pipe), pos);
5404 ivb_update_cursor(crtc, base);
5405 } else {
5406 I915_WRITE(CURPOS(pipe), pos);
5407 if (IS_845G(dev) || IS_I865G(dev))
5408 i845_update_cursor(crtc, base);
5409 else
5410 i9xx_update_cursor(crtc, base);
5411 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005412}
5413
Jesse Barnes79e53942008-11-07 14:24:08 -08005414static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005415 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005416 uint32_t handle,
5417 uint32_t width, uint32_t height)
5418{
5419 struct drm_device *dev = crtc->dev;
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005422 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005423 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005424 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005425
Zhao Yakui28c97732009-10-09 11:39:41 +08005426 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005427
5428 /* if we want to turn off the cursor ignore width and height */
5429 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005430 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005431 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005432 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005433 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005434 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005435 }
5436
5437 /* Currently we only support 64x64 cursors */
5438 if (width != 64 || height != 64) {
5439 DRM_ERROR("we currently only support 64x64 cursors\n");
5440 return -EINVAL;
5441 }
5442
Chris Wilson05394f32010-11-08 19:18:58 +00005443 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00005444 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08005445 return -ENOENT;
5446
Chris Wilson05394f32010-11-08 19:18:58 +00005447 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005448 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005449 ret = -ENOMEM;
5450 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005451 }
5452
Dave Airlie71acb5e2008-12-30 20:31:46 +10005453 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005454 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005455 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005456 if (obj->tiling_mode) {
5457 DRM_ERROR("cursor cannot be tiled\n");
5458 ret = -EINVAL;
5459 goto fail_locked;
5460 }
5461
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005462 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005463 if (ret) {
5464 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005465 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005466 }
5467
Chris Wilsond9e86c02010-11-10 16:40:20 +00005468 ret = i915_gem_object_put_fence(obj);
5469 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005470 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00005471 goto fail_unpin;
5472 }
5473
Chris Wilson05394f32010-11-08 19:18:58 +00005474 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005475 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005476 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005477 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005478 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5479 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005480 if (ret) {
5481 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005482 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005483 }
Chris Wilson05394f32010-11-08 19:18:58 +00005484 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005485 }
5486
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005487 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005488 I915_WRITE(CURSIZE, (height << 12) | width);
5489
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005490 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005491 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005492 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005493 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005494 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5495 } else
5496 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005497 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005498 }
Jesse Barnes80824002009-09-10 15:28:06 -07005499
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005500 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005501
5502 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005503 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005504 intel_crtc->cursor_width = width;
5505 intel_crtc->cursor_height = height;
5506
Chris Wilson6b383a72010-09-13 13:54:26 +01005507 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005508
Jesse Barnes79e53942008-11-07 14:24:08 -08005509 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005510fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005511 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005512fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005513 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005514fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005515 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005516 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005517}
5518
5519static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5520{
Jesse Barnes79e53942008-11-07 14:24:08 -08005521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005522
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005523 intel_crtc->cursor_x = x;
5524 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005525
Chris Wilson6b383a72010-09-13 13:54:26 +01005526 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005527
5528 return 0;
5529}
5530
5531/** Sets the color ramps on behalf of RandR */
5532void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5533 u16 blue, int regno)
5534{
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536
5537 intel_crtc->lut_r[regno] = red >> 8;
5538 intel_crtc->lut_g[regno] = green >> 8;
5539 intel_crtc->lut_b[regno] = blue >> 8;
5540}
5541
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005542void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5543 u16 *blue, int regno)
5544{
5545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5546
5547 *red = intel_crtc->lut_r[regno] << 8;
5548 *green = intel_crtc->lut_g[regno] << 8;
5549 *blue = intel_crtc->lut_b[regno] << 8;
5550}
5551
Jesse Barnes79e53942008-11-07 14:24:08 -08005552static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005553 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005554{
James Simmons72034252010-08-03 01:33:19 +01005555 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005557
James Simmons72034252010-08-03 01:33:19 +01005558 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005559 intel_crtc->lut_r[i] = red[i] >> 8;
5560 intel_crtc->lut_g[i] = green[i] >> 8;
5561 intel_crtc->lut_b[i] = blue[i] >> 8;
5562 }
5563
5564 intel_crtc_load_lut(crtc);
5565}
5566
5567/**
5568 * Get a pipe with a simple mode set on it for doing load-based monitor
5569 * detection.
5570 *
5571 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005572 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005573 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005574 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005575 * configured for it. In the future, it could choose to temporarily disable
5576 * some outputs to free up a pipe for its use.
5577 *
5578 * \return crtc, or NULL if no pipes are available.
5579 */
5580
5581/* VESA 640x480x72Hz mode to set on the pipe */
5582static struct drm_display_mode load_detect_mode = {
5583 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5584 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5585};
5586
Chris Wilsond2dff872011-04-19 08:36:26 +01005587static struct drm_framebuffer *
5588intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005589 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01005590 struct drm_i915_gem_object *obj)
5591{
5592 struct intel_framebuffer *intel_fb;
5593 int ret;
5594
5595 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5596 if (!intel_fb) {
5597 drm_gem_object_unreference_unlocked(&obj->base);
5598 return ERR_PTR(-ENOMEM);
5599 }
5600
5601 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5602 if (ret) {
5603 drm_gem_object_unreference_unlocked(&obj->base);
5604 kfree(intel_fb);
5605 return ERR_PTR(ret);
5606 }
5607
5608 return &intel_fb->base;
5609}
5610
5611static u32
5612intel_framebuffer_pitch_for_width(int width, int bpp)
5613{
5614 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5615 return ALIGN(pitch, 64);
5616}
5617
5618static u32
5619intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5620{
5621 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5622 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5623}
5624
5625static struct drm_framebuffer *
5626intel_framebuffer_create_for_mode(struct drm_device *dev,
5627 struct drm_display_mode *mode,
5628 int depth, int bpp)
5629{
5630 struct drm_i915_gem_object *obj;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005631 struct drm_mode_fb_cmd2 mode_cmd;
Chris Wilsond2dff872011-04-19 08:36:26 +01005632
5633 obj = i915_gem_alloc_object(dev,
5634 intel_framebuffer_size_for_mode(mode, bpp));
5635 if (obj == NULL)
5636 return ERR_PTR(-ENOMEM);
5637
5638 mode_cmd.width = mode->hdisplay;
5639 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005640 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5641 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00005642 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01005643
5644 return intel_framebuffer_create(dev, &mode_cmd, obj);
5645}
5646
5647static struct drm_framebuffer *
5648mode_fits_in_fbdev(struct drm_device *dev,
5649 struct drm_display_mode *mode)
5650{
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652 struct drm_i915_gem_object *obj;
5653 struct drm_framebuffer *fb;
5654
5655 if (dev_priv->fbdev == NULL)
5656 return NULL;
5657
5658 obj = dev_priv->fbdev->ifb.obj;
5659 if (obj == NULL)
5660 return NULL;
5661
5662 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02005663 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5664 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01005665 return NULL;
5666
Ville Syrjälä01f2c772011-12-20 00:06:49 +02005667 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01005668 return NULL;
5669
5670 return fb;
5671}
5672
Daniel Vetterd2434ab2012-08-12 21:20:10 +02005673bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01005674 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01005675 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005676{
5677 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02005678 struct intel_encoder *intel_encoder =
5679 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08005680 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01005681 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005682 struct drm_crtc *crtc = NULL;
5683 struct drm_device *dev = encoder->dev;
Chris Wilsond2dff872011-04-19 08:36:26 +01005684 struct drm_framebuffer *old_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08005685 int i = -1;
5686
Chris Wilsond2dff872011-04-19 08:36:26 +01005687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5688 connector->base.id, drm_get_connector_name(connector),
5689 encoder->base.id, drm_get_encoder_name(encoder));
5690
Jesse Barnes79e53942008-11-07 14:24:08 -08005691 /*
5692 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01005693 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005694 * - if the connector already has an assigned crtc, use it (but make
5695 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01005696 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005697 * - try to find the first unused crtc that can drive this connector,
5698 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08005699 */
5700
5701 /* See if we already have a CRTC for this connector */
5702 if (encoder->crtc) {
5703 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01005704
Daniel Vetter24218aa2012-08-12 19:27:11 +02005705 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01005706 old->load_detect_temp = false;
5707
5708 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02005709 if (connector->dpms != DRM_MODE_DPMS_ON)
5710 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01005711
Chris Wilson71731882011-04-19 23:10:58 +01005712 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005713 }
5714
5715 /* Find an unused one (if possible) */
5716 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5717 i++;
5718 if (!(encoder->possible_crtcs & (1 << i)))
5719 continue;
5720 if (!possible_crtc->enabled) {
5721 crtc = possible_crtc;
5722 break;
5723 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005724 }
5725
5726 /*
5727 * If we didn't find an unused CRTC, don't use any.
5728 */
5729 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01005730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5731 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005732 }
5733
5734 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005735 connector->encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005736
5737 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02005738 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01005739 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01005740 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005741
Chris Wilson64927112011-04-20 07:25:26 +01005742 if (!mode)
5743 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08005744
Chris Wilsond2dff872011-04-19 08:36:26 +01005745 old_fb = crtc->fb;
5746
5747 /* We need a framebuffer large enough to accommodate all accesses
5748 * that the plane may generate whilst we perform load detection.
5749 * We can not rely on the fbcon either being present (we get called
5750 * during its initialisation to detect all boot displays, or it may
5751 * not even exist) or that it is large enough to satisfy the
5752 * requested mode.
5753 */
5754 crtc->fb = mode_fits_in_fbdev(dev, mode);
5755 if (crtc->fb == NULL) {
5756 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5757 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5758 old->release_fb = crtc->fb;
5759 } else
5760 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5761 if (IS_ERR(crtc->fb)) {
5762 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter24218aa2012-08-12 19:27:11 +02005763 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005764 }
Chris Wilsond2dff872011-04-19 08:36:26 +01005765
Daniel Vettera6778b32012-07-02 09:56:42 +02005766 if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01005767 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01005768 if (old->release_fb)
5769 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter24218aa2012-08-12 19:27:11 +02005770 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005771 }
Chris Wilson71731882011-04-19 23:10:58 +01005772
Jesse Barnes79e53942008-11-07 14:24:08 -08005773 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005774 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005775
Chris Wilson71731882011-04-19 23:10:58 +01005776 return true;
Daniel Vetter24218aa2012-08-12 19:27:11 +02005777fail:
5778 connector->encoder = NULL;
5779 encoder->crtc = NULL;
5780 crtc->fb = old_fb;
5781 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005782}
5783
Daniel Vetterd2434ab2012-08-12 21:20:10 +02005784void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01005785 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005786{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02005787 struct intel_encoder *intel_encoder =
5788 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01005789 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005790 struct drm_device *dev = encoder->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08005791
Chris Wilsond2dff872011-04-19 08:36:26 +01005792 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5793 connector->base.id, drm_get_connector_name(connector),
5794 encoder->base.id, drm_get_encoder_name(encoder));
5795
Chris Wilson8261b192011-04-19 23:18:09 +01005796 if (old->load_detect_temp) {
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005797 connector->encoder = NULL;
Daniel Vetter24218aa2012-08-12 19:27:11 +02005798 encoder->crtc = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005799 drm_helper_disable_unused_functions(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +01005800
5801 if (old->release_fb)
5802 old->release_fb->funcs->destroy(old->release_fb);
5803
Chris Wilson0622a532011-04-21 09:32:11 +01005804 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08005805 }
5806
Eric Anholtc751ce42010-03-25 11:48:48 -07005807 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02005808 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5809 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08005810}
5811
5812/* Returns the clock of the currently programmed mode of the given pipe. */
5813static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5814{
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08005818 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005819 u32 fp;
5820 intel_clock_t clock;
5821
5822 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01005823 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005824 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01005825 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005826
5827 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005828 if (IS_PINEVIEW(dev)) {
5829 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5830 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08005831 } else {
5832 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5833 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5834 }
5835
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005836 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005837 if (IS_PINEVIEW(dev))
5838 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5839 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08005840 else
5841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08005842 DPLL_FPA01_P1_POST_DIV_SHIFT);
5843
5844 switch (dpll & DPLL_MODE_MASK) {
5845 case DPLLB_MODE_DAC_SERIAL:
5846 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5847 5 : 10;
5848 break;
5849 case DPLLB_MODE_LVDS:
5850 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5851 7 : 14;
5852 break;
5853 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08005854 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08005855 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5856 return 0;
5857 }
5858
5859 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08005860 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005861 } else {
5862 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5863
5864 if (is_lvds) {
5865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5866 DPLL_FPA01_P1_POST_DIV_SHIFT);
5867 clock.p2 = 14;
5868
5869 if ((dpll & PLL_REF_INPUT_MASK) ==
5870 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5871 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08005872 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005873 } else
Shaohua Li21778322009-02-23 15:19:16 +08005874 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005875 } else {
5876 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5877 clock.p1 = 2;
5878 else {
5879 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5880 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5881 }
5882 if (dpll & PLL_P2_DIVIDE_BY_4)
5883 clock.p2 = 4;
5884 else
5885 clock.p2 = 2;
5886
Shaohua Li21778322009-02-23 15:19:16 +08005887 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005888 }
5889 }
5890
5891 /* XXX: It would be nice to validate the clocks, but we can't reuse
5892 * i830PllIsValid() because it relies on the xf86_config connector
5893 * configuration being accurate, which it isn't necessarily.
5894 */
5895
5896 return clock.dot;
5897}
5898
5899/** Returns the currently programmed mode of the given pipe. */
5900struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5901 struct drm_crtc *crtc)
5902{
Jesse Barnes548f2452011-02-17 10:40:53 -08005903 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5905 int pipe = intel_crtc->pipe;
5906 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08005907 int htot = I915_READ(HTOTAL(pipe));
5908 int hsync = I915_READ(HSYNC(pipe));
5909 int vtot = I915_READ(VTOTAL(pipe));
5910 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005911
5912 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5913 if (!mode)
5914 return NULL;
5915
5916 mode->clock = intel_crtc_clock_get(dev, crtc);
5917 mode->hdisplay = (htot & 0xffff) + 1;
5918 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5919 mode->hsync_start = (hsync & 0xffff) + 1;
5920 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5921 mode->vdisplay = (vtot & 0xffff) + 1;
5922 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5923 mode->vsync_start = (vsync & 0xffff) + 1;
5924 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5925
5926 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08005927
5928 return mode;
5929}
5930
Daniel Vetter3dec0092010-08-20 21:40:52 +02005931static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07005932{
5933 struct drm_device *dev = crtc->dev;
5934 drm_i915_private_t *dev_priv = dev->dev_private;
5935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005937 int dpll_reg = DPLL(pipe);
5938 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07005939
Eric Anholtbad720f2009-10-22 16:11:14 -07005940 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005941 return;
5942
5943 if (!dev_priv->lvds_downclock_avail)
5944 return;
5945
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005946 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005947 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005948 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005949
Sean Paul8ac5a6d2012-02-13 13:14:51 -05005950 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005951
5952 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5953 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005954 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005955
Jesse Barnes652c3932009-08-17 13:31:43 -07005956 dpll = I915_READ(dpll_reg);
5957 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08005958 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005959 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005960}
5961
5962static void intel_decrease_pllclock(struct drm_crtc *crtc)
5963{
5964 struct drm_device *dev = crtc->dev;
5965 drm_i915_private_t *dev_priv = dev->dev_private;
5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005967
Eric Anholtbad720f2009-10-22 16:11:14 -07005968 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005969 return;
5970
5971 if (!dev_priv->lvds_downclock_avail)
5972 return;
5973
5974 /*
5975 * Since this is called by a timer, we should never get here in
5976 * the manual case.
5977 */
5978 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01005979 int pipe = intel_crtc->pipe;
5980 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02005981 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01005982
Zhao Yakui44d98a62009-10-09 11:39:40 +08005983 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005984
Sean Paul8ac5a6d2012-02-13 13:14:51 -05005985 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005986
Chris Wilson074b5e12012-05-02 12:07:06 +01005987 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005988 dpll |= DISPLAY_RATE_SELECT_FPA1;
5989 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005990 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005991 dpll = I915_READ(dpll_reg);
5992 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08005993 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005994 }
5995
5996}
5997
Chris Wilsonf047e392012-07-21 12:31:41 +01005998void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07005999{
Chris Wilsonf047e392012-07-21 12:31:41 +01006000 i915_update_gfx_val(dev->dev_private);
6001}
6002
6003void intel_mark_idle(struct drm_device *dev)
6004{
Chris Wilsonf047e392012-07-21 12:31:41 +01006005}
6006
6007void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6008{
6009 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07006010 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07006011
6012 if (!i915_powersave)
6013 return;
6014
Jesse Barnes652c3932009-08-17 13:31:43 -07006015 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006016 if (!crtc->fb)
6017 continue;
6018
Chris Wilsonf047e392012-07-21 12:31:41 +01006019 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6020 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006021 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006022}
6023
Chris Wilsonf047e392012-07-21 12:31:41 +01006024void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07006025{
Chris Wilsonf047e392012-07-21 12:31:41 +01006026 struct drm_device *dev = obj->base.dev;
6027 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07006028
Chris Wilsonf047e392012-07-21 12:31:41 +01006029 if (!i915_powersave)
Chris Wilsonacb87df2012-05-03 15:47:57 +01006030 return;
6031
Jesse Barnes652c3932009-08-17 13:31:43 -07006032 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6033 if (!crtc->fb)
6034 continue;
6035
Chris Wilsonf047e392012-07-21 12:31:41 +01006036 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6037 intel_decrease_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006038 }
6039}
6040
Jesse Barnes79e53942008-11-07 14:24:08 -08006041static void intel_crtc_destroy(struct drm_crtc *crtc)
6042{
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006044 struct drm_device *dev = crtc->dev;
6045 struct intel_unpin_work *work;
6046 unsigned long flags;
6047
6048 spin_lock_irqsave(&dev->event_lock, flags);
6049 work = intel_crtc->unpin_work;
6050 intel_crtc->unpin_work = NULL;
6051 spin_unlock_irqrestore(&dev->event_lock, flags);
6052
6053 if (work) {
6054 cancel_work_sync(&work->work);
6055 kfree(work);
6056 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006057
6058 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02006059
Jesse Barnes79e53942008-11-07 14:24:08 -08006060 kfree(intel_crtc);
6061}
6062
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006063static void intel_unpin_work_fn(struct work_struct *__work)
6064{
6065 struct intel_unpin_work *work =
6066 container_of(__work, struct intel_unpin_work, work);
6067
6068 mutex_lock(&work->dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01006069 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00006070 drm_gem_object_unreference(&work->pending_flip_obj->base);
6071 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006072
Chris Wilson7782de32011-07-08 12:22:41 +01006073 intel_update_fbc(work->dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006074 mutex_unlock(&work->dev->struct_mutex);
6075 kfree(work);
6076}
6077
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006078static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01006079 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006080{
6081 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00006084 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006085 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006086 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006087 unsigned long flags;
6088
6089 /* Ignore early vblank irqs */
6090 if (intel_crtc == NULL)
6091 return;
6092
Mario Kleiner49b14a52010-12-09 07:00:07 +01006093 do_gettimeofday(&tnow);
6094
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006095 spin_lock_irqsave(&dev->event_lock, flags);
6096 work = intel_crtc->unpin_work;
6097 if (work == NULL || !work->pending) {
6098 spin_unlock_irqrestore(&dev->event_lock, flags);
6099 return;
6100 }
6101
6102 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006103
6104 if (work->event) {
6105 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006106 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006107
6108 /* Called before vblank count and timestamps have
6109 * been updated for the vblank interval of flip
6110 * completion? Need to increment vblank count and
6111 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01006112 * to account for this. We assume this happened if we
6113 * get called over 0.9 frame durations after the last
6114 * timestamped vblank.
6115 *
6116 * This calculation can not be used with vrefresh rates
6117 * below 5Hz (10Hz to be on the safe side) without
6118 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006119 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01006120 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6121 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006122 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006123 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6124 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006125 }
6126
Mario Kleiner49b14a52010-12-09 07:00:07 +01006127 e->event.tv_sec = tvbl.tv_sec;
6128 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006129
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006130 list_add_tail(&e->base.link,
6131 &e->base.file_priv->event_list);
6132 wake_up_interruptible(&e->base.file_priv->event_wait);
6133 }
6134
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006135 drm_vblank_put(dev, intel_crtc->pipe);
6136
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006137 spin_unlock_irqrestore(&dev->event_lock, flags);
6138
Chris Wilson05394f32010-11-08 19:18:58 +00006139 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006140
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006141 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006142 &obj->pending_flip.counter);
6143 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006144 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006145
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006146 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006147
6148 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006149}
6150
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006151void intel_finish_page_flip(struct drm_device *dev, int pipe)
6152{
6153 drm_i915_private_t *dev_priv = dev->dev_private;
6154 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6155
Mario Kleiner49b14a52010-12-09 07:00:07 +01006156 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006157}
6158
6159void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6160{
6161 drm_i915_private_t *dev_priv = dev->dev_private;
6162 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6163
Mario Kleiner49b14a52010-12-09 07:00:07 +01006164 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006165}
6166
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006167void intel_prepare_page_flip(struct drm_device *dev, int plane)
6168{
6169 drm_i915_private_t *dev_priv = dev->dev_private;
6170 struct intel_crtc *intel_crtc =
6171 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6172 unsigned long flags;
6173
6174 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006175 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006176 if ((++intel_crtc->unpin_work->pending) > 1)
6177 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006178 } else {
6179 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6180 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006181 spin_unlock_irqrestore(&dev->event_lock, flags);
6182}
6183
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006184static int intel_gen2_queue_flip(struct drm_device *dev,
6185 struct drm_crtc *crtc,
6186 struct drm_framebuffer *fb,
6187 struct drm_i915_gem_object *obj)
6188{
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006191 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006192 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006193 int ret;
6194
Daniel Vetter6d90c952012-04-26 23:28:05 +02006195 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006196 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006197 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006198
Daniel Vetter6d90c952012-04-26 23:28:05 +02006199 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006200 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006201 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006202
6203 /* Can't queue multiple flips, so wait for the previous
6204 * one to finish before executing the next.
6205 */
6206 if (intel_crtc->plane)
6207 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6208 else
6209 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006210 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6211 intel_ring_emit(ring, MI_NOOP);
6212 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6213 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6214 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006215 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006216 intel_ring_emit(ring, 0); /* aux display base address, unused */
6217 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006218 return 0;
6219
6220err_unpin:
6221 intel_unpin_fb_obj(obj);
6222err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006223 return ret;
6224}
6225
6226static int intel_gen3_queue_flip(struct drm_device *dev,
6227 struct drm_crtc *crtc,
6228 struct drm_framebuffer *fb,
6229 struct drm_i915_gem_object *obj)
6230{
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006233 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006234 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006235 int ret;
6236
Daniel Vetter6d90c952012-04-26 23:28:05 +02006237 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006238 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006239 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006240
Daniel Vetter6d90c952012-04-26 23:28:05 +02006241 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006242 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006243 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006244
6245 if (intel_crtc->plane)
6246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6247 else
6248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250 intel_ring_emit(ring, MI_NOOP);
6251 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006255 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006256
Daniel Vetter6d90c952012-04-26 23:28:05 +02006257 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006258 return 0;
6259
6260err_unpin:
6261 intel_unpin_fb_obj(obj);
6262err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006263 return ret;
6264}
6265
6266static int intel_gen4_queue_flip(struct drm_device *dev,
6267 struct drm_crtc *crtc,
6268 struct drm_framebuffer *fb,
6269 struct drm_i915_gem_object *obj)
6270{
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006275 int ret;
6276
Daniel Vetter6d90c952012-04-26 23:28:05 +02006277 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006278 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006279 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006280
Daniel Vetter6d90c952012-04-26 23:28:05 +02006281 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006282 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006283 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006284
6285 /* i965+ uses the linear or tiled offsets from the
6286 * Display Registers (which do not change across a page-flip)
6287 * so we need only reprogram the base address.
6288 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02006289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6291 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006292 intel_ring_emit(ring,
6293 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6294 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006295
6296 /* XXX Enabling the panel-fitter across page-flip is so far
6297 * untested on non-native modes, so ignore it for now.
6298 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6299 */
6300 pf = 0;
6301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006302 intel_ring_emit(ring, pf | pipesrc);
6303 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006304 return 0;
6305
6306err_unpin:
6307 intel_unpin_fb_obj(obj);
6308err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006309 return ret;
6310}
6311
6312static int intel_gen6_queue_flip(struct drm_device *dev,
6313 struct drm_crtc *crtc,
6314 struct drm_framebuffer *fb,
6315 struct drm_i915_gem_object *obj)
6316{
6317 struct drm_i915_private *dev_priv = dev->dev_private;
6318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006320 uint32_t pf, pipesrc;
6321 int ret;
6322
Daniel Vetter6d90c952012-04-26 23:28:05 +02006323 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006324 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006325 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006326
Daniel Vetter6d90c952012-04-26 23:28:05 +02006327 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006328 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006329 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006330
Daniel Vetter6d90c952012-04-26 23:28:05 +02006331 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6332 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6333 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006334 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006335
Chris Wilson99d9acd2012-04-17 20:37:00 +01006336 /* Contrary to the suggestions in the documentation,
6337 * "Enable Panel Fitter" does not seem to be required when page
6338 * flipping with a non-native mode, and worse causes a normal
6339 * modeset to fail.
6340 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6341 */
6342 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006343 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006344 intel_ring_emit(ring, pf | pipesrc);
6345 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006346 return 0;
6347
6348err_unpin:
6349 intel_unpin_fb_obj(obj);
6350err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006351 return ret;
6352}
6353
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006354/*
6355 * On gen7 we currently use the blit ring because (in early silicon at least)
6356 * the render ring doesn't give us interrpts for page flip completion, which
6357 * means clients will hang after the first flip is queued. Fortunately the
6358 * blit ring generates interrupts properly, so use it instead.
6359 */
6360static int intel_gen7_queue_flip(struct drm_device *dev,
6361 struct drm_crtc *crtc,
6362 struct drm_framebuffer *fb,
6363 struct drm_i915_gem_object *obj)
6364{
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006368 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006369 int ret;
6370
6371 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6372 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006373 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006374
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006375 switch(intel_crtc->plane) {
6376 case PLANE_A:
6377 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6378 break;
6379 case PLANE_B:
6380 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6381 break;
6382 case PLANE_C:
6383 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6384 break;
6385 default:
6386 WARN_ONCE(1, "unknown plane in flip command\n");
6387 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03006388 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006389 }
6390
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006391 ret = intel_ring_begin(ring, 4);
6392 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006393 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006394
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006395 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006396 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02006397 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006398 intel_ring_emit(ring, (MI_NOOP));
6399 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006400 return 0;
6401
6402err_unpin:
6403 intel_unpin_fb_obj(obj);
6404err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006405 return ret;
6406}
6407
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006408static int intel_default_queue_flip(struct drm_device *dev,
6409 struct drm_crtc *crtc,
6410 struct drm_framebuffer *fb,
6411 struct drm_i915_gem_object *obj)
6412{
6413 return -ENODEV;
6414}
6415
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006416static int intel_crtc_page_flip(struct drm_crtc *crtc,
6417 struct drm_framebuffer *fb,
6418 struct drm_pending_vblank_event *event)
6419{
6420 struct drm_device *dev = crtc->dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00006423 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6425 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006426 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01006427 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006428
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03006429 /* Can't change pixel format via MI display flips. */
6430 if (fb->pixel_format != crtc->fb->pixel_format)
6431 return -EINVAL;
6432
6433 /*
6434 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6435 * Note that pitch changes could also affect these register.
6436 */
6437 if (INTEL_INFO(dev)->gen > 3 &&
6438 (fb->offsets[0] != crtc->fb->offsets[0] ||
6439 fb->pitches[0] != crtc->fb->pitches[0]))
6440 return -EINVAL;
6441
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006442 work = kzalloc(sizeof *work, GFP_KERNEL);
6443 if (work == NULL)
6444 return -ENOMEM;
6445
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006446 work->event = event;
6447 work->dev = crtc->dev;
6448 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006449 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006450 INIT_WORK(&work->work, intel_unpin_work_fn);
6451
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006452 ret = drm_vblank_get(dev, intel_crtc->pipe);
6453 if (ret)
6454 goto free_work;
6455
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006456 /* We borrow the event spin lock for protecting unpin_work */
6457 spin_lock_irqsave(&dev->event_lock, flags);
6458 if (intel_crtc->unpin_work) {
6459 spin_unlock_irqrestore(&dev->event_lock, flags);
6460 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006461 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01006462
6463 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006464 return -EBUSY;
6465 }
6466 intel_crtc->unpin_work = work;
6467 spin_unlock_irqrestore(&dev->event_lock, flags);
6468
6469 intel_fb = to_intel_framebuffer(fb);
6470 obj = intel_fb->obj;
6471
Chris Wilson79158102012-05-23 11:13:58 +01006472 ret = i915_mutex_lock_interruptible(dev);
6473 if (ret)
6474 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006475
Jesse Barnes75dfca82010-02-10 15:09:44 -08006476 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00006477 drm_gem_object_reference(&work->old_fb_obj->base);
6478 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006479
6480 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01006481
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006482 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006483
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006484 work->enable_stall_check = true;
6485
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006486 /* Block clients from rendering to the new back buffer until
6487 * the flip occurs and the object is no longer visible.
6488 */
Chris Wilson05394f32010-11-08 19:18:58 +00006489 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006490
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006491 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6492 if (ret)
6493 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006494
Chris Wilson7782de32011-07-08 12:22:41 +01006495 intel_disable_fbc(dev);
Chris Wilsonf047e392012-07-21 12:31:41 +01006496 intel_mark_fb_busy(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006497 mutex_unlock(&dev->struct_mutex);
6498
Jesse Barnese5510fa2010-07-01 16:48:37 -07006499 trace_i915_flip_request(intel_crtc->plane, obj);
6500
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006501 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006502
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006503cleanup_pending:
6504 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson05394f32010-11-08 19:18:58 +00006505 drm_gem_object_unreference(&work->old_fb_obj->base);
6506 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006507 mutex_unlock(&dev->struct_mutex);
6508
Chris Wilson79158102012-05-23 11:13:58 +01006509cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01006510 spin_lock_irqsave(&dev->event_lock, flags);
6511 intel_crtc->unpin_work = NULL;
6512 spin_unlock_irqrestore(&dev->event_lock, flags);
6513
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006514 drm_vblank_put(dev, intel_crtc->pipe);
6515free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01006516 kfree(work);
6517
6518 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006519}
6520
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006521static void intel_sanitize_modesetting(struct drm_device *dev,
6522 int pipe, int plane)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 u32 reg, val;
Daniel Vettera9dcf842012-05-13 22:29:25 +02006526 int i;
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006527
Chris Wilsonf47166d2012-03-22 15:00:50 +00006528 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vettera9dcf842012-05-13 22:29:25 +02006529 for_each_pipe(i) {
6530 reg = PIPECONF(i);
Chris Wilsonf47166d2012-03-22 15:00:50 +00006531 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6532 }
6533
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006534 if (HAS_PCH_SPLIT(dev))
6535 return;
6536
6537 /* Who knows what state these registers were left in by the BIOS or
6538 * grub?
6539 *
6540 * If we leave the registers in a conflicting state (e.g. with the
6541 * display plane reading from the other pipe than the one we intend
6542 * to use) then when we attempt to teardown the active mode, we will
6543 * not disable the pipes and planes in the correct order -- leaving
6544 * a plane reading from a disabled pipe and possibly leading to
6545 * undefined behaviour.
6546 */
6547
6548 reg = DSPCNTR(plane);
6549 val = I915_READ(reg);
6550
6551 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6552 return;
6553 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6554 return;
6555
6556 /* This display plane is active and attached to the other CPU pipe. */
6557 pipe = !pipe;
6558
6559 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006560 intel_disable_plane(dev_priv, plane, pipe);
6561 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006562}
Jesse Barnes79e53942008-11-07 14:24:08 -08006563
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006564static void intel_crtc_reset(struct drm_crtc *crtc)
6565{
6566 struct drm_device *dev = crtc->dev;
6567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6568
6569 /* Reset flags back to the 'unknown' status so that they
6570 * will be correctly set on the initial modeset.
6571 */
6572 intel_crtc->dpms_mode = -1;
6573
6574 /* We need to fix up any BIOS configuration that conflicts with
6575 * our expectations.
6576 */
6577 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6578}
6579
6580static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006581 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6582 .load_lut = intel_crtc_load_lut,
6583 .disable = intel_crtc_disable,
6584};
6585
Daniel Vetter50f56112012-07-02 09:35:43 +02006586static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6587 struct drm_crtc *crtc)
6588{
6589 struct drm_device *dev;
6590 struct drm_crtc *tmp;
6591 int crtc_mask = 1;
6592
6593 WARN(!crtc, "checking null crtc?\n");
6594
6595 dev = crtc->dev;
6596
6597 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6598 if (tmp == crtc)
6599 break;
6600 crtc_mask <<= 1;
6601 }
6602
6603 if (encoder->possible_crtcs & crtc_mask)
6604 return true;
6605 return false;
6606}
6607
6608static int
6609intel_crtc_helper_disable(struct drm_crtc *crtc)
6610{
6611 struct drm_device *dev = crtc->dev;
6612 struct drm_connector *connector;
6613 struct drm_encoder *encoder;
6614
6615 /* Decouple all encoders and their attached connectors from this crtc */
6616 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6617 if (encoder->crtc != crtc)
6618 continue;
6619
6620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6621 if (connector->encoder != encoder)
6622 continue;
6623
6624 connector->encoder = NULL;
6625 }
6626 }
6627
6628 drm_helper_disable_unused_functions(dev);
6629 return 0;
6630}
6631
Daniel Vettera6778b32012-07-02 09:56:42 +02006632static void
Daniel Vettera6778b32012-07-02 09:56:42 +02006633intel_crtc_prepare_encoders(struct drm_device *dev)
6634{
Daniel Vetter821112a2012-07-02 10:16:35 +02006635 struct intel_encoder *encoder;
Daniel Vettera6778b32012-07-02 09:56:42 +02006636
Daniel Vetter821112a2012-07-02 10:16:35 +02006637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
Daniel Vettera6778b32012-07-02 09:56:42 +02006638 /* Disable unused encoders */
Daniel Vetter821112a2012-07-02 10:16:35 +02006639 if (encoder->base.crtc == NULL)
6640 encoder->disable(encoder);
Daniel Vettera6778b32012-07-02 09:56:42 +02006641 }
6642}
6643
6644bool intel_set_mode(struct drm_crtc *crtc,
6645 struct drm_display_mode *mode,
6646 int x, int y, struct drm_framebuffer *old_fb)
6647{
6648 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02006649 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vettera6778b32012-07-02 09:56:42 +02006650 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
Daniel Vettera6778b32012-07-02 09:56:42 +02006651 struct drm_encoder_helper_funcs *encoder_funcs;
6652 int saved_x, saved_y;
6653 struct drm_encoder *encoder;
6654 bool ret = true;
6655
6656 crtc->enabled = drm_helper_crtc_in_use(crtc);
6657 if (!crtc->enabled)
6658 return true;
6659
6660 adjusted_mode = drm_mode_duplicate(dev, mode);
6661 if (!adjusted_mode)
6662 return false;
6663
6664 saved_hwmode = crtc->hwmode;
6665 saved_mode = crtc->mode;
6666 saved_x = crtc->x;
6667 saved_y = crtc->y;
6668
6669 /* Update crtc values up front so the driver can rely on them for mode
6670 * setting.
6671 */
6672 crtc->mode = *mode;
6673 crtc->x = x;
6674 crtc->y = y;
6675
6676 /* Pass our mode to the connectors and the CRTC to give them a chance to
6677 * adjust it according to limitations or connector properties, and also
6678 * a chance to reject the mode entirely.
6679 */
6680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6681
6682 if (encoder->crtc != crtc)
6683 continue;
6684 encoder_funcs = encoder->helper_private;
6685 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6686 adjusted_mode))) {
6687 DRM_DEBUG_KMS("Encoder fixup failed\n");
6688 goto done;
6689 }
6690 }
6691
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02006692 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
Daniel Vettera6778b32012-07-02 09:56:42 +02006693 DRM_DEBUG_KMS("CRTC fixup failed\n");
6694 goto done;
6695 }
6696 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6697
Daniel Vettera6778b32012-07-02 09:56:42 +02006698 intel_crtc_prepare_encoders(dev);
6699
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02006700 dev_priv->display.crtc_disable(crtc);
Daniel Vettera6778b32012-07-02 09:56:42 +02006701
6702 /* Set up the DPLL and any encoders state that needs to adjust or depend
6703 * on the DPLL.
6704 */
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02006705 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
Daniel Vettera6778b32012-07-02 09:56:42 +02006706 if (!ret)
6707 goto done;
6708
6709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6710
6711 if (encoder->crtc != crtc)
6712 continue;
6713
6714 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6715 encoder->base.id, drm_get_encoder_name(encoder),
6716 mode->base.id, mode->name);
6717 encoder_funcs = encoder->helper_private;
6718 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6719 }
6720
6721 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02006722 dev_priv->display.crtc_enable(crtc);
Daniel Vettera6778b32012-07-02 09:56:42 +02006723
Daniel Vettera6778b32012-07-02 09:56:42 +02006724 /* Store real post-adjustment hardware mode. */
6725 crtc->hwmode = *adjusted_mode;
6726
6727 /* Calculate and store various constants which
6728 * are later needed by vblank and swap-completion
6729 * timestamping. They are derived from true hwmode.
6730 */
6731 drm_calc_timestamping_constants(crtc);
6732
6733 /* FIXME: add subpixel order */
6734done:
6735 drm_mode_destroy(dev, adjusted_mode);
6736 if (!ret) {
6737 crtc->hwmode = saved_hwmode;
6738 crtc->mode = saved_mode;
6739 crtc->x = saved_x;
6740 crtc->y = saved_y;
6741 }
6742
6743 return ret;
6744}
6745
Daniel Vetter50f56112012-07-02 09:35:43 +02006746static int intel_crtc_set_config(struct drm_mode_set *set)
6747{
6748 struct drm_device *dev;
6749 struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6750 struct drm_encoder *save_encoders, *new_encoder, *encoder;
6751 struct drm_framebuffer *old_fb = NULL;
6752 bool mode_changed = false; /* if true do a full mode set */
6753 bool fb_changed = false; /* if true and !mode_changed just do a flip */
6754 struct drm_connector *save_connectors, *connector;
Daniel Vetter6d832d12012-07-02 10:45:45 +02006755 int count = 0, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02006756 struct drm_mode_set save_set;
6757 int ret;
6758 int i;
6759
6760 DRM_DEBUG_KMS("\n");
6761
6762 if (!set)
6763 return -EINVAL;
6764
6765 if (!set->crtc)
6766 return -EINVAL;
6767
6768 if (!set->crtc->helper_private)
6769 return -EINVAL;
6770
Daniel Vetter50f56112012-07-02 09:35:43 +02006771 if (!set->mode)
6772 set->fb = NULL;
6773
6774 if (set->fb) {
6775 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6776 set->crtc->base.id, set->fb->base.id,
6777 (int)set->num_connectors, set->x, set->y);
6778 } else {
6779 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6780 return intel_crtc_helper_disable(set->crtc);
6781 }
6782
6783 dev = set->crtc->dev;
6784
6785 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6786 * connector data. */
6787 save_crtcs = kzalloc(dev->mode_config.num_crtc *
6788 sizeof(struct drm_crtc), GFP_KERNEL);
6789 if (!save_crtcs)
6790 return -ENOMEM;
6791
6792 save_encoders = kzalloc(dev->mode_config.num_encoder *
6793 sizeof(struct drm_encoder), GFP_KERNEL);
6794 if (!save_encoders) {
6795 kfree(save_crtcs);
6796 return -ENOMEM;
6797 }
6798
6799 save_connectors = kzalloc(dev->mode_config.num_connector *
6800 sizeof(struct drm_connector), GFP_KERNEL);
6801 if (!save_connectors) {
6802 kfree(save_crtcs);
6803 kfree(save_encoders);
6804 return -ENOMEM;
6805 }
6806
6807 /* Copy data. Note that driver private data is not affected.
6808 * Should anything bad happen only the expected state is
6809 * restored, not the drivers personal bookkeeping.
6810 */
6811 count = 0;
6812 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6813 save_crtcs[count++] = *crtc;
6814 }
6815
6816 count = 0;
6817 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6818 save_encoders[count++] = *encoder;
6819 }
6820
6821 count = 0;
6822 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6823 save_connectors[count++] = *connector;
6824 }
6825
6826 save_set.crtc = set->crtc;
6827 save_set.mode = &set->crtc->mode;
6828 save_set.x = set->crtc->x;
6829 save_set.y = set->crtc->y;
6830 save_set.fb = set->crtc->fb;
6831
6832 /* We should be able to check here if the fb has the same properties
6833 * and then just flip_or_move it */
6834 if (set->crtc->fb != set->fb) {
6835 /* If we have no fb then treat it as a full mode set */
6836 if (set->crtc->fb == NULL) {
6837 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6838 mode_changed = true;
6839 } else if (set->fb == NULL) {
6840 mode_changed = true;
6841 } else if (set->fb->depth != set->crtc->fb->depth) {
6842 mode_changed = true;
6843 } else if (set->fb->bits_per_pixel !=
6844 set->crtc->fb->bits_per_pixel) {
6845 mode_changed = true;
6846 } else
6847 fb_changed = true;
6848 }
6849
6850 if (set->x != set->crtc->x || set->y != set->crtc->y)
6851 fb_changed = true;
6852
6853 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6854 DRM_DEBUG_KMS("modes are different, full mode set\n");
6855 drm_mode_debug_printmodeline(&set->crtc->mode);
6856 drm_mode_debug_printmodeline(set->mode);
6857 mode_changed = true;
6858 }
6859
6860 /* a) traverse passed in connector list and get encoders for them */
6861 count = 0;
6862 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter50f56112012-07-02 09:35:43 +02006863 new_encoder = connector->encoder;
6864 for (ro = 0; ro < set->num_connectors; ro++) {
6865 if (set->connectors[ro] == connector) {
Daniel Vetter6d832d12012-07-02 10:45:45 +02006866 new_encoder =
6867 &intel_attached_encoder(connector)->base;
Daniel Vetter50f56112012-07-02 09:35:43 +02006868 break;
6869 }
6870 }
6871
6872 if (new_encoder != connector->encoder) {
6873 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6874 mode_changed = true;
6875 /* If the encoder is reused for another connector, then
6876 * the appropriate crtc will be set later.
6877 */
6878 if (connector->encoder)
6879 connector->encoder->crtc = NULL;
6880 connector->encoder = new_encoder;
6881 }
6882 }
6883
Daniel Vetter50f56112012-07-02 09:35:43 +02006884 count = 0;
6885 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6886 if (!connector->encoder)
6887 continue;
6888
6889 if (connector->encoder->crtc == set->crtc)
6890 new_crtc = NULL;
6891 else
6892 new_crtc = connector->encoder->crtc;
6893
6894 for (ro = 0; ro < set->num_connectors; ro++) {
6895 if (set->connectors[ro] == connector)
6896 new_crtc = set->crtc;
6897 }
6898
6899 /* Make sure the new CRTC will work with the encoder */
6900 if (new_crtc &&
6901 !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6902 ret = -EINVAL;
6903 goto fail;
6904 }
6905 if (new_crtc != connector->encoder->crtc) {
6906 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6907 mode_changed = true;
6908 connector->encoder->crtc = new_crtc;
6909 }
6910 if (new_crtc) {
6911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6912 connector->base.id, drm_get_connector_name(connector),
6913 new_crtc->base.id);
6914 } else {
6915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6916 connector->base.id, drm_get_connector_name(connector));
6917 }
6918 }
6919
Daniel Vetter50f56112012-07-02 09:35:43 +02006920 if (mode_changed) {
6921 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6922 if (set->crtc->enabled) {
6923 DRM_DEBUG_KMS("attempting to set mode from"
6924 " userspace\n");
6925 drm_mode_debug_printmodeline(set->mode);
6926 old_fb = set->crtc->fb;
6927 set->crtc->fb = set->fb;
Daniel Vettera6778b32012-07-02 09:56:42 +02006928 if (!intel_set_mode(set->crtc, set->mode,
6929 set->x, set->y, old_fb)) {
Daniel Vetter50f56112012-07-02 09:35:43 +02006930 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6931 set->crtc->base.id);
6932 set->crtc->fb = old_fb;
6933 ret = -EINVAL;
6934 goto fail;
6935 }
6936 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6937 for (i = 0; i < set->num_connectors; i++) {
6938 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6939 drm_get_connector_name(set->connectors[i]));
6940 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6941 }
6942 }
6943 drm_helper_disable_unused_functions(dev);
6944 } else if (fb_changed) {
6945 set->crtc->x = set->x;
6946 set->crtc->y = set->y;
6947
6948 old_fb = set->crtc->fb;
6949 if (set->crtc->fb != set->fb)
6950 set->crtc->fb = set->fb;
Daniel Vetter4f660f42012-07-02 09:47:37 +02006951 ret = intel_pipe_set_base(set->crtc,
6952 set->x, set->y, old_fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02006953 if (ret != 0) {
6954 set->crtc->fb = old_fb;
6955 goto fail;
6956 }
6957 }
6958
6959 kfree(save_connectors);
6960 kfree(save_encoders);
6961 kfree(save_crtcs);
6962 return 0;
6963
6964fail:
6965 /* Restore all previous data. */
6966 count = 0;
6967 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6968 *crtc = save_crtcs[count++];
6969 }
6970
6971 count = 0;
6972 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6973 *encoder = save_encoders[count++];
6974 }
6975
6976 count = 0;
6977 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6978 *connector = save_connectors[count++];
6979 }
6980
6981 /* Try to restore the config */
6982 if (mode_changed &&
Daniel Vettera6778b32012-07-02 09:56:42 +02006983 !intel_set_mode(save_set.crtc, save_set.mode,
6984 save_set.x, save_set.y, save_set.fb))
Daniel Vetter50f56112012-07-02 09:35:43 +02006985 DRM_ERROR("failed to restore config after modeset failure\n");
6986
6987 kfree(save_connectors);
6988 kfree(save_encoders);
6989 kfree(save_crtcs);
6990 return ret;
6991}
6992
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006993static const struct drm_crtc_funcs intel_crtc_funcs = {
6994 .reset = intel_crtc_reset,
6995 .cursor_set = intel_crtc_cursor_set,
6996 .cursor_move = intel_crtc_cursor_move,
6997 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02006998 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006999 .destroy = intel_crtc_destroy,
7000 .page_flip = intel_crtc_page_flip,
7001};
7002
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007003static void intel_pch_pll_init(struct drm_device *dev)
7004{
7005 drm_i915_private_t *dev_priv = dev->dev_private;
7006 int i;
7007
7008 if (dev_priv->num_pch_pll == 0) {
7009 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7010 return;
7011 }
7012
7013 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7014 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7015 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7016 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7017 }
7018}
7019
Hannes Ederb358d0a2008-12-18 21:18:47 +01007020static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08007021{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007022 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007023 struct intel_crtc *intel_crtc;
7024 int i;
7025
7026 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7027 if (intel_crtc == NULL)
7028 return;
7029
7030 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7031
7032 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08007033 for (i = 0; i < 256; i++) {
7034 intel_crtc->lut_r[i] = i;
7035 intel_crtc->lut_g[i] = i;
7036 intel_crtc->lut_b[i] = i;
7037 }
7038
Jesse Barnes80824002009-09-10 15:28:06 -07007039 /* Swap pipes & planes for FBC on pre-965 */
7040 intel_crtc->pipe = pipe;
7041 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01007042 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007043 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01007044 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07007045 }
7046
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007047 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7048 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7049 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7050 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7051
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00007052 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00007053 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes5a354202011-06-24 12:19:22 -07007054 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07007055
Jesse Barnes79e53942008-11-07 14:24:08 -08007056 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08007057}
7058
Carl Worth08d7b3d2009-04-29 14:43:54 -07007059int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00007060 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07007061{
Carl Worth08d7b3d2009-04-29 14:43:54 -07007062 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02007063 struct drm_mode_object *drmmode_obj;
7064 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007065
Daniel Vetter1cff8f62012-04-24 09:55:08 +02007066 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7067 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007068
Daniel Vetterc05422d2009-08-11 16:05:30 +02007069 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7070 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07007071
Daniel Vetterc05422d2009-08-11 16:05:30 +02007072 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07007073 DRM_ERROR("no such CRTC id\n");
7074 return -EINVAL;
7075 }
7076
Daniel Vetterc05422d2009-08-11 16:05:30 +02007077 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7078 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007079
Daniel Vetterc05422d2009-08-11 16:05:30 +02007080 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007081}
7082
Daniel Vetter66a92782012-07-12 20:08:18 +02007083static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08007084{
Daniel Vetter66a92782012-07-12 20:08:18 +02007085 struct drm_device *dev = encoder->base.dev;
7086 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007087 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007088 int entry = 0;
7089
Daniel Vetter66a92782012-07-12 20:08:18 +02007090 list_for_each_entry(source_encoder,
7091 &dev->mode_config.encoder_list, base.head) {
7092
7093 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08007094 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02007095
7096 /* Intel hw has only one MUX where enocoders could be cloned. */
7097 if (encoder->cloneable && source_encoder->cloneable)
7098 index_mask |= (1 << entry);
7099
Jesse Barnes79e53942008-11-07 14:24:08 -08007100 entry++;
7101 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01007102
Jesse Barnes79e53942008-11-07 14:24:08 -08007103 return index_mask;
7104}
7105
Chris Wilson4d302442010-12-14 19:21:29 +00007106static bool has_edp_a(struct drm_device *dev)
7107{
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109
7110 if (!IS_MOBILE(dev))
7111 return false;
7112
7113 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7114 return false;
7115
7116 if (IS_GEN5(dev) &&
7117 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7118 return false;
7119
7120 return true;
7121}
7122
Jesse Barnes79e53942008-11-07 14:24:08 -08007123static void intel_setup_outputs(struct drm_device *dev)
7124{
Eric Anholt725e30a2009-01-22 13:01:02 -08007125 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007126 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007127 bool dpd_is_edp = false;
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00007128 bool has_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08007129
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00007130 has_lvds = intel_lvds_init(dev);
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007131 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7132 /* disable the panel fitter on everything but LVDS */
7133 I915_WRITE(PFIT_CONTROL, 0);
7134 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007135
Eric Anholtbad720f2009-10-22 16:11:14 -07007136 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007137 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007138
Chris Wilson4d302442010-12-14 19:21:29 +00007139 if (has_edp_a(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007140 intel_dp_init(dev, DP_A, PORT_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08007141
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007142 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007143 intel_dp_init(dev, PCH_DP_D, PORT_D);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007144 }
7145
7146 intel_crt_init(dev);
7147
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03007148 if (IS_HASWELL(dev)) {
7149 int found;
7150
7151 /* Haswell uses DDI functions to detect digital outputs */
7152 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7153 /* DDI A only supports eDP */
7154 if (found)
7155 intel_ddi_init(dev, PORT_A);
7156
7157 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7158 * register */
7159 found = I915_READ(SFUSE_STRAP);
7160
7161 if (found & SFUSE_STRAP_DDIB_DETECTED)
7162 intel_ddi_init(dev, PORT_B);
7163 if (found & SFUSE_STRAP_DDIC_DETECTED)
7164 intel_ddi_init(dev, PORT_C);
7165 if (found & SFUSE_STRAP_DDID_DETECTED)
7166 intel_ddi_init(dev, PORT_D);
7167 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007168 int found;
7169
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007170 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08007171 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01007172 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007173 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007174 intel_hdmi_init(dev, HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007175 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007176 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007177 }
7178
7179 if (I915_READ(HDMIC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007180 intel_hdmi_init(dev, HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007181
Jesse Barnesb708a1d2012-06-11 14:39:56 -04007182 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007183 intel_hdmi_init(dev, HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007184
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007185 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007186 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007187
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007188 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007189 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007190 } else if (IS_VALLEYVIEW(dev)) {
7191 int found;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007192
Jesse Barnes4a87d652012-06-15 11:55:16 -07007193 if (I915_READ(SDVOB) & PORT_DETECTED) {
7194 /* SDVOB multiplex with HDMIB */
7195 found = intel_sdvo_init(dev, SDVOB, true);
7196 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007197 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007198 if (!found && (I915_READ(DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007199 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007200 }
7201
7202 if (I915_READ(SDVOC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02007203 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnes4a87d652012-06-15 11:55:16 -07007204
7205 /* Shares lanes with HDMI on SDVOC */
7206 if (I915_READ(DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007207 intel_dp_init(dev, DP_C, PORT_C);
Zhenyu Wang103a1962009-11-27 11:44:36 +08007208 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08007209 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08007210
Eric Anholt725e30a2009-01-22 13:01:02 -08007211 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007212 DRM_DEBUG_KMS("probing SDVOB\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01007213 found = intel_sdvo_init(dev, SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007214 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7215 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02007216 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007217 }
Ma Ling27185ae2009-08-24 13:50:23 +08007218
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007219 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7220 DRM_DEBUG_KMS("probing DP_B\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007221 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007222 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007223 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007224
7225 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007226
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007227 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7228 DRM_DEBUG_KMS("probing SDVOC\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01007229 found = intel_sdvo_init(dev, SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007230 }
Ma Ling27185ae2009-08-24 13:50:23 +08007231
7232 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7233
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007234 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7235 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02007236 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007237 }
7238 if (SUPPORTS_INTEGRATED_DP(dev)) {
7239 DRM_DEBUG_KMS("probing DP_C\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007240 intel_dp_init(dev, DP_C, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007241 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007242 }
Ma Ling27185ae2009-08-24 13:50:23 +08007243
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007244 if (SUPPORTS_INTEGRATED_DP(dev) &&
7245 (I915_READ(DP_D) & DP_DETECTED)) {
7246 DRM_DEBUG_KMS("probing DP_D\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03007247 intel_dp_init(dev, DP_D, PORT_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007248 }
Eric Anholtbad720f2009-10-22 16:11:14 -07007249 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007250 intel_dvo_init(dev);
7251
Zhenyu Wang103a1962009-11-27 11:44:36 +08007252 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007253 intel_tv_init(dev);
7254
Chris Wilson4ef69c72010-09-09 15:14:28 +01007255 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7256 encoder->base.possible_crtcs = encoder->crtc_mask;
7257 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02007258 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08007259 }
Chris Wilson47356eb2011-01-11 17:06:04 +00007260
Chris Wilson2c7111d2011-03-29 10:40:27 +01007261 /* disable all the possible outputs/crtcs before entering KMS mode */
7262 drm_helper_disable_unused_functions(dev);
Keith Packard9fb526d2011-09-26 22:24:57 -07007263
Paulo Zanoni40579ab2012-07-03 15:57:33 -03007264 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Keith Packard9fb526d2011-09-26 22:24:57 -07007265 ironlake_init_pch_refclk(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007266}
7267
7268static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7269{
7270 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08007271
7272 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007273 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007274
7275 kfree(intel_fb);
7276}
7277
7278static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00007279 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08007280 unsigned int *handle)
7281{
7282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007283 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007284
Chris Wilson05394f32010-11-08 19:18:58 +00007285 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08007286}
7287
7288static const struct drm_framebuffer_funcs intel_fb_funcs = {
7289 .destroy = intel_user_framebuffer_destroy,
7290 .create_handle = intel_user_framebuffer_create_handle,
7291};
7292
Dave Airlie38651672010-03-30 05:34:13 +00007293int intel_framebuffer_init(struct drm_device *dev,
7294 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007295 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00007296 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08007297{
Jesse Barnes79e53942008-11-07 14:24:08 -08007298 int ret;
7299
Chris Wilson05394f32010-11-08 19:18:58 +00007300 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01007301 return -EINVAL;
7302
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007303 if (mode_cmd->pitches[0] & 63)
Chris Wilson57cd6502010-08-08 12:34:44 +01007304 return -EINVAL;
7305
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007306 switch (mode_cmd->pixel_format) {
Ville Syrjälä04b39242011-11-17 18:05:13 +02007307 case DRM_FORMAT_RGB332:
7308 case DRM_FORMAT_RGB565:
7309 case DRM_FORMAT_XRGB8888:
Jesse Barnesb250da72012-03-07 08:49:29 -08007310 case DRM_FORMAT_XBGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02007311 case DRM_FORMAT_ARGB8888:
7312 case DRM_FORMAT_XRGB2101010:
7313 case DRM_FORMAT_ARGB2101010:
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007314 /* RGB formats are common across chipsets */
Jesse Barnesb5626742011-06-24 12:19:27 -07007315 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02007316 case DRM_FORMAT_YUYV:
7317 case DRM_FORMAT_UYVY:
7318 case DRM_FORMAT_YVYU:
7319 case DRM_FORMAT_VYUY:
Chris Wilson57cd6502010-08-08 12:34:44 +01007320 break;
7321 default:
Eugeni Dodonovaca25842012-01-17 15:25:45 -02007322 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7323 mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01007324 return -EINVAL;
7325 }
7326
Jesse Barnes79e53942008-11-07 14:24:08 -08007327 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7328 if (ret) {
7329 DRM_ERROR("framebuffer init failed %d\n", ret);
7330 return ret;
7331 }
7332
7333 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08007334 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007335 return 0;
7336}
7337
Jesse Barnes79e53942008-11-07 14:24:08 -08007338static struct drm_framebuffer *
7339intel_user_framebuffer_create(struct drm_device *dev,
7340 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007341 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08007342{
Chris Wilson05394f32010-11-08 19:18:58 +00007343 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007344
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007345 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7346 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00007347 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01007348 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08007349
Chris Wilsond2dff872011-04-19 08:36:26 +01007350 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08007351}
7352
Jesse Barnes79e53942008-11-07 14:24:08 -08007353static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08007354 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00007355 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08007356};
7357
Jesse Barnese70236a2009-09-21 10:42:27 -07007358/* Set up chip specific display functions */
7359static void intel_init_display(struct drm_device *dev)
7360{
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362
7363 /* We always want a DPMS function */
Eric Anholtf564048e2011-03-30 13:01:02 -07007364 if (HAS_PCH_SPLIT(dev)) {
Eric Anholtf564048e2011-03-30 13:01:02 -07007365 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02007366 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7367 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007368 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07007369 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07007370 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07007371 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02007372 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7373 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007374 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07007375 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07007376 }
Jesse Barnese70236a2009-09-21 10:42:27 -07007377
Jesse Barnese70236a2009-09-21 10:42:27 -07007378 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07007379 if (IS_VALLEYVIEW(dev))
7380 dev_priv->display.get_display_clock_speed =
7381 valleyview_get_display_clock_speed;
7382 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07007383 dev_priv->display.get_display_clock_speed =
7384 i945_get_display_clock_speed;
7385 else if (IS_I915G(dev))
7386 dev_priv->display.get_display_clock_speed =
7387 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007388 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007389 dev_priv->display.get_display_clock_speed =
7390 i9xx_misc_get_display_clock_speed;
7391 else if (IS_I915GM(dev))
7392 dev_priv->display.get_display_clock_speed =
7393 i915gm_get_display_clock_speed;
7394 else if (IS_I865G(dev))
7395 dev_priv->display.get_display_clock_speed =
7396 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02007397 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007398 dev_priv->display.get_display_clock_speed =
7399 i855_get_display_clock_speed;
7400 else /* 852, 830 */
7401 dev_priv->display.get_display_clock_speed =
7402 i830_get_display_clock_speed;
7403
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007404 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01007405 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07007406 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08007407 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08007408 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07007409 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08007410 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07007411 } else if (IS_IVYBRIDGE(dev)) {
7412 /* FIXME: detect B0+ stepping and use auto training */
7413 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08007414 dev_priv->display.write_eld = ironlake_write_eld;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03007415 } else if (IS_HASWELL(dev)) {
7416 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08007417 dev_priv->display.write_eld = haswell_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007418 } else
7419 dev_priv->display.update_wm = NULL;
Jesse Barnes6067aae2011-04-28 15:04:31 -07007420 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08007421 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07007422 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007423
7424 /* Default just returns -ENODEV to indicate unsupported */
7425 dev_priv->display.queue_flip = intel_default_queue_flip;
7426
7427 switch (INTEL_INFO(dev)->gen) {
7428 case 2:
7429 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7430 break;
7431
7432 case 3:
7433 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7434 break;
7435
7436 case 4:
7437 case 5:
7438 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7439 break;
7440
7441 case 6:
7442 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7443 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007444 case 7:
7445 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7446 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007447 }
Jesse Barnese70236a2009-09-21 10:42:27 -07007448}
7449
Jesse Barnesb690e962010-07-19 13:53:12 -07007450/*
7451 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7452 * resume, or other times. This quirk makes sure that's the case for
7453 * affected systems.
7454 */
Akshay Joshi0206e352011-08-16 15:34:10 -04007455static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07007456{
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458
7459 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02007460 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07007461}
7462
Keith Packard435793d2011-07-12 14:56:22 -07007463/*
7464 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7465 */
7466static void quirk_ssc_force_disable(struct drm_device *dev)
7467{
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02007470 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07007471}
7472
Carsten Emde4dca20e2012-03-15 15:56:26 +01007473/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01007474 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7475 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01007476 */
7477static void quirk_invert_brightness(struct drm_device *dev)
7478{
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02007481 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07007482}
7483
7484struct intel_quirk {
7485 int device;
7486 int subsystem_vendor;
7487 int subsystem_device;
7488 void (*hook)(struct drm_device *dev);
7489};
7490
Ben Widawskyc43b5632012-04-16 14:07:40 -07007491static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07007492 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04007493 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07007494
Jesse Barnesb690e962010-07-19 13:53:12 -07007495 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7496 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7497
Jesse Barnesb690e962010-07-19 13:53:12 -07007498 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7499 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7500
7501 /* 855 & before need to leave pipe A & dpll A up */
7502 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7503 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02007504 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07007505
7506 /* Lenovo U160 cannot use SSC on LVDS */
7507 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02007508
7509 /* Sony Vaio Y cannot use SSC on LVDS */
7510 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01007511
7512 /* Acer Aspire 5734Z must invert backlight brightness */
7513 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07007514};
7515
7516static void intel_init_quirks(struct drm_device *dev)
7517{
7518 struct pci_dev *d = dev->pdev;
7519 int i;
7520
7521 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7522 struct intel_quirk *q = &intel_quirks[i];
7523
7524 if (d->device == q->device &&
7525 (d->subsystem_vendor == q->subsystem_vendor ||
7526 q->subsystem_vendor == PCI_ANY_ID) &&
7527 (d->subsystem_device == q->subsystem_device ||
7528 q->subsystem_device == PCI_ANY_ID))
7529 q->hook(dev);
7530 }
7531}
7532
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007533/* Disable the VGA plane that we never use */
7534static void i915_disable_vga(struct drm_device *dev)
7535{
7536 struct drm_i915_private *dev_priv = dev->dev_private;
7537 u8 sr1;
7538 u32 vga_reg;
7539
7540 if (HAS_PCH_SPLIT(dev))
7541 vga_reg = CPU_VGACNTRL;
7542 else
7543 vga_reg = VGACNTRL;
7544
7545 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07007546 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007547 sr1 = inb(VGA_SR_DATA);
7548 outb(sr1 | 1<<5, VGA_SR_DATA);
7549 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7550 udelay(300);
7551
7552 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7553 POSTING_READ(vga_reg);
7554}
7555
Daniel Vetterf8175862012-04-10 15:50:11 +02007556void intel_modeset_init_hw(struct drm_device *dev)
7557{
Eugeni Dodonov0232e922012-07-06 15:42:36 -03007558 /* We attempt to init the necessary power wells early in the initialization
7559 * time, so the subsystems that expect power to be enabled can work.
7560 */
7561 intel_init_power_wells(dev);
7562
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03007563 intel_prepare_ddi(dev);
7564
Daniel Vetterf8175862012-04-10 15:50:11 +02007565 intel_init_clock_gating(dev);
7566
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02007567 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02007568 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02007569 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02007570}
7571
Jesse Barnes79e53942008-11-07 14:24:08 -08007572void intel_modeset_init(struct drm_device *dev)
7573{
Jesse Barnes652c3932009-08-17 13:31:43 -07007574 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007575 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007576
7577 drm_mode_config_init(dev);
7578
7579 dev->mode_config.min_width = 0;
7580 dev->mode_config.min_height = 0;
7581
Dave Airlie019d96c2011-09-29 16:20:42 +01007582 dev->mode_config.preferred_depth = 24;
7583 dev->mode_config.prefer_shadow = 1;
7584
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02007585 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08007586
Jesse Barnesb690e962010-07-19 13:53:12 -07007587 intel_init_quirks(dev);
7588
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007589 intel_init_pm(dev);
7590
Jesse Barnese70236a2009-09-21 10:42:27 -07007591 intel_init_display(dev);
7592
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007593 if (IS_GEN2(dev)) {
7594 dev->mode_config.max_width = 2048;
7595 dev->mode_config.max_height = 2048;
7596 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07007597 dev->mode_config.max_width = 4096;
7598 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08007599 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007600 dev->mode_config.max_width = 8192;
7601 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08007602 }
Daniel Vetterdd2757f2012-06-07 15:55:57 +02007603 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
Jesse Barnes79e53942008-11-07 14:24:08 -08007604
Zhao Yakui28c97732009-10-09 11:39:41 +08007605 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10007606 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08007607
Dave Airliea3524f12010-06-06 18:59:41 +10007608 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007609 intel_crtc_init(dev, i);
Jesse Barnes00c2064b2012-01-13 15:48:39 -08007610 ret = intel_plane_init(dev, i);
7611 if (ret)
7612 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08007613 }
7614
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007615 intel_pch_pll_init(dev);
7616
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007617 /* Just disable it once at startup */
7618 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007619 intel_setup_outputs(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01007620}
7621
7622void intel_modeset_gem_init(struct drm_device *dev)
7623{
Chris Wilson1833b132012-05-09 11:56:28 +01007624 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02007625
7626 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007627}
7628
7629void intel_modeset_cleanup(struct drm_device *dev)
7630{
Jesse Barnes652c3932009-08-17 13:31:43 -07007631 struct drm_i915_private *dev_priv = dev->dev_private;
7632 struct drm_crtc *crtc;
7633 struct intel_crtc *intel_crtc;
7634
Keith Packardf87ea762010-10-03 19:36:26 -07007635 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007636 mutex_lock(&dev->struct_mutex);
7637
Jesse Barnes723bfd72010-10-07 16:01:13 -07007638 intel_unregister_dsm_handler();
7639
7640
Jesse Barnes652c3932009-08-17 13:31:43 -07007641 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7642 /* Skip inactive CRTCs */
7643 if (!crtc->fb)
7644 continue;
7645
7646 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02007647 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007648 }
7649
Chris Wilson973d04f2011-07-08 12:22:37 +01007650 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07007651
Daniel Vetter8090c6b2012-06-24 16:42:32 +02007652 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00007653
Daniel Vetter930ebb42012-06-29 23:32:16 +02007654 ironlake_teardown_rc6(dev);
7655
Jesse Barnes57f350b2012-03-28 13:39:25 -07007656 if (IS_VALLEYVIEW(dev))
7657 vlv_init_dpio(dev);
7658
Kristian Høgsberg69341a52009-11-11 12:19:17 -05007659 mutex_unlock(&dev->struct_mutex);
7660
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007661 /* Disable the irq before mode object teardown, for the irq might
7662 * enqueue unpin/hotplug work. */
7663 drm_irq_uninstall(dev);
7664 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02007665 cancel_work_sync(&dev_priv->rps.work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007666
Chris Wilson1630fe72011-07-08 12:22:42 +01007667 /* flush any delayed tasks or pending work */
7668 flush_scheduled_work();
7669
Jesse Barnes79e53942008-11-07 14:24:08 -08007670 drm_mode_config_cleanup(dev);
7671}
7672
Dave Airlie28d52042009-09-21 14:33:58 +10007673/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08007674 * Return which encoder is currently attached for connector.
7675 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01007676struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08007677{
Chris Wilsondf0e9242010-09-09 16:20:55 +01007678 return &intel_attached_encoder(connector)->base;
7679}
Jesse Barnes79e53942008-11-07 14:24:08 -08007680
Chris Wilsondf0e9242010-09-09 16:20:55 +01007681void intel_connector_attach_encoder(struct intel_connector *connector,
7682 struct intel_encoder *encoder)
7683{
7684 connector->encoder = encoder;
7685 drm_mode_connector_attach_encoder(&connector->base,
7686 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007687}
Dave Airlie28d52042009-09-21 14:33:58 +10007688
7689/*
7690 * set vga decode state - true == enable VGA decode
7691 */
7692int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7693{
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 u16 gmch_ctrl;
7696
7697 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7698 if (state)
7699 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7700 else
7701 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7702 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7703 return 0;
7704}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007705
7706#ifdef CONFIG_DEBUG_FS
7707#include <linux/seq_file.h>
7708
7709struct intel_display_error_state {
7710 struct intel_cursor_error_state {
7711 u32 control;
7712 u32 position;
7713 u32 base;
7714 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +01007715 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007716
7717 struct intel_pipe_error_state {
7718 u32 conf;
7719 u32 source;
7720
7721 u32 htotal;
7722 u32 hblank;
7723 u32 hsync;
7724 u32 vtotal;
7725 u32 vblank;
7726 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +01007727 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007728
7729 struct intel_plane_error_state {
7730 u32 control;
7731 u32 stride;
7732 u32 size;
7733 u32 pos;
7734 u32 addr;
7735 u32 surface;
7736 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +01007737 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007738};
7739
7740struct intel_display_error_state *
7741intel_display_capture_error_state(struct drm_device *dev)
7742{
Akshay Joshi0206e352011-08-16 15:34:10 -04007743 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007744 struct intel_display_error_state *error;
7745 int i;
7746
7747 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7748 if (error == NULL)
7749 return NULL;
7750
Damien Lespiau52331302012-08-15 19:23:25 +01007751 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007752 error->cursor[i].control = I915_READ(CURCNTR(i));
7753 error->cursor[i].position = I915_READ(CURPOS(i));
7754 error->cursor[i].base = I915_READ(CURBASE(i));
7755
7756 error->plane[i].control = I915_READ(DSPCNTR(i));
7757 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7758 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04007759 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007760 error->plane[i].addr = I915_READ(DSPADDR(i));
7761 if (INTEL_INFO(dev)->gen >= 4) {
7762 error->plane[i].surface = I915_READ(DSPSURF(i));
7763 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7764 }
7765
7766 error->pipe[i].conf = I915_READ(PIPECONF(i));
7767 error->pipe[i].source = I915_READ(PIPESRC(i));
7768 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7769 error->pipe[i].hblank = I915_READ(HBLANK(i));
7770 error->pipe[i].hsync = I915_READ(HSYNC(i));
7771 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7772 error->pipe[i].vblank = I915_READ(VBLANK(i));
7773 error->pipe[i].vsync = I915_READ(VSYNC(i));
7774 }
7775
7776 return error;
7777}
7778
7779void
7780intel_display_print_error_state(struct seq_file *m,
7781 struct drm_device *dev,
7782 struct intel_display_error_state *error)
7783{
Damien Lespiau52331302012-08-15 19:23:25 +01007784 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007785 int i;
7786
Damien Lespiau52331302012-08-15 19:23:25 +01007787 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7788 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007789 seq_printf(m, "Pipe [%d]:\n", i);
7790 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7791 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7792 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7793 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7794 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7795 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7796 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7797 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7798
7799 seq_printf(m, "Plane [%d]:\n", i);
7800 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7801 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7802 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7803 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7804 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7805 if (INTEL_INFO(dev)->gen >= 4) {
7806 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7807 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7808 }
7809
7810 seq_printf(m, "Cursor [%d]:\n", i);
7811 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7812 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7813 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7814 }
7815}
7816#endif