blob: 2fbc3da06c2926050a443ad7e4bbe252545a3d8f [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070032#include <linux/vgaarb.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070037#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100038#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080039
40#include "drm_crtc_helper.h"
41
Zhenyu Wang32f9d652009-07-24 01:00:32 +080042#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
Jesse Barnes79e53942008-11-07 14:24:08 -080044bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080045static void intel_update_watermarks(struct drm_device *dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +020046static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010047static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080048
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080071typedef struct intel_limit intel_limit_t;
72struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080073 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080075 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
Jesse Barnes79e53942008-11-07 14:24:08 -080078
79#define I8XX_DOT_MIN 25000
80#define I8XX_DOT_MAX 350000
81#define I8XX_VCO_MIN 930000
82#define I8XX_VCO_MAX 1400000
83#define I8XX_N_MIN 3
84#define I8XX_N_MAX 16
85#define I8XX_M_MIN 96
86#define I8XX_M_MAX 140
87#define I8XX_M1_MIN 18
88#define I8XX_M1_MAX 26
89#define I8XX_M2_MIN 6
90#define I8XX_M2_MAX 16
91#define I8XX_P_MIN 4
92#define I8XX_P_MAX 128
93#define I8XX_P1_MIN 2
94#define I8XX_P1_MAX 33
95#define I8XX_P1_LVDS_MIN 1
96#define I8XX_P1_LVDS_MAX 6
97#define I8XX_P2_SLOW 4
98#define I8XX_P2_FAST 2
99#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +0800100#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -0800101#define I8XX_P2_SLOW_LIMIT 165000
102
103#define I9XX_DOT_MIN 20000
104#define I9XX_DOT_MAX 400000
105#define I9XX_VCO_MIN 1400000
106#define I9XX_VCO_MAX 2800000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500107#define PINEVIEW_VCO_MIN 1700000
108#define PINEVIEW_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500109#define I9XX_N_MIN 1
110#define I9XX_N_MAX 6
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500111/* Pineview's Ncounter is a ring counter */
112#define PINEVIEW_N_MIN 3
113#define PINEVIEW_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800114#define I9XX_M_MIN 70
115#define I9XX_M_MAX 120
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500116#define PINEVIEW_M_MIN 2
117#define PINEVIEW_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800118#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500119#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800120#define I9XX_M2_MIN 5
121#define I9XX_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500122/* Pineview M1 is reserved, and must be 0 */
123#define PINEVIEW_M1_MIN 0
124#define PINEVIEW_M1_MAX 0
125#define PINEVIEW_M2_MIN 0
126#define PINEVIEW_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800127#define I9XX_P_SDVO_DAC_MIN 5
128#define I9XX_P_SDVO_DAC_MAX 80
129#define I9XX_P_LVDS_MIN 7
130#define I9XX_P_LVDS_MAX 98
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500131#define PINEVIEW_P_LVDS_MIN 7
132#define PINEVIEW_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800133#define I9XX_P1_MIN 1
134#define I9XX_P1_MAX 8
135#define I9XX_P2_SDVO_DAC_SLOW 10
136#define I9XX_P2_SDVO_DAC_FAST 5
137#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138#define I9XX_P2_LVDS_SLOW 14
139#define I9XX_P2_LVDS_FAST 7
140#define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
Ma Ling044c7c42009-03-18 20:13:23 +0800142/*The parameter is for SDVO on G4x platform*/
143#define G4X_DOT_SDVO_MIN 25000
144#define G4X_DOT_SDVO_MAX 270000
145#define G4X_VCO_MIN 1750000
146#define G4X_VCO_MAX 3500000
147#define G4X_N_SDVO_MIN 1
148#define G4X_N_SDVO_MAX 4
149#define G4X_M_SDVO_MIN 104
150#define G4X_M_SDVO_MAX 138
151#define G4X_M1_SDVO_MIN 17
152#define G4X_M1_SDVO_MAX 23
153#define G4X_M2_SDVO_MIN 5
154#define G4X_M2_SDVO_MAX 11
155#define G4X_P_SDVO_MIN 10
156#define G4X_P_SDVO_MAX 30
157#define G4X_P1_SDVO_MIN 1
158#define G4X_P1_SDVO_MAX 3
159#define G4X_P2_SDVO_SLOW 10
160#define G4X_P2_SDVO_FAST 10
161#define G4X_P2_SDVO_LIMIT 270000
162
163/*The parameter is for HDMI_DAC on G4x platform*/
164#define G4X_DOT_HDMI_DAC_MIN 22000
165#define G4X_DOT_HDMI_DAC_MAX 400000
166#define G4X_N_HDMI_DAC_MIN 1
167#define G4X_N_HDMI_DAC_MAX 4
168#define G4X_M_HDMI_DAC_MIN 104
169#define G4X_M_HDMI_DAC_MAX 138
170#define G4X_M1_HDMI_DAC_MIN 16
171#define G4X_M1_HDMI_DAC_MAX 23
172#define G4X_M2_HDMI_DAC_MIN 5
173#define G4X_M2_HDMI_DAC_MAX 11
174#define G4X_P_HDMI_DAC_MIN 5
175#define G4X_P_HDMI_DAC_MAX 80
176#define G4X_P1_HDMI_DAC_MIN 1
177#define G4X_P1_HDMI_DAC_MAX 8
178#define G4X_P2_HDMI_DAC_SLOW 10
179#define G4X_P2_HDMI_DAC_FAST 5
180#define G4X_P2_HDMI_DAC_LIMIT 165000
181
182/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700220/*The parameter is for DISPLAY PORT on G4x platform*/
221#define G4X_DOT_DISPLAY_PORT_MIN 161670
222#define G4X_DOT_DISPLAY_PORT_MAX 227000
223#define G4X_N_DISPLAY_PORT_MIN 1
224#define G4X_N_DISPLAY_PORT_MAX 2
225#define G4X_M_DISPLAY_PORT_MIN 97
226#define G4X_M_DISPLAY_PORT_MAX 108
227#define G4X_M1_DISPLAY_PORT_MIN 0x10
228#define G4X_M1_DISPLAY_PORT_MAX 0x12
229#define G4X_M2_DISPLAY_PORT_MIN 0x05
230#define G4X_M2_DISPLAY_PORT_MAX 0x06
231#define G4X_P_DISPLAY_PORT_MIN 10
232#define G4X_P_DISPLAY_PORT_MAX 20
233#define G4X_P1_DISPLAY_PORT_MIN 1
234#define G4X_P1_DISPLAY_PORT_MAX 2
235#define G4X_P2_DISPLAY_PORT_SLOW 10
236#define G4X_P2_DISPLAY_PORT_FAST 10
237#define G4X_P2_DISPLAY_PORT_LIMIT 0
238
Eric Anholtbad720f2009-10-22 16:11:14 -0700239/* Ironlake / Sandybridge */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800240/* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243#define IRONLAKE_DOT_MIN 25000
244#define IRONLAKE_DOT_MAX 350000
245#define IRONLAKE_VCO_MIN 1760000
246#define IRONLAKE_VCO_MAX 3510000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500247#define IRONLAKE_M1_MIN 12
Zhao Yakuia59e3852010-01-06 22:05:57 +0800248#define IRONLAKE_M1_MAX 22
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500249#define IRONLAKE_M2_MIN 5
250#define IRONLAKE_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500251#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800252
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800253/* We have parameter ranges for different type of outputs. */
254
255/* DAC & HDMI Refclk 120Mhz */
256#define IRONLAKE_DAC_N_MIN 1
257#define IRONLAKE_DAC_N_MAX 5
258#define IRONLAKE_DAC_M_MIN 79
259#define IRONLAKE_DAC_M_MAX 127
260#define IRONLAKE_DAC_P_MIN 5
261#define IRONLAKE_DAC_P_MAX 80
262#define IRONLAKE_DAC_P1_MIN 1
263#define IRONLAKE_DAC_P1_MAX 8
264#define IRONLAKE_DAC_P2_SLOW 10
265#define IRONLAKE_DAC_P2_FAST 5
266
267/* LVDS single-channel 120Mhz refclk */
268#define IRONLAKE_LVDS_S_N_MIN 1
269#define IRONLAKE_LVDS_S_N_MAX 3
270#define IRONLAKE_LVDS_S_M_MIN 79
271#define IRONLAKE_LVDS_S_M_MAX 118
272#define IRONLAKE_LVDS_S_P_MIN 28
273#define IRONLAKE_LVDS_S_P_MAX 112
274#define IRONLAKE_LVDS_S_P1_MIN 2
275#define IRONLAKE_LVDS_S_P1_MAX 8
276#define IRONLAKE_LVDS_S_P2_SLOW 14
277#define IRONLAKE_LVDS_S_P2_FAST 14
278
279/* LVDS dual-channel 120Mhz refclk */
280#define IRONLAKE_LVDS_D_N_MIN 1
281#define IRONLAKE_LVDS_D_N_MAX 3
282#define IRONLAKE_LVDS_D_M_MIN 79
283#define IRONLAKE_LVDS_D_M_MAX 127
284#define IRONLAKE_LVDS_D_P_MIN 14
285#define IRONLAKE_LVDS_D_P_MAX 56
286#define IRONLAKE_LVDS_D_P1_MIN 2
287#define IRONLAKE_LVDS_D_P1_MAX 8
288#define IRONLAKE_LVDS_D_P2_SLOW 7
289#define IRONLAKE_LVDS_D_P2_FAST 7
290
291/* LVDS single-channel 100Mhz refclk */
292#define IRONLAKE_LVDS_S_SSC_N_MIN 1
293#define IRONLAKE_LVDS_S_SSC_N_MAX 2
294#define IRONLAKE_LVDS_S_SSC_M_MIN 79
295#define IRONLAKE_LVDS_S_SSC_M_MAX 126
296#define IRONLAKE_LVDS_S_SSC_P_MIN 28
297#define IRONLAKE_LVDS_S_SSC_P_MAX 112
298#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303/* LVDS dual-channel 100Mhz refclk */
304#define IRONLAKE_LVDS_D_SSC_N_MIN 1
305#define IRONLAKE_LVDS_D_SSC_N_MAX 3
306#define IRONLAKE_LVDS_D_SSC_M_MIN 79
307#define IRONLAKE_LVDS_D_SSC_M_MAX 126
308#define IRONLAKE_LVDS_D_SSC_P_MIN 14
309#define IRONLAKE_LVDS_D_SSC_P_MAX 42
310#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315/* DisplayPort */
316#define IRONLAKE_DP_N_MIN 1
317#define IRONLAKE_DP_N_MAX 2
318#define IRONLAKE_DP_M_MIN 81
319#define IRONLAKE_DP_M_MAX 90
320#define IRONLAKE_DP_P_MIN 10
321#define IRONLAKE_DP_P_MAX 20
322#define IRONLAKE_DP_P2_FAST 10
323#define IRONLAKE_DP_P2_SLOW 10
324#define IRONLAKE_DP_P2_LIMIT 0
325#define IRONLAKE_DP_P1_MIN 1
326#define IRONLAKE_DP_P1_MAX 2
Zhao Yakui45476682009-12-31 16:06:04 +0800327
Jesse Barnes2377b742010-07-07 14:06:43 -0700328/* FDI */
329#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
Ma Lingd4906092009-03-18 20:13:27 +0800331static bool
332intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334static bool
335intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800337
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700338static bool
339intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800341static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500342intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700344
Chris Wilson021357a2010-09-07 20:54:59 +0100345static inline u32 /* units of 100MHz */
346intel_fdi_link_freq(struct drm_device *dev)
347{
Chris Wilson8b99e682010-10-13 09:59:17 +0100348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100353}
354
Keith Packarde4b36692009-06-05 19:22:17 -0700355static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800366 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700367};
368
369static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800380 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700381};
382
383static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800394 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700395};
396
397static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800411 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700412};
413
Ma Ling044c7c42009-03-18 20:13:23 +0800414 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700415static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
Ma Lingd4906092009-03-18 20:13:27 +0800428 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700429};
430
431static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
Ma Lingd4906092009-03-18 20:13:27 +0800444 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700445};
446
447static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
Ma Lingd4906092009-03-18 20:13:27 +0800468 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700469};
470
471static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
Ma Lingd4906092009-03-18 20:13:27 +0800492 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700493};
494
495static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700516};
517
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500518static const intel_limit_t intel_limits_pineview_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800529 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700530};
531
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500532static const intel_limit_t intel_limits_pineview_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500541 /* Pineview only supports single-channel mode. */
Shaohua Li21778322009-02-23 15:19:16 +0800542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800544 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700545};
546
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800547static const intel_limit_t intel_limits_ironlake_dac = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800559 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700560};
561
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800562static const intel_limit_t intel_limits_ironlake_single_lvds = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575};
576
577static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590};
591
592static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605};
606
607static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800619 .find_pll = intel_g4x_find_best_PLL,
620};
621
622static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
Zhao Yakui45476682009-12-31 16:06:04 +0800631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800642 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800643};
644
Chris Wilson1b894b52010-12-14 20:04:54 +0000645static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800647{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800650 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000656 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000661 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800669 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800670 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800671
672 return limit;
673}
674
Ma Ling044c7c42009-03-18 20:13:23 +0800675static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676{
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700685 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800686 else
687 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700688 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700691 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700693 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700695 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800696 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700697 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800698
699 return limit;
700}
701
Chris Wilson1b894b52010-12-14 20:04:54 +0000702static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800703{
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
Eric Anholtbad720f2009-10-22 16:11:14 -0700707 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000708 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800709 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800710 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500711 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500713 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800714 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500715 limit = &intel_limits_pineview_sdvo;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700723 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800724 else
Keith Packarde4b36692009-06-05 19:22:17 -0700725 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800726 }
727 return limit;
728}
729
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500730/* m1 is reserved as 0 in Pineview, n is a ring counter */
731static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800732{
Shaohua Li21778322009-02-23 15:19:16 +0800733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737}
738
739static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800743 return;
744 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749}
750
Jesse Barnes79e53942008-11-07 14:24:08 -0800751/**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100754bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800755{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800759
Chris Wilson4ef69c72010-09-09 15:14:28 +0100760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800765}
766
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800767#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800768/**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
Chris Wilson1b894b52010-12-14 20:04:54 +0000773static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800776{
Jesse Barnes79e53942008-11-07 14:24:08 -0800777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800}
801
Ma Lingd4906092009-03-18 20:13:27 +0800802static bool
803intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
Jesse Barnes79e53942008-11-07 14:24:08 -0800806{
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800810 int err = target;
811
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800813 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
Zhao Yakui42158662009-11-20 11:24:18 +0800834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800845 int this_err;
846
Shaohua Li21778322009-02-23 15:19:16 +0800847 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863}
864
Ma Lingd4906092009-03-18 20:13:27 +0800865static bool
866intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868{
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800879 int lvds_reg;
880
Eric Anholtc619eed2010-01-28 16:45:52 -0800881 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200899 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200901 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
Shaohua Li21778322009-02-23 15:19:16 +0800910 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800913 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000914
915 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800926 return found;
927}
Ma Lingd4906092009-03-18 20:13:27 +0800928
Zhenyu Wang2c072452009-06-05 15:38:42 +0800929static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500930intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800932{
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800935
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952}
953
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700954/* DisplayPort has only two frequencies, 162MHz and 270MHz */
955static bool
956intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958{
Chris Wilson5eddb702010-09-11 13:48:45 +0100959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700979}
980
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700981/**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800990{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993
Chris Wilson300387c2010-09-05 20:25:43 +0100994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001010 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +01001011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015}
1016
Keith Packardab7ad7f2010-10-03 00:33:06 -07001017/*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001032 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001033 */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001034void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001037
Keith Packardab7ad7f2010-10-03 00:33:06 -07001038 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001039 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001040
Keith Packardab7ad7f2010-10-03 00:33:06 -07001041 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -07001044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001047 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001052 last_line = I915_READ(reg) & DSL_LINEMASK;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001053 mdelay(5);
Chris Wilson58e10eb2010-10-03 10:56:11 +01001054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001059}
1060
Jesse Barnesb24e7172011-01-04 15:09:30 -08001061static const char *state_string(bool enabled)
1062{
1063 return enabled ? "on" : "off";
1064}
1065
1066/* Only for pre-ILK configs */
1067static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1069{
1070 int reg;
1071 u32 val;
1072 bool cur_state;
1073
1074 reg = DPLL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1080}
1081#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
Jesse Barnes040484a2011-01-03 12:14:26 -08001084/* For ILK+ */
1085static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087{
1088 int reg;
1089 u32 val;
1090 bool cur_state;
1091
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1098}
1099#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1115}
1116#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
1133#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137 enum pipe pipe)
1138{
1139 int reg;
1140 u32 val;
1141
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1144 return;
1145
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149}
1150
1151static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152 enum pipe pipe)
1153{
1154 int reg;
1155 u32 val;
1156
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160}
1161
Jesse Barnesea0760c2011-01-04 15:09:32 -08001162static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int pp_reg, lvds_reg;
1166 u32 val;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1169
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1173 } else {
1174 pp_reg = PP_CONTROL;
1175 lvds_reg = LVDS;
1176 }
1177
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181 locked = false;
1182
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
1188 pipe ? 'B' : 'A');
1189}
1190
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001191static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001193{
1194 int reg;
1195 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001196 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001197
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
1203 pipe ? 'B' : 'A', state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001204}
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001205#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001207
1208static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209 enum plane plane)
1210{
1211 int reg;
1212 u32 val;
1213
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
1218 plane ? 'B' : 'A');
1219}
1220
1221static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
1223{
1224 int reg, i;
1225 u32 val;
1226 int cur_pipe;
1227
1228 /* Need to check both planes against the pipe */
1229 for (i = 0; i < 2; i++) {
1230 reg = DSPCNTR(i);
1231 val = I915_READ(reg);
1232 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1233 DISPPLANE_SEL_PIPE_SHIFT;
1234 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1235 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1236 i, pipe ? 'B' : 'A');
1237 }
1238}
1239
Jesse Barnes92f25842011-01-04 15:09:34 -08001240static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1241{
1242 u32 val;
1243 bool enabled;
1244
1245 val = I915_READ(PCH_DREF_CONTROL);
1246 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1247 DREF_SUPERSPREAD_SOURCE_MASK));
1248 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1249}
1250
1251static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe)
1253{
1254 int reg;
1255 u32 val;
1256 bool enabled;
1257
1258 reg = TRANSCONF(pipe);
1259 val = I915_READ(reg);
1260 enabled = !!(val & TRANS_ENABLE);
1261 WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A');
1262}
1263
Jesse Barnesb24e7172011-01-04 15:09:30 -08001264/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001265 * intel_enable_pll - enable a PLL
1266 * @dev_priv: i915 private structure
1267 * @pipe: pipe PLL to enable
1268 *
1269 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1270 * make sure the PLL reg is writable first though, since the panel write
1271 * protect mechanism may be enabled.
1272 *
1273 * Note! This is for pre-ILK only.
1274 */
1275static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1276{
1277 int reg;
1278 u32 val;
1279
1280 /* No really, not for ILK+ */
1281 BUG_ON(dev_priv->info->gen >= 5);
1282
1283 /* PLL is protected by panel, make sure we can write it */
1284 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1285 assert_panel_unlocked(dev_priv, pipe);
1286
1287 reg = DPLL(pipe);
1288 val = I915_READ(reg);
1289 val |= DPLL_VCO_ENABLE;
1290
1291 /* We do this three times for luck */
1292 I915_WRITE(reg, val);
1293 POSTING_READ(reg);
1294 udelay(150); /* wait for warmup */
1295 I915_WRITE(reg, val);
1296 POSTING_READ(reg);
1297 udelay(150); /* wait for warmup */
1298 I915_WRITE(reg, val);
1299 POSTING_READ(reg);
1300 udelay(150); /* wait for warmup */
1301}
1302
1303/**
1304 * intel_disable_pll - disable a PLL
1305 * @dev_priv: i915 private structure
1306 * @pipe: pipe PLL to disable
1307 *
1308 * Disable the PLL for @pipe, making sure the pipe is off first.
1309 *
1310 * Note! This is for pre-ILK only.
1311 */
1312static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313{
1314 int reg;
1315 u32 val;
1316
1317 /* Don't disable pipe A or pipe A PLLs if needed */
1318 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1319 return;
1320
1321 /* Make sure the pipe isn't still relying on us */
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1324 reg = DPLL(pipe);
1325 val = I915_READ(reg);
1326 val &= ~DPLL_VCO_ENABLE;
1327 I915_WRITE(reg, val);
1328 POSTING_READ(reg);
1329}
1330
1331/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001332 * intel_enable_pch_pll - enable PCH PLL
1333 * @dev_priv: i915 private structure
1334 * @pipe: pipe PLL to enable
1335 *
1336 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1337 * drives the transcoder clock.
1338 */
1339static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 /* PCH only available on ILK+ */
1346 BUG_ON(dev_priv->info->gen < 5);
1347
1348 /* PCH refclock must be enabled first */
1349 assert_pch_refclk_enabled(dev_priv);
1350
1351 reg = PCH_DPLL(pipe);
1352 val = I915_READ(reg);
1353 val |= DPLL_VCO_ENABLE;
1354 I915_WRITE(reg, val);
1355 POSTING_READ(reg);
1356 udelay(200);
1357}
1358
1359static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1360 enum pipe pipe)
1361{
1362 int reg;
1363 u32 val;
1364
1365 /* PCH only available on ILK+ */
1366 BUG_ON(dev_priv->info->gen < 5);
1367
1368 /* Make sure transcoder isn't still depending on us */
1369 assert_transcoder_disabled(dev_priv, pipe);
1370
1371 reg = PCH_DPLL(pipe);
1372 val = I915_READ(reg);
1373 val &= ~DPLL_VCO_ENABLE;
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(200);
1377}
1378
Jesse Barnes040484a2011-01-03 12:14:26 -08001379static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1380 enum pipe pipe)
1381{
1382 int reg;
1383 u32 val;
1384
1385 /* PCH only available on ILK+ */
1386 BUG_ON(dev_priv->info->gen < 5);
1387
1388 /* Make sure PCH DPLL is enabled */
1389 assert_pch_pll_enabled(dev_priv, pipe);
1390
1391 /* FDI must be feeding us bits for PCH ports */
1392 assert_fdi_tx_enabled(dev_priv, pipe);
1393 assert_fdi_rx_enabled(dev_priv, pipe);
1394
1395 reg = TRANSCONF(pipe);
1396 val = I915_READ(reg);
1397 /*
1398 * make the BPC in transcoder be consistent with
1399 * that in pipeconf reg.
1400 */
1401 val &= ~PIPE_BPC_MASK;
1402 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1403 I915_WRITE(reg, val | TRANS_ENABLE);
1404 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1405 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1406}
1407
1408static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1409 enum pipe pipe)
1410{
1411 int reg;
1412 u32 val;
1413
1414 /* FDI relies on the transcoder */
1415 assert_fdi_tx_disabled(dev_priv, pipe);
1416 assert_fdi_rx_disabled(dev_priv, pipe);
1417
1418 reg = TRANSCONF(pipe);
1419 val = I915_READ(reg);
1420 val &= ~TRANS_ENABLE;
1421 I915_WRITE(reg, val);
1422 /* wait for PCH transcoder off, transcoder state */
1423 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1424 DRM_ERROR("failed to disable transcoder\n");
1425}
1426
Jesse Barnes92f25842011-01-04 15:09:34 -08001427/**
Jesse Barnesb24e7172011-01-04 15:09:30 -08001428 * intel_enable_pipe - enable a pipe, assertiing requirements
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001431 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001432 *
1433 * Enable @pipe, making sure that various hardware specific requirements
1434 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1435 *
1436 * @pipe should be %PIPE_A or %PIPE_B.
1437 *
1438 * Will wait until the pipe is actually running (i.e. first vblank) before
1439 * returning.
1440 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001441static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1442 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001443{
1444 int reg;
1445 u32 val;
1446
1447 /*
1448 * A pipe without a PLL won't actually be able to drive bits from
1449 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1450 * need the check.
1451 */
1452 if (!HAS_PCH_SPLIT(dev_priv->dev))
1453 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001454 else {
1455 if (pch_port) {
1456 /* if driving the PCH, we need FDI enabled */
1457 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1458 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1459 }
1460 /* FIXME: assert CPU port conditions for SNB+ */
1461 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001462
1463 reg = PIPECONF(pipe);
1464 val = I915_READ(reg);
1465 val |= PIPECONF_ENABLE;
1466 I915_WRITE(reg, val);
1467 POSTING_READ(reg);
1468 intel_wait_for_vblank(dev_priv->dev, pipe);
1469}
1470
1471/**
1472 * intel_disable_pipe - disable a pipe, assertiing requirements
1473 * @dev_priv: i915 private structure
1474 * @pipe: pipe to disable
1475 *
1476 * Disable @pipe, making sure that various hardware specific requirements
1477 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1478 *
1479 * @pipe should be %PIPE_A or %PIPE_B.
1480 *
1481 * Will wait until the pipe has shut down before returning.
1482 */
1483static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1484 enum pipe pipe)
1485{
1486 int reg;
1487 u32 val;
1488
1489 /*
1490 * Make sure planes won't keep trying to pump pixels to us,
1491 * or we might hang the display.
1492 */
1493 assert_planes_disabled(dev_priv, pipe);
1494
1495 /* Don't disable pipe A or pipe A PLLs if needed */
1496 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1497 return;
1498
1499 reg = PIPECONF(pipe);
1500 val = I915_READ(reg);
1501 val &= ~PIPECONF_ENABLE;
1502 I915_WRITE(reg, val);
1503 POSTING_READ(reg);
1504 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1505}
1506
1507/**
1508 * intel_enable_plane - enable a display plane on a given pipe
1509 * @dev_priv: i915 private structure
1510 * @plane: plane to enable
1511 * @pipe: pipe being fed
1512 *
1513 * Enable @plane on @pipe, making sure that @pipe is running first.
1514 */
1515static void intel_enable_plane(struct drm_i915_private *dev_priv,
1516 enum plane plane, enum pipe pipe)
1517{
1518 int reg;
1519 u32 val;
1520
1521 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1522 assert_pipe_enabled(dev_priv, pipe);
1523
1524 reg = DSPCNTR(plane);
1525 val = I915_READ(reg);
1526 val |= DISPLAY_PLANE_ENABLE;
1527 I915_WRITE(reg, val);
1528 POSTING_READ(reg);
1529 intel_wait_for_vblank(dev_priv->dev, pipe);
1530}
1531
1532/*
1533 * Plane regs are double buffered, going from enabled->disabled needs a
1534 * trigger in order to latch. The display address reg provides this.
1535 */
1536static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1537 enum plane plane)
1538{
1539 u32 reg = DSPADDR(plane);
1540 I915_WRITE(reg, I915_READ(reg));
1541}
1542
1543/**
1544 * intel_disable_plane - disable a display plane
1545 * @dev_priv: i915 private structure
1546 * @plane: plane to disable
1547 * @pipe: pipe consuming the data
1548 *
1549 * Disable @plane; should be an independent operation.
1550 */
1551static void intel_disable_plane(struct drm_i915_private *dev_priv,
1552 enum plane plane, enum pipe pipe)
1553{
1554 int reg;
1555 u32 val;
1556
1557 reg = DSPCNTR(plane);
1558 val = I915_READ(reg);
1559 val &= ~DISPLAY_PLANE_ENABLE;
1560 I915_WRITE(reg, val);
1561 POSTING_READ(reg);
1562 intel_flush_display_plane(dev_priv, plane);
1563 intel_wait_for_vblank(dev_priv->dev, pipe);
1564}
1565
Jesse Barnes80824002009-09-10 15:28:06 -07001566static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1567{
1568 struct drm_device *dev = crtc->dev;
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 struct drm_framebuffer *fb = crtc->fb;
1571 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001572 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes80824002009-09-10 15:28:06 -07001573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1574 int plane, i;
1575 u32 fbc_ctl, fbc_ctl2;
1576
Chris Wilsonbed4a672010-09-11 10:47:47 +01001577 if (fb->pitch == dev_priv->cfb_pitch &&
Chris Wilson05394f32010-11-08 19:18:58 +00001578 obj->fence_reg == dev_priv->cfb_fence &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001579 intel_crtc->plane == dev_priv->cfb_plane &&
1580 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1581 return;
1582
1583 i8xx_disable_fbc(dev);
1584
Jesse Barnes80824002009-09-10 15:28:06 -07001585 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1586
1587 if (fb->pitch < dev_priv->cfb_pitch)
1588 dev_priv->cfb_pitch = fb->pitch;
1589
1590 /* FBC_CTL wants 64B units */
1591 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001592 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes80824002009-09-10 15:28:06 -07001593 dev_priv->cfb_plane = intel_crtc->plane;
1594 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1595
1596 /* Clear old tags */
1597 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1598 I915_WRITE(FBC_TAG + (i * 4), 0);
1599
1600 /* Set it up... */
1601 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001602 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001603 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1604 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1605 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1606
1607 /* enable it... */
1608 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001609 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001610 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Jesse Barnes80824002009-09-10 15:28:06 -07001611 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1612 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
Chris Wilson05394f32010-11-08 19:18:58 +00001613 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001614 fbc_ctl |= dev_priv->cfb_fence;
1615 I915_WRITE(FBC_CONTROL, fbc_ctl);
1616
Zhao Yakui28c97732009-10-09 11:39:41 +08001617 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
Chris Wilson5eddb702010-09-11 13:48:45 +01001618 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
Jesse Barnes80824002009-09-10 15:28:06 -07001619}
1620
1621void i8xx_disable_fbc(struct drm_device *dev)
1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 u32 fbc_ctl;
1625
1626 /* Disable compression */
1627 fbc_ctl = I915_READ(FBC_CONTROL);
Chris Wilsona5cad622010-09-22 13:15:10 +01001628 if ((fbc_ctl & FBC_CTL_EN) == 0)
1629 return;
1630
Jesse Barnes80824002009-09-10 15:28:06 -07001631 fbc_ctl &= ~FBC_CTL_EN;
1632 I915_WRITE(FBC_CONTROL, fbc_ctl);
1633
1634 /* Wait for compressing bit to clear */
Chris Wilson481b6af2010-08-23 17:43:35 +01001635 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
Chris Wilson913d8d12010-08-07 11:01:35 +01001636 DRM_DEBUG_KMS("FBC idle timed out\n");
1637 return;
Jesse Barnes9517a922010-05-21 09:40:45 -07001638 }
Jesse Barnes80824002009-09-10 15:28:06 -07001639
Zhao Yakui28c97732009-10-09 11:39:41 +08001640 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001641}
1642
Adam Jacksonee5382a2010-04-23 11:17:39 -04001643static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001644{
Jesse Barnes80824002009-09-10 15:28:06 -07001645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1648}
1649
Jesse Barnes74dff282009-09-14 15:39:40 -07001650static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1651{
1652 struct drm_device *dev = crtc->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 struct drm_framebuffer *fb = crtc->fb;
1655 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001656 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes74dff282009-09-14 15:39:40 -07001657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001658 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Jesse Barnes74dff282009-09-14 15:39:40 -07001659 unsigned long stall_watermark = 200;
1660 u32 dpfc_ctl;
1661
Chris Wilsonbed4a672010-09-11 10:47:47 +01001662 dpfc_ctl = I915_READ(DPFC_CONTROL);
1663 if (dpfc_ctl & DPFC_CTL_EN) {
1664 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001665 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001666 dev_priv->cfb_plane == intel_crtc->plane &&
1667 dev_priv->cfb_y == crtc->y)
1668 return;
1669
1670 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1671 POSTING_READ(DPFC_CONTROL);
1672 intel_wait_for_vblank(dev, intel_crtc->pipe);
1673 }
1674
Jesse Barnes74dff282009-09-14 15:39:40 -07001675 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001676 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes74dff282009-09-14 15:39:40 -07001677 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001678 dev_priv->cfb_y = crtc->y;
Jesse Barnes74dff282009-09-14 15:39:40 -07001679
1680 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
Chris Wilson05394f32010-11-08 19:18:58 +00001681 if (obj->tiling_mode != I915_TILING_NONE) {
Jesse Barnes74dff282009-09-14 15:39:40 -07001682 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1683 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1684 } else {
1685 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1686 }
1687
Jesse Barnes74dff282009-09-14 15:39:40 -07001688 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1689 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1690 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1691 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1692
1693 /* enable it... */
1694 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1695
Zhao Yakui28c97732009-10-09 11:39:41 +08001696 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001697}
1698
1699void g4x_disable_fbc(struct drm_device *dev)
1700{
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 u32 dpfc_ctl;
1703
1704 /* Disable compression */
1705 dpfc_ctl = I915_READ(DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001706 if (dpfc_ctl & DPFC_CTL_EN) {
1707 dpfc_ctl &= ~DPFC_CTL_EN;
1708 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Jesse Barnes74dff282009-09-14 15:39:40 -07001709
Chris Wilsonbed4a672010-09-11 10:47:47 +01001710 DRM_DEBUG_KMS("disabled FBC\n");
1711 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001712}
1713
Adam Jacksonee5382a2010-04-23 11:17:39 -04001714static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001715{
Jesse Barnes74dff282009-09-14 15:39:40 -07001716 struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1719}
1720
Jesse Barnes4efe0702011-01-18 11:25:41 -08001721static void sandybridge_blit_fbc_update(struct drm_device *dev)
1722{
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 u32 blt_ecoskpd;
1725
1726 /* Make sure blitter notifies FBC of writes */
1727 __gen6_force_wake_get(dev_priv);
1728 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1729 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1730 GEN6_BLITTER_LOCK_SHIFT;
1731 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1732 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1733 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1734 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1735 GEN6_BLITTER_LOCK_SHIFT);
1736 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1737 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1738 __gen6_force_wake_put(dev_priv);
1739}
1740
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001741static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1742{
1743 struct drm_device *dev = crtc->dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 struct drm_framebuffer *fb = crtc->fb;
1746 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001747 struct drm_i915_gem_object *obj = intel_fb->obj;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001749 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001750 unsigned long stall_watermark = 200;
1751 u32 dpfc_ctl;
1752
Chris Wilsonbed4a672010-09-11 10:47:47 +01001753 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1754 if (dpfc_ctl & DPFC_CTL_EN) {
1755 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001756 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001757 dev_priv->cfb_plane == intel_crtc->plane &&
Chris Wilson05394f32010-11-08 19:18:58 +00001758 dev_priv->cfb_offset == obj->gtt_offset &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001759 dev_priv->cfb_y == crtc->y)
1760 return;
1761
1762 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1763 POSTING_READ(ILK_DPFC_CONTROL);
1764 intel_wait_for_vblank(dev, intel_crtc->pipe);
1765 }
1766
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001767 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001768 dev_priv->cfb_fence = obj->fence_reg;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001769 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001770 dev_priv->cfb_offset = obj->gtt_offset;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001771 dev_priv->cfb_y = crtc->y;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001772
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001773 dpfc_ctl &= DPFC_RESERVED;
1774 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
Chris Wilson05394f32010-11-08 19:18:58 +00001775 if (obj->tiling_mode != I915_TILING_NONE) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001776 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1777 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1778 } else {
1779 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1780 }
1781
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001782 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1783 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1784 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1785 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
Chris Wilson05394f32010-11-08 19:18:58 +00001786 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001787 /* enable it... */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001788 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001789
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001790 if (IS_GEN6(dev)) {
1791 I915_WRITE(SNB_DPFC_CTL_SA,
1792 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1793 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001794 sandybridge_blit_fbc_update(dev);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001795 }
1796
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001797 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1798}
1799
1800void ironlake_disable_fbc(struct drm_device *dev)
1801{
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 u32 dpfc_ctl;
1804
1805 /* Disable compression */
1806 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001807 if (dpfc_ctl & DPFC_CTL_EN) {
1808 dpfc_ctl &= ~DPFC_CTL_EN;
1809 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001810
Chris Wilsonbed4a672010-09-11 10:47:47 +01001811 DRM_DEBUG_KMS("disabled FBC\n");
1812 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001813}
1814
1815static bool ironlake_fbc_enabled(struct drm_device *dev)
1816{
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818
1819 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1820}
1821
Adam Jacksonee5382a2010-04-23 11:17:39 -04001822bool intel_fbc_enabled(struct drm_device *dev)
1823{
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825
1826 if (!dev_priv->display.fbc_enabled)
1827 return false;
1828
1829 return dev_priv->display.fbc_enabled(dev);
1830}
1831
1832void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1833{
1834 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1835
1836 if (!dev_priv->display.enable_fbc)
1837 return;
1838
1839 dev_priv->display.enable_fbc(crtc, interval);
1840}
1841
1842void intel_disable_fbc(struct drm_device *dev)
1843{
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845
1846 if (!dev_priv->display.disable_fbc)
1847 return;
1848
1849 dev_priv->display.disable_fbc(dev);
1850}
1851
Jesse Barnes80824002009-09-10 15:28:06 -07001852/**
1853 * intel_update_fbc - enable/disable FBC as needed
Chris Wilsonbed4a672010-09-11 10:47:47 +01001854 * @dev: the drm_device
Jesse Barnes80824002009-09-10 15:28:06 -07001855 *
1856 * Set up the framebuffer compression hardware at mode set time. We
1857 * enable it if possible:
1858 * - plane A only (on pre-965)
1859 * - no pixel mulitply/line duplication
1860 * - no alpha buffer discard
1861 * - no dual wide
1862 * - framebuffer <= 2048 in width, 1536 in height
1863 *
1864 * We can't assume that any compression will take place (worst case),
1865 * so the compressed buffer has to be the same size as the uncompressed
1866 * one. It also must reside (along with the line length buffer) in
1867 * stolen memory.
1868 *
1869 * We need to enable/disable FBC on a global basis.
1870 */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001871static void intel_update_fbc(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001872{
Jesse Barnes80824002009-09-10 15:28:06 -07001873 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001874 struct drm_crtc *crtc = NULL, *tmp_crtc;
1875 struct intel_crtc *intel_crtc;
1876 struct drm_framebuffer *fb;
Jesse Barnes80824002009-09-10 15:28:06 -07001877 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001878 struct drm_i915_gem_object *obj;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001879
1880 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001881
1882 if (!i915_powersave)
1883 return;
1884
Adam Jacksonee5382a2010-04-23 11:17:39 -04001885 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001886 return;
1887
Jesse Barnes80824002009-09-10 15:28:06 -07001888 /*
1889 * If FBC is already on, we just have to verify that we can
1890 * keep it that way...
1891 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001892 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001893 * - changing FBC params (stride, fence, mode)
1894 * - new fb is too large to fit in compressed buffer
1895 * - going to an unsupported config (interlace, pixel multiply, etc.)
1896 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001897 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001898 if (tmp_crtc->enabled) {
1899 if (crtc) {
1900 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1901 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1902 goto out_disable;
1903 }
1904 crtc = tmp_crtc;
1905 }
Jesse Barnes9c928d12010-07-23 15:20:00 -07001906 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001907
1908 if (!crtc || crtc->fb == NULL) {
1909 DRM_DEBUG_KMS("no output, disabling\n");
1910 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001911 goto out_disable;
1912 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001913
1914 intel_crtc = to_intel_crtc(crtc);
1915 fb = crtc->fb;
1916 intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001917 obj = intel_fb->obj;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001918
Chris Wilson05394f32010-11-08 19:18:58 +00001919 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001920 DRM_DEBUG_KMS("framebuffer too large, disabling "
Chris Wilson5eddb702010-09-11 13:48:45 +01001921 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001922 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001923 goto out_disable;
1924 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001925 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1926 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001927 DRM_DEBUG_KMS("mode incompatible with compression, "
Chris Wilson5eddb702010-09-11 13:48:45 +01001928 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001929 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001930 goto out_disable;
1931 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001932 if ((crtc->mode.hdisplay > 2048) ||
1933 (crtc->mode.vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001934 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001935 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001936 goto out_disable;
1937 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001938 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001939 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001940 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001941 goto out_disable;
1942 }
Chris Wilson05394f32010-11-08 19:18:58 +00001943 if (obj->tiling_mode != I915_TILING_X) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001944 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001945 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001946 goto out_disable;
1947 }
1948
Jason Wesselc924b932010-08-05 09:22:32 -05001949 /* If the kernel debugger is active, always disable compression */
1950 if (in_dbg_master())
1951 goto out_disable;
1952
Chris Wilsonbed4a672010-09-11 10:47:47 +01001953 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001954 return;
1955
1956out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001957 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001958 if (intel_fbc_enabled(dev)) {
1959 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001960 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001961 }
Jesse Barnes80824002009-09-10 15:28:06 -07001962}
1963
Chris Wilson127bd2a2010-07-23 23:32:05 +01001964int
Chris Wilson48b956c2010-09-14 12:50:34 +01001965intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001966 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001967 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001968{
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001969 u32 alignment;
1970 int ret;
1971
Chris Wilson05394f32010-11-08 19:18:58 +00001972 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001973 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001976 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
Daniel Vetter75e9e912010-11-04 17:11:09 +01001993 ret = i915_gem_object_pin(obj, alignment, true);
Chris Wilson48b956c2010-09-14 12:50:34 +01001994 if (ret)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001995 return ret;
1996
Chris Wilson48b956c2010-09-14 12:50:34 +01001997 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1998 if (ret)
1999 goto err_unpin;
Chris Wilson72133422010-09-13 23:56:38 +01002000
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002001 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2002 * fence, whereas 965+ only requires a fence if using
2003 * framebuffer compression. For simplicity, we always install
2004 * a fence as the cost is not that onerous.
2005 */
Chris Wilson05394f32010-11-08 19:18:58 +00002006 if (obj->tiling_mode != I915_TILING_NONE) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00002007 ret = i915_gem_object_get_fence(obj, pipelined, false);
Chris Wilson48b956c2010-09-14 12:50:34 +01002008 if (ret)
2009 goto err_unpin;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002010 }
2011
2012 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002013
2014err_unpin:
2015 i915_gem_object_unpin(obj);
2016 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002017}
2018
Jesse Barnes81255562010-08-02 12:07:50 -07002019/* Assume fb object is pinned & idle & fenced and just update base pointers */
2020static int
2021intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
Jason Wessel21c74a82010-10-13 14:09:44 -05002022 int x, int y, enum mode_set_atomic state)
Jesse Barnes81255562010-08-02 12:07:50 -07002023{
2024 struct drm_device *dev = crtc->dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002028 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002029 int plane = intel_crtc->plane;
2030 unsigned long Start, Offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002031 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002032 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002033
2034 switch (plane) {
2035 case 0:
2036 case 1:
2037 break;
2038 default:
2039 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2040 return -EINVAL;
2041 }
2042
2043 intel_fb = to_intel_framebuffer(fb);
2044 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002045
Chris Wilson5eddb702010-09-11 13:48:45 +01002046 reg = DSPCNTR(plane);
2047 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002048 /* Mask out pixel format bits in case we change it */
2049 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2050 switch (fb->bits_per_pixel) {
2051 case 8:
2052 dspcntr |= DISPPLANE_8BPP;
2053 break;
2054 case 16:
2055 if (fb->depth == 15)
2056 dspcntr |= DISPPLANE_15_16BPP;
2057 else
2058 dspcntr |= DISPPLANE_16BPP;
2059 break;
2060 case 24:
2061 case 32:
2062 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2063 break;
2064 default:
2065 DRM_ERROR("Unknown color depth\n");
2066 return -EINVAL;
2067 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002068 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002069 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002070 dspcntr |= DISPPLANE_TILED;
2071 else
2072 dspcntr &= ~DISPPLANE_TILED;
2073 }
2074
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002075 if (HAS_PCH_SPLIT(dev))
Jesse Barnes81255562010-08-02 12:07:50 -07002076 /* must disable */
2077 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2078
Chris Wilson5eddb702010-09-11 13:48:45 +01002079 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002080
Chris Wilson05394f32010-11-08 19:18:58 +00002081 Start = obj->gtt_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002082 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2083
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002084 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2085 Start, Offset, x, y, fb->pitch);
Chris Wilson5eddb702010-09-11 13:48:45 +01002086 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002087 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002088 I915_WRITE(DSPSURF(plane), Start);
2089 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2090 I915_WRITE(DSPADDR(plane), Offset);
2091 } else
2092 I915_WRITE(DSPADDR(plane), Start + Offset);
2093 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002094
Chris Wilsonbed4a672010-09-11 10:47:47 +01002095 intel_update_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002096 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002097
2098 return 0;
2099}
2100
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002101static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002102intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2103 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002104{
2105 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002106 struct drm_i915_master_private *master_priv;
2107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002108 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002109
2110 /* no fb bound */
2111 if (!crtc->fb) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002112 DRM_DEBUG_KMS("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002113 return 0;
2114 }
2115
Chris Wilson265db952010-09-20 15:41:01 +01002116 switch (intel_crtc->plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002117 case 0:
2118 case 1:
2119 break;
2120 default:
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002121 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002122 }
2123
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002124 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002125 ret = intel_pin_and_fence_fb_obj(dev,
2126 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002127 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002128 if (ret != 0) {
2129 mutex_unlock(&dev->struct_mutex);
2130 return ret;
2131 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002132
Chris Wilson265db952010-09-20 15:41:01 +01002133 if (old_fb) {
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002134 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00002135 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
Chris Wilson265db952010-09-20 15:41:01 +01002136
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002137 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002138 atomic_read(&obj->pending_flip) == 0);
Chris Wilson85345512010-11-13 09:49:11 +00002139
2140 /* Big Hammer, we also need to ensure that any pending
2141 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2142 * current scanout is retired before unpinning the old
2143 * framebuffer.
2144 */
Chris Wilson05394f32010-11-08 19:18:58 +00002145 ret = i915_gem_object_flush_gpu(obj, false);
Chris Wilson85345512010-11-13 09:49:11 +00002146 if (ret) {
2147 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2148 mutex_unlock(&dev->struct_mutex);
2149 return ret;
2150 }
Chris Wilson265db952010-09-20 15:41:01 +01002151 }
2152
Jason Wessel21c74a82010-10-13 14:09:44 -05002153 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2154 LEAVE_ATOMIC_MODE_SET);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002155 if (ret) {
Chris Wilson265db952010-09-20 15:41:01 +01002156 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002157 mutex_unlock(&dev->struct_mutex);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002158 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002159 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002160
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002161 if (old_fb) {
2162 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson265db952010-09-20 15:41:01 +01002163 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002164 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002165
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002166 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002167
2168 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002169 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002170
2171 master_priv = dev->primary->master->driver_priv;
2172 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002173 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002174
Chris Wilson265db952010-09-20 15:41:01 +01002175 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002176 master_priv->sarea_priv->pipeB_x = x;
2177 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002178 } else {
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002181 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002182
2183 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002184}
2185
Chris Wilson5eddb702010-09-11 13:48:45 +01002186static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002187{
2188 struct drm_device *dev = crtc->dev;
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 u32 dpa_ctl;
2191
Zhao Yakui28c97732009-10-09 11:39:41 +08002192 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002193 dpa_ctl = I915_READ(DP_A);
2194 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2195
2196 if (clock < 200000) {
2197 u32 temp;
2198 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2199 /* workaround for 160Mhz:
2200 1) program 0x4600c bits 15:0 = 0x8124
2201 2) program 0x46010 bit 0 = 1
2202 3) program 0x46034 bit 24 = 1
2203 4) program 0x64000 bit 14 = 1
2204 */
2205 temp = I915_READ(0x4600c);
2206 temp &= 0xffff0000;
2207 I915_WRITE(0x4600c, temp | 0x8124);
2208
2209 temp = I915_READ(0x46010);
2210 I915_WRITE(0x46010, temp | 1);
2211
2212 temp = I915_READ(0x46034);
2213 I915_WRITE(0x46034, temp | (1 << 24));
2214 } else {
2215 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2216 }
2217 I915_WRITE(DP_A, dpa_ctl);
2218
Chris Wilson5eddb702010-09-11 13:48:45 +01002219 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002220 udelay(500);
2221}
2222
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002223static void intel_fdi_normal_train(struct drm_crtc *crtc)
2224{
2225 struct drm_device *dev = crtc->dev;
2226 struct drm_i915_private *dev_priv = dev->dev_private;
2227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228 int pipe = intel_crtc->pipe;
2229 u32 reg, temp;
2230
2231 /* enable normal train */
2232 reg = FDI_TX_CTL(pipe);
2233 temp = I915_READ(reg);
2234 temp &= ~FDI_LINK_TRAIN_NONE;
2235 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2236 I915_WRITE(reg, temp);
2237
2238 reg = FDI_RX_CTL(pipe);
2239 temp = I915_READ(reg);
2240 if (HAS_PCH_CPT(dev)) {
2241 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2242 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2243 } else {
2244 temp &= ~FDI_LINK_TRAIN_NONE;
2245 temp |= FDI_LINK_TRAIN_NONE;
2246 }
2247 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2248
2249 /* wait one idle pattern time */
2250 POSTING_READ(reg);
2251 udelay(1000);
2252}
2253
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002254/* The FDI link training functions for ILK/Ibexpeak. */
2255static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2256{
2257 struct drm_device *dev = crtc->dev;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2260 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002261 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002262 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002263
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002264 /* FDI needs bits from pipe & plane first */
2265 assert_pipe_enabled(dev_priv, pipe);
2266 assert_plane_enabled(dev_priv, plane);
2267
Adam Jacksone1a44742010-06-25 15:32:14 -04002268 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2269 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002270 reg = FDI_RX_IMR(pipe);
2271 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002272 temp &= ~FDI_RX_SYMBOL_LOCK;
2273 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002274 I915_WRITE(reg, temp);
2275 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002276 udelay(150);
2277
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002278 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002279 reg = FDI_TX_CTL(pipe);
2280 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002281 temp &= ~(7 << 19);
2282 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002283 temp &= ~FDI_LINK_TRAIN_NONE;
2284 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002285 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002286
Chris Wilson5eddb702010-09-11 13:48:45 +01002287 reg = FDI_RX_CTL(pipe);
2288 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002289 temp &= ~FDI_LINK_TRAIN_NONE;
2290 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002291 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2292
2293 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002294 udelay(150);
2295
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002296 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002297 if (HAS_PCH_IBX(dev)) {
2298 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2299 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2300 FDI_RX_PHASE_SYNC_POINTER_EN);
2301 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002302
Chris Wilson5eddb702010-09-11 13:48:45 +01002303 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002304 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002305 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002306 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2307
2308 if ((temp & FDI_RX_BIT_LOCK)) {
2309 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002310 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002311 break;
2312 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002313 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002314 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002315 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002316
2317 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002322 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002323
Chris Wilson5eddb702010-09-11 13:48:45 +01002324 reg = FDI_RX_CTL(pipe);
2325 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002326 temp &= ~FDI_LINK_TRAIN_NONE;
2327 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002328 I915_WRITE(reg, temp);
2329
2330 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002331 udelay(150);
2332
Chris Wilson5eddb702010-09-11 13:48:45 +01002333 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002334 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002335 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002336 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2337
2338 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002339 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002340 DRM_DEBUG_KMS("FDI train 2 done.\n");
2341 break;
2342 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002343 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002344 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002345 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002346
2347 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002348
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002349}
2350
Chris Wilson311bd682011-01-13 19:06:50 +00002351static const int snb_b_fdi_train_param [] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002352 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2353 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2354 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2355 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2356};
2357
2358/* The FDI link training functions for SNB/Cougarpoint. */
2359static void gen6_fdi_link_train(struct drm_crtc *crtc)
2360{
2361 struct drm_device *dev = crtc->dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002365 u32 reg, temp, i;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002366
Adam Jacksone1a44742010-06-25 15:32:14 -04002367 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2368 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002369 reg = FDI_RX_IMR(pipe);
2370 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002371 temp &= ~FDI_RX_SYMBOL_LOCK;
2372 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002373 I915_WRITE(reg, temp);
2374
2375 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002376 udelay(150);
2377
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002378 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002381 temp &= ~(7 << 19);
2382 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_1;
2385 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2386 /* SNB-B */
2387 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002388 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002389
Chris Wilson5eddb702010-09-11 13:48:45 +01002390 reg = FDI_RX_CTL(pipe);
2391 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002392 if (HAS_PCH_CPT(dev)) {
2393 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2394 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2395 } else {
2396 temp &= ~FDI_LINK_TRAIN_NONE;
2397 temp |= FDI_LINK_TRAIN_PATTERN_1;
2398 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002402 udelay(150);
2403
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002404 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002405 reg = FDI_TX_CTL(pipe);
2406 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002407 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2408 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002409 I915_WRITE(reg, temp);
2410
2411 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002412 udelay(500);
2413
Chris Wilson5eddb702010-09-11 13:48:45 +01002414 reg = FDI_RX_IIR(pipe);
2415 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002416 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2417
2418 if (temp & FDI_RX_BIT_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002419 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002420 DRM_DEBUG_KMS("FDI train 1 done.\n");
2421 break;
2422 }
2423 }
2424 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002425 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002426
2427 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_2;
2432 if (IS_GEN6(dev)) {
2433 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2434 /* SNB-B */
2435 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2436 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002437 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002438
Chris Wilson5eddb702010-09-11 13:48:45 +01002439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002441 if (HAS_PCH_CPT(dev)) {
2442 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2443 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2444 } else {
2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_2;
2447 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002448 I915_WRITE(reg, temp);
2449
2450 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002451 udelay(150);
2452
2453 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002456 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2457 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002458 I915_WRITE(reg, temp);
2459
2460 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002461 udelay(500);
2462
Chris Wilson5eddb702010-09-11 13:48:45 +01002463 reg = FDI_RX_IIR(pipe);
2464 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2466
2467 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002468 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002469 DRM_DEBUG_KMS("FDI train 2 done.\n");
2470 break;
2471 }
2472 }
2473 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002474 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002475
2476 DRM_DEBUG_KMS("FDI train done.\n");
2477}
2478
Jesse Barnes0e23b992010-09-10 11:10:00 -07002479static void ironlake_fdi_enable(struct drm_crtc *crtc)
2480{
2481 struct drm_device *dev = crtc->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2484 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002485 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002486
Jesse Barnesc64e3112010-09-10 11:27:03 -07002487 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002488 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2489 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002490
Jesse Barnes0e23b992010-09-10 11:10:00 -07002491 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002492 reg = FDI_RX_CTL(pipe);
2493 temp = I915_READ(reg);
2494 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002495 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002496 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2497 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2498
2499 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002500 udelay(200);
2501
2502 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002503 temp = I915_READ(reg);
2504 I915_WRITE(reg, temp | FDI_PCDCLK);
2505
2506 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002507 udelay(200);
2508
2509 /* Enable CPU FDI TX PLL, always on for Ironlake */
Chris Wilson5eddb702010-09-11 13:48:45 +01002510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002512 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002513 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2514
2515 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002516 udelay(100);
2517 }
2518}
2519
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002520static void ironlake_fdi_disable(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp;
2527
2528 /* disable CPU FDI tx and PCH FDI rx */
2529 reg = FDI_TX_CTL(pipe);
2530 temp = I915_READ(reg);
2531 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2532 POSTING_READ(reg);
2533
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 temp &= ~(0x7 << 16);
2537 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2538 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2539
2540 POSTING_READ(reg);
2541 udelay(100);
2542
2543 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002544 if (HAS_PCH_IBX(dev)) {
2545 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002546 I915_WRITE(FDI_RX_CHICKEN(pipe),
2547 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002548 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2549 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002550
2551 /* still set train pattern 1 */
2552 reg = FDI_TX_CTL(pipe);
2553 temp = I915_READ(reg);
2554 temp &= ~FDI_LINK_TRAIN_NONE;
2555 temp |= FDI_LINK_TRAIN_PATTERN_1;
2556 I915_WRITE(reg, temp);
2557
2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 if (HAS_PCH_CPT(dev)) {
2561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2563 } else {
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_1;
2566 }
2567 /* BPC in FDI rx is consistent with that in PIPECONF */
2568 temp &= ~(0x07 << 16);
2569 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2570 I915_WRITE(reg, temp);
2571
2572 POSTING_READ(reg);
2573 udelay(100);
2574}
2575
Chris Wilson6b383a72010-09-13 13:54:26 +01002576/*
2577 * When we disable a pipe, we need to clear any pending scanline wait events
2578 * to avoid hanging the ring, which we assume we are waiting on.
2579 */
2580static void intel_clear_scanline_wait(struct drm_device *dev)
2581{
2582 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8168bd42010-11-11 17:54:52 +00002583 struct intel_ring_buffer *ring;
Chris Wilson6b383a72010-09-13 13:54:26 +01002584 u32 tmp;
2585
2586 if (IS_GEN2(dev))
2587 /* Can't break the hang on i8xx */
2588 return;
2589
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002590 ring = LP_RING(dev_priv);
Chris Wilson8168bd42010-11-11 17:54:52 +00002591 tmp = I915_READ_CTL(ring);
2592 if (tmp & RING_WAIT)
2593 I915_WRITE_CTL(ring, tmp);
Chris Wilson6b383a72010-09-13 13:54:26 +01002594}
2595
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002596static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2597{
Chris Wilson05394f32010-11-08 19:18:58 +00002598 struct drm_i915_gem_object *obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002599 struct drm_i915_private *dev_priv;
2600
2601 if (crtc->fb == NULL)
2602 return;
2603
Chris Wilson05394f32010-11-08 19:18:58 +00002604 obj = to_intel_framebuffer(crtc->fb)->obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002605 dev_priv = crtc->dev->dev_private;
2606 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002607 atomic_read(&obj->pending_flip) == 0);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002608}
2609
Jesse Barnes040484a2011-01-03 12:14:26 -08002610static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2611{
2612 struct drm_device *dev = crtc->dev;
2613 struct drm_mode_config *mode_config = &dev->mode_config;
2614 struct intel_encoder *encoder;
2615
2616 /*
2617 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2618 * must be driven by its own crtc; no sharing is possible.
2619 */
2620 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2621 if (encoder->base.crtc != crtc)
2622 continue;
2623
2624 switch (encoder->type) {
2625 case INTEL_OUTPUT_EDP:
2626 if (!intel_encoder_is_pch_edp(&encoder->base))
2627 return false;
2628 continue;
2629 }
2630 }
2631
2632 return true;
2633}
2634
Jesse Barnesf67a5592011-01-05 10:31:48 -08002635/*
2636 * Enable PCH resources required for PCH ports:
2637 * - PCH PLLs
2638 * - FDI training & RX/TX
2639 * - update transcoder timings
2640 * - DP transcoding bits
2641 * - transcoder
2642 */
2643static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002644{
2645 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002649 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002650
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002651 /* For PCH output, training FDI link */
2652 if (IS_GEN6(dev))
2653 gen6_fdi_link_train(crtc);
2654 else
2655 ironlake_fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002656
Jesse Barnes92f25842011-01-04 15:09:34 -08002657 intel_enable_pch_pll(dev_priv, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002658
2659 if (HAS_PCH_CPT(dev)) {
2660 /* Be sure PCH DPLL SEL is set */
2661 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002662 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002663 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002664 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002665 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2666 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002667 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002668
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002669 /* set transcoder timing, panel must allow it */
2670 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01002671 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2672 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2673 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2674
2675 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2676 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2677 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002678
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002679 intel_fdi_normal_train(crtc);
2680
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002681 /* For PCH DP, enable TRANS_DP_CTL */
2682 if (HAS_PCH_CPT(dev) &&
2683 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002684 reg = TRANS_DP_CTL(pipe);
2685 temp = I915_READ(reg);
2686 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002687 TRANS_DP_SYNC_MASK |
2688 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01002689 temp |= (TRANS_DP_OUTPUT_ENABLE |
2690 TRANS_DP_ENH_FRAMING);
Eric Anholt220cad32010-11-18 09:32:58 +08002691 temp |= TRANS_DP_8BPC;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002692
2693 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002694 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002695 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002696 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002697
2698 switch (intel_trans_dp_port_sel(crtc)) {
2699 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01002700 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002701 break;
2702 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01002703 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002704 break;
2705 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01002706 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002707 break;
2708 default:
2709 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002710 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002711 break;
2712 }
2713
Chris Wilson5eddb702010-09-11 13:48:45 +01002714 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002715 }
2716
Jesse Barnes040484a2011-01-03 12:14:26 -08002717 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002718}
2719
2720static void ironlake_crtc_enable(struct drm_crtc *crtc)
2721{
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 int plane = intel_crtc->plane;
2727 u32 temp;
2728 bool is_pch_port;
2729
2730 if (intel_crtc->active)
2731 return;
2732
2733 intel_crtc->active = true;
2734 intel_update_watermarks(dev);
2735
2736 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2737 temp = I915_READ(PCH_LVDS);
2738 if ((temp & LVDS_PORT_EN) == 0)
2739 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2740 }
2741
2742 is_pch_port = intel_crtc_driving_pch(crtc);
2743
2744 if (is_pch_port)
2745 ironlake_fdi_enable(crtc);
2746 else
2747 ironlake_fdi_disable(crtc);
2748
2749 /* Enable panel fitting for LVDS */
2750 if (dev_priv->pch_pf_size &&
2751 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2752 /* Force use of hard-coded filter coefficients
2753 * as some pre-programmed values are broken,
2754 * e.g. x201.
2755 */
2756 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2757 PF_ENABLE | PF_FILTER_MED_3x3);
2758 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2759 dev_priv->pch_pf_pos);
2760 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2761 dev_priv->pch_pf_size);
2762 }
2763
2764 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2765 intel_enable_plane(dev_priv, plane, pipe);
2766
2767 if (is_pch_port)
2768 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002769
2770 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01002771 intel_update_fbc(dev);
Chris Wilson6b383a72010-09-13 13:54:26 +01002772 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002773}
2774
2775static void ironlake_crtc_disable(struct drm_crtc *crtc)
2776{
2777 struct drm_device *dev = crtc->dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2780 int pipe = intel_crtc->pipe;
2781 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002782 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002783
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002784 if (!intel_crtc->active)
2785 return;
2786
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002787 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002788 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01002789 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01002790
Jesse Barnesb24e7172011-01-04 15:09:30 -08002791 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002792
2793 if (dev_priv->cfb_plane == plane &&
2794 dev_priv->display.disable_fbc)
2795 dev_priv->display.disable_fbc(dev);
2796
Jesse Barnesb24e7172011-01-04 15:09:30 -08002797 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002798
Jesse Barnes6be4a602010-09-10 10:26:01 -07002799 /* Disable PF */
2800 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2801 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2802
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002803 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002804
2805 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2806 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01002807 if (temp & LVDS_PORT_EN) {
2808 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2809 POSTING_READ(PCH_LVDS);
2810 udelay(100);
2811 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07002812 }
2813
Jesse Barnes040484a2011-01-03 12:14:26 -08002814 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002815
Jesse Barnes6be4a602010-09-10 10:26:01 -07002816 if (HAS_PCH_CPT(dev)) {
2817 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002818 reg = TRANS_DP_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2821 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002822
2823 /* disable DPLL_SEL */
2824 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002825 if (pipe == 0)
Jesse Barnes6be4a602010-09-10 10:26:01 -07002826 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2827 else
2828 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2829 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002830 }
2831
2832 /* disable PCH DPLL */
Jesse Barnes92f25842011-01-04 15:09:34 -08002833 intel_disable_pch_pll(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002834
2835 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002839
2840 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2844
2845 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002846 udelay(100);
2847
Chris Wilson5eddb702010-09-11 13:48:45 +01002848 reg = FDI_RX_CTL(pipe);
2849 temp = I915_READ(reg);
2850 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002851
2852 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01002853 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002854 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01002855
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002856 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01002857 intel_update_watermarks(dev);
2858 intel_update_fbc(dev);
2859 intel_clear_scanline_wait(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002860}
2861
2862static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2863{
2864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2865 int pipe = intel_crtc->pipe;
2866 int plane = intel_crtc->plane;
2867
Zhenyu Wang2c072452009-06-05 15:38:42 +08002868 /* XXX: When our outputs are all unaware of DPMS modes other than off
2869 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2870 */
2871 switch (mode) {
2872 case DRM_MODE_DPMS_ON:
2873 case DRM_MODE_DPMS_STANDBY:
2874 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01002875 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002876 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01002877 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002878
Zhenyu Wang2c072452009-06-05 15:38:42 +08002879 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01002880 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002881 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002882 break;
2883 }
2884}
2885
Daniel Vetter02e792f2009-09-15 22:57:34 +02002886static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2887{
Daniel Vetter02e792f2009-09-15 22:57:34 +02002888 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01002889 struct drm_device *dev = intel_crtc->base.dev;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002890
Chris Wilson23f09ce2010-08-12 13:53:37 +01002891 mutex_lock(&dev->struct_mutex);
2892 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2893 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02002894 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02002895
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01002896 /* Let userspace switch the overlay on again. In most cases userspace
2897 * has to recompute where to put it anyway.
2898 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02002899}
2900
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002901static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08002902{
2903 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07002907 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08002908
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002909 if (intel_crtc->active)
2910 return;
2911
2912 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01002913 intel_update_watermarks(dev);
2914
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08002915 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08002916 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002917 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002918
2919 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01002920 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002921
2922 /* Give the overlay scaler a chance to enable if it's on this pipe */
2923 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01002924 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002925}
2926
2927static void i9xx_crtc_disable(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932 int pipe = intel_crtc->pipe;
2933 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002934
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002935 if (!intel_crtc->active)
2936 return;
2937
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002938 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002939 intel_crtc_wait_for_pending_flips(crtc);
2940 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002941 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01002942 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002943
2944 if (dev_priv->cfb_plane == plane &&
2945 dev_priv->display.disable_fbc)
2946 dev_priv->display.disable_fbc(dev);
2947
Jesse Barnesb24e7172011-01-04 15:09:30 -08002948 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08002949 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08002950 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002951
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002952 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01002953 intel_update_fbc(dev);
2954 intel_update_watermarks(dev);
2955 intel_clear_scanline_wait(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002956}
2957
2958static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2959{
Jesse Barnes79e53942008-11-07 14:24:08 -08002960 /* XXX: When our outputs are all unaware of DPMS modes other than off
2961 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2962 */
2963 switch (mode) {
2964 case DRM_MODE_DPMS_ON:
2965 case DRM_MODE_DPMS_STANDBY:
2966 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002967 i9xx_crtc_enable(crtc);
2968 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08002969 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07002970 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08002971 break;
2972 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08002973}
2974
2975/**
2976 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08002977 */
2978static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2979{
2980 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07002981 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002982 struct drm_i915_master_private *master_priv;
2983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984 int pipe = intel_crtc->pipe;
2985 bool enabled;
2986
Chris Wilson032d2a02010-09-06 16:17:22 +01002987 if (intel_crtc->dpms_mode == mode)
2988 return;
2989
Chris Wilsondebcadd2010-08-07 11:01:33 +01002990 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01002991
Jesse Barnese70236a2009-09-21 10:42:27 -07002992 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08002993
2994 if (!dev->primary->master)
2995 return;
2996
2997 master_priv = dev->primary->master->driver_priv;
2998 if (!master_priv->sarea_priv)
2999 return;
3000
3001 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3002
3003 switch (pipe) {
3004 case 0:
3005 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3006 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3007 break;
3008 case 1:
3009 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3010 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3011 break;
3012 default:
3013 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
3014 break;
3015 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003016}
3017
Chris Wilsoncdd59982010-09-08 16:30:16 +01003018static void intel_crtc_disable(struct drm_crtc *crtc)
3019{
3020 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3021 struct drm_device *dev = crtc->dev;
3022
3023 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3024
3025 if (crtc->fb) {
3026 mutex_lock(&dev->struct_mutex);
3027 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3028 mutex_unlock(&dev->struct_mutex);
3029 }
3030}
3031
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003032/* Prepare for a mode set.
3033 *
3034 * Note we could be a lot smarter here. We need to figure out which outputs
3035 * will be enabled, which disabled (in short, how the config will changes)
3036 * and perform the minimum necessary steps to accomplish that, e.g. updating
3037 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3038 * panel fitting is in the proper state, etc.
3039 */
3040static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003041{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003042 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003043}
3044
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003045static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003046{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003047 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003048}
3049
3050static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3051{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003052 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003053}
3054
3055static void ironlake_crtc_commit(struct drm_crtc *crtc)
3056{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003057 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003058}
3059
3060void intel_encoder_prepare (struct drm_encoder *encoder)
3061{
3062 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3063 /* lvds has its own version of prepare see intel_lvds_prepare */
3064 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3065}
3066
3067void intel_encoder_commit (struct drm_encoder *encoder)
3068{
3069 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3070 /* lvds has its own version of commit see intel_lvds_commit */
3071 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3072}
3073
Chris Wilsonea5b2132010-08-04 13:50:23 +01003074void intel_encoder_destroy(struct drm_encoder *encoder)
3075{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003076 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003077
Chris Wilsonea5b2132010-08-04 13:50:23 +01003078 drm_encoder_cleanup(encoder);
3079 kfree(intel_encoder);
3080}
3081
Jesse Barnes79e53942008-11-07 14:24:08 -08003082static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3083 struct drm_display_mode *mode,
3084 struct drm_display_mode *adjusted_mode)
3085{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003086 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003087
Eric Anholtbad720f2009-10-22 16:11:14 -07003088 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003089 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003090 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3091 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003092 }
Chris Wilson89749352010-09-12 18:25:19 +01003093
3094 /* XXX some encoders set the crtcinfo, others don't.
3095 * Obviously we need some form of conflict resolution here...
3096 */
3097 if (adjusted_mode->crtc_htotal == 0)
3098 drm_mode_set_crtcinfo(adjusted_mode, 0);
3099
Jesse Barnes79e53942008-11-07 14:24:08 -08003100 return true;
3101}
3102
Jesse Barnese70236a2009-09-21 10:42:27 -07003103static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003104{
Jesse Barnese70236a2009-09-21 10:42:27 -07003105 return 400000;
3106}
Jesse Barnes79e53942008-11-07 14:24:08 -08003107
Jesse Barnese70236a2009-09-21 10:42:27 -07003108static int i915_get_display_clock_speed(struct drm_device *dev)
3109{
3110 return 333000;
3111}
Jesse Barnes79e53942008-11-07 14:24:08 -08003112
Jesse Barnese70236a2009-09-21 10:42:27 -07003113static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3114{
3115 return 200000;
3116}
Jesse Barnes79e53942008-11-07 14:24:08 -08003117
Jesse Barnese70236a2009-09-21 10:42:27 -07003118static int i915gm_get_display_clock_speed(struct drm_device *dev)
3119{
3120 u16 gcfgc = 0;
3121
3122 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3123
3124 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003125 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003126 else {
3127 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3128 case GC_DISPLAY_CLOCK_333_MHZ:
3129 return 333000;
3130 default:
3131 case GC_DISPLAY_CLOCK_190_200_MHZ:
3132 return 190000;
3133 }
3134 }
3135}
Jesse Barnes79e53942008-11-07 14:24:08 -08003136
Jesse Barnese70236a2009-09-21 10:42:27 -07003137static int i865_get_display_clock_speed(struct drm_device *dev)
3138{
3139 return 266000;
3140}
3141
3142static int i855_get_display_clock_speed(struct drm_device *dev)
3143{
3144 u16 hpllcc = 0;
3145 /* Assume that the hardware is in the high speed state. This
3146 * should be the default.
3147 */
3148 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3149 case GC_CLOCK_133_200:
3150 case GC_CLOCK_100_200:
3151 return 200000;
3152 case GC_CLOCK_166_250:
3153 return 250000;
3154 case GC_CLOCK_100_133:
3155 return 133000;
3156 }
3157
3158 /* Shouldn't happen */
3159 return 0;
3160}
3161
3162static int i830_get_display_clock_speed(struct drm_device *dev)
3163{
3164 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003165}
3166
Zhenyu Wang2c072452009-06-05 15:38:42 +08003167struct fdi_m_n {
3168 u32 tu;
3169 u32 gmch_m;
3170 u32 gmch_n;
3171 u32 link_m;
3172 u32 link_n;
3173};
3174
3175static void
3176fdi_reduce_ratio(u32 *num, u32 *den)
3177{
3178 while (*num > 0xffffff || *den > 0xffffff) {
3179 *num >>= 1;
3180 *den >>= 1;
3181 }
3182}
3183
Zhenyu Wang2c072452009-06-05 15:38:42 +08003184static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003185ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3186 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003187{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003188 m_n->tu = 64; /* default size */
3189
Chris Wilson22ed1112010-12-04 01:01:29 +00003190 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3191 m_n->gmch_m = bits_per_pixel * pixel_clock;
3192 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003193 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3194
Chris Wilson22ed1112010-12-04 01:01:29 +00003195 m_n->link_m = pixel_clock;
3196 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003197 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3198}
3199
3200
Shaohua Li7662c8b2009-06-26 11:23:55 +08003201struct intel_watermark_params {
3202 unsigned long fifo_size;
3203 unsigned long max_wm;
3204 unsigned long default_wm;
3205 unsigned long guard_size;
3206 unsigned long cacheline_size;
3207};
3208
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003209/* Pineview has different values for various configs */
3210static struct intel_watermark_params pineview_display_wm = {
3211 PINEVIEW_DISPLAY_FIFO,
3212 PINEVIEW_MAX_WM,
3213 PINEVIEW_DFT_WM,
3214 PINEVIEW_GUARD_WM,
3215 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003216};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003217static struct intel_watermark_params pineview_display_hplloff_wm = {
3218 PINEVIEW_DISPLAY_FIFO,
3219 PINEVIEW_MAX_WM,
3220 PINEVIEW_DFT_HPLLOFF_WM,
3221 PINEVIEW_GUARD_WM,
3222 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003223};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003224static struct intel_watermark_params pineview_cursor_wm = {
3225 PINEVIEW_CURSOR_FIFO,
3226 PINEVIEW_CURSOR_MAX_WM,
3227 PINEVIEW_CURSOR_DFT_WM,
3228 PINEVIEW_CURSOR_GUARD_WM,
3229 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003230};
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003231static struct intel_watermark_params pineview_cursor_hplloff_wm = {
3232 PINEVIEW_CURSOR_FIFO,
3233 PINEVIEW_CURSOR_MAX_WM,
3234 PINEVIEW_CURSOR_DFT_WM,
3235 PINEVIEW_CURSOR_GUARD_WM,
3236 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003237};
Jesse Barnes0e442c62009-10-19 10:09:33 +09003238static struct intel_watermark_params g4x_wm_info = {
3239 G4X_FIFO_SIZE,
3240 G4X_MAX_WM,
3241 G4X_MAX_WM,
3242 2,
3243 G4X_FIFO_LINE_SIZE,
3244};
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003245static struct intel_watermark_params g4x_cursor_wm_info = {
3246 I965_CURSOR_FIFO,
3247 I965_CURSOR_MAX_WM,
3248 I965_CURSOR_DFT_WM,
3249 2,
3250 G4X_FIFO_LINE_SIZE,
3251};
3252static struct intel_watermark_params i965_cursor_wm_info = {
3253 I965_CURSOR_FIFO,
3254 I965_CURSOR_MAX_WM,
3255 I965_CURSOR_DFT_WM,
3256 2,
3257 I915_FIFO_LINE_SIZE,
3258};
Shaohua Li7662c8b2009-06-26 11:23:55 +08003259static struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003260 I945_FIFO_SIZE,
3261 I915_MAX_WM,
3262 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003263 2,
3264 I915_FIFO_LINE_SIZE
3265};
3266static struct intel_watermark_params i915_wm_info = {
3267 I915_FIFO_SIZE,
3268 I915_MAX_WM,
3269 1,
3270 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003271 I915_FIFO_LINE_SIZE
3272};
3273static struct intel_watermark_params i855_wm_info = {
3274 I855GM_FIFO_SIZE,
3275 I915_MAX_WM,
3276 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003277 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003278 I830_FIFO_LINE_SIZE
3279};
3280static struct intel_watermark_params i830_wm_info = {
3281 I830_FIFO_SIZE,
3282 I915_MAX_WM,
3283 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003284 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003285 I830_FIFO_LINE_SIZE
3286};
3287
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003288static struct intel_watermark_params ironlake_display_wm_info = {
3289 ILK_DISPLAY_FIFO,
3290 ILK_DISPLAY_MAXWM,
3291 ILK_DISPLAY_DFTWM,
3292 2,
3293 ILK_FIFO_LINE_SIZE
3294};
3295
Zhao Yakuic936f442010-06-12 14:32:26 +08003296static struct intel_watermark_params ironlake_cursor_wm_info = {
3297 ILK_CURSOR_FIFO,
3298 ILK_CURSOR_MAXWM,
3299 ILK_CURSOR_DFTWM,
3300 2,
3301 ILK_FIFO_LINE_SIZE
3302};
3303
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003304static struct intel_watermark_params ironlake_display_srwm_info = {
3305 ILK_DISPLAY_SR_FIFO,
3306 ILK_DISPLAY_MAX_SRWM,
3307 ILK_DISPLAY_DFT_SRWM,
3308 2,
3309 ILK_FIFO_LINE_SIZE
3310};
3311
3312static struct intel_watermark_params ironlake_cursor_srwm_info = {
3313 ILK_CURSOR_SR_FIFO,
3314 ILK_CURSOR_MAX_SRWM,
3315 ILK_CURSOR_DFT_SRWM,
3316 2,
3317 ILK_FIFO_LINE_SIZE
3318};
3319
Yuanhan Liu13982612010-12-15 15:42:31 +08003320static struct intel_watermark_params sandybridge_display_wm_info = {
3321 SNB_DISPLAY_FIFO,
3322 SNB_DISPLAY_MAXWM,
3323 SNB_DISPLAY_DFTWM,
3324 2,
3325 SNB_FIFO_LINE_SIZE
3326};
3327
3328static struct intel_watermark_params sandybridge_cursor_wm_info = {
3329 SNB_CURSOR_FIFO,
3330 SNB_CURSOR_MAXWM,
3331 SNB_CURSOR_DFTWM,
3332 2,
3333 SNB_FIFO_LINE_SIZE
3334};
3335
3336static struct intel_watermark_params sandybridge_display_srwm_info = {
3337 SNB_DISPLAY_SR_FIFO,
3338 SNB_DISPLAY_MAX_SRWM,
3339 SNB_DISPLAY_DFT_SRWM,
3340 2,
3341 SNB_FIFO_LINE_SIZE
3342};
3343
3344static struct intel_watermark_params sandybridge_cursor_srwm_info = {
3345 SNB_CURSOR_SR_FIFO,
3346 SNB_CURSOR_MAX_SRWM,
3347 SNB_CURSOR_DFT_SRWM,
3348 2,
3349 SNB_FIFO_LINE_SIZE
3350};
3351
3352
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003353/**
3354 * intel_calculate_wm - calculate watermark level
3355 * @clock_in_khz: pixel clock
3356 * @wm: chip FIFO params
3357 * @pixel_size: display pixel size
3358 * @latency_ns: memory latency for the platform
3359 *
3360 * Calculate the watermark level (the level at which the display plane will
3361 * start fetching from memory again). Each chip has a different display
3362 * FIFO size and allocation, so the caller needs to figure that out and pass
3363 * in the correct intel_watermark_params structure.
3364 *
3365 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3366 * on the pixel size. When it reaches the watermark level, it'll start
3367 * fetching FIFO line sized based chunks from memory until the FIFO fills
3368 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3369 * will occur, and a display engine hang could result.
3370 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003371static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3372 struct intel_watermark_params *wm,
3373 int pixel_size,
3374 unsigned long latency_ns)
3375{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003376 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003377
Jesse Barnesd6604672009-09-11 12:25:56 -07003378 /*
3379 * Note: we need to make sure we don't overflow for various clock &
3380 * latency values.
3381 * clocks go from a few thousand to several hundred thousand.
3382 * latency is usually a few thousand
3383 */
3384 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3385 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003386 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003387
Zhao Yakui28c97732009-10-09 11:39:41 +08003388 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003389
3390 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
3391
Zhao Yakui28c97732009-10-09 11:39:41 +08003392 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003393
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003394 /* Don't promote wm_size to unsigned... */
3395 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003396 wm_size = wm->max_wm;
Chris Wilsonc3add4b2010-09-08 09:14:08 +01003397 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003398 wm_size = wm->default_wm;
3399 return wm_size;
3400}
3401
3402struct cxsr_latency {
3403 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08003404 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003405 unsigned long fsb_freq;
3406 unsigned long mem_freq;
3407 unsigned long display_sr;
3408 unsigned long display_hpll_disable;
3409 unsigned long cursor_sr;
3410 unsigned long cursor_hpll_disable;
3411};
3412
Chris Wilson403c89f2010-08-04 15:25:31 +01003413static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08003414 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3415 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3416 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3417 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3418 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003419
Li Peng95534262010-05-18 18:58:44 +08003420 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3421 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3422 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3423 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3424 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003425
Li Peng95534262010-05-18 18:58:44 +08003426 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3427 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3428 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3429 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3430 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003431
Li Peng95534262010-05-18 18:58:44 +08003432 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3433 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3434 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3435 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3436 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003437
Li Peng95534262010-05-18 18:58:44 +08003438 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3439 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3440 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3441 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3442 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003443
Li Peng95534262010-05-18 18:58:44 +08003444 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3445 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3446 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3447 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3448 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003449};
3450
Chris Wilson403c89f2010-08-04 15:25:31 +01003451static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3452 int is_ddr3,
3453 int fsb,
3454 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003455{
Chris Wilson403c89f2010-08-04 15:25:31 +01003456 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003457 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003458
3459 if (fsb == 0 || mem == 0)
3460 return NULL;
3461
3462 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3463 latency = &cxsr_latency_table[i];
3464 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08003465 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303466 fsb == latency->fsb_freq && mem == latency->mem_freq)
3467 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003468 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303469
Zhao Yakui28c97732009-10-09 11:39:41 +08003470 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303471
3472 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003473}
3474
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003475static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003476{
3477 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003478
3479 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003480 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003481}
3482
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07003483/*
3484 * Latency for FIFO fetches is dependent on several factors:
3485 * - memory configuration (speed, channels)
3486 * - chipset
3487 * - current MCH state
3488 * It can be fairly high in some situations, so here we assume a fairly
3489 * pessimal value. It's a tradeoff between extra memory fetches (if we
3490 * set this value too high, the FIFO will fetch frequently to stay full)
3491 * and power consumption (set it too low to save power and we might see
3492 * FIFO underruns and display "flicker").
3493 *
3494 * A value of 5us seems to be a good balance; safe for very low end
3495 * platforms but not overly aggressive on lower latency configs.
3496 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003497static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003498
Jesse Barnese70236a2009-09-21 10:42:27 -07003499static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003500{
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 uint32_t dsparb = I915_READ(DSPARB);
3503 int size;
3504
Chris Wilson8de9b312010-07-19 19:59:52 +01003505 size = dsparb & 0x7f;
3506 if (plane)
3507 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003508
Zhao Yakui28c97732009-10-09 11:39:41 +08003509 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003510 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003511
3512 return size;
3513}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003514
Jesse Barnese70236a2009-09-21 10:42:27 -07003515static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3516{
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 uint32_t dsparb = I915_READ(DSPARB);
3519 int size;
3520
Chris Wilson8de9b312010-07-19 19:59:52 +01003521 size = dsparb & 0x1ff;
3522 if (plane)
3523 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07003524 size >>= 1; /* Convert to cachelines */
3525
Zhao Yakui28c97732009-10-09 11:39:41 +08003526 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003527 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003528
3529 return size;
3530}
3531
3532static int i845_get_fifo_size(struct drm_device *dev, int plane)
3533{
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535 uint32_t dsparb = I915_READ(DSPARB);
3536 int size;
3537
3538 size = dsparb & 0x7f;
3539 size >>= 2; /* Convert to cachelines */
3540
Zhao Yakui28c97732009-10-09 11:39:41 +08003541 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003542 plane ? "B" : "A",
3543 size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003544
3545 return size;
3546}
3547
3548static int i830_get_fifo_size(struct drm_device *dev, int plane)
3549{
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 uint32_t dsparb = I915_READ(DSPARB);
3552 int size;
3553
3554 size = dsparb & 0x7f;
3555 size >>= 1; /* Convert to cachelines */
3556
Zhao Yakui28c97732009-10-09 11:39:41 +08003557 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003558 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003559
3560 return size;
3561}
3562
Zhao Yakuid4294342010-03-22 22:45:36 +08003563static void pineview_update_wm(struct drm_device *dev, int planea_clock,
Chris Wilson5eddb702010-09-11 13:48:45 +01003564 int planeb_clock, int sr_hdisplay, int unused,
3565 int pixel_size)
Zhao Yakuid4294342010-03-22 22:45:36 +08003566{
3567 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson403c89f2010-08-04 15:25:31 +01003568 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003569 u32 reg;
3570 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003571 int sr_clock;
3572
Chris Wilson403c89f2010-08-04 15:25:31 +01003573 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003574 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003575 if (!latency) {
3576 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3577 pineview_disable_cxsr(dev);
3578 return;
3579 }
3580
3581 if (!planea_clock || !planeb_clock) {
3582 sr_clock = planea_clock ? planea_clock : planeb_clock;
3583
3584 /* Display SR */
3585 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3586 pixel_size, latency->display_sr);
3587 reg = I915_READ(DSPFW1);
3588 reg &= ~DSPFW_SR_MASK;
3589 reg |= wm << DSPFW_SR_SHIFT;
3590 I915_WRITE(DSPFW1, reg);
3591 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3592
3593 /* cursor SR */
3594 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3595 pixel_size, latency->cursor_sr);
3596 reg = I915_READ(DSPFW3);
3597 reg &= ~DSPFW_CURSOR_SR_MASK;
3598 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3599 I915_WRITE(DSPFW3, reg);
3600
3601 /* Display HPLL off SR */
3602 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3603 pixel_size, latency->display_hpll_disable);
3604 reg = I915_READ(DSPFW3);
3605 reg &= ~DSPFW_HPLL_SR_MASK;
3606 reg |= wm & DSPFW_HPLL_SR_MASK;
3607 I915_WRITE(DSPFW3, reg);
3608
3609 /* cursor HPLL off SR */
3610 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3611 pixel_size, latency->cursor_hpll_disable);
3612 reg = I915_READ(DSPFW3);
3613 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3614 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3615 I915_WRITE(DSPFW3, reg);
3616 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3617
3618 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003619 I915_WRITE(DSPFW3,
3620 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003621 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3622 } else {
3623 pineview_disable_cxsr(dev);
3624 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3625 }
3626}
3627
Chris Wilson417ae142011-01-19 15:04:42 +00003628static bool g4x_compute_wm0(struct drm_device *dev,
3629 int plane,
3630 const struct intel_watermark_params *display,
3631 int display_latency_ns,
3632 const struct intel_watermark_params *cursor,
3633 int cursor_latency_ns,
3634 int *plane_wm,
3635 int *cursor_wm)
Jesse Barnes652c3932009-08-17 13:31:43 -07003636{
Chris Wilson417ae142011-01-19 15:04:42 +00003637 struct drm_crtc *crtc;
3638 int htotal, hdisplay, clock, pixel_size;
3639 int line_time_us, line_count;
3640 int entries, tlb_miss;
Jesse Barnes652c3932009-08-17 13:31:43 -07003641
Chris Wilson417ae142011-01-19 15:04:42 +00003642 crtc = intel_get_crtc_for_plane(dev, plane);
3643 if (crtc->fb == NULL || !crtc->enabled)
3644 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003645
Chris Wilson417ae142011-01-19 15:04:42 +00003646 htotal = crtc->mode.htotal;
3647 hdisplay = crtc->mode.hdisplay;
3648 clock = crtc->mode.clock;
3649 pixel_size = crtc->fb->bits_per_pixel / 8;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003650
Chris Wilson417ae142011-01-19 15:04:42 +00003651 /* Use the small buffer method to calculate plane watermark */
3652 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3653 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3654 if (tlb_miss > 0)
3655 entries += tlb_miss;
3656 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3657 *plane_wm = entries + display->guard_size;
3658 if (*plane_wm > (int)display->max_wm)
3659 *plane_wm = display->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003660
Chris Wilson417ae142011-01-19 15:04:42 +00003661 /* Use the large buffer method to calculate cursor watermark */
3662 line_time_us = ((htotal * 1000) / clock);
3663 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3664 entries = line_count * 64 * pixel_size;
3665 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3666 if (tlb_miss > 0)
3667 entries += tlb_miss;
3668 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3669 *cursor_wm = entries + cursor->guard_size;
3670 if (*cursor_wm > (int)cursor->max_wm)
3671 *cursor_wm = (int)cursor->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003672
Chris Wilson417ae142011-01-19 15:04:42 +00003673 return true;
3674}
Jesse Barnes0e442c62009-10-19 10:09:33 +09003675
Chris Wilson417ae142011-01-19 15:04:42 +00003676/*
3677 * Check the wm result.
3678 *
3679 * If any calculated watermark values is larger than the maximum value that
3680 * can be programmed into the associated watermark register, that watermark
3681 * must be disabled.
3682 */
3683static bool g4x_check_srwm(struct drm_device *dev,
3684 int display_wm, int cursor_wm,
3685 const struct intel_watermark_params *display,
3686 const struct intel_watermark_params *cursor)
3687{
3688 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3689 display_wm, cursor_wm);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003690
Chris Wilson417ae142011-01-19 15:04:42 +00003691 if (display_wm > display->max_wm) {
3692 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3693 display_wm, display->max_wm);
3694 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003695 }
3696
Chris Wilson417ae142011-01-19 15:04:42 +00003697 if (cursor_wm > cursor->max_wm) {
3698 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3699 cursor_wm, cursor->max_wm);
3700 return false;
3701 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003702
Chris Wilson417ae142011-01-19 15:04:42 +00003703 if (!(display_wm || cursor_wm)) {
3704 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3705 return false;
3706 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003707
Chris Wilson417ae142011-01-19 15:04:42 +00003708 return true;
3709}
3710
3711static bool g4x_compute_srwm(struct drm_device *dev,
3712 int hdisplay, int htotal,
3713 int pixel_size, int clock, int latency_ns,
3714 const struct intel_watermark_params *display,
3715 const struct intel_watermark_params *cursor,
3716 int *display_wm, int *cursor_wm)
3717{
3718 unsigned long line_time_us;
3719 int line_count, line_size;
3720 int small, large;
3721 int entries;
3722
3723 if (!latency_ns) {
3724 *display_wm = *cursor_wm = 0;
3725 return false;
3726 }
3727
3728 line_time_us = (htotal * 1000) / clock;
3729 line_count = (latency_ns / line_time_us + 1000) / 1000;
3730 line_size = hdisplay * pixel_size;
3731
3732 /* Use the minimum of the small and large buffer method for primary */
3733 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3734 large = line_count * line_size;
3735
3736 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3737 *display_wm = entries + display->guard_size;
3738
3739 /* calculate the self-refresh watermark for display cursor */
3740 entries = line_count * pixel_size * 64;
3741 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3742 *cursor_wm = entries + cursor->guard_size;
3743
3744 return g4x_check_srwm(dev,
3745 *display_wm, *cursor_wm,
3746 display, cursor);
3747}
3748
3749static void g4x_update_wm(struct drm_device *dev,
3750 int planea_clock, int planeb_clock,
3751 int hdisplay, int htotal, int pixel_size)
3752{
3753 static const int sr_latency_ns = 12000;
3754 struct drm_i915_private *dev_priv = dev->dev_private;
3755 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3756 int enabled = 0, plane_sr, cursor_sr, clock;
3757
3758 if (g4x_compute_wm0(dev, 0,
3759 &g4x_wm_info, latency_ns,
3760 &g4x_cursor_wm_info, latency_ns,
3761 &planea_wm, &cursora_wm))
3762 enabled++;
3763
3764 if (g4x_compute_wm0(dev, 1,
3765 &g4x_wm_info, latency_ns,
3766 &g4x_cursor_wm_info, latency_ns,
3767 &planeb_wm, &cursorb_wm))
3768 enabled++;
3769
3770 plane_sr = cursor_sr = 0;
3771 clock = planea_clock ? planea_clock : planeb_clock;
3772 if (enabled == 1 &&
3773 g4x_compute_srwm(dev, hdisplay, htotal, pixel_size,
3774 clock, sr_latency_ns,
3775 &g4x_wm_info,
3776 &g4x_cursor_wm_info,
3777 &plane_sr, &cursor_sr))
3778 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3779 else
3780 I915_WRITE(FW_BLC_SELF,
3781 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3782
3783 DRM_DEBUG("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3784 planea_wm, cursora_wm,
3785 planeb_wm, cursorb_wm,
3786 plane_sr, cursor_sr);
3787
3788 I915_WRITE(DSPFW1,
3789 (plane_sr << DSPFW_SR_SHIFT) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003790 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
Chris Wilson417ae142011-01-19 15:04:42 +00003791 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3792 planea_wm);
3793 I915_WRITE(DSPFW2,
3794 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003795 (cursora_wm << DSPFW_CURSORA_SHIFT));
3796 /* HPLL off in SR has some issues on G4x... disable it */
Chris Wilson417ae142011-01-19 15:04:42 +00003797 I915_WRITE(DSPFW3,
3798 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003799 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07003800}
3801
Jesse Barnes1dc75462009-10-19 10:08:17 +09003802static void i965_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003803 int planeb_clock, int sr_hdisplay, int sr_htotal,
3804 int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003805{
3806 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003807 unsigned long line_time_us;
3808 int sr_clock, sr_entries, srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003809 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003810
Jesse Barnes1dc75462009-10-19 10:08:17 +09003811 /* Calc sr entries for one plane configs */
3812 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3813 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003814 static const int sr_latency_ns = 12000;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003815
3816 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003817 line_time_us = ((sr_htotal * 1000) / sr_clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003818
3819 /* Use ns/us then divide to preserve precision */
Zhao Yakuifa143212010-06-12 14:32:23 +08003820 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01003821 pixel_size * sr_hdisplay;
Chris Wilson8de9b312010-07-19 19:59:52 +01003822 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003823 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
Zhao Yakui1b07e042010-06-12 14:32:24 +08003824 srwm = I965_FIFO_SIZE - sr_entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003825 if (srwm < 0)
3826 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08003827 srwm &= 0x1ff;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003828
3829 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01003830 pixel_size * 64;
Chris Wilson8de9b312010-07-19 19:59:52 +01003831 sr_entries = DIV_ROUND_UP(sr_entries,
3832 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003833 cursor_sr = i965_cursor_wm_info.fifo_size -
Chris Wilson5eddb702010-09-11 13:48:45 +01003834 (sr_entries + i965_cursor_wm_info.guard_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003835
3836 if (cursor_sr > i965_cursor_wm_info.max_wm)
3837 cursor_sr = i965_cursor_wm_info.max_wm;
3838
3839 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3840 "cursor %d\n", srwm, cursor_sr);
3841
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003842 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003843 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05303844 } else {
3845 /* Turn off self refresh if both pipes are enabled */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003846 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003847 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3848 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003849 }
3850
3851 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3852 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003853
3854 /* 965 has limitations... */
Chris Wilson417ae142011-01-19 15:04:42 +00003855 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3856 (8 << 16) | (8 << 8) | (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003857 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003858 /* update cursor SR watermark */
3859 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003860}
3861
3862static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08003863 int planeb_clock, int sr_hdisplay, int sr_htotal,
3864 int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003865{
3866 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003867 uint32_t fwater_lo;
3868 uint32_t fwater_hi;
3869 int total_size, cacheline_size, cwm, srwm = 1;
3870 int planea_wm, planeb_wm;
3871 struct intel_watermark_params planea_params, planeb_params;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003872 unsigned long line_time_us;
Alexander Lam18b21902011-01-03 13:28:56 -05003873 int sr_clock, sr_entries = 0, sr_enabled = 0;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003874
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003875 /* Create copies of the base settings for each pipe */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003876 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003877 planea_params = planeb_params = i945_wm_info;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003878 else if (!IS_GEN2(dev))
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003879 planea_params = planeb_params = i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003880 else
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003881 planea_params = planeb_params = i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003882
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003883 /* Grab a couple of global values before we overwrite them */
3884 total_size = planea_params.fifo_size;
3885 cacheline_size = planea_params.cacheline_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003886
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003887 /* Update per-plane FIFO sizes */
Jesse Barnese70236a2009-09-21 10:42:27 -07003888 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3889 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003890
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003891 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3892 pixel_size, latency_ns);
3893 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3894 pixel_size, latency_ns);
Zhao Yakui28c97732009-10-09 11:39:41 +08003895 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003896
3897 /*
3898 * Overlay gets an aggressive default since video jitter is bad.
3899 */
3900 cwm = 2;
3901
Alexander Lam18b21902011-01-03 13:28:56 -05003902 /* Play safe and disable self-refresh before adjusting watermarks. */
3903 if (IS_I945G(dev) || IS_I945GM(dev))
3904 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3905 else if (IS_I915GM(dev))
3906 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3907
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003908 /* Calc sr entries for one plane configs */
Jesse Barnes652c3932009-08-17 13:31:43 -07003909 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3910 (!planea_clock || !planeb_clock)) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003911 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003912 static const int sr_latency_ns = 6000;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003913
Shaohua Li7662c8b2009-06-26 11:23:55 +08003914 sr_clock = planea_clock ? planea_clock : planeb_clock;
Zhao Yakuifa143212010-06-12 14:32:23 +08003915 line_time_us = ((sr_htotal * 1000) / sr_clock);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003916
3917 /* Use ns/us then divide to preserve precision */
Zhao Yakuifa143212010-06-12 14:32:23 +08003918 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01003919 pixel_size * sr_hdisplay;
Chris Wilson8de9b312010-07-19 19:59:52 +01003920 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
Zhao Yakui28c97732009-10-09 11:39:41 +08003921 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003922 srwm = total_size - sr_entries;
3923 if (srwm < 0)
3924 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08003925
3926 if (IS_I945G(dev) || IS_I945GM(dev))
Alexander Lam18b21902011-01-03 13:28:56 -05003927 I915_WRITE(FW_BLC_SELF,
3928 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3929 else if (IS_I915GM(dev))
Li Pengee980b82010-01-27 19:01:11 +08003930 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
Alexander Lam18b21902011-01-03 13:28:56 -05003931
3932 sr_enabled = 1;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003933 }
3934
Zhao Yakui28c97732009-10-09 11:39:41 +08003935 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01003936 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003937
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003938 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3939 fwater_hi = (cwm & 0x1f);
3940
3941 /* Set request length to 8 cachelines per fetch */
3942 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3943 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003944
3945 I915_WRITE(FW_BLC, fwater_lo);
3946 I915_WRITE(FW_BLC2, fwater_hi);
Alexander Lam18b21902011-01-03 13:28:56 -05003947
3948 if (sr_enabled) {
3949 if (IS_I945G(dev) || IS_I945GM(dev))
3950 I915_WRITE(FW_BLC_SELF,
3951 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3952 else if (IS_I915GM(dev))
3953 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3954 DRM_DEBUG_KMS("memory self refresh enabled\n");
3955 } else
3956 DRM_DEBUG_KMS("memory self refresh disabled\n");
Shaohua Li7662c8b2009-06-26 11:23:55 +08003957}
3958
Jesse Barnese70236a2009-09-21 10:42:27 -07003959static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
Zhao Yakuifa143212010-06-12 14:32:23 +08003960 int unused2, int unused3, int pixel_size)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf3601322009-07-22 12:54:59 -07003963 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003964 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003965
Jesse Barnese70236a2009-09-21 10:42:27 -07003966 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003967
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003968 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3969 pixel_size, latency_ns);
Jesse Barnesf3601322009-07-22 12:54:59 -07003970 fwater_lo |= (3<<8) | planea_wm;
3971
Zhao Yakui28c97732009-10-09 11:39:41 +08003972 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003973
3974 I915_WRITE(FW_BLC, fwater_lo);
3975}
3976
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003977#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08003978#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003979
Chris Wilson4ed765f2010-09-11 10:46:47 +01003980static bool ironlake_compute_wm0(struct drm_device *dev,
3981 int pipe,
Yuanhan Liu13982612010-12-15 15:42:31 +08003982 const struct intel_watermark_params *display,
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08003983 int display_latency_ns,
Yuanhan Liu13982612010-12-15 15:42:31 +08003984 const struct intel_watermark_params *cursor,
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08003985 int cursor_latency_ns,
Chris Wilson4ed765f2010-09-11 10:46:47 +01003986 int *plane_wm,
3987 int *cursor_wm)
3988{
3989 struct drm_crtc *crtc;
Chris Wilsondb66e372011-01-08 09:02:21 +00003990 int htotal, hdisplay, clock, pixel_size;
3991 int line_time_us, line_count;
3992 int entries, tlb_miss;
Chris Wilson4ed765f2010-09-11 10:46:47 +01003993
3994 crtc = intel_get_crtc_for_pipe(dev, pipe);
3995 if (crtc->fb == NULL || !crtc->enabled)
3996 return false;
3997
3998 htotal = crtc->mode.htotal;
3999 hdisplay = crtc->mode.hdisplay;
4000 clock = crtc->mode.clock;
4001 pixel_size = crtc->fb->bits_per_pixel / 8;
4002
4003 /* Use the small buffer method to calculate plane watermark */
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004004 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
Chris Wilsondb66e372011-01-08 09:02:21 +00004005 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4006 if (tlb_miss > 0)
4007 entries += tlb_miss;
Yuanhan Liu13982612010-12-15 15:42:31 +08004008 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4009 *plane_wm = entries + display->guard_size;
4010 if (*plane_wm > (int)display->max_wm)
4011 *plane_wm = display->max_wm;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004012
4013 /* Use the large buffer method to calculate cursor watermark */
4014 line_time_us = ((htotal * 1000) / clock);
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004015 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004016 entries = line_count * 64 * pixel_size;
Chris Wilsondb66e372011-01-08 09:02:21 +00004017 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4018 if (tlb_miss > 0)
4019 entries += tlb_miss;
Yuanhan Liu13982612010-12-15 15:42:31 +08004020 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4021 *cursor_wm = entries + cursor->guard_size;
4022 if (*cursor_wm > (int)cursor->max_wm)
4023 *cursor_wm = (int)cursor->max_wm;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004024
4025 return true;
4026}
4027
Jesse Barnesb79d4992010-12-21 13:10:23 -08004028/*
4029 * Check the wm result.
4030 *
4031 * If any calculated watermark values is larger than the maximum value that
4032 * can be programmed into the associated watermark register, that watermark
4033 * must be disabled.
4034 */
4035static bool ironlake_check_srwm(struct drm_device *dev, int level,
4036 int fbc_wm, int display_wm, int cursor_wm,
4037 const struct intel_watermark_params *display,
4038 const struct intel_watermark_params *cursor)
4039{
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041
4042 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4043 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4044
4045 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4046 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4047 fbc_wm, SNB_FBC_MAX_SRWM, level);
4048
4049 /* fbc has it's own way to disable FBC WM */
4050 I915_WRITE(DISP_ARB_CTL,
4051 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4052 return false;
4053 }
4054
4055 if (display_wm > display->max_wm) {
4056 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4057 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4058 return false;
4059 }
4060
4061 if (cursor_wm > cursor->max_wm) {
4062 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4063 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4064 return false;
4065 }
4066
4067 if (!(fbc_wm || display_wm || cursor_wm)) {
4068 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4069 return false;
4070 }
4071
4072 return true;
4073}
4074
4075/*
4076 * Compute watermark values of WM[1-3],
4077 */
4078static bool ironlake_compute_srwm(struct drm_device *dev, int level,
4079 int hdisplay, int htotal,
4080 int pixel_size, int clock, int latency_ns,
4081 const struct intel_watermark_params *display,
4082 const struct intel_watermark_params *cursor,
4083 int *fbc_wm, int *display_wm, int *cursor_wm)
4084{
4085
4086 unsigned long line_time_us;
4087 int line_count, line_size;
4088 int small, large;
4089 int entries;
4090
4091 if (!latency_ns) {
4092 *fbc_wm = *display_wm = *cursor_wm = 0;
4093 return false;
4094 }
4095
4096 line_time_us = (htotal * 1000) / clock;
4097 line_count = (latency_ns / line_time_us + 1000) / 1000;
4098 line_size = hdisplay * pixel_size;
4099
4100 /* Use the minimum of the small and large buffer method for primary */
4101 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4102 large = line_count * line_size;
4103
4104 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4105 *display_wm = entries + display->guard_size;
4106
4107 /*
4108 * Spec says:
4109 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4110 */
4111 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4112
4113 /* calculate the self-refresh watermark for display cursor */
4114 entries = line_count * pixel_size * 64;
4115 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4116 *cursor_wm = entries + cursor->guard_size;
4117
4118 return ironlake_check_srwm(dev, level,
4119 *fbc_wm, *display_wm, *cursor_wm,
4120 display, cursor);
4121}
4122
Chris Wilson4ed765f2010-09-11 10:46:47 +01004123static void ironlake_update_wm(struct drm_device *dev,
4124 int planea_clock, int planeb_clock,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004125 int hdisplay, int htotal,
Chris Wilson4ed765f2010-09-11 10:46:47 +01004126 int pixel_size)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004127{
4128 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004129 int fbc_wm, plane_wm, cursor_wm, enabled;
4130 int clock;
Zhao Yakuic936f442010-06-12 14:32:26 +08004131
Chris Wilson4ed765f2010-09-11 10:46:47 +01004132 enabled = 0;
Yuanhan Liu13982612010-12-15 15:42:31 +08004133 if (ironlake_compute_wm0(dev, 0,
4134 &ironlake_display_wm_info,
4135 ILK_LP0_PLANE_LATENCY,
4136 &ironlake_cursor_wm_info,
4137 ILK_LP0_CURSOR_LATENCY,
4138 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004139 I915_WRITE(WM0_PIPEA_ILK,
4140 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4141 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4142 " plane %d, " "cursor: %d\n",
4143 plane_wm, cursor_wm);
4144 enabled++;
Zhao Yakuic936f442010-06-12 14:32:26 +08004145 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004146
Yuanhan Liu13982612010-12-15 15:42:31 +08004147 if (ironlake_compute_wm0(dev, 1,
4148 &ironlake_display_wm_info,
4149 ILK_LP0_PLANE_LATENCY,
4150 &ironlake_cursor_wm_info,
4151 ILK_LP0_CURSOR_LATENCY,
4152 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004153 I915_WRITE(WM0_PIPEB_ILK,
4154 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4155 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4156 " plane %d, cursor: %d\n",
4157 plane_wm, cursor_wm);
4158 enabled++;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004159 }
4160
4161 /*
4162 * Calculate and update the self-refresh watermark only when one
4163 * display plane is used.
4164 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004165 I915_WRITE(WM3_LP_ILK, 0);
4166 I915_WRITE(WM2_LP_ILK, 0);
4167 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004168
Jesse Barnesb79d4992010-12-21 13:10:23 -08004169 if (enabled != 1)
4170 return;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004171
Jesse Barnesb79d4992010-12-21 13:10:23 -08004172 clock = planea_clock ? planea_clock : planeb_clock;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004173
Jesse Barnesb79d4992010-12-21 13:10:23 -08004174 /* WM1 */
4175 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4176 clock, ILK_READ_WM1_LATENCY() * 500,
4177 &ironlake_display_srwm_info,
4178 &ironlake_cursor_srwm_info,
4179 &fbc_wm, &plane_wm, &cursor_wm))
4180 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004181
Jesse Barnesb79d4992010-12-21 13:10:23 -08004182 I915_WRITE(WM1_LP_ILK,
4183 WM1_LP_SR_EN |
4184 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4185 (fbc_wm << WM1_LP_FBC_SHIFT) |
4186 (plane_wm << WM1_LP_SR_SHIFT) |
4187 cursor_wm);
Chris Wilson4ed765f2010-09-11 10:46:47 +01004188
Jesse Barnesb79d4992010-12-21 13:10:23 -08004189 /* WM2 */
4190 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
4191 clock, ILK_READ_WM2_LATENCY() * 500,
4192 &ironlake_display_srwm_info,
4193 &ironlake_cursor_srwm_info,
4194 &fbc_wm, &plane_wm, &cursor_wm))
4195 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004196
Jesse Barnesb79d4992010-12-21 13:10:23 -08004197 I915_WRITE(WM2_LP_ILK,
4198 WM2_LP_EN |
4199 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4200 (fbc_wm << WM1_LP_FBC_SHIFT) |
4201 (plane_wm << WM1_LP_SR_SHIFT) |
4202 cursor_wm);
Yuanhan Liu13982612010-12-15 15:42:31 +08004203
4204 /*
Jesse Barnesb79d4992010-12-21 13:10:23 -08004205 * WM3 is unsupported on ILK, probably because we don't have latency
4206 * data for that power state
Yuanhan Liu13982612010-12-15 15:42:31 +08004207 */
Yuanhan Liu13982612010-12-15 15:42:31 +08004208}
4209
4210static void sandybridge_update_wm(struct drm_device *dev,
4211 int planea_clock, int planeb_clock,
4212 int hdisplay, int htotal,
4213 int pixel_size)
4214{
4215 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004216 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Yuanhan Liu13982612010-12-15 15:42:31 +08004217 int fbc_wm, plane_wm, cursor_wm, enabled;
4218 int clock;
4219
4220 enabled = 0;
4221 if (ironlake_compute_wm0(dev, 0,
4222 &sandybridge_display_wm_info, latency,
4223 &sandybridge_cursor_wm_info, latency,
4224 &plane_wm, &cursor_wm)) {
4225 I915_WRITE(WM0_PIPEA_ILK,
4226 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4227 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4228 " plane %d, " "cursor: %d\n",
4229 plane_wm, cursor_wm);
4230 enabled++;
4231 }
4232
4233 if (ironlake_compute_wm0(dev, 1,
4234 &sandybridge_display_wm_info, latency,
4235 &sandybridge_cursor_wm_info, latency,
4236 &plane_wm, &cursor_wm)) {
4237 I915_WRITE(WM0_PIPEB_ILK,
4238 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4239 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4240 " plane %d, cursor: %d\n",
4241 plane_wm, cursor_wm);
4242 enabled++;
4243 }
4244
4245 /*
4246 * Calculate and update the self-refresh watermark only when one
4247 * display plane is used.
4248 *
4249 * SNB support 3 levels of watermark.
4250 *
4251 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4252 * and disabled in the descending order
4253 *
4254 */
4255 I915_WRITE(WM3_LP_ILK, 0);
4256 I915_WRITE(WM2_LP_ILK, 0);
4257 I915_WRITE(WM1_LP_ILK, 0);
4258
4259 if (enabled != 1)
4260 return;
4261
4262 clock = planea_clock ? planea_clock : planeb_clock;
4263
4264 /* WM1 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004265 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
4266 clock, SNB_READ_WM1_LATENCY() * 500,
4267 &sandybridge_display_srwm_info,
4268 &sandybridge_cursor_srwm_info,
4269 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004270 return;
4271
4272 I915_WRITE(WM1_LP_ILK,
4273 WM1_LP_SR_EN |
4274 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4275 (fbc_wm << WM1_LP_FBC_SHIFT) |
4276 (plane_wm << WM1_LP_SR_SHIFT) |
4277 cursor_wm);
4278
4279 /* WM2 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004280 if (!ironlake_compute_srwm(dev, 2,
4281 hdisplay, htotal, pixel_size,
4282 clock, SNB_READ_WM2_LATENCY() * 500,
4283 &sandybridge_display_srwm_info,
4284 &sandybridge_cursor_srwm_info,
4285 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004286 return;
4287
4288 I915_WRITE(WM2_LP_ILK,
4289 WM2_LP_EN |
4290 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4291 (fbc_wm << WM1_LP_FBC_SHIFT) |
4292 (plane_wm << WM1_LP_SR_SHIFT) |
4293 cursor_wm);
4294
4295 /* WM3 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004296 if (!ironlake_compute_srwm(dev, 3,
4297 hdisplay, htotal, pixel_size,
4298 clock, SNB_READ_WM3_LATENCY() * 500,
4299 &sandybridge_display_srwm_info,
4300 &sandybridge_cursor_srwm_info,
4301 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004302 return;
4303
4304 I915_WRITE(WM3_LP_ILK,
4305 WM3_LP_EN |
4306 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4307 (fbc_wm << WM1_LP_FBC_SHIFT) |
4308 (plane_wm << WM1_LP_SR_SHIFT) |
4309 cursor_wm);
4310}
4311
Shaohua Li7662c8b2009-06-26 11:23:55 +08004312/**
4313 * intel_update_watermarks - update FIFO watermark values based on current modes
4314 *
4315 * Calculate watermark values for the various WM regs based on current mode
4316 * and plane configuration.
4317 *
4318 * There are several cases to deal with here:
4319 * - normal (i.e. non-self-refresh)
4320 * - self-refresh (SR) mode
4321 * - lines are large relative to FIFO size (buffer can hold up to 2)
4322 * - lines are small relative to FIFO size (buffer can hold more than 2
4323 * lines), so need to account for TLB latency
4324 *
4325 * The normal calculation is:
4326 * watermark = dotclock * bytes per pixel * latency
4327 * where latency is platform & configuration dependent (we assume pessimal
4328 * values here).
4329 *
4330 * The SR calculation is:
4331 * watermark = (trunc(latency/line time)+1) * surface width *
4332 * bytes per pixel
4333 * where
4334 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08004335 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08004336 * and latency is assumed to be high, as above.
4337 *
4338 * The final value programmed to the register should always be rounded up,
4339 * and include an extra 2 entries to account for clock crossings.
4340 *
4341 * We don't use the sprite, so we can ignore that. And on Crestline we have
4342 * to set the non-SR watermarks to 8.
Chris Wilson5eddb702010-09-11 13:48:45 +01004343 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004344static void intel_update_watermarks(struct drm_device *dev)
4345{
Jesse Barnese70236a2009-09-21 10:42:27 -07004346 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004347 struct drm_crtc *crtc;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004348 int sr_hdisplay = 0;
Chris Wilson29ee3992011-01-24 16:35:42 +00004349 unsigned long planea_clock = 0, planeb_clock = 0;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004350 int enabled = 0, pixel_size = 0;
Zhao Yakuifa143212010-06-12 14:32:23 +08004351 int sr_htotal = 0;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004352
Zhenyu Wangc03342f2009-09-29 11:01:23 +08004353 if (!dev_priv->display.update_wm)
4354 return;
4355
Shaohua Li7662c8b2009-06-26 11:23:55 +08004356 /* Get the clock config from both planes */
4357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsondebcadd2010-08-07 11:01:33 +01004358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilsonf7abfe82010-09-13 14:19:16 +01004359 if (intel_crtc->active) {
Shaohua Li7662c8b2009-06-26 11:23:55 +08004360 enabled++;
4361 if (intel_crtc->plane == 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004362 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004363 intel_crtc->pipe, crtc->mode.clock);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004364 planea_clock = crtc->mode.clock;
4365 } else {
Zhao Yakui28c97732009-10-09 11:39:41 +08004366 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004367 intel_crtc->pipe, crtc->mode.clock);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004368 planeb_clock = crtc->mode.clock;
4369 }
4370 sr_hdisplay = crtc->mode.hdisplay;
Zhao Yakuifa143212010-06-12 14:32:23 +08004371 sr_htotal = crtc->mode.htotal;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004372 if (crtc->fb)
4373 pixel_size = crtc->fb->bits_per_pixel / 8;
4374 else
4375 pixel_size = 4; /* by default */
4376 }
4377 }
4378
4379 if (enabled <= 0)
4380 return;
4381
Jesse Barnese70236a2009-09-21 10:42:27 -07004382 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
Zhao Yakuifa143212010-06-12 14:32:23 +08004383 sr_hdisplay, sr_htotal, pixel_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004384}
4385
Chris Wilsona7615032011-01-12 17:04:08 +00004386static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4387{
4388 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4389}
4390
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004391static int intel_crtc_mode_set(struct drm_crtc *crtc,
4392 struct drm_display_mode *mode,
4393 struct drm_display_mode *adjusted_mode,
4394 int x, int y,
4395 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004396{
4397 struct drm_device *dev = crtc->dev;
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004401 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01004402 u32 fp_reg, dpll_reg;
Eric Anholtc751ce42010-03-25 11:48:48 -07004403 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004404 intel_clock_t clock, reduced_clock;
Chris Wilson5eddb702010-09-11 13:48:45 +01004405 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Jesse Barnes652c3932009-08-17 13:31:43 -07004406 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004407 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson8e647a22010-08-22 10:54:23 +01004408 struct intel_encoder *has_edp_encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004409 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson5eddb702010-09-11 13:48:45 +01004410 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004411 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004412 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004413 struct fdi_m_n m_n = {0};
Chris Wilson5eddb702010-09-11 13:48:45 +01004414 u32 reg, temp;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004415 u32 lvds_sync = 0;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004416 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08004417
4418 drm_vblank_pre_modeset(dev, pipe);
4419
Chris Wilson5eddb702010-09-11 13:48:45 +01004420 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4421 if (encoder->base.crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004422 continue;
4423
Chris Wilson5eddb702010-09-11 13:48:45 +01004424 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004425 case INTEL_OUTPUT_LVDS:
4426 is_lvds = true;
4427 break;
4428 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004429 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004430 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004431 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004432 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004433 break;
4434 case INTEL_OUTPUT_DVO:
4435 is_dvo = true;
4436 break;
4437 case INTEL_OUTPUT_TVOUT:
4438 is_tv = true;
4439 break;
4440 case INTEL_OUTPUT_ANALOG:
4441 is_crt = true;
4442 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004443 case INTEL_OUTPUT_DISPLAYPORT:
4444 is_dp = true;
4445 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004446 case INTEL_OUTPUT_EDP:
Chris Wilson5eddb702010-09-11 13:48:45 +01004447 has_edp_encoder = encoder;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004448 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004449 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004450
Eric Anholtc751ce42010-03-25 11:48:48 -07004451 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004452 }
4453
Chris Wilsona7615032011-01-12 17:04:08 +00004454 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004455 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08004456 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004457 refclk / 1000);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004458 } else if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004459 refclk = 96000;
Jesse Barnes1cb1b752010-10-07 16:01:17 -07004460 if (HAS_PCH_SPLIT(dev) &&
4461 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004462 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08004463 } else {
4464 refclk = 48000;
4465 }
4466
Ma Lingd4906092009-03-18 20:13:27 +08004467 /*
4468 * Returns a set of divisors for the desired target clock with the given
4469 * refclk, or FALSE. The returned values represent the clock equation:
4470 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4471 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004472 limit = intel_limit(crtc, refclk);
Ma Lingd4906092009-03-18 20:13:27 +08004473 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004474 if (!ok) {
4475 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01004476 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004477 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004478 }
4479
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004480 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01004481 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004482
Zhao Yakuiddc90032010-01-06 22:05:56 +08004483 if (is_lvds && dev_priv->lvds_downclock_avail) {
4484 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01004485 dev_priv->lvds_downclock,
4486 refclk,
4487 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004488 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4489 /*
4490 * If the different P is found, it means that we can't
4491 * switch the display clock by using the FP0/FP1.
4492 * In such case we will disable the LVDS downclock
4493 * feature.
4494 */
4495 DRM_DEBUG_KMS("Different P is found for "
Chris Wilson5eddb702010-09-11 13:48:45 +01004496 "LVDS clock/downclock\n");
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004497 has_reduced_clock = 0;
4498 }
Jesse Barnes652c3932009-08-17 13:31:43 -07004499 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004500 /* SDVO TV has fixed PLL values depend on its clock range,
4501 this mirrors vbios setting. */
4502 if (is_sdvo && is_tv) {
4503 if (adjusted_mode->clock >= 100000
Chris Wilson5eddb702010-09-11 13:48:45 +01004504 && adjusted_mode->clock < 140500) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004505 clock.p1 = 2;
4506 clock.p2 = 10;
4507 clock.n = 3;
4508 clock.m1 = 16;
4509 clock.m2 = 8;
4510 } else if (adjusted_mode->clock >= 140500
Chris Wilson5eddb702010-09-11 13:48:45 +01004511 && adjusted_mode->clock <= 200000) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004512 clock.p1 = 1;
4513 clock.p2 = 10;
4514 clock.n = 6;
4515 clock.m1 = 12;
4516 clock.m2 = 8;
4517 }
4518 }
4519
Zhenyu Wang2c072452009-06-05 15:38:42 +08004520 /* FDI link */
Eric Anholtbad720f2009-10-22 16:11:14 -07004521 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson49078f72010-12-04 07:45:57 +00004522 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
Adam Jackson77ffb592010-04-12 11:38:44 -04004523 int lane = 0, link_bw, bpp;
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004524 /* CPU eDP doesn't require FDI link, so just set DP M/N
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004525 according to current link config */
Jesse Barnes858bc212011-01-04 10:46:49 -08004526 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004527 target_clock = mode->clock;
Chris Wilson8e647a22010-08-22 10:54:23 +01004528 intel_edp_link_config(has_edp_encoder,
4529 &lane, &link_bw);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004530 } else {
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004531 /* [e]DP over FDI requires target mode clock
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004532 instead of link clock */
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004533 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004534 target_clock = mode->clock;
4535 else
4536 target_clock = adjusted_mode->clock;
Chris Wilson021357a2010-09-07 20:54:59 +01004537
4538 /* FDI is a binary signal running at ~2.7GHz, encoding
4539 * each output octet as 10 bits. The actual frequency
4540 * is stored as a divider into a 100MHz clock, and the
4541 * mode pixel clock is stored in units of 1KHz.
4542 * Hence the bw of each lane in terms of the mode signal
4543 * is:
4544 */
4545 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004546 }
Zhenyu Wang58a27472009-09-25 08:01:28 +00004547
4548 /* determine panel color depth */
Chris Wilson5eddb702010-09-11 13:48:45 +01004549 temp = I915_READ(PIPECONF(pipe));
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004550 temp &= ~PIPE_BPC_MASK;
4551 if (is_lvds) {
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004552 /* the BPC will be 6 if it is 18-bit LVDS panel */
Chris Wilson5eddb702010-09-11 13:48:45 +01004553 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004554 temp |= PIPE_8BPC;
4555 else
4556 temp |= PIPE_6BPC;
Jesse Barnes1d850362010-10-07 16:01:10 -07004557 } else if (has_edp_encoder) {
Chris Wilson5ceb0f92010-09-24 10:24:28 +01004558 switch (dev_priv->edp.bpp/3) {
Zhenyu Wang885a5fb2010-01-12 05:38:31 +08004559 case 8:
4560 temp |= PIPE_8BPC;
4561 break;
4562 case 10:
4563 temp |= PIPE_10BPC;
4564 break;
4565 case 6:
4566 temp |= PIPE_6BPC;
4567 break;
4568 case 12:
4569 temp |= PIPE_12BPC;
4570 break;
4571 }
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004572 } else
4573 temp |= PIPE_8BPC;
Chris Wilson5eddb702010-09-11 13:48:45 +01004574 I915_WRITE(PIPECONF(pipe), temp);
Zhenyu Wang58a27472009-09-25 08:01:28 +00004575
4576 switch (temp & PIPE_BPC_MASK) {
4577 case PIPE_8BPC:
4578 bpp = 24;
4579 break;
4580 case PIPE_10BPC:
4581 bpp = 30;
4582 break;
4583 case PIPE_6BPC:
4584 bpp = 18;
4585 break;
4586 case PIPE_12BPC:
4587 bpp = 36;
4588 break;
4589 default:
4590 DRM_ERROR("unknown pipe bpc value\n");
4591 bpp = 24;
4592 }
4593
Adam Jackson77ffb592010-04-12 11:38:44 -04004594 if (!lane) {
4595 /*
4596 * Account for spread spectrum to avoid
4597 * oversubscribing the link. Max center spread
4598 * is 2.5%; use 5% for safety's sake.
4599 */
4600 u32 bps = target_clock * bpp * 21 / 20;
4601 lane = bps / (link_bw * 8) + 1;
4602 }
4603
4604 intel_crtc->fdi_lanes = lane;
4605
Chris Wilson49078f72010-12-04 07:45:57 +00004606 if (pixel_multiplier > 1)
4607 link_bw *= pixel_multiplier;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004608 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004609 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004610
Zhenyu Wangc038e512009-10-19 15:43:48 +08004611 /* Ironlake: try to setup display ref clock before DPLL
4612 * enabling. This is only under driver's control after
4613 * PCH B stepping, previous chipset stepping should be
4614 * ignoring this setting.
4615 */
Eric Anholtbad720f2009-10-22 16:11:14 -07004616 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson633f2ea2011-01-19 13:29:42 +00004617 /*XXX BIOS treats 16:31 as a mask for 0:15 */
4618
Zhenyu Wangc038e512009-10-19 15:43:48 +08004619 temp = I915_READ(PCH_DREF_CONTROL);
Chris Wilson633f2ea2011-01-19 13:29:42 +00004620
4621 /* First clear the current state for output switching */
4622 temp &= ~DREF_SSC1_ENABLE;
4623 temp &= ~DREF_SSC4_ENABLE;
4624 temp &= ~DREF_SUPERSPREAD_SOURCE_MASK;
Zhenyu Wangc038e512009-10-19 15:43:48 +08004625 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Zhenyu Wangc038e512009-10-19 15:43:48 +08004626 temp &= ~DREF_SSC_SOURCE_MASK;
Chris Wilson633f2ea2011-01-19 13:29:42 +00004627 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
Zhenyu Wangc038e512009-10-19 15:43:48 +08004628 I915_WRITE(PCH_DREF_CONTROL, temp);
Zhenyu Wangc038e512009-10-19 15:43:48 +08004629
Chris Wilson5eddb702010-09-11 13:48:45 +01004630 POSTING_READ(PCH_DREF_CONTROL);
Zhenyu Wangc038e512009-10-19 15:43:48 +08004631 udelay(200);
4632
Chris Wilson633f2ea2011-01-19 13:29:42 +00004633 if ((is_lvds || has_edp_encoder) &&
4634 intel_panel_use_ssc(dev_priv)) {
4635 temp |= DREF_SSC_SOURCE_ENABLE;
4636 if (has_edp_encoder) {
4637 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4638 /* Enable CPU source on CPU attached eDP */
Jesse Barnes7f823282010-10-07 16:01:16 -07004639 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Chris Wilson633f2ea2011-01-19 13:29:42 +00004640 } else {
4641 /* Enable SSC on PCH eDP if needed */
Jesse Barnes7f823282010-10-07 16:01:16 -07004642 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4643 }
Chris Wilson633f2ea2011-01-19 13:29:42 +00004644 I915_WRITE(PCH_DREF_CONTROL, temp);
Zhenyu Wangc038e512009-10-19 15:43:48 +08004645 }
Chris Wilson633f2ea2011-01-19 13:29:42 +00004646 if (!dev_priv->display_clock_mode)
4647 temp |= DREF_SSC1_ENABLE;
4648 } else {
4649 if (dev_priv->display_clock_mode)
4650 temp |= DREF_NONSPREAD_CK505_ENABLE;
4651 else
4652 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4653 if (has_edp_encoder &&
4654 !intel_encoder_is_pch_edp(&has_edp_encoder->base))
4655 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Zhenyu Wangc038e512009-10-19 15:43:48 +08004656 }
Chris Wilson633f2ea2011-01-19 13:29:42 +00004657
4658 I915_WRITE(PCH_DREF_CONTROL, temp);
4659 POSTING_READ(PCH_DREF_CONTROL);
4660 udelay(200);
Zhenyu Wangc038e512009-10-19 15:43:48 +08004661 }
4662
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004663 if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08004664 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07004665 if (has_reduced_clock)
4666 fp2 = (1 << reduced_clock.n) << 16 |
4667 reduced_clock.m1 << 8 | reduced_clock.m2;
4668 } else {
Shaohua Li21778322009-02-23 15:19:16 +08004669 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07004670 if (has_reduced_clock)
4671 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4672 reduced_clock.m2;
4673 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004674
Chris Wilsonc1858122010-12-03 21:35:48 +00004675 /* Enable autotuning of the PLL clock (if permissible) */
4676 if (HAS_PCH_SPLIT(dev)) {
4677 int factor = 21;
4678
4679 if (is_lvds) {
Chris Wilsona7615032011-01-12 17:04:08 +00004680 if ((intel_panel_use_ssc(dev_priv) &&
Chris Wilsonc1858122010-12-03 21:35:48 +00004681 dev_priv->lvds_ssc_freq == 100) ||
4682 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4683 factor = 25;
4684 } else if (is_sdvo && is_tv)
4685 factor = 20;
4686
4687 if (clock.m1 < factor * clock.n)
4688 fp |= FP_CB_TUNE;
4689 }
4690
Chris Wilson5eddb702010-09-11 13:48:45 +01004691 dpll = 0;
Eric Anholtbad720f2009-10-22 16:11:14 -07004692 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004693 dpll = DPLL_VGA_MODE_DIS;
4694
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004695 if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004696 if (is_lvds)
4697 dpll |= DPLLB_MODE_LVDS;
4698 else
4699 dpll |= DPLLB_MODE_DAC_SERIAL;
4700 if (is_sdvo) {
Chris Wilson6c9547f2010-08-25 10:05:17 +01004701 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4702 if (pixel_multiplier > 1) {
4703 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4704 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4705 else if (HAS_PCH_SPLIT(dev))
4706 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4707 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004708 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004709 }
Jesse Barnes83240122010-10-07 16:01:18 -07004710 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004711 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004712
4713 /* compute bitmask from p1 value */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004714 if (IS_PINEVIEW(dev))
4715 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004716 else {
Shaohua Li21778322009-02-23 15:19:16 +08004717 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004718 /* also FPA1 */
Eric Anholtbad720f2009-10-22 16:11:14 -07004719 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004720 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07004721 if (IS_G4X(dev) && has_reduced_clock)
4722 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004723 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004724 switch (clock.p2) {
4725 case 5:
4726 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4727 break;
4728 case 7:
4729 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4730 break;
4731 case 10:
4732 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4733 break;
4734 case 14:
4735 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4736 break;
4737 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004738 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004739 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4740 } else {
4741 if (is_lvds) {
4742 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4743 } else {
4744 if (clock.p1 == 2)
4745 dpll |= PLL_P1_DIVIDE_BY_TWO;
4746 else
4747 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4748 if (clock.p2 == 4)
4749 dpll |= PLL_P2_DIVIDE_BY_4;
4750 }
4751 }
4752
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004753 if (is_sdvo && is_tv)
4754 dpll |= PLL_REF_INPUT_TVCLKINBC;
4755 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08004756 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004757 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08004758 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00004759 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004760 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08004761 else
4762 dpll |= PLL_REF_INPUT_DREFCLK;
4763
4764 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01004765 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004766
4767 /* Set up the display plane register */
4768 dspcntr = DISPPLANE_GAMMA_ENABLE;
4769
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004770 /* Ironlake's plane is forced to pipe, bit 24 is to
Zhenyu Wang2c072452009-06-05 15:38:42 +08004771 enable color space conversion */
Eric Anholtbad720f2009-10-22 16:11:14 -07004772 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004773 if (pipe == 0)
Jesse Barnes80824002009-09-10 15:28:06 -07004774 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004775 else
4776 dspcntr |= DISPPLANE_SEL_PIPE_B;
4777 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004778
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004779 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004780 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4781 * core speed.
4782 *
4783 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4784 * pipe == 0 check?
4785 */
Jesse Barnese70236a2009-09-21 10:42:27 -07004786 if (mode->clock >
4787 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
Chris Wilson5eddb702010-09-11 13:48:45 +01004788 pipeconf |= PIPECONF_DOUBLE_WIDE;
Jesse Barnes79e53942008-11-07 14:24:08 -08004789 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004790 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
Jesse Barnes79e53942008-11-07 14:24:08 -08004791 }
4792
Jesse Barnesb24e7172011-01-04 15:09:30 -08004793 if (!HAS_PCH_SPLIT(dev))
Jesse Barnes65993d62011-01-04 15:09:29 -08004794 dpll |= DPLL_VCO_ENABLE;
Linus Torvalds8d86dc62010-06-08 20:16:28 -07004795
Zhao Yakui28c97732009-10-09 11:39:41 +08004796 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08004797 drm_mode_debug_printmodeline(mode);
4798
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004799 /* assign to Ironlake registers */
Eric Anholtbad720f2009-10-22 16:11:14 -07004800 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004801 fp_reg = PCH_FP0(pipe);
4802 dpll_reg = PCH_DPLL(pipe);
4803 } else {
4804 fp_reg = FP0(pipe);
4805 dpll_reg = DPLL(pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004806 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004807
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004808 /* PCH eDP needs FDI, but CPU eDP does not */
4809 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004810 I915_WRITE(fp_reg, fp);
4811 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01004812
4813 POSTING_READ(dpll_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08004814 udelay(150);
4815 }
4816
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004817 /* enable transcoder DPLL */
4818 if (HAS_PCH_CPT(dev)) {
4819 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01004820 if (pipe == 0)
4821 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004822 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004823 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004824 I915_WRITE(PCH_DPLL_SEL, temp);
Chris Wilson5eddb702010-09-11 13:48:45 +01004825
4826 POSTING_READ(PCH_DPLL_SEL);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004827 udelay(150);
4828 }
4829
Jesse Barnes79e53942008-11-07 14:24:08 -08004830 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4831 * This is an exception to the general rule that mode_set doesn't turn
4832 * things on.
4833 */
4834 if (is_lvds) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004835 reg = LVDS;
Eric Anholtbad720f2009-10-22 16:11:14 -07004836 if (HAS_PCH_SPLIT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004837 reg = PCH_LVDS;
Zhenyu Wang541998a2009-06-05 15:38:44 +08004838
Chris Wilson5eddb702010-09-11 13:48:45 +01004839 temp = I915_READ(reg);
4840 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004841 if (pipe == 1) {
4842 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004843 temp |= PORT_TRANS_B_SEL_CPT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004844 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004845 temp |= LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004846 } else {
4847 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004848 temp &= ~PORT_TRANS_SEL_MASK;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004849 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004850 temp &= ~LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004851 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004852 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01004853 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08004854 /* Set the B0-B3 data pairs corresponding to whether we're going to
4855 * set the DPLLs for dual-channel mode or not.
4856 */
4857 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01004858 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08004859 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004860 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08004861
4862 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4863 * appropriately here, but we need to look more thoroughly into how
4864 * panels behave in the two modes.
4865 */
Jesse Barnes434ed092010-09-07 14:48:06 -07004866 /* set the dithering flag on non-PCH LVDS as needed */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004867 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
Jesse Barnes434ed092010-09-07 14:48:06 -07004868 if (dev_priv->lvds_dither)
Chris Wilson5eddb702010-09-11 13:48:45 +01004869 temp |= LVDS_ENABLE_DITHER;
Jesse Barnes434ed092010-09-07 14:48:06 -07004870 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004871 temp &= ~LVDS_ENABLE_DITHER;
Zhao Yakui898822c2010-01-04 16:29:30 +08004872 }
Bryan Freedaa9b5002011-01-12 13:43:19 -08004873 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4874 lvds_sync |= LVDS_HSYNC_POLARITY;
4875 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4876 lvds_sync |= LVDS_VSYNC_POLARITY;
4877 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4878 != lvds_sync) {
4879 char flags[2] = "-+";
4880 DRM_INFO("Changing LVDS panel from "
4881 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4882 flags[!(temp & LVDS_HSYNC_POLARITY)],
4883 flags[!(temp & LVDS_VSYNC_POLARITY)],
4884 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4885 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4886 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4887 temp |= lvds_sync;
4888 }
Chris Wilson5eddb702010-09-11 13:48:45 +01004889 I915_WRITE(reg, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08004890 }
Jesse Barnes434ed092010-09-07 14:48:06 -07004891
4892 /* set the dithering flag and clear for anything other than a panel. */
4893 if (HAS_PCH_SPLIT(dev)) {
4894 pipeconf &= ~PIPECONF_DITHER_EN;
4895 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4896 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4897 pipeconf |= PIPECONF_DITHER_EN;
4898 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4899 }
4900 }
4901
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004902 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004903 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004904 } else if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004905 /* For non-DP output, clear any trans DP clock recovery setting.*/
4906 if (pipe == 0) {
4907 I915_WRITE(TRANSA_DATA_M1, 0);
4908 I915_WRITE(TRANSA_DATA_N1, 0);
4909 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4910 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4911 } else {
4912 I915_WRITE(TRANSB_DATA_M1, 0);
4913 I915_WRITE(TRANSB_DATA_N1, 0);
4914 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4915 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4916 }
4917 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004918
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004919 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004920 I915_WRITE(dpll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01004921
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004922 /* Wait for the clocks to stabilize. */
Chris Wilson5eddb702010-09-11 13:48:45 +01004923 POSTING_READ(dpll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004924 udelay(150);
4925
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004926 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004927 temp = 0;
Zhao Yakuibb66c512009-09-10 15:45:49 +08004928 if (is_sdvo) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004929 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4930 if (temp > 1)
4931 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chris Wilson6c9547f2010-08-25 10:05:17 +01004932 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004933 temp = 0;
4934 }
4935 I915_WRITE(DPLL_MD(pipe), temp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004936 } else {
Chris Wilsona589b9f2010-12-03 21:13:16 +00004937 /* The pixel multiplier can only be updated once the
4938 * DPLL is enabled and the clocks are stable.
4939 *
4940 * So write it again.
4941 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004942 I915_WRITE(dpll_reg, dpll);
4943 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004944 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004945
Chris Wilson5eddb702010-09-11 13:48:45 +01004946 intel_crtc->lowfreq_avail = false;
Jesse Barnes652c3932009-08-17 13:31:43 -07004947 if (is_lvds && has_reduced_clock && i915_powersave) {
4948 I915_WRITE(fp_reg + 4, fp2);
4949 intel_crtc->lowfreq_avail = true;
4950 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004951 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004952 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4953 }
4954 } else {
4955 I915_WRITE(fp_reg + 4, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07004956 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08004957 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07004958 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4959 }
4960 }
4961
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004962 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4963 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4964 /* the chip adds 2 halflines automatically */
4965 adjusted_mode->crtc_vdisplay -= 1;
4966 adjusted_mode->crtc_vtotal -= 1;
4967 adjusted_mode->crtc_vblank_start -= 1;
4968 adjusted_mode->crtc_vblank_end -= 1;
4969 adjusted_mode->crtc_vsync_end -= 1;
4970 adjusted_mode->crtc_vsync_start -= 1;
4971 } else
4972 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4973
Chris Wilson5eddb702010-09-11 13:48:45 +01004974 I915_WRITE(HTOTAL(pipe),
4975 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004976 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004977 I915_WRITE(HBLANK(pipe),
4978 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004979 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004980 I915_WRITE(HSYNC(pipe),
4981 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004982 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004983
4984 I915_WRITE(VTOTAL(pipe),
4985 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004986 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004987 I915_WRITE(VBLANK(pipe),
4988 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004989 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004990 I915_WRITE(VSYNC(pipe),
4991 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004992 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004993
4994 /* pipesrc and dspsize control the size that is scaled from,
4995 * which should always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08004996 */
Eric Anholtbad720f2009-10-22 16:11:14 -07004997 if (!HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004998 I915_WRITE(DSPSIZE(plane),
4999 ((mode->vdisplay - 1) << 16) |
5000 (mode->hdisplay - 1));
5001 I915_WRITE(DSPPOS(plane), 0);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005002 }
Chris Wilson5eddb702010-09-11 13:48:45 +01005003 I915_WRITE(PIPESRC(pipe),
5004 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08005005
Eric Anholtbad720f2009-10-22 16:11:14 -07005006 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005007 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5008 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5009 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5010 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005011
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005012 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005013 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005014 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08005015 }
5016
Chris Wilson5eddb702010-09-11 13:48:45 +01005017 I915_WRITE(PIPECONF(pipe), pipeconf);
5018 POSTING_READ(PIPECONF(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08005019 if (!HAS_PCH_SPLIT(dev))
Jesse Barnes040484a2011-01-03 12:14:26 -08005020 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnes79e53942008-11-07 14:24:08 -08005021
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005022 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005023
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01005024 if (IS_GEN5(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08005025 /* enable address swizzle for tiling buffer */
5026 temp = I915_READ(DISP_ARB_CTL);
5027 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5028 }
5029
Chris Wilson5eddb702010-09-11 13:48:45 +01005030 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005031 POSTING_READ(DSPCNTR(plane));
5032 if (!HAS_PCH_SPLIT(dev))
5033 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005034
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005035 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005036
5037 intel_update_watermarks(dev);
5038
Jesse Barnes79e53942008-11-07 14:24:08 -08005039 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005040
Chris Wilson1f803ee2009-06-06 09:45:59 +01005041 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005042}
5043
5044/** Loads the palette/gamma unit for the CRTC with the prepared values */
5045void intel_crtc_load_lut(struct drm_crtc *crtc)
5046{
5047 struct drm_device *dev = crtc->dev;
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5050 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
5051 int i;
5052
5053 /* The clocks have to be on to load the palette. */
5054 if (!crtc->enabled)
5055 return;
5056
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005057 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005058 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08005059 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
5060 LGC_PALETTE_B;
5061
Jesse Barnes79e53942008-11-07 14:24:08 -08005062 for (i = 0; i < 256; i++) {
5063 I915_WRITE(palreg + 4 * i,
5064 (intel_crtc->lut_r[i] << 16) |
5065 (intel_crtc->lut_g[i] << 8) |
5066 intel_crtc->lut_b[i]);
5067 }
5068}
5069
Chris Wilson560b85b2010-08-07 11:01:38 +01005070static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5071{
5072 struct drm_device *dev = crtc->dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5075 bool visible = base != 0;
5076 u32 cntl;
5077
5078 if (intel_crtc->cursor_visible == visible)
5079 return;
5080
5081 cntl = I915_READ(CURACNTR);
5082 if (visible) {
5083 /* On these chipsets we can only modify the base whilst
5084 * the cursor is disabled.
5085 */
5086 I915_WRITE(CURABASE, base);
5087
5088 cntl &= ~(CURSOR_FORMAT_MASK);
5089 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5090 cntl |= CURSOR_ENABLE |
5091 CURSOR_GAMMA_ENABLE |
5092 CURSOR_FORMAT_ARGB;
5093 } else
5094 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5095 I915_WRITE(CURACNTR, cntl);
5096
5097 intel_crtc->cursor_visible = visible;
5098}
5099
5100static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5101{
5102 struct drm_device *dev = crtc->dev;
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5105 int pipe = intel_crtc->pipe;
5106 bool visible = base != 0;
5107
5108 if (intel_crtc->cursor_visible != visible) {
5109 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
5110 if (base) {
5111 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5112 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5113 cntl |= pipe << 28; /* Connect to correct pipe */
5114 } else {
5115 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5116 cntl |= CURSOR_MODE_DISABLE;
5117 }
5118 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
5119
5120 intel_crtc->cursor_visible = visible;
5121 }
5122 /* and commit changes on next vblank */
5123 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
5124}
5125
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005126/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005127static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5128 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005129{
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133 int pipe = intel_crtc->pipe;
5134 int x = intel_crtc->cursor_x;
5135 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005136 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005137 bool visible;
5138
5139 pos = 0;
5140
Chris Wilson6b383a72010-09-13 13:54:26 +01005141 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005142 base = intel_crtc->cursor_addr;
5143 if (x > (int) crtc->fb->width)
5144 base = 0;
5145
5146 if (y > (int) crtc->fb->height)
5147 base = 0;
5148 } else
5149 base = 0;
5150
5151 if (x < 0) {
5152 if (x + intel_crtc->cursor_width < 0)
5153 base = 0;
5154
5155 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5156 x = -x;
5157 }
5158 pos |= x << CURSOR_X_SHIFT;
5159
5160 if (y < 0) {
5161 if (y + intel_crtc->cursor_height < 0)
5162 base = 0;
5163
5164 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5165 y = -y;
5166 }
5167 pos |= y << CURSOR_Y_SHIFT;
5168
5169 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005170 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005171 return;
5172
5173 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
Chris Wilson560b85b2010-08-07 11:01:38 +01005174 if (IS_845G(dev) || IS_I865G(dev))
5175 i845_update_cursor(crtc, base);
5176 else
5177 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005178
5179 if (visible)
5180 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5181}
5182
Jesse Barnes79e53942008-11-07 14:24:08 -08005183static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005184 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005185 uint32_t handle,
5186 uint32_t width, uint32_t height)
5187{
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005191 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005192 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005193 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005194
Zhao Yakui28c97732009-10-09 11:39:41 +08005195 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005196
5197 /* if we want to turn off the cursor ignore width and height */
5198 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005199 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005200 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005201 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005202 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005203 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005204 }
5205
5206 /* Currently we only support 64x64 cursors */
5207 if (width != 64 || height != 64) {
5208 DRM_ERROR("we currently only support 64x64 cursors\n");
5209 return -EINVAL;
5210 }
5211
Chris Wilson05394f32010-11-08 19:18:58 +00005212 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5213 if (!obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08005214 return -ENOENT;
5215
Chris Wilson05394f32010-11-08 19:18:58 +00005216 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005217 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005218 ret = -ENOMEM;
5219 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005220 }
5221
Dave Airlie71acb5e2008-12-30 20:31:46 +10005222 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005223 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005224 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005225 if (obj->tiling_mode) {
5226 DRM_ERROR("cursor cannot be tiled\n");
5227 ret = -EINVAL;
5228 goto fail_locked;
5229 }
5230
Chris Wilson05394f32010-11-08 19:18:58 +00005231 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005232 if (ret) {
5233 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005234 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005235 }
Chris Wilsone7b526b2010-06-02 08:30:48 +01005236
Chris Wilson05394f32010-11-08 19:18:58 +00005237 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005238 if (ret) {
5239 DRM_ERROR("failed to move cursor bo into the GTT\n");
5240 goto fail_unpin;
5241 }
5242
Chris Wilsond9e86c02010-11-10 16:40:20 +00005243 ret = i915_gem_object_put_fence(obj);
5244 if (ret) {
5245 DRM_ERROR("failed to move cursor bo into the GTT\n");
5246 goto fail_unpin;
5247 }
5248
Chris Wilson05394f32010-11-08 19:18:58 +00005249 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005250 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005251 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005252 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005253 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5254 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005255 if (ret) {
5256 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005257 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005258 }
Chris Wilson05394f32010-11-08 19:18:58 +00005259 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005260 }
5261
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005262 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005263 I915_WRITE(CURSIZE, (height << 12) | width);
5264
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005265 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005266 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005267 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005268 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005269 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5270 } else
5271 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005272 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005273 }
Jesse Barnes80824002009-09-10 15:28:06 -07005274
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005275 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005276
5277 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005278 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005279 intel_crtc->cursor_width = width;
5280 intel_crtc->cursor_height = height;
5281
Chris Wilson6b383a72010-09-13 13:54:26 +01005282 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005283
Jesse Barnes79e53942008-11-07 14:24:08 -08005284 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005285fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005286 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005287fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005288 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005289fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005290 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005291 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005292}
5293
5294static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5295{
Jesse Barnes79e53942008-11-07 14:24:08 -08005296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005297
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005298 intel_crtc->cursor_x = x;
5299 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005300
Chris Wilson6b383a72010-09-13 13:54:26 +01005301 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005302
5303 return 0;
5304}
5305
5306/** Sets the color ramps on behalf of RandR */
5307void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5308 u16 blue, int regno)
5309{
5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311
5312 intel_crtc->lut_r[regno] = red >> 8;
5313 intel_crtc->lut_g[regno] = green >> 8;
5314 intel_crtc->lut_b[regno] = blue >> 8;
5315}
5316
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005317void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5318 u16 *blue, int regno)
5319{
5320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5321
5322 *red = intel_crtc->lut_r[regno] << 8;
5323 *green = intel_crtc->lut_g[regno] << 8;
5324 *blue = intel_crtc->lut_b[regno] << 8;
5325}
5326
Jesse Barnes79e53942008-11-07 14:24:08 -08005327static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005328 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005329{
James Simmons72034252010-08-03 01:33:19 +01005330 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005332
James Simmons72034252010-08-03 01:33:19 +01005333 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005334 intel_crtc->lut_r[i] = red[i] >> 8;
5335 intel_crtc->lut_g[i] = green[i] >> 8;
5336 intel_crtc->lut_b[i] = blue[i] >> 8;
5337 }
5338
5339 intel_crtc_load_lut(crtc);
5340}
5341
5342/**
5343 * Get a pipe with a simple mode set on it for doing load-based monitor
5344 * detection.
5345 *
5346 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005347 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005348 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005349 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005350 * configured for it. In the future, it could choose to temporarily disable
5351 * some outputs to free up a pipe for its use.
5352 *
5353 * \return crtc, or NULL if no pipes are available.
5354 */
5355
5356/* VESA 640x480x72Hz mode to set on the pipe */
5357static struct drm_display_mode load_detect_mode = {
5358 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5359 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5360};
5361
Eric Anholt21d40d32010-03-25 11:11:14 -07005362struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005363 struct drm_connector *connector,
Jesse Barnes79e53942008-11-07 14:24:08 -08005364 struct drm_display_mode *mode,
5365 int *dpms_mode)
5366{
5367 struct intel_crtc *intel_crtc;
5368 struct drm_crtc *possible_crtc;
5369 struct drm_crtc *supported_crtc =NULL;
Chris Wilson4ef69c72010-09-09 15:14:28 +01005370 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005371 struct drm_crtc *crtc = NULL;
5372 struct drm_device *dev = encoder->dev;
5373 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5374 struct drm_crtc_helper_funcs *crtc_funcs;
5375 int i = -1;
5376
5377 /*
5378 * Algorithm gets a little messy:
5379 * - if the connector already has an assigned crtc, use it (but make
5380 * sure it's on first)
5381 * - try to find the first unused crtc that can drive this connector,
5382 * and use that if we find one
5383 * - if there are no unused crtcs available, try to use the first
5384 * one we found that supports the connector
5385 */
5386
5387 /* See if we already have a CRTC for this connector */
5388 if (encoder->crtc) {
5389 crtc = encoder->crtc;
5390 /* Make sure the crtc and connector are running */
5391 intel_crtc = to_intel_crtc(crtc);
5392 *dpms_mode = intel_crtc->dpms_mode;
5393 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5394 crtc_funcs = crtc->helper_private;
5395 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5396 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5397 }
5398 return crtc;
5399 }
5400
5401 /* Find an unused one (if possible) */
5402 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5403 i++;
5404 if (!(encoder->possible_crtcs & (1 << i)))
5405 continue;
5406 if (!possible_crtc->enabled) {
5407 crtc = possible_crtc;
5408 break;
5409 }
5410 if (!supported_crtc)
5411 supported_crtc = possible_crtc;
5412 }
5413
5414 /*
5415 * If we didn't find an unused CRTC, don't use any.
5416 */
5417 if (!crtc) {
5418 return NULL;
5419 }
5420
5421 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005422 connector->encoder = encoder;
Eric Anholt21d40d32010-03-25 11:11:14 -07005423 intel_encoder->load_detect_temp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005424
5425 intel_crtc = to_intel_crtc(crtc);
5426 *dpms_mode = intel_crtc->dpms_mode;
5427
5428 if (!crtc->enabled) {
5429 if (!mode)
5430 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05005431 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005432 } else {
5433 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5434 crtc_funcs = crtc->helper_private;
5435 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5436 }
5437
5438 /* Add this connector to the crtc */
5439 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5440 encoder_funcs->commit(encoder);
5441 }
5442 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005443 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005444
5445 return crtc;
5446}
5447
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005448void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5449 struct drm_connector *connector, int dpms_mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08005450{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005451 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005452 struct drm_device *dev = encoder->dev;
5453 struct drm_crtc *crtc = encoder->crtc;
5454 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5455 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5456
Eric Anholt21d40d32010-03-25 11:11:14 -07005457 if (intel_encoder->load_detect_temp) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005458 encoder->crtc = NULL;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005459 connector->encoder = NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07005460 intel_encoder->load_detect_temp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005461 crtc->enabled = drm_helper_crtc_in_use(crtc);
5462 drm_helper_disable_unused_functions(dev);
5463 }
5464
Eric Anholtc751ce42010-03-25 11:48:48 -07005465 /* Switch crtc and encoder back off if necessary */
Jesse Barnes79e53942008-11-07 14:24:08 -08005466 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5467 if (encoder->crtc == crtc)
5468 encoder_funcs->dpms(encoder, dpms_mode);
5469 crtc_funcs->dpms(crtc, dpms_mode);
5470 }
5471}
5472
5473/* Returns the clock of the currently programmed mode of the given pipe. */
5474static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5475{
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478 int pipe = intel_crtc->pipe;
5479 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
5480 u32 fp;
5481 intel_clock_t clock;
5482
5483 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5484 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
5485 else
5486 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
5487
5488 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005489 if (IS_PINEVIEW(dev)) {
5490 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5491 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08005492 } else {
5493 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5494 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5495 }
5496
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005497 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005498 if (IS_PINEVIEW(dev))
5499 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5500 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08005501 else
5502 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08005503 DPLL_FPA01_P1_POST_DIV_SHIFT);
5504
5505 switch (dpll & DPLL_MODE_MASK) {
5506 case DPLLB_MODE_DAC_SERIAL:
5507 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5508 5 : 10;
5509 break;
5510 case DPLLB_MODE_LVDS:
5511 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5512 7 : 14;
5513 break;
5514 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08005515 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08005516 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5517 return 0;
5518 }
5519
5520 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08005521 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005522 } else {
5523 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5524
5525 if (is_lvds) {
5526 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5527 DPLL_FPA01_P1_POST_DIV_SHIFT);
5528 clock.p2 = 14;
5529
5530 if ((dpll & PLL_REF_INPUT_MASK) ==
5531 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5532 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08005533 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005534 } else
Shaohua Li21778322009-02-23 15:19:16 +08005535 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005536 } else {
5537 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5538 clock.p1 = 2;
5539 else {
5540 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5541 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5542 }
5543 if (dpll & PLL_P2_DIVIDE_BY_4)
5544 clock.p2 = 4;
5545 else
5546 clock.p2 = 2;
5547
Shaohua Li21778322009-02-23 15:19:16 +08005548 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005549 }
5550 }
5551
5552 /* XXX: It would be nice to validate the clocks, but we can't reuse
5553 * i830PllIsValid() because it relies on the xf86_config connector
5554 * configuration being accurate, which it isn't necessarily.
5555 */
5556
5557 return clock.dot;
5558}
5559
5560/** Returns the currently programmed mode of the given pipe. */
5561struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5562 struct drm_crtc *crtc)
5563{
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5566 int pipe = intel_crtc->pipe;
5567 struct drm_display_mode *mode;
5568 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5569 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5570 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5571 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5572
5573 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5574 if (!mode)
5575 return NULL;
5576
5577 mode->clock = intel_crtc_clock_get(dev, crtc);
5578 mode->hdisplay = (htot & 0xffff) + 1;
5579 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5580 mode->hsync_start = (hsync & 0xffff) + 1;
5581 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5582 mode->vdisplay = (vtot & 0xffff) + 1;
5583 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5584 mode->vsync_start = (vsync & 0xffff) + 1;
5585 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5586
5587 drm_mode_set_name(mode);
5588 drm_mode_set_crtcinfo(mode, 0);
5589
5590 return mode;
5591}
5592
Jesse Barnes652c3932009-08-17 13:31:43 -07005593#define GPU_IDLE_TIMEOUT 500 /* ms */
5594
5595/* When this timer fires, we've been idle for awhile */
5596static void intel_gpu_idle_timer(unsigned long arg)
5597{
5598 struct drm_device *dev = (struct drm_device *)arg;
5599 drm_i915_private_t *dev_priv = dev->dev_private;
5600
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005601 if (!list_empty(&dev_priv->mm.active_list)) {
5602 /* Still processing requests, so just re-arm the timer. */
5603 mod_timer(&dev_priv->idle_timer, jiffies +
5604 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5605 return;
5606 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005607
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005608 dev_priv->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005609 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005610}
5611
Jesse Barnes652c3932009-08-17 13:31:43 -07005612#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5613
5614static void intel_crtc_idle_timer(unsigned long arg)
5615{
5616 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5617 struct drm_crtc *crtc = &intel_crtc->base;
5618 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005619 struct intel_framebuffer *intel_fb;
5620
5621 intel_fb = to_intel_framebuffer(crtc->fb);
5622 if (intel_fb && intel_fb->obj->active) {
5623 /* The framebuffer is still being accessed by the GPU. */
5624 mod_timer(&intel_crtc->idle_timer, jiffies +
5625 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5626 return;
5627 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005628
Jesse Barnes652c3932009-08-17 13:31:43 -07005629 intel_crtc->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005630 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005631}
5632
Daniel Vetter3dec0092010-08-20 21:40:52 +02005633static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07005634{
5635 struct drm_device *dev = crtc->dev;
5636 drm_i915_private_t *dev_priv = dev->dev_private;
5637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5638 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005639 int dpll_reg = DPLL(pipe);
5640 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07005641
Eric Anholtbad720f2009-10-22 16:11:14 -07005642 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005643 return;
5644
5645 if (!dev_priv->lvds_downclock_avail)
5646 return;
5647
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005648 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005649 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005650 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005651
5652 /* Unlock panel regs */
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005653 I915_WRITE(PP_CONTROL,
5654 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07005655
5656 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5657 I915_WRITE(dpll_reg, dpll);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005658 POSTING_READ(dpll_reg);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005659 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005660
Jesse Barnes652c3932009-08-17 13:31:43 -07005661 dpll = I915_READ(dpll_reg);
5662 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08005663 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005664
5665 /* ...and lock them again */
5666 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5667 }
5668
5669 /* Schedule downclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02005670 mod_timer(&intel_crtc->idle_timer, jiffies +
5671 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07005672}
5673
5674static void intel_decrease_pllclock(struct drm_crtc *crtc)
5675{
5676 struct drm_device *dev = crtc->dev;
5677 drm_i915_private_t *dev_priv = dev->dev_private;
5678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5679 int pipe = intel_crtc->pipe;
5680 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5681 int dpll = I915_READ(dpll_reg);
5682
Eric Anholtbad720f2009-10-22 16:11:14 -07005683 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005684 return;
5685
5686 if (!dev_priv->lvds_downclock_avail)
5687 return;
5688
5689 /*
5690 * Since this is called by a timer, we should never get here in
5691 * the manual case.
5692 */
5693 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005694 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005695
5696 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07005697 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5698 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07005699
5700 dpll |= DISPLAY_RATE_SELECT_FPA1;
5701 I915_WRITE(dpll_reg, dpll);
5702 dpll = I915_READ(dpll_reg);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005703 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005704 dpll = I915_READ(dpll_reg);
5705 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08005706 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005707
5708 /* ...and lock them again */
5709 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5710 }
5711
5712}
5713
5714/**
5715 * intel_idle_update - adjust clocks for idleness
5716 * @work: work struct
5717 *
5718 * Either the GPU or display (or both) went idle. Check the busy status
5719 * here and adjust the CRTC and GPU clocks as necessary.
5720 */
5721static void intel_idle_update(struct work_struct *work)
5722{
5723 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5724 idle_work);
5725 struct drm_device *dev = dev_priv->dev;
5726 struct drm_crtc *crtc;
5727 struct intel_crtc *intel_crtc;
5728
5729 if (!i915_powersave)
5730 return;
5731
5732 mutex_lock(&dev->struct_mutex);
5733
Jesse Barnes7648fa92010-05-20 14:28:11 -07005734 i915_update_gfx_val(dev_priv);
5735
Jesse Barnes652c3932009-08-17 13:31:43 -07005736 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5737 /* Skip inactive CRTCs */
5738 if (!crtc->fb)
5739 continue;
5740
5741 intel_crtc = to_intel_crtc(crtc);
5742 if (!intel_crtc->busy)
5743 intel_decrease_pllclock(crtc);
5744 }
5745
Li Peng45ac22c2010-06-12 23:38:35 +08005746
Jesse Barnes652c3932009-08-17 13:31:43 -07005747 mutex_unlock(&dev->struct_mutex);
5748}
5749
5750/**
5751 * intel_mark_busy - mark the GPU and possibly the display busy
5752 * @dev: drm device
5753 * @obj: object we're operating on
5754 *
5755 * Callers can use this function to indicate that the GPU is busy processing
5756 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5757 * buffer), we'll also mark the display as busy, so we know to increase its
5758 * clock frequency.
5759 */
Chris Wilson05394f32010-11-08 19:18:58 +00005760void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07005761{
5762 drm_i915_private_t *dev_priv = dev->dev_private;
5763 struct drm_crtc *crtc = NULL;
5764 struct intel_framebuffer *intel_fb;
5765 struct intel_crtc *intel_crtc;
5766
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08005767 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5768 return;
5769
Alexander Lam18b21902011-01-03 13:28:56 -05005770 if (!dev_priv->busy)
Chris Wilson28cf7982009-11-30 01:08:56 +00005771 dev_priv->busy = true;
Alexander Lam18b21902011-01-03 13:28:56 -05005772 else
Chris Wilson28cf7982009-11-30 01:08:56 +00005773 mod_timer(&dev_priv->idle_timer, jiffies +
5774 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07005775
5776 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5777 if (!crtc->fb)
5778 continue;
5779
5780 intel_crtc = to_intel_crtc(crtc);
5781 intel_fb = to_intel_framebuffer(crtc->fb);
5782 if (intel_fb->obj == obj) {
5783 if (!intel_crtc->busy) {
5784 /* Non-busy -> busy, upclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02005785 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005786 intel_crtc->busy = true;
5787 } else {
5788 /* Busy -> busy, put off timer */
5789 mod_timer(&intel_crtc->idle_timer, jiffies +
5790 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5791 }
5792 }
5793 }
5794}
5795
Jesse Barnes79e53942008-11-07 14:24:08 -08005796static void intel_crtc_destroy(struct drm_crtc *crtc)
5797{
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005799 struct drm_device *dev = crtc->dev;
5800 struct intel_unpin_work *work;
5801 unsigned long flags;
5802
5803 spin_lock_irqsave(&dev->event_lock, flags);
5804 work = intel_crtc->unpin_work;
5805 intel_crtc->unpin_work = NULL;
5806 spin_unlock_irqrestore(&dev->event_lock, flags);
5807
5808 if (work) {
5809 cancel_work_sync(&work->work);
5810 kfree(work);
5811 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005812
5813 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005814
Jesse Barnes79e53942008-11-07 14:24:08 -08005815 kfree(intel_crtc);
5816}
5817
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005818static void intel_unpin_work_fn(struct work_struct *__work)
5819{
5820 struct intel_unpin_work *work =
5821 container_of(__work, struct intel_unpin_work, work);
5822
5823 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005824 i915_gem_object_unpin(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00005825 drm_gem_object_unreference(&work->pending_flip_obj->base);
5826 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00005827
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005828 mutex_unlock(&work->dev->struct_mutex);
5829 kfree(work);
5830}
5831
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005832static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01005833 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005834{
5835 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00005838 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005839 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005840 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005841 unsigned long flags;
5842
5843 /* Ignore early vblank irqs */
5844 if (intel_crtc == NULL)
5845 return;
5846
Mario Kleiner49b14a52010-12-09 07:00:07 +01005847 do_gettimeofday(&tnow);
5848
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005849 spin_lock_irqsave(&dev->event_lock, flags);
5850 work = intel_crtc->unpin_work;
5851 if (work == NULL || !work->pending) {
5852 spin_unlock_irqrestore(&dev->event_lock, flags);
5853 return;
5854 }
5855
5856 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005857
5858 if (work->event) {
5859 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005860 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005861
5862 /* Called before vblank count and timestamps have
5863 * been updated for the vblank interval of flip
5864 * completion? Need to increment vblank count and
5865 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01005866 * to account for this. We assume this happened if we
5867 * get called over 0.9 frame durations after the last
5868 * timestamped vblank.
5869 *
5870 * This calculation can not be used with vrefresh rates
5871 * below 5Hz (10Hz to be on the safe side) without
5872 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005873 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01005874 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5875 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005876 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005877 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5878 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005879 }
5880
Mario Kleiner49b14a52010-12-09 07:00:07 +01005881 e->event.tv_sec = tvbl.tv_sec;
5882 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005883
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005884 list_add_tail(&e->base.link,
5885 &e->base.file_priv->event_list);
5886 wake_up_interruptible(&e->base.file_priv->event_wait);
5887 }
5888
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005889 drm_vblank_put(dev, intel_crtc->pipe);
5890
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005891 spin_unlock_irqrestore(&dev->event_lock, flags);
5892
Chris Wilson05394f32010-11-08 19:18:58 +00005893 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00005894
Chris Wilsone59f2ba2010-10-07 17:28:15 +01005895 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00005896 &obj->pending_flip.counter);
5897 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01005898 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00005899
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005900 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07005901
5902 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005903}
5904
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005905void intel_finish_page_flip(struct drm_device *dev, int pipe)
5906{
5907 drm_i915_private_t *dev_priv = dev->dev_private;
5908 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5909
Mario Kleiner49b14a52010-12-09 07:00:07 +01005910 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005911}
5912
5913void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5914{
5915 drm_i915_private_t *dev_priv = dev->dev_private;
5916 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5917
Mario Kleiner49b14a52010-12-09 07:00:07 +01005918 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005919}
5920
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005921void intel_prepare_page_flip(struct drm_device *dev, int plane)
5922{
5923 drm_i915_private_t *dev_priv = dev->dev_private;
5924 struct intel_crtc *intel_crtc =
5925 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5926 unsigned long flags;
5927
5928 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08005929 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01005930 if ((++intel_crtc->unpin_work->pending) > 1)
5931 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08005932 } else {
5933 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5934 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005935 spin_unlock_irqrestore(&dev->event_lock, flags);
5936}
5937
5938static int intel_crtc_page_flip(struct drm_crtc *crtc,
5939 struct drm_framebuffer *fb,
5940 struct drm_pending_vblank_event *event)
5941{
5942 struct drm_device *dev = crtc->dev;
5943 struct drm_i915_private *dev_priv = dev->dev_private;
5944 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00005945 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5947 struct intel_unpin_work *work;
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07005948 unsigned long flags, offset;
Chris Wilson52e68632010-08-08 10:15:59 +01005949 int pipe = intel_crtc->pipe;
Chris Wilson20f0cd52010-09-23 11:00:38 +01005950 u32 pf, pipesrc;
Chris Wilson52e68632010-08-08 10:15:59 +01005951 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005952
5953 work = kzalloc(sizeof *work, GFP_KERNEL);
5954 if (work == NULL)
5955 return -ENOMEM;
5956
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005957 work->event = event;
5958 work->dev = crtc->dev;
5959 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005960 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005961 INIT_WORK(&work->work, intel_unpin_work_fn);
5962
5963 /* We borrow the event spin lock for protecting unpin_work */
5964 spin_lock_irqsave(&dev->event_lock, flags);
5965 if (intel_crtc->unpin_work) {
5966 spin_unlock_irqrestore(&dev->event_lock, flags);
5967 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01005968
5969 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005970 return -EBUSY;
5971 }
5972 intel_crtc->unpin_work = work;
5973 spin_unlock_irqrestore(&dev->event_lock, flags);
5974
5975 intel_fb = to_intel_framebuffer(fb);
5976 obj = intel_fb->obj;
5977
Chris Wilson468f0b42010-05-27 13:18:13 +01005978 mutex_lock(&dev->struct_mutex);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00005979 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
Chris Wilson96b099f2010-06-07 14:03:04 +01005980 if (ret)
5981 goto cleanup_work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005982
Jesse Barnes75dfca82010-02-10 15:09:44 -08005983 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00005984 drm_gem_object_reference(&work->old_fb_obj->base);
5985 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005986
5987 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01005988
5989 ret = drm_vblank_get(dev, intel_crtc->pipe);
5990 if (ret)
5991 goto cleanup_objs;
5992
Chris Wilsonc7f9f9a2010-09-19 15:05:13 +01005993 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5994 u32 flip_mask;
5995
5996 /* Can't queue multiple flips, so wait for the previous
5997 * one to finish before executing the next.
5998 */
Chris Wilsone1f99ce2010-10-27 12:45:26 +01005999 ret = BEGIN_LP_RING(2);
6000 if (ret)
6001 goto cleanup_objs;
6002
Chris Wilsonc7f9f9a2010-09-19 15:05:13 +01006003 if (intel_crtc->plane)
6004 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6005 else
6006 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6007 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6008 OUT_RING(MI_NOOP);
Daniel Vetter6146b3d2010-08-04 21:22:10 +02006009 ADVANCE_LP_RING();
6010 }
Jesse Barnes83f7fd02010-04-05 14:03:51 -07006011
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006012 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006013
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006014 work->enable_stall_check = true;
6015
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07006016 /* Offset into the new buffer for cases of shared fbs between CRTCs */
Chris Wilson52e68632010-08-08 10:15:59 +01006017 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07006018
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006019 ret = BEGIN_LP_RING(4);
6020 if (ret)
6021 goto cleanup_objs;
6022
6023 /* Block clients from rendering to the new back buffer until
6024 * the flip occurs and the object is no longer visible.
6025 */
Chris Wilson05394f32010-11-08 19:18:58 +00006026 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006027
6028 switch (INTEL_INFO(dev)->gen) {
Chris Wilson52e68632010-08-08 10:15:59 +01006029 case 2:
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006030 OUT_RING(MI_DISPLAY_FLIP |
6031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6032 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006033 OUT_RING(obj->gtt_offset + offset);
Chris Wilson52e68632010-08-08 10:15:59 +01006034 OUT_RING(MI_NOOP);
6035 break;
6036
6037 case 3:
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006038 OUT_RING(MI_DISPLAY_FLIP_I915 |
6039 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6040 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006041 OUT_RING(obj->gtt_offset + offset);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006042 OUT_RING(MI_NOOP);
Chris Wilson52e68632010-08-08 10:15:59 +01006043 break;
6044
6045 case 4:
6046 case 5:
6047 /* i965+ uses the linear or tiled offsets from the
6048 * Display Registers (which do not change across a page-flip)
6049 * so we need only reprogram the base address.
6050 */
Daniel Vetter69d0b962010-08-04 21:22:09 +02006051 OUT_RING(MI_DISPLAY_FLIP |
6052 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6053 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006054 OUT_RING(obj->gtt_offset | obj->tiling_mode);
Chris Wilson52e68632010-08-08 10:15:59 +01006055
6056 /* XXX Enabling the panel-fitter across page-flip is so far
6057 * untested on non-native modes, so ignore it for now.
6058 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6059 */
6060 pf = 0;
6061 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
6062 OUT_RING(pf | pipesrc);
6063 break;
6064
6065 case 6:
6066 OUT_RING(MI_DISPLAY_FLIP |
6067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Chris Wilson05394f32010-11-08 19:18:58 +00006068 OUT_RING(fb->pitch | obj->tiling_mode);
6069 OUT_RING(obj->gtt_offset);
Chris Wilson52e68632010-08-08 10:15:59 +01006070
6071 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6072 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
6073 OUT_RING(pf | pipesrc);
6074 break;
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006075 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006076 ADVANCE_LP_RING();
6077
6078 mutex_unlock(&dev->struct_mutex);
6079
Jesse Barnese5510fa2010-07-01 16:48:37 -07006080 trace_i915_flip_request(intel_crtc->plane, obj);
6081
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006082 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006083
6084cleanup_objs:
Chris Wilson05394f32010-11-08 19:18:58 +00006085 drm_gem_object_unreference(&work->old_fb_obj->base);
6086 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006087cleanup_work:
6088 mutex_unlock(&dev->struct_mutex);
6089
6090 spin_lock_irqsave(&dev->event_lock, flags);
6091 intel_crtc->unpin_work = NULL;
6092 spin_unlock_irqrestore(&dev->event_lock, flags);
6093
6094 kfree(work);
6095
6096 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006097}
6098
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006099static struct drm_crtc_helper_funcs intel_helper_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006100 .dpms = intel_crtc_dpms,
6101 .mode_fixup = intel_crtc_mode_fixup,
6102 .mode_set = intel_crtc_mode_set,
6103 .mode_set_base = intel_pipe_set_base,
Jesse Barnes81255562010-08-02 12:07:50 -07006104 .mode_set_base_atomic = intel_pipe_set_base_atomic,
Dave Airlie068143d2009-10-05 09:58:02 +10006105 .load_lut = intel_crtc_load_lut,
Chris Wilsoncdd59982010-09-08 16:30:16 +01006106 .disable = intel_crtc_disable,
Jesse Barnes79e53942008-11-07 14:24:08 -08006107};
6108
6109static const struct drm_crtc_funcs intel_crtc_funcs = {
6110 .cursor_set = intel_crtc_cursor_set,
6111 .cursor_move = intel_crtc_cursor_move,
6112 .gamma_set = intel_crtc_gamma_set,
6113 .set_config = drm_crtc_helper_set_config,
6114 .destroy = intel_crtc_destroy,
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006115 .page_flip = intel_crtc_page_flip,
Jesse Barnes79e53942008-11-07 14:24:08 -08006116};
6117
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006118static void intel_sanitize_modesetting(struct drm_device *dev,
6119 int pipe, int plane)
6120{
6121 struct drm_i915_private *dev_priv = dev->dev_private;
6122 u32 reg, val;
6123
6124 if (HAS_PCH_SPLIT(dev))
6125 return;
6126
6127 /* Who knows what state these registers were left in by the BIOS or
6128 * grub?
6129 *
6130 * If we leave the registers in a conflicting state (e.g. with the
6131 * display plane reading from the other pipe than the one we intend
6132 * to use) then when we attempt to teardown the active mode, we will
6133 * not disable the pipes and planes in the correct order -- leaving
6134 * a plane reading from a disabled pipe and possibly leading to
6135 * undefined behaviour.
6136 */
6137
6138 reg = DSPCNTR(plane);
6139 val = I915_READ(reg);
6140
6141 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6142 return;
6143 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6144 return;
6145
6146 /* This display plane is active and attached to the other CPU pipe. */
6147 pipe = !pipe;
6148
6149 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006150 intel_disable_plane(dev_priv, plane, pipe);
6151 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006152}
Jesse Barnes79e53942008-11-07 14:24:08 -08006153
Hannes Ederb358d0a2008-12-18 21:18:47 +01006154static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08006155{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006156 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006157 struct intel_crtc *intel_crtc;
6158 int i;
6159
6160 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6161 if (intel_crtc == NULL)
6162 return;
6163
6164 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6165
6166 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08006167 for (i = 0; i < 256; i++) {
6168 intel_crtc->lut_r[i] = i;
6169 intel_crtc->lut_g[i] = i;
6170 intel_crtc->lut_b[i] = i;
6171 }
6172
Jesse Barnes80824002009-09-10 15:28:06 -07006173 /* Swap pipes & planes for FBC on pre-965 */
6174 intel_crtc->pipe = pipe;
6175 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01006176 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006177 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01006178 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07006179 }
6180
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006181 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6182 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6184 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6185
Jesse Barnes79e53942008-11-07 14:24:08 -08006186 intel_crtc->cursor_addr = 0;
Chris Wilson032d2a02010-09-06 16:17:22 +01006187 intel_crtc->dpms_mode = -1;
Chris Wilsone65d9302010-09-13 16:58:39 +01006188 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006189
6190 if (HAS_PCH_SPLIT(dev)) {
6191 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6192 intel_helper_funcs.commit = ironlake_crtc_commit;
6193 } else {
6194 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6195 intel_helper_funcs.commit = i9xx_crtc_commit;
6196 }
6197
Jesse Barnes79e53942008-11-07 14:24:08 -08006198 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6199
Jesse Barnes652c3932009-08-17 13:31:43 -07006200 intel_crtc->busy = false;
6201
6202 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6203 (unsigned long)intel_crtc);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006204
6205 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
Jesse Barnes79e53942008-11-07 14:24:08 -08006206}
6207
Carl Worth08d7b3d2009-04-29 14:43:54 -07006208int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00006209 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07006210{
6211 drm_i915_private_t *dev_priv = dev->dev_private;
6212 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02006213 struct drm_mode_object *drmmode_obj;
6214 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006215
6216 if (!dev_priv) {
6217 DRM_ERROR("called with no initialization\n");
6218 return -EINVAL;
6219 }
6220
Daniel Vetterc05422d2009-08-11 16:05:30 +02006221 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6222 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07006223
Daniel Vetterc05422d2009-08-11 16:05:30 +02006224 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07006225 DRM_ERROR("no such CRTC id\n");
6226 return -EINVAL;
6227 }
6228
Daniel Vetterc05422d2009-08-11 16:05:30 +02006229 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6230 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006231
Daniel Vetterc05422d2009-08-11 16:05:30 +02006232 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006233}
6234
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08006235static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006236{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006237 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006238 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006239 int entry = 0;
6240
Chris Wilson4ef69c72010-09-09 15:14:28 +01006241 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6242 if (type_mask & encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006243 index_mask |= (1 << entry);
6244 entry++;
6245 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01006246
Jesse Barnes79e53942008-11-07 14:24:08 -08006247 return index_mask;
6248}
6249
Chris Wilson4d302442010-12-14 19:21:29 +00006250static bool has_edp_a(struct drm_device *dev)
6251{
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253
6254 if (!IS_MOBILE(dev))
6255 return false;
6256
6257 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6258 return false;
6259
6260 if (IS_GEN5(dev) &&
6261 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6262 return false;
6263
6264 return true;
6265}
6266
Jesse Barnes79e53942008-11-07 14:24:08 -08006267static void intel_setup_outputs(struct drm_device *dev)
6268{
Eric Anholt725e30a2009-01-22 13:01:02 -08006269 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006270 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006271 bool dpd_is_edp = false;
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006272 bool has_lvds = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006273
Zhenyu Wang541998a2009-06-05 15:38:44 +08006274 if (IS_MOBILE(dev) && !IS_I830(dev))
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006275 has_lvds = intel_lvds_init(dev);
6276 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6277 /* disable the panel fitter on everything but LVDS */
6278 I915_WRITE(PFIT_CONTROL, 0);
6279 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006280
Eric Anholtbad720f2009-10-22 16:11:14 -07006281 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006282 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006283
Chris Wilson4d302442010-12-14 19:21:29 +00006284 if (has_edp_a(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006285 intel_dp_init(dev, DP_A);
6286
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006287 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6288 intel_dp_init(dev, PCH_DP_D);
6289 }
6290
6291 intel_crt_init(dev);
6292
6293 if (HAS_PCH_SPLIT(dev)) {
6294 int found;
6295
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006296 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08006297 /* PCH SDVOB multiplex with HDMIB */
6298 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006299 if (!found)
6300 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006301 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6302 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006303 }
6304
6305 if (I915_READ(HDMIC) & PORT_DETECTED)
6306 intel_hdmi_init(dev, HDMIC);
6307
6308 if (I915_READ(HDMID) & PORT_DETECTED)
6309 intel_hdmi_init(dev, HDMID);
6310
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006311 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6312 intel_dp_init(dev, PCH_DP_C);
6313
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006314 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006315 intel_dp_init(dev, PCH_DP_D);
6316
Zhenyu Wang103a1962009-11-27 11:44:36 +08006317 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08006318 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08006319
Eric Anholt725e30a2009-01-22 13:01:02 -08006320 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006321 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006322 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006323 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6324 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006325 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006326 }
Ma Ling27185ae2009-08-24 13:50:23 +08006327
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006328 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6329 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006330 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006331 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006332 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006333
6334 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006335
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006336 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6337 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006338 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006339 }
Ma Ling27185ae2009-08-24 13:50:23 +08006340
6341 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6342
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006343 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6344 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006345 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006346 }
6347 if (SUPPORTS_INTEGRATED_DP(dev)) {
6348 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006349 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006350 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006351 }
Ma Ling27185ae2009-08-24 13:50:23 +08006352
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006353 if (SUPPORTS_INTEGRATED_DP(dev) &&
6354 (I915_READ(DP_D) & DP_DETECTED)) {
6355 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006356 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006357 }
Eric Anholtbad720f2009-10-22 16:11:14 -07006358 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006359 intel_dvo_init(dev);
6360
Zhenyu Wang103a1962009-11-27 11:44:36 +08006361 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006362 intel_tv_init(dev);
6363
Chris Wilson4ef69c72010-09-09 15:14:28 +01006364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6365 encoder->base.possible_crtcs = encoder->crtc_mask;
6366 encoder->base.possible_clones =
6367 intel_encoder_clones(dev, encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08006368 }
Chris Wilson47356eb2011-01-11 17:06:04 +00006369
6370 intel_panel_setup_backlight(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006371}
6372
6373static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6374{
6375 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08006376
6377 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006378 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08006379
6380 kfree(intel_fb);
6381}
6382
6383static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00006384 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006385 unsigned int *handle)
6386{
6387 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006388 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006389
Chris Wilson05394f32010-11-08 19:18:58 +00006390 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08006391}
6392
6393static const struct drm_framebuffer_funcs intel_fb_funcs = {
6394 .destroy = intel_user_framebuffer_destroy,
6395 .create_handle = intel_user_framebuffer_create_handle,
6396};
6397
Dave Airlie38651672010-03-30 05:34:13 +00006398int intel_framebuffer_init(struct drm_device *dev,
6399 struct intel_framebuffer *intel_fb,
6400 struct drm_mode_fb_cmd *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00006401 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08006402{
Jesse Barnes79e53942008-11-07 14:24:08 -08006403 int ret;
6404
Chris Wilson05394f32010-11-08 19:18:58 +00006405 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01006406 return -EINVAL;
6407
6408 if (mode_cmd->pitch & 63)
6409 return -EINVAL;
6410
6411 switch (mode_cmd->bpp) {
6412 case 8:
6413 case 16:
6414 case 24:
6415 case 32:
6416 break;
6417 default:
6418 return -EINVAL;
6419 }
6420
Jesse Barnes79e53942008-11-07 14:24:08 -08006421 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6422 if (ret) {
6423 DRM_ERROR("framebuffer init failed %d\n", ret);
6424 return ret;
6425 }
6426
6427 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08006428 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006429 return 0;
6430}
6431
Jesse Barnes79e53942008-11-07 14:24:08 -08006432static struct drm_framebuffer *
6433intel_user_framebuffer_create(struct drm_device *dev,
6434 struct drm_file *filp,
6435 struct drm_mode_fb_cmd *mode_cmd)
6436{
Chris Wilson05394f32010-11-08 19:18:58 +00006437 struct drm_i915_gem_object *obj;
Dave Airlie38651672010-03-30 05:34:13 +00006438 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006439 int ret;
6440
Chris Wilson05394f32010-11-08 19:18:58 +00006441 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
Jesse Barnes79e53942008-11-07 14:24:08 -08006442 if (!obj)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006443 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08006444
Dave Airlie38651672010-03-30 05:34:13 +00006445 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6446 if (!intel_fb)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006447 return ERR_PTR(-ENOMEM);
Dave Airlie38651672010-03-30 05:34:13 +00006448
Chris Wilson05394f32010-11-08 19:18:58 +00006449 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08006450 if (ret) {
Chris Wilson05394f32010-11-08 19:18:58 +00006451 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie38651672010-03-30 05:34:13 +00006452 kfree(intel_fb);
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006453 return ERR_PTR(ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08006454 }
6455
Dave Airlie38651672010-03-30 05:34:13 +00006456 return &intel_fb->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006457}
6458
Jesse Barnes79e53942008-11-07 14:24:08 -08006459static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006460 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00006461 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08006462};
6463
Chris Wilson05394f32010-11-08 19:18:58 +00006464static struct drm_i915_gem_object *
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006465intel_alloc_context_page(struct drm_device *dev)
Chris Wilson9ea8d052010-01-04 18:57:56 +00006466{
Chris Wilson05394f32010-11-08 19:18:58 +00006467 struct drm_i915_gem_object *ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006468 int ret;
6469
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006470 ctx = i915_gem_alloc_object(dev, 4096);
6471 if (!ctx) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00006472 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6473 return NULL;
6474 }
6475
6476 mutex_lock(&dev->struct_mutex);
Daniel Vetter75e9e912010-11-04 17:11:09 +01006477 ret = i915_gem_object_pin(ctx, 4096, true);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006478 if (ret) {
6479 DRM_ERROR("failed to pin power context: %d\n", ret);
6480 goto err_unref;
6481 }
6482
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006483 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006484 if (ret) {
6485 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6486 goto err_unpin;
6487 }
6488 mutex_unlock(&dev->struct_mutex);
6489
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006490 return ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006491
6492err_unpin:
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006493 i915_gem_object_unpin(ctx);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006494err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00006495 drm_gem_object_unreference(&ctx->base);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006496 mutex_unlock(&dev->struct_mutex);
6497 return NULL;
6498}
6499
Jesse Barnes7648fa92010-05-20 14:28:11 -07006500bool ironlake_set_drps(struct drm_device *dev, u8 val)
6501{
6502 struct drm_i915_private *dev_priv = dev->dev_private;
6503 u16 rgvswctl;
6504
6505 rgvswctl = I915_READ16(MEMSWCTL);
6506 if (rgvswctl & MEMCTL_CMD_STS) {
6507 DRM_DEBUG("gpu busy, RCS change rejected\n");
6508 return false; /* still busy with another command */
6509 }
6510
6511 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6512 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6513 I915_WRITE16(MEMSWCTL, rgvswctl);
6514 POSTING_READ16(MEMSWCTL);
6515
6516 rgvswctl |= MEMCTL_CMD_STS;
6517 I915_WRITE16(MEMSWCTL, rgvswctl);
6518
6519 return true;
6520}
6521
Jesse Barnesf97108d2010-01-29 11:27:07 -08006522void ironlake_enable_drps(struct drm_device *dev)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006525 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006526 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08006527
Jesse Barnesea056c12010-09-10 10:02:13 -07006528 /* Enable temp reporting */
6529 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6530 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6531
Jesse Barnesf97108d2010-01-29 11:27:07 -08006532 /* 100ms RC evaluation intervals */
6533 I915_WRITE(RCUPEI, 100000);
6534 I915_WRITE(RCDNEI, 100000);
6535
6536 /* Set max/min thresholds to 90ms and 80ms respectively */
6537 I915_WRITE(RCBMAXAVG, 90000);
6538 I915_WRITE(RCBMINAVG, 80000);
6539
6540 I915_WRITE(MEMIHYST, 1);
6541
6542 /* Set up min, max, and cur for interrupt handling */
6543 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6544 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6545 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6546 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006547
Jesse Barnesf97108d2010-01-29 11:27:07 -08006548 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6549 PXVFREQ_PX_SHIFT;
6550
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006551 dev_priv->fmax = fmax; /* IPS callback will increase this */
Jesse Barnes7648fa92010-05-20 14:28:11 -07006552 dev_priv->fstart = fstart;
6553
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006554 dev_priv->max_delay = fstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08006555 dev_priv->min_delay = fmin;
6556 dev_priv->cur_delay = fstart;
6557
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006558 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6559 fmax, fmin, fstart);
Jesse Barnes7648fa92010-05-20 14:28:11 -07006560
Jesse Barnesf97108d2010-01-29 11:27:07 -08006561 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6562
6563 /*
6564 * Interrupts will be enabled in ironlake_irq_postinstall
6565 */
6566
6567 I915_WRITE(VIDSTART, vstart);
6568 POSTING_READ(VIDSTART);
6569
6570 rgvmodectl |= MEMMODE_SWMODE_EN;
6571 I915_WRITE(MEMMODECTL, rgvmodectl);
6572
Chris Wilson481b6af2010-08-23 17:43:35 +01006573 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Chris Wilson913d8d12010-08-07 11:01:35 +01006574 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08006575 msleep(1);
6576
Jesse Barnes7648fa92010-05-20 14:28:11 -07006577 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006578
Jesse Barnes7648fa92010-05-20 14:28:11 -07006579 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6580 I915_READ(0x112e0);
6581 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6582 dev_priv->last_count2 = I915_READ(0x112f4);
6583 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006584}
6585
6586void ironlake_disable_drps(struct drm_device *dev)
6587{
6588 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006589 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006590
6591 /* Ack interrupts, disable EFC interrupt */
6592 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6593 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6594 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6595 I915_WRITE(DEIIR, DE_PCU_EVENT);
6596 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6597
6598 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07006599 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006600 msleep(1);
6601 rgvswctl |= MEMCTL_CMD_STS;
6602 I915_WRITE(MEMSWCTL, rgvswctl);
6603 msleep(1);
6604
6605}
6606
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006607void gen6_set_rps(struct drm_device *dev, u8 val)
6608{
6609 struct drm_i915_private *dev_priv = dev->dev_private;
6610 u32 swreq;
6611
6612 swreq = (val & 0x3ff) << 25;
6613 I915_WRITE(GEN6_RPNSWREQ, swreq);
6614}
6615
6616void gen6_disable_rps(struct drm_device *dev)
6617{
6618 struct drm_i915_private *dev_priv = dev->dev_private;
6619
6620 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6621 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6622 I915_WRITE(GEN6_PMIER, 0);
6623 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6624}
6625
Jesse Barnes7648fa92010-05-20 14:28:11 -07006626static unsigned long intel_pxfreq(u32 vidfreq)
6627{
6628 unsigned long freq;
6629 int div = (vidfreq & 0x3f0000) >> 16;
6630 int post = (vidfreq & 0x3000) >> 12;
6631 int pre = (vidfreq & 0x7);
6632
6633 if (!pre)
6634 return 0;
6635
6636 freq = ((div * 133333) / ((1<<post) * pre));
6637
6638 return freq;
6639}
6640
6641void intel_init_emon(struct drm_device *dev)
6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 u32 lcfuse;
6645 u8 pxw[16];
6646 int i;
6647
6648 /* Disable to program */
6649 I915_WRITE(ECR, 0);
6650 POSTING_READ(ECR);
6651
6652 /* Program energy weights for various events */
6653 I915_WRITE(SDEW, 0x15040d00);
6654 I915_WRITE(CSIEW0, 0x007f0000);
6655 I915_WRITE(CSIEW1, 0x1e220004);
6656 I915_WRITE(CSIEW2, 0x04000004);
6657
6658 for (i = 0; i < 5; i++)
6659 I915_WRITE(PEW + (i * 4), 0);
6660 for (i = 0; i < 3; i++)
6661 I915_WRITE(DEW + (i * 4), 0);
6662
6663 /* Program P-state weights to account for frequency power adjustment */
6664 for (i = 0; i < 16; i++) {
6665 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6666 unsigned long freq = intel_pxfreq(pxvidfreq);
6667 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6668 PXVFREQ_PX_SHIFT;
6669 unsigned long val;
6670
6671 val = vid * vid;
6672 val *= (freq / 1000);
6673 val *= 255;
6674 val /= (127*127*900);
6675 if (val > 0xff)
6676 DRM_ERROR("bad pxval: %ld\n", val);
6677 pxw[i] = val;
6678 }
6679 /* Render standby states get 0 weight */
6680 pxw[14] = 0;
6681 pxw[15] = 0;
6682
6683 for (i = 0; i < 4; i++) {
6684 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6685 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6686 I915_WRITE(PXW + (i * 4), val);
6687 }
6688
6689 /* Adjust magic regs to magic values (more experimental results) */
6690 I915_WRITE(OGW0, 0);
6691 I915_WRITE(OGW1, 0);
6692 I915_WRITE(EG0, 0x00007f00);
6693 I915_WRITE(EG1, 0x0000000e);
6694 I915_WRITE(EG2, 0x000e0000);
6695 I915_WRITE(EG3, 0x68000300);
6696 I915_WRITE(EG4, 0x42000000);
6697 I915_WRITE(EG5, 0x00140031);
6698 I915_WRITE(EG6, 0);
6699 I915_WRITE(EG7, 0);
6700
6701 for (i = 0; i < 8; i++)
6702 I915_WRITE(PXWL + (i * 4), 0);
6703
6704 /* Enable PMON + select events */
6705 I915_WRITE(ECR, 0x80000019);
6706
6707 lcfuse = I915_READ(LCFUSE02);
6708
6709 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6710}
6711
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006712void gen6_enable_rps(struct drm_i915_private *dev_priv)
Chris Wilson8fd26852010-12-08 18:40:43 +00006713{
Jesse Barnesa6044e22010-12-20 11:34:20 -08006714 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6715 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6716 u32 pcu_mbox;
6717 int cur_freq, min_freq, max_freq;
Chris Wilson8fd26852010-12-08 18:40:43 +00006718 int i;
6719
6720 /* Here begins a magic sequence of register writes to enable
6721 * auto-downclocking.
6722 *
6723 * Perhaps there might be some value in exposing these to
6724 * userspace...
6725 */
6726 I915_WRITE(GEN6_RC_STATE, 0);
6727 __gen6_force_wake_get(dev_priv);
6728
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006729 /* disable the counters and set deterministic thresholds */
Chris Wilson8fd26852010-12-08 18:40:43 +00006730 I915_WRITE(GEN6_RC_CONTROL, 0);
6731
6732 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6733 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6734 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6735 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6736 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6737
6738 for (i = 0; i < I915_NUM_RINGS; i++)
6739 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6740
6741 I915_WRITE(GEN6_RC_SLEEP, 0);
6742 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6743 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6744 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6745 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6746
6747 I915_WRITE(GEN6_RC_CONTROL,
6748 GEN6_RC_CTL_RC6p_ENABLE |
6749 GEN6_RC_CTL_RC6_ENABLE |
Chris Wilson9c3d2f72010-12-17 10:54:26 +00006750 GEN6_RC_CTL_EI_MODE(1) |
Chris Wilson8fd26852010-12-08 18:40:43 +00006751 GEN6_RC_CTL_HW_ENABLE);
6752
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006753 I915_WRITE(GEN6_RPNSWREQ,
Chris Wilson8fd26852010-12-08 18:40:43 +00006754 GEN6_FREQUENCY(10) |
6755 GEN6_OFFSET(0) |
6756 GEN6_AGGRESSIVE_TURBO);
6757 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6758 GEN6_FREQUENCY(12));
6759
6760 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6761 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6762 18 << 24 |
6763 6 << 16);
Jesse Barnesccab5c82011-01-18 15:49:25 -08006764 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6765 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00006766 I915_WRITE(GEN6_RP_UP_EI, 100000);
Jesse Barnesccab5c82011-01-18 15:49:25 -08006767 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00006768 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6769 I915_WRITE(GEN6_RP_CONTROL,
6770 GEN6_RP_MEDIA_TURBO |
6771 GEN6_RP_USE_NORMAL_FREQ |
6772 GEN6_RP_MEDIA_IS_GFX |
6773 GEN6_RP_ENABLE |
Jesse Barnesccab5c82011-01-18 15:49:25 -08006774 GEN6_RP_UP_BUSY_AVG |
6775 GEN6_RP_DOWN_IDLE_CONT);
Chris Wilson8fd26852010-12-08 18:40:43 +00006776
6777 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6778 500))
6779 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6780
6781 I915_WRITE(GEN6_PCODE_DATA, 0);
6782 I915_WRITE(GEN6_PCODE_MAILBOX,
6783 GEN6_PCODE_READY |
6784 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6785 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6786 500))
6787 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6788
Jesse Barnesa6044e22010-12-20 11:34:20 -08006789 min_freq = (rp_state_cap & 0xff0000) >> 16;
6790 max_freq = rp_state_cap & 0xff;
6791 cur_freq = (gt_perf_status & 0xff00) >> 8;
6792
6793 /* Check for overclock support */
6794 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6795 500))
6796 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6797 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6798 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6799 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6800 500))
6801 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6802 if (pcu_mbox & (1<<31)) { /* OC supported */
6803 max_freq = pcu_mbox & 0xff;
6804 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6805 }
6806
6807 /* In units of 100MHz */
6808 dev_priv->max_delay = max_freq;
6809 dev_priv->min_delay = min_freq;
6810 dev_priv->cur_delay = cur_freq;
6811
Chris Wilson8fd26852010-12-08 18:40:43 +00006812 /* requires MSI enabled */
6813 I915_WRITE(GEN6_PMIER,
6814 GEN6_PM_MBOX_EVENT |
6815 GEN6_PM_THERMAL_EVENT |
6816 GEN6_PM_RP_DOWN_TIMEOUT |
6817 GEN6_PM_RP_UP_THRESHOLD |
6818 GEN6_PM_RP_DOWN_THRESHOLD |
6819 GEN6_PM_RP_UP_EI_EXPIRED |
6820 GEN6_PM_RP_DOWN_EI_EXPIRED);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006821 I915_WRITE(GEN6_PMIMR, 0);
6822 /* enable all PM interrupts */
6823 I915_WRITE(GEN6_PMINTRMSK, 0);
Chris Wilson8fd26852010-12-08 18:40:43 +00006824
6825 __gen6_force_wake_put(dev_priv);
6826}
6827
Chris Wilson0cdab212010-12-05 17:27:06 +00006828void intel_enable_clock_gating(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07006829{
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831
6832 /*
6833 * Disable clock gating reported to work incorrectly according to the
6834 * specs, but enable as much else as we can.
6835 */
Eric Anholtbad720f2009-10-22 16:11:14 -07006836 if (HAS_PCH_SPLIT(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07006837 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6838
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006839 if (IS_GEN5(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07006840 /* Required for FBC */
Jesse Barnes1ffa3252011-01-17 13:35:57 -08006841 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6842 DPFCRUNIT_CLOCK_GATE_DISABLE |
6843 DPFDUNIT_CLOCK_GATE_DISABLE;
Eric Anholt8956c8b2010-03-18 13:21:14 -07006844 /* Required for CxSR */
6845 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6846
6847 I915_WRITE(PCH_3DCGDIS0,
6848 MARIUNIT_CLOCK_GATE_DISABLE |
6849 SVSMUNIT_CLOCK_GATE_DISABLE);
Eric Anholt06f37752010-12-14 10:06:46 -08006850 I915_WRITE(PCH_3DCGDIS1,
6851 VFMUNIT_CLOCK_GATE_DISABLE);
Eric Anholt8956c8b2010-03-18 13:21:14 -07006852 }
6853
6854 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006855
6856 /*
Jesse Barnes382b0932010-10-07 16:01:25 -07006857 * On Ibex Peak and Cougar Point, we need to disable clock
6858 * gating for the panel power sequencer or it will fail to
6859 * start up when no ports are active.
6860 */
6861 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6862
6863 /*
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006864 * According to the spec the following bits should be set in
6865 * order to enable memory self-refresh
6866 * The bit 22/21 of 0x42004
6867 * The bit 5 of 0x42020
6868 * The bit 15 of 0x45000
6869 */
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006870 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006871 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6872 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6873 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6874 I915_WRITE(ILK_DSPCLK_GATE,
6875 (I915_READ(ILK_DSPCLK_GATE) |
6876 ILK_DPARB_CLK_GATE));
6877 I915_WRITE(DISP_ARB_CTL,
6878 (I915_READ(DISP_ARB_CTL) |
6879 DISP_FBC_WM_DIS));
Yuanhan Liu13982612010-12-15 15:42:31 +08006880 I915_WRITE(WM3_LP_ILK, 0);
6881 I915_WRITE(WM2_LP_ILK, 0);
6882 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006883 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08006884 /*
6885 * Based on the document from hardware guys the following bits
6886 * should be set unconditionally in order to enable FBC.
6887 * The bit 22 of 0x42000
6888 * The bit 22 of 0x42004
6889 * The bit 7,8,9 of 0x42020.
6890 */
6891 if (IS_IRONLAKE_M(dev)) {
6892 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6893 I915_READ(ILK_DISPLAY_CHICKEN1) |
6894 ILK_FBCQ_DIS);
6895 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6896 I915_READ(ILK_DISPLAY_CHICKEN2) |
6897 ILK_DPARB_GATE);
6898 I915_WRITE(ILK_DSPCLK_GATE,
6899 I915_READ(ILK_DSPCLK_GATE) |
6900 ILK_DPFC_DIS1 |
6901 ILK_DPFC_DIS2 |
6902 ILK_CLK_FBC);
6903 }
Eric Anholtde6e2ea2010-11-06 14:53:32 -07006904
Eric Anholt67e92af2010-11-06 14:53:33 -07006905 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6906 I915_READ(ILK_DISPLAY_CHICKEN2) |
6907 ILK_ELPIN_409_SELECT);
6908
Eric Anholtde6e2ea2010-11-06 14:53:32 -07006909 if (IS_GEN5(dev)) {
6910 I915_WRITE(_3D_CHICKEN2,
6911 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6912 _3D_CHICKEN2_WM_READ_PIPELINED);
6913 }
Chris Wilson8fd26852010-12-08 18:40:43 +00006914
Yuanhan Liu13982612010-12-15 15:42:31 +08006915 if (IS_GEN6(dev)) {
6916 I915_WRITE(WM3_LP_ILK, 0);
6917 I915_WRITE(WM2_LP_ILK, 0);
6918 I915_WRITE(WM1_LP_ILK, 0);
6919
6920 /*
6921 * According to the spec the following bits should be
6922 * set in order to enable memory self-refresh and fbc:
6923 * The bit21 and bit22 of 0x42000
6924 * The bit21 and bit22 of 0x42004
6925 * The bit5 and bit7 of 0x42020
6926 * The bit14 of 0x70180
6927 * The bit14 of 0x71180
6928 */
6929 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6930 I915_READ(ILK_DISPLAY_CHICKEN1) |
6931 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6932 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6933 I915_READ(ILK_DISPLAY_CHICKEN2) |
6934 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6935 I915_WRITE(ILK_DSPCLK_GATE,
6936 I915_READ(ILK_DSPCLK_GATE) |
6937 ILK_DPARB_CLK_GATE |
6938 ILK_DPFD_CLK_GATE);
6939
6940 I915_WRITE(DSPACNTR,
6941 I915_READ(DSPACNTR) |
6942 DISPPLANE_TRICKLE_FEED_DISABLE);
6943 I915_WRITE(DSPBCNTR,
6944 I915_READ(DSPBCNTR) |
6945 DISPPLANE_TRICKLE_FEED_DISABLE);
6946 }
Zhenyu Wangc03342f2009-09-29 11:01:23 +08006947 } else if (IS_G4X(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006948 uint32_t dspclk_gate;
6949 I915_WRITE(RENCLK_GATE_D1, 0);
6950 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6951 GS_UNIT_CLOCK_GATE_DISABLE |
6952 CL_UNIT_CLOCK_GATE_DISABLE);
6953 I915_WRITE(RAMCLK_GATE_D, 0);
6954 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6955 OVRUNIT_CLOCK_GATE_DISABLE |
6956 OVCUNIT_CLOCK_GATE_DISABLE;
6957 if (IS_GM45(dev))
6958 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6959 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006960 } else if (IS_CRESTLINE(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006961 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6962 I915_WRITE(RENCLK_GATE_D2, 0);
6963 I915_WRITE(DSPCLK_GATE_D, 0);
6964 I915_WRITE(RAMCLK_GATE_D, 0);
6965 I915_WRITE16(DEUC, 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006966 } else if (IS_BROADWATER(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006967 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6968 I965_RCC_CLOCK_GATE_DISABLE |
6969 I965_RCPB_CLOCK_GATE_DISABLE |
6970 I965_ISC_CLOCK_GATE_DISABLE |
6971 I965_FBC_CLOCK_GATE_DISABLE);
6972 I915_WRITE(RENCLK_GATE_D2, 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006973 } else if (IS_GEN3(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006974 u32 dstate = I915_READ(D_STATE);
6975
6976 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6977 DSTATE_DOT_CLOCK_GATING;
6978 I915_WRITE(D_STATE, dstate);
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02006979 } else if (IS_I85X(dev) || IS_I865G(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07006980 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6981 } else if (IS_I830(dev)) {
6982 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6983 }
6984}
6985
Chris Wilson0cdab212010-12-05 17:27:06 +00006986void intel_disable_clock_gating(struct drm_device *dev)
6987{
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989
6990 if (dev_priv->renderctx) {
6991 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6992
6993 I915_WRITE(CCID, 0);
6994 POSTING_READ(CCID);
6995
6996 i915_gem_object_unpin(obj);
6997 drm_gem_object_unreference(&obj->base);
6998 dev_priv->renderctx = NULL;
6999 }
7000
7001 if (dev_priv->pwrctx) {
7002 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
7003
7004 I915_WRITE(PWRCTXA, 0);
7005 POSTING_READ(PWRCTXA);
7006
7007 i915_gem_object_unpin(obj);
7008 drm_gem_object_unreference(&obj->base);
7009 dev_priv->pwrctx = NULL;
7010 }
7011}
7012
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007013static void ironlake_disable_rc6(struct drm_device *dev)
7014{
7015 struct drm_i915_private *dev_priv = dev->dev_private;
7016
7017 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7018 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7019 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7020 10);
7021 POSTING_READ(CCID);
7022 I915_WRITE(PWRCTXA, 0);
7023 POSTING_READ(PWRCTXA);
7024 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7025 POSTING_READ(RSTDBYCTL);
7026 i915_gem_object_unpin(dev_priv->renderctx);
7027 drm_gem_object_unreference(&dev_priv->renderctx->base);
7028 dev_priv->renderctx = NULL;
7029 i915_gem_object_unpin(dev_priv->pwrctx);
7030 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7031 dev_priv->pwrctx = NULL;
7032}
7033
7034void ironlake_enable_rc6(struct drm_device *dev)
7035{
7036 struct drm_i915_private *dev_priv = dev->dev_private;
7037 int ret;
7038
7039 /*
7040 * GPU can automatically power down the render unit if given a page
7041 * to save state.
7042 */
7043 ret = BEGIN_LP_RING(6);
7044 if (ret) {
7045 ironlake_disable_rc6(dev);
7046 return;
7047 }
7048 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7049 OUT_RING(MI_SET_CONTEXT);
7050 OUT_RING(dev_priv->renderctx->gtt_offset |
7051 MI_MM_SPACE_GTT |
7052 MI_SAVE_EXT_STATE_EN |
7053 MI_RESTORE_EXT_STATE_EN |
7054 MI_RESTORE_INHIBIT);
7055 OUT_RING(MI_SUSPEND_FLUSH);
7056 OUT_RING(MI_NOOP);
7057 OUT_RING(MI_FLUSH);
7058 ADVANCE_LP_RING();
7059
7060 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7061 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7062}
7063
Jesse Barnese70236a2009-09-21 10:42:27 -07007064/* Set up chip specific display functions */
7065static void intel_init_display(struct drm_device *dev)
7066{
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068
7069 /* We always want a DPMS function */
Eric Anholtbad720f2009-10-22 16:11:14 -07007070 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007071 dev_priv->display.dpms = ironlake_crtc_dpms;
Jesse Barnese70236a2009-09-21 10:42:27 -07007072 else
7073 dev_priv->display.dpms = i9xx_crtc_dpms;
7074
Adam Jacksonee5382a2010-04-23 11:17:39 -04007075 if (I915_HAS_FBC(dev)) {
Yuanhan Liu9c04f012010-12-15 15:42:32 +08007076 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08007077 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7078 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7079 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7080 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07007081 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7082 dev_priv->display.enable_fbc = g4x_enable_fbc;
7083 dev_priv->display.disable_fbc = g4x_disable_fbc;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007084 } else if (IS_CRESTLINE(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007085 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7086 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7087 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7088 }
Jesse Barnes74dff282009-09-14 15:39:40 -07007089 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07007090 }
7091
7092 /* Returns the core display clock speed */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007093 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07007094 dev_priv->display.get_display_clock_speed =
7095 i945_get_display_clock_speed;
7096 else if (IS_I915G(dev))
7097 dev_priv->display.get_display_clock_speed =
7098 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007099 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007100 dev_priv->display.get_display_clock_speed =
7101 i9xx_misc_get_display_clock_speed;
7102 else if (IS_I915GM(dev))
7103 dev_priv->display.get_display_clock_speed =
7104 i915gm_get_display_clock_speed;
7105 else if (IS_I865G(dev))
7106 dev_priv->display.get_display_clock_speed =
7107 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02007108 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007109 dev_priv->display.get_display_clock_speed =
7110 i855_get_display_clock_speed;
7111 else /* 852, 830 */
7112 dev_priv->display.get_display_clock_speed =
7113 i830_get_display_clock_speed;
7114
7115 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007116 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01007117 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007118 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7119 dev_priv->display.update_wm = ironlake_update_wm;
7120 else {
7121 DRM_DEBUG_KMS("Failed to get proper latency. "
7122 "Disable CxSR\n");
7123 dev_priv->display.update_wm = NULL;
7124 }
Yuanhan Liu13982612010-12-15 15:42:31 +08007125 } else if (IS_GEN6(dev)) {
7126 if (SNB_READ_WM0_LATENCY()) {
7127 dev_priv->display.update_wm = sandybridge_update_wm;
7128 } else {
7129 DRM_DEBUG_KMS("Failed to read display plane latency. "
7130 "Disable CxSR\n");
7131 dev_priv->display.update_wm = NULL;
7132 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007133 } else
7134 dev_priv->display.update_wm = NULL;
7135 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08007136 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08007137 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08007138 dev_priv->fsb_freq,
7139 dev_priv->mem_freq)) {
7140 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08007141 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08007142 "disabling CxSR\n",
Li Peng95534262010-05-18 18:58:44 +08007143 (dev_priv->is_ddr3 == 1) ? "3": "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08007144 dev_priv->fsb_freq, dev_priv->mem_freq);
7145 /* Disable CxSR and never update its watermark again */
7146 pineview_disable_cxsr(dev);
7147 dev_priv->display.update_wm = NULL;
7148 } else
7149 dev_priv->display.update_wm = pineview_update_wm;
7150 } else if (IS_G4X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007151 dev_priv->display.update_wm = g4x_update_wm;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007152 else if (IS_GEN4(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007153 dev_priv->display.update_wm = i965_update_wm;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007154 else if (IS_GEN3(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007155 dev_priv->display.update_wm = i9xx_update_wm;
7156 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04007157 } else if (IS_I85X(dev)) {
7158 dev_priv->display.update_wm = i9xx_update_wm;
7159 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07007160 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04007161 dev_priv->display.update_wm = i830_update_wm;
7162 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007163 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7164 else
7165 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07007166 }
7167}
7168
Jesse Barnesb690e962010-07-19 13:53:12 -07007169/*
7170 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7171 * resume, or other times. This quirk makes sure that's the case for
7172 * affected systems.
7173 */
7174static void quirk_pipea_force (struct drm_device *dev)
7175{
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177
7178 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7179 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7180}
7181
7182struct intel_quirk {
7183 int device;
7184 int subsystem_vendor;
7185 int subsystem_device;
7186 void (*hook)(struct drm_device *dev);
7187};
7188
7189struct intel_quirk intel_quirks[] = {
7190 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7191 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7192 /* HP Mini needs pipe A force quirk (LP: #322104) */
7193 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7194
7195 /* Thinkpad R31 needs pipe A force quirk */
7196 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7197 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7198 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7199
7200 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7201 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7202 /* ThinkPad X40 needs pipe A force quirk */
7203
7204 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7205 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7206
7207 /* 855 & before need to leave pipe A & dpll A up */
7208 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7209 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7210};
7211
7212static void intel_init_quirks(struct drm_device *dev)
7213{
7214 struct pci_dev *d = dev->pdev;
7215 int i;
7216
7217 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7218 struct intel_quirk *q = &intel_quirks[i];
7219
7220 if (d->device == q->device &&
7221 (d->subsystem_vendor == q->subsystem_vendor ||
7222 q->subsystem_vendor == PCI_ANY_ID) &&
7223 (d->subsystem_device == q->subsystem_device ||
7224 q->subsystem_device == PCI_ANY_ID))
7225 q->hook(dev);
7226 }
7227}
7228
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007229/* Disable the VGA plane that we never use */
7230static void i915_disable_vga(struct drm_device *dev)
7231{
7232 struct drm_i915_private *dev_priv = dev->dev_private;
7233 u8 sr1;
7234 u32 vga_reg;
7235
7236 if (HAS_PCH_SPLIT(dev))
7237 vga_reg = CPU_VGACNTRL;
7238 else
7239 vga_reg = VGACNTRL;
7240
7241 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7242 outb(1, VGA_SR_INDEX);
7243 sr1 = inb(VGA_SR_DATA);
7244 outb(sr1 | 1<<5, VGA_SR_DATA);
7245 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7246 udelay(300);
7247
7248 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7249 POSTING_READ(vga_reg);
7250}
7251
Jesse Barnes79e53942008-11-07 14:24:08 -08007252void intel_modeset_init(struct drm_device *dev)
7253{
Jesse Barnes652c3932009-08-17 13:31:43 -07007254 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007255 int i;
7256
7257 drm_mode_config_init(dev);
7258
7259 dev->mode_config.min_width = 0;
7260 dev->mode_config.min_height = 0;
7261
7262 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7263
Jesse Barnesb690e962010-07-19 13:53:12 -07007264 intel_init_quirks(dev);
7265
Jesse Barnese70236a2009-09-21 10:42:27 -07007266 intel_init_display(dev);
7267
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007268 if (IS_GEN2(dev)) {
7269 dev->mode_config.max_width = 2048;
7270 dev->mode_config.max_height = 2048;
7271 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07007272 dev->mode_config.max_width = 4096;
7273 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08007274 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007275 dev->mode_config.max_width = 8192;
7276 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08007277 }
Chris Wilson35c30472010-12-22 14:07:12 +00007278 dev->mode_config.fb_base = dev->agp->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08007279
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007280 if (IS_MOBILE(dev) || !IS_GEN2(dev))
Dave Airliea3524f12010-06-06 18:59:41 +10007281 dev_priv->num_pipe = 2;
Jesse Barnes79e53942008-11-07 14:24:08 -08007282 else
Dave Airliea3524f12010-06-06 18:59:41 +10007283 dev_priv->num_pipe = 1;
Zhao Yakui28c97732009-10-09 11:39:41 +08007284 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10007285 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08007286
Dave Airliea3524f12010-06-06 18:59:41 +10007287 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007288 intel_crtc_init(dev, i);
7289 }
7290
7291 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007292
Chris Wilson0cdab212010-12-05 17:27:06 +00007293 intel_enable_clock_gating(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007294
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007295 /* Just disable it once at startup */
7296 i915_disable_vga(dev);
7297
Jesse Barnes7648fa92010-05-20 14:28:11 -07007298 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08007299 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07007300 intel_init_emon(dev);
7301 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08007302
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007303 if (IS_GEN6(dev))
7304 gen6_enable_rps(dev_priv);
7305
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007306 if (IS_IRONLAKE_M(dev)) {
7307 dev_priv->renderctx = intel_alloc_context_page(dev);
7308 if (!dev_priv->renderctx)
7309 goto skip_rc6;
7310 dev_priv->pwrctx = intel_alloc_context_page(dev);
7311 if (!dev_priv->pwrctx) {
7312 i915_gem_object_unpin(dev_priv->renderctx);
7313 drm_gem_object_unreference(&dev_priv->renderctx->base);
7314 dev_priv->renderctx = NULL;
7315 goto skip_rc6;
7316 }
7317 ironlake_enable_rc6(dev);
7318 }
7319
7320skip_rc6:
Jesse Barnes652c3932009-08-17 13:31:43 -07007321 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7322 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7323 (unsigned long)dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02007324
7325 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007326}
7327
7328void intel_modeset_cleanup(struct drm_device *dev)
7329{
Jesse Barnes652c3932009-08-17 13:31:43 -07007330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 struct drm_crtc *crtc;
7332 struct intel_crtc *intel_crtc;
7333
Keith Packardf87ea762010-10-03 19:36:26 -07007334 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007335 mutex_lock(&dev->struct_mutex);
7336
Jesse Barnes723bfd72010-10-07 16:01:13 -07007337 intel_unregister_dsm_handler();
7338
7339
Jesse Barnes652c3932009-08-17 13:31:43 -07007340 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7341 /* Skip inactive CRTCs */
7342 if (!crtc->fb)
7343 continue;
7344
7345 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02007346 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007347 }
7348
Jesse Barnese70236a2009-09-21 10:42:27 -07007349 if (dev_priv->display.disable_fbc)
7350 dev_priv->display.disable_fbc(dev);
7351
Jesse Barnesf97108d2010-01-29 11:27:07 -08007352 if (IS_IRONLAKE_M(dev))
7353 ironlake_disable_drps(dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007354 if (IS_GEN6(dev))
7355 gen6_disable_rps(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007356
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007357 if (IS_IRONLAKE_M(dev))
7358 ironlake_disable_rc6(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00007359
Kristian Høgsberg69341a52009-11-11 12:19:17 -05007360 mutex_unlock(&dev->struct_mutex);
7361
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007362 /* Disable the irq before mode object teardown, for the irq might
7363 * enqueue unpin/hotplug work. */
7364 drm_irq_uninstall(dev);
7365 cancel_work_sync(&dev_priv->hotplug_work);
7366
Daniel Vetter3dec0092010-08-20 21:40:52 +02007367 /* Shut off idle work before the crtcs get freed. */
7368 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7369 intel_crtc = to_intel_crtc(crtc);
7370 del_timer_sync(&intel_crtc->idle_timer);
7371 }
7372 del_timer_sync(&dev_priv->idle_timer);
7373 cancel_work_sync(&dev_priv->idle_work);
7374
Jesse Barnes79e53942008-11-07 14:24:08 -08007375 drm_mode_config_cleanup(dev);
7376}
7377
Dave Airlie28d52042009-09-21 14:33:58 +10007378/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08007379 * Return which encoder is currently attached for connector.
7380 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01007381struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08007382{
Chris Wilsondf0e9242010-09-09 16:20:55 +01007383 return &intel_attached_encoder(connector)->base;
7384}
Jesse Barnes79e53942008-11-07 14:24:08 -08007385
Chris Wilsondf0e9242010-09-09 16:20:55 +01007386void intel_connector_attach_encoder(struct intel_connector *connector,
7387 struct intel_encoder *encoder)
7388{
7389 connector->encoder = encoder;
7390 drm_mode_connector_attach_encoder(&connector->base,
7391 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007392}
Dave Airlie28d52042009-09-21 14:33:58 +10007393
7394/*
7395 * set vga decode state - true == enable VGA decode
7396 */
7397int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7398{
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 u16 gmch_ctrl;
7401
7402 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7403 if (state)
7404 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7405 else
7406 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7407 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7408 return 0;
7409}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007410
7411#ifdef CONFIG_DEBUG_FS
7412#include <linux/seq_file.h>
7413
7414struct intel_display_error_state {
7415 struct intel_cursor_error_state {
7416 u32 control;
7417 u32 position;
7418 u32 base;
7419 u32 size;
7420 } cursor[2];
7421
7422 struct intel_pipe_error_state {
7423 u32 conf;
7424 u32 source;
7425
7426 u32 htotal;
7427 u32 hblank;
7428 u32 hsync;
7429 u32 vtotal;
7430 u32 vblank;
7431 u32 vsync;
7432 } pipe[2];
7433
7434 struct intel_plane_error_state {
7435 u32 control;
7436 u32 stride;
7437 u32 size;
7438 u32 pos;
7439 u32 addr;
7440 u32 surface;
7441 u32 tile_offset;
7442 } plane[2];
7443};
7444
7445struct intel_display_error_state *
7446intel_display_capture_error_state(struct drm_device *dev)
7447{
7448 drm_i915_private_t *dev_priv = dev->dev_private;
7449 struct intel_display_error_state *error;
7450 int i;
7451
7452 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7453 if (error == NULL)
7454 return NULL;
7455
7456 for (i = 0; i < 2; i++) {
7457 error->cursor[i].control = I915_READ(CURCNTR(i));
7458 error->cursor[i].position = I915_READ(CURPOS(i));
7459 error->cursor[i].base = I915_READ(CURBASE(i));
7460
7461 error->plane[i].control = I915_READ(DSPCNTR(i));
7462 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7463 error->plane[i].size = I915_READ(DSPSIZE(i));
7464 error->plane[i].pos= I915_READ(DSPPOS(i));
7465 error->plane[i].addr = I915_READ(DSPADDR(i));
7466 if (INTEL_INFO(dev)->gen >= 4) {
7467 error->plane[i].surface = I915_READ(DSPSURF(i));
7468 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7469 }
7470
7471 error->pipe[i].conf = I915_READ(PIPECONF(i));
7472 error->pipe[i].source = I915_READ(PIPESRC(i));
7473 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7474 error->pipe[i].hblank = I915_READ(HBLANK(i));
7475 error->pipe[i].hsync = I915_READ(HSYNC(i));
7476 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7477 error->pipe[i].vblank = I915_READ(VBLANK(i));
7478 error->pipe[i].vsync = I915_READ(VSYNC(i));
7479 }
7480
7481 return error;
7482}
7483
7484void
7485intel_display_print_error_state(struct seq_file *m,
7486 struct drm_device *dev,
7487 struct intel_display_error_state *error)
7488{
7489 int i;
7490
7491 for (i = 0; i < 2; i++) {
7492 seq_printf(m, "Pipe [%d]:\n", i);
7493 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7494 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7495 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7496 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7497 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7498 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7499 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7500 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7501
7502 seq_printf(m, "Plane [%d]:\n", i);
7503 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7504 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7505 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7506 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7507 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7508 if (INTEL_INFO(dev)->gen >= 4) {
7509 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7510 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7511 }
7512
7513 seq_printf(m, "Cursor [%d]:\n", i);
7514 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7515 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7516 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7517 }
7518}
7519#endif