blob: 3bc6ab56cf8b2ab5450f08cee4c57ed01fcf182d [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnesc1c7af62009-09-10 15:28:03 -070027#include <linux/module.h>
28#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080030#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070032#include <linux/vgaarb.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070037#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100038#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080039
40#include "drm_crtc_helper.h"
41
Zhenyu Wang32f9d652009-07-24 01:00:32 +080042#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
Jesse Barnes79e53942008-11-07 14:24:08 -080044bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080045static void intel_update_watermarks(struct drm_device *dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +020046static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010047static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080048
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080071typedef struct intel_limit intel_limit_t;
72struct intel_limit {
Jesse Barnes79e53942008-11-07 14:24:08 -080073 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
Ma Lingd4906092009-03-18 20:13:27 +080075 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
Jesse Barnes79e53942008-11-07 14:24:08 -080078
79#define I8XX_DOT_MIN 25000
80#define I8XX_DOT_MAX 350000
81#define I8XX_VCO_MIN 930000
82#define I8XX_VCO_MAX 1400000
83#define I8XX_N_MIN 3
84#define I8XX_N_MAX 16
85#define I8XX_M_MIN 96
86#define I8XX_M_MAX 140
87#define I8XX_M1_MIN 18
88#define I8XX_M1_MAX 26
89#define I8XX_M2_MIN 6
90#define I8XX_M2_MAX 16
91#define I8XX_P_MIN 4
92#define I8XX_P_MAX 128
93#define I8XX_P1_MIN 2
94#define I8XX_P1_MAX 33
95#define I8XX_P1_LVDS_MIN 1
96#define I8XX_P1_LVDS_MAX 6
97#define I8XX_P2_SLOW 4
98#define I8XX_P2_FAST 2
99#define I8XX_P2_LVDS_SLOW 14
ling.ma@intel.com0c2e3952009-07-17 11:44:30 +0800100#define I8XX_P2_LVDS_FAST 7
Jesse Barnes79e53942008-11-07 14:24:08 -0800101#define I8XX_P2_SLOW_LIMIT 165000
102
103#define I9XX_DOT_MIN 20000
104#define I9XX_DOT_MAX 400000
105#define I9XX_VCO_MIN 1400000
106#define I9XX_VCO_MAX 2800000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500107#define PINEVIEW_VCO_MIN 1700000
108#define PINEVIEW_VCO_MAX 3500000
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500109#define I9XX_N_MIN 1
110#define I9XX_N_MAX 6
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500111/* Pineview's Ncounter is a ring counter */
112#define PINEVIEW_N_MIN 3
113#define PINEVIEW_N_MAX 6
Jesse Barnes79e53942008-11-07 14:24:08 -0800114#define I9XX_M_MIN 70
115#define I9XX_M_MAX 120
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500116#define PINEVIEW_M_MIN 2
117#define PINEVIEW_M_MAX 256
Jesse Barnes79e53942008-11-07 14:24:08 -0800118#define I9XX_M1_MIN 10
Kristian Høgsbergf3cade52009-02-13 20:56:50 -0500119#define I9XX_M1_MAX 22
Jesse Barnes79e53942008-11-07 14:24:08 -0800120#define I9XX_M2_MIN 5
121#define I9XX_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500122/* Pineview M1 is reserved, and must be 0 */
123#define PINEVIEW_M1_MIN 0
124#define PINEVIEW_M1_MAX 0
125#define PINEVIEW_M2_MIN 0
126#define PINEVIEW_M2_MAX 254
Jesse Barnes79e53942008-11-07 14:24:08 -0800127#define I9XX_P_SDVO_DAC_MIN 5
128#define I9XX_P_SDVO_DAC_MAX 80
129#define I9XX_P_LVDS_MIN 7
130#define I9XX_P_LVDS_MAX 98
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500131#define PINEVIEW_P_LVDS_MIN 7
132#define PINEVIEW_P_LVDS_MAX 112
Jesse Barnes79e53942008-11-07 14:24:08 -0800133#define I9XX_P1_MIN 1
134#define I9XX_P1_MAX 8
135#define I9XX_P2_SDVO_DAC_SLOW 10
136#define I9XX_P2_SDVO_DAC_FAST 5
137#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138#define I9XX_P2_LVDS_SLOW 14
139#define I9XX_P2_LVDS_FAST 7
140#define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
Ma Ling044c7c42009-03-18 20:13:23 +0800142/*The parameter is for SDVO on G4x platform*/
143#define G4X_DOT_SDVO_MIN 25000
144#define G4X_DOT_SDVO_MAX 270000
145#define G4X_VCO_MIN 1750000
146#define G4X_VCO_MAX 3500000
147#define G4X_N_SDVO_MIN 1
148#define G4X_N_SDVO_MAX 4
149#define G4X_M_SDVO_MIN 104
150#define G4X_M_SDVO_MAX 138
151#define G4X_M1_SDVO_MIN 17
152#define G4X_M1_SDVO_MAX 23
153#define G4X_M2_SDVO_MIN 5
154#define G4X_M2_SDVO_MAX 11
155#define G4X_P_SDVO_MIN 10
156#define G4X_P_SDVO_MAX 30
157#define G4X_P1_SDVO_MIN 1
158#define G4X_P1_SDVO_MAX 3
159#define G4X_P2_SDVO_SLOW 10
160#define G4X_P2_SDVO_FAST 10
161#define G4X_P2_SDVO_LIMIT 270000
162
163/*The parameter is for HDMI_DAC on G4x platform*/
164#define G4X_DOT_HDMI_DAC_MIN 22000
165#define G4X_DOT_HDMI_DAC_MAX 400000
166#define G4X_N_HDMI_DAC_MIN 1
167#define G4X_N_HDMI_DAC_MAX 4
168#define G4X_M_HDMI_DAC_MIN 104
169#define G4X_M_HDMI_DAC_MAX 138
170#define G4X_M1_HDMI_DAC_MIN 16
171#define G4X_M1_HDMI_DAC_MAX 23
172#define G4X_M2_HDMI_DAC_MIN 5
173#define G4X_M2_HDMI_DAC_MAX 11
174#define G4X_P_HDMI_DAC_MIN 5
175#define G4X_P_HDMI_DAC_MAX 80
176#define G4X_P1_HDMI_DAC_MIN 1
177#define G4X_P1_HDMI_DAC_MAX 8
178#define G4X_P2_HDMI_DAC_SLOW 10
179#define G4X_P2_HDMI_DAC_FAST 5
180#define G4X_P2_HDMI_DAC_LIMIT 165000
181
182/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700220/*The parameter is for DISPLAY PORT on G4x platform*/
221#define G4X_DOT_DISPLAY_PORT_MIN 161670
222#define G4X_DOT_DISPLAY_PORT_MAX 227000
223#define G4X_N_DISPLAY_PORT_MIN 1
224#define G4X_N_DISPLAY_PORT_MAX 2
225#define G4X_M_DISPLAY_PORT_MIN 97
226#define G4X_M_DISPLAY_PORT_MAX 108
227#define G4X_M1_DISPLAY_PORT_MIN 0x10
228#define G4X_M1_DISPLAY_PORT_MAX 0x12
229#define G4X_M2_DISPLAY_PORT_MIN 0x05
230#define G4X_M2_DISPLAY_PORT_MAX 0x06
231#define G4X_P_DISPLAY_PORT_MIN 10
232#define G4X_P_DISPLAY_PORT_MAX 20
233#define G4X_P1_DISPLAY_PORT_MIN 1
234#define G4X_P1_DISPLAY_PORT_MAX 2
235#define G4X_P2_DISPLAY_PORT_SLOW 10
236#define G4X_P2_DISPLAY_PORT_FAST 10
237#define G4X_P2_DISPLAY_PORT_LIMIT 0
238
Eric Anholtbad720f2009-10-22 16:11:14 -0700239/* Ironlake / Sandybridge */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800240/* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243#define IRONLAKE_DOT_MIN 25000
244#define IRONLAKE_DOT_MAX 350000
245#define IRONLAKE_VCO_MIN 1760000
246#define IRONLAKE_VCO_MAX 3510000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500247#define IRONLAKE_M1_MIN 12
Zhao Yakuia59e3852010-01-06 22:05:57 +0800248#define IRONLAKE_M1_MAX 22
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500249#define IRONLAKE_M2_MIN 5
250#define IRONLAKE_M2_MAX 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500251#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
Zhenyu Wang2c072452009-06-05 15:38:42 +0800252
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800253/* We have parameter ranges for different type of outputs. */
254
255/* DAC & HDMI Refclk 120Mhz */
256#define IRONLAKE_DAC_N_MIN 1
257#define IRONLAKE_DAC_N_MAX 5
258#define IRONLAKE_DAC_M_MIN 79
259#define IRONLAKE_DAC_M_MAX 127
260#define IRONLAKE_DAC_P_MIN 5
261#define IRONLAKE_DAC_P_MAX 80
262#define IRONLAKE_DAC_P1_MIN 1
263#define IRONLAKE_DAC_P1_MAX 8
264#define IRONLAKE_DAC_P2_SLOW 10
265#define IRONLAKE_DAC_P2_FAST 5
266
267/* LVDS single-channel 120Mhz refclk */
268#define IRONLAKE_LVDS_S_N_MIN 1
269#define IRONLAKE_LVDS_S_N_MAX 3
270#define IRONLAKE_LVDS_S_M_MIN 79
271#define IRONLAKE_LVDS_S_M_MAX 118
272#define IRONLAKE_LVDS_S_P_MIN 28
273#define IRONLAKE_LVDS_S_P_MAX 112
274#define IRONLAKE_LVDS_S_P1_MIN 2
275#define IRONLAKE_LVDS_S_P1_MAX 8
276#define IRONLAKE_LVDS_S_P2_SLOW 14
277#define IRONLAKE_LVDS_S_P2_FAST 14
278
279/* LVDS dual-channel 120Mhz refclk */
280#define IRONLAKE_LVDS_D_N_MIN 1
281#define IRONLAKE_LVDS_D_N_MAX 3
282#define IRONLAKE_LVDS_D_M_MIN 79
283#define IRONLAKE_LVDS_D_M_MAX 127
284#define IRONLAKE_LVDS_D_P_MIN 14
285#define IRONLAKE_LVDS_D_P_MAX 56
286#define IRONLAKE_LVDS_D_P1_MIN 2
287#define IRONLAKE_LVDS_D_P1_MAX 8
288#define IRONLAKE_LVDS_D_P2_SLOW 7
289#define IRONLAKE_LVDS_D_P2_FAST 7
290
291/* LVDS single-channel 100Mhz refclk */
292#define IRONLAKE_LVDS_S_SSC_N_MIN 1
293#define IRONLAKE_LVDS_S_SSC_N_MAX 2
294#define IRONLAKE_LVDS_S_SSC_M_MIN 79
295#define IRONLAKE_LVDS_S_SSC_M_MAX 126
296#define IRONLAKE_LVDS_S_SSC_P_MIN 28
297#define IRONLAKE_LVDS_S_SSC_P_MAX 112
298#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303/* LVDS dual-channel 100Mhz refclk */
304#define IRONLAKE_LVDS_D_SSC_N_MIN 1
305#define IRONLAKE_LVDS_D_SSC_N_MAX 3
306#define IRONLAKE_LVDS_D_SSC_M_MIN 79
307#define IRONLAKE_LVDS_D_SSC_M_MAX 126
308#define IRONLAKE_LVDS_D_SSC_P_MIN 14
309#define IRONLAKE_LVDS_D_SSC_P_MAX 42
310#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315/* DisplayPort */
316#define IRONLAKE_DP_N_MIN 1
317#define IRONLAKE_DP_N_MAX 2
318#define IRONLAKE_DP_M_MIN 81
319#define IRONLAKE_DP_M_MAX 90
320#define IRONLAKE_DP_P_MIN 10
321#define IRONLAKE_DP_P_MAX 20
322#define IRONLAKE_DP_P2_FAST 10
323#define IRONLAKE_DP_P2_SLOW 10
324#define IRONLAKE_DP_P2_LIMIT 0
325#define IRONLAKE_DP_P1_MIN 1
326#define IRONLAKE_DP_P1_MAX 2
Zhao Yakui45476682009-12-31 16:06:04 +0800327
Jesse Barnes2377b742010-07-07 14:06:43 -0700328/* FDI */
329#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
Ma Lingd4906092009-03-18 20:13:27 +0800331static bool
332intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334static bool
335intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -0800337
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700338static bool
339intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800341static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500342intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700344
Chris Wilson021357a2010-09-07 20:54:59 +0100345static inline u32 /* units of 100MHz */
346intel_fdi_link_freq(struct drm_device *dev)
347{
Chris Wilson8b99e682010-10-13 09:59:17 +0100348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100353}
354
Keith Packarde4b36692009-06-05 19:22:17 -0700355static const intel_limit_t intel_limits_i8xx_dvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800366 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700367};
368
369static const intel_limit_t intel_limits_i8xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800380 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700381};
382
383static const intel_limit_t intel_limits_i9xx_sdvo = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800394 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700395};
396
397static const intel_limit_t intel_limits_i9xx_lvds = {
Jesse Barnes79e53942008-11-07 14:24:08 -0800398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
Ma Lingd4906092009-03-18 20:13:27 +0800411 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700412};
413
Ma Ling044c7c42009-03-18 20:13:23 +0800414 /* below parameter and function is for G4X Chipset Family*/
Keith Packarde4b36692009-06-05 19:22:17 -0700415static const intel_limit_t intel_limits_g4x_sdvo = {
Ma Ling044c7c42009-03-18 20:13:23 +0800416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
Ma Lingd4906092009-03-18 20:13:27 +0800428 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700429};
430
431static const intel_limit_t intel_limits_g4x_hdmi = {
Ma Ling044c7c42009-03-18 20:13:23 +0800432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
Ma Lingd4906092009-03-18 20:13:27 +0800444 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700445};
446
447static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
Ma Lingd4906092009-03-18 20:13:27 +0800468 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700469};
470
471static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Ma Ling044c7c42009-03-18 20:13:23 +0800472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
Ma Lingd4906092009-03-18 20:13:27 +0800492 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700493};
494
495static const intel_limit_t intel_limits_g4x_display_port = {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700516};
517
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500518static const intel_limit_t intel_limits_pineview_sdvo = {
Shaohua Li21778322009-02-23 15:19:16 +0800519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
Shaohua Li61157072009-04-03 15:24:43 +0800529 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700530};
531
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500532static const intel_limit_t intel_limits_pineview_lvds = {
Shaohua Li21778322009-02-23 15:19:16 +0800533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
Shaohua Li21778322009-02-23 15:19:16 +0800540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500541 /* Pineview only supports single-channel mode. */
Shaohua Li21778322009-02-23 15:19:16 +0800542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
Shaohua Li61157072009-04-03 15:24:43 +0800544 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700545};
546
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800547static const intel_limit_t intel_limits_ironlake_dac = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800559 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700560};
561
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800562static const intel_limit_t intel_limits_ironlake_single_lvds = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575};
576
577static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590};
591
592static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605};
606
607static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800619 .find_pll = intel_g4x_find_best_PLL,
620};
621
622static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
Zhao Yakui45476682009-12-31 16:06:04 +0800631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
Zhao Yakui45476682009-12-31 16:06:04 +0800642 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800643};
644
Chris Wilson1b894b52010-12-14 20:04:54 +0000645static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800647{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800650 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000656 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000661 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800669 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800670 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800671
672 return limit;
673}
674
Ma Ling044c7c42009-03-18 20:13:23 +0800675static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676{
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700685 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800686 else
687 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700688 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700691 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700693 limit = &intel_limits_g4x_sdvo;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700695 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800696 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700697 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800698
699 return limit;
700}
701
Chris Wilson1b894b52010-12-14 20:04:54 +0000702static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800703{
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
Eric Anholtbad720f2009-10-22 16:11:14 -0700707 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000708 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800709 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800710 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500711 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500713 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800714 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500715 limit = &intel_limits_pineview_sdvo;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700723 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800724 else
Keith Packarde4b36692009-06-05 19:22:17 -0700725 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800726 }
727 return limit;
728}
729
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500730/* m1 is reserved as 0 in Pineview, n is a ring counter */
731static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800732{
Shaohua Li21778322009-02-23 15:19:16 +0800733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737}
738
739static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800743 return;
744 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749}
750
Jesse Barnes79e53942008-11-07 14:24:08 -0800751/**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100754bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800755{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800759
Chris Wilson4ef69c72010-09-09 15:14:28 +0100760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800765}
766
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800767#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800768/**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
Chris Wilson1b894b52010-12-14 20:04:54 +0000773static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800776{
Jesse Barnes79e53942008-11-07 14:24:08 -0800777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -0800786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800}
801
Ma Lingd4906092009-03-18 20:13:27 +0800802static bool
803intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
Jesse Barnes79e53942008-11-07 14:24:08 -0800806{
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800810 int err = target;
811
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800813 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
Zhao Yakui42158662009-11-20 11:24:18 +0800834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800845 int this_err;
846
Shaohua Li21778322009-02-23 15:19:16 +0800847 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863}
864
Ma Lingd4906092009-03-18 20:13:27 +0800865static bool
866intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868{
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800879 int lvds_reg;
880
Eric Anholtc619eed2010-01-28 16:45:52 -0800881 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200899 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200901 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
Shaohua Li21778322009-02-23 15:19:16 +0800910 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800913 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000914
915 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800926 return found;
927}
Ma Lingd4906092009-03-18 20:13:27 +0800928
Zhenyu Wang2c072452009-06-05 15:38:42 +0800929static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500930intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800932{
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800935
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952}
953
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700954/* DisplayPort has only two frequencies, 162MHz and 270MHz */
955static bool
956intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958{
Chris Wilson5eddb702010-09-11 13:48:45 +0100959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700979}
980
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700981/**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800990{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700991 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800992 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700993
Chris Wilson300387c2010-09-05 20:25:43 +0100994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001010 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +01001011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015}
1016
Keith Packardab7ad7f2010-10-03 00:33:06 -07001017/*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001032 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001033 */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001034void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001037
Keith Packardab7ad7f2010-10-03 00:33:06 -07001038 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001039 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001040
Keith Packardab7ad7f2010-10-03 00:33:06 -07001041 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -07001044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001047 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001052 last_line = I915_READ(reg) & DSL_LINEMASK;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001053 mdelay(5);
Chris Wilson58e10eb2010-10-03 10:56:11 +01001054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001059}
1060
Jesse Barnesb24e7172011-01-04 15:09:30 -08001061static const char *state_string(bool enabled)
1062{
1063 return enabled ? "on" : "off";
1064}
1065
1066/* Only for pre-ILK configs */
1067static void assert_pll(struct drm_i915_private *dev_priv,
1068 enum pipe pipe, bool state)
1069{
1070 int reg;
1071 u32 val;
1072 bool cur_state;
1073
1074 reg = DPLL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PLL state assertion failure (expected %s, current %s)\n",
1079 state_string(state), state_string(cur_state));
1080}
1081#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1082#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1083
Jesse Barnes040484a2011-01-03 12:14:26 -08001084/* For ILK+ */
1085static void assert_pch_pll(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087{
1088 int reg;
1089 u32 val;
1090 bool cur_state;
1091
1092 reg = PCH_DPLL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1098}
1099#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
1100#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
1108
1109 reg = FDI_TX_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & FDI_TX_ENABLE);
1112 WARN(cur_state != state,
1113 "FDI TX state assertion failure (expected %s, current %s)\n",
1114 state_string(state), state_string(cur_state));
1115}
1116#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1117#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1118
1119static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = FDI_RX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_RX_ENABLE);
1129 WARN(cur_state != state,
1130 "FDI RX state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
1133#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1134#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1135
1136static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1137 enum pipe pipe)
1138{
1139 int reg;
1140 u32 val;
1141
1142 /* ILK FDI PLL is always enabled */
1143 if (dev_priv->info->gen == 5)
1144 return;
1145
1146 reg = FDI_TX_CTL(pipe);
1147 val = I915_READ(reg);
1148 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1149}
1150
1151static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1152 enum pipe pipe)
1153{
1154 int reg;
1155 u32 val;
1156
1157 reg = FDI_RX_CTL(pipe);
1158 val = I915_READ(reg);
1159 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1160}
1161
Jesse Barnesea0760c2011-01-04 15:09:32 -08001162static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int pp_reg, lvds_reg;
1166 u32 val;
1167 enum pipe panel_pipe = PIPE_A;
1168 bool locked = locked;
1169
1170 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 lvds_reg = PCH_LVDS;
1173 } else {
1174 pp_reg = PP_CONTROL;
1175 lvds_reg = LVDS;
1176 }
1177
1178 val = I915_READ(pp_reg);
1179 if (!(val & PANEL_POWER_ON) ||
1180 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1181 locked = false;
1182
1183 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185
1186 WARN(panel_pipe == pipe && locked,
1187 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001188 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001189}
1190
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001191static void assert_pipe(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001193{
1194 int reg;
1195 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001196 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001197
1198 reg = PIPECONF(pipe);
1199 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001200 cur_state = !!(val & PIPECONF_ENABLE);
1201 WARN(cur_state != state,
1202 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001203 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001204}
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001205#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1206#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001207
1208static void assert_plane_enabled(struct drm_i915_private *dev_priv,
1209 enum plane plane)
1210{
1211 int reg;
1212 u32 val;
1213
1214 reg = DSPCNTR(plane);
1215 val = I915_READ(reg);
1216 WARN(!(val & DISPLAY_PLANE_ENABLE),
1217 "plane %c assertion failure, should be active but is disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001218 plane_name(plane));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001219}
1220
1221static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1222 enum pipe pipe)
1223{
1224 int reg, i;
1225 u32 val;
1226 int cur_pipe;
1227
Jesse Barnes19ec1352011-02-02 12:28:02 -08001228 /* Planes are fixed to pipes on ILK+ */
1229 if (HAS_PCH_SPLIT(dev_priv->dev))
1230 return;
1231
Jesse Barnesb24e7172011-01-04 15:09:30 -08001232 /* Need to check both planes against the pipe */
1233 for (i = 0; i < 2; i++) {
1234 reg = DSPCNTR(i);
1235 val = I915_READ(reg);
1236 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1237 DISPPLANE_SEL_PIPE_SHIFT;
1238 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001239 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1240 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001241 }
1242}
1243
Jesse Barnes92f25842011-01-04 15:09:34 -08001244static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1245{
1246 u32 val;
1247 bool enabled;
1248
1249 val = I915_READ(PCH_DREF_CONTROL);
1250 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1251 DREF_SUPERSPREAD_SOURCE_MASK));
1252 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1253}
1254
1255static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1256 enum pipe pipe)
1257{
1258 int reg;
1259 u32 val;
1260 bool enabled;
1261
1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg);
1264 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001265 WARN(enabled,
1266 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1267 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001268}
1269
Jesse Barnes291906f2011-02-02 12:28:03 -08001270static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe, int reg)
1272{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001273 u32 val = I915_READ(reg);
1274 WARN(DP_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001275 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001276 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001277}
1278
1279static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, int reg)
1281{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001282 u32 val = I915_READ(reg);
1283 WARN(HDMI_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001284 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001285 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001286}
1287
1288static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001293
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1296 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1297
1298 reg = PCH_ADPA;
1299 val = I915_READ(reg);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001300 WARN(ADPA_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001301 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001302 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001303
1304 reg = PCH_LVDS;
1305 val = I915_READ(reg);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001306 WARN(LVDS_PIPE_ENABLED(val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001307 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001308 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001309
1310 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1312 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1313}
1314
Jesse Barnesb24e7172011-01-04 15:09:30 -08001315/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001316 * intel_enable_pll - enable a PLL
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe PLL to enable
1319 *
1320 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1321 * make sure the PLL reg is writable first though, since the panel write
1322 * protect mechanism may be enabled.
1323 *
1324 * Note! This is for pre-ILK only.
1325 */
1326static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1327{
1328 int reg;
1329 u32 val;
1330
1331 /* No really, not for ILK+ */
1332 BUG_ON(dev_priv->info->gen >= 5);
1333
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336 assert_panel_unlocked(dev_priv, pipe);
1337
1338 reg = DPLL(pipe);
1339 val = I915_READ(reg);
1340 val |= DPLL_VCO_ENABLE;
1341
1342 /* We do this three times for luck */
1343 I915_WRITE(reg, val);
1344 POSTING_READ(reg);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352}
1353
1354/**
1355 * intel_disable_pll - disable a PLL
1356 * @dev_priv: i915 private structure
1357 * @pipe: pipe PLL to disable
1358 *
1359 * Disable the PLL for @pipe, making sure the pipe is off first.
1360 *
1361 * Note! This is for pre-ILK only.
1362 */
1363static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1364{
1365 int reg;
1366 u32 val;
1367
1368 /* Don't disable pipe A or pipe A PLLs if needed */
1369 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1370 return;
1371
1372 /* Make sure the pipe isn't still relying on us */
1373 assert_pipe_disabled(dev_priv, pipe);
1374
1375 reg = DPLL(pipe);
1376 val = I915_READ(reg);
1377 val &= ~DPLL_VCO_ENABLE;
1378 I915_WRITE(reg, val);
1379 POSTING_READ(reg);
1380}
1381
1382/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001383 * intel_enable_pch_pll - enable PCH PLL
1384 * @dev_priv: i915 private structure
1385 * @pipe: pipe PLL to enable
1386 *
1387 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1388 * drives the transcoder clock.
1389 */
1390static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392{
1393 int reg;
1394 u32 val;
1395
1396 /* PCH only available on ILK+ */
1397 BUG_ON(dev_priv->info->gen < 5);
1398
1399 /* PCH refclock must be enabled first */
1400 assert_pch_refclk_enabled(dev_priv);
1401
1402 reg = PCH_DPLL(pipe);
1403 val = I915_READ(reg);
1404 val |= DPLL_VCO_ENABLE;
1405 I915_WRITE(reg, val);
1406 POSTING_READ(reg);
1407 udelay(200);
1408}
1409
1410static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1411 enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 /* PCH only available on ILK+ */
1417 BUG_ON(dev_priv->info->gen < 5);
1418
1419 /* Make sure transcoder isn't still depending on us */
1420 assert_transcoder_disabled(dev_priv, pipe);
1421
1422 reg = PCH_DPLL(pipe);
1423 val = I915_READ(reg);
1424 val &= ~DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
1428}
1429
Jesse Barnes040484a2011-01-03 12:14:26 -08001430static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1431 enum pipe pipe)
1432{
1433 int reg;
1434 u32 val;
1435
1436 /* PCH only available on ILK+ */
1437 BUG_ON(dev_priv->info->gen < 5);
1438
1439 /* Make sure PCH DPLL is enabled */
1440 assert_pch_pll_enabled(dev_priv, pipe);
1441
1442 /* FDI must be feeding us bits for PCH ports */
1443 assert_fdi_tx_enabled(dev_priv, pipe);
1444 assert_fdi_rx_enabled(dev_priv, pipe);
1445
1446 reg = TRANSCONF(pipe);
1447 val = I915_READ(reg);
1448 /*
1449 * make the BPC in transcoder be consistent with
1450 * that in pipeconf reg.
1451 */
1452 val &= ~PIPE_BPC_MASK;
1453 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1454 I915_WRITE(reg, val | TRANS_ENABLE);
1455 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1456 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1457}
1458
1459static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461{
1462 int reg;
1463 u32 val;
1464
1465 /* FDI relies on the transcoder */
1466 assert_fdi_tx_disabled(dev_priv, pipe);
1467 assert_fdi_rx_disabled(dev_priv, pipe);
1468
Jesse Barnes291906f2011-02-02 12:28:03 -08001469 /* Ports must be off as well */
1470 assert_pch_ports_disabled(dev_priv, pipe);
1471
Jesse Barnes040484a2011-01-03 12:14:26 -08001472 reg = TRANSCONF(pipe);
1473 val = I915_READ(reg);
1474 val &= ~TRANS_ENABLE;
1475 I915_WRITE(reg, val);
1476 /* wait for PCH transcoder off, transcoder state */
1477 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1478 DRM_ERROR("failed to disable transcoder\n");
1479}
1480
Jesse Barnes92f25842011-01-04 15:09:34 -08001481/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001482 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001483 * @dev_priv: i915 private structure
1484 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001485 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001486 *
1487 * Enable @pipe, making sure that various hardware specific requirements
1488 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1489 *
1490 * @pipe should be %PIPE_A or %PIPE_B.
1491 *
1492 * Will wait until the pipe is actually running (i.e. first vblank) before
1493 * returning.
1494 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001495static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1496 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001497{
1498 int reg;
1499 u32 val;
1500
1501 /*
1502 * A pipe without a PLL won't actually be able to drive bits from
1503 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1504 * need the check.
1505 */
1506 if (!HAS_PCH_SPLIT(dev_priv->dev))
1507 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001508 else {
1509 if (pch_port) {
1510 /* if driving the PCH, we need FDI enabled */
1511 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1512 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1513 }
1514 /* FIXME: assert CPU port conditions for SNB+ */
1515 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001516
1517 reg = PIPECONF(pipe);
1518 val = I915_READ(reg);
1519 val |= PIPECONF_ENABLE;
1520 I915_WRITE(reg, val);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001521 intel_wait_for_vblank(dev_priv->dev, pipe);
1522}
1523
1524/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001525 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001526 * @dev_priv: i915 private structure
1527 * @pipe: pipe to disable
1528 *
1529 * Disable @pipe, making sure that various hardware specific requirements
1530 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1531 *
1532 * @pipe should be %PIPE_A or %PIPE_B.
1533 *
1534 * Will wait until the pipe has shut down before returning.
1535 */
1536static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538{
1539 int reg;
1540 u32 val;
1541
1542 /*
1543 * Make sure planes won't keep trying to pump pixels to us,
1544 * or we might hang the display.
1545 */
1546 assert_planes_disabled(dev_priv, pipe);
1547
1548 /* Don't disable pipe A or pipe A PLLs if needed */
1549 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1550 return;
1551
1552 reg = PIPECONF(pipe);
1553 val = I915_READ(reg);
1554 val &= ~PIPECONF_ENABLE;
1555 I915_WRITE(reg, val);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001556 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1557}
1558
1559/**
1560 * intel_enable_plane - enable a display plane on a given pipe
1561 * @dev_priv: i915 private structure
1562 * @plane: plane to enable
1563 * @pipe: pipe being fed
1564 *
1565 * Enable @plane on @pipe, making sure that @pipe is running first.
1566 */
1567static void intel_enable_plane(struct drm_i915_private *dev_priv,
1568 enum plane plane, enum pipe pipe)
1569{
1570 int reg;
1571 u32 val;
1572
1573 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1574 assert_pipe_enabled(dev_priv, pipe);
1575
1576 reg = DSPCNTR(plane);
1577 val = I915_READ(reg);
1578 val |= DISPLAY_PLANE_ENABLE;
1579 I915_WRITE(reg, val);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001580 intel_wait_for_vblank(dev_priv->dev, pipe);
1581}
1582
1583/*
1584 * Plane regs are double buffered, going from enabled->disabled needs a
1585 * trigger in order to latch. The display address reg provides this.
1586 */
1587static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1588 enum plane plane)
1589{
1590 u32 reg = DSPADDR(plane);
1591 I915_WRITE(reg, I915_READ(reg));
1592}
1593
1594/**
1595 * intel_disable_plane - disable a display plane
1596 * @dev_priv: i915 private structure
1597 * @plane: plane to disable
1598 * @pipe: pipe consuming the data
1599 *
1600 * Disable @plane; should be an independent operation.
1601 */
1602static void intel_disable_plane(struct drm_i915_private *dev_priv,
1603 enum plane plane, enum pipe pipe)
1604{
1605 int reg;
1606 u32 val;
1607
1608 reg = DSPCNTR(plane);
1609 val = I915_READ(reg);
1610 val &= ~DISPLAY_PLANE_ENABLE;
1611 I915_WRITE(reg, val);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001612 intel_flush_display_plane(dev_priv, plane);
1613 intel_wait_for_vblank(dev_priv->dev, pipe);
1614}
1615
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001616static void disable_pch_dp(struct drm_i915_private *dev_priv,
1617 enum pipe pipe, int reg)
1618{
1619 u32 val = I915_READ(reg);
1620 if (DP_PIPE_ENABLED(val, pipe))
1621 I915_WRITE(reg, val & ~DP_PORT_EN);
1622}
1623
1624static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1625 enum pipe pipe, int reg)
1626{
1627 u32 val = I915_READ(reg);
1628 if (HDMI_PIPE_ENABLED(val, pipe))
1629 I915_WRITE(reg, val & ~PORT_ENABLE);
1630}
1631
1632/* Disable any ports connected to this transcoder */
1633static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1634 enum pipe pipe)
1635{
1636 u32 reg, val;
1637
1638 val = I915_READ(PCH_PP_CONTROL);
1639 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1640
1641 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1642 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1643 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1644
1645 reg = PCH_ADPA;
1646 val = I915_READ(reg);
1647 if (ADPA_PIPE_ENABLED(val, pipe))
1648 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1649
1650 reg = PCH_LVDS;
1651 val = I915_READ(reg);
1652 if (LVDS_PIPE_ENABLED(val, pipe)) {
1653 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1654 POSTING_READ(reg);
1655 udelay(100);
1656 }
1657
1658 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1659 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1660 disable_pch_hdmi(dev_priv, pipe, HDMID);
1661}
1662
Jesse Barnes80824002009-09-10 15:28:06 -07001663static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1664{
1665 struct drm_device *dev = crtc->dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 struct drm_framebuffer *fb = crtc->fb;
1668 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001669 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes80824002009-09-10 15:28:06 -07001670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1671 int plane, i;
1672 u32 fbc_ctl, fbc_ctl2;
1673
Chris Wilsonbed4a672010-09-11 10:47:47 +01001674 if (fb->pitch == dev_priv->cfb_pitch &&
Chris Wilson05394f32010-11-08 19:18:58 +00001675 obj->fence_reg == dev_priv->cfb_fence &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001676 intel_crtc->plane == dev_priv->cfb_plane &&
1677 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1678 return;
1679
1680 i8xx_disable_fbc(dev);
1681
Jesse Barnes80824002009-09-10 15:28:06 -07001682 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1683
1684 if (fb->pitch < dev_priv->cfb_pitch)
1685 dev_priv->cfb_pitch = fb->pitch;
1686
1687 /* FBC_CTL wants 64B units */
1688 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001689 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes80824002009-09-10 15:28:06 -07001690 dev_priv->cfb_plane = intel_crtc->plane;
1691 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1692
1693 /* Clear old tags */
1694 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1695 I915_WRITE(FBC_TAG + (i * 4), 0);
1696
1697 /* Set it up... */
1698 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001699 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001700 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1701 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1702 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1703
1704 /* enable it... */
1705 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001706 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001707 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Jesse Barnes80824002009-09-10 15:28:06 -07001708 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1709 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
Chris Wilson05394f32010-11-08 19:18:58 +00001710 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes80824002009-09-10 15:28:06 -07001711 fbc_ctl |= dev_priv->cfb_fence;
1712 I915_WRITE(FBC_CONTROL, fbc_ctl);
1713
Zhao Yakui28c97732009-10-09 11:39:41 +08001714 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
Chris Wilson5eddb702010-09-11 13:48:45 +01001715 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
Jesse Barnes80824002009-09-10 15:28:06 -07001716}
1717
1718void i8xx_disable_fbc(struct drm_device *dev)
1719{
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 u32 fbc_ctl;
1722
1723 /* Disable compression */
1724 fbc_ctl = I915_READ(FBC_CONTROL);
Chris Wilsona5cad622010-09-22 13:15:10 +01001725 if ((fbc_ctl & FBC_CTL_EN) == 0)
1726 return;
1727
Jesse Barnes80824002009-09-10 15:28:06 -07001728 fbc_ctl &= ~FBC_CTL_EN;
1729 I915_WRITE(FBC_CONTROL, fbc_ctl);
1730
1731 /* Wait for compressing bit to clear */
Chris Wilson481b6af2010-08-23 17:43:35 +01001732 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
Chris Wilson913d8d12010-08-07 11:01:35 +01001733 DRM_DEBUG_KMS("FBC idle timed out\n");
1734 return;
Jesse Barnes9517a922010-05-21 09:40:45 -07001735 }
Jesse Barnes80824002009-09-10 15:28:06 -07001736
Zhao Yakui28c97732009-10-09 11:39:41 +08001737 DRM_DEBUG_KMS("disabled FBC\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001738}
1739
Adam Jacksonee5382a2010-04-23 11:17:39 -04001740static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001741{
Jesse Barnes80824002009-09-10 15:28:06 -07001742 struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1745}
1746
Jesse Barnes74dff282009-09-14 15:39:40 -07001747static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1748{
1749 struct drm_device *dev = crtc->dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 struct drm_framebuffer *fb = crtc->fb;
1752 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001753 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes74dff282009-09-14 15:39:40 -07001754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001755 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Jesse Barnes74dff282009-09-14 15:39:40 -07001756 unsigned long stall_watermark = 200;
1757 u32 dpfc_ctl;
1758
Chris Wilsonbed4a672010-09-11 10:47:47 +01001759 dpfc_ctl = I915_READ(DPFC_CONTROL);
1760 if (dpfc_ctl & DPFC_CTL_EN) {
1761 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001762 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001763 dev_priv->cfb_plane == intel_crtc->plane &&
1764 dev_priv->cfb_y == crtc->y)
1765 return;
1766
1767 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001768 intel_wait_for_vblank(dev, intel_crtc->pipe);
1769 }
1770
Jesse Barnes74dff282009-09-14 15:39:40 -07001771 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001772 dev_priv->cfb_fence = obj->fence_reg;
Jesse Barnes74dff282009-09-14 15:39:40 -07001773 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001774 dev_priv->cfb_y = crtc->y;
Jesse Barnes74dff282009-09-14 15:39:40 -07001775
1776 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
Chris Wilson05394f32010-11-08 19:18:58 +00001777 if (obj->tiling_mode != I915_TILING_NONE) {
Jesse Barnes74dff282009-09-14 15:39:40 -07001778 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1779 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1780 } else {
1781 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1782 }
1783
Jesse Barnes74dff282009-09-14 15:39:40 -07001784 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1785 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1786 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1787 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1788
1789 /* enable it... */
1790 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1791
Zhao Yakui28c97732009-10-09 11:39:41 +08001792 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001793}
1794
1795void g4x_disable_fbc(struct drm_device *dev)
1796{
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 u32 dpfc_ctl;
1799
1800 /* Disable compression */
1801 dpfc_ctl = I915_READ(DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001802 if (dpfc_ctl & DPFC_CTL_EN) {
1803 dpfc_ctl &= ~DPFC_CTL_EN;
1804 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Jesse Barnes74dff282009-09-14 15:39:40 -07001805
Chris Wilsonbed4a672010-09-11 10:47:47 +01001806 DRM_DEBUG_KMS("disabled FBC\n");
1807 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001808}
1809
Adam Jacksonee5382a2010-04-23 11:17:39 -04001810static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001811{
Jesse Barnes74dff282009-09-14 15:39:40 -07001812 struct drm_i915_private *dev_priv = dev->dev_private;
1813
1814 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1815}
1816
Jesse Barnes4efe0702011-01-18 11:25:41 -08001817static void sandybridge_blit_fbc_update(struct drm_device *dev)
1818{
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 u32 blt_ecoskpd;
1821
1822 /* Make sure blitter notifies FBC of writes */
Chris Wilson91355832011-03-04 19:22:40 +00001823 __gen6_gt_force_wake_get(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001824 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1825 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1826 GEN6_BLITTER_LOCK_SHIFT;
1827 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1828 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1829 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1830 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1831 GEN6_BLITTER_LOCK_SHIFT);
1832 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1833 POSTING_READ(GEN6_BLITTER_ECOSKPD);
Chris Wilson91355832011-03-04 19:22:40 +00001834 __gen6_gt_force_wake_put(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001835}
1836
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001837static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1838{
1839 struct drm_device *dev = crtc->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct drm_framebuffer *fb = crtc->fb;
1842 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001843 struct drm_i915_gem_object *obj = intel_fb->obj;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001845 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001846 unsigned long stall_watermark = 200;
1847 u32 dpfc_ctl;
1848
Chris Wilsonbed4a672010-09-11 10:47:47 +01001849 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1850 if (dpfc_ctl & DPFC_CTL_EN) {
1851 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
Chris Wilson05394f32010-11-08 19:18:58 +00001852 dev_priv->cfb_fence == obj->fence_reg &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001853 dev_priv->cfb_plane == intel_crtc->plane &&
Chris Wilson05394f32010-11-08 19:18:58 +00001854 dev_priv->cfb_offset == obj->gtt_offset &&
Chris Wilsonbed4a672010-09-11 10:47:47 +01001855 dev_priv->cfb_y == crtc->y)
1856 return;
1857
1858 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001859 intel_wait_for_vblank(dev, intel_crtc->pipe);
1860 }
1861
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001862 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
Chris Wilson05394f32010-11-08 19:18:58 +00001863 dev_priv->cfb_fence = obj->fence_reg;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001864 dev_priv->cfb_plane = intel_crtc->plane;
Chris Wilson05394f32010-11-08 19:18:58 +00001865 dev_priv->cfb_offset = obj->gtt_offset;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001866 dev_priv->cfb_y = crtc->y;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001867
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001868 dpfc_ctl &= DPFC_RESERVED;
1869 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
Chris Wilson05394f32010-11-08 19:18:58 +00001870 if (obj->tiling_mode != I915_TILING_NONE) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001871 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1872 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1873 } else {
1874 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1875 }
1876
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001877 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1878 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1879 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1880 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
Chris Wilson05394f32010-11-08 19:18:58 +00001881 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001882 /* enable it... */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001883 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001884
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001885 if (IS_GEN6(dev)) {
1886 I915_WRITE(SNB_DPFC_CTL_SA,
1887 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1888 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001889 sandybridge_blit_fbc_update(dev);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001890 }
1891
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001892 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1893}
1894
1895void ironlake_disable_fbc(struct drm_device *dev)
1896{
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 u32 dpfc_ctl;
1899
1900 /* Disable compression */
1901 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001902 if (dpfc_ctl & DPFC_CTL_EN) {
1903 dpfc_ctl &= ~DPFC_CTL_EN;
1904 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001905
Chris Wilsonbed4a672010-09-11 10:47:47 +01001906 DRM_DEBUG_KMS("disabled FBC\n");
1907 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001908}
1909
1910static bool ironlake_fbc_enabled(struct drm_device *dev)
1911{
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913
1914 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1915}
1916
Adam Jacksonee5382a2010-04-23 11:17:39 -04001917bool intel_fbc_enabled(struct drm_device *dev)
1918{
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920
1921 if (!dev_priv->display.fbc_enabled)
1922 return false;
1923
1924 return dev_priv->display.fbc_enabled(dev);
1925}
1926
1927void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1928{
1929 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1930
1931 if (!dev_priv->display.enable_fbc)
1932 return;
1933
1934 dev_priv->display.enable_fbc(crtc, interval);
1935}
1936
1937void intel_disable_fbc(struct drm_device *dev)
1938{
1939 struct drm_i915_private *dev_priv = dev->dev_private;
1940
1941 if (!dev_priv->display.disable_fbc)
1942 return;
1943
1944 dev_priv->display.disable_fbc(dev);
1945}
1946
Jesse Barnes80824002009-09-10 15:28:06 -07001947/**
1948 * intel_update_fbc - enable/disable FBC as needed
Chris Wilsonbed4a672010-09-11 10:47:47 +01001949 * @dev: the drm_device
Jesse Barnes80824002009-09-10 15:28:06 -07001950 *
1951 * Set up the framebuffer compression hardware at mode set time. We
1952 * enable it if possible:
1953 * - plane A only (on pre-965)
1954 * - no pixel mulitply/line duplication
1955 * - no alpha buffer discard
1956 * - no dual wide
1957 * - framebuffer <= 2048 in width, 1536 in height
1958 *
1959 * We can't assume that any compression will take place (worst case),
1960 * so the compressed buffer has to be the same size as the uncompressed
1961 * one. It also must reside (along with the line length buffer) in
1962 * stolen memory.
1963 *
1964 * We need to enable/disable FBC on a global basis.
1965 */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001966static void intel_update_fbc(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001967{
Jesse Barnes80824002009-09-10 15:28:06 -07001968 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001969 struct drm_crtc *crtc = NULL, *tmp_crtc;
1970 struct intel_crtc *intel_crtc;
1971 struct drm_framebuffer *fb;
Jesse Barnes80824002009-09-10 15:28:06 -07001972 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001973 struct drm_i915_gem_object *obj;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001974
1975 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001976
1977 if (!i915_powersave)
1978 return;
1979
Adam Jacksonee5382a2010-04-23 11:17:39 -04001980 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001981 return;
1982
Jesse Barnes80824002009-09-10 15:28:06 -07001983 /*
1984 * If FBC is already on, we just have to verify that we can
1985 * keep it that way...
1986 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001987 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001988 * - changing FBC params (stride, fence, mode)
1989 * - new fb is too large to fit in compressed buffer
1990 * - going to an unsupported config (interlace, pixel multiply, etc.)
1991 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001992 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsond2102462011-01-24 17:43:27 +00001993 if (tmp_crtc->enabled && tmp_crtc->fb) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001994 if (crtc) {
1995 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1996 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1997 goto out_disable;
1998 }
1999 crtc = tmp_crtc;
2000 }
Jesse Barnes9c928d12010-07-23 15:20:00 -07002001 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01002002
2003 if (!crtc || crtc->fb == NULL) {
2004 DRM_DEBUG_KMS("no output, disabling\n");
2005 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
Jesse Barnes9c928d12010-07-23 15:20:00 -07002006 goto out_disable;
2007 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01002008
2009 intel_crtc = to_intel_crtc(crtc);
2010 fb = crtc->fb;
2011 intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00002012 obj = intel_fb->obj;
Chris Wilsonbed4a672010-09-11 10:47:47 +01002013
Chris Wilson05394f32010-11-08 19:18:58 +00002014 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002015 DRM_DEBUG_KMS("framebuffer too large, disabling "
Chris Wilson5eddb702010-09-11 13:48:45 +01002016 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002017 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07002018 goto out_disable;
2019 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01002020 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
2021 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002022 DRM_DEBUG_KMS("mode incompatible with compression, "
Chris Wilson5eddb702010-09-11 13:48:45 +01002023 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002024 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07002025 goto out_disable;
2026 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01002027 if ((crtc->mode.hdisplay > 2048) ||
2028 (crtc->mode.vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002029 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002030 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07002031 goto out_disable;
2032 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01002033 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002034 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002035 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07002036 goto out_disable;
2037 }
Chris Wilson05394f32010-11-08 19:18:58 +00002038 if (obj->tiling_mode != I915_TILING_X) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002039 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08002040 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07002041 goto out_disable;
2042 }
2043
Jason Wesselc924b932010-08-05 09:22:32 -05002044 /* If the kernel debugger is active, always disable compression */
2045 if (in_dbg_master())
2046 goto out_disable;
2047
Chris Wilsonbed4a672010-09-11 10:47:47 +01002048 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07002049 return;
2050
2051out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07002052 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01002053 if (intel_fbc_enabled(dev)) {
2054 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04002055 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01002056 }
Jesse Barnes80824002009-09-10 15:28:06 -07002057}
2058
Chris Wilson127bd2a2010-07-23 23:32:05 +01002059int
Chris Wilson48b956c2010-09-14 12:50:34 +01002060intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002061 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002062 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002063{
Chris Wilsonce453d82011-02-21 14:43:56 +00002064 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002065 u32 alignment;
2066 int ret;
2067
Chris Wilson05394f32010-11-08 19:18:58 +00002068 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002069 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002070 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2071 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002072 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002073 alignment = 4 * 1024;
2074 else
2075 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002076 break;
2077 case I915_TILING_X:
2078 /* pin() will align the object as required by fence */
2079 alignment = 0;
2080 break;
2081 case I915_TILING_Y:
2082 /* FIXME: Is this true? */
2083 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2084 return -EINVAL;
2085 default:
2086 BUG();
2087 }
2088
Chris Wilsonce453d82011-02-21 14:43:56 +00002089 dev_priv->mm.interruptible = false;
Daniel Vetter75e9e912010-11-04 17:11:09 +01002090 ret = i915_gem_object_pin(obj, alignment, true);
Chris Wilson48b956c2010-09-14 12:50:34 +01002091 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002092 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002093
Chris Wilson48b956c2010-09-14 12:50:34 +01002094 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
2095 if (ret)
2096 goto err_unpin;
Chris Wilson72133422010-09-13 23:56:38 +01002097
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002098 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2099 * fence, whereas 965+ only requires a fence if using
2100 * framebuffer compression. For simplicity, we always install
2101 * a fence as the cost is not that onerous.
2102 */
Chris Wilson05394f32010-11-08 19:18:58 +00002103 if (obj->tiling_mode != I915_TILING_NONE) {
Chris Wilsonce453d82011-02-21 14:43:56 +00002104 ret = i915_gem_object_get_fence(obj, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002105 if (ret)
2106 goto err_unpin;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002107 }
2108
Chris Wilsonce453d82011-02-21 14:43:56 +00002109 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002110 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002111
2112err_unpin:
2113 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002114err_interruptible:
2115 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002116 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002117}
2118
Jesse Barnes81255562010-08-02 12:07:50 -07002119/* Assume fb object is pinned & idle & fenced and just update base pointers */
2120static int
2121intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
Jason Wessel21c74a82010-10-13 14:09:44 -05002122 int x, int y, enum mode_set_atomic state)
Jesse Barnes81255562010-08-02 12:07:50 -07002123{
2124 struct drm_device *dev = crtc->dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002128 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002129 int plane = intel_crtc->plane;
2130 unsigned long Start, Offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002131 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002132 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002133
2134 switch (plane) {
2135 case 0:
2136 case 1:
2137 break;
2138 default:
2139 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2140 return -EINVAL;
2141 }
2142
2143 intel_fb = to_intel_framebuffer(fb);
2144 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002145
Chris Wilson5eddb702010-09-11 13:48:45 +01002146 reg = DSPCNTR(plane);
2147 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002148 /* Mask out pixel format bits in case we change it */
2149 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2150 switch (fb->bits_per_pixel) {
2151 case 8:
2152 dspcntr |= DISPPLANE_8BPP;
2153 break;
2154 case 16:
2155 if (fb->depth == 15)
2156 dspcntr |= DISPPLANE_15_16BPP;
2157 else
2158 dspcntr |= DISPPLANE_16BPP;
2159 break;
2160 case 24:
2161 case 32:
2162 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2163 break;
2164 default:
2165 DRM_ERROR("Unknown color depth\n");
2166 return -EINVAL;
2167 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002168 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002169 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002170 dspcntr |= DISPPLANE_TILED;
2171 else
2172 dspcntr &= ~DISPPLANE_TILED;
2173 }
2174
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002175 if (HAS_PCH_SPLIT(dev))
Jesse Barnes81255562010-08-02 12:07:50 -07002176 /* must disable */
2177 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2178
Chris Wilson5eddb702010-09-11 13:48:45 +01002179 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002180
Chris Wilson05394f32010-11-08 19:18:58 +00002181 Start = obj->gtt_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002182 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2183
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002184 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2185 Start, Offset, x, y, fb->pitch);
Chris Wilson5eddb702010-09-11 13:48:45 +01002186 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002187 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002188 I915_WRITE(DSPSURF(plane), Start);
2189 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2190 I915_WRITE(DSPADDR(plane), Offset);
2191 } else
2192 I915_WRITE(DSPADDR(plane), Start + Offset);
2193 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002194
Chris Wilsonbed4a672010-09-11 10:47:47 +01002195 intel_update_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002196 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002197
2198 return 0;
2199}
2200
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002201static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002202intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2203 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002204{
2205 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002206 struct drm_i915_master_private *master_priv;
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002208 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002209
2210 /* no fb bound */
2211 if (!crtc->fb) {
Zhao Yakui28c97732009-10-09 11:39:41 +08002212 DRM_DEBUG_KMS("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002213 return 0;
2214 }
2215
Chris Wilson265db952010-09-20 15:41:01 +01002216 switch (intel_crtc->plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002217 case 0:
2218 case 1:
2219 break;
2220 default:
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002221 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002222 }
2223
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002224 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002225 ret = intel_pin_and_fence_fb_obj(dev,
2226 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002227 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002228 if (ret != 0) {
2229 mutex_unlock(&dev->struct_mutex);
2230 return ret;
2231 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002232
Chris Wilson265db952010-09-20 15:41:01 +01002233 if (old_fb) {
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002234 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00002235 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
Chris Wilson265db952010-09-20 15:41:01 +01002236
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002237 wait_event(dev_priv->pending_flip_queue,
Chris Wilson01eec722011-02-11 20:47:45 +00002238 atomic_read(&dev_priv->mm.wedged) ||
Chris Wilson05394f32010-11-08 19:18:58 +00002239 atomic_read(&obj->pending_flip) == 0);
Chris Wilson85345512010-11-13 09:49:11 +00002240
2241 /* Big Hammer, we also need to ensure that any pending
2242 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2243 * current scanout is retired before unpinning the old
2244 * framebuffer.
Chris Wilson01eec722011-02-11 20:47:45 +00002245 *
2246 * This should only fail upon a hung GPU, in which case we
2247 * can safely continue.
Chris Wilson85345512010-11-13 09:49:11 +00002248 */
Chris Wilsonce453d82011-02-21 14:43:56 +00002249 ret = i915_gem_object_flush_gpu(obj);
Chris Wilson01eec722011-02-11 20:47:45 +00002250 (void) ret;
Chris Wilson265db952010-09-20 15:41:01 +01002251 }
2252
Jason Wessel21c74a82010-10-13 14:09:44 -05002253 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2254 LEAVE_ATOMIC_MODE_SET);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002255 if (ret) {
Chris Wilson265db952010-09-20 15:41:01 +01002256 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002257 mutex_unlock(&dev->struct_mutex);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002258 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002259 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002260
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002261 if (old_fb) {
2262 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson265db952010-09-20 15:41:01 +01002263 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002264 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002265
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002266 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002267
2268 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002269 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002270
2271 master_priv = dev->primary->master->driver_priv;
2272 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002273 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002274
Chris Wilson265db952010-09-20 15:41:01 +01002275 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002276 master_priv->sarea_priv->pipeB_x = x;
2277 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002278 } else {
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002281 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002282
2283 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002284}
2285
Chris Wilson5eddb702010-09-11 13:48:45 +01002286static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002287{
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 u32 dpa_ctl;
2291
Zhao Yakui28c97732009-10-09 11:39:41 +08002292 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002293 dpa_ctl = I915_READ(DP_A);
2294 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2295
2296 if (clock < 200000) {
2297 u32 temp;
2298 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2299 /* workaround for 160Mhz:
2300 1) program 0x4600c bits 15:0 = 0x8124
2301 2) program 0x46010 bit 0 = 1
2302 3) program 0x46034 bit 24 = 1
2303 4) program 0x64000 bit 14 = 1
2304 */
2305 temp = I915_READ(0x4600c);
2306 temp &= 0xffff0000;
2307 I915_WRITE(0x4600c, temp | 0x8124);
2308
2309 temp = I915_READ(0x46010);
2310 I915_WRITE(0x46010, temp | 1);
2311
2312 temp = I915_READ(0x46034);
2313 I915_WRITE(0x46034, temp | (1 << 24));
2314 } else {
2315 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2316 }
2317 I915_WRITE(DP_A, dpa_ctl);
2318
Chris Wilson5eddb702010-09-11 13:48:45 +01002319 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002320 udelay(500);
2321}
2322
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002323static void intel_fdi_normal_train(struct drm_crtc *crtc)
2324{
2325 struct drm_device *dev = crtc->dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2328 int pipe = intel_crtc->pipe;
2329 u32 reg, temp;
2330
2331 /* enable normal train */
2332 reg = FDI_TX_CTL(pipe);
2333 temp = I915_READ(reg);
2334 temp &= ~FDI_LINK_TRAIN_NONE;
2335 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
2352}
2353
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002354/* The FDI link training functions for ILK/Ibexpeak. */
2355static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2356{
2357 struct drm_device *dev = crtc->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2360 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002361 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002362 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002363
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002364 /* FDI needs bits from pipe & plane first */
2365 assert_pipe_enabled(dev_priv, pipe);
2366 assert_plane_enabled(dev_priv, plane);
2367
Adam Jacksone1a44742010-06-25 15:32:14 -04002368 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2369 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002370 reg = FDI_RX_IMR(pipe);
2371 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002372 temp &= ~FDI_RX_SYMBOL_LOCK;
2373 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002374 I915_WRITE(reg, temp);
2375 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002376 udelay(150);
2377
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002378 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002381 temp &= ~(7 << 19);
2382 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002385 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002386
Chris Wilson5eddb702010-09-11 13:48:45 +01002387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002391 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2392
2393 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002394 udelay(150);
2395
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002396 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002397 if (HAS_PCH_IBX(dev)) {
2398 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2399 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2400 FDI_RX_PHASE_SYNC_POINTER_EN);
2401 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002402
Chris Wilson5eddb702010-09-11 13:48:45 +01002403 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002404 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002405 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002406 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408 if ((temp & FDI_RX_BIT_LOCK)) {
2409 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002410 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002411 break;
2412 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002413 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002414 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002415 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002416
2417 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002420 temp &= ~FDI_LINK_TRAIN_NONE;
2421 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002422 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002423
Chris Wilson5eddb702010-09-11 13:48:45 +01002424 reg = FDI_RX_CTL(pipe);
2425 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002428 I915_WRITE(reg, temp);
2429
2430 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002431 udelay(150);
2432
Chris Wilson5eddb702010-09-11 13:48:45 +01002433 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002434 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002435 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002439 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002440 DRM_DEBUG_KMS("FDI train 2 done.\n");
2441 break;
2442 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002443 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002444 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002445 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002446
2447 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002448
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002449}
2450
Chris Wilson311bd682011-01-13 19:06:50 +00002451static const int snb_b_fdi_train_param [] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002452 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2456};
2457
2458/* The FDI link training functions for SNB/Cougarpoint. */
2459static void gen6_fdi_link_train(struct drm_crtc *crtc)
2460{
2461 struct drm_device *dev = crtc->dev;
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002465 u32 reg, temp, i;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002466
Adam Jacksone1a44742010-06-25 15:32:14 -04002467 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002469 reg = FDI_RX_IMR(pipe);
2470 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002471 temp &= ~FDI_RX_SYMBOL_LOCK;
2472 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002473 I915_WRITE(reg, temp);
2474
2475 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002476 udelay(150);
2477
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002478 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002481 temp &= ~(7 << 19);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
2485 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486 /* SNB-B */
2487 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002488 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002489
Chris Wilson5eddb702010-09-11 13:48:45 +01002490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002492 if (HAS_PCH_CPT(dev)) {
2493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2494 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2495 } else {
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_1;
2498 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002502 udelay(150);
2503
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002504 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002509 I915_WRITE(reg, temp);
2510
2511 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002512 udelay(500);
2513
Chris Wilson5eddb702010-09-11 13:48:45 +01002514 reg = FDI_RX_IIR(pipe);
2515 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002516 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517
2518 if (temp & FDI_RX_BIT_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002520 DRM_DEBUG_KMS("FDI train 1 done.\n");
2521 break;
2522 }
2523 }
2524 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002525 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002526
2527 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002528 reg = FDI_TX_CTL(pipe);
2529 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2;
2532 if (IS_GEN6(dev)) {
2533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2534 /* SNB-B */
2535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2536 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002537 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002538
Chris Wilson5eddb702010-09-11 13:48:45 +01002539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002541 if (HAS_PCH_CPT(dev)) {
2542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2543 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2544 } else {
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002551 udelay(150);
2552
2553 for (i = 0; i < 4; i++ ) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2557 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002561 udelay(500);
2562
Chris Wilson5eddb702010-09-11 13:48:45 +01002563 reg = FDI_RX_IIR(pipe);
2564 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2566
2567 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002568 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002569 DRM_DEBUG_KMS("FDI train 2 done.\n");
2570 break;
2571 }
2572 }
2573 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002574 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002575
2576 DRM_DEBUG_KMS("FDI train done.\n");
2577}
2578
Jesse Barnes0e23b992010-09-10 11:10:00 -07002579static void ironlake_fdi_enable(struct drm_crtc *crtc)
2580{
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2584 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002585 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002586
Jesse Barnesc64e3112010-09-10 11:27:03 -07002587 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002588 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2589 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002590
Jesse Barnes0e23b992010-09-10 11:10:00 -07002591 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
2594 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002595 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002596 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2597 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2598
2599 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002600 udelay(200);
2601
2602 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002603 temp = I915_READ(reg);
2604 I915_WRITE(reg, temp | FDI_PCDCLK);
2605
2606 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002607 udelay(200);
2608
2609 /* Enable CPU FDI TX PLL, always on for Ironlake */
Chris Wilson5eddb702010-09-11 13:48:45 +01002610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002612 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002613 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2614
2615 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002616 udelay(100);
2617 }
2618}
2619
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002620static void ironlake_fdi_disable(struct drm_crtc *crtc)
2621{
2622 struct drm_device *dev = crtc->dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2625 int pipe = intel_crtc->pipe;
2626 u32 reg, temp;
2627
2628 /* disable CPU FDI tx and PCH FDI rx */
2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2632 POSTING_READ(reg);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~(0x7 << 16);
2637 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2638 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2639
2640 POSTING_READ(reg);
2641 udelay(100);
2642
2643 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002644 if (HAS_PCH_IBX(dev)) {
2645 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002646 I915_WRITE(FDI_RX_CHICKEN(pipe),
2647 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002648 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2649 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002650
2651 /* still set train pattern 1 */
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_NONE;
2655 temp |= FDI_LINK_TRAIN_PATTERN_1;
2656 I915_WRITE(reg, temp);
2657
2658 reg = FDI_RX_CTL(pipe);
2659 temp = I915_READ(reg);
2660 if (HAS_PCH_CPT(dev)) {
2661 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2662 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2663 } else {
2664 temp &= ~FDI_LINK_TRAIN_NONE;
2665 temp |= FDI_LINK_TRAIN_PATTERN_1;
2666 }
2667 /* BPC in FDI rx is consistent with that in PIPECONF */
2668 temp &= ~(0x07 << 16);
2669 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
2673 udelay(100);
2674}
2675
Chris Wilson6b383a72010-09-13 13:54:26 +01002676/*
2677 * When we disable a pipe, we need to clear any pending scanline wait events
2678 * to avoid hanging the ring, which we assume we are waiting on.
2679 */
2680static void intel_clear_scanline_wait(struct drm_device *dev)
2681{
2682 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8168bd42010-11-11 17:54:52 +00002683 struct intel_ring_buffer *ring;
Chris Wilson6b383a72010-09-13 13:54:26 +01002684 u32 tmp;
2685
2686 if (IS_GEN2(dev))
2687 /* Can't break the hang on i8xx */
2688 return;
2689
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002690 ring = LP_RING(dev_priv);
Chris Wilson8168bd42010-11-11 17:54:52 +00002691 tmp = I915_READ_CTL(ring);
2692 if (tmp & RING_WAIT)
2693 I915_WRITE_CTL(ring, tmp);
Chris Wilson6b383a72010-09-13 13:54:26 +01002694}
2695
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002696static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2697{
Chris Wilson05394f32010-11-08 19:18:58 +00002698 struct drm_i915_gem_object *obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002699 struct drm_i915_private *dev_priv;
2700
2701 if (crtc->fb == NULL)
2702 return;
2703
Chris Wilson05394f32010-11-08 19:18:58 +00002704 obj = to_intel_framebuffer(crtc->fb)->obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002705 dev_priv = crtc->dev->dev_private;
2706 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002707 atomic_read(&obj->pending_flip) == 0);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002708}
2709
Jesse Barnes040484a2011-01-03 12:14:26 -08002710static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2711{
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_mode_config *mode_config = &dev->mode_config;
2714 struct intel_encoder *encoder;
2715
2716 /*
2717 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2718 * must be driven by its own crtc; no sharing is possible.
2719 */
2720 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2721 if (encoder->base.crtc != crtc)
2722 continue;
2723
2724 switch (encoder->type) {
2725 case INTEL_OUTPUT_EDP:
2726 if (!intel_encoder_is_pch_edp(&encoder->base))
2727 return false;
2728 continue;
2729 }
2730 }
2731
2732 return true;
2733}
2734
Jesse Barnesf67a5592011-01-05 10:31:48 -08002735/*
2736 * Enable PCH resources required for PCH ports:
2737 * - PCH PLLs
2738 * - FDI training & RX/TX
2739 * - update transcoder timings
2740 * - DP transcoding bits
2741 * - transcoder
2742 */
2743static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002744{
2745 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2748 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002749 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002750
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002751 /* For PCH output, training FDI link */
2752 if (IS_GEN6(dev))
2753 gen6_fdi_link_train(crtc);
2754 else
2755 ironlake_fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002756
Jesse Barnes92f25842011-01-04 15:09:34 -08002757 intel_enable_pch_pll(dev_priv, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002758
2759 if (HAS_PCH_CPT(dev)) {
2760 /* Be sure PCH DPLL SEL is set */
2761 temp = I915_READ(PCH_DPLL_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002762 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002763 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
Chris Wilson5eddb702010-09-11 13:48:45 +01002764 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002765 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2766 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002767 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002768
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002769 /* set transcoder timing, panel must allow it */
2770 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01002771 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2772 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2773 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2774
2775 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2776 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2777 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002778
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002779 intel_fdi_normal_train(crtc);
2780
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002781 /* For PCH DP, enable TRANS_DP_CTL */
2782 if (HAS_PCH_CPT(dev) &&
2783 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002784 reg = TRANS_DP_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002787 TRANS_DP_SYNC_MASK |
2788 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01002789 temp |= (TRANS_DP_OUTPUT_ENABLE |
2790 TRANS_DP_ENH_FRAMING);
Eric Anholt220cad32010-11-18 09:32:58 +08002791 temp |= TRANS_DP_8BPC;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002792
2793 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002794 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002795 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002796 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002797
2798 switch (intel_trans_dp_port_sel(crtc)) {
2799 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01002800 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002801 break;
2802 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01002803 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002804 break;
2805 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01002806 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002807 break;
2808 default:
2809 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002810 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002811 break;
2812 }
2813
Chris Wilson5eddb702010-09-11 13:48:45 +01002814 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002815 }
2816
Jesse Barnes040484a2011-01-03 12:14:26 -08002817 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002818}
2819
2820static void ironlake_crtc_enable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 int plane = intel_crtc->plane;
2827 u32 temp;
2828 bool is_pch_port;
2829
2830 if (intel_crtc->active)
2831 return;
2832
2833 intel_crtc->active = true;
2834 intel_update_watermarks(dev);
2835
2836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2837 temp = I915_READ(PCH_LVDS);
2838 if ((temp & LVDS_PORT_EN) == 0)
2839 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2840 }
2841
2842 is_pch_port = intel_crtc_driving_pch(crtc);
2843
2844 if (is_pch_port)
2845 ironlake_fdi_enable(crtc);
2846 else
2847 ironlake_fdi_disable(crtc);
2848
2849 /* Enable panel fitting for LVDS */
2850 if (dev_priv->pch_pf_size &&
2851 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2852 /* Force use of hard-coded filter coefficients
2853 * as some pre-programmed values are broken,
2854 * e.g. x201.
2855 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002856 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2857 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2858 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08002859 }
2860
2861 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2862 intel_enable_plane(dev_priv, plane, pipe);
2863
2864 if (is_pch_port)
2865 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002866
2867 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01002868 intel_update_fbc(dev);
Chris Wilson6b383a72010-09-13 13:54:26 +01002869 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002870}
2871
2872static void ironlake_crtc_disable(struct drm_crtc *crtc)
2873{
2874 struct drm_device *dev = crtc->dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877 int pipe = intel_crtc->pipe;
2878 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002879 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002880
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002881 if (!intel_crtc->active)
2882 return;
2883
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002884 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002885 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01002886 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01002887
Jesse Barnesb24e7172011-01-04 15:09:30 -08002888 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002889
2890 if (dev_priv->cfb_plane == plane &&
2891 dev_priv->display.disable_fbc)
2892 dev_priv->display.disable_fbc(dev);
2893
Jesse Barnesb24e7172011-01-04 15:09:30 -08002894 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002895
Jesse Barnes6be4a602010-09-10 10:26:01 -07002896 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002897 I915_WRITE(PF_CTL(pipe), 0);
2898 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002899
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002900 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002901
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002902 /* This is a horrible layering violation; we should be doing this in
2903 * the connector/encoder ->prepare instead, but we don't always have
2904 * enough information there about the config to know whether it will
2905 * actually be necessary or just cause undesired flicker.
2906 */
2907 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002908
Jesse Barnes040484a2011-01-03 12:14:26 -08002909 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002910
Jesse Barnes6be4a602010-09-10 10:26:01 -07002911 if (HAS_PCH_CPT(dev)) {
2912 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002913 reg = TRANS_DP_CTL(pipe);
2914 temp = I915_READ(reg);
2915 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08002916 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01002917 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002918
2919 /* disable DPLL_SEL */
2920 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002921 switch (pipe) {
2922 case 0:
2923 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2924 break;
2925 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07002926 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002927 break;
2928 case 2:
2929 /* FIXME: manage transcoder PLLs? */
2930 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2931 break;
2932 default:
2933 BUG(); /* wtf */
2934 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07002935 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002936 }
2937
2938 /* disable PCH DPLL */
Jesse Barnes92f25842011-01-04 15:09:34 -08002939 intel_disable_pch_pll(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002940
2941 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002942 reg = FDI_RX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002945
2946 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01002947 reg = FDI_TX_CTL(pipe);
2948 temp = I915_READ(reg);
2949 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2950
2951 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002952 udelay(100);
2953
Chris Wilson5eddb702010-09-11 13:48:45 +01002954 reg = FDI_RX_CTL(pipe);
2955 temp = I915_READ(reg);
2956 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002957
2958 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01002959 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002960 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01002961
Chris Wilsonf7abfe82010-09-13 14:19:16 +01002962 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01002963 intel_update_watermarks(dev);
2964 intel_update_fbc(dev);
2965 intel_clear_scanline_wait(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002966}
2967
2968static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2969{
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 int pipe = intel_crtc->pipe;
2972 int plane = intel_crtc->plane;
2973
Zhenyu Wang2c072452009-06-05 15:38:42 +08002974 /* XXX: When our outputs are all unaware of DPMS modes other than off
2975 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2976 */
2977 switch (mode) {
2978 case DRM_MODE_DPMS_ON:
2979 case DRM_MODE_DPMS_STANDBY:
2980 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01002981 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002982 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01002983 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08002984
Zhenyu Wang2c072452009-06-05 15:38:42 +08002985 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01002986 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002987 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08002988 break;
2989 }
2990}
2991
Daniel Vetter02e792f2009-09-15 22:57:34 +02002992static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2993{
Daniel Vetter02e792f2009-09-15 22:57:34 +02002994 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01002995 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00002996 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02002997
Chris Wilson23f09ce2010-08-12 13:53:37 +01002998 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00002999 dev_priv->mm.interruptible = false;
3000 (void) intel_overlay_switch_off(intel_crtc->overlay);
3001 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003002 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003003 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003004
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003005 /* Let userspace switch the overlay on again. In most cases userspace
3006 * has to recompute where to put it anyway.
3007 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003008}
3009
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003010static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003011{
3012 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003016 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003017
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003018 if (intel_crtc->active)
3019 return;
3020
3021 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003022 intel_update_watermarks(dev);
3023
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003024 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003025 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003026 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003027
3028 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003029 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003030
3031 /* Give the overlay scaler a chance to enable if it's on this pipe */
3032 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003033 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003034}
3035
3036static void i9xx_crtc_disable(struct drm_crtc *crtc)
3037{
3038 struct drm_device *dev = crtc->dev;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041 int pipe = intel_crtc->pipe;
3042 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003043
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003044 if (!intel_crtc->active)
3045 return;
3046
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003047 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003048 intel_crtc_wait_for_pending_flips(crtc);
3049 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003050 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003051 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003052
3053 if (dev_priv->cfb_plane == plane &&
3054 dev_priv->display.disable_fbc)
3055 dev_priv->display.disable_fbc(dev);
3056
Jesse Barnesb24e7172011-01-04 15:09:30 -08003057 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003058 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003059 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003060
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003061 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003062 intel_update_fbc(dev);
3063 intel_update_watermarks(dev);
3064 intel_clear_scanline_wait(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003065}
3066
3067static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3068{
Jesse Barnes79e53942008-11-07 14:24:08 -08003069 /* XXX: When our outputs are all unaware of DPMS modes other than off
3070 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3071 */
3072 switch (mode) {
3073 case DRM_MODE_DPMS_ON:
3074 case DRM_MODE_DPMS_STANDBY:
3075 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003076 i9xx_crtc_enable(crtc);
3077 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003078 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003079 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003080 break;
3081 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003082}
3083
3084/**
3085 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08003086 */
3087static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3088{
3089 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07003090 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003091 struct drm_i915_master_private *master_priv;
3092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3093 int pipe = intel_crtc->pipe;
3094 bool enabled;
3095
Chris Wilson032d2a02010-09-06 16:17:22 +01003096 if (intel_crtc->dpms_mode == mode)
3097 return;
3098
Chris Wilsondebcadd2010-08-07 11:01:33 +01003099 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01003100
Jesse Barnese70236a2009-09-21 10:42:27 -07003101 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08003102
3103 if (!dev->primary->master)
3104 return;
3105
3106 master_priv = dev->primary->master->driver_priv;
3107 if (!master_priv->sarea_priv)
3108 return;
3109
3110 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3111
3112 switch (pipe) {
3113 case 0:
3114 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3115 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3116 break;
3117 case 1:
3118 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3119 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3120 break;
3121 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003122 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003123 break;
3124 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003125}
3126
Chris Wilsoncdd59982010-09-08 16:30:16 +01003127static void intel_crtc_disable(struct drm_crtc *crtc)
3128{
3129 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3130 struct drm_device *dev = crtc->dev;
3131
3132 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3133
3134 if (crtc->fb) {
3135 mutex_lock(&dev->struct_mutex);
3136 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3137 mutex_unlock(&dev->struct_mutex);
3138 }
3139}
3140
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003141/* Prepare for a mode set.
3142 *
3143 * Note we could be a lot smarter here. We need to figure out which outputs
3144 * will be enabled, which disabled (in short, how the config will changes)
3145 * and perform the minimum necessary steps to accomplish that, e.g. updating
3146 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3147 * panel fitting is in the proper state, etc.
3148 */
3149static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003150{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003151 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003152}
3153
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003154static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003155{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003156 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003157}
3158
3159static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3160{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003161 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003162}
3163
3164static void ironlake_crtc_commit(struct drm_crtc *crtc)
3165{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003166 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003167}
3168
3169void intel_encoder_prepare (struct drm_encoder *encoder)
3170{
3171 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3172 /* lvds has its own version of prepare see intel_lvds_prepare */
3173 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3174}
3175
3176void intel_encoder_commit (struct drm_encoder *encoder)
3177{
3178 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3179 /* lvds has its own version of commit see intel_lvds_commit */
3180 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3181}
3182
Chris Wilsonea5b2132010-08-04 13:50:23 +01003183void intel_encoder_destroy(struct drm_encoder *encoder)
3184{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003185 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003186
Chris Wilsonea5b2132010-08-04 13:50:23 +01003187 drm_encoder_cleanup(encoder);
3188 kfree(intel_encoder);
3189}
3190
Jesse Barnes79e53942008-11-07 14:24:08 -08003191static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3192 struct drm_display_mode *mode,
3193 struct drm_display_mode *adjusted_mode)
3194{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003195 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003196
Eric Anholtbad720f2009-10-22 16:11:14 -07003197 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003198 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003199 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3200 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003201 }
Chris Wilson89749352010-09-12 18:25:19 +01003202
3203 /* XXX some encoders set the crtcinfo, others don't.
3204 * Obviously we need some form of conflict resolution here...
3205 */
3206 if (adjusted_mode->crtc_htotal == 0)
3207 drm_mode_set_crtcinfo(adjusted_mode, 0);
3208
Jesse Barnes79e53942008-11-07 14:24:08 -08003209 return true;
3210}
3211
Jesse Barnese70236a2009-09-21 10:42:27 -07003212static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003213{
Jesse Barnese70236a2009-09-21 10:42:27 -07003214 return 400000;
3215}
Jesse Barnes79e53942008-11-07 14:24:08 -08003216
Jesse Barnese70236a2009-09-21 10:42:27 -07003217static int i915_get_display_clock_speed(struct drm_device *dev)
3218{
3219 return 333000;
3220}
Jesse Barnes79e53942008-11-07 14:24:08 -08003221
Jesse Barnese70236a2009-09-21 10:42:27 -07003222static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3223{
3224 return 200000;
3225}
Jesse Barnes79e53942008-11-07 14:24:08 -08003226
Jesse Barnese70236a2009-09-21 10:42:27 -07003227static int i915gm_get_display_clock_speed(struct drm_device *dev)
3228{
3229 u16 gcfgc = 0;
3230
3231 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3232
3233 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003234 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003235 else {
3236 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3237 case GC_DISPLAY_CLOCK_333_MHZ:
3238 return 333000;
3239 default:
3240 case GC_DISPLAY_CLOCK_190_200_MHZ:
3241 return 190000;
3242 }
3243 }
3244}
Jesse Barnes79e53942008-11-07 14:24:08 -08003245
Jesse Barnese70236a2009-09-21 10:42:27 -07003246static int i865_get_display_clock_speed(struct drm_device *dev)
3247{
3248 return 266000;
3249}
3250
3251static int i855_get_display_clock_speed(struct drm_device *dev)
3252{
3253 u16 hpllcc = 0;
3254 /* Assume that the hardware is in the high speed state. This
3255 * should be the default.
3256 */
3257 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3258 case GC_CLOCK_133_200:
3259 case GC_CLOCK_100_200:
3260 return 200000;
3261 case GC_CLOCK_166_250:
3262 return 250000;
3263 case GC_CLOCK_100_133:
3264 return 133000;
3265 }
3266
3267 /* Shouldn't happen */
3268 return 0;
3269}
3270
3271static int i830_get_display_clock_speed(struct drm_device *dev)
3272{
3273 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003274}
3275
Zhenyu Wang2c072452009-06-05 15:38:42 +08003276struct fdi_m_n {
3277 u32 tu;
3278 u32 gmch_m;
3279 u32 gmch_n;
3280 u32 link_m;
3281 u32 link_n;
3282};
3283
3284static void
3285fdi_reduce_ratio(u32 *num, u32 *den)
3286{
3287 while (*num > 0xffffff || *den > 0xffffff) {
3288 *num >>= 1;
3289 *den >>= 1;
3290 }
3291}
3292
Zhenyu Wang2c072452009-06-05 15:38:42 +08003293static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003294ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3295 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003296{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003297 m_n->tu = 64; /* default size */
3298
Chris Wilson22ed1112010-12-04 01:01:29 +00003299 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3300 m_n->gmch_m = bits_per_pixel * pixel_clock;
3301 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003302 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3303
Chris Wilson22ed1112010-12-04 01:01:29 +00003304 m_n->link_m = pixel_clock;
3305 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003306 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3307}
3308
3309
Shaohua Li7662c8b2009-06-26 11:23:55 +08003310struct intel_watermark_params {
3311 unsigned long fifo_size;
3312 unsigned long max_wm;
3313 unsigned long default_wm;
3314 unsigned long guard_size;
3315 unsigned long cacheline_size;
3316};
3317
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003318/* Pineview has different values for various configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003319static const struct intel_watermark_params pineview_display_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003320 PINEVIEW_DISPLAY_FIFO,
3321 PINEVIEW_MAX_WM,
3322 PINEVIEW_DFT_WM,
3323 PINEVIEW_GUARD_WM,
3324 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003325};
Chris Wilsond2102462011-01-24 17:43:27 +00003326static const struct intel_watermark_params pineview_display_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003327 PINEVIEW_DISPLAY_FIFO,
3328 PINEVIEW_MAX_WM,
3329 PINEVIEW_DFT_HPLLOFF_WM,
3330 PINEVIEW_GUARD_WM,
3331 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003332};
Chris Wilsond2102462011-01-24 17:43:27 +00003333static const struct intel_watermark_params pineview_cursor_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003334 PINEVIEW_CURSOR_FIFO,
3335 PINEVIEW_CURSOR_MAX_WM,
3336 PINEVIEW_CURSOR_DFT_WM,
3337 PINEVIEW_CURSOR_GUARD_WM,
3338 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003339};
Chris Wilsond2102462011-01-24 17:43:27 +00003340static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003341 PINEVIEW_CURSOR_FIFO,
3342 PINEVIEW_CURSOR_MAX_WM,
3343 PINEVIEW_CURSOR_DFT_WM,
3344 PINEVIEW_CURSOR_GUARD_WM,
3345 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003346};
Chris Wilsond2102462011-01-24 17:43:27 +00003347static const struct intel_watermark_params g4x_wm_info = {
Jesse Barnes0e442c62009-10-19 10:09:33 +09003348 G4X_FIFO_SIZE,
3349 G4X_MAX_WM,
3350 G4X_MAX_WM,
3351 2,
3352 G4X_FIFO_LINE_SIZE,
3353};
Chris Wilsond2102462011-01-24 17:43:27 +00003354static const struct intel_watermark_params g4x_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003355 I965_CURSOR_FIFO,
3356 I965_CURSOR_MAX_WM,
3357 I965_CURSOR_DFT_WM,
3358 2,
3359 G4X_FIFO_LINE_SIZE,
3360};
Chris Wilsond2102462011-01-24 17:43:27 +00003361static const struct intel_watermark_params i965_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003362 I965_CURSOR_FIFO,
3363 I965_CURSOR_MAX_WM,
3364 I965_CURSOR_DFT_WM,
3365 2,
3366 I915_FIFO_LINE_SIZE,
3367};
Chris Wilsond2102462011-01-24 17:43:27 +00003368static const struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003369 I945_FIFO_SIZE,
3370 I915_MAX_WM,
3371 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003372 2,
3373 I915_FIFO_LINE_SIZE
3374};
Chris Wilsond2102462011-01-24 17:43:27 +00003375static const struct intel_watermark_params i915_wm_info = {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003376 I915_FIFO_SIZE,
3377 I915_MAX_WM,
3378 1,
3379 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003380 I915_FIFO_LINE_SIZE
3381};
Chris Wilsond2102462011-01-24 17:43:27 +00003382static const struct intel_watermark_params i855_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003383 I855GM_FIFO_SIZE,
3384 I915_MAX_WM,
3385 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003386 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003387 I830_FIFO_LINE_SIZE
3388};
Chris Wilsond2102462011-01-24 17:43:27 +00003389static const struct intel_watermark_params i830_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003390 I830_FIFO_SIZE,
3391 I915_MAX_WM,
3392 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003393 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003394 I830_FIFO_LINE_SIZE
3395};
3396
Chris Wilsond2102462011-01-24 17:43:27 +00003397static const struct intel_watermark_params ironlake_display_wm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003398 ILK_DISPLAY_FIFO,
3399 ILK_DISPLAY_MAXWM,
3400 ILK_DISPLAY_DFTWM,
3401 2,
3402 ILK_FIFO_LINE_SIZE
3403};
Chris Wilsond2102462011-01-24 17:43:27 +00003404static const struct intel_watermark_params ironlake_cursor_wm_info = {
Zhao Yakuic936f442010-06-12 14:32:26 +08003405 ILK_CURSOR_FIFO,
3406 ILK_CURSOR_MAXWM,
3407 ILK_CURSOR_DFTWM,
3408 2,
3409 ILK_FIFO_LINE_SIZE
3410};
Chris Wilsond2102462011-01-24 17:43:27 +00003411static const struct intel_watermark_params ironlake_display_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003412 ILK_DISPLAY_SR_FIFO,
3413 ILK_DISPLAY_MAX_SRWM,
3414 ILK_DISPLAY_DFT_SRWM,
3415 2,
3416 ILK_FIFO_LINE_SIZE
3417};
Chris Wilsond2102462011-01-24 17:43:27 +00003418static const struct intel_watermark_params ironlake_cursor_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003419 ILK_CURSOR_SR_FIFO,
3420 ILK_CURSOR_MAX_SRWM,
3421 ILK_CURSOR_DFT_SRWM,
3422 2,
3423 ILK_FIFO_LINE_SIZE
3424};
3425
Chris Wilsond2102462011-01-24 17:43:27 +00003426static const struct intel_watermark_params sandybridge_display_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003427 SNB_DISPLAY_FIFO,
3428 SNB_DISPLAY_MAXWM,
3429 SNB_DISPLAY_DFTWM,
3430 2,
3431 SNB_FIFO_LINE_SIZE
3432};
Chris Wilsond2102462011-01-24 17:43:27 +00003433static const struct intel_watermark_params sandybridge_cursor_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003434 SNB_CURSOR_FIFO,
3435 SNB_CURSOR_MAXWM,
3436 SNB_CURSOR_DFTWM,
3437 2,
3438 SNB_FIFO_LINE_SIZE
3439};
Chris Wilsond2102462011-01-24 17:43:27 +00003440static const struct intel_watermark_params sandybridge_display_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003441 SNB_DISPLAY_SR_FIFO,
3442 SNB_DISPLAY_MAX_SRWM,
3443 SNB_DISPLAY_DFT_SRWM,
3444 2,
3445 SNB_FIFO_LINE_SIZE
3446};
Chris Wilsond2102462011-01-24 17:43:27 +00003447static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003448 SNB_CURSOR_SR_FIFO,
3449 SNB_CURSOR_MAX_SRWM,
3450 SNB_CURSOR_DFT_SRWM,
3451 2,
3452 SNB_FIFO_LINE_SIZE
3453};
3454
3455
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003456/**
3457 * intel_calculate_wm - calculate watermark level
3458 * @clock_in_khz: pixel clock
3459 * @wm: chip FIFO params
3460 * @pixel_size: display pixel size
3461 * @latency_ns: memory latency for the platform
3462 *
3463 * Calculate the watermark level (the level at which the display plane will
3464 * start fetching from memory again). Each chip has a different display
3465 * FIFO size and allocation, so the caller needs to figure that out and pass
3466 * in the correct intel_watermark_params structure.
3467 *
3468 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3469 * on the pixel size. When it reaches the watermark level, it'll start
3470 * fetching FIFO line sized based chunks from memory until the FIFO fills
3471 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3472 * will occur, and a display engine hang could result.
3473 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003474static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
Chris Wilsond2102462011-01-24 17:43:27 +00003475 const struct intel_watermark_params *wm,
3476 int fifo_size,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003477 int pixel_size,
3478 unsigned long latency_ns)
3479{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003480 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003481
Jesse Barnesd6604672009-09-11 12:25:56 -07003482 /*
3483 * Note: we need to make sure we don't overflow for various clock &
3484 * latency values.
3485 * clocks go from a few thousand to several hundred thousand.
3486 * latency is usually a few thousand
3487 */
3488 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3489 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003490 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003491
Zhao Yakui28c97732009-10-09 11:39:41 +08003492 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003493
Chris Wilsond2102462011-01-24 17:43:27 +00003494 wm_size = fifo_size - (entries_required + wm->guard_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003495
Zhao Yakui28c97732009-10-09 11:39:41 +08003496 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003497
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003498 /* Don't promote wm_size to unsigned... */
3499 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003500 wm_size = wm->max_wm;
Chris Wilsonc3add4b2010-09-08 09:14:08 +01003501 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003502 wm_size = wm->default_wm;
3503 return wm_size;
3504}
3505
3506struct cxsr_latency {
3507 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08003508 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003509 unsigned long fsb_freq;
3510 unsigned long mem_freq;
3511 unsigned long display_sr;
3512 unsigned long display_hpll_disable;
3513 unsigned long cursor_sr;
3514 unsigned long cursor_hpll_disable;
3515};
3516
Chris Wilson403c89f2010-08-04 15:25:31 +01003517static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08003518 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3519 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3520 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3521 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3522 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003523
Li Peng95534262010-05-18 18:58:44 +08003524 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3525 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3526 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3527 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3528 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003529
Li Peng95534262010-05-18 18:58:44 +08003530 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3531 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3532 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3533 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3534 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003535
Li Peng95534262010-05-18 18:58:44 +08003536 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3537 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3538 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3539 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3540 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003541
Li Peng95534262010-05-18 18:58:44 +08003542 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3543 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3544 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3545 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3546 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003547
Li Peng95534262010-05-18 18:58:44 +08003548 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3549 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3550 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3551 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3552 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003553};
3554
Chris Wilson403c89f2010-08-04 15:25:31 +01003555static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3556 int is_ddr3,
3557 int fsb,
3558 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003559{
Chris Wilson403c89f2010-08-04 15:25:31 +01003560 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003561 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003562
3563 if (fsb == 0 || mem == 0)
3564 return NULL;
3565
3566 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3567 latency = &cxsr_latency_table[i];
3568 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08003569 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303570 fsb == latency->fsb_freq && mem == latency->mem_freq)
3571 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003572 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303573
Zhao Yakui28c97732009-10-09 11:39:41 +08003574 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303575
3576 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003577}
3578
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003579static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003580{
3581 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003582
3583 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003584 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003585}
3586
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07003587/*
3588 * Latency for FIFO fetches is dependent on several factors:
3589 * - memory configuration (speed, channels)
3590 * - chipset
3591 * - current MCH state
3592 * It can be fairly high in some situations, so here we assume a fairly
3593 * pessimal value. It's a tradeoff between extra memory fetches (if we
3594 * set this value too high, the FIFO will fetch frequently to stay full)
3595 * and power consumption (set it too low to save power and we might see
3596 * FIFO underruns and display "flicker").
3597 *
3598 * A value of 5us seems to be a good balance; safe for very low end
3599 * platforms but not overly aggressive on lower latency configs.
3600 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003601static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003602
Jesse Barnese70236a2009-09-21 10:42:27 -07003603static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003604{
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 uint32_t dsparb = I915_READ(DSPARB);
3607 int size;
3608
Chris Wilson8de9b312010-07-19 19:59:52 +01003609 size = dsparb & 0x7f;
3610 if (plane)
3611 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003612
Zhao Yakui28c97732009-10-09 11:39:41 +08003613 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003614 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003615
3616 return size;
3617}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003618
Jesse Barnese70236a2009-09-21 10:42:27 -07003619static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3620{
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 uint32_t dsparb = I915_READ(DSPARB);
3623 int size;
3624
Chris Wilson8de9b312010-07-19 19:59:52 +01003625 size = dsparb & 0x1ff;
3626 if (plane)
3627 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07003628 size >>= 1; /* Convert to cachelines */
3629
Zhao Yakui28c97732009-10-09 11:39:41 +08003630 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003631 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003632
3633 return size;
3634}
3635
3636static int i845_get_fifo_size(struct drm_device *dev, int plane)
3637{
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639 uint32_t dsparb = I915_READ(DSPARB);
3640 int size;
3641
3642 size = dsparb & 0x7f;
3643 size >>= 2; /* Convert to cachelines */
3644
Zhao Yakui28c97732009-10-09 11:39:41 +08003645 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003646 plane ? "B" : "A",
3647 size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003648
3649 return size;
3650}
3651
3652static int i830_get_fifo_size(struct drm_device *dev, int plane)
3653{
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 uint32_t dsparb = I915_READ(DSPARB);
3656 int size;
3657
3658 size = dsparb & 0x7f;
3659 size >>= 1; /* Convert to cachelines */
3660
Zhao Yakui28c97732009-10-09 11:39:41 +08003661 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003662 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003663
3664 return size;
3665}
3666
Chris Wilsond2102462011-01-24 17:43:27 +00003667static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3668{
3669 struct drm_crtc *crtc, *enabled = NULL;
3670
3671 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3672 if (crtc->enabled && crtc->fb) {
3673 if (enabled)
3674 return NULL;
3675 enabled = crtc;
3676 }
3677 }
3678
3679 return enabled;
3680}
3681
3682static void pineview_update_wm(struct drm_device *dev)
Zhao Yakuid4294342010-03-22 22:45:36 +08003683{
3684 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003685 struct drm_crtc *crtc;
Chris Wilson403c89f2010-08-04 15:25:31 +01003686 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003687 u32 reg;
3688 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003689
Chris Wilson403c89f2010-08-04 15:25:31 +01003690 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003691 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003692 if (!latency) {
3693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3694 pineview_disable_cxsr(dev);
3695 return;
3696 }
3697
Chris Wilsond2102462011-01-24 17:43:27 +00003698 crtc = single_enabled_crtc(dev);
3699 if (crtc) {
3700 int clock = crtc->mode.clock;
3701 int pixel_size = crtc->fb->bits_per_pixel / 8;
Zhao Yakuid4294342010-03-22 22:45:36 +08003702
3703 /* Display SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003704 wm = intel_calculate_wm(clock, &pineview_display_wm,
3705 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003706 pixel_size, latency->display_sr);
3707 reg = I915_READ(DSPFW1);
3708 reg &= ~DSPFW_SR_MASK;
3709 reg |= wm << DSPFW_SR_SHIFT;
3710 I915_WRITE(DSPFW1, reg);
3711 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3712
3713 /* cursor SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003714 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3715 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003716 pixel_size, latency->cursor_sr);
3717 reg = I915_READ(DSPFW3);
3718 reg &= ~DSPFW_CURSOR_SR_MASK;
3719 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3720 I915_WRITE(DSPFW3, reg);
3721
3722 /* Display HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003723 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3724 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003725 pixel_size, latency->display_hpll_disable);
3726 reg = I915_READ(DSPFW3);
3727 reg &= ~DSPFW_HPLL_SR_MASK;
3728 reg |= wm & DSPFW_HPLL_SR_MASK;
3729 I915_WRITE(DSPFW3, reg);
3730
3731 /* cursor HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003732 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3733 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003734 pixel_size, latency->cursor_hpll_disable);
3735 reg = I915_READ(DSPFW3);
3736 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3737 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3738 I915_WRITE(DSPFW3, reg);
3739 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3740
3741 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003742 I915_WRITE(DSPFW3,
3743 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003744 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3745 } else {
3746 pineview_disable_cxsr(dev);
3747 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3748 }
3749}
3750
Chris Wilson417ae142011-01-19 15:04:42 +00003751static bool g4x_compute_wm0(struct drm_device *dev,
3752 int plane,
3753 const struct intel_watermark_params *display,
3754 int display_latency_ns,
3755 const struct intel_watermark_params *cursor,
3756 int cursor_latency_ns,
3757 int *plane_wm,
3758 int *cursor_wm)
Jesse Barnes652c3932009-08-17 13:31:43 -07003759{
Chris Wilson417ae142011-01-19 15:04:42 +00003760 struct drm_crtc *crtc;
3761 int htotal, hdisplay, clock, pixel_size;
3762 int line_time_us, line_count;
3763 int entries, tlb_miss;
Jesse Barnes652c3932009-08-17 13:31:43 -07003764
Chris Wilson417ae142011-01-19 15:04:42 +00003765 crtc = intel_get_crtc_for_plane(dev, plane);
3766 if (crtc->fb == NULL || !crtc->enabled)
3767 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003768
Chris Wilson417ae142011-01-19 15:04:42 +00003769 htotal = crtc->mode.htotal;
3770 hdisplay = crtc->mode.hdisplay;
3771 clock = crtc->mode.clock;
3772 pixel_size = crtc->fb->bits_per_pixel / 8;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003773
Chris Wilson417ae142011-01-19 15:04:42 +00003774 /* Use the small buffer method to calculate plane watermark */
3775 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3776 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3777 if (tlb_miss > 0)
3778 entries += tlb_miss;
3779 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3780 *plane_wm = entries + display->guard_size;
3781 if (*plane_wm > (int)display->max_wm)
3782 *plane_wm = display->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003783
Chris Wilson417ae142011-01-19 15:04:42 +00003784 /* Use the large buffer method to calculate cursor watermark */
3785 line_time_us = ((htotal * 1000) / clock);
3786 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3787 entries = line_count * 64 * pixel_size;
3788 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3789 if (tlb_miss > 0)
3790 entries += tlb_miss;
3791 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3792 *cursor_wm = entries + cursor->guard_size;
3793 if (*cursor_wm > (int)cursor->max_wm)
3794 *cursor_wm = (int)cursor->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003795
Chris Wilson417ae142011-01-19 15:04:42 +00003796 return true;
3797}
Jesse Barnes0e442c62009-10-19 10:09:33 +09003798
Chris Wilson417ae142011-01-19 15:04:42 +00003799/*
3800 * Check the wm result.
3801 *
3802 * If any calculated watermark values is larger than the maximum value that
3803 * can be programmed into the associated watermark register, that watermark
3804 * must be disabled.
3805 */
3806static bool g4x_check_srwm(struct drm_device *dev,
3807 int display_wm, int cursor_wm,
3808 const struct intel_watermark_params *display,
3809 const struct intel_watermark_params *cursor)
3810{
3811 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3812 display_wm, cursor_wm);
Jesse Barnes0e442c62009-10-19 10:09:33 +09003813
Chris Wilson417ae142011-01-19 15:04:42 +00003814 if (display_wm > display->max_wm) {
3815 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3816 display_wm, display->max_wm);
3817 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09003818 }
3819
Chris Wilson417ae142011-01-19 15:04:42 +00003820 if (cursor_wm > cursor->max_wm) {
3821 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3822 cursor_wm, cursor->max_wm);
3823 return false;
3824 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003825
Chris Wilson417ae142011-01-19 15:04:42 +00003826 if (!(display_wm || cursor_wm)) {
3827 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3828 return false;
3829 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09003830
Chris Wilson417ae142011-01-19 15:04:42 +00003831 return true;
3832}
3833
3834static bool g4x_compute_srwm(struct drm_device *dev,
Chris Wilsond2102462011-01-24 17:43:27 +00003835 int plane,
3836 int latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00003837 const struct intel_watermark_params *display,
3838 const struct intel_watermark_params *cursor,
3839 int *display_wm, int *cursor_wm)
3840{
Chris Wilsond2102462011-01-24 17:43:27 +00003841 struct drm_crtc *crtc;
3842 int hdisplay, htotal, pixel_size, clock;
Chris Wilson417ae142011-01-19 15:04:42 +00003843 unsigned long line_time_us;
3844 int line_count, line_size;
3845 int small, large;
3846 int entries;
3847
3848 if (!latency_ns) {
3849 *display_wm = *cursor_wm = 0;
3850 return false;
3851 }
3852
Chris Wilsond2102462011-01-24 17:43:27 +00003853 crtc = intel_get_crtc_for_plane(dev, plane);
3854 hdisplay = crtc->mode.hdisplay;
3855 htotal = crtc->mode.htotal;
3856 clock = crtc->mode.clock;
3857 pixel_size = crtc->fb->bits_per_pixel / 8;
3858
Chris Wilson417ae142011-01-19 15:04:42 +00003859 line_time_us = (htotal * 1000) / clock;
3860 line_count = (latency_ns / line_time_us + 1000) / 1000;
3861 line_size = hdisplay * pixel_size;
3862
3863 /* Use the minimum of the small and large buffer method for primary */
3864 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3865 large = line_count * line_size;
3866
3867 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3868 *display_wm = entries + display->guard_size;
3869
3870 /* calculate the self-refresh watermark for display cursor */
3871 entries = line_count * pixel_size * 64;
3872 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3873 *cursor_wm = entries + cursor->guard_size;
3874
3875 return g4x_check_srwm(dev,
3876 *display_wm, *cursor_wm,
3877 display, cursor);
3878}
3879
Chris Wilsond2102462011-01-24 17:43:27 +00003880static inline bool single_plane_enabled(unsigned int mask)
3881{
3882 return mask && (mask & -mask) == 0;
3883}
3884
3885static void g4x_update_wm(struct drm_device *dev)
Chris Wilson417ae142011-01-19 15:04:42 +00003886{
3887 static const int sr_latency_ns = 12000;
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00003890 int plane_sr, cursor_sr;
3891 unsigned int enabled = 0;
Chris Wilson417ae142011-01-19 15:04:42 +00003892
3893 if (g4x_compute_wm0(dev, 0,
3894 &g4x_wm_info, latency_ns,
3895 &g4x_cursor_wm_info, latency_ns,
3896 &planea_wm, &cursora_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00003897 enabled |= 1;
Chris Wilson417ae142011-01-19 15:04:42 +00003898
3899 if (g4x_compute_wm0(dev, 1,
3900 &g4x_wm_info, latency_ns,
3901 &g4x_cursor_wm_info, latency_ns,
3902 &planeb_wm, &cursorb_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00003903 enabled |= 2;
Chris Wilson417ae142011-01-19 15:04:42 +00003904
3905 plane_sr = cursor_sr = 0;
Chris Wilsond2102462011-01-24 17:43:27 +00003906 if (single_plane_enabled(enabled) &&
3907 g4x_compute_srwm(dev, ffs(enabled) - 1,
3908 sr_latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00003909 &g4x_wm_info,
3910 &g4x_cursor_wm_info,
3911 &plane_sr, &cursor_sr))
3912 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3913 else
3914 I915_WRITE(FW_BLC_SELF,
3915 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3916
Chris Wilson308977a2011-02-02 10:41:20 +00003917 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3918 planea_wm, cursora_wm,
3919 planeb_wm, cursorb_wm,
3920 plane_sr, cursor_sr);
Chris Wilson417ae142011-01-19 15:04:42 +00003921
3922 I915_WRITE(DSPFW1,
3923 (plane_sr << DSPFW_SR_SHIFT) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003924 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
Chris Wilson417ae142011-01-19 15:04:42 +00003925 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3926 planea_wm);
3927 I915_WRITE(DSPFW2,
3928 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003929 (cursora_wm << DSPFW_CURSORA_SHIFT));
3930 /* HPLL off in SR has some issues on G4x... disable it */
Chris Wilson417ae142011-01-19 15:04:42 +00003931 I915_WRITE(DSPFW3,
3932 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09003933 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07003934}
3935
Chris Wilsond2102462011-01-24 17:43:27 +00003936static void i965_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003937{
3938 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003939 struct drm_crtc *crtc;
3940 int srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003941 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003942
Jesse Barnes1dc75462009-10-19 10:08:17 +09003943 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003944 crtc = single_enabled_crtc(dev);
3945 if (crtc) {
Jesse Barnes1dc75462009-10-19 10:08:17 +09003946 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003947 static const int sr_latency_ns = 12000;
Chris Wilsond2102462011-01-24 17:43:27 +00003948 int clock = crtc->mode.clock;
3949 int htotal = crtc->mode.htotal;
3950 int hdisplay = crtc->mode.hdisplay;
3951 int pixel_size = crtc->fb->bits_per_pixel / 8;
3952 unsigned long line_time_us;
3953 int entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003954
Chris Wilsond2102462011-01-24 17:43:27 +00003955 line_time_us = ((htotal * 1000) / clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003956
3957 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00003958 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3959 pixel_size * hdisplay;
3960 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
Chris Wilsond2102462011-01-24 17:43:27 +00003961 srwm = I965_FIFO_SIZE - entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09003962 if (srwm < 0)
3963 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08003964 srwm &= 0x1ff;
Chris Wilson308977a2011-02-02 10:41:20 +00003965 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3966 entries, srwm);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003967
Chris Wilsond2102462011-01-24 17:43:27 +00003968 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01003969 pixel_size * 64;
Chris Wilsond2102462011-01-24 17:43:27 +00003970 entries = DIV_ROUND_UP(entries,
Chris Wilson8de9b312010-07-19 19:59:52 +01003971 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003972 cursor_sr = i965_cursor_wm_info.fifo_size -
Chris Wilsond2102462011-01-24 17:43:27 +00003973 (entries + i965_cursor_wm_info.guard_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003974
3975 if (cursor_sr > i965_cursor_wm_info.max_wm)
3976 cursor_sr = i965_cursor_wm_info.max_wm;
3977
3978 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3979 "cursor %d\n", srwm, cursor_sr);
3980
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003981 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003982 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05303983 } else {
3984 /* Turn off self refresh if both pipes are enabled */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01003985 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07003986 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3987 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09003988 }
3989
3990 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3991 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003992
3993 /* 965 has limitations... */
Chris Wilson417ae142011-01-19 15:04:42 +00003994 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3995 (8 << 16) | (8 << 8) | (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003996 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003997 /* update cursor SR watermark */
3998 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08003999}
4000
Chris Wilsond2102462011-01-24 17:43:27 +00004001static void i9xx_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004002{
4003 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004004 const struct intel_watermark_params *wm_info;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004005 uint32_t fwater_lo;
4006 uint32_t fwater_hi;
Chris Wilsond2102462011-01-24 17:43:27 +00004007 int cwm, srwm = 1;
4008 int fifo_size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004009 int planea_wm, planeb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00004010 struct drm_crtc *crtc, *enabled = NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004011
Chris Wilson72557b42011-01-31 10:29:55 +00004012 if (IS_I945GM(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004013 wm_info = &i945_wm_info;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004014 else if (!IS_GEN2(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004015 wm_info = &i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004016 else
Chris Wilsond2102462011-01-24 17:43:27 +00004017 wm_info = &i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004018
Chris Wilsond2102462011-01-24 17:43:27 +00004019 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4020 crtc = intel_get_crtc_for_plane(dev, 0);
4021 if (crtc->enabled && crtc->fb) {
4022 planea_wm = intel_calculate_wm(crtc->mode.clock,
4023 wm_info, fifo_size,
4024 crtc->fb->bits_per_pixel / 8,
4025 latency_ns);
4026 enabled = crtc;
4027 } else
4028 planea_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004029
Chris Wilsond2102462011-01-24 17:43:27 +00004030 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4031 crtc = intel_get_crtc_for_plane(dev, 1);
4032 if (crtc->enabled && crtc->fb) {
4033 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4034 wm_info, fifo_size,
4035 crtc->fb->bits_per_pixel / 8,
4036 latency_ns);
4037 if (enabled == NULL)
4038 enabled = crtc;
4039 else
4040 enabled = NULL;
4041 } else
4042 planeb_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004043
Zhao Yakui28c97732009-10-09 11:39:41 +08004044 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004045
4046 /*
4047 * Overlay gets an aggressive default since video jitter is bad.
4048 */
4049 cwm = 2;
4050
Alexander Lam18b21902011-01-03 13:28:56 -05004051 /* Play safe and disable self-refresh before adjusting watermarks. */
4052 if (IS_I945G(dev) || IS_I945GM(dev))
4053 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4054 else if (IS_I915GM(dev))
4055 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4056
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004057 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00004058 if (HAS_FW_BLC(dev) && enabled) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004059 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01004060 static const int sr_latency_ns = 6000;
Chris Wilsond2102462011-01-24 17:43:27 +00004061 int clock = enabled->mode.clock;
4062 int htotal = enabled->mode.htotal;
4063 int hdisplay = enabled->mode.hdisplay;
4064 int pixel_size = enabled->fb->bits_per_pixel / 8;
4065 unsigned long line_time_us;
4066 int entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004067
Chris Wilsond2102462011-01-24 17:43:27 +00004068 line_time_us = (htotal * 1000) / clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004069
4070 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00004071 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4072 pixel_size * hdisplay;
4073 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4074 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4075 srwm = wm_info->fifo_size - entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004076 if (srwm < 0)
4077 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08004078
4079 if (IS_I945G(dev) || IS_I945GM(dev))
Alexander Lam18b21902011-01-03 13:28:56 -05004080 I915_WRITE(FW_BLC_SELF,
4081 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4082 else if (IS_I915GM(dev))
Li Pengee980b82010-01-27 19:01:11 +08004083 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004084 }
4085
Zhao Yakui28c97732009-10-09 11:39:41 +08004086 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004087 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004088
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004089 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4090 fwater_hi = (cwm & 0x1f);
4091
4092 /* Set request length to 8 cachelines per fetch */
4093 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4094 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004095
4096 I915_WRITE(FW_BLC, fwater_lo);
4097 I915_WRITE(FW_BLC2, fwater_hi);
Alexander Lam18b21902011-01-03 13:28:56 -05004098
Chris Wilsond2102462011-01-24 17:43:27 +00004099 if (HAS_FW_BLC(dev)) {
4100 if (enabled) {
4101 if (IS_I945G(dev) || IS_I945GM(dev))
4102 I915_WRITE(FW_BLC_SELF,
4103 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4104 else if (IS_I915GM(dev))
4105 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4106 DRM_DEBUG_KMS("memory self refresh enabled\n");
4107 } else
4108 DRM_DEBUG_KMS("memory self refresh disabled\n");
4109 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08004110}
4111
Chris Wilsond2102462011-01-24 17:43:27 +00004112static void i830_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004113{
4114 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004115 struct drm_crtc *crtc;
4116 uint32_t fwater_lo;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004117 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004118
Chris Wilsond2102462011-01-24 17:43:27 +00004119 crtc = single_enabled_crtc(dev);
4120 if (crtc == NULL)
4121 return;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004122
Chris Wilsond2102462011-01-24 17:43:27 +00004123 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4124 dev_priv->display.get_fifo_size(dev, 0),
4125 crtc->fb->bits_per_pixel / 8,
4126 latency_ns);
4127 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesf3601322009-07-22 12:54:59 -07004128 fwater_lo |= (3<<8) | planea_wm;
4129
Zhao Yakui28c97732009-10-09 11:39:41 +08004130 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004131
4132 I915_WRITE(FW_BLC, fwater_lo);
4133}
4134
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004135#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08004136#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004137
Chris Wilson4ed765f2010-09-11 10:46:47 +01004138static bool ironlake_compute_wm0(struct drm_device *dev,
4139 int pipe,
Yuanhan Liu13982612010-12-15 15:42:31 +08004140 const struct intel_watermark_params *display,
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004141 int display_latency_ns,
Yuanhan Liu13982612010-12-15 15:42:31 +08004142 const struct intel_watermark_params *cursor,
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004143 int cursor_latency_ns,
Chris Wilson4ed765f2010-09-11 10:46:47 +01004144 int *plane_wm,
4145 int *cursor_wm)
4146{
4147 struct drm_crtc *crtc;
Chris Wilsondb66e372011-01-08 09:02:21 +00004148 int htotal, hdisplay, clock, pixel_size;
4149 int line_time_us, line_count;
4150 int entries, tlb_miss;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004151
4152 crtc = intel_get_crtc_for_pipe(dev, pipe);
4153 if (crtc->fb == NULL || !crtc->enabled)
4154 return false;
4155
4156 htotal = crtc->mode.htotal;
4157 hdisplay = crtc->mode.hdisplay;
4158 clock = crtc->mode.clock;
4159 pixel_size = crtc->fb->bits_per_pixel / 8;
4160
4161 /* Use the small buffer method to calculate plane watermark */
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004162 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
Chris Wilsondb66e372011-01-08 09:02:21 +00004163 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4164 if (tlb_miss > 0)
4165 entries += tlb_miss;
Yuanhan Liu13982612010-12-15 15:42:31 +08004166 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4167 *plane_wm = entries + display->guard_size;
4168 if (*plane_wm > (int)display->max_wm)
4169 *plane_wm = display->max_wm;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004170
4171 /* Use the large buffer method to calculate cursor watermark */
4172 line_time_us = ((htotal * 1000) / clock);
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004173 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004174 entries = line_count * 64 * pixel_size;
Chris Wilsondb66e372011-01-08 09:02:21 +00004175 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4176 if (tlb_miss > 0)
4177 entries += tlb_miss;
Yuanhan Liu13982612010-12-15 15:42:31 +08004178 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4179 *cursor_wm = entries + cursor->guard_size;
4180 if (*cursor_wm > (int)cursor->max_wm)
4181 *cursor_wm = (int)cursor->max_wm;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004182
4183 return true;
4184}
4185
Jesse Barnesb79d4992010-12-21 13:10:23 -08004186/*
4187 * Check the wm result.
4188 *
4189 * If any calculated watermark values is larger than the maximum value that
4190 * can be programmed into the associated watermark register, that watermark
4191 * must be disabled.
4192 */
4193static bool ironlake_check_srwm(struct drm_device *dev, int level,
4194 int fbc_wm, int display_wm, int cursor_wm,
4195 const struct intel_watermark_params *display,
4196 const struct intel_watermark_params *cursor)
4197{
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199
4200 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4201 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4202
4203 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4204 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4205 fbc_wm, SNB_FBC_MAX_SRWM, level);
4206
4207 /* fbc has it's own way to disable FBC WM */
4208 I915_WRITE(DISP_ARB_CTL,
4209 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4210 return false;
4211 }
4212
4213 if (display_wm > display->max_wm) {
4214 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4215 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4216 return false;
4217 }
4218
4219 if (cursor_wm > cursor->max_wm) {
4220 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4221 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4222 return false;
4223 }
4224
4225 if (!(fbc_wm || display_wm || cursor_wm)) {
4226 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4227 return false;
4228 }
4229
4230 return true;
4231}
4232
4233/*
4234 * Compute watermark values of WM[1-3],
4235 */
Chris Wilsond2102462011-01-24 17:43:27 +00004236static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4237 int latency_ns,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004238 const struct intel_watermark_params *display,
4239 const struct intel_watermark_params *cursor,
4240 int *fbc_wm, int *display_wm, int *cursor_wm)
4241{
Chris Wilsond2102462011-01-24 17:43:27 +00004242 struct drm_crtc *crtc;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004243 unsigned long line_time_us;
Chris Wilsond2102462011-01-24 17:43:27 +00004244 int hdisplay, htotal, pixel_size, clock;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004245 int line_count, line_size;
4246 int small, large;
4247 int entries;
4248
4249 if (!latency_ns) {
4250 *fbc_wm = *display_wm = *cursor_wm = 0;
4251 return false;
4252 }
4253
Chris Wilsond2102462011-01-24 17:43:27 +00004254 crtc = intel_get_crtc_for_plane(dev, plane);
4255 hdisplay = crtc->mode.hdisplay;
4256 htotal = crtc->mode.htotal;
4257 clock = crtc->mode.clock;
4258 pixel_size = crtc->fb->bits_per_pixel / 8;
4259
Jesse Barnesb79d4992010-12-21 13:10:23 -08004260 line_time_us = (htotal * 1000) / clock;
4261 line_count = (latency_ns / line_time_us + 1000) / 1000;
4262 line_size = hdisplay * pixel_size;
4263
4264 /* Use the minimum of the small and large buffer method for primary */
4265 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4266 large = line_count * line_size;
4267
4268 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4269 *display_wm = entries + display->guard_size;
4270
4271 /*
4272 * Spec says:
4273 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4274 */
4275 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4276
4277 /* calculate the self-refresh watermark for display cursor */
4278 entries = line_count * pixel_size * 64;
4279 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4280 *cursor_wm = entries + cursor->guard_size;
4281
4282 return ironlake_check_srwm(dev, level,
4283 *fbc_wm, *display_wm, *cursor_wm,
4284 display, cursor);
4285}
4286
Chris Wilsond2102462011-01-24 17:43:27 +00004287static void ironlake_update_wm(struct drm_device *dev)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004288{
4289 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004290 int fbc_wm, plane_wm, cursor_wm;
4291 unsigned int enabled;
Zhao Yakuic936f442010-06-12 14:32:26 +08004292
Chris Wilson4ed765f2010-09-11 10:46:47 +01004293 enabled = 0;
Yuanhan Liu13982612010-12-15 15:42:31 +08004294 if (ironlake_compute_wm0(dev, 0,
4295 &ironlake_display_wm_info,
4296 ILK_LP0_PLANE_LATENCY,
4297 &ironlake_cursor_wm_info,
4298 ILK_LP0_CURSOR_LATENCY,
4299 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004300 I915_WRITE(WM0_PIPEA_ILK,
4301 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4302 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4303 " plane %d, " "cursor: %d\n",
4304 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004305 enabled |= 1;
Zhao Yakuic936f442010-06-12 14:32:26 +08004306 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004307
Yuanhan Liu13982612010-12-15 15:42:31 +08004308 if (ironlake_compute_wm0(dev, 1,
4309 &ironlake_display_wm_info,
4310 ILK_LP0_PLANE_LATENCY,
4311 &ironlake_cursor_wm_info,
4312 ILK_LP0_CURSOR_LATENCY,
4313 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004314 I915_WRITE(WM0_PIPEB_ILK,
4315 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4316 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4317 " plane %d, cursor: %d\n",
4318 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004319 enabled |= 2;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004320 }
4321
4322 /*
4323 * Calculate and update the self-refresh watermark only when one
4324 * display plane is used.
4325 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004326 I915_WRITE(WM3_LP_ILK, 0);
4327 I915_WRITE(WM2_LP_ILK, 0);
4328 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004329
Chris Wilsond2102462011-01-24 17:43:27 +00004330 if (!single_plane_enabled(enabled))
Jesse Barnesb79d4992010-12-21 13:10:23 -08004331 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004332 enabled = ffs(enabled) - 1;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004333
Jesse Barnesb79d4992010-12-21 13:10:23 -08004334 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004335 if (!ironlake_compute_srwm(dev, 1, enabled,
4336 ILK_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004337 &ironlake_display_srwm_info,
4338 &ironlake_cursor_srwm_info,
4339 &fbc_wm, &plane_wm, &cursor_wm))
4340 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004341
Jesse Barnesb79d4992010-12-21 13:10:23 -08004342 I915_WRITE(WM1_LP_ILK,
4343 WM1_LP_SR_EN |
4344 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4345 (fbc_wm << WM1_LP_FBC_SHIFT) |
4346 (plane_wm << WM1_LP_SR_SHIFT) |
4347 cursor_wm);
Chris Wilson4ed765f2010-09-11 10:46:47 +01004348
Jesse Barnesb79d4992010-12-21 13:10:23 -08004349 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004350 if (!ironlake_compute_srwm(dev, 2, enabled,
4351 ILK_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004352 &ironlake_display_srwm_info,
4353 &ironlake_cursor_srwm_info,
4354 &fbc_wm, &plane_wm, &cursor_wm))
4355 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004356
Jesse Barnesb79d4992010-12-21 13:10:23 -08004357 I915_WRITE(WM2_LP_ILK,
4358 WM2_LP_EN |
4359 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4360 (fbc_wm << WM1_LP_FBC_SHIFT) |
4361 (plane_wm << WM1_LP_SR_SHIFT) |
4362 cursor_wm);
Yuanhan Liu13982612010-12-15 15:42:31 +08004363
4364 /*
Jesse Barnesb79d4992010-12-21 13:10:23 -08004365 * WM3 is unsupported on ILK, probably because we don't have latency
4366 * data for that power state
Yuanhan Liu13982612010-12-15 15:42:31 +08004367 */
Yuanhan Liu13982612010-12-15 15:42:31 +08004368}
4369
Chris Wilsond2102462011-01-24 17:43:27 +00004370static void sandybridge_update_wm(struct drm_device *dev)
Yuanhan Liu13982612010-12-15 15:42:31 +08004371{
4372 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004373 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Chris Wilsond2102462011-01-24 17:43:27 +00004374 int fbc_wm, plane_wm, cursor_wm;
4375 unsigned int enabled;
Yuanhan Liu13982612010-12-15 15:42:31 +08004376
4377 enabled = 0;
4378 if (ironlake_compute_wm0(dev, 0,
4379 &sandybridge_display_wm_info, latency,
4380 &sandybridge_cursor_wm_info, latency,
4381 &plane_wm, &cursor_wm)) {
4382 I915_WRITE(WM0_PIPEA_ILK,
4383 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4384 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4385 " plane %d, " "cursor: %d\n",
4386 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004387 enabled |= 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004388 }
4389
4390 if (ironlake_compute_wm0(dev, 1,
4391 &sandybridge_display_wm_info, latency,
4392 &sandybridge_cursor_wm_info, latency,
4393 &plane_wm, &cursor_wm)) {
4394 I915_WRITE(WM0_PIPEB_ILK,
4395 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4396 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4397 " plane %d, cursor: %d\n",
4398 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004399 enabled |= 2;
Yuanhan Liu13982612010-12-15 15:42:31 +08004400 }
4401
4402 /*
4403 * Calculate and update the self-refresh watermark only when one
4404 * display plane is used.
4405 *
4406 * SNB support 3 levels of watermark.
4407 *
4408 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4409 * and disabled in the descending order
4410 *
4411 */
4412 I915_WRITE(WM3_LP_ILK, 0);
4413 I915_WRITE(WM2_LP_ILK, 0);
4414 I915_WRITE(WM1_LP_ILK, 0);
4415
Chris Wilsond2102462011-01-24 17:43:27 +00004416 if (!single_plane_enabled(enabled))
Yuanhan Liu13982612010-12-15 15:42:31 +08004417 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004418 enabled = ffs(enabled) - 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004419
4420 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004421 if (!ironlake_compute_srwm(dev, 1, enabled,
4422 SNB_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004423 &sandybridge_display_srwm_info,
4424 &sandybridge_cursor_srwm_info,
4425 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004426 return;
4427
4428 I915_WRITE(WM1_LP_ILK,
4429 WM1_LP_SR_EN |
4430 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4431 (fbc_wm << WM1_LP_FBC_SHIFT) |
4432 (plane_wm << WM1_LP_SR_SHIFT) |
4433 cursor_wm);
4434
4435 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004436 if (!ironlake_compute_srwm(dev, 2, enabled,
4437 SNB_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004438 &sandybridge_display_srwm_info,
4439 &sandybridge_cursor_srwm_info,
4440 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004441 return;
4442
4443 I915_WRITE(WM2_LP_ILK,
4444 WM2_LP_EN |
4445 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4446 (fbc_wm << WM1_LP_FBC_SHIFT) |
4447 (plane_wm << WM1_LP_SR_SHIFT) |
4448 cursor_wm);
4449
4450 /* WM3 */
Chris Wilsond2102462011-01-24 17:43:27 +00004451 if (!ironlake_compute_srwm(dev, 3, enabled,
4452 SNB_READ_WM3_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004453 &sandybridge_display_srwm_info,
4454 &sandybridge_cursor_srwm_info,
4455 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004456 return;
4457
4458 I915_WRITE(WM3_LP_ILK,
4459 WM3_LP_EN |
4460 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4461 (fbc_wm << WM1_LP_FBC_SHIFT) |
4462 (plane_wm << WM1_LP_SR_SHIFT) |
4463 cursor_wm);
4464}
4465
Shaohua Li7662c8b2009-06-26 11:23:55 +08004466/**
4467 * intel_update_watermarks - update FIFO watermark values based on current modes
4468 *
4469 * Calculate watermark values for the various WM regs based on current mode
4470 * and plane configuration.
4471 *
4472 * There are several cases to deal with here:
4473 * - normal (i.e. non-self-refresh)
4474 * - self-refresh (SR) mode
4475 * - lines are large relative to FIFO size (buffer can hold up to 2)
4476 * - lines are small relative to FIFO size (buffer can hold more than 2
4477 * lines), so need to account for TLB latency
4478 *
4479 * The normal calculation is:
4480 * watermark = dotclock * bytes per pixel * latency
4481 * where latency is platform & configuration dependent (we assume pessimal
4482 * values here).
4483 *
4484 * The SR calculation is:
4485 * watermark = (trunc(latency/line time)+1) * surface width *
4486 * bytes per pixel
4487 * where
4488 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08004489 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08004490 * and latency is assumed to be high, as above.
4491 *
4492 * The final value programmed to the register should always be rounded up,
4493 * and include an extra 2 entries to account for clock crossings.
4494 *
4495 * We don't use the sprite, so we can ignore that. And on Crestline we have
4496 * to set the non-SR watermarks to 8.
Chris Wilson5eddb702010-09-11 13:48:45 +01004497 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004498static void intel_update_watermarks(struct drm_device *dev)
4499{
Jesse Barnese70236a2009-09-21 10:42:27 -07004500 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004501
Chris Wilsond2102462011-01-24 17:43:27 +00004502 if (dev_priv->display.update_wm)
4503 dev_priv->display.update_wm(dev);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004504}
4505
Chris Wilsona7615032011-01-12 17:04:08 +00004506static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4507{
4508 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4509}
4510
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004511static int intel_crtc_mode_set(struct drm_crtc *crtc,
4512 struct drm_display_mode *mode,
4513 struct drm_display_mode *adjusted_mode,
4514 int x, int y,
4515 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004516{
4517 struct drm_device *dev = crtc->dev;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4520 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004521 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01004522 u32 fp_reg, dpll_reg;
Eric Anholtc751ce42010-03-25 11:48:48 -07004523 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004524 intel_clock_t clock, reduced_clock;
Chris Wilson5eddb702010-09-11 13:48:45 +01004525 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Jesse Barnes652c3932009-08-17 13:31:43 -07004526 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004527 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson8e647a22010-08-22 10:54:23 +01004528 struct intel_encoder *has_edp_encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004529 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson5eddb702010-09-11 13:48:45 +01004530 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004531 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004532 int ret;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004533 struct fdi_m_n m_n = {0};
Chris Wilson5eddb702010-09-11 13:48:45 +01004534 u32 reg, temp;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004535 u32 lvds_sync = 0;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004536 int target_clock;
Jesse Barnes79e53942008-11-07 14:24:08 -08004537
4538 drm_vblank_pre_modeset(dev, pipe);
4539
Chris Wilson5eddb702010-09-11 13:48:45 +01004540 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4541 if (encoder->base.crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08004542 continue;
4543
Chris Wilson5eddb702010-09-11 13:48:45 +01004544 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004545 case INTEL_OUTPUT_LVDS:
4546 is_lvds = true;
4547 break;
4548 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004549 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004550 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004551 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004552 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004553 break;
4554 case INTEL_OUTPUT_DVO:
4555 is_dvo = true;
4556 break;
4557 case INTEL_OUTPUT_TVOUT:
4558 is_tv = true;
4559 break;
4560 case INTEL_OUTPUT_ANALOG:
4561 is_crt = true;
4562 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004563 case INTEL_OUTPUT_DISPLAYPORT:
4564 is_dp = true;
4565 break;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004566 case INTEL_OUTPUT_EDP:
Chris Wilson5eddb702010-09-11 13:48:45 +01004567 has_edp_encoder = encoder;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004568 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004569 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004570
Eric Anholtc751ce42010-03-25 11:48:48 -07004571 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004572 }
4573
Chris Wilsona7615032011-01-12 17:04:08 +00004574 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004575 refclk = dev_priv->lvds_ssc_freq * 1000;
Zhao Yakui28c97732009-10-09 11:39:41 +08004576 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004577 refclk / 1000);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004578 } else if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004579 refclk = 96000;
Jesse Barnes1cb1b752010-10-07 16:01:17 -07004580 if (HAS_PCH_SPLIT(dev) &&
4581 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004582 refclk = 120000; /* 120Mhz refclk */
Jesse Barnes79e53942008-11-07 14:24:08 -08004583 } else {
4584 refclk = 48000;
4585 }
4586
Ma Lingd4906092009-03-18 20:13:27 +08004587 /*
4588 * Returns a set of divisors for the desired target clock with the given
4589 * refclk, or FALSE. The returned values represent the clock equation:
4590 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4591 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004592 limit = intel_limit(crtc, refclk);
Ma Lingd4906092009-03-18 20:13:27 +08004593 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004594 if (!ok) {
4595 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Chris Wilson1f803ee2009-06-06 09:45:59 +01004596 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004597 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004598 }
4599
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004600 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01004601 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004602
Zhao Yakuiddc90032010-01-06 22:05:56 +08004603 if (is_lvds && dev_priv->lvds_downclock_avail) {
4604 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01004605 dev_priv->lvds_downclock,
4606 refclk,
4607 &reduced_clock);
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004608 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4609 /*
4610 * If the different P is found, it means that we can't
4611 * switch the display clock by using the FP0/FP1.
4612 * In such case we will disable the LVDS downclock
4613 * feature.
4614 */
4615 DRM_DEBUG_KMS("Different P is found for "
Chris Wilson5eddb702010-09-11 13:48:45 +01004616 "LVDS clock/downclock\n");
Zhao Yakui18f9ed12009-11-20 03:24:16 +00004617 has_reduced_clock = 0;
4618 }
Jesse Barnes652c3932009-08-17 13:31:43 -07004619 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004620 /* SDVO TV has fixed PLL values depend on its clock range,
4621 this mirrors vbios setting. */
4622 if (is_sdvo && is_tv) {
4623 if (adjusted_mode->clock >= 100000
Chris Wilson5eddb702010-09-11 13:48:45 +01004624 && adjusted_mode->clock < 140500) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004625 clock.p1 = 2;
4626 clock.p2 = 10;
4627 clock.n = 3;
4628 clock.m1 = 16;
4629 clock.m2 = 8;
4630 } else if (adjusted_mode->clock >= 140500
Chris Wilson5eddb702010-09-11 13:48:45 +01004631 && adjusted_mode->clock <= 200000) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004632 clock.p1 = 1;
4633 clock.p2 = 10;
4634 clock.n = 6;
4635 clock.m1 = 12;
4636 clock.m2 = 8;
4637 }
4638 }
4639
Zhenyu Wang2c072452009-06-05 15:38:42 +08004640 /* FDI link */
Eric Anholtbad720f2009-10-22 16:11:14 -07004641 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson49078f72010-12-04 07:45:57 +00004642 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
Adam Jackson77ffb592010-04-12 11:38:44 -04004643 int lane = 0, link_bw, bpp;
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004644 /* CPU eDP doesn't require FDI link, so just set DP M/N
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004645 according to current link config */
Jesse Barnes858bc212011-01-04 10:46:49 -08004646 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004647 target_clock = mode->clock;
Chris Wilson8e647a22010-08-22 10:54:23 +01004648 intel_edp_link_config(has_edp_encoder,
4649 &lane, &link_bw);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004650 } else {
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004651 /* [e]DP over FDI requires target mode clock
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004652 instead of link clock */
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004653 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004654 target_clock = mode->clock;
4655 else
4656 target_clock = adjusted_mode->clock;
Chris Wilson021357a2010-09-07 20:54:59 +01004657
4658 /* FDI is a binary signal running at ~2.7GHz, encoding
4659 * each output octet as 10 bits. The actual frequency
4660 * is stored as a divider into a 100MHz clock, and the
4661 * mode pixel clock is stored in units of 1KHz.
4662 * Hence the bw of each lane in terms of the mode signal
4663 * is:
4664 */
4665 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004666 }
Zhenyu Wang58a27472009-09-25 08:01:28 +00004667
4668 /* determine panel color depth */
Chris Wilson5eddb702010-09-11 13:48:45 +01004669 temp = I915_READ(PIPECONF(pipe));
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004670 temp &= ~PIPE_BPC_MASK;
4671 if (is_lvds) {
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004672 /* the BPC will be 6 if it is 18-bit LVDS panel */
Chris Wilson5eddb702010-09-11 13:48:45 +01004673 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004674 temp |= PIPE_8BPC;
4675 else
4676 temp |= PIPE_6BPC;
Jesse Barnes1d850362010-10-07 16:01:10 -07004677 } else if (has_edp_encoder) {
Chris Wilson5ceb0f92010-09-24 10:24:28 +01004678 switch (dev_priv->edp.bpp/3) {
Zhenyu Wang885a5fb2010-01-12 05:38:31 +08004679 case 8:
4680 temp |= PIPE_8BPC;
4681 break;
4682 case 10:
4683 temp |= PIPE_10BPC;
4684 break;
4685 case 6:
4686 temp |= PIPE_6BPC;
4687 break;
4688 case 12:
4689 temp |= PIPE_12BPC;
4690 break;
4691 }
Zhao Yakuie5a95eb2010-01-04 16:29:32 +08004692 } else
4693 temp |= PIPE_8BPC;
Chris Wilson5eddb702010-09-11 13:48:45 +01004694 I915_WRITE(PIPECONF(pipe), temp);
Zhenyu Wang58a27472009-09-25 08:01:28 +00004695
4696 switch (temp & PIPE_BPC_MASK) {
4697 case PIPE_8BPC:
4698 bpp = 24;
4699 break;
4700 case PIPE_10BPC:
4701 bpp = 30;
4702 break;
4703 case PIPE_6BPC:
4704 bpp = 18;
4705 break;
4706 case PIPE_12BPC:
4707 bpp = 36;
4708 break;
4709 default:
4710 DRM_ERROR("unknown pipe bpc value\n");
4711 bpp = 24;
4712 }
4713
Adam Jackson77ffb592010-04-12 11:38:44 -04004714 if (!lane) {
4715 /*
4716 * Account for spread spectrum to avoid
4717 * oversubscribing the link. Max center spread
4718 * is 2.5%; use 5% for safety's sake.
4719 */
4720 u32 bps = target_clock * bpp * 21 / 20;
4721 lane = bps / (link_bw * 8) + 1;
4722 }
4723
4724 intel_crtc->fdi_lanes = lane;
4725
Chris Wilson49078f72010-12-04 07:45:57 +00004726 if (pixel_multiplier > 1)
4727 link_bw *= pixel_multiplier;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004728 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004729 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004730
Zhenyu Wangc038e512009-10-19 15:43:48 +08004731 /* Ironlake: try to setup display ref clock before DPLL
4732 * enabling. This is only under driver's control after
4733 * PCH B stepping, previous chipset stepping should be
4734 * ignoring this setting.
4735 */
Chris Wilsonfc9a2222011-02-17 17:14:34 +00004736 if (HAS_PCH_SPLIT(dev)) {
4737 temp = I915_READ(PCH_DREF_CONTROL);
4738 /* Always enable nonspread source */
4739 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4740 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4741 temp &= ~DREF_SSC_SOURCE_MASK;
4742 temp |= DREF_SSC_SOURCE_ENABLE;
4743 I915_WRITE(PCH_DREF_CONTROL, temp);
4744
4745 POSTING_READ(PCH_DREF_CONTROL);
4746 udelay(200);
4747
4748 if (has_edp_encoder) {
4749 if (intel_panel_use_ssc(dev_priv)) {
4750 temp |= DREF_SSC1_ENABLE;
4751 I915_WRITE(PCH_DREF_CONTROL, temp);
4752
4753 POSTING_READ(PCH_DREF_CONTROL);
4754 udelay(200);
4755 }
4756 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4757
4758 /* Enable CPU source on CPU attached eDP */
4759 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4760 if (intel_panel_use_ssc(dev_priv))
4761 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4762 else
4763 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4764 } else {
4765 /* Enable SSC on PCH eDP if needed */
4766 if (intel_panel_use_ssc(dev_priv)) {
4767 DRM_ERROR("enabling SSC on PCH\n");
4768 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4769 }
4770 }
4771 I915_WRITE(PCH_DREF_CONTROL, temp);
4772 POSTING_READ(PCH_DREF_CONTROL);
4773 udelay(200);
4774 }
4775 }
Zhenyu Wangc038e512009-10-19 15:43:48 +08004776
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004777 if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +08004778 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07004779 if (has_reduced_clock)
4780 fp2 = (1 << reduced_clock.n) << 16 |
4781 reduced_clock.m1 << 8 | reduced_clock.m2;
4782 } else {
Shaohua Li21778322009-02-23 15:19:16 +08004783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
Jesse Barnes652c3932009-08-17 13:31:43 -07004784 if (has_reduced_clock)
4785 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4786 reduced_clock.m2;
4787 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004788
Chris Wilsonc1858122010-12-03 21:35:48 +00004789 /* Enable autotuning of the PLL clock (if permissible) */
4790 if (HAS_PCH_SPLIT(dev)) {
4791 int factor = 21;
4792
4793 if (is_lvds) {
Chris Wilsona7615032011-01-12 17:04:08 +00004794 if ((intel_panel_use_ssc(dev_priv) &&
Chris Wilsonc1858122010-12-03 21:35:48 +00004795 dev_priv->lvds_ssc_freq == 100) ||
4796 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4797 factor = 25;
4798 } else if (is_sdvo && is_tv)
4799 factor = 20;
4800
4801 if (clock.m1 < factor * clock.n)
4802 fp |= FP_CB_TUNE;
4803 }
4804
Chris Wilson5eddb702010-09-11 13:48:45 +01004805 dpll = 0;
Eric Anholtbad720f2009-10-22 16:11:14 -07004806 if (!HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004807 dpll = DPLL_VGA_MODE_DIS;
4808
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004809 if (!IS_GEN2(dev)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004810 if (is_lvds)
4811 dpll |= DPLLB_MODE_LVDS;
4812 else
4813 dpll |= DPLLB_MODE_DAC_SERIAL;
4814 if (is_sdvo) {
Chris Wilson6c9547f2010-08-25 10:05:17 +01004815 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4816 if (pixel_multiplier > 1) {
4817 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4818 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4819 else if (HAS_PCH_SPLIT(dev))
4820 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4821 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004822 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004823 }
Jesse Barnes83240122010-10-07 16:01:18 -07004824 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004825 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004826
4827 /* compute bitmask from p1 value */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004828 if (IS_PINEVIEW(dev))
4829 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004830 else {
Shaohua Li21778322009-02-23 15:19:16 +08004831 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004832 /* also FPA1 */
Eric Anholtbad720f2009-10-22 16:11:14 -07004833 if (HAS_PCH_SPLIT(dev))
Zhenyu Wang2c072452009-06-05 15:38:42 +08004834 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Jesse Barnes652c3932009-08-17 13:31:43 -07004835 if (IS_G4X(dev) && has_reduced_clock)
4836 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004837 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004838 switch (clock.p2) {
4839 case 5:
4840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4841 break;
4842 case 7:
4843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4844 break;
4845 case 10:
4846 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4847 break;
4848 case 14:
4849 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4850 break;
4851 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004852 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08004853 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4854 } else {
4855 if (is_lvds) {
4856 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4857 } else {
4858 if (clock.p1 == 2)
4859 dpll |= PLL_P1_DIVIDE_BY_TWO;
4860 else
4861 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4862 if (clock.p2 == 4)
4863 dpll |= PLL_P2_DIVIDE_BY_4;
4864 }
4865 }
4866
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004867 if (is_sdvo && is_tv)
4868 dpll |= PLL_REF_INPUT_TVCLKINBC;
4869 else if (is_tv)
Jesse Barnes79e53942008-11-07 14:24:08 -08004870 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004871 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08004872 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00004873 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004874 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08004875 else
4876 dpll |= PLL_REF_INPUT_DREFCLK;
4877
4878 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01004879 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004880
4881 /* Set up the display plane register */
4882 dspcntr = DISPPLANE_GAMMA_ENABLE;
4883
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004884 /* Ironlake's plane is forced to pipe, bit 24 is to
Zhenyu Wang2c072452009-06-05 15:38:42 +08004885 enable color space conversion */
Eric Anholtbad720f2009-10-22 16:11:14 -07004886 if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08004887 if (pipe == 0)
Jesse Barnes80824002009-09-10 15:28:06 -07004888 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004889 else
4890 dspcntr |= DISPPLANE_SEL_PIPE_B;
4891 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004892
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004893 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004894 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4895 * core speed.
4896 *
4897 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4898 * pipe == 0 check?
4899 */
Jesse Barnese70236a2009-09-21 10:42:27 -07004900 if (mode->clock >
4901 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
Chris Wilson5eddb702010-09-11 13:48:45 +01004902 pipeconf |= PIPECONF_DOUBLE_WIDE;
Jesse Barnes79e53942008-11-07 14:24:08 -08004903 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004904 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
Jesse Barnes79e53942008-11-07 14:24:08 -08004905 }
4906
Jesse Barnesb24e7172011-01-04 15:09:30 -08004907 if (!HAS_PCH_SPLIT(dev))
Jesse Barnes65993d62011-01-04 15:09:29 -08004908 dpll |= DPLL_VCO_ENABLE;
Linus Torvalds8d86dc62010-06-08 20:16:28 -07004909
Zhao Yakui28c97732009-10-09 11:39:41 +08004910 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
Jesse Barnes79e53942008-11-07 14:24:08 -08004911 drm_mode_debug_printmodeline(mode);
4912
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004913 /* assign to Ironlake registers */
Eric Anholtbad720f2009-10-22 16:11:14 -07004914 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004915 fp_reg = PCH_FP0(pipe);
4916 dpll_reg = PCH_DPLL(pipe);
4917 } else {
4918 fp_reg = FP0(pipe);
4919 dpll_reg = DPLL(pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004920 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004921
Jesse Barnes5c5313c2010-10-07 16:01:11 -07004922 /* PCH eDP needs FDI, but CPU eDP does not */
4923 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004924 I915_WRITE(fp_reg, fp);
4925 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01004926
4927 POSTING_READ(dpll_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -08004928 udelay(150);
4929 }
4930
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004931 /* enable transcoder DPLL */
4932 if (HAS_PCH_CPT(dev)) {
4933 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004934 switch (pipe) {
4935 case 0:
Chris Wilson5eddb702010-09-11 13:48:45 +01004936 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004937 break;
4938 case 1:
Chris Wilson5eddb702010-09-11 13:48:45 +01004939 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004940 break;
4941 case 2:
4942 /* FIXME: manage transcoder PLLs? */
4943 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4944 break;
4945 default:
4946 BUG();
4947 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004948 I915_WRITE(PCH_DPLL_SEL, temp);
Chris Wilson5eddb702010-09-11 13:48:45 +01004949
4950 POSTING_READ(PCH_DPLL_SEL);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004951 udelay(150);
4952 }
4953
Jesse Barnes79e53942008-11-07 14:24:08 -08004954 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4955 * This is an exception to the general rule that mode_set doesn't turn
4956 * things on.
4957 */
4958 if (is_lvds) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004959 reg = LVDS;
Eric Anholtbad720f2009-10-22 16:11:14 -07004960 if (HAS_PCH_SPLIT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004961 reg = PCH_LVDS;
Zhenyu Wang541998a2009-06-05 15:38:44 +08004962
Chris Wilson5eddb702010-09-11 13:48:45 +01004963 temp = I915_READ(reg);
4964 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004965 if (pipe == 1) {
4966 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004967 temp |= PORT_TRANS_B_SEL_CPT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004968 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004969 temp |= LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004970 } else {
4971 if (HAS_PCH_CPT(dev))
Chris Wilson5eddb702010-09-11 13:48:45 +01004972 temp &= ~PORT_TRANS_SEL_MASK;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004973 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004974 temp &= ~LVDS_PIPEB_SELECT;
Zhenyu Wangb3b095b2010-04-07 16:15:56 +08004975 }
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004976 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01004977 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08004978 /* Set the B0-B3 data pairs corresponding to whether we're going to
4979 * set the DPLLs for dual-channel mode or not.
4980 */
4981 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01004982 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08004983 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004984 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08004985
4986 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4987 * appropriately here, but we need to look more thoroughly into how
4988 * panels behave in the two modes.
4989 */
Jesse Barnes434ed092010-09-07 14:48:06 -07004990 /* set the dithering flag on non-PCH LVDS as needed */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004991 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
Jesse Barnes434ed092010-09-07 14:48:06 -07004992 if (dev_priv->lvds_dither)
Chris Wilson5eddb702010-09-11 13:48:45 +01004993 temp |= LVDS_ENABLE_DITHER;
Jesse Barnes434ed092010-09-07 14:48:06 -07004994 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004995 temp &= ~LVDS_ENABLE_DITHER;
Zhao Yakui898822c2010-01-04 16:29:30 +08004996 }
Bryan Freedaa9b5002011-01-12 13:43:19 -08004997 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4998 lvds_sync |= LVDS_HSYNC_POLARITY;
4999 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5000 lvds_sync |= LVDS_VSYNC_POLARITY;
5001 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5002 != lvds_sync) {
5003 char flags[2] = "-+";
5004 DRM_INFO("Changing LVDS panel from "
5005 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5006 flags[!(temp & LVDS_HSYNC_POLARITY)],
5007 flags[!(temp & LVDS_VSYNC_POLARITY)],
5008 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5009 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5010 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5011 temp |= lvds_sync;
5012 }
Chris Wilson5eddb702010-09-11 13:48:45 +01005013 I915_WRITE(reg, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005014 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005015
5016 /* set the dithering flag and clear for anything other than a panel. */
5017 if (HAS_PCH_SPLIT(dev)) {
5018 pipeconf &= ~PIPECONF_DITHER_EN;
5019 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5020 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5021 pipeconf |= PIPECONF_DITHER_EN;
5022 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5023 }
5024 }
5025
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005026 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005027 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005028 } else if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005029 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005030 I915_WRITE(TRANSDATA_M1(pipe), 0);
5031 I915_WRITE(TRANSDATA_N1(pipe), 0);
5032 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5033 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005034 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005035
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005036 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005037 I915_WRITE(dpll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005038
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005039 /* Wait for the clocks to stabilize. */
Chris Wilson5eddb702010-09-11 13:48:45 +01005040 POSTING_READ(dpll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005041 udelay(150);
5042
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005043 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005044 temp = 0;
Zhao Yakuibb66c512009-09-10 15:45:49 +08005045 if (is_sdvo) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005046 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5047 if (temp > 1)
5048 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
Chris Wilson6c9547f2010-08-25 10:05:17 +01005049 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005050 temp = 0;
5051 }
5052 I915_WRITE(DPLL_MD(pipe), temp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005053 } else {
Chris Wilsona589b9f2010-12-03 21:13:16 +00005054 /* The pixel multiplier can only be updated once the
5055 * DPLL is enabled and the clocks are stable.
5056 *
5057 * So write it again.
5058 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005059 I915_WRITE(dpll_reg, dpll);
5060 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005061 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005062
Chris Wilson5eddb702010-09-11 13:48:45 +01005063 intel_crtc->lowfreq_avail = false;
Jesse Barnes652c3932009-08-17 13:31:43 -07005064 if (is_lvds && has_reduced_clock && i915_powersave) {
5065 I915_WRITE(fp_reg + 4, fp2);
5066 intel_crtc->lowfreq_avail = true;
5067 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005068 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005069 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5070 }
5071 } else {
5072 I915_WRITE(fp_reg + 4, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005073 if (HAS_PIPE_CXSR(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005074 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005075 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5076 }
5077 }
5078
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005079 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5080 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5081 /* the chip adds 2 halflines automatically */
5082 adjusted_mode->crtc_vdisplay -= 1;
5083 adjusted_mode->crtc_vtotal -= 1;
5084 adjusted_mode->crtc_vblank_start -= 1;
5085 adjusted_mode->crtc_vblank_end -= 1;
5086 adjusted_mode->crtc_vsync_end -= 1;
5087 adjusted_mode->crtc_vsync_start -= 1;
5088 } else
5089 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5090
Chris Wilson5eddb702010-09-11 13:48:45 +01005091 I915_WRITE(HTOTAL(pipe),
5092 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005093 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005094 I915_WRITE(HBLANK(pipe),
5095 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005096 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005097 I915_WRITE(HSYNC(pipe),
5098 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005099 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005100
5101 I915_WRITE(VTOTAL(pipe),
5102 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005103 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005104 I915_WRITE(VBLANK(pipe),
5105 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005106 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005107 I915_WRITE(VSYNC(pipe),
5108 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005109 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005110
5111 /* pipesrc and dspsize control the size that is scaled from,
5112 * which should always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08005113 */
Eric Anholtbad720f2009-10-22 16:11:14 -07005114 if (!HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005115 I915_WRITE(DSPSIZE(plane),
5116 ((mode->vdisplay - 1) << 16) |
5117 (mode->hdisplay - 1));
5118 I915_WRITE(DSPPOS(plane), 0);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005119 }
Chris Wilson5eddb702010-09-11 13:48:45 +01005120 I915_WRITE(PIPESRC(pipe),
5121 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08005122
Eric Anholtbad720f2009-10-22 16:11:14 -07005123 if (HAS_PCH_SPLIT(dev)) {
Chris Wilson5eddb702010-09-11 13:48:45 +01005124 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5125 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5126 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5127 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005128
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005129 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005130 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005131 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08005132 }
5133
Chris Wilson5eddb702010-09-11 13:48:45 +01005134 I915_WRITE(PIPECONF(pipe), pipeconf);
5135 POSTING_READ(PIPECONF(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08005136 if (!HAS_PCH_SPLIT(dev))
Jesse Barnes040484a2011-01-03 12:14:26 -08005137 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnes79e53942008-11-07 14:24:08 -08005138
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005139 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005140
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01005141 if (IS_GEN5(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08005142 /* enable address swizzle for tiling buffer */
5143 temp = I915_READ(DISP_ARB_CTL);
5144 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5145 }
5146
Chris Wilson5eddb702010-09-11 13:48:45 +01005147 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005148 POSTING_READ(DSPCNTR(plane));
5149 if (!HAS_PCH_SPLIT(dev))
5150 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005151
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005152 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005153
5154 intel_update_watermarks(dev);
5155
Jesse Barnes79e53942008-11-07 14:24:08 -08005156 drm_vblank_post_modeset(dev, pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005157
Chris Wilson1f803ee2009-06-06 09:45:59 +01005158 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005159}
5160
5161/** Loads the palette/gamma unit for the CRTC with the prepared values */
5162void intel_crtc_load_lut(struct drm_crtc *crtc)
5163{
5164 struct drm_device *dev = crtc->dev;
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005167 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005168 int i;
5169
5170 /* The clocks have to be on to load the palette. */
5171 if (!crtc->enabled)
5172 return;
5173
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005174 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005175 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005176 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005177
Jesse Barnes79e53942008-11-07 14:24:08 -08005178 for (i = 0; i < 256; i++) {
5179 I915_WRITE(palreg + 4 * i,
5180 (intel_crtc->lut_r[i] << 16) |
5181 (intel_crtc->lut_g[i] << 8) |
5182 intel_crtc->lut_b[i]);
5183 }
5184}
5185
Chris Wilson560b85b2010-08-07 11:01:38 +01005186static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5187{
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191 bool visible = base != 0;
5192 u32 cntl;
5193
5194 if (intel_crtc->cursor_visible == visible)
5195 return;
5196
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005197 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005198 if (visible) {
5199 /* On these chipsets we can only modify the base whilst
5200 * the cursor is disabled.
5201 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005202 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005203
5204 cntl &= ~(CURSOR_FORMAT_MASK);
5205 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5206 cntl |= CURSOR_ENABLE |
5207 CURSOR_GAMMA_ENABLE |
5208 CURSOR_FORMAT_ARGB;
5209 } else
5210 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005211 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005212
5213 intel_crtc->cursor_visible = visible;
5214}
5215
5216static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5217{
5218 struct drm_device *dev = crtc->dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 int pipe = intel_crtc->pipe;
5222 bool visible = base != 0;
5223
5224 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005225 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005226 if (base) {
5227 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5228 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5229 cntl |= pipe << 28; /* Connect to correct pipe */
5230 } else {
5231 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5232 cntl |= CURSOR_MODE_DISABLE;
5233 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005234 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005235
5236 intel_crtc->cursor_visible = visible;
5237 }
5238 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005239 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005240}
5241
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005242/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005243static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5244 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005245{
5246 struct drm_device *dev = crtc->dev;
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 int pipe = intel_crtc->pipe;
5250 int x = intel_crtc->cursor_x;
5251 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005252 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005253 bool visible;
5254
5255 pos = 0;
5256
Chris Wilson6b383a72010-09-13 13:54:26 +01005257 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005258 base = intel_crtc->cursor_addr;
5259 if (x > (int) crtc->fb->width)
5260 base = 0;
5261
5262 if (y > (int) crtc->fb->height)
5263 base = 0;
5264 } else
5265 base = 0;
5266
5267 if (x < 0) {
5268 if (x + intel_crtc->cursor_width < 0)
5269 base = 0;
5270
5271 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5272 x = -x;
5273 }
5274 pos |= x << CURSOR_X_SHIFT;
5275
5276 if (y < 0) {
5277 if (y + intel_crtc->cursor_height < 0)
5278 base = 0;
5279
5280 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5281 y = -y;
5282 }
5283 pos |= y << CURSOR_Y_SHIFT;
5284
5285 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005286 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005287 return;
5288
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005289 I915_WRITE(CURPOS(pipe), pos);
Chris Wilson560b85b2010-08-07 11:01:38 +01005290 if (IS_845G(dev) || IS_I865G(dev))
5291 i845_update_cursor(crtc, base);
5292 else
5293 i9xx_update_cursor(crtc, base);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005294
5295 if (visible)
5296 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5297}
5298
Jesse Barnes79e53942008-11-07 14:24:08 -08005299static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005300 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005301 uint32_t handle,
5302 uint32_t width, uint32_t height)
5303{
5304 struct drm_device *dev = crtc->dev;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005307 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005308 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005309 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005310
Zhao Yakui28c97732009-10-09 11:39:41 +08005311 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005312
5313 /* if we want to turn off the cursor ignore width and height */
5314 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005315 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005316 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005317 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005318 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005319 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005320 }
5321
5322 /* Currently we only support 64x64 cursors */
5323 if (width != 64 || height != 64) {
5324 DRM_ERROR("we currently only support 64x64 cursors\n");
5325 return -EINVAL;
5326 }
5327
Chris Wilson05394f32010-11-08 19:18:58 +00005328 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00005329 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08005330 return -ENOENT;
5331
Chris Wilson05394f32010-11-08 19:18:58 +00005332 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005333 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005334 ret = -ENOMEM;
5335 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005336 }
5337
Dave Airlie71acb5e2008-12-30 20:31:46 +10005338 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005339 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005340 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005341 if (obj->tiling_mode) {
5342 DRM_ERROR("cursor cannot be tiled\n");
5343 ret = -EINVAL;
5344 goto fail_locked;
5345 }
5346
Chris Wilson05394f32010-11-08 19:18:58 +00005347 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005348 if (ret) {
5349 DRM_ERROR("failed to pin cursor bo\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005350 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005351 }
Chris Wilsone7b526b2010-06-02 08:30:48 +01005352
Chris Wilson05394f32010-11-08 19:18:58 +00005353 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005354 if (ret) {
5355 DRM_ERROR("failed to move cursor bo into the GTT\n");
5356 goto fail_unpin;
5357 }
5358
Chris Wilsond9e86c02010-11-10 16:40:20 +00005359 ret = i915_gem_object_put_fence(obj);
5360 if (ret) {
5361 DRM_ERROR("failed to move cursor bo into the GTT\n");
5362 goto fail_unpin;
5363 }
5364
Chris Wilson05394f32010-11-08 19:18:58 +00005365 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005366 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005367 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005368 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005369 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5370 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005371 if (ret) {
5372 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005373 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005374 }
Chris Wilson05394f32010-11-08 19:18:58 +00005375 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005376 }
5377
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005378 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005379 I915_WRITE(CURSIZE, (height << 12) | width);
5380
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005381 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005382 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005383 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005384 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005385 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5386 } else
5387 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005388 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005389 }
Jesse Barnes80824002009-09-10 15:28:06 -07005390
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005391 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005392
5393 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005394 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005395 intel_crtc->cursor_width = width;
5396 intel_crtc->cursor_height = height;
5397
Chris Wilson6b383a72010-09-13 13:54:26 +01005398 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005399
Jesse Barnes79e53942008-11-07 14:24:08 -08005400 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005401fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005402 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005403fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005404 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005405fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005406 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005407 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005408}
5409
5410static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5411{
Jesse Barnes79e53942008-11-07 14:24:08 -08005412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005413
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005414 intel_crtc->cursor_x = x;
5415 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005416
Chris Wilson6b383a72010-09-13 13:54:26 +01005417 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005418
5419 return 0;
5420}
5421
5422/** Sets the color ramps on behalf of RandR */
5423void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5424 u16 blue, int regno)
5425{
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427
5428 intel_crtc->lut_r[regno] = red >> 8;
5429 intel_crtc->lut_g[regno] = green >> 8;
5430 intel_crtc->lut_b[regno] = blue >> 8;
5431}
5432
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005433void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5434 u16 *blue, int regno)
5435{
5436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437
5438 *red = intel_crtc->lut_r[regno] << 8;
5439 *green = intel_crtc->lut_g[regno] << 8;
5440 *blue = intel_crtc->lut_b[regno] << 8;
5441}
5442
Jesse Barnes79e53942008-11-07 14:24:08 -08005443static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005444 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005445{
James Simmons72034252010-08-03 01:33:19 +01005446 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005448
James Simmons72034252010-08-03 01:33:19 +01005449 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005450 intel_crtc->lut_r[i] = red[i] >> 8;
5451 intel_crtc->lut_g[i] = green[i] >> 8;
5452 intel_crtc->lut_b[i] = blue[i] >> 8;
5453 }
5454
5455 intel_crtc_load_lut(crtc);
5456}
5457
5458/**
5459 * Get a pipe with a simple mode set on it for doing load-based monitor
5460 * detection.
5461 *
5462 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005463 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005464 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005465 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005466 * configured for it. In the future, it could choose to temporarily disable
5467 * some outputs to free up a pipe for its use.
5468 *
5469 * \return crtc, or NULL if no pipes are available.
5470 */
5471
5472/* VESA 640x480x72Hz mode to set on the pipe */
5473static struct drm_display_mode load_detect_mode = {
5474 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5475 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5476};
5477
Eric Anholt21d40d32010-03-25 11:11:14 -07005478struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005479 struct drm_connector *connector,
Jesse Barnes79e53942008-11-07 14:24:08 -08005480 struct drm_display_mode *mode,
5481 int *dpms_mode)
5482{
5483 struct intel_crtc *intel_crtc;
5484 struct drm_crtc *possible_crtc;
5485 struct drm_crtc *supported_crtc =NULL;
Chris Wilson4ef69c72010-09-09 15:14:28 +01005486 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005487 struct drm_crtc *crtc = NULL;
5488 struct drm_device *dev = encoder->dev;
5489 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5490 struct drm_crtc_helper_funcs *crtc_funcs;
5491 int i = -1;
5492
5493 /*
5494 * Algorithm gets a little messy:
5495 * - if the connector already has an assigned crtc, use it (but make
5496 * sure it's on first)
5497 * - try to find the first unused crtc that can drive this connector,
5498 * and use that if we find one
5499 * - if there are no unused crtcs available, try to use the first
5500 * one we found that supports the connector
5501 */
5502
5503 /* See if we already have a CRTC for this connector */
5504 if (encoder->crtc) {
5505 crtc = encoder->crtc;
5506 /* Make sure the crtc and connector are running */
5507 intel_crtc = to_intel_crtc(crtc);
5508 *dpms_mode = intel_crtc->dpms_mode;
5509 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5510 crtc_funcs = crtc->helper_private;
5511 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5512 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5513 }
5514 return crtc;
5515 }
5516
5517 /* Find an unused one (if possible) */
5518 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5519 i++;
5520 if (!(encoder->possible_crtcs & (1 << i)))
5521 continue;
5522 if (!possible_crtc->enabled) {
5523 crtc = possible_crtc;
5524 break;
5525 }
5526 if (!supported_crtc)
5527 supported_crtc = possible_crtc;
5528 }
5529
5530 /*
5531 * If we didn't find an unused CRTC, don't use any.
5532 */
5533 if (!crtc) {
5534 return NULL;
5535 }
5536
5537 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005538 connector->encoder = encoder;
Eric Anholt21d40d32010-03-25 11:11:14 -07005539 intel_encoder->load_detect_temp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005540
5541 intel_crtc = to_intel_crtc(crtc);
5542 *dpms_mode = intel_crtc->dpms_mode;
5543
5544 if (!crtc->enabled) {
5545 if (!mode)
5546 mode = &load_detect_mode;
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05005547 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005548 } else {
5549 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5550 crtc_funcs = crtc->helper_private;
5551 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5552 }
5553
5554 /* Add this connector to the crtc */
5555 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
5556 encoder_funcs->commit(encoder);
5557 }
5558 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005559 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005560
5561 return crtc;
5562}
5563
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005564void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5565 struct drm_connector *connector, int dpms_mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08005566{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005567 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005568 struct drm_device *dev = encoder->dev;
5569 struct drm_crtc *crtc = encoder->crtc;
5570 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5571 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5572
Eric Anholt21d40d32010-03-25 11:11:14 -07005573 if (intel_encoder->load_detect_temp) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005574 encoder->crtc = NULL;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005575 connector->encoder = NULL;
Eric Anholt21d40d32010-03-25 11:11:14 -07005576 intel_encoder->load_detect_temp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005577 crtc->enabled = drm_helper_crtc_in_use(crtc);
5578 drm_helper_disable_unused_functions(dev);
5579 }
5580
Eric Anholtc751ce42010-03-25 11:48:48 -07005581 /* Switch crtc and encoder back off if necessary */
Jesse Barnes79e53942008-11-07 14:24:08 -08005582 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
5583 if (encoder->crtc == crtc)
5584 encoder_funcs->dpms(encoder, dpms_mode);
5585 crtc_funcs->dpms(crtc, dpms_mode);
5586 }
5587}
5588
5589/* Returns the clock of the currently programmed mode of the given pipe. */
5590static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5591{
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08005595 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005596 u32 fp;
5597 intel_clock_t clock;
5598
5599 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005600 fp = FP0(pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005601 else
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005602 fp = FP1(pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005603
5604 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005605 if (IS_PINEVIEW(dev)) {
5606 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5607 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08005608 } else {
5609 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5610 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5611 }
5612
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005613 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005614 if (IS_PINEVIEW(dev))
5615 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5616 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08005617 else
5618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08005619 DPLL_FPA01_P1_POST_DIV_SHIFT);
5620
5621 switch (dpll & DPLL_MODE_MASK) {
5622 case DPLLB_MODE_DAC_SERIAL:
5623 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5624 5 : 10;
5625 break;
5626 case DPLLB_MODE_LVDS:
5627 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5628 7 : 14;
5629 break;
5630 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08005631 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08005632 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5633 return 0;
5634 }
5635
5636 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08005637 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005638 } else {
5639 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5640
5641 if (is_lvds) {
5642 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5643 DPLL_FPA01_P1_POST_DIV_SHIFT);
5644 clock.p2 = 14;
5645
5646 if ((dpll & PLL_REF_INPUT_MASK) ==
5647 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5648 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08005649 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005650 } else
Shaohua Li21778322009-02-23 15:19:16 +08005651 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005652 } else {
5653 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5654 clock.p1 = 2;
5655 else {
5656 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5657 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5658 }
5659 if (dpll & PLL_P2_DIVIDE_BY_4)
5660 clock.p2 = 4;
5661 else
5662 clock.p2 = 2;
5663
Shaohua Li21778322009-02-23 15:19:16 +08005664 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005665 }
5666 }
5667
5668 /* XXX: It would be nice to validate the clocks, but we can't reuse
5669 * i830PllIsValid() because it relies on the xf86_config connector
5670 * configuration being accurate, which it isn't necessarily.
5671 */
5672
5673 return clock.dot;
5674}
5675
5676/** Returns the currently programmed mode of the given pipe. */
5677struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5678 struct drm_crtc *crtc)
5679{
Jesse Barnes548f2452011-02-17 10:40:53 -08005680 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5682 int pipe = intel_crtc->pipe;
5683 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08005684 int htot = I915_READ(HTOTAL(pipe));
5685 int hsync = I915_READ(HSYNC(pipe));
5686 int vtot = I915_READ(VTOTAL(pipe));
5687 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005688
5689 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5690 if (!mode)
5691 return NULL;
5692
5693 mode->clock = intel_crtc_clock_get(dev, crtc);
5694 mode->hdisplay = (htot & 0xffff) + 1;
5695 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5696 mode->hsync_start = (hsync & 0xffff) + 1;
5697 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5698 mode->vdisplay = (vtot & 0xffff) + 1;
5699 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5700 mode->vsync_start = (vsync & 0xffff) + 1;
5701 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5702
5703 drm_mode_set_name(mode);
5704 drm_mode_set_crtcinfo(mode, 0);
5705
5706 return mode;
5707}
5708
Jesse Barnes652c3932009-08-17 13:31:43 -07005709#define GPU_IDLE_TIMEOUT 500 /* ms */
5710
5711/* When this timer fires, we've been idle for awhile */
5712static void intel_gpu_idle_timer(unsigned long arg)
5713{
5714 struct drm_device *dev = (struct drm_device *)arg;
5715 drm_i915_private_t *dev_priv = dev->dev_private;
5716
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005717 if (!list_empty(&dev_priv->mm.active_list)) {
5718 /* Still processing requests, so just re-arm the timer. */
5719 mod_timer(&dev_priv->idle_timer, jiffies +
5720 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5721 return;
5722 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005723
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005724 dev_priv->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005725 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005726}
5727
Jesse Barnes652c3932009-08-17 13:31:43 -07005728#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5729
5730static void intel_crtc_idle_timer(unsigned long arg)
5731{
5732 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5733 struct drm_crtc *crtc = &intel_crtc->base;
5734 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00005735 struct intel_framebuffer *intel_fb;
5736
5737 intel_fb = to_intel_framebuffer(crtc->fb);
5738 if (intel_fb && intel_fb->obj->active) {
5739 /* The framebuffer is still being accessed by the GPU. */
5740 mod_timer(&intel_crtc->idle_timer, jiffies +
5741 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5742 return;
5743 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005744
Jesse Barnes652c3932009-08-17 13:31:43 -07005745 intel_crtc->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07005746 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07005747}
5748
Daniel Vetter3dec0092010-08-20 21:40:52 +02005749static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07005750{
5751 struct drm_device *dev = crtc->dev;
5752 drm_i915_private_t *dev_priv = dev->dev_private;
5753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5754 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005755 int dpll_reg = DPLL(pipe);
5756 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07005757
Eric Anholtbad720f2009-10-22 16:11:14 -07005758 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005759 return;
5760
5761 if (!dev_priv->lvds_downclock_avail)
5762 return;
5763
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005764 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005765 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005766 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005767
5768 /* Unlock panel regs */
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005769 I915_WRITE(PP_CONTROL,
5770 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07005771
5772 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5773 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005774 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005775
Jesse Barnes652c3932009-08-17 13:31:43 -07005776 dpll = I915_READ(dpll_reg);
5777 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08005778 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005779
5780 /* ...and lock them again */
5781 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5782 }
5783
5784 /* Schedule downclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02005785 mod_timer(&intel_crtc->idle_timer, jiffies +
5786 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07005787}
5788
5789static void intel_decrease_pllclock(struct drm_crtc *crtc)
5790{
5791 struct drm_device *dev = crtc->dev;
5792 drm_i915_private_t *dev_priv = dev->dev_private;
5793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5794 int pipe = intel_crtc->pipe;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005795 int dpll_reg = DPLL(pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005796 int dpll = I915_READ(dpll_reg);
5797
Eric Anholtbad720f2009-10-22 16:11:14 -07005798 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005799 return;
5800
5801 if (!dev_priv->lvds_downclock_avail)
5802 return;
5803
5804 /*
5805 * Since this is called by a timer, we should never get here in
5806 * the manual case.
5807 */
5808 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005809 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005810
5811 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07005812 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5813 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07005814
5815 dpll |= DISPLAY_RATE_SELECT_FPA1;
5816 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005817 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005818 dpll = I915_READ(dpll_reg);
5819 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08005820 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005821
5822 /* ...and lock them again */
5823 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5824 }
5825
5826}
5827
5828/**
5829 * intel_idle_update - adjust clocks for idleness
5830 * @work: work struct
5831 *
5832 * Either the GPU or display (or both) went idle. Check the busy status
5833 * here and adjust the CRTC and GPU clocks as necessary.
5834 */
5835static void intel_idle_update(struct work_struct *work)
5836{
5837 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5838 idle_work);
5839 struct drm_device *dev = dev_priv->dev;
5840 struct drm_crtc *crtc;
5841 struct intel_crtc *intel_crtc;
5842
5843 if (!i915_powersave)
5844 return;
5845
5846 mutex_lock(&dev->struct_mutex);
5847
Jesse Barnes7648fa92010-05-20 14:28:11 -07005848 i915_update_gfx_val(dev_priv);
5849
Jesse Barnes652c3932009-08-17 13:31:43 -07005850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5851 /* Skip inactive CRTCs */
5852 if (!crtc->fb)
5853 continue;
5854
5855 intel_crtc = to_intel_crtc(crtc);
5856 if (!intel_crtc->busy)
5857 intel_decrease_pllclock(crtc);
5858 }
5859
Li Peng45ac22c2010-06-12 23:38:35 +08005860
Jesse Barnes652c3932009-08-17 13:31:43 -07005861 mutex_unlock(&dev->struct_mutex);
5862}
5863
5864/**
5865 * intel_mark_busy - mark the GPU and possibly the display busy
5866 * @dev: drm device
5867 * @obj: object we're operating on
5868 *
5869 * Callers can use this function to indicate that the GPU is busy processing
5870 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5871 * buffer), we'll also mark the display as busy, so we know to increase its
5872 * clock frequency.
5873 */
Chris Wilson05394f32010-11-08 19:18:58 +00005874void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07005875{
5876 drm_i915_private_t *dev_priv = dev->dev_private;
5877 struct drm_crtc *crtc = NULL;
5878 struct intel_framebuffer *intel_fb;
5879 struct intel_crtc *intel_crtc;
5880
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08005881 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5882 return;
5883
Alexander Lam18b21902011-01-03 13:28:56 -05005884 if (!dev_priv->busy)
Chris Wilson28cf7982009-11-30 01:08:56 +00005885 dev_priv->busy = true;
Alexander Lam18b21902011-01-03 13:28:56 -05005886 else
Chris Wilson28cf7982009-11-30 01:08:56 +00005887 mod_timer(&dev_priv->idle_timer, jiffies +
5888 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07005889
5890 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5891 if (!crtc->fb)
5892 continue;
5893
5894 intel_crtc = to_intel_crtc(crtc);
5895 intel_fb = to_intel_framebuffer(crtc->fb);
5896 if (intel_fb->obj == obj) {
5897 if (!intel_crtc->busy) {
5898 /* Non-busy -> busy, upclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02005899 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005900 intel_crtc->busy = true;
5901 } else {
5902 /* Busy -> busy, put off timer */
5903 mod_timer(&intel_crtc->idle_timer, jiffies +
5904 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5905 }
5906 }
5907 }
5908}
5909
Jesse Barnes79e53942008-11-07 14:24:08 -08005910static void intel_crtc_destroy(struct drm_crtc *crtc)
5911{
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005913 struct drm_device *dev = crtc->dev;
5914 struct intel_unpin_work *work;
5915 unsigned long flags;
5916
5917 spin_lock_irqsave(&dev->event_lock, flags);
5918 work = intel_crtc->unpin_work;
5919 intel_crtc->unpin_work = NULL;
5920 spin_unlock_irqrestore(&dev->event_lock, flags);
5921
5922 if (work) {
5923 cancel_work_sync(&work->work);
5924 kfree(work);
5925 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005926
5927 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005928
Jesse Barnes79e53942008-11-07 14:24:08 -08005929 kfree(intel_crtc);
5930}
5931
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005932static void intel_unpin_work_fn(struct work_struct *__work)
5933{
5934 struct intel_unpin_work *work =
5935 container_of(__work, struct intel_unpin_work, work);
5936
5937 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08005938 i915_gem_object_unpin(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00005939 drm_gem_object_unreference(&work->pending_flip_obj->base);
5940 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00005941
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005942 mutex_unlock(&work->dev->struct_mutex);
5943 kfree(work);
5944}
5945
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005946static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01005947 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005948{
5949 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00005952 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005953 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005954 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005955 unsigned long flags;
5956
5957 /* Ignore early vblank irqs */
5958 if (intel_crtc == NULL)
5959 return;
5960
Mario Kleiner49b14a52010-12-09 07:00:07 +01005961 do_gettimeofday(&tnow);
5962
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005963 spin_lock_irqsave(&dev->event_lock, flags);
5964 work = intel_crtc->unpin_work;
5965 if (work == NULL || !work->pending) {
5966 spin_unlock_irqrestore(&dev->event_lock, flags);
5967 return;
5968 }
5969
5970 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005971
5972 if (work->event) {
5973 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005974 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005975
5976 /* Called before vblank count and timestamps have
5977 * been updated for the vblank interval of flip
5978 * completion? Need to increment vblank count and
5979 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01005980 * to account for this. We assume this happened if we
5981 * get called over 0.9 frame durations after the last
5982 * timestamped vblank.
5983 *
5984 * This calculation can not be used with vrefresh rates
5985 * below 5Hz (10Hz to be on the safe side) without
5986 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005987 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01005988 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5989 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005990 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005991 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5992 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005993 }
5994
Mario Kleiner49b14a52010-12-09 07:00:07 +01005995 e->event.tv_sec = tvbl.tv_sec;
5996 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01005997
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005998 list_add_tail(&e->base.link,
5999 &e->base.file_priv->event_list);
6000 wake_up_interruptible(&e->base.file_priv->event_wait);
6001 }
6002
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006003 drm_vblank_put(dev, intel_crtc->pipe);
6004
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006005 spin_unlock_irqrestore(&dev->event_lock, flags);
6006
Chris Wilson05394f32010-11-08 19:18:58 +00006007 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006008
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006009 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006010 &obj->pending_flip.counter);
6011 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006012 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006013
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006014 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006015
6016 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006017}
6018
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006019void intel_finish_page_flip(struct drm_device *dev, int pipe)
6020{
6021 drm_i915_private_t *dev_priv = dev->dev_private;
6022 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6023
Mario Kleiner49b14a52010-12-09 07:00:07 +01006024 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006025}
6026
6027void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6028{
6029 drm_i915_private_t *dev_priv = dev->dev_private;
6030 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6031
Mario Kleiner49b14a52010-12-09 07:00:07 +01006032 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006033}
6034
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006035void intel_prepare_page_flip(struct drm_device *dev, int plane)
6036{
6037 drm_i915_private_t *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc =
6039 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6040 unsigned long flags;
6041
6042 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006043 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006044 if ((++intel_crtc->unpin_work->pending) > 1)
6045 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006046 } else {
6047 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6048 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006049 spin_unlock_irqrestore(&dev->event_lock, flags);
6050}
6051
6052static int intel_crtc_page_flip(struct drm_crtc *crtc,
6053 struct drm_framebuffer *fb,
6054 struct drm_pending_vblank_event *event)
6055{
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00006059 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061 struct intel_unpin_work *work;
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07006062 unsigned long flags, offset;
Chris Wilson52e68632010-08-08 10:15:59 +01006063 int pipe = intel_crtc->pipe;
Chris Wilson20f0cd52010-09-23 11:00:38 +01006064 u32 pf, pipesrc;
Chris Wilson52e68632010-08-08 10:15:59 +01006065 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006066
6067 work = kzalloc(sizeof *work, GFP_KERNEL);
6068 if (work == NULL)
6069 return -ENOMEM;
6070
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006071 work->event = event;
6072 work->dev = crtc->dev;
6073 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006074 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006075 INIT_WORK(&work->work, intel_unpin_work_fn);
6076
6077 /* We borrow the event spin lock for protecting unpin_work */
6078 spin_lock_irqsave(&dev->event_lock, flags);
6079 if (intel_crtc->unpin_work) {
6080 spin_unlock_irqrestore(&dev->event_lock, flags);
6081 kfree(work);
Chris Wilson468f0b42010-05-27 13:18:13 +01006082
6083 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006084 return -EBUSY;
6085 }
6086 intel_crtc->unpin_work = work;
6087 spin_unlock_irqrestore(&dev->event_lock, flags);
6088
6089 intel_fb = to_intel_framebuffer(fb);
6090 obj = intel_fb->obj;
6091
Chris Wilson468f0b42010-05-27 13:18:13 +01006092 mutex_lock(&dev->struct_mutex);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00006093 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
Chris Wilson96b099f2010-06-07 14:03:04 +01006094 if (ret)
6095 goto cleanup_work;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006096
Jesse Barnes75dfca82010-02-10 15:09:44 -08006097 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00006098 drm_gem_object_reference(&work->old_fb_obj->base);
6099 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006100
6101 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01006102
6103 ret = drm_vblank_get(dev, intel_crtc->pipe);
6104 if (ret)
6105 goto cleanup_objs;
6106
Chris Wilsonc7f9f9a2010-09-19 15:05:13 +01006107 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6108 u32 flip_mask;
6109
6110 /* Can't queue multiple flips, so wait for the previous
6111 * one to finish before executing the next.
6112 */
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006113 ret = BEGIN_LP_RING(2);
6114 if (ret)
6115 goto cleanup_objs;
6116
Chris Wilsonc7f9f9a2010-09-19 15:05:13 +01006117 if (intel_crtc->plane)
6118 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6119 else
6120 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6121 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6122 OUT_RING(MI_NOOP);
Daniel Vetter6146b3d2010-08-04 21:22:10 +02006123 ADVANCE_LP_RING();
6124 }
Jesse Barnes83f7fd02010-04-05 14:03:51 -07006125
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006126 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006127
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006128 work->enable_stall_check = true;
6129
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07006130 /* Offset into the new buffer for cases of shared fbs between CRTCs */
Chris Wilson52e68632010-08-08 10:15:59 +01006131 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
Jesse Barnesbe9a3db2010-07-23 12:03:37 -07006132
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006133 ret = BEGIN_LP_RING(4);
6134 if (ret)
6135 goto cleanup_objs;
6136
6137 /* Block clients from rendering to the new back buffer until
6138 * the flip occurs and the object is no longer visible.
6139 */
Chris Wilson05394f32010-11-08 19:18:58 +00006140 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006141
6142 switch (INTEL_INFO(dev)->gen) {
Chris Wilson52e68632010-08-08 10:15:59 +01006143 case 2:
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006144 OUT_RING(MI_DISPLAY_FLIP |
6145 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6146 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006147 OUT_RING(obj->gtt_offset + offset);
Chris Wilson52e68632010-08-08 10:15:59 +01006148 OUT_RING(MI_NOOP);
6149 break;
6150
6151 case 3:
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006152 OUT_RING(MI_DISPLAY_FLIP_I915 |
6153 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6154 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006155 OUT_RING(obj->gtt_offset + offset);
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006156 OUT_RING(MI_NOOP);
Chris Wilson52e68632010-08-08 10:15:59 +01006157 break;
6158
6159 case 4:
6160 case 5:
6161 /* i965+ uses the linear or tiled offsets from the
6162 * Display Registers (which do not change across a page-flip)
6163 * so we need only reprogram the base address.
6164 */
Daniel Vetter69d0b962010-08-04 21:22:09 +02006165 OUT_RING(MI_DISPLAY_FLIP |
6166 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6167 OUT_RING(fb->pitch);
Chris Wilson05394f32010-11-08 19:18:58 +00006168 OUT_RING(obj->gtt_offset | obj->tiling_mode);
Chris Wilson52e68632010-08-08 10:15:59 +01006169
6170 /* XXX Enabling the panel-fitter across page-flip is so far
6171 * untested on non-native modes, so ignore it for now.
6172 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6173 */
6174 pf = 0;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006175 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
Chris Wilson52e68632010-08-08 10:15:59 +01006176 OUT_RING(pf | pipesrc);
6177 break;
6178
6179 case 6:
6180 OUT_RING(MI_DISPLAY_FLIP |
6181 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Chris Wilson05394f32010-11-08 19:18:58 +00006182 OUT_RING(fb->pitch | obj->tiling_mode);
6183 OUT_RING(obj->gtt_offset);
Chris Wilson52e68632010-08-08 10:15:59 +01006184
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006185 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6186 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
Chris Wilson52e68632010-08-08 10:15:59 +01006187 OUT_RING(pf | pipesrc);
6188 break;
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006189 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006190 ADVANCE_LP_RING();
6191
6192 mutex_unlock(&dev->struct_mutex);
6193
Jesse Barnese5510fa2010-07-01 16:48:37 -07006194 trace_i915_flip_request(intel_crtc->plane, obj);
6195
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006196 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006197
6198cleanup_objs:
Chris Wilson05394f32010-11-08 19:18:58 +00006199 drm_gem_object_unreference(&work->old_fb_obj->base);
6200 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006201cleanup_work:
6202 mutex_unlock(&dev->struct_mutex);
6203
6204 spin_lock_irqsave(&dev->event_lock, flags);
6205 intel_crtc->unpin_work = NULL;
6206 spin_unlock_irqrestore(&dev->event_lock, flags);
6207
6208 kfree(work);
6209
6210 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006211}
6212
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006213static void intel_crtc_reset(struct drm_crtc *crtc)
6214{
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216
6217 /* Reset flags back to the 'unknown' status so that they
6218 * will be correctly set on the initial modeset.
6219 */
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006220 intel_crtc->dpms_mode = -1;
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006221}
6222
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006223static struct drm_crtc_helper_funcs intel_helper_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006224 .dpms = intel_crtc_dpms,
6225 .mode_fixup = intel_crtc_mode_fixup,
6226 .mode_set = intel_crtc_mode_set,
6227 .mode_set_base = intel_pipe_set_base,
Jesse Barnes81255562010-08-02 12:07:50 -07006228 .mode_set_base_atomic = intel_pipe_set_base_atomic,
Dave Airlie068143d2009-10-05 09:58:02 +10006229 .load_lut = intel_crtc_load_lut,
Chris Wilsoncdd59982010-09-08 16:30:16 +01006230 .disable = intel_crtc_disable,
Jesse Barnes79e53942008-11-07 14:24:08 -08006231};
6232
6233static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006234 .reset = intel_crtc_reset,
Jesse Barnes79e53942008-11-07 14:24:08 -08006235 .cursor_set = intel_crtc_cursor_set,
6236 .cursor_move = intel_crtc_cursor_move,
6237 .gamma_set = intel_crtc_gamma_set,
6238 .set_config = drm_crtc_helper_set_config,
6239 .destroy = intel_crtc_destroy,
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006240 .page_flip = intel_crtc_page_flip,
Jesse Barnes79e53942008-11-07 14:24:08 -08006241};
6242
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006243static void intel_sanitize_modesetting(struct drm_device *dev,
6244 int pipe, int plane)
6245{
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 u32 reg, val;
6248
6249 if (HAS_PCH_SPLIT(dev))
6250 return;
6251
6252 /* Who knows what state these registers were left in by the BIOS or
6253 * grub?
6254 *
6255 * If we leave the registers in a conflicting state (e.g. with the
6256 * display plane reading from the other pipe than the one we intend
6257 * to use) then when we attempt to teardown the active mode, we will
6258 * not disable the pipes and planes in the correct order -- leaving
6259 * a plane reading from a disabled pipe and possibly leading to
6260 * undefined behaviour.
6261 */
6262
6263 reg = DSPCNTR(plane);
6264 val = I915_READ(reg);
6265
6266 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6267 return;
6268 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6269 return;
6270
6271 /* This display plane is active and attached to the other CPU pipe. */
6272 pipe = !pipe;
6273
6274 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006275 intel_disable_plane(dev_priv, plane, pipe);
6276 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006277}
Jesse Barnes79e53942008-11-07 14:24:08 -08006278
Hannes Ederb358d0a2008-12-18 21:18:47 +01006279static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08006280{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006281 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006282 struct intel_crtc *intel_crtc;
6283 int i;
6284
6285 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6286 if (intel_crtc == NULL)
6287 return;
6288
6289 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6290
6291 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08006292 for (i = 0; i < 256; i++) {
6293 intel_crtc->lut_r[i] = i;
6294 intel_crtc->lut_g[i] = i;
6295 intel_crtc->lut_b[i] = i;
6296 }
6297
Jesse Barnes80824002009-09-10 15:28:06 -07006298 /* Swap pipes & planes for FBC on pre-965 */
6299 intel_crtc->pipe = pipe;
6300 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01006301 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006302 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01006303 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07006304 }
6305
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006306 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6307 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6308 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6309 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6310
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006311 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00006312 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006313
6314 if (HAS_PCH_SPLIT(dev)) {
6315 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6316 intel_helper_funcs.commit = ironlake_crtc_commit;
6317 } else {
6318 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6319 intel_helper_funcs.commit = i9xx_crtc_commit;
6320 }
6321
Jesse Barnes79e53942008-11-07 14:24:08 -08006322 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6323
Jesse Barnes652c3932009-08-17 13:31:43 -07006324 intel_crtc->busy = false;
6325
6326 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6327 (unsigned long)intel_crtc);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006328
6329 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
Jesse Barnes79e53942008-11-07 14:24:08 -08006330}
6331
Carl Worth08d7b3d2009-04-29 14:43:54 -07006332int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00006333 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07006334{
6335 drm_i915_private_t *dev_priv = dev->dev_private;
6336 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02006337 struct drm_mode_object *drmmode_obj;
6338 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006339
6340 if (!dev_priv) {
6341 DRM_ERROR("called with no initialization\n");
6342 return -EINVAL;
6343 }
6344
Daniel Vetterc05422d2009-08-11 16:05:30 +02006345 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6346 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07006347
Daniel Vetterc05422d2009-08-11 16:05:30 +02006348 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07006349 DRM_ERROR("no such CRTC id\n");
6350 return -EINVAL;
6351 }
6352
Daniel Vetterc05422d2009-08-11 16:05:30 +02006353 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6354 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006355
Daniel Vetterc05422d2009-08-11 16:05:30 +02006356 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006357}
6358
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08006359static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006360{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006361 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006362 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006363 int entry = 0;
6364
Chris Wilson4ef69c72010-09-09 15:14:28 +01006365 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6366 if (type_mask & encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08006367 index_mask |= (1 << entry);
6368 entry++;
6369 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01006370
Jesse Barnes79e53942008-11-07 14:24:08 -08006371 return index_mask;
6372}
6373
Chris Wilson4d302442010-12-14 19:21:29 +00006374static bool has_edp_a(struct drm_device *dev)
6375{
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377
6378 if (!IS_MOBILE(dev))
6379 return false;
6380
6381 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6382 return false;
6383
6384 if (IS_GEN5(dev) &&
6385 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6386 return false;
6387
6388 return true;
6389}
6390
Jesse Barnes79e53942008-11-07 14:24:08 -08006391static void intel_setup_outputs(struct drm_device *dev)
6392{
Eric Anholt725e30a2009-01-22 13:01:02 -08006393 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006394 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006395 bool dpd_is_edp = false;
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006396 bool has_lvds = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006397
Zhenyu Wang541998a2009-06-05 15:38:44 +08006398 if (IS_MOBILE(dev) && !IS_I830(dev))
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006399 has_lvds = intel_lvds_init(dev);
6400 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6401 /* disable the panel fitter on everything but LVDS */
6402 I915_WRITE(PFIT_CONTROL, 0);
6403 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006404
Eric Anholtbad720f2009-10-22 16:11:14 -07006405 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006406 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006407
Chris Wilson4d302442010-12-14 19:21:29 +00006408 if (has_edp_a(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006409 intel_dp_init(dev, DP_A);
6410
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006411 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6412 intel_dp_init(dev, PCH_DP_D);
6413 }
6414
6415 intel_crt_init(dev);
6416
6417 if (HAS_PCH_SPLIT(dev)) {
6418 int found;
6419
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006420 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08006421 /* PCH SDVOB multiplex with HDMIB */
6422 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006423 if (!found)
6424 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006425 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6426 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006427 }
6428
6429 if (I915_READ(HDMIC) & PORT_DETECTED)
6430 intel_hdmi_init(dev, HDMIC);
6431
6432 if (I915_READ(HDMID) & PORT_DETECTED)
6433 intel_hdmi_init(dev, HDMID);
6434
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006435 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6436 intel_dp_init(dev, PCH_DP_C);
6437
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006438 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006439 intel_dp_init(dev, PCH_DP_D);
6440
Zhenyu Wang103a1962009-11-27 11:44:36 +08006441 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08006442 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08006443
Eric Anholt725e30a2009-01-22 13:01:02 -08006444 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006445 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006446 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006447 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6448 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006449 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006450 }
Ma Ling27185ae2009-08-24 13:50:23 +08006451
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006452 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6453 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006454 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006455 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006456 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006457
6458 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006459
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006460 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6461 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006462 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006463 }
Ma Ling27185ae2009-08-24 13:50:23 +08006464
6465 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6466
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006467 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6468 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08006469 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006470 }
6471 if (SUPPORTS_INTEGRATED_DP(dev)) {
6472 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006473 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006474 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006475 }
Ma Ling27185ae2009-08-24 13:50:23 +08006476
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006477 if (SUPPORTS_INTEGRATED_DP(dev) &&
6478 (I915_READ(DP_D) & DP_DETECTED)) {
6479 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07006480 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006481 }
Eric Anholtbad720f2009-10-22 16:11:14 -07006482 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006483 intel_dvo_init(dev);
6484
Zhenyu Wang103a1962009-11-27 11:44:36 +08006485 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006486 intel_tv_init(dev);
6487
Chris Wilson4ef69c72010-09-09 15:14:28 +01006488 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6489 encoder->base.possible_crtcs = encoder->crtc_mask;
6490 encoder->base.possible_clones =
6491 intel_encoder_clones(dev, encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08006492 }
Chris Wilson47356eb2011-01-11 17:06:04 +00006493
6494 intel_panel_setup_backlight(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006495}
6496
6497static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6498{
6499 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08006500
6501 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006502 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08006503
6504 kfree(intel_fb);
6505}
6506
6507static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00006508 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006509 unsigned int *handle)
6510{
6511 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006512 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006513
Chris Wilson05394f32010-11-08 19:18:58 +00006514 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08006515}
6516
6517static const struct drm_framebuffer_funcs intel_fb_funcs = {
6518 .destroy = intel_user_framebuffer_destroy,
6519 .create_handle = intel_user_framebuffer_create_handle,
6520};
6521
Dave Airlie38651672010-03-30 05:34:13 +00006522int intel_framebuffer_init(struct drm_device *dev,
6523 struct intel_framebuffer *intel_fb,
6524 struct drm_mode_fb_cmd *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00006525 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08006526{
Jesse Barnes79e53942008-11-07 14:24:08 -08006527 int ret;
6528
Chris Wilson05394f32010-11-08 19:18:58 +00006529 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01006530 return -EINVAL;
6531
6532 if (mode_cmd->pitch & 63)
6533 return -EINVAL;
6534
6535 switch (mode_cmd->bpp) {
6536 case 8:
6537 case 16:
6538 case 24:
6539 case 32:
6540 break;
6541 default:
6542 return -EINVAL;
6543 }
6544
Jesse Barnes79e53942008-11-07 14:24:08 -08006545 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6546 if (ret) {
6547 DRM_ERROR("framebuffer init failed %d\n", ret);
6548 return ret;
6549 }
6550
6551 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08006552 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006553 return 0;
6554}
6555
Jesse Barnes79e53942008-11-07 14:24:08 -08006556static struct drm_framebuffer *
6557intel_user_framebuffer_create(struct drm_device *dev,
6558 struct drm_file *filp,
6559 struct drm_mode_fb_cmd *mode_cmd)
6560{
Chris Wilson05394f32010-11-08 19:18:58 +00006561 struct drm_i915_gem_object *obj;
Dave Airlie38651672010-03-30 05:34:13 +00006562 struct intel_framebuffer *intel_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006563 int ret;
6564
Chris Wilson05394f32010-11-08 19:18:58 +00006565 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006566 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006567 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08006568
Dave Airlie38651672010-03-30 05:34:13 +00006569 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6570 if (!intel_fb)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006571 return ERR_PTR(-ENOMEM);
Dave Airlie38651672010-03-30 05:34:13 +00006572
Chris Wilson05394f32010-11-08 19:18:58 +00006573 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08006574 if (ret) {
Chris Wilson05394f32010-11-08 19:18:58 +00006575 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie38651672010-03-30 05:34:13 +00006576 kfree(intel_fb);
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006577 return ERR_PTR(ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08006578 }
6579
Dave Airlie38651672010-03-30 05:34:13 +00006580 return &intel_fb->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006581}
6582
Jesse Barnes79e53942008-11-07 14:24:08 -08006583static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006584 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00006585 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08006586};
6587
Chris Wilson05394f32010-11-08 19:18:58 +00006588static struct drm_i915_gem_object *
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006589intel_alloc_context_page(struct drm_device *dev)
Chris Wilson9ea8d052010-01-04 18:57:56 +00006590{
Chris Wilson05394f32010-11-08 19:18:58 +00006591 struct drm_i915_gem_object *ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006592 int ret;
6593
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006594 ctx = i915_gem_alloc_object(dev, 4096);
6595 if (!ctx) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00006596 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6597 return NULL;
6598 }
6599
6600 mutex_lock(&dev->struct_mutex);
Daniel Vetter75e9e912010-11-04 17:11:09 +01006601 ret = i915_gem_object_pin(ctx, 4096, true);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006602 if (ret) {
6603 DRM_ERROR("failed to pin power context: %d\n", ret);
6604 goto err_unref;
6605 }
6606
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006607 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006608 if (ret) {
6609 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6610 goto err_unpin;
6611 }
6612 mutex_unlock(&dev->struct_mutex);
6613
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006614 return ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00006615
6616err_unpin:
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08006617 i915_gem_object_unpin(ctx);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006618err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00006619 drm_gem_object_unreference(&ctx->base);
Chris Wilson9ea8d052010-01-04 18:57:56 +00006620 mutex_unlock(&dev->struct_mutex);
6621 return NULL;
6622}
6623
Jesse Barnes7648fa92010-05-20 14:28:11 -07006624bool ironlake_set_drps(struct drm_device *dev, u8 val)
6625{
6626 struct drm_i915_private *dev_priv = dev->dev_private;
6627 u16 rgvswctl;
6628
6629 rgvswctl = I915_READ16(MEMSWCTL);
6630 if (rgvswctl & MEMCTL_CMD_STS) {
6631 DRM_DEBUG("gpu busy, RCS change rejected\n");
6632 return false; /* still busy with another command */
6633 }
6634
6635 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6636 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6637 I915_WRITE16(MEMSWCTL, rgvswctl);
6638 POSTING_READ16(MEMSWCTL);
6639
6640 rgvswctl |= MEMCTL_CMD_STS;
6641 I915_WRITE16(MEMSWCTL, rgvswctl);
6642
6643 return true;
6644}
6645
Jesse Barnesf97108d2010-01-29 11:27:07 -08006646void ironlake_enable_drps(struct drm_device *dev)
6647{
6648 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006649 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006650 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08006651
Jesse Barnesea056c12010-09-10 10:02:13 -07006652 /* Enable temp reporting */
6653 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6654 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6655
Jesse Barnesf97108d2010-01-29 11:27:07 -08006656 /* 100ms RC evaluation intervals */
6657 I915_WRITE(RCUPEI, 100000);
6658 I915_WRITE(RCDNEI, 100000);
6659
6660 /* Set max/min thresholds to 90ms and 80ms respectively */
6661 I915_WRITE(RCBMAXAVG, 90000);
6662 I915_WRITE(RCBMINAVG, 80000);
6663
6664 I915_WRITE(MEMIHYST, 1);
6665
6666 /* Set up min, max, and cur for interrupt handling */
6667 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6668 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6669 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6670 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006671
Jesse Barnesf97108d2010-01-29 11:27:07 -08006672 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6673 PXVFREQ_PX_SHIFT;
6674
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006675 dev_priv->fmax = fmax; /* IPS callback will increase this */
Jesse Barnes7648fa92010-05-20 14:28:11 -07006676 dev_priv->fstart = fstart;
6677
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006678 dev_priv->max_delay = fstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08006679 dev_priv->min_delay = fmin;
6680 dev_priv->cur_delay = fstart;
6681
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07006682 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6683 fmax, fmin, fstart);
Jesse Barnes7648fa92010-05-20 14:28:11 -07006684
Jesse Barnesf97108d2010-01-29 11:27:07 -08006685 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6686
6687 /*
6688 * Interrupts will be enabled in ironlake_irq_postinstall
6689 */
6690
6691 I915_WRITE(VIDSTART, vstart);
6692 POSTING_READ(VIDSTART);
6693
6694 rgvmodectl |= MEMMODE_SWMODE_EN;
6695 I915_WRITE(MEMMODECTL, rgvmodectl);
6696
Chris Wilson481b6af2010-08-23 17:43:35 +01006697 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Chris Wilson913d8d12010-08-07 11:01:35 +01006698 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08006699 msleep(1);
6700
Jesse Barnes7648fa92010-05-20 14:28:11 -07006701 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006702
Jesse Barnes7648fa92010-05-20 14:28:11 -07006703 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6704 I915_READ(0x112e0);
6705 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6706 dev_priv->last_count2 = I915_READ(0x112f4);
6707 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006708}
6709
6710void ironlake_disable_drps(struct drm_device *dev)
6711{
6712 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07006713 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006714
6715 /* Ack interrupts, disable EFC interrupt */
6716 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6717 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6718 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6719 I915_WRITE(DEIIR, DE_PCU_EVENT);
6720 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6721
6722 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07006723 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08006724 msleep(1);
6725 rgvswctl |= MEMCTL_CMD_STS;
6726 I915_WRITE(MEMSWCTL, rgvswctl);
6727 msleep(1);
6728
6729}
6730
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006731void gen6_set_rps(struct drm_device *dev, u8 val)
6732{
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 u32 swreq;
6735
6736 swreq = (val & 0x3ff) << 25;
6737 I915_WRITE(GEN6_RPNSWREQ, swreq);
6738}
6739
6740void gen6_disable_rps(struct drm_device *dev)
6741{
6742 struct drm_i915_private *dev_priv = dev->dev_private;
6743
6744 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6745 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6746 I915_WRITE(GEN6_PMIER, 0);
6747 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6748}
6749
Jesse Barnes7648fa92010-05-20 14:28:11 -07006750static unsigned long intel_pxfreq(u32 vidfreq)
6751{
6752 unsigned long freq;
6753 int div = (vidfreq & 0x3f0000) >> 16;
6754 int post = (vidfreq & 0x3000) >> 12;
6755 int pre = (vidfreq & 0x7);
6756
6757 if (!pre)
6758 return 0;
6759
6760 freq = ((div * 133333) / ((1<<post) * pre));
6761
6762 return freq;
6763}
6764
6765void intel_init_emon(struct drm_device *dev)
6766{
6767 struct drm_i915_private *dev_priv = dev->dev_private;
6768 u32 lcfuse;
6769 u8 pxw[16];
6770 int i;
6771
6772 /* Disable to program */
6773 I915_WRITE(ECR, 0);
6774 POSTING_READ(ECR);
6775
6776 /* Program energy weights for various events */
6777 I915_WRITE(SDEW, 0x15040d00);
6778 I915_WRITE(CSIEW0, 0x007f0000);
6779 I915_WRITE(CSIEW1, 0x1e220004);
6780 I915_WRITE(CSIEW2, 0x04000004);
6781
6782 for (i = 0; i < 5; i++)
6783 I915_WRITE(PEW + (i * 4), 0);
6784 for (i = 0; i < 3; i++)
6785 I915_WRITE(DEW + (i * 4), 0);
6786
6787 /* Program P-state weights to account for frequency power adjustment */
6788 for (i = 0; i < 16; i++) {
6789 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6790 unsigned long freq = intel_pxfreq(pxvidfreq);
6791 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6792 PXVFREQ_PX_SHIFT;
6793 unsigned long val;
6794
6795 val = vid * vid;
6796 val *= (freq / 1000);
6797 val *= 255;
6798 val /= (127*127*900);
6799 if (val > 0xff)
6800 DRM_ERROR("bad pxval: %ld\n", val);
6801 pxw[i] = val;
6802 }
6803 /* Render standby states get 0 weight */
6804 pxw[14] = 0;
6805 pxw[15] = 0;
6806
6807 for (i = 0; i < 4; i++) {
6808 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6809 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6810 I915_WRITE(PXW + (i * 4), val);
6811 }
6812
6813 /* Adjust magic regs to magic values (more experimental results) */
6814 I915_WRITE(OGW0, 0);
6815 I915_WRITE(OGW1, 0);
6816 I915_WRITE(EG0, 0x00007f00);
6817 I915_WRITE(EG1, 0x0000000e);
6818 I915_WRITE(EG2, 0x000e0000);
6819 I915_WRITE(EG3, 0x68000300);
6820 I915_WRITE(EG4, 0x42000000);
6821 I915_WRITE(EG5, 0x00140031);
6822 I915_WRITE(EG6, 0);
6823 I915_WRITE(EG7, 0);
6824
6825 for (i = 0; i < 8; i++)
6826 I915_WRITE(PXWL + (i * 4), 0);
6827
6828 /* Enable PMON + select events */
6829 I915_WRITE(ECR, 0x80000019);
6830
6831 lcfuse = I915_READ(LCFUSE02);
6832
6833 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6834}
6835
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006836void gen6_enable_rps(struct drm_i915_private *dev_priv)
Chris Wilson8fd26852010-12-08 18:40:43 +00006837{
Jesse Barnesa6044e22010-12-20 11:34:20 -08006838 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6839 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6840 u32 pcu_mbox;
6841 int cur_freq, min_freq, max_freq;
Chris Wilson8fd26852010-12-08 18:40:43 +00006842 int i;
6843
6844 /* Here begins a magic sequence of register writes to enable
6845 * auto-downclocking.
6846 *
6847 * Perhaps there might be some value in exposing these to
6848 * userspace...
6849 */
6850 I915_WRITE(GEN6_RC_STATE, 0);
Chris Wilson91355832011-03-04 19:22:40 +00006851 __gen6_gt_force_wake_get(dev_priv);
Chris Wilson8fd26852010-12-08 18:40:43 +00006852
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006853 /* disable the counters and set deterministic thresholds */
Chris Wilson8fd26852010-12-08 18:40:43 +00006854 I915_WRITE(GEN6_RC_CONTROL, 0);
6855
6856 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6858 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6859 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6860 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6861
6862 for (i = 0; i < I915_NUM_RINGS; i++)
6863 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6864
6865 I915_WRITE(GEN6_RC_SLEEP, 0);
6866 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6867 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6868 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6869 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6870
6871 I915_WRITE(GEN6_RC_CONTROL,
6872 GEN6_RC_CTL_RC6p_ENABLE |
6873 GEN6_RC_CTL_RC6_ENABLE |
Chris Wilson9c3d2f72010-12-17 10:54:26 +00006874 GEN6_RC_CTL_EI_MODE(1) |
Chris Wilson8fd26852010-12-08 18:40:43 +00006875 GEN6_RC_CTL_HW_ENABLE);
6876
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006877 I915_WRITE(GEN6_RPNSWREQ,
Chris Wilson8fd26852010-12-08 18:40:43 +00006878 GEN6_FREQUENCY(10) |
6879 GEN6_OFFSET(0) |
6880 GEN6_AGGRESSIVE_TURBO);
6881 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6882 GEN6_FREQUENCY(12));
6883
6884 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6885 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6886 18 << 24 |
6887 6 << 16);
Jesse Barnesccab5c82011-01-18 15:49:25 -08006888 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
6889 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00006890 I915_WRITE(GEN6_RP_UP_EI, 100000);
Jesse Barnesccab5c82011-01-18 15:49:25 -08006891 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00006892 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6893 I915_WRITE(GEN6_RP_CONTROL,
6894 GEN6_RP_MEDIA_TURBO |
6895 GEN6_RP_USE_NORMAL_FREQ |
6896 GEN6_RP_MEDIA_IS_GFX |
6897 GEN6_RP_ENABLE |
Jesse Barnesccab5c82011-01-18 15:49:25 -08006898 GEN6_RP_UP_BUSY_AVG |
6899 GEN6_RP_DOWN_IDLE_CONT);
Chris Wilson8fd26852010-12-08 18:40:43 +00006900
6901 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6902 500))
6903 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6904
6905 I915_WRITE(GEN6_PCODE_DATA, 0);
6906 I915_WRITE(GEN6_PCODE_MAILBOX,
6907 GEN6_PCODE_READY |
6908 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6910 500))
6911 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6912
Jesse Barnesa6044e22010-12-20 11:34:20 -08006913 min_freq = (rp_state_cap & 0xff0000) >> 16;
6914 max_freq = rp_state_cap & 0xff;
6915 cur_freq = (gt_perf_status & 0xff00) >> 8;
6916
6917 /* Check for overclock support */
6918 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6919 500))
6920 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6921 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6922 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6923 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6924 500))
6925 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6926 if (pcu_mbox & (1<<31)) { /* OC supported */
6927 max_freq = pcu_mbox & 0xff;
6928 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6929 }
6930
6931 /* In units of 100MHz */
6932 dev_priv->max_delay = max_freq;
6933 dev_priv->min_delay = min_freq;
6934 dev_priv->cur_delay = cur_freq;
6935
Chris Wilson8fd26852010-12-08 18:40:43 +00006936 /* requires MSI enabled */
6937 I915_WRITE(GEN6_PMIER,
6938 GEN6_PM_MBOX_EVENT |
6939 GEN6_PM_THERMAL_EVENT |
6940 GEN6_PM_RP_DOWN_TIMEOUT |
6941 GEN6_PM_RP_UP_THRESHOLD |
6942 GEN6_PM_RP_DOWN_THRESHOLD |
6943 GEN6_PM_RP_UP_EI_EXPIRED |
6944 GEN6_PM_RP_DOWN_EI_EXPIRED);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08006945 I915_WRITE(GEN6_PMIMR, 0);
6946 /* enable all PM interrupts */
6947 I915_WRITE(GEN6_PMINTRMSK, 0);
Chris Wilson8fd26852010-12-08 18:40:43 +00006948
Chris Wilson91355832011-03-04 19:22:40 +00006949 __gen6_gt_force_wake_put(dev_priv);
Chris Wilson8fd26852010-12-08 18:40:43 +00006950}
6951
Chris Wilson0cdab212010-12-05 17:27:06 +00006952void intel_enable_clock_gating(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07006953{
6954 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006955 int pipe;
Jesse Barnes652c3932009-08-17 13:31:43 -07006956
6957 /*
6958 * Disable clock gating reported to work incorrectly according to the
6959 * specs, but enable as much else as we can.
6960 */
Eric Anholtbad720f2009-10-22 16:11:14 -07006961 if (HAS_PCH_SPLIT(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07006962 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6963
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006964 if (IS_GEN5(dev)) {
Eric Anholt8956c8b2010-03-18 13:21:14 -07006965 /* Required for FBC */
Jesse Barnes1ffa3252011-01-17 13:35:57 -08006966 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6967 DPFCRUNIT_CLOCK_GATE_DISABLE |
6968 DPFDUNIT_CLOCK_GATE_DISABLE;
Eric Anholt8956c8b2010-03-18 13:21:14 -07006969 /* Required for CxSR */
6970 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6971
6972 I915_WRITE(PCH_3DCGDIS0,
6973 MARIUNIT_CLOCK_GATE_DISABLE |
6974 SVSMUNIT_CLOCK_GATE_DISABLE);
Eric Anholt06f37752010-12-14 10:06:46 -08006975 I915_WRITE(PCH_3DCGDIS1,
6976 VFMUNIT_CLOCK_GATE_DISABLE);
Eric Anholt8956c8b2010-03-18 13:21:14 -07006977 }
6978
6979 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006980
6981 /*
Jesse Barnes382b0932010-10-07 16:01:25 -07006982 * On Ibex Peak and Cougar Point, we need to disable clock
6983 * gating for the panel power sequencer or it will fail to
6984 * start up when no ports are active.
6985 */
6986 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6987
6988 /*
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006989 * According to the spec the following bits should be set in
6990 * order to enable memory self-refresh
6991 * The bit 22/21 of 0x42004
6992 * The bit 5 of 0x42020
6993 * The bit 15 of 0x45000
6994 */
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006995 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006996 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6997 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6998 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6999 I915_WRITE(ILK_DSPCLK_GATE,
7000 (I915_READ(ILK_DSPCLK_GATE) |
7001 ILK_DPARB_CLK_GATE));
7002 I915_WRITE(DISP_ARB_CTL,
7003 (I915_READ(DISP_ARB_CTL) |
7004 DISP_FBC_WM_DIS));
Yuanhan Liu13982612010-12-15 15:42:31 +08007005 I915_WRITE(WM3_LP_ILK, 0);
7006 I915_WRITE(WM2_LP_ILK, 0);
7007 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007008 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08007009 /*
7010 * Based on the document from hardware guys the following bits
7011 * should be set unconditionally in order to enable FBC.
7012 * The bit 22 of 0x42000
7013 * The bit 22 of 0x42004
7014 * The bit 7,8,9 of 0x42020.
7015 */
7016 if (IS_IRONLAKE_M(dev)) {
7017 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7018 I915_READ(ILK_DISPLAY_CHICKEN1) |
7019 ILK_FBCQ_DIS);
7020 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7021 I915_READ(ILK_DISPLAY_CHICKEN2) |
7022 ILK_DPARB_GATE);
7023 I915_WRITE(ILK_DSPCLK_GATE,
7024 I915_READ(ILK_DSPCLK_GATE) |
7025 ILK_DPFC_DIS1 |
7026 ILK_DPFC_DIS2 |
7027 ILK_CLK_FBC);
7028 }
Eric Anholtde6e2ea2010-11-06 14:53:32 -07007029
Eric Anholt67e92af2010-11-06 14:53:33 -07007030 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7031 I915_READ(ILK_DISPLAY_CHICKEN2) |
7032 ILK_ELPIN_409_SELECT);
7033
Eric Anholtde6e2ea2010-11-06 14:53:32 -07007034 if (IS_GEN5(dev)) {
7035 I915_WRITE(_3D_CHICKEN2,
7036 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7037 _3D_CHICKEN2_WM_READ_PIPELINED);
7038 }
Chris Wilson8fd26852010-12-08 18:40:43 +00007039
Yuanhan Liu13982612010-12-15 15:42:31 +08007040 if (IS_GEN6(dev)) {
7041 I915_WRITE(WM3_LP_ILK, 0);
7042 I915_WRITE(WM2_LP_ILK, 0);
7043 I915_WRITE(WM1_LP_ILK, 0);
7044
7045 /*
7046 * According to the spec the following bits should be
7047 * set in order to enable memory self-refresh and fbc:
7048 * The bit21 and bit22 of 0x42000
7049 * The bit21 and bit22 of 0x42004
7050 * The bit5 and bit7 of 0x42020
7051 * The bit14 of 0x70180
7052 * The bit14 of 0x71180
7053 */
7054 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7055 I915_READ(ILK_DISPLAY_CHICKEN1) |
7056 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7057 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7058 I915_READ(ILK_DISPLAY_CHICKEN2) |
7059 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7060 I915_WRITE(ILK_DSPCLK_GATE,
7061 I915_READ(ILK_DSPCLK_GATE) |
7062 ILK_DPARB_CLK_GATE |
7063 ILK_DPFD_CLK_GATE);
7064
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007065 for_each_pipe(pipe)
7066 I915_WRITE(DSPCNTR(pipe),
7067 I915_READ(DSPCNTR(pipe)) |
7068 DISPPLANE_TRICKLE_FEED_DISABLE);
Yuanhan Liu13982612010-12-15 15:42:31 +08007069 }
Zhenyu Wangc03342f2009-09-29 11:01:23 +08007070 } else if (IS_G4X(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007071 uint32_t dspclk_gate;
7072 I915_WRITE(RENCLK_GATE_D1, 0);
7073 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7074 GS_UNIT_CLOCK_GATE_DISABLE |
7075 CL_UNIT_CLOCK_GATE_DISABLE);
7076 I915_WRITE(RAMCLK_GATE_D, 0);
7077 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7078 OVRUNIT_CLOCK_GATE_DISABLE |
7079 OVCUNIT_CLOCK_GATE_DISABLE;
7080 if (IS_GM45(dev))
7081 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7082 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007083 } else if (IS_CRESTLINE(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007084 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7085 I915_WRITE(RENCLK_GATE_D2, 0);
7086 I915_WRITE(DSPCLK_GATE_D, 0);
7087 I915_WRITE(RAMCLK_GATE_D, 0);
7088 I915_WRITE16(DEUC, 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007089 } else if (IS_BROADWATER(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007090 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7091 I965_RCC_CLOCK_GATE_DISABLE |
7092 I965_RCPB_CLOCK_GATE_DISABLE |
7093 I965_ISC_CLOCK_GATE_DISABLE |
7094 I965_FBC_CLOCK_GATE_DISABLE);
7095 I915_WRITE(RENCLK_GATE_D2, 0);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007096 } else if (IS_GEN3(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007097 u32 dstate = I915_READ(D_STATE);
7098
7099 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7100 DSTATE_DOT_CLOCK_GATING;
7101 I915_WRITE(D_STATE, dstate);
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02007102 } else if (IS_I85X(dev) || IS_I865G(dev)) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007103 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7104 } else if (IS_I830(dev)) {
7105 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7106 }
7107}
7108
Chris Wilsonac668082011-02-09 16:15:32 +00007109static void ironlake_teardown_rc6(struct drm_device *dev)
Chris Wilson0cdab212010-12-05 17:27:06 +00007110{
7111 struct drm_i915_private *dev_priv = dev->dev_private;
7112
7113 if (dev_priv->renderctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00007114 i915_gem_object_unpin(dev_priv->renderctx);
7115 drm_gem_object_unreference(&dev_priv->renderctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00007116 dev_priv->renderctx = NULL;
7117 }
7118
7119 if (dev_priv->pwrctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00007120 i915_gem_object_unpin(dev_priv->pwrctx);
7121 drm_gem_object_unreference(&dev_priv->pwrctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00007122 dev_priv->pwrctx = NULL;
7123 }
7124}
7125
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007126static void ironlake_disable_rc6(struct drm_device *dev)
7127{
7128 struct drm_i915_private *dev_priv = dev->dev_private;
7129
Chris Wilsonac668082011-02-09 16:15:32 +00007130 if (I915_READ(PWRCTXA)) {
7131 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7132 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7133 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7134 50);
7135
7136 I915_WRITE(PWRCTXA, 0);
7137 POSTING_READ(PWRCTXA);
7138
7139 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7140 POSTING_READ(RSTDBYCTL);
7141 }
7142
Chris Wilson99507302011-02-24 09:42:52 +00007143 ironlake_teardown_rc6(dev);
Chris Wilsonac668082011-02-09 16:15:32 +00007144}
7145
7146static int ironlake_setup_rc6(struct drm_device *dev)
7147{
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7149
7150 if (dev_priv->renderctx == NULL)
7151 dev_priv->renderctx = intel_alloc_context_page(dev);
7152 if (!dev_priv->renderctx)
7153 return -ENOMEM;
7154
7155 if (dev_priv->pwrctx == NULL)
7156 dev_priv->pwrctx = intel_alloc_context_page(dev);
7157 if (!dev_priv->pwrctx) {
7158 ironlake_teardown_rc6(dev);
7159 return -ENOMEM;
7160 }
7161
7162 return 0;
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007163}
7164
7165void ironlake_enable_rc6(struct drm_device *dev)
7166{
7167 struct drm_i915_private *dev_priv = dev->dev_private;
7168 int ret;
7169
Chris Wilsonac668082011-02-09 16:15:32 +00007170 /* rc6 disabled by default due to repeated reports of hanging during
7171 * boot and resume.
7172 */
7173 if (!i915_enable_rc6)
7174 return;
7175
7176 ret = ironlake_setup_rc6(dev);
7177 if (ret)
7178 return;
7179
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007180 /*
7181 * GPU can automatically power down the render unit if given a page
7182 * to save state.
7183 */
7184 ret = BEGIN_LP_RING(6);
7185 if (ret) {
Chris Wilsonac668082011-02-09 16:15:32 +00007186 ironlake_teardown_rc6(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007187 return;
7188 }
Chris Wilsonac668082011-02-09 16:15:32 +00007189
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007190 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7191 OUT_RING(MI_SET_CONTEXT);
7192 OUT_RING(dev_priv->renderctx->gtt_offset |
7193 MI_MM_SPACE_GTT |
7194 MI_SAVE_EXT_STATE_EN |
7195 MI_RESTORE_EXT_STATE_EN |
7196 MI_RESTORE_INHIBIT);
7197 OUT_RING(MI_SUSPEND_FLUSH);
7198 OUT_RING(MI_NOOP);
7199 OUT_RING(MI_FLUSH);
7200 ADVANCE_LP_RING();
7201
7202 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7203 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7204}
7205
Chris Wilsonac668082011-02-09 16:15:32 +00007206
Jesse Barnese70236a2009-09-21 10:42:27 -07007207/* Set up chip specific display functions */
7208static void intel_init_display(struct drm_device *dev)
7209{
7210 struct drm_i915_private *dev_priv = dev->dev_private;
7211
7212 /* We always want a DPMS function */
Eric Anholtbad720f2009-10-22 16:11:14 -07007213 if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007214 dev_priv->display.dpms = ironlake_crtc_dpms;
Jesse Barnese70236a2009-09-21 10:42:27 -07007215 else
7216 dev_priv->display.dpms = i9xx_crtc_dpms;
7217
Adam Jacksonee5382a2010-04-23 11:17:39 -04007218 if (I915_HAS_FBC(dev)) {
Yuanhan Liu9c04f012010-12-15 15:42:32 +08007219 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08007220 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7221 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7222 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7223 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07007224 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7225 dev_priv->display.enable_fbc = g4x_enable_fbc;
7226 dev_priv->display.disable_fbc = g4x_disable_fbc;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007227 } else if (IS_CRESTLINE(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007228 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7229 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7230 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7231 }
Jesse Barnes74dff282009-09-14 15:39:40 -07007232 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07007233 }
7234
7235 /* Returns the core display clock speed */
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007236 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07007237 dev_priv->display.get_display_clock_speed =
7238 i945_get_display_clock_speed;
7239 else if (IS_I915G(dev))
7240 dev_priv->display.get_display_clock_speed =
7241 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05007242 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007243 dev_priv->display.get_display_clock_speed =
7244 i9xx_misc_get_display_clock_speed;
7245 else if (IS_I915GM(dev))
7246 dev_priv->display.get_display_clock_speed =
7247 i915gm_get_display_clock_speed;
7248 else if (IS_I865G(dev))
7249 dev_priv->display.get_display_clock_speed =
7250 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02007251 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007252 dev_priv->display.get_display_clock_speed =
7253 i855_get_display_clock_speed;
7254 else /* 852, 830 */
7255 dev_priv->display.get_display_clock_speed =
7256 i830_get_display_clock_speed;
7257
7258 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007259 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01007260 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007261 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7262 dev_priv->display.update_wm = ironlake_update_wm;
7263 else {
7264 DRM_DEBUG_KMS("Failed to get proper latency. "
7265 "Disable CxSR\n");
7266 dev_priv->display.update_wm = NULL;
7267 }
Yuanhan Liu13982612010-12-15 15:42:31 +08007268 } else if (IS_GEN6(dev)) {
7269 if (SNB_READ_WM0_LATENCY()) {
7270 dev_priv->display.update_wm = sandybridge_update_wm;
7271 } else {
7272 DRM_DEBUG_KMS("Failed to read display plane latency. "
7273 "Disable CxSR\n");
7274 dev_priv->display.update_wm = NULL;
7275 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08007276 } else
7277 dev_priv->display.update_wm = NULL;
7278 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08007279 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08007280 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08007281 dev_priv->fsb_freq,
7282 dev_priv->mem_freq)) {
7283 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08007284 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08007285 "disabling CxSR\n",
Li Peng95534262010-05-18 18:58:44 +08007286 (dev_priv->is_ddr3 == 1) ? "3": "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08007287 dev_priv->fsb_freq, dev_priv->mem_freq);
7288 /* Disable CxSR and never update its watermark again */
7289 pineview_disable_cxsr(dev);
7290 dev_priv->display.update_wm = NULL;
7291 } else
7292 dev_priv->display.update_wm = pineview_update_wm;
7293 } else if (IS_G4X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007294 dev_priv->display.update_wm = g4x_update_wm;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007295 else if (IS_GEN4(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007296 dev_priv->display.update_wm = i965_update_wm;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007297 else if (IS_GEN3(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07007298 dev_priv->display.update_wm = i9xx_update_wm;
7299 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04007300 } else if (IS_I85X(dev)) {
7301 dev_priv->display.update_wm = i9xx_update_wm;
7302 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07007303 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04007304 dev_priv->display.update_wm = i830_update_wm;
7305 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07007306 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7307 else
7308 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07007309 }
7310}
7311
Jesse Barnesb690e962010-07-19 13:53:12 -07007312/*
7313 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7314 * resume, or other times. This quirk makes sure that's the case for
7315 * affected systems.
7316 */
7317static void quirk_pipea_force (struct drm_device *dev)
7318{
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320
7321 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7322 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7323}
7324
7325struct intel_quirk {
7326 int device;
7327 int subsystem_vendor;
7328 int subsystem_device;
7329 void (*hook)(struct drm_device *dev);
7330};
7331
7332struct intel_quirk intel_quirks[] = {
7333 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7334 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7335 /* HP Mini needs pipe A force quirk (LP: #322104) */
7336 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7337
7338 /* Thinkpad R31 needs pipe A force quirk */
7339 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7340 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7341 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7342
7343 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7344 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7345 /* ThinkPad X40 needs pipe A force quirk */
7346
7347 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7348 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7349
7350 /* 855 & before need to leave pipe A & dpll A up */
7351 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7352 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7353};
7354
7355static void intel_init_quirks(struct drm_device *dev)
7356{
7357 struct pci_dev *d = dev->pdev;
7358 int i;
7359
7360 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7361 struct intel_quirk *q = &intel_quirks[i];
7362
7363 if (d->device == q->device &&
7364 (d->subsystem_vendor == q->subsystem_vendor ||
7365 q->subsystem_vendor == PCI_ANY_ID) &&
7366 (d->subsystem_device == q->subsystem_device ||
7367 q->subsystem_device == PCI_ANY_ID))
7368 q->hook(dev);
7369 }
7370}
7371
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007372/* Disable the VGA plane that we never use */
7373static void i915_disable_vga(struct drm_device *dev)
7374{
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 u8 sr1;
7377 u32 vga_reg;
7378
7379 if (HAS_PCH_SPLIT(dev))
7380 vga_reg = CPU_VGACNTRL;
7381 else
7382 vga_reg = VGACNTRL;
7383
7384 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7385 outb(1, VGA_SR_INDEX);
7386 sr1 = inb(VGA_SR_DATA);
7387 outb(sr1 | 1<<5, VGA_SR_DATA);
7388 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7389 udelay(300);
7390
7391 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7392 POSTING_READ(vga_reg);
7393}
7394
Jesse Barnes79e53942008-11-07 14:24:08 -08007395void intel_modeset_init(struct drm_device *dev)
7396{
Jesse Barnes652c3932009-08-17 13:31:43 -07007397 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007398 int i;
7399
7400 drm_mode_config_init(dev);
7401
7402 dev->mode_config.min_width = 0;
7403 dev->mode_config.min_height = 0;
7404
7405 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7406
Jesse Barnesb690e962010-07-19 13:53:12 -07007407 intel_init_quirks(dev);
7408
Jesse Barnese70236a2009-09-21 10:42:27 -07007409 intel_init_display(dev);
7410
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007411 if (IS_GEN2(dev)) {
7412 dev->mode_config.max_width = 2048;
7413 dev->mode_config.max_height = 2048;
7414 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07007415 dev->mode_config.max_width = 4096;
7416 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08007417 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007418 dev->mode_config.max_width = 8192;
7419 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08007420 }
Chris Wilson35c30472010-12-22 14:07:12 +00007421 dev->mode_config.fb_base = dev->agp->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08007422
Zhao Yakui28c97732009-10-09 11:39:41 +08007423 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10007424 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08007425
Dave Airliea3524f12010-06-06 18:59:41 +10007426 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007427 intel_crtc_init(dev, i);
7428 }
7429
7430 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007431
Chris Wilson0cdab212010-12-05 17:27:06 +00007432 intel_enable_clock_gating(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007433
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007434 /* Just disable it once at startup */
7435 i915_disable_vga(dev);
7436
Jesse Barnes7648fa92010-05-20 14:28:11 -07007437 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08007438 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07007439 intel_init_emon(dev);
7440 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08007441
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007442 if (IS_GEN6(dev))
7443 gen6_enable_rps(dev_priv);
7444
Chris Wilsonac668082011-02-09 16:15:32 +00007445 if (IS_IRONLAKE_M(dev))
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007446 ironlake_enable_rc6(dev);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007447
Jesse Barnes652c3932009-08-17 13:31:43 -07007448 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7449 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7450 (unsigned long)dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02007451
7452 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007453}
7454
7455void intel_modeset_cleanup(struct drm_device *dev)
7456{
Jesse Barnes652c3932009-08-17 13:31:43 -07007457 struct drm_i915_private *dev_priv = dev->dev_private;
7458 struct drm_crtc *crtc;
7459 struct intel_crtc *intel_crtc;
7460
Keith Packardf87ea762010-10-03 19:36:26 -07007461 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007462 mutex_lock(&dev->struct_mutex);
7463
Jesse Barnes723bfd72010-10-07 16:01:13 -07007464 intel_unregister_dsm_handler();
7465
7466
Jesse Barnes652c3932009-08-17 13:31:43 -07007467 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7468 /* Skip inactive CRTCs */
7469 if (!crtc->fb)
7470 continue;
7471
7472 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02007473 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007474 }
7475
Jesse Barnese70236a2009-09-21 10:42:27 -07007476 if (dev_priv->display.disable_fbc)
7477 dev_priv->display.disable_fbc(dev);
7478
Jesse Barnesf97108d2010-01-29 11:27:07 -08007479 if (IS_IRONLAKE_M(dev))
7480 ironlake_disable_drps(dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08007481 if (IS_GEN6(dev))
7482 gen6_disable_rps(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08007483
Jesse Barnesd5bb0812011-01-05 12:01:26 -08007484 if (IS_IRONLAKE_M(dev))
7485 ironlake_disable_rc6(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00007486
Kristian Høgsberg69341a52009-11-11 12:19:17 -05007487 mutex_unlock(&dev->struct_mutex);
7488
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007489 /* Disable the irq before mode object teardown, for the irq might
7490 * enqueue unpin/hotplug work. */
7491 drm_irq_uninstall(dev);
7492 cancel_work_sync(&dev_priv->hotplug_work);
7493
Daniel Vetter3dec0092010-08-20 21:40:52 +02007494 /* Shut off idle work before the crtcs get freed. */
7495 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7496 intel_crtc = to_intel_crtc(crtc);
7497 del_timer_sync(&intel_crtc->idle_timer);
7498 }
7499 del_timer_sync(&dev_priv->idle_timer);
7500 cancel_work_sync(&dev_priv->idle_work);
7501
Jesse Barnes79e53942008-11-07 14:24:08 -08007502 drm_mode_config_cleanup(dev);
7503}
7504
Dave Airlie28d52042009-09-21 14:33:58 +10007505/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08007506 * Return which encoder is currently attached for connector.
7507 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01007508struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08007509{
Chris Wilsondf0e9242010-09-09 16:20:55 +01007510 return &intel_attached_encoder(connector)->base;
7511}
Jesse Barnes79e53942008-11-07 14:24:08 -08007512
Chris Wilsondf0e9242010-09-09 16:20:55 +01007513void intel_connector_attach_encoder(struct intel_connector *connector,
7514 struct intel_encoder *encoder)
7515{
7516 connector->encoder = encoder;
7517 drm_mode_connector_attach_encoder(&connector->base,
7518 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007519}
Dave Airlie28d52042009-09-21 14:33:58 +10007520
7521/*
7522 * set vga decode state - true == enable VGA decode
7523 */
7524int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7525{
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 u16 gmch_ctrl;
7528
7529 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7530 if (state)
7531 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7532 else
7533 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7534 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7535 return 0;
7536}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007537
7538#ifdef CONFIG_DEBUG_FS
7539#include <linux/seq_file.h>
7540
7541struct intel_display_error_state {
7542 struct intel_cursor_error_state {
7543 u32 control;
7544 u32 position;
7545 u32 base;
7546 u32 size;
7547 } cursor[2];
7548
7549 struct intel_pipe_error_state {
7550 u32 conf;
7551 u32 source;
7552
7553 u32 htotal;
7554 u32 hblank;
7555 u32 hsync;
7556 u32 vtotal;
7557 u32 vblank;
7558 u32 vsync;
7559 } pipe[2];
7560
7561 struct intel_plane_error_state {
7562 u32 control;
7563 u32 stride;
7564 u32 size;
7565 u32 pos;
7566 u32 addr;
7567 u32 surface;
7568 u32 tile_offset;
7569 } plane[2];
7570};
7571
7572struct intel_display_error_state *
7573intel_display_capture_error_state(struct drm_device *dev)
7574{
7575 drm_i915_private_t *dev_priv = dev->dev_private;
7576 struct intel_display_error_state *error;
7577 int i;
7578
7579 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7580 if (error == NULL)
7581 return NULL;
7582
7583 for (i = 0; i < 2; i++) {
7584 error->cursor[i].control = I915_READ(CURCNTR(i));
7585 error->cursor[i].position = I915_READ(CURPOS(i));
7586 error->cursor[i].base = I915_READ(CURBASE(i));
7587
7588 error->plane[i].control = I915_READ(DSPCNTR(i));
7589 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7590 error->plane[i].size = I915_READ(DSPSIZE(i));
7591 error->plane[i].pos= I915_READ(DSPPOS(i));
7592 error->plane[i].addr = I915_READ(DSPADDR(i));
7593 if (INTEL_INFO(dev)->gen >= 4) {
7594 error->plane[i].surface = I915_READ(DSPSURF(i));
7595 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7596 }
7597
7598 error->pipe[i].conf = I915_READ(PIPECONF(i));
7599 error->pipe[i].source = I915_READ(PIPESRC(i));
7600 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7601 error->pipe[i].hblank = I915_READ(HBLANK(i));
7602 error->pipe[i].hsync = I915_READ(HSYNC(i));
7603 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7604 error->pipe[i].vblank = I915_READ(VBLANK(i));
7605 error->pipe[i].vsync = I915_READ(VSYNC(i));
7606 }
7607
7608 return error;
7609}
7610
7611void
7612intel_display_print_error_state(struct seq_file *m,
7613 struct drm_device *dev,
7614 struct intel_display_error_state *error)
7615{
7616 int i;
7617
7618 for (i = 0; i < 2; i++) {
7619 seq_printf(m, "Pipe [%d]:\n", i);
7620 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7621 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7622 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7623 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7624 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7625 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7626 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7627 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7628
7629 seq_printf(m, "Plane [%d]:\n", i);
7630 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7631 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7632 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7633 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7634 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7635 if (INTEL_INFO(dev)->gen >= 4) {
7636 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7637 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7638 }
7639
7640 seq_printf(m, "Cursor [%d]:\n", i);
7641 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7642 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7643 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7644 }
7645}
7646#endif