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ths5fafdf22007-09-16 21:08:06 +00001/*
pbrook502a5392006-05-13 16:11:23 +00002 * ARM Versatile/PB PCI host controller
3 *
Paul Brook0027b062009-05-14 22:35:08 +01004 * Copyright (c) 2006-2009 CodeSourcery.
pbrook502a5392006-05-13 16:11:23 +00005 * Written by Paul Brook
6 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10007 * This code is licensed under the LGPL.
pbrook502a5392006-05-13 16:11:23 +00008 */
9
Paul Brook0027b062009-05-14 22:35:08 +010010#include "sysbus.h"
pbrook87ecb682007-11-17 17:14:51 +000011#include "pci.h"
Isaku Yamahatab6243d92009-11-12 14:58:30 +090012#include "pci_host.h"
Avi Kivity1e391012011-07-26 14:26:19 +030013#include "exec-memory.h"
Paul Brook0027b062009-05-14 22:35:08 +010014
15typedef struct {
16 SysBusDevice busdev;
17 qemu_irq irq[4];
18 int realview;
Avi Kivity45de0942011-08-15 17:17:32 +030019 MemoryRegion mem_config;
20 MemoryRegion mem_config2;
21 MemoryRegion isa;
Paul Brook0027b062009-05-14 22:35:08 +010022} PCIVPBState;
pbrook502a5392006-05-13 16:11:23 +000023
Anthony Liguoric227f092009-10-01 16:12:16 -050024static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
pbrook502a5392006-05-13 16:11:23 +000025{
pbrook80b3ada2006-09-24 17:01:44 +000026 return addr & 0xffffff;
pbrook502a5392006-05-13 16:11:23 +000027}
28
Avi Kivity45de0942011-08-15 17:17:32 +030029static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
30 uint64_t val, unsigned size)
pbrook502a5392006-05-13 16:11:23 +000031{
Avi Kivity45de0942011-08-15 17:17:32 +030032 pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
pbrook502a5392006-05-13 16:11:23 +000033}
34
Avi Kivity45de0942011-08-15 17:17:32 +030035static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
36 unsigned size)
pbrook502a5392006-05-13 16:11:23 +000037{
38 uint32_t val;
Avi Kivity45de0942011-08-15 17:17:32 +030039 val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
pbrook502a5392006-05-13 16:11:23 +000040 return val;
41}
42
Avi Kivity45de0942011-08-15 17:17:32 +030043static const MemoryRegionOps pci_vpb_config_ops = {
44 .read = pci_vpb_config_read,
45 .write = pci_vpb_config_write,
46 .endianness = DEVICE_NATIVE_ENDIAN,
pbrook502a5392006-05-13 16:11:23 +000047};
48
pbrookd2b59312006-09-24 00:16:34 +000049static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
50{
51 return irq_num;
52}
53
Juan Quintela5d4e84c2009-08-28 15:28:17 +020054static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
pbrook502a5392006-05-13 16:11:23 +000055{
Juan Quintela5d4e84c2009-08-28 15:28:17 +020056 qemu_irq *pic = opaque;
57
Paul Brook97aff482009-05-14 22:35:07 +010058 qemu_set_irq(pic[irq_num], level);
pbrook502a5392006-05-13 16:11:23 +000059}
60
Avi Kivity45de0942011-08-15 17:17:32 +030061
Anthony Liguoric227f092009-10-01 16:12:16 -050062static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
pbrook502a5392006-05-13 16:11:23 +000063{
Paul Brook0027b062009-05-14 22:35:08 +010064 PCIVPBState *s = (PCIVPBState *)dev;
pbrook502a5392006-05-13 16:11:23 +000065 /* Selfconfig area. */
Avi Kivity45de0942011-08-15 17:17:32 +030066 memory_region_add_subregion(get_system_memory(), base + 0x01000000,
67 &s->mem_config);
pbrook502a5392006-05-13 16:11:23 +000068 /* Normal config area. */
Avi Kivity45de0942011-08-15 17:17:32 +030069 memory_region_add_subregion(get_system_memory(), base + 0x02000000,
70 &s->mem_config2);
pbrook502a5392006-05-13 16:11:23 +000071
Paul Brook0027b062009-05-14 22:35:08 +010072 if (s->realview) {
pbrooke69954b2006-09-23 17:40:58 +000073 /* IO memory area. */
Avi Kivity45de0942011-08-15 17:17:32 +030074 memory_region_add_subregion(get_system_memory(), base + 0x03000000,
75 &s->isa);
76 }
77}
78
79static void pci_vpb_unmap(SysBusDevice *dev, target_phys_addr_t base)
80{
81 PCIVPBState *s = (PCIVPBState *)dev;
82 /* Selfconfig area. */
83 memory_region_del_subregion(get_system_memory(), &s->mem_config);
84 /* Normal config area. */
85 memory_region_del_subregion(get_system_memory(), &s->mem_config2);
86
87 if (s->realview) {
88 /* IO memory area. */
89 memory_region_del_subregion(get_system_memory(), &s->isa);
pbrooke69954b2006-09-23 17:40:58 +000090 }
Paul Brook0027b062009-05-14 22:35:08 +010091}
pbrooke69954b2006-09-23 17:40:58 +000092
Gerd Hoffmann81a322d2009-08-14 10:36:05 +020093static int pci_vpb_init(SysBusDevice *dev)
Paul Brook0027b062009-05-14 22:35:08 +010094{
95 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
96 PCIBus *bus;
97 int i;
98
99 for (i = 0; i < 4; i++) {
100 sysbus_init_irq(dev, &s->irq[i]);
101 }
Paul Brook02e2da42009-05-23 00:05:19 +0100102 bus = pci_register_bus(&dev->qdev, "pci",
103 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
Avi Kivityaee97b82011-08-08 16:09:04 +0300104 get_system_memory(), get_system_io(),
Isaku Yamahata520128b2010-06-23 16:15:25 +0900105 PCI_DEVFN(11, 0), 4);
Paul Brook0027b062009-05-14 22:35:08 +0100106
107 /* ??? Register memory space. */
108
Avi Kivity45de0942011-08-15 17:17:32 +0300109 memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
110 "pci-vpb-selfconfig", 0x1000000);
111 memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
112 "pci-vpb-config", 0x1000000);
113 if (s->realview) {
114 isa_mmio_setup(&s->isa, 0x0100000);
115 }
116
117 sysbus_init_mmio_cb2(dev, pci_vpb_map, pci_vpb_unmap);
Paul Brook0027b062009-05-14 22:35:08 +0100118
119 pci_create_simple(bus, -1, "versatile_pci_host");
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200120 return 0;
Paul Brook0027b062009-05-14 22:35:08 +0100121}
122
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200123static int pci_realview_init(SysBusDevice *dev)
Paul Brook0027b062009-05-14 22:35:08 +0100124{
125 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
126 s->realview = 1;
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200127 return pci_vpb_init(dev);
Paul Brook0027b062009-05-14 22:35:08 +0100128}
129
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200130static int versatile_pci_host_init(PCIDevice *d)
Paul Brook0027b062009-05-14 22:35:08 +0100131{
Michael S. Tsirkina408b1d2010-02-08 23:36:02 +0200132 pci_set_word(d->config + PCI_STATUS,
133 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
Michael S. Tsirkin01764fe2010-02-08 23:33:33 +0200134 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200135 return 0;
pbrook502a5392006-05-13 16:11:23 +0000136}
Paul Brook0027b062009-05-14 22:35:08 +0100137
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +0200138static PCIDeviceInfo versatile_pci_host_info = {
139 .qdev.name = "versatile_pci_host",
140 .qdev.size = sizeof(PCIDevice),
141 .init = versatile_pci_host_init,
Isaku Yamahata56fe6402011-05-25 10:58:30 +0900142 .vendor_id = PCI_VENDOR_ID_XILINX,
143 /* Both boards have the same device ID. Oh well. */
144 .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
145 .class_id = PCI_CLASS_PROCESSOR_CO,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +0200146};
147
Paul Brook0027b062009-05-14 22:35:08 +0100148static void versatile_pci_register_devices(void)
149{
150 sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
151 sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
152 pci_realview_init);
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +0200153 pci_qdev_register(&versatile_pci_host_info);
Paul Brook0027b062009-05-14 22:35:08 +0100154}
155
156device_init(versatile_pci_register_devices)