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bellardd19893d2003-06-15 19:58:51 +00001/*
2 * Host code generation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardd19893d2003-06-15 19:58:51 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26#include "config.h"
bellard20543962003-06-15 23:28:43 +000027
bellardaf5ad102004-01-04 23:28:12 +000028#define NO_CPU_IO_DEFS
bellardd3eead22003-09-30 20:59:51 +000029#include "cpu.h"
30#include "exec-all.h"
bellardd19893d2003-06-15 19:58:51 +000031#include "disas.h"
bellard57fec1f2008-02-01 10:50:11 +000032#include "tcg.h"
bellardd19893d2003-06-15 19:58:51 +000033
bellard57fec1f2008-02-01 10:50:11 +000034/* code generation context */
35TCGContext tcg_ctx;
bellardd19893d2003-06-15 19:58:51 +000036
bellardd19893d2003-06-15 19:58:51 +000037uint16_t gen_opc_buf[OPC_BUF_SIZE];
bellard57fec1f2008-02-01 10:50:11 +000038TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
bellardc4687872005-01-03 23:44:44 +000039
40target_ulong gen_opc_pc[OPC_BUF_SIZE];
bellardd19893d2003-06-15 19:58:51 +000041uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
bellardf76af4b2003-06-24 13:21:23 +000042#if defined(TARGET_I386)
43uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
bellarde95c8d52004-09-30 22:22:08 +000044#elif defined(TARGET_SPARC)
bellardc4687872005-01-03 23:44:44 +000045target_ulong gen_opc_npc[OPC_BUF_SIZE];
bellardc3278b72005-03-20 12:43:29 +000046target_ulong gen_opc_jump_pc[2];
ths823029f2007-12-02 06:10:04 +000047#elif defined(TARGET_MIPS) || defined(TARGET_SH4)
bellard30d6cb82005-12-05 19:56:07 +000048uint32_t gen_opc_hflags[OPC_BUF_SIZE];
bellardf76af4b2003-06-24 13:21:23 +000049#endif
bellardd19893d2003-06-15 19:58:51 +000050
bellard58fe2f12004-02-16 22:11:32 +000051int code_copy_enabled = 1;
52
bellard57fec1f2008-02-01 10:50:11 +000053#ifdef CONFIG_PROFILER
54int64_t dyngen_tb_count1;
55int64_t dyngen_tb_count;
56int64_t dyngen_op_count;
57int64_t dyngen_old_op_count;
58int64_t dyngen_tcg_del_op_count;
59int dyngen_op_count_max;
60int64_t dyngen_code_in_len;
61int64_t dyngen_code_out_len;
62int64_t dyngen_interm_time;
63int64_t dyngen_code_time;
64int64_t dyngen_restore_count;
65int64_t dyngen_restore_time;
bellardd19893d2003-06-15 19:58:51 +000066#endif
67
bellard57fec1f2008-02-01 10:50:11 +000068/* XXX: suppress that */
blueswir1d07bde82007-12-11 19:35:45 +000069unsigned long code_gen_max_block_size(void)
70{
71 static unsigned long max;
72
73 if (max == 0) {
74#define DEF(s, n, copy_size) max = copy_size > max? copy_size : max;
bellard57fec1f2008-02-01 10:50:11 +000075#include "tcg-opc.h"
blueswir1d07bde82007-12-11 19:35:45 +000076#undef DEF
77 max *= OPC_MAX_SIZE;
78 }
79
80 return max;
81}
82
bellard57fec1f2008-02-01 10:50:11 +000083void cpu_gen_init(void)
84{
85 tcg_context_init(&tcg_ctx);
86 tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
87 128 * sizeof(long));
88}
89
bellardd19893d2003-06-15 19:58:51 +000090/* return non zero if the very first instruction is invalid so that
ths5fafdf22007-09-16 21:08:06 +000091 the virtual CPU can trigger an exception.
bellardd19893d2003-06-15 19:58:51 +000092
93 '*gen_code_size_ptr' contains the size of the generated code (host
94 code).
95*/
blueswir1d07bde82007-12-11 19:35:45 +000096int cpu_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr)
bellardd19893d2003-06-15 19:58:51 +000097{
bellard57fec1f2008-02-01 10:50:11 +000098 TCGContext *s = &tcg_ctx;
bellardd19893d2003-06-15 19:58:51 +000099 uint8_t *gen_code_buf;
100 int gen_code_size;
bellard57fec1f2008-02-01 10:50:11 +0000101#ifdef CONFIG_PROFILER
102 int64_t ti;
103#endif
104
105#ifdef CONFIG_PROFILER
106 dyngen_tb_count1++; /* includes aborted translations because of
107 exceptions */
108 ti = profile_getclock();
109#endif
110 tcg_func_start(s);
bellardd19893d2003-06-15 19:58:51 +0000111
bellardec6338b2007-11-08 14:25:03 +0000112 if (gen_intermediate_code(env, tb) < 0)
113 return -1;
114
115 /* generate machine code */
bellard57fec1f2008-02-01 10:50:11 +0000116 gen_code_buf = tb->tc_ptr;
bellardec6338b2007-11-08 14:25:03 +0000117 tb->tb_next_offset[0] = 0xffff;
118 tb->tb_next_offset[1] = 0xffff;
bellard57fec1f2008-02-01 10:50:11 +0000119 s->tb_next_offset = tb->tb_next_offset;
bellard4cbb86e2003-09-17 22:53:29 +0000120#ifdef USE_DIRECT_JUMP
bellard57fec1f2008-02-01 10:50:11 +0000121 s->tb_jmp_offset = tb->tb_jmp_offset;
122 s->tb_next = NULL;
bellardec6338b2007-11-08 14:25:03 +0000123 /* the following two entries are optional (only used for string ops) */
bellard57fec1f2008-02-01 10:50:11 +0000124 /* XXX: not used ? */
bellardec6338b2007-11-08 14:25:03 +0000125 tb->tb_jmp_offset[2] = 0xffff;
126 tb->tb_jmp_offset[3] = 0xffff;
bellardd19893d2003-06-15 19:58:51 +0000127#else
bellard57fec1f2008-02-01 10:50:11 +0000128 s->tb_jmp_offset = NULL;
129 s->tb_next = tb->tb_next;
bellardd19893d2003-06-15 19:58:51 +0000130#endif
bellard57fec1f2008-02-01 10:50:11 +0000131
132#ifdef CONFIG_PROFILER
133 dyngen_tb_count++;
134 dyngen_interm_time += profile_getclock() - ti;
135 dyngen_code_time -= profile_getclock();
136#endif
137 gen_code_size = dyngen_code(s, gen_code_buf);
bellardd19893d2003-06-15 19:58:51 +0000138 *gen_code_size_ptr = gen_code_size;
bellard57fec1f2008-02-01 10:50:11 +0000139#ifdef CONFIG_PROFILER
140 dyngen_code_time += profile_getclock();
141 dyngen_code_in_len += tb->size;
142 dyngen_code_out_len += gen_code_size;
143#endif
144
bellardd19893d2003-06-15 19:58:51 +0000145#ifdef DEBUG_DISAS
bellardf193c792004-03-21 17:06:25 +0000146 if (loglevel & CPU_LOG_TB_OUT_ASM) {
bellardd19893d2003-06-15 19:58:51 +0000147 fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
bellardc4687872005-01-03 23:44:44 +0000148 disas(logfile, tb->tc_ptr, *gen_code_size_ptr);
bellardd19893d2003-06-15 19:58:51 +0000149 fprintf(logfile, "\n");
150 fflush(logfile);
151 }
152#endif
153 return 0;
154}
155
ths5fafdf22007-09-16 21:08:06 +0000156/* The cpu state corresponding to 'searched_pc' is restored.
bellardd19893d2003-06-15 19:58:51 +0000157 */
ths5fafdf22007-09-16 21:08:06 +0000158int cpu_restore_state(TranslationBlock *tb,
bellard58fe2f12004-02-16 22:11:32 +0000159 CPUState *env, unsigned long searched_pc,
160 void *puc)
bellardd19893d2003-06-15 19:58:51 +0000161{
bellard57fec1f2008-02-01 10:50:11 +0000162 TCGContext *s = &tcg_ctx;
163 int j;
bellardd19893d2003-06-15 19:58:51 +0000164 unsigned long tc_ptr;
bellard57fec1f2008-02-01 10:50:11 +0000165#ifdef CONFIG_PROFILER
166 int64_t ti;
167#endif
168
169#ifdef CONFIG_PROFILER
170 ti = profile_getclock();
171#endif
172 tcg_func_start(s);
bellardd19893d2003-06-15 19:58:51 +0000173
bellard4c3a88a2003-07-26 12:06:08 +0000174 if (gen_intermediate_code_pc(env, tb) < 0)
bellardd19893d2003-06-15 19:58:51 +0000175 return -1;
ths3b46e622007-09-17 08:09:54 +0000176
bellardd19893d2003-06-15 19:58:51 +0000177 /* find opc index corresponding to search_pc */
178 tc_ptr = (unsigned long)tb->tc_ptr;
179 if (searched_pc < tc_ptr)
180 return -1;
bellard57fec1f2008-02-01 10:50:11 +0000181
182 s->tb_next_offset = tb->tb_next_offset;
183#ifdef USE_DIRECT_JUMP
184 s->tb_jmp_offset = tb->tb_jmp_offset;
185 s->tb_next = NULL;
186#else
187 s->tb_jmp_offset = NULL;
188 s->tb_next = tb->tb_next;
189#endif
190 j = dyngen_code_search_pc(s, (uint8_t *)tc_ptr,
191 (void *)searched_pc);
192 if (j < 0)
193 return -1;
bellardd19893d2003-06-15 19:58:51 +0000194 /* now find start of instruction before */
195 while (gen_opc_instr_start[j] == 0)
196 j--;
bellardf76af4b2003-06-24 13:21:23 +0000197#if defined(TARGET_I386)
198 {
199 int cc_op;
bellard3c1cf9f2003-07-07 11:30:47 +0000200#ifdef DEBUG_DISAS
bellardf193c792004-03-21 17:06:25 +0000201 if (loglevel & CPU_LOG_TB_OP) {
bellard3c1cf9f2003-07-07 11:30:47 +0000202 int i;
bellard6e0374f2003-07-13 17:34:37 +0000203 fprintf(logfile, "RESTORE:\n");
bellard3c1cf9f2003-07-07 11:30:47 +0000204 for(i=0;i<=j; i++) {
205 if (gen_opc_instr_start[i]) {
bellardc4687872005-01-03 23:44:44 +0000206 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
bellard3c1cf9f2003-07-07 11:30:47 +0000207 }
208 }
ths5fafdf22007-09-16 21:08:06 +0000209 fprintf(logfile, "spc=0x%08lx j=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
210 searched_pc, j, gen_opc_pc[j] - tb->cs_base,
bellardc4687872005-01-03 23:44:44 +0000211 (uint32_t)tb->cs_base);
bellard3c1cf9f2003-07-07 11:30:47 +0000212 }
213#endif
bellardf76af4b2003-06-24 13:21:23 +0000214 env->eip = gen_opc_pc[j] - tb->cs_base;
215 cc_op = gen_opc_cc_op[j];
216 if (cc_op != CC_OP_DYNAMIC)
217 env->cc_op = cc_op;
218 }
219#elif defined(TARGET_ARM)
220 env->regs[15] = gen_opc_pc[j];
bellardd3eead22003-09-30 20:59:51 +0000221#elif defined(TARGET_SPARC)
bellardc3278b72005-03-20 12:43:29 +0000222 {
223 target_ulong npc;
224 env->pc = gen_opc_pc[j];
225 npc = gen_opc_npc[j];
226 if (npc == 1) {
227 /* dynamic NPC: already stored */
228 } else if (npc == 2) {
bellard745cacc2007-11-11 17:26:45 +0000229 target_ulong t2 = (target_ulong)(unsigned long)puc;
bellardc3278b72005-03-20 12:43:29 +0000230 /* jump PC: use T2 and the jump targets of the translation */
ths5fafdf22007-09-16 21:08:06 +0000231 if (t2)
bellardc3278b72005-03-20 12:43:29 +0000232 env->npc = gen_opc_jump_pc[0];
233 else
234 env->npc = gen_opc_jump_pc[1];
235 } else {
236 env->npc = npc;
237 }
238 }
bellard6dca2012003-11-23 17:32:06 +0000239#elif defined(TARGET_PPC)
bellardaf5ad102004-01-04 23:28:12 +0000240 {
bellard57fec1f2008-02-01 10:50:11 +0000241 int type, c;
bellardaf5ad102004-01-04 23:28:12 +0000242 /* for PPC, we need to look at the micro operation to get the
243 access type */
244 env->nip = gen_opc_pc[j];
bellard57fec1f2008-02-01 10:50:11 +0000245 c = gen_opc_buf[j];
bellardaf5ad102004-01-04 23:28:12 +0000246 switch(c) {
247#if defined(CONFIG_USER_ONLY)
248#define CASE3(op)\
249 case INDEX_op_ ## op ## _raw
250#else
251#define CASE3(op)\
bellardaf5ad102004-01-04 23:28:12 +0000252 case INDEX_op_ ## op ## _user:\
j_mayer78636672007-11-16 14:11:28 +0000253 case INDEX_op_ ## op ## _kernel:\
254 case INDEX_op_ ## op ## _hypv
bellardaf5ad102004-01-04 23:28:12 +0000255#endif
ths3b46e622007-09-17 08:09:54 +0000256
bellardaf5ad102004-01-04 23:28:12 +0000257 CASE3(stfd):
258 CASE3(stfs):
259 CASE3(lfd):
260 CASE3(lfs):
261 type = ACCESS_FLOAT;
262 break;
bellarda541f292004-04-12 20:39:29 +0000263 CASE3(lwarx):
264 type = ACCESS_RES;
265 break;
bellardaf5ad102004-01-04 23:28:12 +0000266 CASE3(stwcx):
267 type = ACCESS_RES;
268 break;
269 CASE3(eciwx):
270 CASE3(ecowx):
271 type = ACCESS_EXT;
272 break;
273 default:
274 type = ACCESS_INT;
275 break;
276 }
277 env->access_type = type;
278 }
pbrooke6e59062006-10-22 00:18:54 +0000279#elif defined(TARGET_M68K)
280 env->pc = gen_opc_pc[j];
bellard6af0bf92005-07-02 14:58:51 +0000281#elif defined(TARGET_MIPS)
thsead93602007-09-06 00:18:15 +0000282 env->PC[env->current_tc] = gen_opc_pc[j];
bellard30d6cb82005-12-05 19:56:07 +0000283 env->hflags &= ~MIPS_HFLAG_BMASK;
284 env->hflags |= gen_opc_hflags[j];
j_mayereddf68a2007-04-05 07:22:49 +0000285#elif defined(TARGET_ALPHA)
286 env->pc = gen_opc_pc[j];
ths823029f2007-12-02 06:10:04 +0000287#elif defined(TARGET_SH4)
288 env->pc = gen_opc_pc[j];
289 env->flags = gen_opc_hflags[j];
bellardf76af4b2003-06-24 13:21:23 +0000290#endif
bellard57fec1f2008-02-01 10:50:11 +0000291
292#ifdef CONFIG_PROFILER
293 dyngen_restore_time += profile_getclock() - ti;
294 dyngen_restore_count++;
295#endif
bellardd19893d2003-06-15 19:58:51 +0000296 return 0;
297}