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bellardd19893d2003-06-15 19:58:51 +00001/*
2 * Host code generation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26#include "config.h"
bellard20543962003-06-15 23:28:43 +000027
bellardaf5ad102004-01-04 23:28:12 +000028#define NO_CPU_IO_DEFS
bellardd3eead22003-09-30 20:59:51 +000029#include "cpu.h"
30#include "exec-all.h"
bellardd19893d2003-06-15 19:58:51 +000031#include "disas.h"
32
33enum {
34#define DEF(s, n, copy_size) INDEX_op_ ## s,
bellardd3eead22003-09-30 20:59:51 +000035#include "opc.h"
bellardd19893d2003-06-15 19:58:51 +000036#undef DEF
37 NB_OPS,
38};
39
40#include "dyngen.h"
bellardd3eead22003-09-30 20:59:51 +000041#include "op.h"
bellardd19893d2003-06-15 19:58:51 +000042
43uint16_t gen_opc_buf[OPC_BUF_SIZE];
44uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
45uint32_t gen_opc_pc[OPC_BUF_SIZE];
46uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
bellardf76af4b2003-06-24 13:21:23 +000047#if defined(TARGET_I386)
48uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
49#endif
bellardd19893d2003-06-15 19:58:51 +000050
51#ifdef DEBUG_DISAS
52static const char *op_str[] = {
53#define DEF(s, n, copy_size) #s,
bellardd3eead22003-09-30 20:59:51 +000054#include "opc.h"
bellardd19893d2003-06-15 19:58:51 +000055#undef DEF
56};
57
58static uint8_t op_nb_args[] = {
59#define DEF(s, n, copy_size) n,
bellardd3eead22003-09-30 20:59:51 +000060#include "opc.h"
bellardd19893d2003-06-15 19:58:51 +000061#undef DEF
62};
63
64void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
65{
66 const uint16_t *opc_ptr;
67 const uint32_t *opparam_ptr;
68 int c, n, i;
69
70 opc_ptr = opc_buf;
71 opparam_ptr = opparam_buf;
72 for(;;) {
73 c = *opc_ptr++;
74 n = op_nb_args[c];
75 fprintf(logfile, "0x%04x: %s",
76 (int)(opc_ptr - opc_buf - 1), op_str[c]);
77 for(i = 0; i < n; i++) {
78 fprintf(logfile, " 0x%x", opparam_ptr[i]);
79 }
80 fprintf(logfile, "\n");
81 if (c == INDEX_op_end)
82 break;
83 opparam_ptr += n;
84 }
85}
86
87#endif
88
89/* return non zero if the very first instruction is invalid so that
90 the virtual CPU can trigger an exception.
91
92 '*gen_code_size_ptr' contains the size of the generated code (host
93 code).
94*/
bellard4c3a88a2003-07-26 12:06:08 +000095int cpu_gen_code(CPUState *env, TranslationBlock *tb,
bellardd19893d2003-06-15 19:58:51 +000096 int max_code_size, int *gen_code_size_ptr)
97{
98 uint8_t *gen_code_buf;
99 int gen_code_size;
100
bellard4c3a88a2003-07-26 12:06:08 +0000101 if (gen_intermediate_code(env, tb) < 0)
bellardd19893d2003-06-15 19:58:51 +0000102 return -1;
103
104 /* generate machine code */
105 tb->tb_next_offset[0] = 0xffff;
106 tb->tb_next_offset[1] = 0xffff;
107 gen_code_buf = tb->tc_ptr;
bellard4cbb86e2003-09-17 22:53:29 +0000108#ifdef USE_DIRECT_JUMP
109 /* the following two entries are optional (only used for string ops) */
110 tb->tb_jmp_offset[2] = 0xffff;
111 tb->tb_jmp_offset[3] = 0xffff;
112#endif
bellardd19893d2003-06-15 19:58:51 +0000113 gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
114#ifdef USE_DIRECT_JUMP
115 tb->tb_jmp_offset,
116#else
117 NULL,
118#endif
119 gen_opc_buf, gen_opparam_buf);
120 *gen_code_size_ptr = gen_code_size;
121#ifdef DEBUG_DISAS
122 if (loglevel) {
123 fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
124 disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0);
125 fprintf(logfile, "\n");
126 fflush(logfile);
127 }
128#endif
129 return 0;
130}
131
132static const unsigned short opc_copy_size[] = {
133#define DEF(s, n, copy_size) copy_size,
bellardd3eead22003-09-30 20:59:51 +0000134#include "opc.h"
bellardd19893d2003-06-15 19:58:51 +0000135#undef DEF
136};
137
bellardf76af4b2003-06-24 13:21:23 +0000138/* The cpu state corresponding to 'searched_pc' is restored.
bellardd19893d2003-06-15 19:58:51 +0000139 */
bellardf76af4b2003-06-24 13:21:23 +0000140int cpu_restore_state(TranslationBlock *tb,
141 CPUState *env, unsigned long searched_pc)
bellardd19893d2003-06-15 19:58:51 +0000142{
143 int j, c;
144 unsigned long tc_ptr;
145 uint16_t *opc_ptr;
146
bellard4c3a88a2003-07-26 12:06:08 +0000147 if (gen_intermediate_code_pc(env, tb) < 0)
bellardd19893d2003-06-15 19:58:51 +0000148 return -1;
149
150 /* find opc index corresponding to search_pc */
151 tc_ptr = (unsigned long)tb->tc_ptr;
152 if (searched_pc < tc_ptr)
153 return -1;
154 j = 0;
155 opc_ptr = gen_opc_buf;
156 for(;;) {
157 c = *opc_ptr;
158 if (c == INDEX_op_end)
159 return -1;
160 tc_ptr += opc_copy_size[c];
161 if (searched_pc < tc_ptr)
162 break;
163 opc_ptr++;
164 }
165 j = opc_ptr - gen_opc_buf;
166 /* now find start of instruction before */
167 while (gen_opc_instr_start[j] == 0)
168 j--;
bellardf76af4b2003-06-24 13:21:23 +0000169#if defined(TARGET_I386)
170 {
171 int cc_op;
bellard3c1cf9f2003-07-07 11:30:47 +0000172#ifdef DEBUG_DISAS
173 if (loglevel) {
174 int i;
bellard6e0374f2003-07-13 17:34:37 +0000175 fprintf(logfile, "RESTORE:\n");
bellard3c1cf9f2003-07-07 11:30:47 +0000176 for(i=0;i<=j; i++) {
177 if (gen_opc_instr_start[i]) {
bellard6e0374f2003-07-13 17:34:37 +0000178 fprintf(logfile, "0x%04x: 0x%08x\n", i, gen_opc_pc[i]);
bellard3c1cf9f2003-07-07 11:30:47 +0000179 }
180 }
bellard6e0374f2003-07-13 17:34:37 +0000181 fprintf(logfile, "spc=0x%08lx j=0x%x eip=0x%lx cs_base=%lx\n",
182 searched_pc, j, gen_opc_pc[j] - tb->cs_base, tb->cs_base);
bellard3c1cf9f2003-07-07 11:30:47 +0000183 }
184#endif
bellardf76af4b2003-06-24 13:21:23 +0000185 env->eip = gen_opc_pc[j] - tb->cs_base;
186 cc_op = gen_opc_cc_op[j];
187 if (cc_op != CC_OP_DYNAMIC)
188 env->cc_op = cc_op;
189 }
190#elif defined(TARGET_ARM)
191 env->regs[15] = gen_opc_pc[j];
bellardd3eead22003-09-30 20:59:51 +0000192#elif defined(TARGET_SPARC)
bellard6dca2012003-11-23 17:32:06 +0000193 env->pc = gen_opc_pc[j];
194#elif defined(TARGET_PPC)
bellardaf5ad102004-01-04 23:28:12 +0000195 {
196 int type;
197 /* for PPC, we need to look at the micro operation to get the
198 access type */
199 env->nip = gen_opc_pc[j];
200 switch(c) {
201#if defined(CONFIG_USER_ONLY)
202#define CASE3(op)\
203 case INDEX_op_ ## op ## _raw
204#else
205#define CASE3(op)\
206 case INDEX_op_ ## op ## _raw:\
207 case INDEX_op_ ## op ## _user:\
208 case INDEX_op_ ## op ## _kernel
209#endif
210
211 CASE3(stfd):
212 CASE3(stfs):
213 CASE3(lfd):
214 CASE3(lfs):
215 type = ACCESS_FLOAT;
216 break;
217 CASE3(stwcx):
218 type = ACCESS_RES;
219 break;
220 CASE3(eciwx):
221 CASE3(ecowx):
222 type = ACCESS_EXT;
223 break;
224 default:
225 type = ACCESS_INT;
226 break;
227 }
228 env->access_type = type;
229 }
bellardf76af4b2003-06-24 13:21:23 +0000230#endif
bellardd19893d2003-06-15 19:58:51 +0000231 return 0;
232}