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Damien George075d5972014-11-27 20:30:33 +00001/******************************************************************************
2 * Copyright 2013-2014 Espressif Systems (Wuxi)
3 *
4 * FileName: uart.c
5 *
6 * Description: Two UART mode configration and interrupt handler.
7 * Check your hardware connection while use this mode.
8 *
9 * Modification history:
10 * 2014/3/12, v1.0 create this file.
11*******************************************************************************/
12#include "ets_sys.h"
13#include "osapi.h"
14#include "uart.h"
15#include "osapi.h"
16#include "uart_register.h"
17#include "etshal.h"
18#include "c_types.h"
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +020019#include "user_interface.h"
20#include "esp_mphal.h"
Damien George075d5972014-11-27 20:30:33 +000021
22#define RX_BUF_SIZE (256)
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +030023#define UART_REPL UART0
Damien George075d5972014-11-27 20:30:33 +000024
25// UartDev is defined and initialized in rom code.
26extern UartDevice UartDev;
27
28// circular buffer for RX buffering
29static uint16_t rx_buf_in;
30static uint16_t rx_buf_out;
31static uint8_t rx_buf[RX_BUF_SIZE];
32
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +020033static os_event_t uart_evt_queue[16];
34
Damien George075d5972014-11-27 20:30:33 +000035static void uart0_rx_intr_handler(void *para);
36
37/******************************************************************************
38 * FunctionName : uart_config
39 * Description : Internal used function
40 * UART0 used for data TX/RX, RX buffer size is 0x100, interrupt enabled
41 * UART1 just used for debug output
42 * Parameters : uart_no, use UART0 or UART1 defined ahead
43 * Returns : NONE
44*******************************************************************************/
45static void ICACHE_FLASH_ATTR uart_config(uint8 uart_no) {
46 if (uart_no == UART1) {
47 PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
48 } else {
49 ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, NULL);
50 PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
51 PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
52 PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
53 }
54
55 uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate));
56
57 WRITE_PERI_REG(UART_CONF0(uart_no), UartDev.exist_parity
58 | UartDev.parity
59 | (UartDev.stop_bits << UART_STOP_BIT_NUM_S)
60 | (UartDev.data_bits << UART_BIT_NUM_S));
61
62 // clear rx and tx fifo,not ready
63 SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
64 CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
65
66 if (uart_no == UART0) {
67 // set rx fifo trigger
68 WRITE_PERI_REG(UART_CONF1(uart_no),
69 ((0x10 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
70 ((0x10 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) |
71 UART_RX_FLOW_EN |
72 (0x02 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S |
73 UART_RX_TOUT_EN);
74 SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_TOUT_INT_ENA |
75 UART_FRM_ERR_INT_ENA);
76 } else {
77 WRITE_PERI_REG(UART_CONF1(uart_no),
78 ((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
79 }
80
81 // clear all interrupt
82 WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
83 // enable rx_interrupt
84 SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA);
85
86 // init RX buffer
87 rx_buf_in = 0;
88 rx_buf_out = 0;
89}
90
91/******************************************************************************
92 * FunctionName : uart1_tx_one_char
93 * Description : Internal used function
94 * Use uart1 interface to transfer one char
95 * Parameters : uint8 TxChar - character to tx
96 * Returns : OK
97*******************************************************************************/
98void uart_tx_one_char(uint8 uart, uint8 TxChar) {
99 while (true) {
100 uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT<<UART_TXFIFO_CNT_S);
101 if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
102 break;
103 }
104 }
105 WRITE_PERI_REG(UART_FIFO(uart), TxChar);
106}
107
108/******************************************************************************
109 * FunctionName : uart1_write_char
110 * Description : Internal used function
111 * Do some special deal while tx char is '\r' or '\n'
112 * Parameters : char c - character to tx
113 * Returns : NONE
114*******************************************************************************/
115static void ICACHE_FLASH_ATTR
Josef Gajdusek1c132c82015-05-13 15:39:25 +0200116uart_os_write_char(char c) {
Damien George075d5972014-11-27 20:30:33 +0000117 if (c == '\n') {
Josef Gajdusek1c132c82015-05-13 15:39:25 +0200118 uart_tx_one_char(UART_OS, '\r');
119 uart_tx_one_char(UART_OS, '\n');
Damien George075d5972014-11-27 20:30:33 +0000120 } else if (c == '\r') {
121 } else {
Josef Gajdusek1c132c82015-05-13 15:39:25 +0200122 uart_tx_one_char(UART_OS, c);
Damien George075d5972014-11-27 20:30:33 +0000123 }
124}
125
126/******************************************************************************
127 * FunctionName : uart0_rx_intr_handler
128 * Description : Internal used function
129 * UART0 interrupt handler, add self handle code inside
130 * Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg
131 * Returns : NONE
132*******************************************************************************/
133
134static void uart0_rx_intr_handler(void *para) {
135 /* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents
136 * uart1 and uart0 respectively
137 */
138
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300139 uint8 uart_no = UART_REPL;
Damien George075d5972014-11-27 20:30:33 +0000140
141 if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST)) {
142 // frame error
143 WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
144 }
145
146 if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) {
147 // fifo full
Damien George075d5972014-11-27 20:30:33 +0000148 goto read_chars;
149 } else if (UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)) {
Damien George075d5972014-11-27 20:30:33 +0000150 read_chars:
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +0200151#if 1 //MICROPY_REPL_EVENT_DRIVEN is not available here
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300152 ETS_UART_INTR_DISABLE();
153 system_os_post(UART_TASK_ID, 0, 0);
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +0200154#else
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300155 while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
156 uint8 RcvChar = READ_PERI_REG(UART_FIFO(uart_no)) & 0xff;
Damien George075d5972014-11-27 20:30:33 +0000157 uint16_t rx_buf_in_next = (rx_buf_in + 1) % RX_BUF_SIZE;
158 if (rx_buf_in_next != rx_buf_out) {
159 rx_buf[rx_buf_in] = RcvChar;
160 rx_buf_in = rx_buf_in_next;
161 }
162 }
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300163#endif
Damien George075d5972014-11-27 20:30:33 +0000164 }
165}
166
167int uart0_rx(void) {
168 if (rx_buf_out != rx_buf_in) {
169 int chr = rx_buf[rx_buf_out];
170 rx_buf_out = (rx_buf_out + 1) % RX_BUF_SIZE;
171 return chr;
172 } else {
173 return -1;
174 }
175}
176
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300177int uart_rx_one_char(uint8 uart_no) {
178 if (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S)) {
179 return READ_PERI_REG(UART_FIFO(uart_no)) & 0xff;
180 }
181 return -1;
182}
183
Damien George075d5972014-11-27 20:30:33 +0000184/******************************************************************************
185 * FunctionName : uart_init
186 * Description : user interface for init uart
187 * Parameters : UartBautRate uart0_br - uart0 bautrate
188 * UartBautRate uart1_br - uart1 bautrate
189 * Returns : NONE
190*******************************************************************************/
191void ICACHE_FLASH_ATTR uart_init(UartBautRate uart0_br, UartBautRate uart1_br) {
192 // rom use 74880 baut_rate, here reinitialize
193 UartDev.baut_rate = uart0_br;
194 uart_config(UART0);
195 UartDev.baut_rate = uart1_br;
196 uart_config(UART1);
197 ETS_UART_INTR_ENABLE();
198
199 // install uart1 putc callback
Josef Gajdusek1c132c82015-05-13 15:39:25 +0200200 os_install_putc1((void *)uart_os_write_char);
Damien George075d5972014-11-27 20:30:33 +0000201}
202
203void ICACHE_FLASH_ATTR uart_reattach() {
204 uart_init(UART_BIT_RATE_74880, UART_BIT_RATE_74880);
205}
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +0200206
207// Task-based UART interface
208
Damien Georgec98c1282015-05-06 00:02:58 +0100209#include "py/obj.h"
Damien George40274fe2015-11-09 13:13:09 +0000210#include "lib/utils/pyexec.h"
Damien Georgec98c1282015-05-06 00:02:58 +0100211
212void soft_reset(void);
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +0200213
214void uart_task_handler(os_event_t *evt) {
Paul Sokolovsky2fc1e642015-06-01 01:27:39 +0300215 int c, ret = 0;
216 while ((c = uart_rx_one_char(UART_REPL)) >= 0) {
217 ret = pyexec_event_repl_process_char(c);
218 if (ret & PYEXEC_FORCED_EXIT) {
219 break;
220 }
221 }
222
223 // Clear pending FIFO interrupts
224 WRITE_PERI_REG(UART_INT_CLR(UART_REPL), UART_RXFIFO_TOUT_INT_CLR | UART_RXFIFO_FULL_INT_ST);
225 // Enable UART interrupts, so our task will receive events again from IRQ handler
226 ETS_UART_INTR_ENABLE();
227
Damien Georgec98c1282015-05-06 00:02:58 +0100228 if (ret & PYEXEC_FORCED_EXIT) {
229 soft_reset();
230 }
Paul Sokolovskyf12ea7c2015-01-16 01:54:40 +0200231}
232
233void uart_task_init() {
234 system_os_task(uart_task_handler, UART_TASK_ID, uart_evt_queue, sizeof(uart_evt_queue) / sizeof(*uart_evt_queue));
235}