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Stephen Streete0c99052006-03-07 23:53:24 -08001/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
Mika Westerberga0d26422013-01-22 12:26:32 +02003 * Copyright (C) 2013, Intel Corporation
Stephen Streete0c99052006-03-07 23:53:24 -08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Stephen Streete0c99052006-03-07 23:53:24 -080014 */
15
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020016#include <linux/bitops.h>
Stephen Streete0c99052006-03-07 23:53:24 -080017#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/ioport.h>
21#include <linux/errno.h>
Sachin Kamatcbfd6a22013-04-08 15:49:33 +053022#include <linux/err.h>
Stephen Streete0c99052006-03-07 23:53:24 -080023#include <linux/interrupt.h>
Andy Shevchenko9df461e2015-03-25 15:06:16 +020024#include <linux/kernel.h>
Jarkko Nikula34cadd92015-07-30 16:30:07 +030025#include <linux/pci.h>
Stephen Streete0c99052006-03-07 23:53:24 -080026#include <linux/platform_device.h>
Sebastian Andrzej Siewior8348c252010-11-22 17:12:15 -080027#include <linux/spi/pxa2xx_spi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080028#include <linux/spi/spi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080029#include <linux/delay.h>
Eric Miaoa7bb3902009-04-06 19:00:54 -070030#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Mika Westerberg3343b7a2013-01-22 12:26:27 +020032#include <linux/clk.h>
Mika Westerberg7d94a502013-01-22 12:26:30 +020033#include <linux/pm_runtime.h>
Mika Westerberga3496852013-01-22 12:26:33 +020034#include <linux/acpi.h>
Stephen Streete0c99052006-03-07 23:53:24 -080035
Mika Westerbergcd7bed02013-01-22 12:26:28 +020036#include "spi-pxa2xx.h"
Stephen Streete0c99052006-03-07 23:53:24 -080037
38MODULE_AUTHOR("Stephen Street");
Will Newton037cdaf2007-12-10 15:49:25 -080039MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
Stephen Streete0c99052006-03-07 23:53:24 -080040MODULE_LICENSE("GPL");
Kay Sievers7e38c3c2008-04-10 21:29:20 -070041MODULE_ALIAS("platform:pxa2xx-spi");
Stephen Streete0c99052006-03-07 23:53:24 -080042
Vernon Sauderf1f640a2008-10-15 22:02:43 -070043#define TIMOUT_DFLT 1000
44
Ned Forresterb97c74b2008-02-23 15:23:40 -080045/*
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
51 */
52#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
Stephen Street8d94cc52006-12-10 02:18:54 -080053 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
Ned Forresterb97c74b2008-02-23 15:23:40 -080054 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
Stephen Street8d94cc52006-12-10 02:18:54 -080058
Weike Chene5262d02014-11-26 02:35:10 -080059#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
64
Jarkko Nikula624ea722015-10-28 15:13:39 +020065#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66#define LPSS_CS_CONTROL_SW_MODE BIT(0)
67#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
Jarkko Nikulad0283eb2015-10-28 15:13:40 +020068#define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
69#define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020070#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
Mika Westerberga0d26422013-01-22 12:26:32 +020072
Jarkko Nikuladccf7362015-06-04 16:55:11 +030073struct lpss_config {
74 /* LPSS offset from drv_data->ioaddr */
75 unsigned offset;
76 /* Register offsets from drv_data->lpss_base or -1 */
77 int reg_general;
78 int reg_ssp;
79 int reg_cs_ctrl;
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020080 int reg_capabilities;
Jarkko Nikuladccf7362015-06-04 16:55:11 +030081 /* FIFO thresholds */
82 u32 rx_threshold;
83 u32 tx_threshold_lo;
84 u32 tx_threshold_hi;
85};
86
87/* Keep these sorted with enum pxa_ssp_type */
88static const struct lpss_config lpss_platforms[] = {
89 { /* LPSS_LPT_SSP */
90 .offset = 0x800,
91 .reg_general = 0x08,
92 .reg_ssp = 0x0c,
93 .reg_cs_ctrl = 0x18,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +020094 .reg_capabilities = -1,
Jarkko Nikuladccf7362015-06-04 16:55:11 +030095 .rx_threshold = 64,
96 .tx_threshold_lo = 160,
97 .tx_threshold_hi = 224,
98 },
99 { /* LPSS_BYT_SSP */
100 .offset = 0x400,
101 .reg_general = 0x08,
102 .reg_ssp = 0x0c,
103 .reg_cs_ctrl = 0x18,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +0200104 .reg_capabilities = -1,
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300105 .rx_threshold = 64,
106 .tx_threshold_lo = 160,
107 .tx_threshold_hi = 224,
108 },
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300109 { /* LPSS_SPT_SSP */
110 .offset = 0x200,
111 .reg_general = -1,
112 .reg_ssp = 0x20,
113 .reg_cs_ctrl = 0x24,
Jarkko Nikula8b136ba2015-10-28 15:13:41 +0200114 .reg_capabilities = 0xfc,
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300115 .rx_threshold = 1,
116 .tx_threshold_lo = 32,
117 .tx_threshold_hi = 56,
118 },
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300119};
120
121static inline const struct lpss_config
122*lpss_get_config(const struct driver_data *drv_data)
123{
124 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
125}
126
Mika Westerberga0d26422013-01-22 12:26:32 +0200127static bool is_lpss_ssp(const struct driver_data *drv_data)
128{
Jarkko Nikula03fbf482015-06-04 16:55:10 +0300129 switch (drv_data->ssp_type) {
130 case LPSS_LPT_SSP:
131 case LPSS_BYT_SSP:
Jarkko Nikula34cadd92015-07-30 16:30:07 +0300132 case LPSS_SPT_SSP:
Jarkko Nikula03fbf482015-06-04 16:55:10 +0300133 return true;
134 default:
135 return false;
136 }
Mika Westerberga0d26422013-01-22 12:26:32 +0200137}
138
Weike Chene5262d02014-11-26 02:35:10 -0800139static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
140{
141 return drv_data->ssp_type == QUARK_X1000_SSP;
142}
143
Weike Chen4fdb2422014-10-08 08:50:22 -0700144static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
145{
146 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800147 case QUARK_X1000_SSP:
148 return QUARK_X1000_SSCR1_CHANGE_MASK;
Weike Chen4fdb2422014-10-08 08:50:22 -0700149 default:
150 return SSCR1_CHANGE_MASK;
151 }
152}
153
154static u32
155pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
156{
157 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800158 case QUARK_X1000_SSP:
159 return RX_THRESH_QUARK_X1000_DFLT;
Weike Chen4fdb2422014-10-08 08:50:22 -0700160 default:
161 return RX_THRESH_DFLT;
162 }
163}
164
165static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
166{
Weike Chen4fdb2422014-10-08 08:50:22 -0700167 u32 mask;
168
169 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800170 case QUARK_X1000_SSP:
171 mask = QUARK_X1000_SSSR_TFL_MASK;
172 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700173 default:
174 mask = SSSR_TFL_MASK;
175 break;
176 }
177
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200178 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
Weike Chen4fdb2422014-10-08 08:50:22 -0700179}
180
181static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
182 u32 *sccr1_reg)
183{
184 u32 mask;
185
186 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800187 case QUARK_X1000_SSP:
188 mask = QUARK_X1000_SSCR1_RFT;
189 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700190 default:
191 mask = SSCR1_RFT;
192 break;
193 }
194 *sccr1_reg &= ~mask;
195}
196
197static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
198 u32 *sccr1_reg, u32 threshold)
199{
200 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800201 case QUARK_X1000_SSP:
202 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
203 break;
Weike Chen4fdb2422014-10-08 08:50:22 -0700204 default:
205 *sccr1_reg |= SSCR1_RxTresh(threshold);
206 break;
207 }
208}
209
210static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
211 u32 clk_div, u8 bits)
212{
213 switch (drv_data->ssp_type) {
Weike Chene5262d02014-11-26 02:35:10 -0800214 case QUARK_X1000_SSP:
215 return clk_div
216 | QUARK_X1000_SSCR0_Motorola
217 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
218 | SSCR0_SSE;
Weike Chen4fdb2422014-10-08 08:50:22 -0700219 default:
220 return clk_div
221 | SSCR0_Motorola
222 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
223 | SSCR0_SSE
224 | (bits > 16 ? SSCR0_EDSS : 0);
225 }
226}
227
Mika Westerberga0d26422013-01-22 12:26:32 +0200228/*
229 * Read and write LPSS SSP private registers. Caller must first check that
230 * is_lpss_ssp() returns true before these can be called.
231 */
232static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
233{
234 WARN_ON(!drv_data->lpss_base);
235 return readl(drv_data->lpss_base + offset);
236}
237
238static void __lpss_ssp_write_priv(struct driver_data *drv_data,
239 unsigned offset, u32 value)
240{
241 WARN_ON(!drv_data->lpss_base);
242 writel(value, drv_data->lpss_base + offset);
243}
244
245/*
246 * lpss_ssp_setup - perform LPSS SSP specific setup
247 * @drv_data: pointer to the driver private data
248 *
249 * Perform LPSS SSP specific setup. This function must be called first if
250 * one is going to use LPSS SSP private registers.
251 */
252static void lpss_ssp_setup(struct driver_data *drv_data)
253{
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300254 const struct lpss_config *config;
255 u32 value;
Mika Westerberga0d26422013-01-22 12:26:32 +0200256
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300257 config = lpss_get_config(drv_data);
258 drv_data->lpss_base = drv_data->ioaddr + config->offset;
Mika Westerberga0d26422013-01-22 12:26:32 +0200259
260 /* Enable software chip select control */
Jarkko Nikula0e897212015-10-22 16:44:42 +0300261 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
Jarkko Nikula624ea722015-10-28 15:13:39 +0200262 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
263 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300264 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
Mika Westerberg0054e282013-03-05 12:05:17 +0200265
266 /* Enable multiblock DMA transfers */
Mika Westerberg1de70612013-07-03 13:25:06 +0300267 if (drv_data->master_info->enable_dma) {
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300268 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
Mika Westerberg1de70612013-07-03 13:25:06 +0300269
Jarkko Nikula82ba2c22015-06-04 16:55:12 +0300270 if (config->reg_general >= 0) {
271 value = __lpss_ssp_read_priv(drv_data,
272 config->reg_general);
Jarkko Nikula624ea722015-10-28 15:13:39 +0200273 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
Jarkko Nikula82ba2c22015-06-04 16:55:12 +0300274 __lpss_ssp_write_priv(drv_data,
275 config->reg_general, value);
276 }
Mika Westerberg1de70612013-07-03 13:25:06 +0300277 }
Mika Westerberga0d26422013-01-22 12:26:32 +0200278}
279
280static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
281{
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300282 const struct lpss_config *config;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200283 u32 value, cs;
Mika Westerberga0d26422013-01-22 12:26:32 +0200284
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300285 config = lpss_get_config(drv_data);
286
287 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200288 if (enable) {
289 cs = drv_data->cur_msg->spi->chip_select;
290 cs <<= LPSS_CS_CONTROL_CS_SEL_SHIFT;
291 if (cs != (value & LPSS_CS_CONTROL_CS_SEL_MASK)) {
292 /*
293 * When switching another chip select output active
294 * the output must be selected first and wait 2 ssp_clk
295 * cycles before changing state to active. Otherwise
296 * a short glitch will occur on the previous chip
297 * select since output select is latched but state
298 * control is not.
299 */
300 value &= ~LPSS_CS_CONTROL_CS_SEL_MASK;
301 value |= cs;
302 __lpss_ssp_write_priv(drv_data,
303 config->reg_cs_ctrl, value);
304 ndelay(1000000000 /
305 (drv_data->master->max_speed_hz / 2));
306 }
Jarkko Nikula624ea722015-10-28 15:13:39 +0200307 value &= ~LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200308 } else {
Jarkko Nikula624ea722015-10-28 15:13:39 +0200309 value |= LPSS_CS_CONTROL_CS_HIGH;
Jarkko Nikulad0283eb2015-10-28 15:13:40 +0200310 }
Jarkko Nikuladccf7362015-06-04 16:55:11 +0300311 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
Mika Westerberga0d26422013-01-22 12:26:32 +0200312}
313
Eric Miaoa7bb3902009-04-06 19:00:54 -0700314static void cs_assert(struct driver_data *drv_data)
315{
316 struct chip_data *chip = drv_data->cur_chip;
317
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800318 if (drv_data->ssp_type == CE4100_SSP) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200319 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800320 return;
321 }
322
Eric Miaoa7bb3902009-04-06 19:00:54 -0700323 if (chip->cs_control) {
324 chip->cs_control(PXA2XX_CS_ASSERT);
325 return;
326 }
327
Mika Westerberga0d26422013-01-22 12:26:32 +0200328 if (gpio_is_valid(chip->gpio_cs)) {
Eric Miaoa7bb3902009-04-06 19:00:54 -0700329 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
Mika Westerberga0d26422013-01-22 12:26:32 +0200330 return;
331 }
332
Jarkko Nikula7566bcc2014-12-18 15:04:20 +0200333 if (is_lpss_ssp(drv_data))
334 lpss_ssp_cs_control(drv_data, true);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700335}
336
337static void cs_deassert(struct driver_data *drv_data)
338{
339 struct chip_data *chip = drv_data->cur_chip;
340
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800341 if (drv_data->ssp_type == CE4100_SSP)
342 return;
343
Eric Miaoa7bb3902009-04-06 19:00:54 -0700344 if (chip->cs_control) {
Daniel Ribeiro2b2562d2009-04-08 22:48:03 -0300345 chip->cs_control(PXA2XX_CS_DEASSERT);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700346 return;
347 }
348
Mika Westerberga0d26422013-01-22 12:26:32 +0200349 if (gpio_is_valid(chip->gpio_cs)) {
Eric Miaoa7bb3902009-04-06 19:00:54 -0700350 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
Mika Westerberga0d26422013-01-22 12:26:32 +0200351 return;
352 }
353
Jarkko Nikula7566bcc2014-12-18 15:04:20 +0200354 if (is_lpss_ssp(drv_data))
355 lpss_ssp_cs_control(drv_data, false);
Eric Miaoa7bb3902009-04-06 19:00:54 -0700356}
357
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200358int pxa2xx_spi_flush(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800359{
360 unsigned long limit = loops_per_jiffy << 1;
361
Stephen Streete0c99052006-03-07 23:53:24 -0800362 do {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200363 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
364 pxa2xx_spi_read(drv_data, SSDR);
365 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800366 write_SSSR_CS(drv_data, SSSR_ROR);
Stephen Streete0c99052006-03-07 23:53:24 -0800367
368 return limit;
369}
370
Stephen Street8d94cc52006-12-10 02:18:54 -0800371static int null_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800372{
Stephen Street9708c122006-03-28 14:05:23 -0800373 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800374
Weike Chen4fdb2422014-10-08 08:50:22 -0700375 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800376 || (drv_data->tx == drv_data->tx_end))
377 return 0;
378
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200379 pxa2xx_spi_write(drv_data, SSDR, 0);
Stephen Street8d94cc52006-12-10 02:18:54 -0800380 drv_data->tx += n_bytes;
381
382 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800383}
384
Stephen Street8d94cc52006-12-10 02:18:54 -0800385static int null_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800386{
Stephen Street9708c122006-03-28 14:05:23 -0800387 u8 n_bytes = drv_data->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800388
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200389 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
390 && (drv_data->rx < drv_data->rx_end)) {
391 pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800392 drv_data->rx += n_bytes;
393 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800394
395 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800396}
397
Stephen Street8d94cc52006-12-10 02:18:54 -0800398static int u8_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800399{
Weike Chen4fdb2422014-10-08 08:50:22 -0700400 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800401 || (drv_data->tx == drv_data->tx_end))
402 return 0;
403
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200404 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800405 ++drv_data->tx;
406
407 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800408}
409
Stephen Street8d94cc52006-12-10 02:18:54 -0800410static int u8_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800411{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200412 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
413 && (drv_data->rx < drv_data->rx_end)) {
414 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800415 ++drv_data->rx;
416 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800417
418 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800419}
420
Stephen Street8d94cc52006-12-10 02:18:54 -0800421static int u16_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800422{
Weike Chen4fdb2422014-10-08 08:50:22 -0700423 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800424 || (drv_data->tx == drv_data->tx_end))
425 return 0;
426
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200427 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800428 drv_data->tx += 2;
429
430 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800431}
432
Stephen Street8d94cc52006-12-10 02:18:54 -0800433static int u16_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800434{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200435 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
436 && (drv_data->rx < drv_data->rx_end)) {
437 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800438 drv_data->rx += 2;
439 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800440
441 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800442}
Stephen Street8d94cc52006-12-10 02:18:54 -0800443
444static int u32_writer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800445{
Weike Chen4fdb2422014-10-08 08:50:22 -0700446 if (pxa2xx_spi_txfifo_full(drv_data)
Stephen Street8d94cc52006-12-10 02:18:54 -0800447 || (drv_data->tx == drv_data->tx_end))
448 return 0;
449
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200450 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
Stephen Street8d94cc52006-12-10 02:18:54 -0800451 drv_data->tx += 4;
452
453 return 1;
Stephen Streete0c99052006-03-07 23:53:24 -0800454}
455
Stephen Street8d94cc52006-12-10 02:18:54 -0800456static int u32_reader(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800457{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200458 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
459 && (drv_data->rx < drv_data->rx_end)) {
460 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
Stephen Streete0c99052006-03-07 23:53:24 -0800461 drv_data->rx += 4;
462 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800463
464 return drv_data->rx == drv_data->rx_end;
Stephen Streete0c99052006-03-07 23:53:24 -0800465}
466
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200467void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800468{
469 struct spi_message *msg = drv_data->cur_msg;
470 struct spi_transfer *trans = drv_data->cur_transfer;
471
472 /* Move to next transfer */
473 if (trans->transfer_list.next != &msg->transfers) {
474 drv_data->cur_transfer =
475 list_entry(trans->transfer_list.next,
476 struct spi_transfer,
477 transfer_list);
478 return RUNNING_STATE;
479 } else
480 return DONE_STATE;
481}
482
Stephen Streete0c99052006-03-07 23:53:24 -0800483/* caller already set message->status; dma and pio irqs are blocked */
Stephen Street5daa3ba2006-05-20 15:00:19 -0700484static void giveback(struct driver_data *drv_data)
Stephen Streete0c99052006-03-07 23:53:24 -0800485{
486 struct spi_transfer* last_transfer;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700487 struct spi_message *msg;
Stephen Streete0c99052006-03-07 23:53:24 -0800488
Stephen Street5daa3ba2006-05-20 15:00:19 -0700489 msg = drv_data->cur_msg;
490 drv_data->cur_msg = NULL;
491 drv_data->cur_transfer = NULL;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700492
Axel Lin23e2c2a2014-02-12 22:13:27 +0800493 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
Stephen Streete0c99052006-03-07 23:53:24 -0800494 transfer_list);
495
Ned Forrester84235972008-09-13 02:33:17 -0700496 /* Delay if requested before any change in chip select */
497 if (last_transfer->delay_usecs)
498 udelay(last_transfer->delay_usecs);
499
500 /* Drop chip select UNLESS cs_change is true or we are returning
501 * a message with an error, or next message is for another chip
502 */
Stephen Streete0c99052006-03-07 23:53:24 -0800503 if (!last_transfer->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700504 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700505 else {
506 struct spi_message *next_msg;
507
508 /* Holding of cs was hinted, but we need to make sure
509 * the next message is for the same chip. Don't waste
510 * time with the following tests unless this was hinted.
511 *
512 * We cannot postpone this until pump_messages, because
513 * after calling msg->complete (below) the driver that
514 * sent the current message could be unloaded, which
515 * could invalidate the cs_control() callback...
516 */
517
518 /* get a pointer to the next message, if any */
Mika Westerberg7f86bde2013-01-22 12:26:26 +0200519 next_msg = spi_get_next_queued_message(drv_data->master);
Ned Forrester84235972008-09-13 02:33:17 -0700520
521 /* see if the next and current messages point
522 * to the same chip
523 */
524 if (next_msg && next_msg->spi != msg->spi)
525 next_msg = NULL;
526 if (!next_msg || msg->state == ERROR_STATE)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700527 cs_deassert(drv_data);
Ned Forrester84235972008-09-13 02:33:17 -0700528 }
Stephen Streete0c99052006-03-07 23:53:24 -0800529
Eric Miaoa7bb3902009-04-06 19:00:54 -0700530 drv_data->cur_chip = NULL;
Mika Westerbergc957e8f2014-12-29 10:33:36 +0200531 spi_finalize_current_message(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -0800532}
533
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800534static void reset_sccr1(struct driver_data *drv_data)
535{
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800536 struct chip_data *chip = drv_data->cur_chip;
537 u32 sccr1_reg;
538
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200539 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800540 sccr1_reg &= ~SSCR1_RFT;
541 sccr1_reg |= chip->threshold;
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200542 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800543}
544
Stephen Street8d94cc52006-12-10 02:18:54 -0800545static void int_error_stop(struct driver_data *drv_data, const char* msg)
546{
Stephen Street8d94cc52006-12-10 02:18:54 -0800547 /* Stop and reset SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800548 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800549 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800550 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200551 pxa2xx_spi_write(drv_data, SSTO, 0);
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200552 pxa2xx_spi_flush(drv_data);
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200553 pxa2xx_spi_write(drv_data, SSCR0,
554 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
Stephen Street8d94cc52006-12-10 02:18:54 -0800555
556 dev_err(&drv_data->pdev->dev, "%s\n", msg);
557
558 drv_data->cur_msg->state = ERROR_STATE;
559 tasklet_schedule(&drv_data->pump_transfers);
560}
561
562static void int_transfer_complete(struct driver_data *drv_data)
563{
Stephen Street8d94cc52006-12-10 02:18:54 -0800564 /* Stop SSP */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800565 write_SSSR_CS(drv_data, drv_data->clear_sr);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800566 reset_sccr1(drv_data);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800567 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200568 pxa2xx_spi_write(drv_data, SSTO, 0);
Stephen Street8d94cc52006-12-10 02:18:54 -0800569
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300570 /* Update total byte transferred return count actual bytes read */
Stephen Street8d94cc52006-12-10 02:18:54 -0800571 drv_data->cur_msg->actual_length += drv_data->len -
572 (drv_data->rx_end - drv_data->rx);
573
Ned Forrester84235972008-09-13 02:33:17 -0700574 /* Transfer delays and chip select release are
575 * handled in pump_transfers or giveback
576 */
Stephen Street8d94cc52006-12-10 02:18:54 -0800577
578 /* Move to next transfer */
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200579 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
Stephen Street8d94cc52006-12-10 02:18:54 -0800580
581 /* Schedule transfer tasklet */
582 tasklet_schedule(&drv_data->pump_transfers);
583}
584
Stephen Streete0c99052006-03-07 23:53:24 -0800585static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
586{
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200587 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
588 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
Stephen Street8d94cc52006-12-10 02:18:54 -0800589
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200590 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
Stephen Streete0c99052006-03-07 23:53:24 -0800591
Stephen Street8d94cc52006-12-10 02:18:54 -0800592 if (irq_status & SSSR_ROR) {
593 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
594 return IRQ_HANDLED;
595 }
Stephen Streete0c99052006-03-07 23:53:24 -0800596
Stephen Street8d94cc52006-12-10 02:18:54 -0800597 if (irq_status & SSSR_TINT) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200598 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
Stephen Street8d94cc52006-12-10 02:18:54 -0800599 if (drv_data->read(drv_data)) {
600 int_transfer_complete(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800601 return IRQ_HANDLED;
602 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800603 }
Stephen Streete0c99052006-03-07 23:53:24 -0800604
Stephen Street8d94cc52006-12-10 02:18:54 -0800605 /* Drain rx fifo, Fill tx fifo and prevent overruns */
606 do {
607 if (drv_data->read(drv_data)) {
608 int_transfer_complete(drv_data);
609 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800610 }
Stephen Street8d94cc52006-12-10 02:18:54 -0800611 } while (drv_data->write(drv_data));
Stephen Streete0c99052006-03-07 23:53:24 -0800612
Stephen Street8d94cc52006-12-10 02:18:54 -0800613 if (drv_data->read(drv_data)) {
614 int_transfer_complete(drv_data);
615 return IRQ_HANDLED;
616 }
Stephen Streete0c99052006-03-07 23:53:24 -0800617
Stephen Street8d94cc52006-12-10 02:18:54 -0800618 if (drv_data->tx == drv_data->tx_end) {
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800619 u32 bytes_left;
620 u32 sccr1_reg;
621
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200622 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800623 sccr1_reg &= ~SSCR1_TIE;
624
625 /*
626 * PXA25x_SSP has no timeout, set up rx threshould for the
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300627 * remaining RX bytes.
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800628 */
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800629 if (pxa25x_ssp_comp(drv_data)) {
Weike Chen4fdb2422014-10-08 08:50:22 -0700630 u32 rx_thre;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800631
Weike Chen4fdb2422014-10-08 08:50:22 -0700632 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800633
634 bytes_left = drv_data->rx_end - drv_data->rx;
635 switch (drv_data->n_bytes) {
636 case 4:
637 bytes_left >>= 1;
638 case 2:
639 bytes_left >>= 1;
Stephen Street8d94cc52006-12-10 02:18:54 -0800640 }
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800641
Weike Chen4fdb2422014-10-08 08:50:22 -0700642 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
643 if (rx_thre > bytes_left)
644 rx_thre = bytes_left;
Sebastian Andrzej Siewior579d3bb2010-11-22 17:12:17 -0800645
Weike Chen4fdb2422014-10-08 08:50:22 -0700646 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
Stephen Streete0c99052006-03-07 23:53:24 -0800647 }
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200648 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
Stephen Streete0c99052006-03-07 23:53:24 -0800649 }
650
Stephen Street5daa3ba2006-05-20 15:00:19 -0700651 /* We did something */
652 return IRQ_HANDLED;
Stephen Streete0c99052006-03-07 23:53:24 -0800653}
654
David Howells7d12e782006-10-05 14:55:46 +0100655static irqreturn_t ssp_int(int irq, void *dev_id)
Stephen Streete0c99052006-03-07 23:53:24 -0800656{
Jeff Garzikc7bec5a2006-10-06 15:00:58 -0400657 struct driver_data *drv_data = dev_id;
Mika Westerberg7d94a502013-01-22 12:26:30 +0200658 u32 sccr1_reg;
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800659 u32 mask = drv_data->mask_sr;
660 u32 status;
661
Mika Westerberg7d94a502013-01-22 12:26:30 +0200662 /*
663 * The IRQ might be shared with other peripherals so we must first
664 * check that are we RPM suspended or not. If we are we assume that
665 * the IRQ was not for us (we shouldn't be RPM suspended when the
666 * interrupt is enabled).
667 */
668 if (pm_runtime_suspended(&drv_data->pdev->dev))
669 return IRQ_NONE;
670
Mika Westerberg269e4a42013-09-04 13:37:43 +0300671 /*
672 * If the device is not yet in RPM suspended state and we get an
673 * interrupt that is meant for another device, check if status bits
674 * are all set to one. That means that the device is already
675 * powered off.
676 */
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200677 status = pxa2xx_spi_read(drv_data, SSSR);
Mika Westerberg269e4a42013-09-04 13:37:43 +0300678 if (status == ~0)
679 return IRQ_NONE;
680
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -0800682
683 /* Ignore possible writes if we don't need to write */
684 if (!(sccr1_reg & SSCR1_TIE))
685 mask &= ~SSSR_TFS;
686
687 if (!(status & mask))
688 return IRQ_NONE;
Stephen Streete0c99052006-03-07 23:53:24 -0800689
690 if (!drv_data->cur_msg) {
Stephen Street5daa3ba2006-05-20 15:00:19 -0700691
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200692 pxa2xx_spi_write(drv_data, SSCR0,
693 pxa2xx_spi_read(drv_data, SSCR0)
694 & ~SSCR0_SSE);
695 pxa2xx_spi_write(drv_data, SSCR1,
696 pxa2xx_spi_read(drv_data, SSCR1)
697 & ~drv_data->int_cr1);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800698 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200699 pxa2xx_spi_write(drv_data, SSTO, 0);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800700 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street5daa3ba2006-05-20 15:00:19 -0700701
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300702 dev_err(&drv_data->pdev->dev,
703 "bad message state in interrupt handler\n");
Stephen Street5daa3ba2006-05-20 15:00:19 -0700704
Stephen Streete0c99052006-03-07 23:53:24 -0800705 /* Never fail */
706 return IRQ_HANDLED;
707 }
708
709 return drv_data->transfer_handler(drv_data);
710}
711
Weike Chene5262d02014-11-26 02:35:10 -0800712/*
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200713 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
714 * input frequency by fractions of 2^24. It also has a divider by 5.
715 *
716 * There are formulas to get baud rate value for given input frequency and
717 * divider parameters, such as DDS_CLK_RATE and SCR:
718 *
719 * Fsys = 200MHz
720 *
721 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
722 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
723 *
724 * DDS_CLK_RATE either 2^n or 2^n / 5.
725 * SCR is in range 0 .. 255
726 *
727 * Divisor = 5^i * 2^j * 2 * k
728 * i = [0, 1] i = 1 iff j = 0 or j > 3
729 * j = [0, 23] j = 0 iff i = 1
730 * k = [1, 256]
731 * Special case: j = 0, i = 1: Divisor = 2 / 5
732 *
733 * Accordingly to the specification the recommended values for DDS_CLK_RATE
734 * are:
735 * Case 1: 2^n, n = [0, 23]
736 * Case 2: 2^24 * 2 / 5 (0x666666)
737 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
738 *
739 * In all cases the lowest possible value is better.
740 *
741 * The function calculates parameters for all cases and chooses the one closest
742 * to the asked baud rate.
Weike Chene5262d02014-11-26 02:35:10 -0800743 */
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200744static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
Weike Chene5262d02014-11-26 02:35:10 -0800745{
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200746 unsigned long xtal = 200000000;
747 unsigned long fref = xtal / 2; /* mandatory division by 2,
748 see (2) */
749 /* case 3 */
750 unsigned long fref1 = fref / 2; /* case 1 */
751 unsigned long fref2 = fref * 2 / 5; /* case 2 */
752 unsigned long scale;
753 unsigned long q, q1, q2;
754 long r, r1, r2;
755 u32 mul;
Weike Chene5262d02014-11-26 02:35:10 -0800756
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200757 /* Case 1 */
758
759 /* Set initial value for DDS_CLK_RATE */
760 mul = (1 << 24) >> 1;
761
762 /* Calculate initial quot */
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300763 q1 = DIV_ROUND_UP(fref1, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200764
765 /* Scale q1 if it's too big */
766 if (q1 > 256) {
767 /* Scale q1 to range [1, 512] */
768 scale = fls_long(q1 - 1);
769 if (scale > 9) {
770 q1 >>= scale - 9;
771 mul >>= scale - 9;
772 }
773
774 /* Round the result if we have a remainder */
775 q1 += q1 & 1;
776 }
777
778 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
779 scale = __ffs(q1);
780 q1 >>= scale;
781 mul >>= scale;
782
783 /* Get the remainder */
784 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
785
786 /* Case 2 */
787
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300788 q2 = DIV_ROUND_UP(fref2, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200789 r2 = abs(fref2 / q2 - rate);
790
791 /*
792 * Choose the best between two: less remainder we have the better. We
793 * can't go case 2 if q2 is greater than 256 since SCR register can
794 * hold only values 0 .. 255.
795 */
796 if (r2 >= r1 || q2 > 256) {
797 /* case 1 is better */
798 r = r1;
799 q = q1;
800 } else {
801 /* case 2 is better */
802 r = r2;
803 q = q2;
804 mul = (1 << 24) * 2 / 5;
805 }
806
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300807 /* Check case 3 only if the divisor is big enough */
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200808 if (fref / rate >= 80) {
809 u64 fssp;
810 u32 m;
811
812 /* Calculate initial quot */
Andy Shevchenko3ad48062015-10-13 17:09:14 +0300813 q1 = DIV_ROUND_UP(fref, rate);
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200814 m = (1 << 24) / q1;
815
816 /* Get the remainder */
817 fssp = (u64)fref * m;
818 do_div(fssp, 1 << 24);
819 r1 = abs(fssp - rate);
820
821 /* Choose this one if it suits better */
822 if (r1 < r) {
823 /* case 3 is better */
824 q = 1;
825 mul = m;
Weike Chene5262d02014-11-26 02:35:10 -0800826 }
827 }
828
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200829 *dds = mul;
830 return q - 1;
Weike Chene5262d02014-11-26 02:35:10 -0800831}
832
Mika Westerberg3343b7a2013-01-22 12:26:27 +0200833static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
eric miao2f1a74e2007-11-21 18:50:53 +0800834{
Jarkko Nikula0eca7cf2015-09-25 10:27:17 +0300835 unsigned long ssp_clk = drv_data->master->max_speed_hz;
Mika Westerberg3343b7a2013-01-22 12:26:27 +0200836 const struct ssp_device *ssp = drv_data->ssp;
837
838 rate = min_t(int, ssp_clk, rate);
eric miao2f1a74e2007-11-21 18:50:53 +0800839
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -0800840 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200841 return (ssp_clk / (2 * rate) - 1) & 0xff;
eric miao2f1a74e2007-11-21 18:50:53 +0800842 else
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200843 return (ssp_clk / rate - 1) & 0xfff;
eric miao2f1a74e2007-11-21 18:50:53 +0800844}
845
Weike Chene5262d02014-11-26 02:35:10 -0800846static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300847 int rate)
Weike Chene5262d02014-11-26 02:35:10 -0800848{
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300849 struct chip_data *chip = drv_data->cur_chip;
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200850 unsigned int clk_div;
Weike Chene5262d02014-11-26 02:35:10 -0800851
852 switch (drv_data->ssp_type) {
853 case QUARK_X1000_SSP:
Andy Shevchenko9df461e2015-03-25 15:06:16 +0200854 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
Dan Carpentereecacf72015-03-31 16:49:38 +0300855 break;
Weike Chene5262d02014-11-26 02:35:10 -0800856 default:
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200857 clk_div = ssp_get_clk_div(drv_data, rate);
Dan Carpentereecacf72015-03-31 16:49:38 +0300858 break;
Weike Chene5262d02014-11-26 02:35:10 -0800859 }
Andy Shevchenko025ffe82015-03-24 17:43:21 +0200860 return clk_div << 8;
Weike Chene5262d02014-11-26 02:35:10 -0800861}
862
Stephen Streete0c99052006-03-07 23:53:24 -0800863static void pump_transfers(unsigned long data)
864{
865 struct driver_data *drv_data = (struct driver_data *)data;
866 struct spi_message *message = NULL;
867 struct spi_transfer *transfer = NULL;
868 struct spi_transfer *previous = NULL;
869 struct chip_data *chip = NULL;
Stephen Street9708c122006-03-28 14:05:23 -0800870 u32 clk_div = 0;
871 u8 bits = 0;
872 u32 speed = 0;
873 u32 cr0;
Stephen Street8d94cc52006-12-10 02:18:54 -0800874 u32 cr1;
875 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
876 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
Weike Chen4fdb2422014-10-08 08:50:22 -0700877 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800878
879 /* Get current state information */
880 message = drv_data->cur_msg;
881 transfer = drv_data->cur_transfer;
882 chip = drv_data->cur_chip;
883
884 /* Handle for abort */
885 if (message->state == ERROR_STATE) {
886 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700887 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800888 return;
889 }
890
891 /* Handle end of message */
892 if (message->state == DONE_STATE) {
893 message->status = 0;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700894 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800895 return;
896 }
897
Ned Forrester84235972008-09-13 02:33:17 -0700898 /* Delay if requested at end of transfer before CS change */
Stephen Streete0c99052006-03-07 23:53:24 -0800899 if (message->state == RUNNING_STATE) {
900 previous = list_entry(transfer->transfer_list.prev,
901 struct spi_transfer,
902 transfer_list);
903 if (previous->delay_usecs)
904 udelay(previous->delay_usecs);
Ned Forrester84235972008-09-13 02:33:17 -0700905
906 /* Drop chip select only if cs_change is requested */
907 if (previous->cs_change)
Eric Miaoa7bb3902009-04-06 19:00:54 -0700908 cs_deassert(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800909 }
910
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200911 /* Check if we can DMA this transfer */
912 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
Ned Forrester7e964452008-09-13 02:33:18 -0700913
914 /* reject already-mapped transfers; PIO won't always work */
915 if (message->is_dma_mapped
916 || transfer->rx_dma || transfer->tx_dma) {
917 dev_err(&drv_data->pdev->dev,
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300918 "pump_transfers: mapped transfer length of "
919 "%u is greater than %d\n",
Ned Forrester7e964452008-09-13 02:33:18 -0700920 transfer->len, MAX_DMA_LEN);
921 message->status = -EINVAL;
922 giveback(drv_data);
923 return;
924 }
925
926 /* warn ... we force this to PIO mode */
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +0300927 dev_warn_ratelimited(&message->spi->dev,
928 "pump_transfers: DMA disabled for transfer length %ld "
929 "greater than %d\n",
930 (long)drv_data->len, MAX_DMA_LEN);
Stephen Street8d94cc52006-12-10 02:18:54 -0800931 }
932
Stephen Streete0c99052006-03-07 23:53:24 -0800933 /* Setup the transfer state based on the type of transfer */
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200934 if (pxa2xx_spi_flush(drv_data) == 0) {
Stephen Streete0c99052006-03-07 23:53:24 -0800935 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
936 message->status = -EIO;
Stephen Street5daa3ba2006-05-20 15:00:19 -0700937 giveback(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -0800938 return;
939 }
Stephen Street9708c122006-03-28 14:05:23 -0800940 drv_data->n_bytes = chip->n_bytes;
Stephen Streete0c99052006-03-07 23:53:24 -0800941 drv_data->tx = (void *)transfer->tx_buf;
942 drv_data->tx_end = drv_data->tx + transfer->len;
943 drv_data->rx = transfer->rx_buf;
944 drv_data->rx_end = drv_data->rx + transfer->len;
945 drv_data->rx_dma = transfer->rx_dma;
946 drv_data->tx_dma = transfer->tx_dma;
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200947 drv_data->len = transfer->len;
Stephen Streete0c99052006-03-07 23:53:24 -0800948 drv_data->write = drv_data->tx ? chip->write : null_writer;
949 drv_data->read = drv_data->rx ? chip->read : null_reader;
Stephen Street9708c122006-03-28 14:05:23 -0800950
951 /* Change speed and bit per word on a per transfer */
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300952 bits = transfer->bits_per_word;
953 speed = transfer->speed_hz;
Stephen Street9708c122006-03-28 14:05:23 -0800954
Andy Shevchenkod2c2f6a2015-10-22 16:44:40 +0300955 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
Stephen Street9708c122006-03-28 14:05:23 -0800956
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300957 if (bits <= 8) {
958 drv_data->n_bytes = 1;
959 drv_data->read = drv_data->read != null_reader ?
960 u8_reader : null_reader;
961 drv_data->write = drv_data->write != null_writer ?
962 u8_writer : null_writer;
963 } else if (bits <= 16) {
964 drv_data->n_bytes = 2;
965 drv_data->read = drv_data->read != null_reader ?
966 u16_reader : null_reader;
967 drv_data->write = drv_data->write != null_writer ?
968 u16_writer : null_writer;
969 } else if (bits <= 32) {
970 drv_data->n_bytes = 4;
971 drv_data->read = drv_data->read != null_reader ?
972 u32_reader : null_reader;
973 drv_data->write = drv_data->write != null_writer ?
974 u32_writer : null_writer;
Stephen Street9708c122006-03-28 14:05:23 -0800975 }
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300976 /*
977 * if bits/word is changed in dma mode, then must check the
978 * thresholds and burst also
979 */
980 if (chip->enable_dma) {
981 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
982 message->spi,
983 bits, &dma_burst,
984 &dma_thresh))
985 dev_warn_ratelimited(&message->spi->dev,
986 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
987 }
988
Andy Shevchenkod74c4b1c2015-10-22 16:44:39 +0300989 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
Jarkko Nikula196b0e22015-09-15 16:26:27 +0300990 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
Andy Shevchenkod74c4b1c2015-10-22 16:44:39 +0300991 if (!pxa25x_ssp_comp(drv_data))
992 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
993 drv_data->master->max_speed_hz
994 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
995 chip->enable_dma ? "DMA" : "PIO");
996 else
997 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
998 drv_data->master->max_speed_hz / 2
999 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1000 chip->enable_dma ? "DMA" : "PIO");
Stephen Street9708c122006-03-28 14:05:23 -08001001
Stephen Streete0c99052006-03-07 23:53:24 -08001002 message->state = RUNNING_STATE;
1003
Ned Forrester7e964452008-09-13 02:33:18 -07001004 drv_data->dma_mapped = 0;
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001005 if (pxa2xx_spi_dma_is_possible(drv_data->len))
1006 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
Ned Forrester7e964452008-09-13 02:33:18 -07001007 if (drv_data->dma_mapped) {
Stephen Streete0c99052006-03-07 23:53:24 -08001008
1009 /* Ensure we have the correct interrupt handler */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001010 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
Stephen Streete0c99052006-03-07 23:53:24 -08001011
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001012 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
Stephen Streete0c99052006-03-07 23:53:24 -08001013
Stephen Street8d94cc52006-12-10 02:18:54 -08001014 /* Clear status and start DMA engine */
1015 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001016 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001017
1018 pxa2xx_spi_dma_start(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001019 } else {
1020 /* Ensure we have the correct interrupt handler */
1021 drv_data->transfer_handler = interrupt_transfer;
1022
Stephen Street8d94cc52006-12-10 02:18:54 -08001023 /* Clear status */
1024 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001025 write_SSSR_CS(drv_data, drv_data->clear_sr);
Stephen Street8d94cc52006-12-10 02:18:54 -08001026 }
1027
Mika Westerberga0d26422013-01-22 12:26:32 +02001028 if (is_lpss_ssp(drv_data)) {
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001029 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1030 != chip->lpss_rx_threshold)
1031 pxa2xx_spi_write(drv_data, SSIRF,
1032 chip->lpss_rx_threshold);
1033 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1034 != chip->lpss_tx_threshold)
1035 pxa2xx_spi_write(drv_data, SSITF,
1036 chip->lpss_tx_threshold);
Mika Westerberga0d26422013-01-22 12:26:32 +02001037 }
1038
Weike Chene5262d02014-11-26 02:35:10 -08001039 if (is_quark_x1000_ssp(drv_data) &&
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001040 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1041 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
Weike Chene5262d02014-11-26 02:35:10 -08001042
Stephen Street8d94cc52006-12-10 02:18:54 -08001043 /* see if we need to reload the config registers */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001044 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1045 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1046 != (cr1 & change_mask)) {
Ned Forresterb97c74b2008-02-23 15:23:40 -08001047 /* stop the SSP, and update the other bits */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001048 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001049 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001050 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001051 /* first set CR1 without interrupt and service enables */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001052 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001053 /* restart the SSP */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001054 pxa2xx_spi_write(drv_data, SSCR0, cr0);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001055
Stephen Street8d94cc52006-12-10 02:18:54 -08001056 } else {
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001057 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001058 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
Stephen Streete0c99052006-03-07 23:53:24 -08001059 }
Ned Forresterb97c74b2008-02-23 15:23:40 -08001060
Eric Miaoa7bb3902009-04-06 19:00:54 -07001061 cs_assert(drv_data);
Ned Forresterb97c74b2008-02-23 15:23:40 -08001062
1063 /* after chip select, release the data by enabling service
1064 * requests and interrupts, without changing any mode bits */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001065 pxa2xx_spi_write(drv_data, SSCR1, cr1);
Stephen Streete0c99052006-03-07 23:53:24 -08001066}
1067
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001068static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1069 struct spi_message *msg)
Stephen Streete0c99052006-03-07 23:53:24 -08001070{
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001071 struct driver_data *drv_data = spi_master_get_devdata(master);
Stephen Streete0c99052006-03-07 23:53:24 -08001072
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001073 drv_data->cur_msg = msg;
Stephen Streete0c99052006-03-07 23:53:24 -08001074 /* Initial message state*/
1075 drv_data->cur_msg->state = START_STATE;
1076 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1077 struct spi_transfer,
1078 transfer_list);
1079
Stephen Street8d94cc52006-12-10 02:18:54 -08001080 /* prepare to setup the SSP, in pump_transfers, using the per
1081 * chip configuration */
Stephen Streete0c99052006-03-07 23:53:24 -08001082 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Stephen Streete0c99052006-03-07 23:53:24 -08001083
1084 /* Mark as busy and launch transfers */
1085 tasklet_schedule(&drv_data->pump_transfers);
Stephen Streete0c99052006-03-07 23:53:24 -08001086 return 0;
1087}
1088
Mika Westerberg7d94a502013-01-22 12:26:30 +02001089static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1090{
1091 struct driver_data *drv_data = spi_master_get_devdata(master);
1092
1093 /* Disable the SSP now */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001094 pxa2xx_spi_write(drv_data, SSCR0,
1095 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
Mika Westerberg7d94a502013-01-22 12:26:30 +02001096
Mika Westerberg7d94a502013-01-22 12:26:30 +02001097 return 0;
1098}
1099
Eric Miaoa7bb3902009-04-06 19:00:54 -07001100static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1101 struct pxa2xx_spi_chip *chip_info)
1102{
1103 int err = 0;
1104
1105 if (chip == NULL || chip_info == NULL)
1106 return 0;
1107
1108 /* NOTE: setup() can be called multiple times, possibly with
1109 * different chip_info, release previously requested GPIO
1110 */
1111 if (gpio_is_valid(chip->gpio_cs))
1112 gpio_free(chip->gpio_cs);
1113
1114 /* If (*cs_control) is provided, ignore GPIO chip select */
1115 if (chip_info->cs_control) {
1116 chip->cs_control = chip_info->cs_control;
1117 return 0;
1118 }
1119
1120 if (gpio_is_valid(chip_info->gpio_cs)) {
1121 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1122 if (err) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001123 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1124 chip_info->gpio_cs);
Eric Miaoa7bb3902009-04-06 19:00:54 -07001125 return err;
1126 }
1127
1128 chip->gpio_cs = chip_info->gpio_cs;
1129 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1130
1131 err = gpio_direction_output(chip->gpio_cs,
1132 !chip->gpio_cs_inverted);
1133 }
1134
1135 return err;
1136}
1137
Stephen Streete0c99052006-03-07 23:53:24 -08001138static int setup(struct spi_device *spi)
1139{
1140 struct pxa2xx_spi_chip *chip_info = NULL;
1141 struct chip_data *chip;
Jarkko Nikuladccf7362015-06-04 16:55:11 +03001142 const struct lpss_config *config;
Stephen Streete0c99052006-03-07 23:53:24 -08001143 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Mika Westerberga0d26422013-01-22 12:26:32 +02001144 uint tx_thres, tx_hi_thres, rx_thres;
1145
Weike Chene5262d02014-11-26 02:35:10 -08001146 switch (drv_data->ssp_type) {
1147 case QUARK_X1000_SSP:
1148 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1149 tx_hi_thres = 0;
1150 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1151 break;
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001152 case LPSS_LPT_SSP:
1153 case LPSS_BYT_SSP:
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001154 case LPSS_SPT_SSP:
Jarkko Nikuladccf7362015-06-04 16:55:11 +03001155 config = lpss_get_config(drv_data);
1156 tx_thres = config->tx_threshold_lo;
1157 tx_hi_thres = config->tx_threshold_hi;
1158 rx_thres = config->rx_threshold;
Weike Chene5262d02014-11-26 02:35:10 -08001159 break;
1160 default:
Mika Westerberga0d26422013-01-22 12:26:32 +02001161 tx_thres = TX_THRESH_DFLT;
1162 tx_hi_thres = 0;
1163 rx_thres = RX_THRESH_DFLT;
Weike Chene5262d02014-11-26 02:35:10 -08001164 break;
Mika Westerberga0d26422013-01-22 12:26:32 +02001165 }
Stephen Streete0c99052006-03-07 23:53:24 -08001166
Stephen Street8d94cc52006-12-10 02:18:54 -08001167 /* Only alloc on first setup */
Stephen Streete0c99052006-03-07 23:53:24 -08001168 chip = spi_get_ctldata(spi);
Stephen Street8d94cc52006-12-10 02:18:54 -08001169 if (!chip) {
Stephen Streete0c99052006-03-07 23:53:24 -08001170 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Jingoo Han9deae452014-04-29 17:19:38 +09001171 if (!chip)
Stephen Streete0c99052006-03-07 23:53:24 -08001172 return -ENOMEM;
1173
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001174 if (drv_data->ssp_type == CE4100_SSP) {
1175 if (spi->chip_select > 4) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001176 dev_err(&spi->dev,
1177 "failed setup: cs number must not be > 4.\n");
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001178 kfree(chip);
1179 return -EINVAL;
1180 }
1181
1182 chip->frm = spi->chip_select;
1183 } else
1184 chip->gpio_cs = -1;
Stephen Streete0c99052006-03-07 23:53:24 -08001185 chip->enable_dma = 0;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001186 chip->timeout = TIMOUT_DFLT;
Stephen Streete0c99052006-03-07 23:53:24 -08001187 }
1188
Stephen Street8d94cc52006-12-10 02:18:54 -08001189 /* protocol drivers may change the chip settings, so...
1190 * if chip_info exists, use it */
1191 chip_info = spi->controller_data;
1192
Stephen Streete0c99052006-03-07 23:53:24 -08001193 /* chip_info isn't always needed */
Stephen Street8d94cc52006-12-10 02:18:54 -08001194 chip->cr1 = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001195 if (chip_info) {
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001196 if (chip_info->timeout)
1197 chip->timeout = chip_info->timeout;
1198 if (chip_info->tx_threshold)
1199 tx_thres = chip_info->tx_threshold;
Mika Westerberga0d26422013-01-22 12:26:32 +02001200 if (chip_info->tx_hi_threshold)
1201 tx_hi_thres = chip_info->tx_hi_threshold;
Vernon Sauderf1f640a2008-10-15 22:02:43 -07001202 if (chip_info->rx_threshold)
1203 rx_thres = chip_info->rx_threshold;
1204 chip->enable_dma = drv_data->master_info->enable_dma;
Stephen Streete0c99052006-03-07 23:53:24 -08001205 chip->dma_threshold = 0;
Stephen Streete0c99052006-03-07 23:53:24 -08001206 if (chip_info->enable_loopback)
1207 chip->cr1 = SSCR1_LBM;
Mika Westerberga3496852013-01-22 12:26:33 +02001208 } else if (ACPI_HANDLE(&spi->dev)) {
1209 /*
1210 * Slave devices enumerated from ACPI namespace don't
1211 * usually have chip_info but we still might want to use
1212 * DMA with them.
1213 */
1214 chip->enable_dma = drv_data->master_info->enable_dma;
Stephen Streete0c99052006-03-07 23:53:24 -08001215 }
1216
Mika Westerberga0d26422013-01-22 12:26:32 +02001217 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1218 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1219 | SSITF_TxHiThresh(tx_hi_thres);
1220
Stephen Street8d94cc52006-12-10 02:18:54 -08001221 /* set dma burst and threshold outside of chip_info path so that if
1222 * chip_info goes away after setting chip->enable_dma, the
1223 * burst and threshold can still respond to changes in bits_per_word */
1224 if (chip->enable_dma) {
1225 /* set up legal burst and threshold for dma */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001226 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1227 spi->bits_per_word,
Stephen Street8d94cc52006-12-10 02:18:54 -08001228 &chip->dma_burst_size,
1229 &chip->dma_threshold)) {
Jarkko Nikulaf6bd03a2013-10-11 13:54:00 +03001230 dev_warn(&spi->dev,
1231 "in setup: DMA burst size reduced to match bits_per_word\n");
Stephen Street8d94cc52006-12-10 02:18:54 -08001232 }
1233 }
1234
Weike Chene5262d02014-11-26 02:35:10 -08001235 switch (drv_data->ssp_type) {
1236 case QUARK_X1000_SSP:
1237 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1238 & QUARK_X1000_SSCR1_RFT)
1239 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1240 & QUARK_X1000_SSCR1_TFT);
1241 break;
1242 default:
1243 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1244 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1245 break;
1246 }
1247
Justin Clacherty7f6ee1a2007-01-26 00:56:44 -08001248 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1249 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1250 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
Stephen Streete0c99052006-03-07 23:53:24 -08001251
Mika Westerbergb8331722013-01-22 12:26:31 +02001252 if (spi->mode & SPI_LOOP)
1253 chip->cr1 |= SSCR1_LBM;
1254
Stephen Streete0c99052006-03-07 23:53:24 -08001255 if (spi->bits_per_word <= 8) {
1256 chip->n_bytes = 1;
Stephen Streete0c99052006-03-07 23:53:24 -08001257 chip->read = u8_reader;
1258 chip->write = u8_writer;
1259 } else if (spi->bits_per_word <= 16) {
1260 chip->n_bytes = 2;
Stephen Streete0c99052006-03-07 23:53:24 -08001261 chip->read = u16_reader;
1262 chip->write = u16_writer;
1263 } else if (spi->bits_per_word <= 32) {
Stephen Streete0c99052006-03-07 23:53:24 -08001264 chip->n_bytes = 4;
Stephen Streete0c99052006-03-07 23:53:24 -08001265 chip->read = u32_reader;
1266 chip->write = u32_writer;
Stephen Streete0c99052006-03-07 23:53:24 -08001267 }
Stephen Streete0c99052006-03-07 23:53:24 -08001268
1269 spi_set_ctldata(spi, chip);
1270
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001271 if (drv_data->ssp_type == CE4100_SSP)
1272 return 0;
1273
Eric Miaoa7bb3902009-04-06 19:00:54 -07001274 return setup_cs(spi, chip, chip_info);
Stephen Streete0c99052006-03-07 23:53:24 -08001275}
1276
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001277static void cleanup(struct spi_device *spi)
Stephen Streete0c99052006-03-07 23:53:24 -08001278{
Hans-Peter Nilsson0ffa0282007-02-12 00:52:45 -08001279 struct chip_data *chip = spi_get_ctldata(spi);
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001280 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001281
Daniel Ribeiro7348d822009-05-12 13:19:36 -07001282 if (!chip)
1283 return;
1284
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001285 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
Eric Miaoa7bb3902009-04-06 19:00:54 -07001286 gpio_free(chip->gpio_cs);
1287
Stephen Streete0c99052006-03-07 23:53:24 -08001288 kfree(chip);
1289}
1290
Mika Westerberga3496852013-01-22 12:26:33 +02001291#ifdef CONFIG_ACPI
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001292
Mathias Krause8422ddf2015-06-13 14:22:14 +02001293static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001294 { "INT33C0", LPSS_LPT_SSP },
1295 { "INT33C1", LPSS_LPT_SSP },
1296 { "INT3430", LPSS_LPT_SSP },
1297 { "INT3431", LPSS_LPT_SSP },
1298 { "80860F0E", LPSS_BYT_SSP },
1299 { "8086228E", LPSS_BYT_SSP },
1300 { },
1301};
1302MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1303
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001304/*
1305 * PCI IDs of compound devices that integrate both host controller and private
1306 * integrated DMA engine. Please note these are not used in module
1307 * autoloading and probing in this module but matching the LPSS SSP type.
1308 */
1309static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1310 /* SPT-LP */
1311 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1312 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1313 /* SPT-H */
1314 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1315 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
Axel Lin94e5c232015-08-04 13:52:22 +08001316 { },
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001317};
1318
1319static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1320{
1321 struct device *dev = param;
1322
1323 if (dev != chan->device->dev->parent)
1324 return false;
1325
1326 return true;
1327}
1328
Mika Westerberga3496852013-01-22 12:26:33 +02001329static struct pxa2xx_spi_master *
1330pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1331{
1332 struct pxa2xx_spi_master *pdata;
Mika Westerberga3496852013-01-22 12:26:33 +02001333 struct acpi_device *adev;
1334 struct ssp_device *ssp;
1335 struct resource *res;
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001336 const struct acpi_device_id *adev_id = NULL;
1337 const struct pci_device_id *pcidev_id = NULL;
Jarkko Nikula3b8b6d02015-10-22 16:44:41 +03001338 unsigned int devid;
1339 int type;
Mika Westerberga3496852013-01-22 12:26:33 +02001340
Jarkko Nikulab9f69402015-09-25 10:27:18 +03001341 adev = ACPI_COMPANION(&pdev->dev);
1342 if (!adev)
Mika Westerberga3496852013-01-22 12:26:33 +02001343 return NULL;
1344
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001345 if (dev_is_pci(pdev->dev.parent))
1346 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1347 to_pci_dev(pdev->dev.parent));
1348 else
1349 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1350 &pdev->dev);
1351
1352 if (adev_id)
1353 type = (int)adev_id->driver_data;
1354 else if (pcidev_id)
1355 type = (int)pcidev_id->driver_data;
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001356 else
1357 return NULL;
1358
Mika Westerbergcc0ee982013-06-20 17:44:22 +03001359 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
Jingoo Han9deae452014-04-29 17:19:38 +09001360 if (!pdata)
Mika Westerberga3496852013-01-22 12:26:33 +02001361 return NULL;
Mika Westerberga3496852013-01-22 12:26:33 +02001362
1363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1364 if (!res)
1365 return NULL;
1366
1367 ssp = &pdata->ssp;
1368
1369 ssp->phys_base = res->start;
Sachin Kamatcbfd6a22013-04-08 15:49:33 +05301370 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1371 if (IS_ERR(ssp->mmio_base))
Mika Westerberg6dc81f62013-05-13 13:45:09 +03001372 return NULL;
Mika Westerberga3496852013-01-22 12:26:33 +02001373
Jarkko Nikula34cadd92015-07-30 16:30:07 +03001374 if (pcidev_id) {
1375 pdata->tx_param = pdev->dev.parent;
1376 pdata->rx_param = pdev->dev.parent;
1377 pdata->dma_filter = pxa2xx_spi_idma_filter;
1378 }
1379
Mika Westerberga3496852013-01-22 12:26:33 +02001380 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1381 ssp->irq = platform_get_irq(pdev, 0);
Jarkko Nikula03fbf482015-06-04 16:55:10 +03001382 ssp->type = type;
Mika Westerberga3496852013-01-22 12:26:33 +02001383 ssp->pdev = pdev;
1384
1385 ssp->port_id = -1;
Jarkko Nikula3b8b6d02015-10-22 16:44:41 +03001386 if (adev->pnp.unique_id && !kstrtouint(adev->pnp.unique_id, 0, &devid))
Mika Westerberga3496852013-01-22 12:26:33 +02001387 ssp->port_id = devid;
1388
1389 pdata->num_chipselect = 1;
Mika Westerbergcddb3392013-05-13 13:45:10 +03001390 pdata->enable_dma = true;
Mika Westerberga3496852013-01-22 12:26:33 +02001391
1392 return pdata;
1393}
1394
Mika Westerberga3496852013-01-22 12:26:33 +02001395#else
1396static inline struct pxa2xx_spi_master *
1397pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1398{
1399 return NULL;
1400}
1401#endif
1402
Grant Likelyfd4a3192012-12-07 16:57:14 +00001403static int pxa2xx_spi_probe(struct platform_device *pdev)
Stephen Streete0c99052006-03-07 23:53:24 -08001404{
1405 struct device *dev = &pdev->dev;
1406 struct pxa2xx_spi_master *platform_info;
1407 struct spi_master *master;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001408 struct driver_data *drv_data;
eric miao2f1a74e2007-11-21 18:50:53 +08001409 struct ssp_device *ssp;
Jarkko Nikula8b136ba2015-10-28 15:13:41 +02001410 const struct lpss_config *config;
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001411 int status;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001412 u32 tmp;
Stephen Streete0c99052006-03-07 23:53:24 -08001413
Mika Westerberg851bacf2013-01-07 12:44:33 +02001414 platform_info = dev_get_platdata(dev);
1415 if (!platform_info) {
Mika Westerberga3496852013-01-22 12:26:33 +02001416 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1417 if (!platform_info) {
1418 dev_err(&pdev->dev, "missing platform data\n");
1419 return -ENODEV;
1420 }
Mika Westerberg851bacf2013-01-07 12:44:33 +02001421 }
Stephen Streete0c99052006-03-07 23:53:24 -08001422
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001423 ssp = pxa_ssp_request(pdev->id, pdev->name);
Mika Westerberg851bacf2013-01-07 12:44:33 +02001424 if (!ssp)
1425 ssp = &platform_info->ssp;
1426
1427 if (!ssp->mmio_base) {
1428 dev_err(&pdev->dev, "failed to get ssp\n");
Stephen Streete0c99052006-03-07 23:53:24 -08001429 return -ENODEV;
1430 }
1431
Jarkko Nikula757fe8d2015-08-05 10:04:05 +03001432 master = spi_alloc_master(dev, sizeof(struct driver_data));
Stephen Streete0c99052006-03-07 23:53:24 -08001433 if (!master) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001434 dev_err(&pdev->dev, "cannot alloc spi_master\n");
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001435 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001436 return -ENOMEM;
1437 }
1438 drv_data = spi_master_get_devdata(master);
1439 drv_data->master = master;
1440 drv_data->master_info = platform_info;
1441 drv_data->pdev = pdev;
eric miao2f1a74e2007-11-21 18:50:53 +08001442 drv_data->ssp = ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001443
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001444 master->dev.parent = &pdev->dev;
Sebastian Andrzej Siewior21486af2010-10-08 18:11:19 +02001445 master->dev.of_node = pdev->dev.of_node;
David Brownelle7db06b2009-06-17 16:26:04 -07001446 /* the spi->mode bits understood by this driver: */
Mika Westerbergb8331722013-01-22 12:26:31 +02001447 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
David Brownelle7db06b2009-06-17 16:26:04 -07001448
Mika Westerberg851bacf2013-01-07 12:44:33 +02001449 master->bus_num = ssp->port_id;
Mike Rapoport7ad0ba92009-04-06 19:00:57 -07001450 master->dma_alignment = DMA_ALIGNMENT;
Stephen Streete0c99052006-03-07 23:53:24 -08001451 master->cleanup = cleanup;
1452 master->setup = setup;
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001453 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
Mika Westerberg7d94a502013-01-22 12:26:30 +02001454 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
Mark Brown7dd62782013-07-28 15:35:21 +01001455 master->auto_runtime_pm = true;
Stephen Streete0c99052006-03-07 23:53:24 -08001456
eric miao2f1a74e2007-11-21 18:50:53 +08001457 drv_data->ssp_type = ssp->type;
Stephen Streete0c99052006-03-07 23:53:24 -08001458
eric miao2f1a74e2007-11-21 18:50:53 +08001459 drv_data->ioaddr = ssp->mmio_base;
1460 drv_data->ssdr_physical = ssp->phys_base + SSDR;
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001461 if (pxa25x_ssp_comp(drv_data)) {
Weike Chene5262d02014-11-26 02:35:10 -08001462 switch (drv_data->ssp_type) {
1463 case QUARK_X1000_SSP:
1464 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1465 break;
1466 default:
1467 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1468 break;
1469 }
1470
Stephen Streete0c99052006-03-07 23:53:24 -08001471 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1472 drv_data->dma_cr1 = 0;
1473 drv_data->clear_sr = SSSR_ROR;
1474 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1475 } else {
Stephen Warren24778be2013-05-21 20:36:35 -06001476 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
Stephen Streete0c99052006-03-07 23:53:24 -08001477 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
Mika Westerberg59288082013-01-22 12:26:29 +02001478 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
Stephen Streete0c99052006-03-07 23:53:24 -08001479 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1480 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1481 }
1482
Sebastian Andrzej Siewior49cbb1e2010-11-22 17:12:14 -08001483 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1484 drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001485 if (status < 0) {
Guennadi Liakhovetski65a00a22008-10-15 22:02:42 -07001486 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
Stephen Streete0c99052006-03-07 23:53:24 -08001487 goto out_error_master_alloc;
1488 }
1489
1490 /* Setup DMA if requested */
Stephen Streete0c99052006-03-07 23:53:24 -08001491 if (platform_info->enable_dma) {
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001492 status = pxa2xx_spi_dma_setup(drv_data);
1493 if (status) {
Mika Westerbergcddb3392013-05-13 13:45:10 +03001494 dev_dbg(dev, "no DMA channels available, using PIO\n");
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001495 platform_info->enable_dma = false;
Stephen Streete0c99052006-03-07 23:53:24 -08001496 }
Stephen Streete0c99052006-03-07 23:53:24 -08001497 }
1498
1499 /* Enable SOC clock */
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001500 clk_prepare_enable(ssp->clk);
1501
Jarkko Nikula0eca7cf2015-09-25 10:27:17 +03001502 master->max_speed_hz = clk_get_rate(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001503
1504 /* Load default SSP configuration */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001505 pxa2xx_spi_write(drv_data, SSCR0, 0);
Weike Chene5262d02014-11-26 02:35:10 -08001506 switch (drv_data->ssp_type) {
1507 case QUARK_X1000_SSP:
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001508 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1509 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1510 pxa2xx_spi_write(drv_data, SSCR1, tmp);
Weike Chene5262d02014-11-26 02:35:10 -08001511
1512 /* using the Motorola SPI protocol and use 8 bit frame */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001513 pxa2xx_spi_write(drv_data, SSCR0,
1514 QUARK_X1000_SSCR0_Motorola
1515 | QUARK_X1000_SSCR0_DataSize(8));
Weike Chene5262d02014-11-26 02:35:10 -08001516 break;
1517 default:
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001518 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1519 SSCR1_TxTresh(TX_THRESH_DFLT);
1520 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1521 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1522 pxa2xx_spi_write(drv_data, SSCR0, tmp);
Weike Chene5262d02014-11-26 02:35:10 -08001523 break;
1524 }
1525
Sebastian Andrzej Siewior2a8626a2010-11-22 17:12:17 -08001526 if (!pxa25x_ssp_comp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001527 pxa2xx_spi_write(drv_data, SSTO, 0);
Weike Chene5262d02014-11-26 02:35:10 -08001528
1529 if (!is_quark_x1000_ssp(drv_data))
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001530 pxa2xx_spi_write(drv_data, SSPSP, 0);
Stephen Streete0c99052006-03-07 23:53:24 -08001531
Jarkko Nikula7566bcc2014-12-18 15:04:20 +02001532 if (is_lpss_ssp(drv_data))
1533 lpss_ssp_setup(drv_data);
Mika Westerberga0d26422013-01-22 12:26:32 +02001534
Jarkko Nikula8b136ba2015-10-28 15:13:41 +02001535 if (is_lpss_ssp(drv_data)) {
1536 lpss_ssp_setup(drv_data);
1537 config = lpss_get_config(drv_data);
1538 if (config->reg_capabilities >= 0) {
1539 tmp = __lpss_ssp_read_priv(drv_data,
1540 config->reg_capabilities);
1541 tmp &= LPSS_CAPS_CS_EN_MASK;
1542 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1543 platform_info->num_chipselect = ffz(tmp);
1544 }
1545 }
1546 master->num_chipselect = platform_info->num_chipselect;
1547
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001548 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1549 (unsigned long)drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001550
Antonio Ospite836d1a22014-05-30 18:18:09 +02001551 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1552 pm_runtime_use_autosuspend(&pdev->dev);
1553 pm_runtime_set_active(&pdev->dev);
1554 pm_runtime_enable(&pdev->dev);
1555
Stephen Streete0c99052006-03-07 23:53:24 -08001556 /* Register with the SPI framework */
1557 platform_set_drvdata(pdev, drv_data);
Jingoo Hana807fcd2013-09-24 13:46:55 +09001558 status = devm_spi_register_master(&pdev->dev, master);
Stephen Streete0c99052006-03-07 23:53:24 -08001559 if (status != 0) {
1560 dev_err(&pdev->dev, "problem registering spi master\n");
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001561 goto out_error_clock_enabled;
Stephen Streete0c99052006-03-07 23:53:24 -08001562 }
1563
1564 return status;
1565
Stephen Streete0c99052006-03-07 23:53:24 -08001566out_error_clock_enabled:
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001567 clk_disable_unprepare(ssp->clk);
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001568 pxa2xx_spi_dma_release(drv_data);
eric miao2f1a74e2007-11-21 18:50:53 +08001569 free_irq(ssp->irq, drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001570
1571out_error_master_alloc:
1572 spi_master_put(master);
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001573 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001574 return status;
1575}
1576
1577static int pxa2xx_spi_remove(struct platform_device *pdev)
1578{
1579 struct driver_data *drv_data = platform_get_drvdata(pdev);
Julia Lawall51e911e2009-01-06 14:41:45 -08001580 struct ssp_device *ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001581
1582 if (!drv_data)
1583 return 0;
Julia Lawall51e911e2009-01-06 14:41:45 -08001584 ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001585
Mika Westerberg7d94a502013-01-22 12:26:30 +02001586 pm_runtime_get_sync(&pdev->dev);
1587
Stephen Streete0c99052006-03-07 23:53:24 -08001588 /* Disable the SSP at the peripheral and SOC level */
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001589 pxa2xx_spi_write(drv_data, SSCR0, 0);
Mika Westerberg3343b7a2013-01-22 12:26:27 +02001590 clk_disable_unprepare(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001591
1592 /* Release DMA */
Mika Westerbergcd7bed02013-01-22 12:26:28 +02001593 if (drv_data->master_info->enable_dma)
1594 pxa2xx_spi_dma_release(drv_data);
Stephen Streete0c99052006-03-07 23:53:24 -08001595
Mika Westerberg7d94a502013-01-22 12:26:30 +02001596 pm_runtime_put_noidle(&pdev->dev);
1597 pm_runtime_disable(&pdev->dev);
1598
Stephen Streete0c99052006-03-07 23:53:24 -08001599 /* Release IRQ */
eric miao2f1a74e2007-11-21 18:50:53 +08001600 free_irq(ssp->irq, drv_data);
1601
1602 /* Release SSP */
Haojian Zhuangbaffe162010-05-05 10:11:15 -04001603 pxa_ssp_free(ssp);
Stephen Streete0c99052006-03-07 23:53:24 -08001604
Stephen Streete0c99052006-03-07 23:53:24 -08001605 return 0;
1606}
1607
1608static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1609{
1610 int status = 0;
1611
1612 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1613 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1614}
1615
Mika Westerberg382cebb2014-01-16 14:50:55 +02001616#ifdef CONFIG_PM_SLEEP
Mike Rapoport86d25932009-07-21 17:50:16 +03001617static int pxa2xx_spi_suspend(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001618{
Mike Rapoport86d25932009-07-21 17:50:16 +03001619 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001620 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001621 int status = 0;
1622
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001623 status = spi_master_suspend(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001624 if (status != 0)
1625 return status;
Jarkko Nikulac039dd22014-12-18 15:04:23 +02001626 pxa2xx_spi_write(drv_data, SSCR0, 0);
Dmitry Eremin-Solenikov2b9375b2014-11-06 14:08:29 +03001627
1628 if (!pm_runtime_suspended(dev))
1629 clk_disable_unprepare(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001630
1631 return 0;
1632}
1633
Mike Rapoport86d25932009-07-21 17:50:16 +03001634static int pxa2xx_spi_resume(struct device *dev)
Stephen Streete0c99052006-03-07 23:53:24 -08001635{
Mike Rapoport86d25932009-07-21 17:50:16 +03001636 struct driver_data *drv_data = dev_get_drvdata(dev);
eric miao2f1a74e2007-11-21 18:50:53 +08001637 struct ssp_device *ssp = drv_data->ssp;
Stephen Streete0c99052006-03-07 23:53:24 -08001638 int status = 0;
1639
1640 /* Enable the SSP clock */
Dmitry Eremin-Solenikov2b9375b2014-11-06 14:08:29 +03001641 if (!pm_runtime_suspended(dev))
1642 clk_prepare_enable(ssp->clk);
Stephen Streete0c99052006-03-07 23:53:24 -08001643
Chew, Chiau Eec50325f2013-11-29 02:13:11 +08001644 /* Restore LPSS private register bits */
Jarkko Nikula48421ad2015-01-28 10:09:42 +02001645 if (is_lpss_ssp(drv_data))
1646 lpss_ssp_setup(drv_data);
Chew, Chiau Eec50325f2013-11-29 02:13:11 +08001647
Stephen Streete0c99052006-03-07 23:53:24 -08001648 /* Start the queue running */
Mika Westerberg7f86bde2013-01-22 12:26:26 +02001649 status = spi_master_resume(drv_data->master);
Stephen Streete0c99052006-03-07 23:53:24 -08001650 if (status != 0) {
Mike Rapoport86d25932009-07-21 17:50:16 +03001651 dev_err(dev, "problem starting queue (%d)\n", status);
Stephen Streete0c99052006-03-07 23:53:24 -08001652 return status;
1653 }
1654
1655 return 0;
1656}
Mika Westerberg7d94a502013-01-22 12:26:30 +02001657#endif
1658
Rafael J. Wysockiec833052014-12-13 00:41:15 +01001659#ifdef CONFIG_PM
Mika Westerberg7d94a502013-01-22 12:26:30 +02001660static int pxa2xx_spi_runtime_suspend(struct device *dev)
1661{
1662 struct driver_data *drv_data = dev_get_drvdata(dev);
1663
1664 clk_disable_unprepare(drv_data->ssp->clk);
1665 return 0;
1666}
1667
1668static int pxa2xx_spi_runtime_resume(struct device *dev)
1669{
1670 struct driver_data *drv_data = dev_get_drvdata(dev);
1671
1672 clk_prepare_enable(drv_data->ssp->clk);
1673 return 0;
1674}
1675#endif
Mike Rapoport86d25932009-07-21 17:50:16 +03001676
Alexey Dobriyan47145212009-12-14 18:00:08 -08001677static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
Mika Westerberg7d94a502013-01-22 12:26:30 +02001678 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1679 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1680 pxa2xx_spi_runtime_resume, NULL)
Mike Rapoport86d25932009-07-21 17:50:16 +03001681};
Stephen Streete0c99052006-03-07 23:53:24 -08001682
1683static struct platform_driver driver = {
1684 .driver = {
Mike Rapoport86d25932009-07-21 17:50:16 +03001685 .name = "pxa2xx-spi",
Mike Rapoport86d25932009-07-21 17:50:16 +03001686 .pm = &pxa2xx_spi_pm_ops,
Mika Westerberga3496852013-01-22 12:26:33 +02001687 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
Stephen Streete0c99052006-03-07 23:53:24 -08001688 },
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001689 .probe = pxa2xx_spi_probe,
David Brownelld1e44d92007-10-16 01:27:46 -07001690 .remove = pxa2xx_spi_remove,
Stephen Streete0c99052006-03-07 23:53:24 -08001691 .shutdown = pxa2xx_spi_shutdown,
Stephen Streete0c99052006-03-07 23:53:24 -08001692};
1693
1694static int __init pxa2xx_spi_init(void)
1695{
Sebastian Andrzej Siewiorfbd29a12010-11-19 09:00:11 -08001696 return platform_driver_register(&driver);
Stephen Streete0c99052006-03-07 23:53:24 -08001697}
Antonio Ospite5b61a742009-09-22 16:46:10 -07001698subsys_initcall(pxa2xx_spi_init);
Stephen Streete0c99052006-03-07 23:53:24 -08001699
1700static void __exit pxa2xx_spi_exit(void)
1701{
1702 platform_driver_unregister(&driver);
1703}
1704module_exit(pxa2xx_spi_exit);