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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +000028#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000029#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capper2f4620f2014-01-15 14:07:13 +000031#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +000032#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
36 */
Catalin Marinas4b905a82013-10-23 16:50:07 +010037#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000038#define VMALLOC_END (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
39
40#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
41
42#define FIRST_USER_ADDRESS 0
43
44#ifndef __ASSEMBLY__
45extern void __pte_error(const char *file, int line, unsigned long val);
46extern void __pmd_error(const char *file, int line, unsigned long val);
47extern void __pgd_error(const char *file, int line, unsigned long val);
48
49#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
50#ifndef CONFIG_ARM64_64K_PAGES
51#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
52#endif
53#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
54
Catalin Marinas8b343c862014-04-03 15:57:15 +010055#ifdef CONFIG_SMP
56#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
57#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
58#else
59#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF)
60#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF)
61#endif
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000062
Catalin Marinas8b343c862014-04-03 15:57:15 +010063#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
64#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
65#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000066
Catalin Marinas8b343c862014-04-03 15:57:15 +010067#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
68#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
69#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000070
Catalin Marinas8b343c862014-04-03 15:57:15 +010071#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
Will Deacona6fadf72012-12-18 14:15:15 +000072
Catalin Marinas8b343c862014-04-03 15:57:15 +010073#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
74#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000075
Catalin Marinas8b343c862014-04-03 15:57:15 +010076#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
77#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000078
Catalin Marinas8b343c862014-04-03 15:57:15 +010079#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
80#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000081
Catalin Marinas8b343c862014-04-03 15:57:15 +010082#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
83#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
85#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
86#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
87#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
88#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000089
Catalin Marinas8b343c862014-04-03 15:57:15 +010090#define __P000 PAGE_NONE
91#define __P001 PAGE_READONLY
92#define __P010 PAGE_COPY
93#define __P011 PAGE_COPY
Catalin Marinas5af70c92014-05-16 16:44:32 +010094#define __P100 PAGE_READONLY_EXEC
Catalin Marinas8b343c862014-04-03 15:57:15 +010095#define __P101 PAGE_READONLY_EXEC
96#define __P110 PAGE_COPY_EXEC
97#define __P111 PAGE_COPY_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000098
Catalin Marinas8b343c862014-04-03 15:57:15 +010099#define __S000 PAGE_NONE
100#define __S001 PAGE_READONLY
101#define __S010 PAGE_SHARED
102#define __S011 PAGE_SHARED
Catalin Marinas5af70c92014-05-16 16:44:32 +0100103#define __S100 PAGE_READONLY_EXEC
Catalin Marinas8b343c862014-04-03 15:57:15 +0100104#define __S101 PAGE_READONLY_EXEC
105#define __S110 PAGE_SHARED_EXEC
106#define __S111 PAGE_SHARED_EXEC
107
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000108/*
109 * ZERO_PAGE is a global shared page that is always zero: used
110 * for zero-mapped memory areas etc..
111 */
112extern struct page *empty_zero_page;
113#define ZERO_PAGE(vaddr) (empty_zero_page)
114
115#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
116
117#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
118
119#define pte_none(pte) (!pte_val(pte))
120#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
121#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Will Deacon712bda62013-06-10 19:34:41 +0100122#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000123
124#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
125#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
126#define pte_unmap(pte) do { } while (0)
127#define pte_unmap_nested(pte) do { } while (0)
128
129/*
130 * The following only work if pte_present(). Undefined behaviour otherwise.
131 */
Steve Capper2457c272014-02-25 11:38:53 +0000132#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
133#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
134#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
135#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
136#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000137#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000138
Catalin Marinas5af70c92014-05-16 16:44:32 +0100139#define pte_valid_user(pte) \
140 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas6dca4f12014-06-09 11:55:03 +0100141#define pte_valid_not_user(pte) \
142 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000143
Laura Abbott73cf4132014-08-19 20:41:42 +0100144static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
145{
146 pte_val(pte) &= ~pgprot_val(prot);
147 return pte;
148}
149
150static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
151{
152 pte_val(pte) |= pgprot_val(prot);
153 return pte;
154}
155
Steve Capper93701032014-01-15 14:07:12 +0000156static inline pte_t pte_wrprotect(pte_t pte)
157{
Laura Abbott73cf4132014-08-19 20:41:42 +0100158 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
Steve Capper93701032014-01-15 14:07:12 +0000159}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000160
Steve Capper93701032014-01-15 14:07:12 +0000161static inline pte_t pte_mkwrite(pte_t pte)
162{
Laura Abbott73cf4132014-08-19 20:41:42 +0100163 return set_pte_bit(pte, __pgprot(PTE_WRITE));
Steve Capper93701032014-01-15 14:07:12 +0000164}
165
166static inline pte_t pte_mkclean(pte_t pte)
167{
Laura Abbott73cf4132014-08-19 20:41:42 +0100168 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
Steve Capper93701032014-01-15 14:07:12 +0000169}
170
171static inline pte_t pte_mkdirty(pte_t pte)
172{
Laura Abbott73cf4132014-08-19 20:41:42 +0100173 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
Steve Capper93701032014-01-15 14:07:12 +0000174}
175
176static inline pte_t pte_mkold(pte_t pte)
177{
Laura Abbott73cf4132014-08-19 20:41:42 +0100178 return clear_pte_bit(pte, __pgprot(PTE_AF));
Steve Capper93701032014-01-15 14:07:12 +0000179}
180
181static inline pte_t pte_mkyoung(pte_t pte)
182{
Laura Abbott73cf4132014-08-19 20:41:42 +0100183 return set_pte_bit(pte, __pgprot(PTE_AF));
Steve Capper93701032014-01-15 14:07:12 +0000184}
185
186static inline pte_t pte_mkspecial(pte_t pte)
187{
Laura Abbott73cf4132014-08-19 20:41:42 +0100188 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
Steve Capper93701032014-01-15 14:07:12 +0000189}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000190
191static inline void set_pte(pte_t *ptep, pte_t pte)
192{
193 *ptep = pte;
Catalin Marinas6dca4f12014-06-09 11:55:03 +0100194
195 /*
196 * Only if the new pte is valid and kernel, otherwise TLB maintenance
197 * or update_mmu_cache() have the necessary barriers.
198 */
199 if (pte_valid_not_user(pte)) {
200 dsb(ishst);
201 isb();
202 }
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000203}
204
205extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
206
207static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
208 pte_t *ptep, pte_t pte)
209{
Catalin Marinas5af70c92014-05-16 16:44:32 +0100210 if (pte_valid_user(pte)) {
Catalin Marinas5aab0862014-03-12 16:28:09 +0000211 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000212 __sync_icache_dcache(pte, addr);
Steve Capper2f4620f2014-01-15 14:07:13 +0000213 if (pte_dirty(pte) && pte_write(pte))
214 pte_val(pte) &= ~PTE_RDONLY;
215 else
216 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000217 }
218
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000219 set_pte(ptep, pte);
220}
221
222/*
223 * Huge pte definitions.
224 */
Steve Capper3b5a3a62013-04-10 13:48:00 +0100225#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
226#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
227
228/*
229 * Hugetlb definitions.
230 */
231#define HUGE_MAX_HSTATE 2
232#define HPAGE_SHIFT PMD_SHIFT
233#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
234#define HPAGE_MASK (~(HPAGE_SIZE - 1))
235#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000236
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000237#define __HAVE_ARCH_PTE_SPECIAL
238
Steve Capperae635c72014-02-25 10:02:13 +0000239static inline pte_t pmd_pte(pmd_t pmd)
240{
241 return __pte(pmd_val(pmd));
242}
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100243
Steve Capperae635c72014-02-25 10:02:13 +0000244static inline pmd_t pte_pmd(pte_t pte)
245{
246 return __pmd(pte_val(pte));
247}
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100248
249/*
250 * THP definitions.
251 */
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100252
253#ifdef CONFIG_TRANSPARENT_HUGEPAGE
254#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
Steve Capperae635c72014-02-25 10:02:13 +0000255#define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd))
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100256#endif
257
Steve Capperae635c72014-02-25 10:02:13 +0000258#define pmd_young(pmd) pte_young(pmd_pte(pmd))
259#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
260#define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd)))
261#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
262#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
263#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
264#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
Will Deacon84f329f2014-06-18 14:06:27 +0100265#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100266
Steve Capperae635c72014-02-25 10:02:13 +0000267#define __HAVE_ARCH_PMD_WRITE
268#define pmd_write(pmd) pte_write(pmd_pte(pmd))
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100269
270#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
271
272#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
273#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
274#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
275
276#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
277
Will Deacon263d7732014-05-27 19:11:58 +0100278#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100279
280static inline int has_transparent_hugepage(void)
281{
282 return 1;
283}
284
Catalin Marinas8b343c862014-04-03 15:57:15 +0100285#define __pgprot_modify(prot,mask,bits) \
286 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
287
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100288/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000289 * Mark the prot value as uncacheable and unbufferable.
290 */
291#define pgprot_noncached(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000292 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000293#define pgprot_writecombine(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000294 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000295#define pgprot_dmacoherent(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000296 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000297#define __HAVE_PHYS_MEM_ACCESS_PROT
298struct file;
299extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
300 unsigned long size, pgprot_t vma_prot);
301
302#define pmd_none(pmd) (!pmd_val(pmd))
303#define pmd_present(pmd) (pmd_val(pmd))
304
305#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
306
Marc Zyngier20f2b5c2012-12-07 18:35:41 +0000307#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
308 PMD_TYPE_TABLE)
309#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
310 PMD_TYPE_SECT)
311
312
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000313static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
314{
315 *pmdp = pmd;
Will Deacon2b3a92c2014-05-02 16:24:10 +0100316 dsb(ishst);
Catalin Marinas6dca4f12014-06-09 11:55:03 +0100317 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000318}
319
320static inline void pmd_clear(pmd_t *pmdp)
321{
322 set_pmd(pmdp, __pmd(0));
323}
324
325static inline pte_t *pmd_page_vaddr(pmd_t pmd)
326{
327 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
328}
329
330#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
331
332/*
333 * Conversion functions: convert a page and protection to a page entry,
334 * and a page entry and page directory to the page they refer to.
335 */
336#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
337
338#ifndef CONFIG_ARM64_64K_PAGES
339
340#define pud_none(pud) (!pud_val(pud))
341#define pud_bad(pud) (!(pud_val(pud) & 2))
342#define pud_present(pud) (pud_val(pud))
343
344static inline void set_pud(pud_t *pudp, pud_t pud)
345{
346 *pudp = pud;
Will Deacon2b3a92c2014-05-02 16:24:10 +0100347 dsb(ishst);
Catalin Marinas6dca4f12014-06-09 11:55:03 +0100348 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000349}
350
351static inline void pud_clear(pud_t *pudp)
352{
353 set_pud(pudp, __pud(0));
354}
355
356static inline pmd_t *pud_page_vaddr(pud_t pud)
357{
358 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
359}
360
361#endif /* CONFIG_ARM64_64K_PAGES */
362
363/* to find an entry in a page-table-directory */
364#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
365
366#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
367
368/* to find an entry in a kernel page-table-directory */
369#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
370
371/* Find an entry in the second-level page table.. */
372#ifndef CONFIG_ARM64_64K_PAGES
373#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
374static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
375{
376 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
377}
378#endif
379
380/* Find an entry in the third-level page table.. */
Will Deacon712bda62013-06-10 19:34:41 +0100381#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000382
383static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
384{
Will Deacona6fadf72012-12-18 14:15:15 +0000385 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Steve Capper2f4620f2014-01-15 14:07:13 +0000386 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000387 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
388 return pte;
389}
390
Steve Capperae635c72014-02-25 10:02:13 +0000391static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
392{
393 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
394}
395
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000396extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
397extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
398
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000399/*
400 * Encode and decode a swap entry:
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000401 * bits 0-1: present (must be zero)
402 * bit 2: PTE_FILE
403 * bits 3-8: swap type
404 * bits 9-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000405 */
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000406#define __SWP_TYPE_SHIFT 3
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000407#define __SWP_TYPE_BITS 6
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000408#define __SWP_OFFSET_BITS 49
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000409#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
410#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000411#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000412
413#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000414#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000415#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
416
417#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
418#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
419
420/*
421 * Ensure that there are not more swap files than can be encoded in the kernel
Geert Uytterhoeven7d7a38f2014-03-11 11:23:39 +0100422 * PTEs.
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000423 */
424#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
425
426/*
427 * Encode and decode a file entry:
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000428 * bits 0-1: present (must be zero)
429 * bit 2: PTE_FILE
430 * bits 3-57: file offset / PAGE_SIZE
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000431 */
432#define pte_file(pte) (pte_val(pte) & PTE_FILE)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000433#define pte_to_pgoff(x) (pte_val(x) >> 3)
434#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000435
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000436#define PTE_FILE_MAX_BITS 55
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000437
438extern int kern_addr_valid(unsigned long addr);
439
440#include <asm-generic/pgtable.h>
441
442/*
443 * remap a physical page `pfn' of size `size' with page protection `prot'
444 * into virtual address `from'
445 */
446#define io_remap_pfn_range(vma,from,pfn,size,prot) \
447 remap_pfn_range(vma, from, pfn, size, prot)
448
449#define pgtable_cache_init() do { } while (0)
450
451#endif /* !__ASSEMBLY__ */
452
453#endif /* __ASM_PGTABLE_H */