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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +000028#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000029#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capper2f4620f2014-01-15 14:07:13 +000031#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +000032#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000033
34/*
35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
36 */
Catalin Marinas4b905a82013-10-23 16:50:07 +010037#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000038#define VMALLOC_END (PAGE_OFFSET - UL(0x400000000) - SZ_64K)
39
40#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
41
42#define FIRST_USER_ADDRESS 0
43
44#ifndef __ASSEMBLY__
45extern void __pte_error(const char *file, int line, unsigned long val);
46extern void __pmd_error(const char *file, int line, unsigned long val);
47extern void __pgd_error(const char *file, int line, unsigned long val);
48
49#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
50#ifndef CONFIG_ARM64_64K_PAGES
51#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
52#endif
53#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
54
55/*
56 * The pgprot_* and protection_map entries will be fixed up at runtime to
57 * include the cachable and bufferable bits based on memory policy, as well as
58 * any architecture dependent bits like global/ASID and SMP shared mapping
59 * bits.
60 */
61#define _PAGE_DEFAULT PTE_TYPE_PAGE | PTE_AF
62
63extern pgprot_t pgprot_default;
64
Will Deacona6fadf72012-12-18 14:15:15 +000065#define __pgprot_modify(prot,mask,bits) \
66 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000067
Will Deacona6fadf72012-12-18 14:15:15 +000068#define _MOD_PROT(p, b) __pgprot_modify(p, 0, b)
69
Steve Capper2f4620f2014-01-15 14:07:13 +000070#define PAGE_NONE __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_PXN | PTE_UXN)
71#define PAGE_SHARED _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
72#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
73#define PAGE_COPY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
74#define PAGE_COPY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
75#define PAGE_READONLY _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
76#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
77#define PAGE_KERNEL _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
78#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000079
Mark Brownae419442014-04-14 18:25:05 +010080#define __PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
Steve Capper2f4620f2014-01-15 14:07:13 +000081#define __PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
82#define __PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
83#define __PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
84#define __PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
85#define __PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
86#define __PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000087
88#endif /* __ASSEMBLY__ */
89
90#define __P000 __PAGE_NONE
91#define __P001 __PAGE_READONLY
92#define __P010 __PAGE_COPY
93#define __P011 __PAGE_COPY
94#define __P100 __PAGE_READONLY_EXEC
95#define __P101 __PAGE_READONLY_EXEC
96#define __P110 __PAGE_COPY_EXEC
97#define __P111 __PAGE_COPY_EXEC
98
99#define __S000 __PAGE_NONE
100#define __S001 __PAGE_READONLY
101#define __S010 __PAGE_SHARED
102#define __S011 __PAGE_SHARED
103#define __S100 __PAGE_READONLY_EXEC
104#define __S101 __PAGE_READONLY_EXEC
105#define __S110 __PAGE_SHARED_EXEC
106#define __S111 __PAGE_SHARED_EXEC
107
108#ifndef __ASSEMBLY__
109/*
110 * ZERO_PAGE is a global shared page that is always zero: used
111 * for zero-mapped memory areas etc..
112 */
113extern struct page *empty_zero_page;
114#define ZERO_PAGE(vaddr) (empty_zero_page)
115
116#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
117
118#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
119
120#define pte_none(pte) (!pte_val(pte))
121#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
122#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Will Deacon712bda62013-06-10 19:34:41 +0100123#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000124
125#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
126#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
127#define pte_unmap(pte) do { } while (0)
128#define pte_unmap_nested(pte) do { } while (0)
129
130/*
131 * The following only work if pte_present(). Undefined behaviour otherwise.
132 */
Steve Capper2457c272014-02-25 11:38:53 +0000133#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
134#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
135#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
136#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
137#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000138#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000139
Will Deacona6fadf72012-12-18 14:15:15 +0000140#define pte_valid_user(pte) \
Will Deacon02522462013-01-09 11:08:10 +0000141 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000142
Steve Capper93701032014-01-15 14:07:12 +0000143static inline pte_t pte_wrprotect(pte_t pte)
144{
Steve Capper2f4620f2014-01-15 14:07:13 +0000145 pte_val(pte) &= ~PTE_WRITE;
Steve Capper93701032014-01-15 14:07:12 +0000146 return pte;
147}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000148
Steve Capper93701032014-01-15 14:07:12 +0000149static inline pte_t pte_mkwrite(pte_t pte)
150{
Steve Capper2f4620f2014-01-15 14:07:13 +0000151 pte_val(pte) |= PTE_WRITE;
Steve Capper93701032014-01-15 14:07:12 +0000152 return pte;
153}
154
155static inline pte_t pte_mkclean(pte_t pte)
156{
157 pte_val(pte) &= ~PTE_DIRTY;
158 return pte;
159}
160
161static inline pte_t pte_mkdirty(pte_t pte)
162{
163 pte_val(pte) |= PTE_DIRTY;
164 return pte;
165}
166
167static inline pte_t pte_mkold(pte_t pte)
168{
169 pte_val(pte) &= ~PTE_AF;
170 return pte;
171}
172
173static inline pte_t pte_mkyoung(pte_t pte)
174{
175 pte_val(pte) |= PTE_AF;
176 return pte;
177}
178
179static inline pte_t pte_mkspecial(pte_t pte)
180{
181 pte_val(pte) |= PTE_SPECIAL;
182 return pte;
183}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000184
185static inline void set_pte(pte_t *ptep, pte_t pte)
186{
187 *ptep = pte;
188}
189
190extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
191
192static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
193 pte_t *ptep, pte_t pte)
194{
Will Deacona6fadf72012-12-18 14:15:15 +0000195 if (pte_valid_user(pte)) {
Catalin Marinas5aab0862014-03-12 16:28:09 +0000196 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000197 __sync_icache_dcache(pte, addr);
Steve Capper2f4620f2014-01-15 14:07:13 +0000198 if (pte_dirty(pte) && pte_write(pte))
199 pte_val(pte) &= ~PTE_RDONLY;
200 else
201 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000202 }
203
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000204 set_pte(ptep, pte);
205}
206
207/*
208 * Huge pte definitions.
209 */
Steve Capper3b5a3a62013-04-10 13:48:00 +0100210#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
211#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
212
213/*
214 * Hugetlb definitions.
215 */
216#define HUGE_MAX_HSTATE 2
217#define HPAGE_SHIFT PMD_SHIFT
218#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
219#define HPAGE_MASK (~(HPAGE_SIZE - 1))
220#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000221
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000222#define __HAVE_ARCH_PTE_SPECIAL
223
224/*
Steve Capperd9ccf6b2013-04-19 16:23:57 +0100225 * Software PMD bits for THP
226 */
227
228#define PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
229#define PMD_SECT_SPLITTING (_AT(pmdval_t, 1) << 57)
230
231/*
232 * THP definitions.
233 */
234#define pmd_young(pmd) (pmd_val(pmd) & PMD_SECT_AF)
235
236#define __HAVE_ARCH_PMD_WRITE
237#define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY))
238
239#ifdef CONFIG_TRANSPARENT_HUGEPAGE
240#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
241#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
242#endif
243
244#define PMD_BIT_FUNC(fn,op) \
245static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
246
247PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
248PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
249PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
250PMD_BIT_FUNC(mkwrite, &= ~PMD_SECT_RDONLY);
251PMD_BIT_FUNC(mkdirty, |= PMD_SECT_DIRTY);
252PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
253PMD_BIT_FUNC(mknotpresent, &= ~PMD_TYPE_MASK);
254
255#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
256
257#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
258#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
259#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
260
261#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
262
263static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
264{
265 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_PXN | PMD_SECT_UXN |
266 PMD_SECT_RDONLY | PMD_SECT_PROT_NONE |
267 PMD_SECT_VALID;
268 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
269 return pmd;
270}
271
272#define set_pmd_at(mm, addr, pmdp, pmd) set_pmd(pmdp, pmd)
273
274static inline int has_transparent_hugepage(void)
275{
276 return 1;
277}
278
279/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000280 * Mark the prot value as uncacheable and unbufferable.
281 */
282#define pgprot_noncached(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000283 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000284#define pgprot_writecombine(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000285 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000286#define pgprot_dmacoherent(prot) \
Catalin Marinase4cb9732014-03-12 16:07:06 +0000287 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000288#define __HAVE_PHYS_MEM_ACCESS_PROT
289struct file;
290extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
291 unsigned long size, pgprot_t vma_prot);
292
293#define pmd_none(pmd) (!pmd_val(pmd))
294#define pmd_present(pmd) (pmd_val(pmd))
295
296#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
297
298static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
299{
300 *pmdp = pmd;
301 dsb();
302}
303
304static inline void pmd_clear(pmd_t *pmdp)
305{
306 set_pmd(pmdp, __pmd(0));
307}
308
309static inline pte_t *pmd_page_vaddr(pmd_t pmd)
310{
311 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
312}
313
314#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
315
316/*
317 * Conversion functions: convert a page and protection to a page entry,
318 * and a page entry and page directory to the page they refer to.
319 */
320#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
321
322#ifndef CONFIG_ARM64_64K_PAGES
323
324#define pud_none(pud) (!pud_val(pud))
325#define pud_bad(pud) (!(pud_val(pud) & 2))
326#define pud_present(pud) (pud_val(pud))
327
328static inline void set_pud(pud_t *pudp, pud_t pud)
329{
330 *pudp = pud;
331 dsb();
332}
333
334static inline void pud_clear(pud_t *pudp)
335{
336 set_pud(pudp, __pud(0));
337}
338
339static inline pmd_t *pud_page_vaddr(pud_t pud)
340{
341 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
342}
343
344#endif /* CONFIG_ARM64_64K_PAGES */
345
346/* to find an entry in a page-table-directory */
347#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
348
349#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
350
351/* to find an entry in a kernel page-table-directory */
352#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
353
354/* Find an entry in the second-level page table.. */
355#ifndef CONFIG_ARM64_64K_PAGES
356#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
357static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
358{
359 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
360}
361#endif
362
363/* Find an entry in the third-level page table.. */
Will Deacon712bda62013-06-10 19:34:41 +0100364#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000365
366static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
367{
Will Deacona6fadf72012-12-18 14:15:15 +0000368 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Steve Capper2f4620f2014-01-15 14:07:13 +0000369 PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000370 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
371 return pte;
372}
373
374extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
375extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
376
377#define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
378#define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
379
380/*
381 * Encode and decode a swap entry:
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000382 * bits 0-1: present (must be zero)
383 * bit 2: PTE_FILE
384 * bits 3-8: swap type
385 * bits 9-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000386 */
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000387#define __SWP_TYPE_SHIFT 3
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000388#define __SWP_TYPE_BITS 6
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000389#define __SWP_OFFSET_BITS 49
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000390#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
391#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000392#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000393
394#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000395#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000396#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
397
398#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
399#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
400
401/*
402 * Ensure that there are not more swap files than can be encoded in the kernel
403 * the PTEs.
404 */
405#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
406
407/*
408 * Encode and decode a file entry:
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000409 * bits 0-1: present (must be zero)
410 * bit 2: PTE_FILE
411 * bits 3-57: file offset / PAGE_SIZE
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000412 */
413#define pte_file(pte) (pte_val(pte) & PTE_FILE)
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000414#define pte_to_pgoff(x) (pte_val(x) >> 3)
415#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000416
Catalin Marinas6d9c4ff2013-11-27 16:59:27 +0000417#define PTE_FILE_MAX_BITS 55
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000418
419extern int kern_addr_valid(unsigned long addr);
420
421#include <asm-generic/pgtable.h>
422
423/*
424 * remap a physical page `pfn' of size `size' with page protection `prot'
425 * into virtual address `from'
426 */
427#define io_remap_pfn_range(vma,from,pfn,size,prot) \
428 remap_pfn_range(vma, from, pfn, size, prot)
429
430#define pgtable_cache_init() do { } while (0)
431
432#endif /* !__ASSEMBLY__ */
433
434#endif /* __ASM_PGTABLE_H */