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Komal Shah010d442c42006-08-13 23:44:09 +02001/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
Komal Shah010d442c42006-08-13 23:44:09 +02005 * Copyright (C) 2005 Nokia Corporation
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08006 * Copyright (C) 2004 - 2007 Texas Instruments.
Komal Shah010d442c42006-08-13 23:44:09 +02007 *
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08008 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
Komal Shah010d442c42006-08-13 23:44:09 +020015 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
Tony Lindgrenc1a473b2008-11-21 13:39:47 -080039#include <linux/io.h>
Benoit Cousson61451972011-12-22 15:56:36 +010040#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090043#include <linux/slab.h>
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -070044#include <linux/i2c-omap.h>
Rajendra Nayak27b1fec2010-09-28 21:02:58 +053045#include <linux/pm_runtime.h>
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +000046#include <linux/pinctrl/consumer.h>
Komal Shah010d442c42006-08-13 23:44:09 +020047
Paul Walmsley9c76b872008-11-21 13:39:55 -080048/* I2C controller revisions */
Andy Green4e80f722011-05-30 07:43:07 -070049#define OMAP_I2C_OMAP1_REV_2 0x20
Paul Walmsley9c76b872008-11-21 13:39:55 -080050
51/* I2C controller revisions present on specific hardware */
Shubhrajyoti D47dcd012012-11-05 17:53:36 +053052#define OMAP_I2C_REV_ON_2430 0x00000036
53#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
54#define OMAP_I2C_REV_ON_3630 0x00000040
55#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
Paul Walmsley9c76b872008-11-21 13:39:55 -080056
Komal Shah010d442c42006-08-13 23:44:09 +020057/* timeout waiting for the controller to respond */
58#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
59
Felipe Balbi6d8451d2012-09-12 16:28:15 +053060/* timeout for pm runtime autosuspend */
61#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
62
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -080063/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070064enum {
65 OMAP_I2C_REV_REG = 0,
66 OMAP_I2C_IE_REG,
67 OMAP_I2C_STAT_REG,
68 OMAP_I2C_IV_REG,
69 OMAP_I2C_WE_REG,
70 OMAP_I2C_SYSS_REG,
71 OMAP_I2C_BUF_REG,
72 OMAP_I2C_CNT_REG,
73 OMAP_I2C_DATA_REG,
74 OMAP_I2C_SYSC_REG,
75 OMAP_I2C_CON_REG,
76 OMAP_I2C_OA_REG,
77 OMAP_I2C_SA_REG,
78 OMAP_I2C_PSC_REG,
79 OMAP_I2C_SCLL_REG,
80 OMAP_I2C_SCLH_REG,
81 OMAP_I2C_SYSTEST_REG,
82 OMAP_I2C_BUFSTAT_REG,
Andy Greenb8853082011-05-30 07:43:04 -070083 /* only on OMAP4430 */
84 OMAP_I2C_IP_V2_REVNB_LO,
85 OMAP_I2C_IP_V2_REVNB_HI,
86 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
87 OMAP_I2C_IP_V2_IRQENABLE_SET,
88 OMAP_I2C_IP_V2_IRQENABLE_CLR,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070089};
Komal Shah010d442c42006-08-13 23:44:09 +020090
91/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -080092#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
93#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
Komal Shah010d442c42006-08-13 23:44:09 +020094#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
95#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
96#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
97#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
98#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
99
100/* I2C Status Register (OMAP_I2C_STAT): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800101#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
102#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
Komal Shah010d442c42006-08-13 23:44:09 +0200103#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
104#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
105#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
106#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
107#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
108#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
109#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
110#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
111#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
112#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
113
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800114/* I2C WE wakeup enable register */
115#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
116#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
117#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
118#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
119#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
120#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
121#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
122#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
123#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
124#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
125
126#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
127 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
128 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
129 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
130 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
131
Komal Shah010d442c42006-08-13 23:44:09 +0200132/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
133#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800134#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200135#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800136#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200137
138/* I2C Configuration Register (OMAP_I2C_CON): */
139#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
140#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800141#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
Komal Shah010d442c42006-08-13 23:44:09 +0200142#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
143#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
144#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
145#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
146#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
147#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
148#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
149
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800150/* I2C SCL time value when Master */
151#define OMAP_I2C_SCLL_HSSCLL 8
152#define OMAP_I2C_SCLH_HSSCLH 8
153
Komal Shah010d442c42006-08-13 23:44:09 +0200154/* I2C System Test Register (OMAP_I2C_SYSTEST): */
155#ifdef DEBUG
156#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
157#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
158#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
159#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
160#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
161#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
162#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
163#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
164#endif
165
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800166/* OCP_SYSSTATUS bit definitions */
167#define SYSS_RESETDONE_MASK (1 << 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200168
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800169/* OCP_SYSCONFIG bit definitions */
170#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
171#define SYSC_SIDLEMODE_MASK (0x3 << 3)
172#define SYSC_ENAWAKEUP_MASK (1 << 2)
173#define SYSC_SOFTRESET_MASK (1 << 1)
174#define SYSC_AUTOIDLE_MASK (1 << 0)
175
176#define SYSC_IDLEMODE_SMART 0x2
177#define SYSC_CLOCKACTIVITY_FCLK 0x2
178
manjugk manjugkf3083d92010-05-11 11:35:20 -0700179/* Errata definitions */
180#define I2C_OMAP_ERRATA_I207 (1 << 0)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530181#define I2C_OMAP_ERRATA_I462 (1 << 1)
Komal Shah010d442c42006-08-13 23:44:09 +0200182
Komal Shah010d442c42006-08-13 23:44:09 +0200183struct omap_i2c_dev {
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530184 spinlock_t lock; /* IRQ synchronization */
Komal Shah010d442c42006-08-13 23:44:09 +0200185 struct device *dev;
186 void __iomem *base; /* virtual */
187 int irq;
Cory Maccarroned84d3ea2009-12-12 17:54:02 -0800188 int reg_shift; /* bit shift for I2C register addresses */
Komal Shah010d442c42006-08-13 23:44:09 +0200189 struct completion cmd_complete;
190 struct resource *ioarea;
Paul Walmsley49839dc2012-11-06 16:31:32 +0000191 u32 latency; /* maximum mpu wkup latency */
192 void (*set_mpu_wkup_lat)(struct device *dev,
193 long latency);
Benoit Cousson61451972011-12-22 15:56:36 +0100194 u32 speed; /* Speed of bus in kHz */
195 u32 dtrev; /* extra revision from DT */
196 u32 flags;
Komal Shah010d442c42006-08-13 23:44:09 +0200197 u16 cmd_err;
198 u8 *buf;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700199 u8 *regs;
Komal Shah010d442c42006-08-13 23:44:09 +0200200 size_t buf_len;
201 struct i2c_adapter adapter;
Felipe Balbidd745482012-09-12 16:28:10 +0530202 u8 threshold;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800203 u8 fifo_size; /* use as flag and value
204 * fifo_size==0 implies no fifo
205 * if set, should be trsh+1
206 */
Shubhrajyoti D47dcd012012-11-05 17:53:36 +0530207 u32 rev;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800208 unsigned b_hw:1; /* bad h/w fixes */
Felipe Balbi079d8af2012-09-12 16:28:06 +0530209 unsigned receiver:1; /* true when we're in receiver mode */
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100210 u16 iestate; /* Saved interrupt register */
Rajendra Nayakef871432009-11-23 08:59:18 -0800211 u16 pscstate;
212 u16 scllstate;
213 u16 sclhstate;
214 u16 bufstate;
215 u16 syscstate;
216 u16 westate;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700217 u16 errata;
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +0000218
219 struct pinctrl *pins;
Komal Shah010d442c42006-08-13 23:44:09 +0200220};
221
Andy Greena1295572011-05-30 07:43:06 -0700222static const u8 reg_map_ip_v1[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700223 [OMAP_I2C_REV_REG] = 0x00,
224 [OMAP_I2C_IE_REG] = 0x01,
225 [OMAP_I2C_STAT_REG] = 0x02,
226 [OMAP_I2C_IV_REG] = 0x03,
227 [OMAP_I2C_WE_REG] = 0x03,
228 [OMAP_I2C_SYSS_REG] = 0x04,
229 [OMAP_I2C_BUF_REG] = 0x05,
230 [OMAP_I2C_CNT_REG] = 0x06,
231 [OMAP_I2C_DATA_REG] = 0x07,
232 [OMAP_I2C_SYSC_REG] = 0x08,
233 [OMAP_I2C_CON_REG] = 0x09,
234 [OMAP_I2C_OA_REG] = 0x0a,
235 [OMAP_I2C_SA_REG] = 0x0b,
236 [OMAP_I2C_PSC_REG] = 0x0c,
237 [OMAP_I2C_SCLL_REG] = 0x0d,
238 [OMAP_I2C_SCLH_REG] = 0x0e,
239 [OMAP_I2C_SYSTEST_REG] = 0x0f,
240 [OMAP_I2C_BUFSTAT_REG] = 0x10,
241};
242
Andy Greena1295572011-05-30 07:43:06 -0700243static const u8 reg_map_ip_v2[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700244 [OMAP_I2C_REV_REG] = 0x04,
245 [OMAP_I2C_IE_REG] = 0x2c,
246 [OMAP_I2C_STAT_REG] = 0x28,
247 [OMAP_I2C_IV_REG] = 0x34,
248 [OMAP_I2C_WE_REG] = 0x34,
249 [OMAP_I2C_SYSS_REG] = 0x90,
250 [OMAP_I2C_BUF_REG] = 0x94,
251 [OMAP_I2C_CNT_REG] = 0x98,
252 [OMAP_I2C_DATA_REG] = 0x9c,
Alexander Aring2727b172011-12-08 15:43:53 +0100253 [OMAP_I2C_SYSC_REG] = 0x10,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700254 [OMAP_I2C_CON_REG] = 0xa4,
255 [OMAP_I2C_OA_REG] = 0xa8,
256 [OMAP_I2C_SA_REG] = 0xac,
257 [OMAP_I2C_PSC_REG] = 0xb0,
258 [OMAP_I2C_SCLL_REG] = 0xb4,
259 [OMAP_I2C_SCLH_REG] = 0xb8,
260 [OMAP_I2C_SYSTEST_REG] = 0xbC,
261 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
Andy Greenb8853082011-05-30 07:43:04 -0700262 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
263 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
264 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
265 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
266 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700267};
268
Komal Shah010d442c42006-08-13 23:44:09 +0200269static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
270 int reg, u16 val)
271{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700272 __raw_writew(val, i2c_dev->base +
273 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200274}
275
276static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
277{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700278 return __raw_readw(i2c_dev->base +
279 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200280}
281
Komal Shah010d442c42006-08-13 23:44:09 +0200282static int omap_i2c_init(struct omap_i2c_dev *dev)
283{
Rajendra Nayakef871432009-11-23 08:59:18 -0800284 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800285 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200286 unsigned long fclk_rate = 12000000;
287 unsigned long timeout;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800288 unsigned long internal_clk = 0;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530289 struct clk *fclk;
Komal Shah010d442c42006-08-13 23:44:09 +0200290
Andy Green4e80f722011-05-30 07:43:07 -0700291 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
Manjunatha GK57eb81b2009-12-11 11:09:08 +0530292 /* Disable I2C controller before soft reset */
293 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
294 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
295 ~(OMAP_I2C_CON_EN));
296
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800297 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
Komal Shah010d442c42006-08-13 23:44:09 +0200298 /* For some reason we need to set the EN bit before the
299 * reset done bit gets set. */
300 timeout = jiffies + OMAP_I2C_TIMEOUT;
301 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
302 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800303 SYSS_RESETDONE_MASK)) {
Komal Shah010d442c42006-08-13 23:44:09 +0200304 if (time_after(jiffies, timeout)) {
Joe Perchesfce3ff02007-12-12 13:45:24 +0100305 dev_warn(dev->dev, "timeout waiting "
Komal Shah010d442c42006-08-13 23:44:09 +0200306 "for controller reset\n");
307 return -ETIMEDOUT;
308 }
309 msleep(1);
310 }
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800311
312 /* SYSC register is cleared by the reset; rewrite it */
313 if (dev->rev == OMAP_I2C_REV_ON_2430) {
314
315 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
316 SYSC_AUTOIDLE_MASK);
317
Jon Hunterf518b482012-06-28 20:41:31 +0530318 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800319 dev->syscstate = SYSC_AUTOIDLE_MASK;
320 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
321 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800322 __ffs(SYSC_SIDLEMODE_MASK));
Rajendra Nayakef871432009-11-23 08:59:18 -0800323 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800324 __ffs(SYSC_CLOCKACTIVITY_MASK));
325
Rajendra Nayakef871432009-11-23 08:59:18 -0800326 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
327 dev->syscstate);
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800328 /*
329 * Enabling all wakup sources to stop I2C freezing on
330 * WFI instruction.
331 * REVISIT: Some wkup sources might not be needed.
332 */
Rajendra Nayakef871432009-11-23 08:59:18 -0800333 dev->westate = OMAP_I2C_WE_ALL;
Shubhrajyoti Dcb28e582011-08-03 13:58:08 +0530334 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
335 dev->westate);
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800336 }
Komal Shah010d442c42006-08-13 23:44:09 +0200337 }
338 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
339
Benoit Cousson61451972011-12-22 15:56:36 +0100340 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
Russell King0e9ae102009-01-22 19:31:46 +0000341 /*
342 * The I2C functional clock is the armxor_ck, so there's
343 * no need to get "armxor_ck" separately. Now, if OMAP2420
344 * always returns 12MHz for the functional clock, we can
345 * do this bit unconditionally.
346 */
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530347 fclk = clk_get(dev->dev, "fck");
348 fclk_rate = clk_get_rate(fclk);
349 clk_put(fclk);
Komal Shah010d442c42006-08-13 23:44:09 +0200350
Komal Shah010d442c42006-08-13 23:44:09 +0200351 /* TRM for 5912 says the I2C clock must be prescaled to be
352 * between 7 - 12 MHz. The XOR input clock is typically
353 * 12, 13 or 19.2 MHz. So we should have code that produces:
354 *
355 * XOR MHz Divider Prescaler
356 * 12 1 0
357 * 13 2 1
358 * 19.2 2 1
359 */
Jean Delvared7aef132006-12-10 21:21:34 +0100360 if (fclk_rate > 12000000)
361 psc = fclk_rate / 12000000;
Komal Shah010d442c42006-08-13 23:44:09 +0200362 }
363
Benoit Cousson61451972011-12-22 15:56:36 +0100364 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800365
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300366 /*
367 * HSI2C controller internal clk rate should be 19.2 Mhz for
368 * HS and for all modes on 2430. On 34xx we can use lower rate
369 * to get longer filter period for better noise suppression.
370 * The filter is iclk (fclk for HS) period.
371 */
Andy Green3be00532011-05-30 07:43:09 -0700372 if (dev->speed > 400 ||
Benoit Cousson61451972011-12-22 15:56:36 +0100373 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300374 internal_clk = 19200;
375 else if (dev->speed > 100)
376 internal_clk = 9600;
377 else
378 internal_clk = 4000;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530379 fclk = clk_get(dev->dev, "fck");
380 fclk_rate = clk_get_rate(fclk) / 1000;
381 clk_put(fclk);
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800382
383 /* Compute prescaler divisor */
384 psc = fclk_rate / internal_clk;
385 psc = psc - 1;
386
387 /* If configured for High Speed */
388 if (dev->speed > 400) {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300389 unsigned long scl;
390
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800391 /* For first phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300392 scl = internal_clk / 400;
393 fsscll = scl - (scl / 3) - 7;
394 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800395
396 /* For second phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300397 scl = fclk_rate / dev->speed;
398 hsscll = scl - (scl / 3) - 7;
399 hssclh = (scl / 3) - 5;
400 } else if (dev->speed > 100) {
401 unsigned long scl;
402
403 /* Fast mode */
404 scl = internal_clk / dev->speed;
405 fsscll = scl - (scl / 3) - 7;
406 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800407 } else {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300408 /* Standard mode */
409 fsscll = internal_clk / (dev->speed * 2) - 7;
410 fssclh = internal_clk / (dev->speed * 2) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800411 }
412 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
413 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
414 } else {
415 /* Program desired operating rate */
416 fclk_rate /= (psc + 1) * 1000;
417 if (psc > 2)
418 psc = 2;
419 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
420 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
421 }
422
Komal Shah010d442c42006-08-13 23:44:09 +0200423 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
424 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
425
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800426 /* SCL low and high time values */
427 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
428 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
Komal Shah010d442c42006-08-13 23:44:09 +0200429
430 /* Take the I2C module out of reset: */
431 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
432
433 /* Enable interrupts */
Rajendra Nayakef871432009-11-23 08:59:18 -0800434 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800435 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
436 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
Rajendra Nayakef871432009-11-23 08:59:18 -0800437 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
438 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
Benoit Cousson61451972011-12-22 15:56:36 +0100439 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800440 dev->pscstate = psc;
441 dev->scllstate = scll;
442 dev->sclhstate = sclh;
443 dev->bufstate = buf;
444 }
Komal Shah010d442c42006-08-13 23:44:09 +0200445 return 0;
446}
447
448/*
449 * Waiting on Bus Busy
450 */
451static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
452{
453 unsigned long timeout;
454
455 timeout = jiffies + OMAP_I2C_TIMEOUT;
456 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
457 if (time_after(jiffies, timeout)) {
458 dev_warn(dev->dev, "timeout waiting for bus ready\n");
459 return -ETIMEDOUT;
460 }
461 msleep(1);
462 }
463
464 return 0;
465}
466
Felipe Balbidd745482012-09-12 16:28:10 +0530467static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
468{
469 u16 buf;
470
471 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
472 return;
473
474 /*
475 * Set up notification threshold based on message size. We're doing
476 * this to try and avoid draining feature as much as possible. Whenever
477 * we have big messages to transfer (bigger than our total fifo size)
478 * then we might use draining feature to transfer the remaining bytes.
479 */
480
481 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
482
483 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
484
485 if (is_rx) {
486 /* Clear RX Threshold */
487 buf &= ~(0x3f << 8);
488 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
489 } else {
490 /* Clear TX Threshold */
491 buf &= ~0x3f;
492 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
493 }
494
495 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
496
Shubhrajyoti D47dcd012012-11-05 17:53:36 +0530497 if (dev->rev < OMAP_I2C_REV_ON_3630)
Felipe Balbidd745482012-09-12 16:28:10 +0530498 dev->b_hw = 1; /* Enable hardware fixes */
499
500 /* calculate wakeup latency constraint for MPU */
Paul Walmsley49839dc2012-11-06 16:31:32 +0000501 if (dev->set_mpu_wkup_lat != NULL)
502 dev->latency = (1000000 * dev->threshold) /
503 (1000 * dev->speed / 8);
Felipe Balbidd745482012-09-12 16:28:10 +0530504}
505
Komal Shah010d442c42006-08-13 23:44:09 +0200506/*
507 * Low level master read/write transaction.
508 */
509static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
510 struct i2c_msg *msg, int stop)
511{
512 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530513 unsigned long timeout;
Komal Shah010d442c42006-08-13 23:44:09 +0200514 u16 w;
515
516 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
517 msg->addr, msg->len, msg->flags, stop);
518
519 if (msg->len == 0)
520 return -EINVAL;
521
Felipe Balbidd745482012-09-12 16:28:10 +0530522 dev->receiver = !!(msg->flags & I2C_M_RD);
523 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
524
Komal Shah010d442c42006-08-13 23:44:09 +0200525 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
526
527 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
528 dev->buf = msg->buf;
529 dev->buf_len = msg->len;
530
Felipe Balbid60ece52012-11-14 16:22:45 +0200531 /* make sure writes to dev->buf_len are ordered */
532 barrier();
533
Komal Shah010d442c42006-08-13 23:44:09 +0200534 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
535
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800536 /* Clear the FIFO Buffers */
537 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
538 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
539 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
540
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +0530541 INIT_COMPLETION(dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +0200542 dev->cmd_err = 0;
543
544 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800545
546 /* High speed configuration */
547 if (dev->speed > 400)
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800548 w |= OMAP_I2C_CON_OPMODE_HS;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800549
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200550 if (msg->flags & I2C_M_STOP)
551 stop = 1;
Komal Shah010d442c42006-08-13 23:44:09 +0200552 if (msg->flags & I2C_M_TEN)
553 w |= OMAP_I2C_CON_XA;
554 if (!(msg->flags & I2C_M_RD))
555 w |= OMAP_I2C_CON_TRX;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800556
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800557 if (!dev->b_hw && stop)
Komal Shah010d442c42006-08-13 23:44:09 +0200558 w |= OMAP_I2C_CON_STP;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800559
Komal Shah010d442c42006-08-13 23:44:09 +0200560 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
561
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800562 /*
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800563 * Don't write stt and stp together on some hardware.
564 */
565 if (dev->b_hw && stop) {
566 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
567 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
568 while (con & OMAP_I2C_CON_STT) {
569 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
570
571 /* Let the user know if i2c is in a bad state */
572 if (time_after(jiffies, delay)) {
573 dev_err(dev->dev, "controller timed out "
574 "waiting for start condition to finish\n");
575 return -ETIMEDOUT;
576 }
577 cpu_relax();
578 }
579
580 w |= OMAP_I2C_CON_STP;
581 w &= ~OMAP_I2C_CON_STT;
582 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
583 }
584
585 /*
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800586 * REVISIT: We should abort the transfer on signals, but the bus goes
587 * into arbitration and we're currently unable to recover from it.
588 */
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530589 timeout = wait_for_completion_timeout(&dev->cmd_complete,
590 OMAP_I2C_TIMEOUT);
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530591 if (timeout == 0) {
Komal Shah010d442c42006-08-13 23:44:09 +0200592 dev_err(dev->dev, "controller timed out\n");
593 omap_i2c_init(dev);
594 return -ETIMEDOUT;
595 }
596
597 if (likely(!dev->cmd_err))
598 return 0;
599
600 /* We have an error */
601 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
602 OMAP_I2C_STAT_XUDF)) {
603 omap_i2c_init(dev);
604 return -EIO;
605 }
606
607 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
608 if (msg->flags & I2C_M_IGNORE_NAK)
609 return 0;
610 if (stop) {
611 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
612 w |= OMAP_I2C_CON_STP;
613 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
614 }
615 return -EREMOTEIO;
616 }
617 return -EIO;
618}
619
620
621/*
622 * Prepare controller for a transaction and call omap_i2c_xfer_msg
623 * to do the work during IRQ processing.
624 */
625static int
626omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
627{
628 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
629 int i;
630 int r;
631
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +0530632 r = pm_runtime_get_sync(dev->dev);
633 if (IS_ERR_VALUE(r))
Kevin Hilman33ec5e82012-06-26 18:45:32 -0700634 goto out;
Komal Shah010d442c42006-08-13 23:44:09 +0200635
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800636 r = omap_i2c_wait_for_bb(dev);
637 if (r < 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200638 goto out;
639
Paul Walmsley49839dc2012-11-06 16:31:32 +0000640 if (dev->set_mpu_wkup_lat != NULL)
641 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
Samu Onkalo6a91b552010-11-18 12:04:20 +0200642
Komal Shah010d442c42006-08-13 23:44:09 +0200643 for (i = 0; i < num; i++) {
644 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
645 if (r != 0)
646 break;
647 }
648
Paul Walmsley49839dc2012-11-06 16:31:32 +0000649 if (dev->set_mpu_wkup_lat != NULL)
650 dev->set_mpu_wkup_lat(dev->dev, -1);
Samu Onkalo6a91b552010-11-18 12:04:20 +0200651
Komal Shah010d442c42006-08-13 23:44:09 +0200652 if (r == 0)
653 r = num;
Mathias Nyman5c64eb22010-08-26 07:36:44 +0000654
655 omap_i2c_wait_for_bb(dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200656out:
Felipe Balbi6d8451d2012-09-12 16:28:15 +0530657 pm_runtime_mark_last_busy(dev->dev);
658 pm_runtime_put_autosuspend(dev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200659 return r;
660}
661
662static u32
663omap_i2c_func(struct i2c_adapter *adap)
664{
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200665 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
666 I2C_FUNC_PROTOCOL_MANGLING;
Komal Shah010d442c42006-08-13 23:44:09 +0200667}
668
669static inline void
670omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
671{
672 dev->cmd_err |= err;
673 complete(&dev->cmd_complete);
674}
675
676static inline void
677omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
678{
679 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
680}
681
manjugk manjugkf3083d92010-05-11 11:35:20 -0700682static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
683{
684 /*
685 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
686 * Not applicable for OMAP4.
687 * Under certain rare conditions, RDR could be set again
688 * when the bus is busy, then ignore the interrupt and
689 * clear the interrupt.
690 */
691 if (stat & OMAP_I2C_STAT_RDR) {
692 /* Step 1: If RDR is set, clear it */
693 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
694
695 /* Step 2: */
696 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
697 & OMAP_I2C_STAT_BB)) {
698
699 /* Step 3: */
700 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
701 & OMAP_I2C_STAT_RDR) {
702 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
703 dev_dbg(dev->dev, "RDR when bus is busy.\n");
704 }
705
706 }
707 }
708}
709
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800710/* rev1 devices are apparently only on some 15xx */
711#ifdef CONFIG_ARCH_OMAP15XX
712
Komal Shah010d442c42006-08-13 23:44:09 +0200713static irqreturn_t
Andy Green4e80f722011-05-30 07:43:07 -0700714omap_i2c_omap1_isr(int this_irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200715{
716 struct omap_i2c_dev *dev = dev_id;
717 u16 iv, w;
718
Kevin Hilmanfab67af2011-05-17 16:31:38 +0200719 if (pm_runtime_suspended(dev->dev))
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100720 return IRQ_NONE;
721
Komal Shah010d442c42006-08-13 23:44:09 +0200722 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
723 switch (iv) {
724 case 0x00: /* None */
725 break;
726 case 0x01: /* Arbitration lost */
727 dev_err(dev->dev, "Arbitration lost\n");
728 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
729 break;
730 case 0x02: /* No acknowledgement */
731 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
732 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
733 break;
734 case 0x03: /* Register access ready */
735 omap_i2c_complete_cmd(dev, 0);
736 break;
737 case 0x04: /* Receive data ready */
738 if (dev->buf_len) {
739 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
740 *dev->buf++ = w;
741 dev->buf_len--;
742 if (dev->buf_len) {
743 *dev->buf++ = w >> 8;
744 dev->buf_len--;
745 }
746 } else
747 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
748 break;
749 case 0x05: /* Transmit data ready */
750 if (dev->buf_len) {
751 w = *dev->buf++;
752 dev->buf_len--;
753 if (dev->buf_len) {
754 w |= *dev->buf++ << 8;
755 dev->buf_len--;
756 }
757 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
758 } else
759 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
760 break;
761 default:
762 return IRQ_NONE;
763 }
764
765 return IRQ_HANDLED;
766}
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800767#else
Andy Green4e80f722011-05-30 07:43:07 -0700768#define omap_i2c_omap1_isr NULL
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800769#endif
Komal Shah010d442c42006-08-13 23:44:09 +0200770
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700771/*
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530772 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700773 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
774 * them from the memory to the I2C interface.
775 */
Felipe Balbi4151e742012-09-12 16:28:01 +0530776static int errata_omap3_i462(struct omap_i2c_dev *dev)
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700777{
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700778 unsigned long timeout = 10000;
Felipe Balbi4151e742012-09-12 16:28:01 +0530779 u16 stat;
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700780
Felipe Balbi4151e742012-09-12 16:28:01 +0530781 do {
782 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
783 if (stat & OMAP_I2C_STAT_XUDF)
784 break;
785
786 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530787 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700788 OMAP_I2C_STAT_XDR));
Felipe Balbib07be0f2012-09-12 16:28:11 +0530789 if (stat & OMAP_I2C_STAT_NACK) {
790 dev->cmd_err |= OMAP_I2C_STAT_NACK;
791 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
792 }
793
794 if (stat & OMAP_I2C_STAT_AL) {
795 dev_err(dev->dev, "Arbitration lost\n");
796 dev->cmd_err |= OMAP_I2C_STAT_AL;
797 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
798 }
799
Felipe Balbi4151e742012-09-12 16:28:01 +0530800 return -EIO;
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700801 }
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700802
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700803 cpu_relax();
Felipe Balbi4151e742012-09-12 16:28:01 +0530804 } while (--timeout);
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700805
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700806 if (!timeout) {
807 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
808 return 0;
809 }
810
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700811 return 0;
812}
813
Felipe Balbi3312d252012-09-12 16:28:02 +0530814static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
815 bool is_rdr)
816{
817 u16 w;
818
819 while (num_bytes--) {
Felipe Balbi3312d252012-09-12 16:28:02 +0530820 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
821 *dev->buf++ = w;
822 dev->buf_len--;
823
824 /*
825 * Data reg in 2430, omap3 and
826 * omap4 is 8 bit wide
827 */
828 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
Felipe Balbidd745482012-09-12 16:28:10 +0530829 *dev->buf++ = w >> 8;
830 dev->buf_len--;
Felipe Balbi3312d252012-09-12 16:28:02 +0530831 }
832 }
833}
834
835static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
836 bool is_xdr)
837{
838 u16 w;
839
840 while (num_bytes--) {
Felipe Balbi3312d252012-09-12 16:28:02 +0530841 w = *dev->buf++;
842 dev->buf_len--;
843
844 /*
845 * Data reg in 2430, omap3 and
846 * omap4 is 8 bit wide
847 */
848 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
Felipe Balbidd745482012-09-12 16:28:10 +0530849 w |= *dev->buf++ << 8;
850 dev->buf_len--;
Felipe Balbi3312d252012-09-12 16:28:02 +0530851 }
852
853 if (dev->errata & I2C_OMAP_ERRATA_I462) {
854 int ret;
855
856 ret = errata_omap3_i462(dev);
857 if (ret < 0)
858 return ret;
859 }
860
861 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
862 }
863
Komal Shah010d442c42006-08-13 23:44:09 +0200864 return 0;
865}
866
867static irqreturn_t
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530868omap_i2c_isr(int irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200869{
870 struct omap_i2c_dev *dev = dev_id;
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530871 irqreturn_t ret = IRQ_HANDLED;
872 u16 mask;
873 u16 stat;
874
875 spin_lock(&dev->lock);
876 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
877 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
878
879 if (stat & mask)
880 ret = IRQ_WAKE_THREAD;
881
882 spin_unlock(&dev->lock);
883
884 return ret;
885}
886
887static irqreturn_t
888omap_i2c_isr_thread(int this_irq, void *dev_id)
889{
890 struct omap_i2c_dev *dev = dev_id;
891 unsigned long flags;
Komal Shah010d442c42006-08-13 23:44:09 +0200892 u16 bits;
Felipe Balbi3312d252012-09-12 16:28:02 +0530893 u16 stat;
Felipe Balbi66b92982012-09-12 16:28:03 +0530894 int err = 0, count = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200895
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530896 spin_lock_irqsave(&dev->lock, flags);
Felipe Balbi66b92982012-09-12 16:28:03 +0530897 do {
898 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
899 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
900 stat &= bits;
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100901
Felipe Balbi079d8af2012-09-12 16:28:06 +0530902 /* If we're in receiver mode, ignore XDR/XRDY */
903 if (dev->receiver)
904 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
905 else
906 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
907
Felipe Balbi66b92982012-09-12 16:28:03 +0530908 if (!stat) {
909 /* my work here is done */
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530910 goto out;
Felipe Balbi66b92982012-09-12 16:28:03 +0530911 }
912
Komal Shah010d442c42006-08-13 23:44:09 +0200913 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
914 if (count++ == 100) {
915 dev_warn(dev->dev, "Too much work in one IRQ\n");
916 break;
917 }
918
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530919 if (stat & OMAP_I2C_STAT_NACK) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800920 err |= OMAP_I2C_STAT_NACK;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530921 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530922 break;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530923 }
Jan Weitzel78e1cf42011-12-07 11:50:16 -0800924
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800925 if (stat & OMAP_I2C_STAT_AL) {
926 dev_err(dev->dev, "Arbitration lost\n");
927 err |= OMAP_I2C_STAT_AL;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530928 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530929 break;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800930 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530931
Ben Dooksa5a595c2011-02-23 00:43:55 +0000932 /*
Richard woodruffcb527ed2011-02-16 10:24:16 +0530933 * ProDB0017052: Clear ARDY bit twice
Ben Dooksa5a595c2011-02-23 00:43:55 +0000934 */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800935 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500936 OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530937 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
938 OMAP_I2C_STAT_RDR |
939 OMAP_I2C_STAT_XRDY |
940 OMAP_I2C_STAT_XDR |
941 OMAP_I2C_STAT_ARDY));
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530942 break;
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500943 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530944
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530945 if (stat & OMAP_I2C_STAT_RDR) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800946 u8 num_bytes = 1;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700947
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530948 if (dev->fifo_size)
949 num_bytes = dev->buf_len;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700950
Felipe Balbi3312d252012-09-12 16:28:02 +0530951 omap_i2c_receive_data(dev, num_bytes, true);
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530952
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800953 if (dev->errata & I2C_OMAP_ERRATA_I207)
954 i2c_omap_errata_i207(dev, stat);
Komal Shah010d442c42006-08-13 23:44:09 +0200955
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530956 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530957 break;
Komal Shah010d442c42006-08-13 23:44:09 +0200958 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530959
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530960 if (stat & OMAP_I2C_STAT_RRDY) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800961 u8 num_bytes = 1;
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500962
Felipe Balbidd745482012-09-12 16:28:10 +0530963 if (dev->threshold)
964 num_bytes = dev->threshold;
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500965
Felipe Balbi3312d252012-09-12 16:28:02 +0530966 omap_i2c_receive_data(dev, num_bytes, false);
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530967 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
Komal Shah010d442c42006-08-13 23:44:09 +0200968 continue;
969 }
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530970
971 if (stat & OMAP_I2C_STAT_XDR) {
972 u8 num_bytes = 1;
Felipe Balbi3312d252012-09-12 16:28:02 +0530973 int ret;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530974
975 if (dev->fifo_size)
976 num_bytes = dev->buf_len;
977
Felipe Balbi3312d252012-09-12 16:28:02 +0530978 ret = omap_i2c_transmit_data(dev, num_bytes, true);
Felipe Balbi3312d252012-09-12 16:28:02 +0530979 if (ret < 0)
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530980 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530981
982 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530983 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530984 }
985
986 if (stat & OMAP_I2C_STAT_XRDY) {
987 u8 num_bytes = 1;
Felipe Balbi3312d252012-09-12 16:28:02 +0530988 int ret;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530989
Felipe Balbidd745482012-09-12 16:28:10 +0530990 if (dev->threshold)
991 num_bytes = dev->threshold;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530992
Felipe Balbi3312d252012-09-12 16:28:02 +0530993 ret = omap_i2c_transmit_data(dev, num_bytes, false);
Felipe Balbi3312d252012-09-12 16:28:02 +0530994 if (ret < 0)
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530995 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530996
997 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
Komal Shah010d442c42006-08-13 23:44:09 +0200998 continue;
999 }
Felipe Balbic55edb92012-09-12 16:27:58 +05301000
Komal Shah010d442c42006-08-13 23:44:09 +02001001 if (stat & OMAP_I2C_STAT_ROVR) {
1002 dev_err(dev->dev, "Receive overrun\n");
Felipe Balbi1d7afc92012-09-12 16:28:04 +05301003 err |= OMAP_I2C_STAT_ROVR;
1004 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301005 break;
Komal Shah010d442c42006-08-13 23:44:09 +02001006 }
Felipe Balbic55edb92012-09-12 16:27:58 +05301007
Komal Shah010d442c42006-08-13 23:44:09 +02001008 if (stat & OMAP_I2C_STAT_XUDF) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001009 dev_err(dev->dev, "Transmit underflow\n");
Felipe Balbi1d7afc92012-09-12 16:28:04 +05301010 err |= OMAP_I2C_STAT_XUDF;
1011 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301012 break;
Komal Shah010d442c42006-08-13 23:44:09 +02001013 }
Felipe Balbi66b92982012-09-12 16:28:03 +05301014 } while (stat);
Komal Shah010d442c42006-08-13 23:44:09 +02001015
Felipe Balbi4a7ec4e2012-09-12 16:28:09 +05301016 omap_i2c_complete_cmd(dev, err);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301017
1018out:
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301019 spin_unlock_irqrestore(&dev->lock, flags);
1020
Felipe Balbi6a85ced2012-09-12 16:28:08 +05301021 return IRQ_HANDLED;
Komal Shah010d442c42006-08-13 23:44:09 +02001022}
1023
Jean Delvare8f9082c2006-09-03 22:39:46 +02001024static const struct i2c_algorithm omap_i2c_algo = {
Komal Shah010d442c42006-08-13 23:44:09 +02001025 .master_xfer = omap_i2c_xfer,
1026 .functionality = omap_i2c_func,
1027};
1028
Benoit Cousson61451972011-12-22 15:56:36 +01001029#ifdef CONFIG_OF
1030static struct omap_i2c_bus_platform_data omap3_pdata = {
1031 .rev = OMAP_I2C_IP_VERSION_1,
1032 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1033 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1034 OMAP_I2C_FLAG_BUS_SHIFT_2,
1035};
1036
1037static struct omap_i2c_bus_platform_data omap4_pdata = {
1038 .rev = OMAP_I2C_IP_VERSION_2,
1039};
1040
1041static const struct of_device_id omap_i2c_of_match[] = {
1042 {
1043 .compatible = "ti,omap4-i2c",
1044 .data = &omap4_pdata,
1045 },
1046 {
1047 .compatible = "ti,omap3-i2c",
1048 .data = &omap3_pdata,
1049 },
1050 { },
1051};
1052MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1053#endif
1054
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301055#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1056
1057#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1058#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1059
1060#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1061#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1062#define OMAP_I2C_SCHEME_0 0
1063#define OMAP_I2C_SCHEME_1 1
1064
Uwe Kleine-König1139aea2010-02-04 20:56:53 +01001065static int __devinit
Komal Shah010d442c42006-08-13 23:44:09 +02001066omap_i2c_probe(struct platform_device *pdev)
1067{
1068 struct omap_i2c_dev *dev;
1069 struct i2c_adapter *adap;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301070 struct resource *mem;
Uwe Kleine-Königc4dba012012-05-21 21:57:39 +02001071 const struct omap_i2c_bus_platform_data *pdata =
1072 pdev->dev.platform_data;
Benoit Cousson61451972011-12-22 15:56:36 +01001073 struct device_node *node = pdev->dev.of_node;
1074 const struct of_device_id *match;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301075 int irq;
Komal Shah010d442c42006-08-13 23:44:09 +02001076 int r;
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301077 u32 rev;
1078 u16 minor, major;
Komal Shah010d442c42006-08-13 23:44:09 +02001079
1080 /* NOTE: driver uses the static register mapping */
1081 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 if (!mem) {
1083 dev_err(&pdev->dev, "no mem resource?\n");
1084 return -ENODEV;
1085 }
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301086
1087 irq = platform_get_irq(pdev, 0);
1088 if (irq < 0) {
Komal Shah010d442c42006-08-13 23:44:09 +02001089 dev_err(&pdev->dev, "no irq resource?\n");
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301090 return irq;
Komal Shah010d442c42006-08-13 23:44:09 +02001091 }
1092
Felipe Balbid9ebd042012-09-12 16:27:55 +05301093 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
Komal Shah010d442c42006-08-13 23:44:09 +02001094 if (!dev) {
Felipe Balbid9ebd042012-09-12 16:27:55 +05301095 dev_err(&pdev->dev, "Menory allocation failed\n");
1096 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001097 }
1098
Felipe Balbid9ebd042012-09-12 16:27:55 +05301099 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1100 if (!dev->base) {
1101 dev_err(&pdev->dev, "I2C region already claimed\n");
1102 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001103 }
1104
Cousson, Benoit6c5aa402012-01-20 16:55:04 +01001105 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
Benoit Cousson61451972011-12-22 15:56:36 +01001106 if (match) {
1107 u32 freq = 100000; /* default to 100000 Hz */
1108
1109 pdata = match->data;
1110 dev->dtrev = pdata->rev;
1111 dev->flags = pdata->flags;
1112
1113 of_property_read_u32(node, "clock-frequency", &freq);
1114 /* convert DT freq value in Hz into kHz for speed */
1115 dev->speed = freq / 1000;
1116 } else if (pdata != NULL) {
1117 dev->speed = pdata->clkrate;
1118 dev->flags = pdata->flags;
Paul Walmsley49839dc2012-11-06 16:31:32 +00001119 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
Benoit Cousson61451972011-12-22 15:56:36 +01001120 dev->dtrev = pdata->rev;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001121 }
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -08001122
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +00001123 dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
1124 if (IS_ERR(dev->pins)) {
1125 if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
1126 return -EPROBE_DEFER;
1127
1128 dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
1129 PTR_ERR(dev->pins));
1130 dev->pins = NULL;
1131 }
1132
Komal Shah010d442c42006-08-13 23:44:09 +02001133 dev->dev = &pdev->dev;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301134 dev->irq = irq;
Russell King55c381e2008-09-04 14:07:22 +01001135
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301136 spin_lock_init(&dev->lock);
Komal Shah010d442c42006-08-13 23:44:09 +02001137
1138 platform_set_drvdata(pdev, dev);
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +05301139 init_completion(&dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +02001140
Benoit Cousson61451972011-12-22 15:56:36 +01001141 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
Mika Westerberg7c6bd202010-03-23 12:12:56 +02001142
Kevin Hilman7f4b08e2011-05-17 16:31:37 +02001143 pm_runtime_enable(dev->dev);
Felipe Balbi6d8451d2012-09-12 16:28:15 +05301144 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1145 pm_runtime_use_autosuspend(dev->dev);
1146
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301147 r = pm_runtime_get_sync(dev->dev);
1148 if (IS_ERR_VALUE(r))
1149 goto err_free_mem;
Komal Shah010d442c42006-08-13 23:44:09 +02001150
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301151 /*
1152 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1153 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1154 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1155 * raw_readw is done.
1156 */
1157 rev = __raw_readw(dev->base + 0x04);
1158
1159 switch (OMAP_I2C_SCHEME(rev)) {
1160 case OMAP_I2C_SCHEME_0:
1161 dev->regs = (u8 *)reg_map_ip_v1;
1162 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1163 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1164 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1165 break;
1166 case OMAP_I2C_SCHEME_1:
1167 /* FALLTHROUGH */
1168 default:
1169 dev->regs = (u8 *)reg_map_ip_v2;
1170 rev = (rev << 16) |
1171 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1172 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1173 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1174 dev->rev = rev;
1175 }
Komal Shah010d442c42006-08-13 23:44:09 +02001176
Tasslehoff Kjappfot9aa8ec62012-05-29 16:26:20 +05301177 dev->errata = 0;
1178
1179 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1180 dev->errata |= I2C_OMAP_ERRATA_I207;
1181
Jon Hunterf518b482012-06-28 20:41:31 +05301182 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +05301183 dev->errata |= I2C_OMAP_ERRATA_I462;
manjugk manjugk8a9d97d2010-05-11 11:35:23 -07001184
Benoit Cousson61451972011-12-22 15:56:36 +01001185 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001186 u16 s;
1187
1188 /* Set up the fifo size - Get total size */
1189 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1190 dev->fifo_size = 0x8 << s;
1191
1192 /*
1193 * Set up notification threshold as half the total available
1194 * size. This is to ensure that we can handle the status on int
1195 * call back latencies.
1196 */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001197
1198 dev->fifo_size = (dev->fifo_size / 2);
1199
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301200 if (dev->rev < OMAP_I2C_REV_ON_3630)
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001201 dev->b_hw = 1; /* Enable hardware fixes */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001202
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001203 /* calculate wakeup latency constraint for MPU */
Paul Walmsley49839dc2012-11-06 16:31:32 +00001204 if (dev->set_mpu_wkup_lat != NULL)
1205 dev->latency = (1000000 * dev->fifo_size) /
1206 (1000 * dev->speed / 8);
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001207 }
1208
Komal Shah010d442c42006-08-13 23:44:09 +02001209 /* reset ASAP, clearing any IRQs */
1210 omap_i2c_init(dev);
1211
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301212 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1213 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1214 IRQF_NO_SUSPEND, pdev->name, dev);
1215 else
1216 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1217 omap_i2c_isr, omap_i2c_isr_thread,
1218 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1219 pdev->name, dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001220
1221 if (r) {
1222 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1223 goto err_unuse_clocks;
1224 }
Paul Walmsley9c76b872008-11-21 13:39:55 -08001225
Komal Shah010d442c42006-08-13 23:44:09 +02001226 adap = &dev->adapter;
1227 i2c_set_adapdata(adap, dev);
1228 adap->owner = THIS_MODULE;
1229 adap->class = I2C_CLASS_HWMON;
Roel Kluin783fd6f2009-07-17 15:24:00 +02001230 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
Komal Shah010d442c42006-08-13 23:44:09 +02001231 adap->algo = &omap_i2c_algo;
1232 adap->dev.parent = &pdev->dev;
Benoit Cousson61451972011-12-22 15:56:36 +01001233 adap->dev.of_node = pdev->dev.of_node;
Komal Shah010d442c42006-08-13 23:44:09 +02001234
1235 /* i2c device drivers may be active on return from add_adapter() */
David Brownell7c175492007-05-01 23:26:32 +02001236 adap->nr = pdev->id;
1237 r = i2c_add_numbered_adapter(adap);
Komal Shah010d442c42006-08-13 23:44:09 +02001238 if (r) {
1239 dev_err(dev->dev, "failure adding adapter\n");
Felipe Balbid9ebd042012-09-12 16:27:55 +05301240 goto err_unuse_clocks;
Komal Shah010d442c42006-08-13 23:44:09 +02001241 }
1242
Florian Vaussardc5d3cd62012-08-31 13:02:55 +02001243 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301244 dev->dtrev, major, minor, dev->speed);
Florian Vaussardc5d3cd62012-08-31 13:02:55 +02001245
Benoit Cousson61451972011-12-22 15:56:36 +01001246 of_i2c_register_devices(adap);
1247
Felipe Balbi6d8451d2012-09-12 16:28:15 +05301248 pm_runtime_mark_last_busy(dev->dev);
1249 pm_runtime_put_autosuspend(dev->dev);
Shubhrajyoti D62ff2c22012-05-29 16:26:16 +05301250
Komal Shah010d442c42006-08-13 23:44:09 +02001251 return 0;
1252
Komal Shah010d442c42006-08-13 23:44:09 +02001253err_unuse_clocks:
Tony Lindgren3e397522008-01-14 21:53:30 +01001254 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001255 pm_runtime_put(dev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301256 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001257err_free_mem:
1258 platform_set_drvdata(pdev, NULL);
Komal Shah010d442c42006-08-13 23:44:09 +02001259
1260 return r;
1261}
1262
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301263static int __devexit omap_i2c_remove(struct platform_device *pdev)
Komal Shah010d442c42006-08-13 23:44:09 +02001264{
1265 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301266 int ret;
Komal Shah010d442c42006-08-13 23:44:09 +02001267
1268 platform_set_drvdata(pdev, NULL);
1269
Komal Shah010d442c42006-08-13 23:44:09 +02001270 i2c_del_adapter(&dev->adapter);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301271 ret = pm_runtime_get_sync(&pdev->dev);
1272 if (IS_ERR_VALUE(ret))
1273 return ret;
1274
Komal Shah010d442c42006-08-13 23:44:09 +02001275 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Shubhrajyoti D0861f432012-05-29 16:26:18 +05301276 pm_runtime_put(&pdev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301277 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001278 return 0;
1279}
1280
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301281#ifdef CONFIG_PM
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001282#ifdef CONFIG_PM_RUNTIME
1283static int omap_i2c_runtime_suspend(struct device *dev)
1284{
1285 struct platform_device *pdev = to_platform_device(dev);
1286 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301287 u16 iv;
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001288
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301289 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
Shubhrajyoti Dbd16c822012-05-29 16:26:15 +05301290
1291 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301292
1293 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1294 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1295 } else {
1296 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1297
1298 /* Flush posted write */
1299 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1300 }
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001301
1302 return 0;
1303}
1304
1305static int omap_i2c_runtime_resume(struct device *dev)
1306{
1307 struct platform_device *pdev = to_platform_device(dev);
1308 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1309
Shubhrajyoti D47dcd012012-11-05 17:53:36 +05301310 if (!_dev->regs)
1311 return 0;
1312
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301313 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1314 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1315 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1316 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1317 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1318 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1319 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1320 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1321 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1322 }
1323
1324 /*
1325 * Don't write to this register if the IE state is 0 as it can
1326 * cause deadlock.
1327 */
1328 if (_dev->iestate)
1329 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001330
1331 return 0;
1332}
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301333#endif /* CONFIG_PM_RUNTIME */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001334
1335static struct dev_pm_ops omap_i2c_pm_ops = {
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301336 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1337 omap_i2c_runtime_resume, NULL)
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001338};
1339#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1340#else
1341#define OMAP_I2C_PM_OPS NULL
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301342#endif /* CONFIG_PM */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001343
Komal Shah010d442c42006-08-13 23:44:09 +02001344static struct platform_driver omap_i2c_driver = {
1345 .probe = omap_i2c_probe,
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301346 .remove = __devexit_p(omap_i2c_remove),
Komal Shah010d442c42006-08-13 23:44:09 +02001347 .driver = {
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001348 .name = "omap_i2c",
Komal Shah010d442c42006-08-13 23:44:09 +02001349 .owner = THIS_MODULE,
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001350 .pm = OMAP_I2C_PM_OPS,
Benoit Cousson61451972011-12-22 15:56:36 +01001351 .of_match_table = of_match_ptr(omap_i2c_of_match),
Komal Shah010d442c42006-08-13 23:44:09 +02001352 },
1353};
1354
1355/* I2C may be needed to bring up other drivers */
1356static int __init
1357omap_i2c_init_driver(void)
1358{
1359 return platform_driver_register(&omap_i2c_driver);
1360}
1361subsys_initcall(omap_i2c_init_driver);
1362
1363static void __exit omap_i2c_exit_driver(void)
1364{
1365 platform_driver_unregister(&omap_i2c_driver);
1366}
1367module_exit(omap_i2c_exit_driver);
1368
1369MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1370MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1371MODULE_LICENSE("GPL");
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001372MODULE_ALIAS("platform:omap_i2c");