blob: 16afb289cca7a8d27875320c7c539510718ac893 [file] [log] [blame]
Komal Shah010d442c42006-08-13 23:44:09 +02001/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
Komal Shah010d442c42006-08-13 23:44:09 +02005 * Copyright (C) 2005 Nokia Corporation
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08006 * Copyright (C) 2004 - 2007 Texas Instruments.
Komal Shah010d442c42006-08-13 23:44:09 +02007 *
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08008 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
Komal Shah010d442c42006-08-13 23:44:09 +020015 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
Tony Lindgrenc1a473b2008-11-21 13:39:47 -080039#include <linux/io.h>
Benoit Cousson61451972011-12-22 15:56:36 +010040#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090043#include <linux/slab.h>
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -070044#include <linux/i2c-omap.h>
Rajendra Nayak27b1fec2010-09-28 21:02:58 +053045#include <linux/pm_runtime.h>
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +000046#include <linux/pinctrl/consumer.h>
Komal Shah010d442c42006-08-13 23:44:09 +020047
Paul Walmsley9c76b872008-11-21 13:39:55 -080048/* I2C controller revisions */
Andy Green4e80f722011-05-30 07:43:07 -070049#define OMAP_I2C_OMAP1_REV_2 0x20
Paul Walmsley9c76b872008-11-21 13:39:55 -080050
51/* I2C controller revisions present on specific hardware */
52#define OMAP_I2C_REV_ON_2430 0x36
Jon Hunterf518b482012-06-28 20:41:31 +053053#define OMAP_I2C_REV_ON_3430_3530 0x3C
54#define OMAP_I2C_REV_ON_3630_4430 0x40
Paul Walmsley9c76b872008-11-21 13:39:55 -080055
Komal Shah010d442c42006-08-13 23:44:09 +020056/* timeout waiting for the controller to respond */
57#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
58
Felipe Balbi6d8451d2012-09-12 16:28:15 +053059/* timeout for pm runtime autosuspend */
60#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
61
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -080062/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070063enum {
64 OMAP_I2C_REV_REG = 0,
65 OMAP_I2C_IE_REG,
66 OMAP_I2C_STAT_REG,
67 OMAP_I2C_IV_REG,
68 OMAP_I2C_WE_REG,
69 OMAP_I2C_SYSS_REG,
70 OMAP_I2C_BUF_REG,
71 OMAP_I2C_CNT_REG,
72 OMAP_I2C_DATA_REG,
73 OMAP_I2C_SYSC_REG,
74 OMAP_I2C_CON_REG,
75 OMAP_I2C_OA_REG,
76 OMAP_I2C_SA_REG,
77 OMAP_I2C_PSC_REG,
78 OMAP_I2C_SCLL_REG,
79 OMAP_I2C_SCLH_REG,
80 OMAP_I2C_SYSTEST_REG,
81 OMAP_I2C_BUFSTAT_REG,
Andy Greenb8853082011-05-30 07:43:04 -070082 /* only on OMAP4430 */
83 OMAP_I2C_IP_V2_REVNB_LO,
84 OMAP_I2C_IP_V2_REVNB_HI,
85 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
86 OMAP_I2C_IP_V2_IRQENABLE_SET,
87 OMAP_I2C_IP_V2_IRQENABLE_CLR,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070088};
Komal Shah010d442c42006-08-13 23:44:09 +020089
90/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -080091#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
92#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
Komal Shah010d442c42006-08-13 23:44:09 +020093#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
94#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
95#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
96#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
97#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
98
99/* I2C Status Register (OMAP_I2C_STAT): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800100#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
101#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
Komal Shah010d442c42006-08-13 23:44:09 +0200102#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
103#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
104#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
105#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
106#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
107#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
108#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
109#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
110#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
111#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
112
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800113/* I2C WE wakeup enable register */
114#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
115#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
116#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
117#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
118#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
119#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
120#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
121#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
122#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
123#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
124
125#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
126 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
127 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
128 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
129 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
130
Komal Shah010d442c42006-08-13 23:44:09 +0200131/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
132#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800133#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200134#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800135#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200136
137/* I2C Configuration Register (OMAP_I2C_CON): */
138#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
139#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800140#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
Komal Shah010d442c42006-08-13 23:44:09 +0200141#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
142#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
143#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
144#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
145#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
146#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
147#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
148
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800149/* I2C SCL time value when Master */
150#define OMAP_I2C_SCLL_HSSCLL 8
151#define OMAP_I2C_SCLH_HSSCLH 8
152
Komal Shah010d442c42006-08-13 23:44:09 +0200153/* I2C System Test Register (OMAP_I2C_SYSTEST): */
154#ifdef DEBUG
155#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
156#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
157#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
158#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
159#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
160#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
161#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
162#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
163#endif
164
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800165/* OCP_SYSSTATUS bit definitions */
166#define SYSS_RESETDONE_MASK (1 << 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200167
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800168/* OCP_SYSCONFIG bit definitions */
169#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
170#define SYSC_SIDLEMODE_MASK (0x3 << 3)
171#define SYSC_ENAWAKEUP_MASK (1 << 2)
172#define SYSC_SOFTRESET_MASK (1 << 1)
173#define SYSC_AUTOIDLE_MASK (1 << 0)
174
175#define SYSC_IDLEMODE_SMART 0x2
176#define SYSC_CLOCKACTIVITY_FCLK 0x2
177
manjugk manjugkf3083d92010-05-11 11:35:20 -0700178/* Errata definitions */
179#define I2C_OMAP_ERRATA_I207 (1 << 0)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530180#define I2C_OMAP_ERRATA_I462 (1 << 1)
Komal Shah010d442c42006-08-13 23:44:09 +0200181
Komal Shah010d442c42006-08-13 23:44:09 +0200182struct omap_i2c_dev {
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530183 spinlock_t lock; /* IRQ synchronization */
Komal Shah010d442c42006-08-13 23:44:09 +0200184 struct device *dev;
185 void __iomem *base; /* virtual */
186 int irq;
Cory Maccarroned84d3ea2009-12-12 17:54:02 -0800187 int reg_shift; /* bit shift for I2C register addresses */
Komal Shah010d442c42006-08-13 23:44:09 +0200188 struct completion cmd_complete;
189 struct resource *ioarea;
Paul Walmsley49839dc2012-11-06 16:31:32 +0000190 u32 latency; /* maximum mpu wkup latency */
191 void (*set_mpu_wkup_lat)(struct device *dev,
192 long latency);
Benoit Cousson61451972011-12-22 15:56:36 +0100193 u32 speed; /* Speed of bus in kHz */
194 u32 dtrev; /* extra revision from DT */
195 u32 flags;
Komal Shah010d442c42006-08-13 23:44:09 +0200196 u16 cmd_err;
197 u8 *buf;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700198 u8 *regs;
Komal Shah010d442c42006-08-13 23:44:09 +0200199 size_t buf_len;
200 struct i2c_adapter adapter;
Felipe Balbidd745482012-09-12 16:28:10 +0530201 u8 threshold;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800202 u8 fifo_size; /* use as flag and value
203 * fifo_size==0 implies no fifo
204 * if set, should be trsh+1
205 */
Paul Walmsley9c76b872008-11-21 13:39:55 -0800206 u8 rev;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800207 unsigned b_hw:1; /* bad h/w fixes */
Felipe Balbi079d8af2012-09-12 16:28:06 +0530208 unsigned receiver:1; /* true when we're in receiver mode */
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100209 u16 iestate; /* Saved interrupt register */
Rajendra Nayakef871432009-11-23 08:59:18 -0800210 u16 pscstate;
211 u16 scllstate;
212 u16 sclhstate;
213 u16 bufstate;
214 u16 syscstate;
215 u16 westate;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700216 u16 errata;
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +0000217
218 struct pinctrl *pins;
Komal Shah010d442c42006-08-13 23:44:09 +0200219};
220
Andy Greena1295572011-05-30 07:43:06 -0700221static const u8 reg_map_ip_v1[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700222 [OMAP_I2C_REV_REG] = 0x00,
223 [OMAP_I2C_IE_REG] = 0x01,
224 [OMAP_I2C_STAT_REG] = 0x02,
225 [OMAP_I2C_IV_REG] = 0x03,
226 [OMAP_I2C_WE_REG] = 0x03,
227 [OMAP_I2C_SYSS_REG] = 0x04,
228 [OMAP_I2C_BUF_REG] = 0x05,
229 [OMAP_I2C_CNT_REG] = 0x06,
230 [OMAP_I2C_DATA_REG] = 0x07,
231 [OMAP_I2C_SYSC_REG] = 0x08,
232 [OMAP_I2C_CON_REG] = 0x09,
233 [OMAP_I2C_OA_REG] = 0x0a,
234 [OMAP_I2C_SA_REG] = 0x0b,
235 [OMAP_I2C_PSC_REG] = 0x0c,
236 [OMAP_I2C_SCLL_REG] = 0x0d,
237 [OMAP_I2C_SCLH_REG] = 0x0e,
238 [OMAP_I2C_SYSTEST_REG] = 0x0f,
239 [OMAP_I2C_BUFSTAT_REG] = 0x10,
240};
241
Andy Greena1295572011-05-30 07:43:06 -0700242static const u8 reg_map_ip_v2[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700243 [OMAP_I2C_REV_REG] = 0x04,
244 [OMAP_I2C_IE_REG] = 0x2c,
245 [OMAP_I2C_STAT_REG] = 0x28,
246 [OMAP_I2C_IV_REG] = 0x34,
247 [OMAP_I2C_WE_REG] = 0x34,
248 [OMAP_I2C_SYSS_REG] = 0x90,
249 [OMAP_I2C_BUF_REG] = 0x94,
250 [OMAP_I2C_CNT_REG] = 0x98,
251 [OMAP_I2C_DATA_REG] = 0x9c,
Alexander Aring2727b172011-12-08 15:43:53 +0100252 [OMAP_I2C_SYSC_REG] = 0x10,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700253 [OMAP_I2C_CON_REG] = 0xa4,
254 [OMAP_I2C_OA_REG] = 0xa8,
255 [OMAP_I2C_SA_REG] = 0xac,
256 [OMAP_I2C_PSC_REG] = 0xb0,
257 [OMAP_I2C_SCLL_REG] = 0xb4,
258 [OMAP_I2C_SCLH_REG] = 0xb8,
259 [OMAP_I2C_SYSTEST_REG] = 0xbC,
260 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
Andy Greenb8853082011-05-30 07:43:04 -0700261 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
262 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
263 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
264 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
265 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700266};
267
Komal Shah010d442c42006-08-13 23:44:09 +0200268static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
269 int reg, u16 val)
270{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700271 __raw_writew(val, i2c_dev->base +
272 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200273}
274
275static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
276{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700277 return __raw_readw(i2c_dev->base +
278 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200279}
280
Komal Shah010d442c42006-08-13 23:44:09 +0200281static int omap_i2c_init(struct omap_i2c_dev *dev)
282{
Rajendra Nayakef871432009-11-23 08:59:18 -0800283 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800284 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200285 unsigned long fclk_rate = 12000000;
286 unsigned long timeout;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800287 unsigned long internal_clk = 0;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530288 struct clk *fclk;
Komal Shah010d442c42006-08-13 23:44:09 +0200289
Andy Green4e80f722011-05-30 07:43:07 -0700290 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
Manjunatha GK57eb81b2009-12-11 11:09:08 +0530291 /* Disable I2C controller before soft reset */
292 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
293 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
294 ~(OMAP_I2C_CON_EN));
295
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800296 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
Komal Shah010d442c42006-08-13 23:44:09 +0200297 /* For some reason we need to set the EN bit before the
298 * reset done bit gets set. */
299 timeout = jiffies + OMAP_I2C_TIMEOUT;
300 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
301 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800302 SYSS_RESETDONE_MASK)) {
Komal Shah010d442c42006-08-13 23:44:09 +0200303 if (time_after(jiffies, timeout)) {
Joe Perchesfce3ff02007-12-12 13:45:24 +0100304 dev_warn(dev->dev, "timeout waiting "
Komal Shah010d442c42006-08-13 23:44:09 +0200305 "for controller reset\n");
306 return -ETIMEDOUT;
307 }
308 msleep(1);
309 }
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800310
311 /* SYSC register is cleared by the reset; rewrite it */
312 if (dev->rev == OMAP_I2C_REV_ON_2430) {
313
314 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
315 SYSC_AUTOIDLE_MASK);
316
Jon Hunterf518b482012-06-28 20:41:31 +0530317 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800318 dev->syscstate = SYSC_AUTOIDLE_MASK;
319 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
320 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800321 __ffs(SYSC_SIDLEMODE_MASK));
Rajendra Nayakef871432009-11-23 08:59:18 -0800322 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800323 __ffs(SYSC_CLOCKACTIVITY_MASK));
324
Rajendra Nayakef871432009-11-23 08:59:18 -0800325 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
326 dev->syscstate);
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800327 /*
328 * Enabling all wakup sources to stop I2C freezing on
329 * WFI instruction.
330 * REVISIT: Some wkup sources might not be needed.
331 */
Rajendra Nayakef871432009-11-23 08:59:18 -0800332 dev->westate = OMAP_I2C_WE_ALL;
Shubhrajyoti Dcb28e582011-08-03 13:58:08 +0530333 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
334 dev->westate);
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800335 }
Komal Shah010d442c42006-08-13 23:44:09 +0200336 }
337 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
338
Benoit Cousson61451972011-12-22 15:56:36 +0100339 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
Russell King0e9ae102009-01-22 19:31:46 +0000340 /*
341 * The I2C functional clock is the armxor_ck, so there's
342 * no need to get "armxor_ck" separately. Now, if OMAP2420
343 * always returns 12MHz for the functional clock, we can
344 * do this bit unconditionally.
345 */
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530346 fclk = clk_get(dev->dev, "fck");
347 fclk_rate = clk_get_rate(fclk);
348 clk_put(fclk);
Komal Shah010d442c42006-08-13 23:44:09 +0200349
Komal Shah010d442c42006-08-13 23:44:09 +0200350 /* TRM for 5912 says the I2C clock must be prescaled to be
351 * between 7 - 12 MHz. The XOR input clock is typically
352 * 12, 13 or 19.2 MHz. So we should have code that produces:
353 *
354 * XOR MHz Divider Prescaler
355 * 12 1 0
356 * 13 2 1
357 * 19.2 2 1
358 */
Jean Delvared7aef132006-12-10 21:21:34 +0100359 if (fclk_rate > 12000000)
360 psc = fclk_rate / 12000000;
Komal Shah010d442c42006-08-13 23:44:09 +0200361 }
362
Benoit Cousson61451972011-12-22 15:56:36 +0100363 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800364
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300365 /*
366 * HSI2C controller internal clk rate should be 19.2 Mhz for
367 * HS and for all modes on 2430. On 34xx we can use lower rate
368 * to get longer filter period for better noise suppression.
369 * The filter is iclk (fclk for HS) period.
370 */
Andy Green3be00532011-05-30 07:43:09 -0700371 if (dev->speed > 400 ||
Benoit Cousson61451972011-12-22 15:56:36 +0100372 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300373 internal_clk = 19200;
374 else if (dev->speed > 100)
375 internal_clk = 9600;
376 else
377 internal_clk = 4000;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530378 fclk = clk_get(dev->dev, "fck");
379 fclk_rate = clk_get_rate(fclk) / 1000;
380 clk_put(fclk);
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800381
382 /* Compute prescaler divisor */
383 psc = fclk_rate / internal_clk;
384 psc = psc - 1;
385
386 /* If configured for High Speed */
387 if (dev->speed > 400) {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300388 unsigned long scl;
389
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800390 /* For first phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300391 scl = internal_clk / 400;
392 fsscll = scl - (scl / 3) - 7;
393 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800394
395 /* For second phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300396 scl = fclk_rate / dev->speed;
397 hsscll = scl - (scl / 3) - 7;
398 hssclh = (scl / 3) - 5;
399 } else if (dev->speed > 100) {
400 unsigned long scl;
401
402 /* Fast mode */
403 scl = internal_clk / dev->speed;
404 fsscll = scl - (scl / 3) - 7;
405 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800406 } else {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300407 /* Standard mode */
408 fsscll = internal_clk / (dev->speed * 2) - 7;
409 fssclh = internal_clk / (dev->speed * 2) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800410 }
411 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
412 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
413 } else {
414 /* Program desired operating rate */
415 fclk_rate /= (psc + 1) * 1000;
416 if (psc > 2)
417 psc = 2;
418 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
419 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
420 }
421
Komal Shah010d442c42006-08-13 23:44:09 +0200422 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
423 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
424
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800425 /* SCL low and high time values */
426 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
427 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
Komal Shah010d442c42006-08-13 23:44:09 +0200428
429 /* Take the I2C module out of reset: */
430 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
431
432 /* Enable interrupts */
Rajendra Nayakef871432009-11-23 08:59:18 -0800433 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800434 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
435 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
Rajendra Nayakef871432009-11-23 08:59:18 -0800436 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
437 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
Benoit Cousson61451972011-12-22 15:56:36 +0100438 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800439 dev->pscstate = psc;
440 dev->scllstate = scll;
441 dev->sclhstate = sclh;
442 dev->bufstate = buf;
443 }
Komal Shah010d442c42006-08-13 23:44:09 +0200444 return 0;
445}
446
447/*
448 * Waiting on Bus Busy
449 */
450static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
451{
452 unsigned long timeout;
453
454 timeout = jiffies + OMAP_I2C_TIMEOUT;
455 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
456 if (time_after(jiffies, timeout)) {
457 dev_warn(dev->dev, "timeout waiting for bus ready\n");
458 return -ETIMEDOUT;
459 }
460 msleep(1);
461 }
462
463 return 0;
464}
465
Felipe Balbidd745482012-09-12 16:28:10 +0530466static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
467{
468 u16 buf;
469
470 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
471 return;
472
473 /*
474 * Set up notification threshold based on message size. We're doing
475 * this to try and avoid draining feature as much as possible. Whenever
476 * we have big messages to transfer (bigger than our total fifo size)
477 * then we might use draining feature to transfer the remaining bytes.
478 */
479
480 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
481
482 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
483
484 if (is_rx) {
485 /* Clear RX Threshold */
486 buf &= ~(0x3f << 8);
487 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
488 } else {
489 /* Clear TX Threshold */
490 buf &= ~0x3f;
491 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
492 }
493
494 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
495
496 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
497 dev->b_hw = 1; /* Enable hardware fixes */
498
499 /* calculate wakeup latency constraint for MPU */
Paul Walmsley49839dc2012-11-06 16:31:32 +0000500 if (dev->set_mpu_wkup_lat != NULL)
501 dev->latency = (1000000 * dev->threshold) /
502 (1000 * dev->speed / 8);
Felipe Balbidd745482012-09-12 16:28:10 +0530503}
504
Komal Shah010d442c42006-08-13 23:44:09 +0200505/*
506 * Low level master read/write transaction.
507 */
508static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
509 struct i2c_msg *msg, int stop)
510{
511 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530512 unsigned long timeout;
Komal Shah010d442c42006-08-13 23:44:09 +0200513 u16 w;
514
515 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
516 msg->addr, msg->len, msg->flags, stop);
517
518 if (msg->len == 0)
519 return -EINVAL;
520
Felipe Balbidd745482012-09-12 16:28:10 +0530521 dev->receiver = !!(msg->flags & I2C_M_RD);
522 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
523
Komal Shah010d442c42006-08-13 23:44:09 +0200524 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
525
526 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
527 dev->buf = msg->buf;
528 dev->buf_len = msg->len;
529
Felipe Balbid60ece52012-11-14 16:22:45 +0200530 /* make sure writes to dev->buf_len are ordered */
531 barrier();
532
Komal Shah010d442c42006-08-13 23:44:09 +0200533 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
534
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800535 /* Clear the FIFO Buffers */
536 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
537 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
538 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
539
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +0530540 INIT_COMPLETION(dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +0200541 dev->cmd_err = 0;
542
543 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800544
545 /* High speed configuration */
546 if (dev->speed > 400)
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800547 w |= OMAP_I2C_CON_OPMODE_HS;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800548
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200549 if (msg->flags & I2C_M_STOP)
550 stop = 1;
Komal Shah010d442c42006-08-13 23:44:09 +0200551 if (msg->flags & I2C_M_TEN)
552 w |= OMAP_I2C_CON_XA;
553 if (!(msg->flags & I2C_M_RD))
554 w |= OMAP_I2C_CON_TRX;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800555
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800556 if (!dev->b_hw && stop)
Komal Shah010d442c42006-08-13 23:44:09 +0200557 w |= OMAP_I2C_CON_STP;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800558
Komal Shah010d442c42006-08-13 23:44:09 +0200559 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
560
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800561 /*
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800562 * Don't write stt and stp together on some hardware.
563 */
564 if (dev->b_hw && stop) {
565 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
566 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
567 while (con & OMAP_I2C_CON_STT) {
568 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
569
570 /* Let the user know if i2c is in a bad state */
571 if (time_after(jiffies, delay)) {
572 dev_err(dev->dev, "controller timed out "
573 "waiting for start condition to finish\n");
574 return -ETIMEDOUT;
575 }
576 cpu_relax();
577 }
578
579 w |= OMAP_I2C_CON_STP;
580 w &= ~OMAP_I2C_CON_STT;
581 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
582 }
583
584 /*
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800585 * REVISIT: We should abort the transfer on signals, but the bus goes
586 * into arbitration and we're currently unable to recover from it.
587 */
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530588 timeout = wait_for_completion_timeout(&dev->cmd_complete,
589 OMAP_I2C_TIMEOUT);
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530590 if (timeout == 0) {
Komal Shah010d442c42006-08-13 23:44:09 +0200591 dev_err(dev->dev, "controller timed out\n");
592 omap_i2c_init(dev);
593 return -ETIMEDOUT;
594 }
595
596 if (likely(!dev->cmd_err))
597 return 0;
598
599 /* We have an error */
600 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
601 OMAP_I2C_STAT_XUDF)) {
602 omap_i2c_init(dev);
603 return -EIO;
604 }
605
606 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
607 if (msg->flags & I2C_M_IGNORE_NAK)
608 return 0;
609 if (stop) {
610 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
611 w |= OMAP_I2C_CON_STP;
612 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
613 }
614 return -EREMOTEIO;
615 }
616 return -EIO;
617}
618
619
620/*
621 * Prepare controller for a transaction and call omap_i2c_xfer_msg
622 * to do the work during IRQ processing.
623 */
624static int
625omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
626{
627 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
628 int i;
629 int r;
630
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +0530631 r = pm_runtime_get_sync(dev->dev);
632 if (IS_ERR_VALUE(r))
Kevin Hilman33ec5e82012-06-26 18:45:32 -0700633 goto out;
Komal Shah010d442c42006-08-13 23:44:09 +0200634
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800635 r = omap_i2c_wait_for_bb(dev);
636 if (r < 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200637 goto out;
638
Paul Walmsley49839dc2012-11-06 16:31:32 +0000639 if (dev->set_mpu_wkup_lat != NULL)
640 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
Samu Onkalo6a91b552010-11-18 12:04:20 +0200641
Komal Shah010d442c42006-08-13 23:44:09 +0200642 for (i = 0; i < num; i++) {
643 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
644 if (r != 0)
645 break;
646 }
647
Paul Walmsley49839dc2012-11-06 16:31:32 +0000648 if (dev->set_mpu_wkup_lat != NULL)
649 dev->set_mpu_wkup_lat(dev->dev, -1);
Samu Onkalo6a91b552010-11-18 12:04:20 +0200650
Komal Shah010d442c42006-08-13 23:44:09 +0200651 if (r == 0)
652 r = num;
Mathias Nyman5c64eb22010-08-26 07:36:44 +0000653
654 omap_i2c_wait_for_bb(dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200655out:
Felipe Balbi6d8451d2012-09-12 16:28:15 +0530656 pm_runtime_mark_last_busy(dev->dev);
657 pm_runtime_put_autosuspend(dev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200658 return r;
659}
660
661static u32
662omap_i2c_func(struct i2c_adapter *adap)
663{
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200664 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
665 I2C_FUNC_PROTOCOL_MANGLING;
Komal Shah010d442c42006-08-13 23:44:09 +0200666}
667
668static inline void
669omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
670{
671 dev->cmd_err |= err;
672 complete(&dev->cmd_complete);
673}
674
675static inline void
676omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
677{
678 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
679}
680
manjugk manjugkf3083d92010-05-11 11:35:20 -0700681static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
682{
683 /*
684 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
685 * Not applicable for OMAP4.
686 * Under certain rare conditions, RDR could be set again
687 * when the bus is busy, then ignore the interrupt and
688 * clear the interrupt.
689 */
690 if (stat & OMAP_I2C_STAT_RDR) {
691 /* Step 1: If RDR is set, clear it */
692 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
693
694 /* Step 2: */
695 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
696 & OMAP_I2C_STAT_BB)) {
697
698 /* Step 3: */
699 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
700 & OMAP_I2C_STAT_RDR) {
701 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
702 dev_dbg(dev->dev, "RDR when bus is busy.\n");
703 }
704
705 }
706 }
707}
708
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800709/* rev1 devices are apparently only on some 15xx */
710#ifdef CONFIG_ARCH_OMAP15XX
711
Komal Shah010d442c42006-08-13 23:44:09 +0200712static irqreturn_t
Andy Green4e80f722011-05-30 07:43:07 -0700713omap_i2c_omap1_isr(int this_irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200714{
715 struct omap_i2c_dev *dev = dev_id;
716 u16 iv, w;
717
Kevin Hilmanfab67af2011-05-17 16:31:38 +0200718 if (pm_runtime_suspended(dev->dev))
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100719 return IRQ_NONE;
720
Komal Shah010d442c42006-08-13 23:44:09 +0200721 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
722 switch (iv) {
723 case 0x00: /* None */
724 break;
725 case 0x01: /* Arbitration lost */
726 dev_err(dev->dev, "Arbitration lost\n");
727 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
728 break;
729 case 0x02: /* No acknowledgement */
730 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
731 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
732 break;
733 case 0x03: /* Register access ready */
734 omap_i2c_complete_cmd(dev, 0);
735 break;
736 case 0x04: /* Receive data ready */
737 if (dev->buf_len) {
738 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
739 *dev->buf++ = w;
740 dev->buf_len--;
741 if (dev->buf_len) {
742 *dev->buf++ = w >> 8;
743 dev->buf_len--;
744 }
745 } else
746 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
747 break;
748 case 0x05: /* Transmit data ready */
749 if (dev->buf_len) {
750 w = *dev->buf++;
751 dev->buf_len--;
752 if (dev->buf_len) {
753 w |= *dev->buf++ << 8;
754 dev->buf_len--;
755 }
756 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
757 } else
758 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
759 break;
760 default:
761 return IRQ_NONE;
762 }
763
764 return IRQ_HANDLED;
765}
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800766#else
Andy Green4e80f722011-05-30 07:43:07 -0700767#define omap_i2c_omap1_isr NULL
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800768#endif
Komal Shah010d442c42006-08-13 23:44:09 +0200769
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700770/*
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530771 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700772 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
773 * them from the memory to the I2C interface.
774 */
Felipe Balbi4151e742012-09-12 16:28:01 +0530775static int errata_omap3_i462(struct omap_i2c_dev *dev)
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700776{
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700777 unsigned long timeout = 10000;
Felipe Balbi4151e742012-09-12 16:28:01 +0530778 u16 stat;
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700779
Felipe Balbi4151e742012-09-12 16:28:01 +0530780 do {
781 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
782 if (stat & OMAP_I2C_STAT_XUDF)
783 break;
784
785 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530786 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700787 OMAP_I2C_STAT_XDR));
Felipe Balbib07be0f2012-09-12 16:28:11 +0530788 if (stat & OMAP_I2C_STAT_NACK) {
789 dev->cmd_err |= OMAP_I2C_STAT_NACK;
790 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
791 }
792
793 if (stat & OMAP_I2C_STAT_AL) {
794 dev_err(dev->dev, "Arbitration lost\n");
795 dev->cmd_err |= OMAP_I2C_STAT_AL;
796 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
797 }
798
Felipe Balbi4151e742012-09-12 16:28:01 +0530799 return -EIO;
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700800 }
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700801
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700802 cpu_relax();
Felipe Balbi4151e742012-09-12 16:28:01 +0530803 } while (--timeout);
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700804
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700805 if (!timeout) {
806 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
807 return 0;
808 }
809
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700810 return 0;
811}
812
Felipe Balbi3312d252012-09-12 16:28:02 +0530813static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
814 bool is_rdr)
815{
816 u16 w;
817
818 while (num_bytes--) {
Felipe Balbi3312d252012-09-12 16:28:02 +0530819 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
820 *dev->buf++ = w;
821 dev->buf_len--;
822
823 /*
824 * Data reg in 2430, omap3 and
825 * omap4 is 8 bit wide
826 */
827 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
Felipe Balbidd745482012-09-12 16:28:10 +0530828 *dev->buf++ = w >> 8;
829 dev->buf_len--;
Felipe Balbi3312d252012-09-12 16:28:02 +0530830 }
831 }
832}
833
834static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
835 bool is_xdr)
836{
837 u16 w;
838
839 while (num_bytes--) {
Felipe Balbi3312d252012-09-12 16:28:02 +0530840 w = *dev->buf++;
841 dev->buf_len--;
842
843 /*
844 * Data reg in 2430, omap3 and
845 * omap4 is 8 bit wide
846 */
847 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
Felipe Balbidd745482012-09-12 16:28:10 +0530848 w |= *dev->buf++ << 8;
849 dev->buf_len--;
Felipe Balbi3312d252012-09-12 16:28:02 +0530850 }
851
852 if (dev->errata & I2C_OMAP_ERRATA_I462) {
853 int ret;
854
855 ret = errata_omap3_i462(dev);
856 if (ret < 0)
857 return ret;
858 }
859
860 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
861 }
862
Komal Shah010d442c42006-08-13 23:44:09 +0200863 return 0;
864}
865
866static irqreturn_t
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530867omap_i2c_isr(int irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200868{
869 struct omap_i2c_dev *dev = dev_id;
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530870 irqreturn_t ret = IRQ_HANDLED;
871 u16 mask;
872 u16 stat;
873
874 spin_lock(&dev->lock);
875 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
876 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
877
878 if (stat & mask)
879 ret = IRQ_WAKE_THREAD;
880
881 spin_unlock(&dev->lock);
882
883 return ret;
884}
885
886static irqreturn_t
887omap_i2c_isr_thread(int this_irq, void *dev_id)
888{
889 struct omap_i2c_dev *dev = dev_id;
890 unsigned long flags;
Komal Shah010d442c42006-08-13 23:44:09 +0200891 u16 bits;
Felipe Balbi3312d252012-09-12 16:28:02 +0530892 u16 stat;
Felipe Balbi66b92982012-09-12 16:28:03 +0530893 int err = 0, count = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200894
Felipe Balbi3b2f8f82012-09-12 16:28:13 +0530895 spin_lock_irqsave(&dev->lock, flags);
Felipe Balbi66b92982012-09-12 16:28:03 +0530896 do {
897 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
898 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
899 stat &= bits;
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100900
Felipe Balbi079d8af2012-09-12 16:28:06 +0530901 /* If we're in receiver mode, ignore XDR/XRDY */
902 if (dev->receiver)
903 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
904 else
905 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
906
Felipe Balbi66b92982012-09-12 16:28:03 +0530907 if (!stat) {
908 /* my work here is done */
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530909 goto out;
Felipe Balbi66b92982012-09-12 16:28:03 +0530910 }
911
Komal Shah010d442c42006-08-13 23:44:09 +0200912 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
913 if (count++ == 100) {
914 dev_warn(dev->dev, "Too much work in one IRQ\n");
915 break;
916 }
917
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530918 if (stat & OMAP_I2C_STAT_NACK) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800919 err |= OMAP_I2C_STAT_NACK;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530920 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530921 break;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530922 }
Jan Weitzel78e1cf42011-12-07 11:50:16 -0800923
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800924 if (stat & OMAP_I2C_STAT_AL) {
925 dev_err(dev->dev, "Arbitration lost\n");
926 err |= OMAP_I2C_STAT_AL;
Felipe Balbi1d7afc92012-09-12 16:28:04 +0530927 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530928 break;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800929 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530930
Ben Dooksa5a595c2011-02-23 00:43:55 +0000931 /*
Richard woodruffcb527ed2011-02-16 10:24:16 +0530932 * ProDB0017052: Clear ARDY bit twice
Ben Dooksa5a595c2011-02-23 00:43:55 +0000933 */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800934 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500935 OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530936 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
937 OMAP_I2C_STAT_RDR |
938 OMAP_I2C_STAT_XRDY |
939 OMAP_I2C_STAT_XDR |
940 OMAP_I2C_STAT_ARDY));
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530941 break;
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500942 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530943
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530944 if (stat & OMAP_I2C_STAT_RDR) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800945 u8 num_bytes = 1;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700946
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530947 if (dev->fifo_size)
948 num_bytes = dev->buf_len;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700949
Felipe Balbi3312d252012-09-12 16:28:02 +0530950 omap_i2c_receive_data(dev, num_bytes, true);
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530951
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800952 if (dev->errata & I2C_OMAP_ERRATA_I207)
953 i2c_omap_errata_i207(dev, stat);
Komal Shah010d442c42006-08-13 23:44:09 +0200954
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530955 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530956 break;
Komal Shah010d442c42006-08-13 23:44:09 +0200957 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530958
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530959 if (stat & OMAP_I2C_STAT_RRDY) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800960 u8 num_bytes = 1;
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500961
Felipe Balbidd745482012-09-12 16:28:10 +0530962 if (dev->threshold)
963 num_bytes = dev->threshold;
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500964
Felipe Balbi3312d252012-09-12 16:28:02 +0530965 omap_i2c_receive_data(dev, num_bytes, false);
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530966 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
Komal Shah010d442c42006-08-13 23:44:09 +0200967 continue;
968 }
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530969
970 if (stat & OMAP_I2C_STAT_XDR) {
971 u8 num_bytes = 1;
Felipe Balbi3312d252012-09-12 16:28:02 +0530972 int ret;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530973
974 if (dev->fifo_size)
975 num_bytes = dev->buf_len;
976
Felipe Balbi3312d252012-09-12 16:28:02 +0530977 ret = omap_i2c_transmit_data(dev, num_bytes, true);
Felipe Balbi3312d252012-09-12 16:28:02 +0530978 if (ret < 0)
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530979 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530980
981 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530982 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530983 }
984
985 if (stat & OMAP_I2C_STAT_XRDY) {
986 u8 num_bytes = 1;
Felipe Balbi3312d252012-09-12 16:28:02 +0530987 int ret;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530988
Felipe Balbidd745482012-09-12 16:28:10 +0530989 if (dev->threshold)
990 num_bytes = dev->threshold;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530991
Felipe Balbi3312d252012-09-12 16:28:02 +0530992 ret = omap_i2c_transmit_data(dev, num_bytes, false);
Felipe Balbi3312d252012-09-12 16:28:02 +0530993 if (ret < 0)
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +0530994 break;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530995
996 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
Komal Shah010d442c42006-08-13 23:44:09 +0200997 continue;
998 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530999
Komal Shah010d442c42006-08-13 23:44:09 +02001000 if (stat & OMAP_I2C_STAT_ROVR) {
1001 dev_err(dev->dev, "Receive overrun\n");
Felipe Balbi1d7afc92012-09-12 16:28:04 +05301002 err |= OMAP_I2C_STAT_ROVR;
1003 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301004 break;
Komal Shah010d442c42006-08-13 23:44:09 +02001005 }
Felipe Balbic55edb92012-09-12 16:27:58 +05301006
Komal Shah010d442c42006-08-13 23:44:09 +02001007 if (stat & OMAP_I2C_STAT_XUDF) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001008 dev_err(dev->dev, "Transmit underflow\n");
Felipe Balbi1d7afc92012-09-12 16:28:04 +05301009 err |= OMAP_I2C_STAT_XUDF;
1010 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301011 break;
Komal Shah010d442c42006-08-13 23:44:09 +02001012 }
Felipe Balbi66b92982012-09-12 16:28:03 +05301013 } while (stat);
Komal Shah010d442c42006-08-13 23:44:09 +02001014
Felipe Balbi4a7ec4e2012-09-12 16:28:09 +05301015 omap_i2c_complete_cmd(dev, err);
Felipe Balbi0bdfe0c2012-09-12 16:28:16 +05301016
1017out:
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301018 spin_unlock_irqrestore(&dev->lock, flags);
1019
Felipe Balbi6a85ced2012-09-12 16:28:08 +05301020 return IRQ_HANDLED;
Komal Shah010d442c42006-08-13 23:44:09 +02001021}
1022
Jean Delvare8f9082c2006-09-03 22:39:46 +02001023static const struct i2c_algorithm omap_i2c_algo = {
Komal Shah010d442c42006-08-13 23:44:09 +02001024 .master_xfer = omap_i2c_xfer,
1025 .functionality = omap_i2c_func,
1026};
1027
Benoit Cousson61451972011-12-22 15:56:36 +01001028#ifdef CONFIG_OF
1029static struct omap_i2c_bus_platform_data omap3_pdata = {
1030 .rev = OMAP_I2C_IP_VERSION_1,
1031 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1032 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1033 OMAP_I2C_FLAG_BUS_SHIFT_2,
1034};
1035
1036static struct omap_i2c_bus_platform_data omap4_pdata = {
1037 .rev = OMAP_I2C_IP_VERSION_2,
1038};
1039
1040static const struct of_device_id omap_i2c_of_match[] = {
1041 {
1042 .compatible = "ti,omap4-i2c",
1043 .data = &omap4_pdata,
1044 },
1045 {
1046 .compatible = "ti,omap3-i2c",
1047 .data = &omap3_pdata,
1048 },
1049 { },
1050};
1051MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1052#endif
1053
Uwe Kleine-König1139aea2010-02-04 20:56:53 +01001054static int __devinit
Komal Shah010d442c42006-08-13 23:44:09 +02001055omap_i2c_probe(struct platform_device *pdev)
1056{
1057 struct omap_i2c_dev *dev;
1058 struct i2c_adapter *adap;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301059 struct resource *mem;
Uwe Kleine-Königc4dba012012-05-21 21:57:39 +02001060 const struct omap_i2c_bus_platform_data *pdata =
1061 pdev->dev.platform_data;
Benoit Cousson61451972011-12-22 15:56:36 +01001062 struct device_node *node = pdev->dev.of_node;
1063 const struct of_device_id *match;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301064 int irq;
Komal Shah010d442c42006-08-13 23:44:09 +02001065 int r;
1066
1067 /* NOTE: driver uses the static register mapping */
1068 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069 if (!mem) {
1070 dev_err(&pdev->dev, "no mem resource?\n");
1071 return -ENODEV;
1072 }
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301073
1074 irq = platform_get_irq(pdev, 0);
1075 if (irq < 0) {
Komal Shah010d442c42006-08-13 23:44:09 +02001076 dev_err(&pdev->dev, "no irq resource?\n");
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301077 return irq;
Komal Shah010d442c42006-08-13 23:44:09 +02001078 }
1079
Felipe Balbid9ebd042012-09-12 16:27:55 +05301080 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
Komal Shah010d442c42006-08-13 23:44:09 +02001081 if (!dev) {
Felipe Balbid9ebd042012-09-12 16:27:55 +05301082 dev_err(&pdev->dev, "Menory allocation failed\n");
1083 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001084 }
1085
Felipe Balbid9ebd042012-09-12 16:27:55 +05301086 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1087 if (!dev->base) {
1088 dev_err(&pdev->dev, "I2C region already claimed\n");
1089 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001090 }
1091
Cousson, Benoit6c5aa402012-01-20 16:55:04 +01001092 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
Benoit Cousson61451972011-12-22 15:56:36 +01001093 if (match) {
1094 u32 freq = 100000; /* default to 100000 Hz */
1095
1096 pdata = match->data;
1097 dev->dtrev = pdata->rev;
1098 dev->flags = pdata->flags;
1099
1100 of_property_read_u32(node, "clock-frequency", &freq);
1101 /* convert DT freq value in Hz into kHz for speed */
1102 dev->speed = freq / 1000;
1103 } else if (pdata != NULL) {
1104 dev->speed = pdata->clkrate;
1105 dev->flags = pdata->flags;
Paul Walmsley49839dc2012-11-06 16:31:32 +00001106 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
Benoit Cousson61451972011-12-22 15:56:36 +01001107 dev->dtrev = pdata->rev;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001108 }
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -08001109
Sebastien Guiriec2d4b4522012-10-16 15:23:20 +00001110 dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
1111 if (IS_ERR(dev->pins)) {
1112 if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
1113 return -EPROBE_DEFER;
1114
1115 dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
1116 PTR_ERR(dev->pins));
1117 dev->pins = NULL;
1118 }
1119
Komal Shah010d442c42006-08-13 23:44:09 +02001120 dev->dev = &pdev->dev;
Felipe Balbiac79e4b2012-09-12 16:28:05 +05301121 dev->irq = irq;
Russell King55c381e2008-09-04 14:07:22 +01001122
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301123 spin_lock_init(&dev->lock);
Komal Shah010d442c42006-08-13 23:44:09 +02001124
1125 platform_set_drvdata(pdev, dev);
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +05301126 init_completion(&dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +02001127
Benoit Cousson61451972011-12-22 15:56:36 +01001128 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
Mika Westerberg7c6bd202010-03-23 12:12:56 +02001129
Benoit Cousson61451972011-12-22 15:56:36 +01001130 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
Andy Greena1295572011-05-30 07:43:06 -07001131 dev->regs = (u8 *)reg_map_ip_v2;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001132 else
Andy Greena1295572011-05-30 07:43:06 -07001133 dev->regs = (u8 *)reg_map_ip_v1;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001134
Kevin Hilman7f4b08e2011-05-17 16:31:37 +02001135 pm_runtime_enable(dev->dev);
Felipe Balbi6d8451d2012-09-12 16:28:15 +05301136 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1137 pm_runtime_use_autosuspend(dev->dev);
1138
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301139 r = pm_runtime_get_sync(dev->dev);
1140 if (IS_ERR_VALUE(r))
1141 goto err_free_mem;
Komal Shah010d442c42006-08-13 23:44:09 +02001142
Paul Walmsley9c76b872008-11-21 13:39:55 -08001143 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
Komal Shah010d442c42006-08-13 23:44:09 +02001144
Tasslehoff Kjappfot9aa8ec62012-05-29 16:26:20 +05301145 dev->errata = 0;
1146
1147 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1148 dev->errata |= I2C_OMAP_ERRATA_I207;
1149
Jon Hunterf518b482012-06-28 20:41:31 +05301150 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +05301151 dev->errata |= I2C_OMAP_ERRATA_I462;
manjugk manjugk8a9d97d2010-05-11 11:35:23 -07001152
Benoit Cousson61451972011-12-22 15:56:36 +01001153 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001154 u16 s;
1155
1156 /* Set up the fifo size - Get total size */
1157 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1158 dev->fifo_size = 0x8 << s;
1159
1160 /*
1161 * Set up notification threshold as half the total available
1162 * size. This is to ensure that we can handle the status on int
1163 * call back latencies.
1164 */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001165
1166 dev->fifo_size = (dev->fifo_size / 2);
1167
Felipe Balbi3ff44432012-09-12 16:28:07 +05301168 if (dev->rev < OMAP_I2C_REV_ON_3630_4430)
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001169 dev->b_hw = 1; /* Enable hardware fixes */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001170
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001171 /* calculate wakeup latency constraint for MPU */
Paul Walmsley49839dc2012-11-06 16:31:32 +00001172 if (dev->set_mpu_wkup_lat != NULL)
1173 dev->latency = (1000000 * dev->fifo_size) /
1174 (1000 * dev->speed / 8);
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001175 }
1176
Komal Shah010d442c42006-08-13 23:44:09 +02001177 /* reset ASAP, clearing any IRQs */
1178 omap_i2c_init(dev);
1179
Felipe Balbi3b2f8f82012-09-12 16:28:13 +05301180 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1181 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1182 IRQF_NO_SUSPEND, pdev->name, dev);
1183 else
1184 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1185 omap_i2c_isr, omap_i2c_isr_thread,
1186 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1187 pdev->name, dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001188
1189 if (r) {
1190 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1191 goto err_unuse_clocks;
1192 }
Paul Walmsley9c76b872008-11-21 13:39:55 -08001193
Komal Shah010d442c42006-08-13 23:44:09 +02001194 adap = &dev->adapter;
1195 i2c_set_adapdata(adap, dev);
1196 adap->owner = THIS_MODULE;
1197 adap->class = I2C_CLASS_HWMON;
Roel Kluin783fd6f2009-07-17 15:24:00 +02001198 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
Komal Shah010d442c42006-08-13 23:44:09 +02001199 adap->algo = &omap_i2c_algo;
1200 adap->dev.parent = &pdev->dev;
Benoit Cousson61451972011-12-22 15:56:36 +01001201 adap->dev.of_node = pdev->dev.of_node;
Komal Shah010d442c42006-08-13 23:44:09 +02001202
1203 /* i2c device drivers may be active on return from add_adapter() */
David Brownell7c175492007-05-01 23:26:32 +02001204 adap->nr = pdev->id;
1205 r = i2c_add_numbered_adapter(adap);
Komal Shah010d442c42006-08-13 23:44:09 +02001206 if (r) {
1207 dev_err(dev->dev, "failure adding adapter\n");
Felipe Balbid9ebd042012-09-12 16:27:55 +05301208 goto err_unuse_clocks;
Komal Shah010d442c42006-08-13 23:44:09 +02001209 }
1210
Florian Vaussardc5d3cd62012-08-31 13:02:55 +02001211 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr,
1212 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1213
Benoit Cousson61451972011-12-22 15:56:36 +01001214 of_i2c_register_devices(adap);
1215
Felipe Balbi6d8451d2012-09-12 16:28:15 +05301216 pm_runtime_mark_last_busy(dev->dev);
1217 pm_runtime_put_autosuspend(dev->dev);
Shubhrajyoti D62ff2c22012-05-29 16:26:16 +05301218
Komal Shah010d442c42006-08-13 23:44:09 +02001219 return 0;
1220
Komal Shah010d442c42006-08-13 23:44:09 +02001221err_unuse_clocks:
Tony Lindgren3e397522008-01-14 21:53:30 +01001222 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001223 pm_runtime_put(dev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301224 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001225err_free_mem:
1226 platform_set_drvdata(pdev, NULL);
Komal Shah010d442c42006-08-13 23:44:09 +02001227
1228 return r;
1229}
1230
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301231static int __devexit omap_i2c_remove(struct platform_device *pdev)
Komal Shah010d442c42006-08-13 23:44:09 +02001232{
1233 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301234 int ret;
Komal Shah010d442c42006-08-13 23:44:09 +02001235
1236 platform_set_drvdata(pdev, NULL);
1237
Komal Shah010d442c42006-08-13 23:44:09 +02001238 i2c_del_adapter(&dev->adapter);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301239 ret = pm_runtime_get_sync(&pdev->dev);
1240 if (IS_ERR_VALUE(ret))
1241 return ret;
1242
Komal Shah010d442c42006-08-13 23:44:09 +02001243 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Shubhrajyoti D0861f432012-05-29 16:26:18 +05301244 pm_runtime_put(&pdev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301245 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001246 return 0;
1247}
1248
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301249#ifdef CONFIG_PM
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001250#ifdef CONFIG_PM_RUNTIME
1251static int omap_i2c_runtime_suspend(struct device *dev)
1252{
1253 struct platform_device *pdev = to_platform_device(dev);
1254 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301255 u16 iv;
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001256
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301257 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
Shubhrajyoti Dbd16c822012-05-29 16:26:15 +05301258
1259 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301260
1261 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1262 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1263 } else {
1264 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1265
1266 /* Flush posted write */
1267 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1268 }
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001269
1270 return 0;
1271}
1272
1273static int omap_i2c_runtime_resume(struct device *dev)
1274{
1275 struct platform_device *pdev = to_platform_device(dev);
1276 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1277
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301278 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1279 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1280 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1281 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1282 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1283 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1284 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1285 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1286 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1287 }
1288
1289 /*
1290 * Don't write to this register if the IE state is 0 as it can
1291 * cause deadlock.
1292 */
1293 if (_dev->iestate)
1294 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001295
1296 return 0;
1297}
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301298#endif /* CONFIG_PM_RUNTIME */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001299
1300static struct dev_pm_ops omap_i2c_pm_ops = {
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301301 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1302 omap_i2c_runtime_resume, NULL)
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001303};
1304#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1305#else
1306#define OMAP_I2C_PM_OPS NULL
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301307#endif /* CONFIG_PM */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001308
Komal Shah010d442c42006-08-13 23:44:09 +02001309static struct platform_driver omap_i2c_driver = {
1310 .probe = omap_i2c_probe,
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301311 .remove = __devexit_p(omap_i2c_remove),
Komal Shah010d442c42006-08-13 23:44:09 +02001312 .driver = {
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001313 .name = "omap_i2c",
Komal Shah010d442c42006-08-13 23:44:09 +02001314 .owner = THIS_MODULE,
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001315 .pm = OMAP_I2C_PM_OPS,
Benoit Cousson61451972011-12-22 15:56:36 +01001316 .of_match_table = of_match_ptr(omap_i2c_of_match),
Komal Shah010d442c42006-08-13 23:44:09 +02001317 },
1318};
1319
1320/* I2C may be needed to bring up other drivers */
1321static int __init
1322omap_i2c_init_driver(void)
1323{
1324 return platform_driver_register(&omap_i2c_driver);
1325}
1326subsys_initcall(omap_i2c_init_driver);
1327
1328static void __exit omap_i2c_exit_driver(void)
1329{
1330 platform_driver_unregister(&omap_i2c_driver);
1331}
1332module_exit(omap_i2c_exit_driver);
1333
1334MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1335MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1336MODULE_LICENSE("GPL");
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001337MODULE_ALIAS("platform:omap_i2c");