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authorRichard Henderson <rth@twiddle.net>2015-08-30 09:25:36 -0700
committerRichard Henderson <rth@twiddle.net>2015-10-07 20:36:46 +1100
commitc20d594e45bc8c4b21be1a7637cba0f279f72879 (patch)
treed71834d965061f6844161a3754c67967ab7fac77
parent2066d09516ba34d0d180fdea451436d9babb3308 (diff)
downloadqemu-arm-c20d594e45bc8c4b21be1a7637cba0f279f72879.tar.gz
target-mips: Add delayed branch state to insn_start
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--target-mips/cpu.h1
-rw-r--r--target-mips/translate.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index ec5f991dfb..532b39ea1f 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -130,6 +130,7 @@ struct CPUMIPSFPUContext {
};
#define NB_MMU_MODES 3
+#define TARGET_INSN_START_EXTRA_WORDS 2
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 57e826db21..30d7d46c47 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19562,6 +19562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb;
ctx.bstate = BS_NONE;
+ ctx.btarget = 0;
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
@@ -19603,7 +19604,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
tcg_ctx.gen_opc_instr_start[lj] = 1;
tcg_ctx.gen_opc_icount[lj] = num_insns;
}
- tcg_gen_insn_start(ctx.pc);
+ tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
num_insns++;
if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {