diff options
Diffstat (limited to 'lib/Basic/Targets')
46 files changed, 565 insertions, 267 deletions
diff --git a/lib/Basic/Targets/AArch64.cpp b/lib/Basic/Targets/AArch64.cpp index 62919a02dc..120a0e2d4e 100644 --- a/lib/Basic/Targets/AArch64.cpp +++ b/lib/Basic/Targets/AArch64.cpp @@ -1,9 +1,8 @@ //===--- AArch64.cpp - Implement AArch64 target feature support -----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -50,6 +49,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, // All AArch64 implementations support ARMv8 FP, which makes half a legal type. HasLegalHalfType = true; + HasFloat16 = true; LongWidth = LongAlign = PointerWidth = PointerAlign = 64; MaxVectorAlign = 128; @@ -194,6 +194,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasDotProd) Builder.defineMacro("__ARM_FEATURE_DOTPROD", "1"); + if (HasMTE) + Builder.defineMacro("__ARM_FEATURE_MEMORY_TAGGING", "1"); + if ((FPU & NeonMode) && HasFP16FML) Builder.defineMacro("__ARM_FEATURE_FP16FML", "1"); @@ -235,6 +238,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasFullFP16 = 0; HasDotProd = 0; HasFP16FML = 0; + HasMTE = 0; ArchKind = llvm::AArch64::ArchKind::ARMV8A; for (const auto &Feature : Features) { @@ -258,6 +262,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasDotProd = 1; if (Feature == "+fp16fml") HasFP16FML = 1; + if (Feature == "+mte") + HasMTE = 1; } setDataLayout(); @@ -545,6 +551,23 @@ MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const { return CCK_MicrosoftWin64; } +unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const { + unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize); + + // MSVC does size based alignment for arm64 based on alignment section in + // below document, replicate that to keep alignment consistent with object + // files compiled by MSVC. + // https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions + if (TypeSize >= 512) { // TypeSize >= 64 bytes + Align = std::max(Align, 128u); // align type at least 16 bytes + } else if (TypeSize >= 64) { // TypeSize >= 8 bytes + Align = std::max(Align, 64u); // align type at least 8 butes + } else if (TypeSize >= 16) { // TypeSize >= 2 bytes + Align = std::max(Align, 32u); // align type at least 4 bytes + } + return Align; +} + MinGWARM64TargetInfo::MinGWARM64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : WindowsARM64TargetInfo(Triple, Opts) { diff --git a/lib/Basic/Targets/AArch64.h b/lib/Basic/Targets/AArch64.h index d7f767abd4..73fd3bde5a 100644 --- a/lib/Basic/Targets/AArch64.h +++ b/lib/Basic/Targets/AArch64.h @@ -1,9 +1,8 @@ //===--- AArch64.h - Declare AArch64 target feature support -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -35,6 +34,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { unsigned HasFullFP16; unsigned HasDotProd; unsigned HasFP16FML; + unsigned HasMTE; llvm::AArch64::ArchKind ArchKind; static const Builtin::Info BuiltinInfo[]; @@ -129,6 +129,8 @@ public: MacroBuilder &Builder) const override; TargetInfo::CallingConvKind getCallingConvKind(bool ClangABICompat4) const override; + + unsigned getMinGlobalAlign(uint64_t TypeSize) const override; }; // ARM64 MinGW target diff --git a/lib/Basic/Targets/AMDGPU.cpp b/lib/Basic/Targets/AMDGPU.cpp index 7313a692f4..922f02f73d 100644 --- a/lib/Basic/Targets/AMDGPU.cpp +++ b/lib/Basic/Targets/AMDGPU.cpp @@ -1,9 +1,8 @@ //===--- AMDGPU.cpp - Implement AMDGPU target feature support -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -35,7 +34,8 @@ static const char *const DataLayoutStringR600 = static const char *const DataLayoutStringAMDGCN = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" - "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"; + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" + "-ni:7"; const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = { Generic, // Default @@ -137,7 +137,8 @@ bool AMDGPUTargetInfo::initFeatureMap( switch (llvm::AMDGPU::parseArchAMDGCN(CPU)) { case GK_GFX906: Features["dl-insts"] = true; - Features["dot-insts"] = true; + Features["dot1-insts"] = true; + Features["dot2-insts"] = true; LLVM_FALLTHROUGH; case GK_GFX909: case GK_GFX904: @@ -149,7 +150,7 @@ bool AMDGPUTargetInfo::initFeatureMap( case GK_GFX803: case GK_GFX802: case GK_GFX801: - Features["vi-insts"] = true; + Features["gfx8-insts"] = true; Features["16-bit-insts"] = true; Features["dpp"] = true; Features["s-memrealtime"] = true; @@ -251,6 +252,9 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple, !isAMDGCN(Triple)); UseAddrSpaceMapMangling = true; + HasLegalHalfType = true; + HasFloat16 = true; + // Set pointer width and alignment for target address space 0. PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); if (getMaxPointerWidth() == 64) { @@ -306,3 +310,18 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, if (hasFastFMA()) Builder.defineMacro("FP_FAST_FMA"); } + +void AMDGPUTargetInfo::setAuxTarget(const TargetInfo *Aux) { + assert(HalfFormat == Aux->HalfFormat); + assert(FloatFormat == Aux->FloatFormat); + assert(DoubleFormat == Aux->DoubleFormat); + + // On x86_64 long double is 80-bit extended precision format, which is + // not supported by AMDGPU. 128-bit floating point format is also not + // supported by AMDGPU. Therefore keep its own format for these two types. + auto SaveLongDoubleFormat = LongDoubleFormat; + auto SaveFloat128Format = Float128Format; + copyAuxTarget(Aux); + LongDoubleFormat = SaveLongDoubleFormat; + Float128Format = SaveFloat128Format; +} diff --git a/lib/Basic/Targets/AMDGPU.h b/lib/Basic/Targets/AMDGPU.h index 926772809a..e78e766672 100644 --- a/lib/Basic/Targets/AMDGPU.h +++ b/lib/Basic/Targets/AMDGPU.h @@ -1,9 +1,8 @@ //===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -352,6 +351,8 @@ public: uint64_t getNullPointerValue(LangAS AS) const override { return AS == LangAS::opencl_local ? ~0 : 0; } + + void setAuxTarget(const TargetInfo *Aux) override; }; } // namespace targets diff --git a/lib/Basic/Targets/ARC.cpp b/lib/Basic/Targets/ARC.cpp index 2159ab8e20..5cc13e2cf7 100644 --- a/lib/Basic/Targets/ARC.cpp +++ b/lib/Basic/Targets/ARC.cpp @@ -1,9 +1,8 @@ //===--- ARC.cpp - Implement ARC target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -22,4 +21,4 @@ using namespace clang::targets; void ARCTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__arc__"); -}
+} diff --git a/lib/Basic/Targets/ARC.h b/lib/Basic/Targets/ARC.h index ee20568f3d..c43a39984e 100644 --- a/lib/Basic/Targets/ARC.h +++ b/lib/Basic/Targets/ARC.h @@ -1,9 +1,8 @@ //===--- ARC.h - Declare ARC target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/ARM.cpp b/lib/Basic/Targets/ARM.cpp index 16644ace10..b74514ea2c 100644 --- a/lib/Basic/Targets/ARM.cpp +++ b/lib/Basic/Targets/ARM.cpp @@ -1,9 +1,8 @@ //===--- ARM.cpp - Implement ARM target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -41,13 +40,14 @@ void ARMTargetInfo::setABIAAPCS() { // so set preferred for small types to 32. if (T.isOSBinFormatMachO()) { resetDataLayout(BigEndian - ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" - : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); + ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); } else if (T.isOSWindows()) { assert(!BigEndian && "Windows on ARM does not support big endian"); resetDataLayout("e" "-m:w" "-p:32:32" + "-Fi8" "-i64:64" "-v128:64:128" "-a:0:32" @@ -55,11 +55,11 @@ void ARMTargetInfo::setABIAAPCS() { "-S64"); } else if (T.isOSNaCl()) { assert(!BigEndian && "NaCl on ARM does not support big endian"); - resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); + resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"); } else { resetDataLayout(BigEndian - ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" - : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); + ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); } // FIXME: Enumerated types are variable width in straight AAPCS. @@ -88,17 +88,17 @@ void ARMTargetInfo::setABIAPCS(bool IsAAPCS16) { if (T.isOSBinFormatMachO() && IsAAPCS16) { assert(!BigEndian && "AAPCS16 does not support big-endian"); - resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); + resetDataLayout("e-m:o-p:32:32-Fi8-i64:64-a:0:32-n32-S128"); } else if (T.isOSBinFormatMachO()) resetDataLayout( BigEndian - ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" - : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); + ? "E-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" + : "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); else resetDataLayout( BigEndian - ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" - : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); + ? "E-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" + : "e-m:e-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); // FIXME: Override "preferred align" for double and long long. } @@ -397,6 +397,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, SoftFloat = SoftFloatABI = false; HWDiv = 0; DotProd = 0; + HasFloat16 = true; // This does not diagnose illegal cases like having both // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". @@ -475,7 +476,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, Features.push_back("-neonfp"); // Remove front-end specific options which the backend handles differently. - auto Feature = std::find(Features.begin(), Features.end(), "+soft-float-abi"); + auto Feature = llvm::find(Features, "+soft-float-abi"); if (Feature != Features.end()) Features.erase(Feature); @@ -652,6 +653,12 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, if (SoftFloat) Builder.defineMacro("__SOFTFP__"); + // ACLE position independent code macros. + if (Opts.ROPI) + Builder.defineMacro("__ARM_ROPI", "1"); + if (Opts.RWPI) + Builder.defineMacro("__ARM_RWPI", "1"); + if (ArchKind == llvm::ARM::ArchKind::XSCALE) Builder.defineMacro("__XSCALE__"); @@ -1049,7 +1056,7 @@ CygwinARMTargetInfo::CygwinARMTargetInfo(const llvm::Triple &Triple, this->WCharType = TargetInfo::UnsignedShort; TLSSupported = false; DoubleAlign = LongLongAlign = 64; - resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); + resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"); } void CygwinARMTargetInfo::getTargetDefines(const LangOptions &Opts, diff --git a/lib/Basic/Targets/ARM.h b/lib/Basic/Targets/ARM.h index 9c72c3387f..c977c78a75 100644 --- a/lib/Basic/Targets/ARM.h +++ b/lib/Basic/Targets/ARM.h @@ -1,9 +1,8 @@ //===--- ARM.h - Declare ARM target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/AVR.cpp b/lib/Basic/Targets/AVR.cpp index 9b66449cbc..d865676700 100644 --- a/lib/Basic/Targets/AVR.cpp +++ b/lib/Basic/Targets/AVR.cpp @@ -1,9 +1,8 @@ //===--- AVR.cpp - Implement AVR target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/AVR.h b/lib/Basic/Targets/AVR.h index d595f48e8e..94f006ee1b 100644 --- a/lib/Basic/Targets/AVR.h +++ b/lib/Basic/Targets/AVR.h @@ -1,9 +1,8 @@ //===--- AVR.h - Declare AVR target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/BPF.cpp b/lib/Basic/Targets/BPF.cpp index cf41a09d76..0cf55a58a9 100644 --- a/lib/Basic/Targets/BPF.cpp +++ b/lib/Basic/Targets/BPF.cpp @@ -1,9 +1,8 @@ //===--- BPF.cpp - Implement BPF target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -21,12 +20,12 @@ using namespace clang::targets; void BPFTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { - DefineStd(Builder, "bpf", Opts); + Builder.defineMacro("__bpf__"); Builder.defineMacro("__BPF__"); } static constexpr llvm::StringLiteral ValidCPUNames[] = {"generic", "v1", "v2", - "probe"}; + "v3", "probe"}; bool BPFTargetInfo::isValidCPUName(StringRef Name) const { return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames); diff --git a/lib/Basic/Targets/BPF.h b/lib/Basic/Targets/BPF.h index 7f97f81891..79abd8828a 100644 --- a/lib/Basic/Targets/BPF.h +++ b/lib/Basic/Targets/BPF.h @@ -1,9 +1,8 @@ //===--- BPF.h - Declare BPF target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Hexagon.cpp b/lib/Basic/Targets/Hexagon.cpp index 94e1388e38..be23fd2536 100644 --- a/lib/Basic/Targets/Hexagon.cpp +++ b/lib/Basic/Targets/Hexagon.cpp @@ -1,9 +1,8 @@ //===--- Hexagon.cpp - Implement Hexagon target feature support -----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Hexagon.h b/lib/Basic/Targets/Hexagon.h index fb4956a9e5..25a78c1815 100644 --- a/lib/Basic/Targets/Hexagon.h +++ b/lib/Basic/Targets/Hexagon.h @@ -1,9 +1,8 @@ //===--- Hexagon.h - Declare Hexagon target feature support -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Lanai.cpp b/lib/Basic/Targets/Lanai.cpp index 0e8030c04e..bb1872083c 100644 --- a/lib/Basic/Targets/Lanai.cpp +++ b/lib/Basic/Targets/Lanai.cpp @@ -1,9 +1,8 @@ //===--- Lanai.cpp - Implement Lanai target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Lanai.h b/lib/Basic/Targets/Lanai.h index b9e6dbe044..e119606384 100644 --- a/lib/Basic/Targets/Lanai.h +++ b/lib/Basic/Targets/Lanai.h @@ -1,9 +1,8 @@ //===--- Lanai.h - Declare Lanai target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Le64.cpp b/lib/Basic/Targets/Le64.cpp index 5a1c1c88e7..cacd10dc89 100644 --- a/lib/Basic/Targets/Le64.cpp +++ b/lib/Basic/Targets/Le64.cpp @@ -1,9 +1,8 @@ //===--- Le64.cpp - Implement Le64 target feature support -----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Le64.h b/lib/Basic/Targets/Le64.h index 5e18d04986..253d5681ab 100644 --- a/lib/Basic/Targets/Le64.h +++ b/lib/Basic/Targets/Le64.h @@ -1,9 +1,8 @@ //===--- Le64.h - Declare Le64 target feature support -----------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/MSP430.cpp b/lib/Basic/Targets/MSP430.cpp index 86f85a398f..ef53ee352c 100644 --- a/lib/Basic/Targets/MSP430.cpp +++ b/lib/Basic/Targets/MSP430.cpp @@ -1,9 +1,8 @@ //===--- MSP430.cpp - Implement MSP430 target feature support -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/MSP430.h b/lib/Basic/Targets/MSP430.h index 72aafb9459..620f12d2b8 100644 --- a/lib/Basic/Targets/MSP430.h +++ b/lib/Basic/Targets/MSP430.h @@ -1,9 +1,8 @@ //===--- MSP430.h - Declare MSP430 target feature support -------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -34,6 +33,10 @@ public: LongWidth = 32; LongLongWidth = 64; LongAlign = LongLongAlign = 16; + FloatWidth = 32; + FloatAlign = 16; + DoubleWidth = LongDoubleWidth = 64; + DoubleAlign = LongDoubleAlign = 16; PointerWidth = 16; PointerAlign = 16; SuitableAlign = 16; @@ -52,6 +55,8 @@ public: return None; } + bool allowsLargerPreferedTypeAlignment() const override { return false; } + bool hasFeature(StringRef Feature) const override { return Feature == "msp430"; } diff --git a/lib/Basic/Targets/Mips.cpp b/lib/Basic/Targets/Mips.cpp index d43edeae60..2cafbe87a9 100644 --- a/lib/Basic/Targets/Mips.cpp +++ b/lib/Basic/Targets/Mips.cpp @@ -1,9 +1,8 @@ //===--- Mips.cpp - Implement Mips target feature support -----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -216,6 +215,14 @@ ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const { Builtin::FirstTSBuiltin); } +unsigned MipsTargetInfo::getUnwindWordWidth() const { + return llvm::StringSwitch<unsigned>(ABI) + .Case("o32", 32) + .Case("n32", 64) + .Case("n64", 64) + .Default(getPointerWidth(0)); +} + bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const { // microMIPS64R6 backend was removed. if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) { diff --git a/lib/Basic/Targets/Mips.h b/lib/Basic/Targets/Mips.h index d49f49888b..474cda84a4 100644 --- a/lib/Basic/Targets/Mips.h +++ b/lib/Basic/Targets/Mips.h @@ -1,9 +1,8 @@ //===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -402,6 +401,8 @@ public: return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128; } + unsigned getUnwindWordWidth() const override; + bool validateTarget(DiagnosticsEngine &Diags) const override; }; } // namespace targets diff --git a/lib/Basic/Targets/NVPTX.cpp b/lib/Basic/Targets/NVPTX.cpp index ca41c4d14c..c917e3d419 100644 --- a/lib/Basic/Targets/NVPTX.cpp +++ b/lib/Basic/Targets/NVPTX.cpp @@ -1,9 +1,8 @@ //===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -45,6 +44,8 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, if (!Feature.startswith("+ptx")) continue; PTXVersion = llvm::StringSwitch<unsigned>(Feature) + .Case("+ptx64", 64) + .Case("+ptx63", 63) .Case("+ptx61", 61) .Case("+ptx60", 60) .Case("+ptx50", 50) @@ -118,7 +119,7 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, LongAlign = HostTarget->getLongAlign(); LongLongWidth = HostTarget->getLongLongWidth(); LongLongAlign = HostTarget->getLongLongAlign(); - MinGlobalAlign = HostTarget->getMinGlobalAlign(); + MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0); NewAlign = HostTarget->getNewAlign(); DefaultAlignForAttributeAligned = HostTarget->getDefaultAlignForAttributeAligned(); diff --git a/lib/Basic/Targets/NVPTX.h b/lib/Basic/Targets/NVPTX.h index 84d466d2f4..2cdd37ca1b 100644 --- a/lib/Basic/Targets/NVPTX.h +++ b/lib/Basic/Targets/NVPTX.h @@ -1,9 +1,8 @@ //===--- NVPTX.h - Declare NVPTX target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -36,6 +35,16 @@ static const unsigned NVPTXAddrSpaceMap[] = { 3, // cuda_shared }; +/// The DWARF address class. Taken from +/// https://docs.nvidia.com/cuda/archive/10.0/ptx-writers-guide-to-interoperability/index.html#cuda-specific-dwarf +static const int NVPTXDWARFAddrSpaceMap[] = { + -1, // Default, opencl_private or opencl_generic - not defined + 5, // opencl_global + -1, + 8, // opencl_local or cuda_shared + 4, // opencl_constant or cuda_constant +}; + class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; static const Builtin::Info BuiltinInfo[]; @@ -125,6 +134,20 @@ public: Opts.support("cl_khr_local_int32_extended_atomics"); } + /// \returns If a target requires an address within a target specific address + /// space \p AddressSpace to be converted in order to be used, then return the + /// corresponding target specific DWARF address space. + /// + /// \returns Otherwise return None and no conversion will be emitted in the + /// DWARF. + Optional<unsigned> + getDWARFAddressSpace(unsigned AddressSpace) const override { + if (AddressSpace >= llvm::array_lengthof(NVPTXDWARFAddrSpaceMap) || + NVPTXDWARFAddrSpaceMap[AddressSpace] < 0) + return llvm::None; + return NVPTXDWARFAddrSpaceMap[AddressSpace]; + } + CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { // CUDA compilations support all of the host's calling conventions. // diff --git a/lib/Basic/Targets/OSTargets.cpp b/lib/Basic/Targets/OSTargets.cpp index 6252a51ef7..5f4280a989 100644 --- a/lib/Basic/Targets/OSTargets.cpp +++ b/lib/Basic/Targets/OSTargets.cpp @@ -1,9 +1,8 @@ //===--- OSTargets.cpp - Implement OS target feature support --------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/OSTargets.h b/lib/Basic/Targets/OSTargets.h index 085efa02cc..a0e8061dc1 100644 --- a/lib/Basic/Targets/OSTargets.h +++ b/lib/Basic/Targets/OSTargets.h @@ -1,9 +1,8 @@ //===--- OSTargets.h - Declare OS target feature support --------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -614,6 +613,53 @@ public: } }; +// AIX Target +template <typename Target> +class AIXTargetInfo : public OSTargetInfo<Target> { +protected: + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const override { + DefineStd(Builder, "unix", Opts); + Builder.defineMacro("_IBMR2"); + Builder.defineMacro("_POWER"); + + // FIXME: Define AIX OS-Version Macros. + Builder.defineMacro("_AIX"); + + // FIXME: Do not define _LONG_LONG when -fno-long-long is specified. + Builder.defineMacro("_LONG_LONG"); + + if (Opts.POSIXThreads) { + Builder.defineMacro("_THREAD_SAFE"); + } + + if (this->PointerWidth == 64) { + Builder.defineMacro("__64BIT__"); + } + + // Define _WCHAR_T when it is a fundamental type + // (i.e., for C++ without -fno-wchar). + if (Opts.CPlusPlus && Opts.WChar) { + Builder.defineMacro("_WCHAR_T"); + } + } + +public: + AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : OSTargetInfo<Target>(Triple, Opts) { + if (this->PointerWidth == 64) { + this->WCharType = this->UnsignedInt; + } else { + this->WCharType = this->UnsignedShort; + } + this->UseZeroLengthBitfieldAlignment = true; + } + + // AIX sets FLT_EVAL_METHOD to be 1. + unsigned getFloatEvalMethod() const override { return 1; } + bool hasInt128Type() const override { return false; } +}; + // Windows target template <typename Target> class LLVM_LIBRARY_VISIBILITY WindowsTargetInfo : public OSTargetInfo<Target> { @@ -764,14 +810,17 @@ public: template <typename Target> class LLVM_LIBRARY_VISIBILITY WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { +protected: void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, - MacroBuilder &Builder) const final { + MacroBuilder &Builder) const { // A common platform macro. if (Opts.POSIXThreads) Builder.defineMacro("_REENTRANT"); // Follow g++ convention and predefine _GNU_SOURCE for C++. if (Opts.CPlusPlus) Builder.defineMacro("_GNU_SOURCE"); + // Indicate that we have __float128. + Builder.defineMacro("__FLOAT128__"); } public: @@ -780,7 +829,38 @@ public: : OSTargetInfo<Target>(Triple, Opts) { this->MCountName = "__mcount"; this->TheCXXABI.set(TargetCXXABI::WebAssembly); + this->HasFloat128 = true; + } +}; + +// WASI target +template <typename Target> +class LLVM_LIBRARY_VISIBILITY WASITargetInfo + : public WebAssemblyOSTargetInfo<Target> { + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const final { + WebAssemblyOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder); + Builder.defineMacro("__wasi__"); } + +public: + explicit WASITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : WebAssemblyOSTargetInfo<Target>(Triple, Opts) {} +}; + +// Emscripten target +template <typename Target> +class LLVM_LIBRARY_VISIBILITY EmscriptenTargetInfo + : public WebAssemblyOSTargetInfo<Target> { + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const final { + WebAssemblyOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder); + Builder.defineMacro("__EMSCRIPTEN__"); + } + +public: + explicit EmscriptenTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : WebAssemblyOSTargetInfo<Target>(Triple, Opts) {} }; } // namespace targets diff --git a/lib/Basic/Targets/PNaCl.cpp b/lib/Basic/Targets/PNaCl.cpp index b9128c2716..60e9467193 100644 --- a/lib/Basic/Targets/PNaCl.cpp +++ b/lib/Basic/Targets/PNaCl.cpp @@ -1,9 +1,8 @@ //===--- PNaCl.cpp - Implement PNaCl target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/PNaCl.h b/lib/Basic/Targets/PNaCl.h index 922944e85c..ab4abf9fc5 100644 --- a/lib/Basic/Targets/PNaCl.h +++ b/lib/Basic/Targets/PNaCl.h @@ -1,9 +1,8 @@ //===--- PNaCl.h - Declare PNaCl target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/PPC.cpp b/lib/Basic/Targets/PPC.cpp index 6cfbed1713..b052ef433e 100644 --- a/lib/Basic/Targets/PPC.cpp +++ b/lib/Basic/Targets/PPC.cpp @@ -1,9 +1,8 @@ //===--- PPC.cpp - Implement PPC target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -31,6 +30,7 @@ const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { /// configured set of features. bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) { + FloatABI = HardFloat; for (const auto &Feature : Features) { if (Feature == "+altivec") { HasAltivec = true; @@ -54,6 +54,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasFloat128 = true; } else if (Feature == "+power9-vector") { HasP9Vector = true; + } else if (Feature == "-hard-float") { + FloatABI = SoftFloat; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -101,7 +103,9 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("_CALL_LINUX", "1"); // Subtarget options. - Builder.defineMacro("__NATURAL_ALIGNMENT__"); + if (!getTriple().isOSAIX()){ + Builder.defineMacro("__NATURAL_ALIGNMENT__"); + } Builder.defineMacro("__REGISTER_PREFIX__", ""); // FIXME: Should be controlled by command line option. @@ -213,31 +217,26 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, const std::vector<std::string> &FeaturesVec) { - if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != - FeaturesVec.end()) { - if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != - FeaturesVec.end()) { + if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) { + if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) { Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << "-mno-vsx"; return false; } - if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != - FeaturesVec.end()) { + if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) { Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << "-mno-vsx"; return false; } - if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != - FeaturesVec.end()) { + if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << "-mno-vsx"; return false; } - if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != - FeaturesVec.end()) { + if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) { Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" << "-mno-vsx"; return false; @@ -310,8 +309,7 @@ bool PPCTargetInfo::initFeatureMap( return false; if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != - FeaturesVec.end()) { + llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { // We have __float128 on PPC but not power 9 and above. Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU; return false; diff --git a/lib/Basic/Targets/PPC.h b/lib/Basic/Targets/PPC.h index 058970a0e0..3c2191b43e 100644 --- a/lib/Basic/Targets/PPC.h +++ b/lib/Basic/Targets/PPC.h @@ -1,9 +1,8 @@ //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -54,6 +53,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; static const TargetInfo::GCCRegAlias GCCRegAliases[]; std::string CPU; + enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; // Target cpu features. bool HasAltivec = false; @@ -132,19 +132,18 @@ public: ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Cases("power7", "pwr7", - ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | - ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | - ArchDefinePpcgr | ArchDefinePpcsq) + ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) // powerpc64le automatically defaults to at least power8. .Cases("power8", "pwr8", "ppc64le", - ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | - ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | - ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) .Cases("power9", "pwr9", - ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | - ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | - ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | - ArchDefinePpcsq) + ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | + ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Default(ArchDefineNone); } return CPUKnown; @@ -185,8 +184,12 @@ public: return false; case 'O': // Zero break; - case 'b': // Base register case 'f': // Floating point register + // Don't use floating point registers on soft float ABI. + if (FloatABI == SoftFloat) + return false; + LLVM_FALLTHROUGH; + case 'b': // Base register Info.setAllowsRegister(); break; // FIXME: The following are added to allow parsing. @@ -194,6 +197,10 @@ public: // Also, is more specific checking needed? I.e. specific registers? case 'd': // Floating point register (containing 64-bit value) case 'v': // Altivec vector register + // Don't use floating point and altivec vector registers + // on soft float ABI + if (FloatABI == SoftFloat) + return false; Info.setAllowsRegister(); break; case 'w': @@ -327,13 +334,27 @@ public: PtrDiffType = SignedInt; IntPtrType = SignedInt; break; + case llvm::Triple::AIX: + SizeType = UnsignedLong; + PtrDiffType = SignedLong; + IntPtrType = SignedLong; + SuitableAlign = 64; + break; default: break; } - if (getTriple().isOSFreeBSD()) { + switch (getTriple().getOS()) { + case llvm::Triple::FreeBSD: + case llvm::Triple::NetBSD: + case llvm::Triple::OpenBSD: + // FIXME: -mlong-double-128 is not yet supported on AIX. + case llvm::Triple::AIX: LongDoubleWidth = LongDoubleAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); + break; + default: + break; } // PPC32 supports atomics up to 4 bytes. @@ -369,6 +390,12 @@ public: LongDoubleWidth = LongDoubleAlign = 64; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); break; + case llvm::Triple::AIX: + // FIXME: -mlong-double-128 is not yet supported on AIX. + LongDoubleWidth = LongDoubleAlign = 64; + LongDoubleFormat = &llvm::APFloat::IEEEdouble(); + SuitableAlign = 64; + break; default: break; } @@ -427,6 +454,21 @@ public: } }; +class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : + public AIXTargetInfo<PPC32TargetInfo> { +public: + using AIXTargetInfo::AIXTargetInfo; + BuiltinVaListKind getBuiltinVaListKind() const override { + return TargetInfo::CharPtrBuiltinVaList; + } +}; + +class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : + public AIXTargetInfo<PPC64TargetInfo> { +public: + using AIXTargetInfo::AIXTargetInfo; +}; + } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H diff --git a/lib/Basic/Targets/RISCV.cpp b/lib/Basic/Targets/RISCV.cpp index 7eb5e6a686..a9fef5e0e4 100644 --- a/lib/Basic/Targets/RISCV.cpp +++ b/lib/Basic/Targets/RISCV.cpp @@ -1,9 +1,8 @@ //===--- RISCV.cpp - Implement RISCV target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/RISCV.h b/lib/Basic/Targets/RISCV.h index f83aae5393..cc513cf728 100644 --- a/lib/Basic/Targets/RISCV.h +++ b/lib/Basic/Targets/RISCV.h @@ -1,9 +1,8 @@ //===--- RISCV.h - Declare RISCV target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/SPIR.cpp b/lib/Basic/Targets/SPIR.cpp index 304d904368..a9b815d13b 100644 --- a/lib/Basic/Targets/SPIR.cpp +++ b/lib/Basic/Targets/SPIR.cpp @@ -1,9 +1,8 @@ //===--- SPIR.cpp - Implement SPIR target feature support -----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/SPIR.h b/lib/Basic/Targets/SPIR.h index 9815292fc2..6023c868db 100644 --- a/lib/Basic/Targets/SPIR.h +++ b/lib/Basic/Targets/SPIR.h @@ -1,9 +1,8 @@ //===--- SPIR.h - Declare SPIR target feature support -----------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -48,6 +47,7 @@ public: AddrSpaceMap = &SPIRAddrSpaceMap; UseAddrSpaceMapMangling = true; HasLegalHalfType = true; + HasFloat16 = true; // Define available target features // These must be defined in sorted order! NoAsmVariants = true; diff --git a/lib/Basic/Targets/Sparc.cpp b/lib/Basic/Targets/Sparc.cpp index ee4f309363..13aa964d47 100644 --- a/lib/Basic/Targets/Sparc.cpp +++ b/lib/Basic/Targets/Sparc.cpp @@ -1,9 +1,8 @@ //===--- Sparc.cpp - Implement Sparc target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/Sparc.h b/lib/Basic/Targets/Sparc.h index 5ae305bffb..963192a463 100644 --- a/lib/Basic/Targets/Sparc.h +++ b/lib/Basic/Targets/Sparc.h @@ -1,9 +1,8 @@ //===--- Sparc.h - declare sparc target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -40,7 +39,7 @@ public: bool handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) override { // Check if software floating point is enabled - auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); + auto Feature = llvm::find(Features, "+soft-float"); if (Feature != Features.end()) { SoftFloat = true; } diff --git a/lib/Basic/Targets/SystemZ.cpp b/lib/Basic/Targets/SystemZ.cpp index 6f06f1fc76..8131798758 100644 --- a/lib/Basic/Targets/SystemZ.cpp +++ b/lib/Basic/Targets/SystemZ.cpp @@ -1,9 +1,8 @@ //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/SystemZ.h b/lib/Basic/Targets/SystemZ.h index 842316005e..2aa1e3835e 100644 --- a/lib/Basic/Targets/SystemZ.h +++ b/lib/Basic/Targets/SystemZ.h @@ -1,9 +1,8 @@ //===--- SystemZ.h - Declare SystemZ target feature support -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/TCE.cpp b/lib/Basic/Targets/TCE.cpp index bf89c1dc54..91194b568a 100644 --- a/lib/Basic/Targets/TCE.cpp +++ b/lib/Basic/Targets/TCE.cpp @@ -1,9 +1,8 @@ //===--- TCE.cpp - Implement TCE target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/TCE.h b/lib/Basic/Targets/TCE.h index be43bed98d..967ef5c59e 100644 --- a/lib/Basic/Targets/TCE.h +++ b/lib/Basic/Targets/TCE.h @@ -1,9 +1,8 @@ //===--- TCE.h - Declare TCE target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/WebAssembly.cpp b/lib/Basic/Targets/WebAssembly.cpp index 2fdc84bb8c..2fceed2ad1 100644 --- a/lib/Basic/Targets/WebAssembly.cpp +++ b/lib/Basic/Targets/WebAssembly.cpp @@ -1,9 +1,8 @@ //===--- WebAssembly.cpp - Implement WebAssembly target feature support ---===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -41,6 +40,9 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const { .Case("nontrapping-fptoint", HasNontrappingFPToInt) .Case("sign-ext", HasSignExt) .Case("exception-handling", HasExceptionHandling) + .Case("bulk-memory", HasBulkMemory) + .Case("atomics", HasAtomics) + .Case("mutable-globals", HasMutableGlobals) .Default(false); } @@ -60,6 +62,18 @@ void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__wasm_simd128__"); if (SIMDLevel >= UnimplementedSIMD128) Builder.defineMacro("__wasm_unimplemented_simd128__"); + if (HasNontrappingFPToInt) + Builder.defineMacro("__wasm_nontrapping_fptoint__"); + if (HasSignExt) + Builder.defineMacro("__wasm_sign_ext__"); + if (HasExceptionHandling) + Builder.defineMacro("__wasm_exception_handling__"); + if (HasBulkMemory) + Builder.defineMacro("__wasm_bulk_memory__"); + if (HasAtomics) + Builder.defineMacro("__wasm_atomics__"); + if (HasMutableGlobals) + Builder.defineMacro("__wasm_mutable_globals__"); } void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features, @@ -82,6 +96,8 @@ bool WebAssemblyTargetInfo::initFeatureMap( if (CPU == "bleeding-edge") { Features["nontrapping-fptoint"] = true; Features["sign-ext"] = true; + Features["atomics"] = true; + Features["mutable-globals"] = true; setSIMDLevel(Features, SIMD128); } // Other targets do not consider user-configured features here, but while we @@ -94,6 +110,12 @@ bool WebAssemblyTargetInfo::initFeatureMap( Features["sign-ext"] = true; if (HasExceptionHandling) Features["exception-handling"] = true; + if (HasBulkMemory) + Features["bulk-memory"] = true; + if (HasAtomics) + Features["atomics"] = true; + if (HasMutableGlobals) + Features["mutable-globals"] = true; return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } @@ -141,6 +163,30 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasExceptionHandling = false; continue; } + if (Feature == "+bulk-memory") { + HasBulkMemory = true; + continue; + } + if (Feature == "-bulk-memory") { + HasBulkMemory = false; + continue; + } + if (Feature == "+atomics") { + HasAtomics = true; + continue; + } + if (Feature == "-atomics") { + HasAtomics = false; + continue; + } + if (Feature == "+mutable-globals") { + HasMutableGlobals = true; + continue; + } + if (Feature == "-mutable-globals") { + HasMutableGlobals = false; + continue; + } Diags.Report(diag::err_opt_not_valid_with_opt) << Feature << "-target-feature"; diff --git a/lib/Basic/Targets/WebAssembly.h b/lib/Basic/Targets/WebAssembly.h index 3dea9a373c..a0516da286 100644 --- a/lib/Basic/Targets/WebAssembly.h +++ b/lib/Basic/Targets/WebAssembly.h @@ -1,9 +1,8 @@ //=== WebAssembly.h - Declare WebAssembly target feature support *- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -31,14 +30,16 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo { UnimplementedSIMD128, } SIMDLevel = NoSIMD; - bool HasNontrappingFPToInt; - bool HasSignExt; - bool HasExceptionHandling; + bool HasNontrappingFPToInt = false; + bool HasSignExt = false; + bool HasExceptionHandling = false; + bool HasBulkMemory = false; + bool HasAtomics = false; + bool HasMutableGlobals = false; public: explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) - : TargetInfo(T), SIMDLevel(NoSIMD), HasNontrappingFPToInt(false), - HasSignExt(false), HasExceptionHandling(false) { + : TargetInfo(T) { NoAsmVariants = true; SuitableAlign = 128; LargeArrayMinWidth = 128; diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp index 53b4c153e9..b83c9382fc 100644 --- a/lib/Basic/Targets/X86.cpp +++ b/lib/Basic/Targets/X86.cpp @@ -1,9 +1,8 @@ //===--- X86.cpp - Implement X86 target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -116,6 +115,11 @@ bool X86TargetInfo::initFeatureMap( if (Kind != CK_Lakemont) setFeatureEnabledImpl(Features, "x87", true); + // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards + // compatibility. + if (Kind >= CK_i586 || Kind == CK_Generic) + setFeatureEnabledImpl(Features, "cx8", true); + switch (Kind) { case CK_Generic: case CK_i386: @@ -123,6 +127,7 @@ bool X86TargetInfo::initFeatureMap( case CK_i586: case CK_Pentium: case CK_PentiumPro: + case CK_i686: case CK_Lakemont: break; @@ -215,11 +220,12 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; + case CK_Nocona: + setFeatureEnabledImpl(Features, "cx16", true); + LLVM_FALLTHROUGH; case CK_Yonah: case CK_Prescott: - case CK_Nocona: setFeatureEnabledImpl(Features, "sse3", true); - setFeatureEnabledImpl(Features, "cx16", true); LLVM_FALLTHROUGH; case CK_PentiumM: case CK_Pentium4: @@ -348,6 +354,11 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sahf", true); break; + case CK_ZNVER2: + setFeatureEnabledImpl(Features, "clwb", true); + setFeatureEnabledImpl(Features, "rdpid", true); + setFeatureEnabledImpl(Features, "wbnoinvd", true); + LLVM_FALLTHROUGH; case CK_ZNVER1: setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "aes", true); @@ -416,23 +427,20 @@ bool X86TargetInfo::initFeatureMap( // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. auto I = Features.find("sse4.2"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) Features["popcnt"] = true; // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. I = Features.find("3dnow"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) Features["prfchw"] = true; // Additionally, if SSE is enabled and mmx is not explicitly disabled, // then enable MMX. I = Features.find("sse"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) Features["mmx"] = true; return true; @@ -513,6 +521,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, Features["avx512ifma"] = Features["avx512vpopcntdq"] = Features["avx512bitalg"] = Features["avx512vnni"] = Features["avx512vbmi2"] = false; + Features["avx512bf16"] = false; break; } } @@ -644,16 +653,22 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || Name == "avx512vbmi" || Name == "avx512ifma" || Name == "avx512vpopcntdq" || Name == "avx512bitalg" || + Name == "avx512bf16" || Name == "avx512vnni" || Name == "avx512vbmi2") { if (Enabled) setSSELevel(Features, AVX512F, Enabled); // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) Features["avx512bw"] = true; + if (Name == "avx512bf16" && Enabled) + Features["avx512bw"] = Features["avx512vl"] = true; // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. if (Name == "avx512bw" && !Enabled) Features["avx512vbmi"] = Features["avx512vbmi2"] = + Features["avx512bf16"] = Features["avx512bitalg"] = false; + if (Name == "avx512vl" && !Enabled) + Features["avx512bf16"] = false; } else if (Name == "fma") { if (Enabled) setSSELevel(Features, AVX, Enabled); @@ -743,6 +758,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAVX512VPOPCNTDQ = true; } else if (Feature == "+avx512vnni") { HasAVX512VNNI = true; + } else if (Feature == "+avx512bf16") { + HasAVX512BF16 = true; } else if (Feature == "+avx512er") { HasAVX512ER = true; } else if (Feature == "+avx512pf") { @@ -771,6 +788,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasMOVBE = true; } else if (Feature == "+sgx") { HasSGX = true; + } else if (Feature == "+cx8") { + HasCX8 = true; } else if (Feature == "+cx16") { HasCX16 = true; } else if (Feature == "+fxsr") { @@ -865,6 +884,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, /// definitions for this particular subtarget. void X86TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { + // Inline assembly supports X86 flag outputs. + Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); + std::string CodeModel = getTargetOpts().CodeModel; if (CodeModel == "default") CodeModel = "small"; @@ -918,6 +940,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__tune_pentium2__"); LLVM_FALLTHROUGH; case CK_PentiumPro: + case CK_i686: defineCPUMacros(Builder, "i686"); defineCPUMacros(Builder, "pentiumpro"); break; @@ -1028,6 +1051,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_ZNVER1: defineCPUMacros(Builder, "znver1"); break; + case CK_ZNVER2: + defineCPUMacros(Builder, "znver2"); + break; case CK_Geode: defineCPUMacros(Builder, "geode"); break; @@ -1124,6 +1150,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AVX512VPOPCNTDQ__"); if (HasAVX512VNNI) Builder.defineMacro("__AVX512VNNI__"); + if (HasAVX512BF16) + Builder.defineMacro("__AVX512BF16__"); if (HasAVX512ER) Builder.defineMacro("__AVX512ER__"); if (HasAVX512PF) @@ -1262,14 +1290,14 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, break; } - if (CPU >= CK_i486) { + if (CPU >= CK_i486 || CPU == CK_Generic) { Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); } - if (CPU >= CK_i586) + if (HasCX8) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - if (HasCX16) + if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); if (HasFloat128) @@ -1288,6 +1316,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("avx512cd", true) .Case("avx512vpopcntdq", true) .Case("avx512vnni", true) + .Case("avx512bf16", true) .Case("avx512er", true) .Case("avx512pf", true) .Case("avx512dq", true) @@ -1366,6 +1395,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("avx512cd", HasAVX512CD) .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512vnni", HasAVX512VNNI) + .Case("avx512bf16", HasAVX512BF16) .Case("avx512er", HasAVX512ER) .Case("avx512pf", HasAVX512PF) .Case("avx512dq", HasAVX512DQ) @@ -1381,6 +1411,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("clflushopt", HasCLFLUSHOPT) .Case("clwb", HasCLWB) .Case("clzero", HasCLZERO) + .Case("cx8", HasCX8) .Case("cx16", HasCX16) .Case("f16c", HasF16C) .Case("fma", HasFMA) @@ -1527,18 +1558,6 @@ void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); } -std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { - switch (Kind) { - case CK_Generic: - return ""; -#define PROC(ENUM, STRING, IS64BIT) \ - case CK_##ENUM: \ - return STRING; -#include "clang/Basic/X86Target.def" - } - llvm_unreachable("Invalid CPUKind"); -} - // We can't use a generic validation scheme for the cpus accepted here // versus subtarget cpus accepted in the target attribute because the // variables intitialized by the runtime only support the below currently @@ -1554,6 +1573,40 @@ bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { .Default(false); } +static unsigned matchAsmCCConstraint(const char *&Name) { + auto RV = llvm::StringSwitch<unsigned>(Name) + .Case("@cca", 4) + .Case("@ccae", 5) + .Case("@ccb", 4) + .Case("@ccbe", 5) + .Case("@ccc", 4) + .Case("@cce", 4) + .Case("@ccz", 4) + .Case("@ccg", 4) + .Case("@ccge", 5) + .Case("@ccl", 4) + .Case("@ccle", 5) + .Case("@ccna", 5) + .Case("@ccnae", 6) + .Case("@ccnb", 5) + .Case("@ccnbe", 6) + .Case("@ccnc", 5) + .Case("@ccne", 5) + .Case("@ccnz", 5) + .Case("@ccng", 5) + .Case("@ccnge", 6) + .Case("@ccnl", 5) + .Case("@ccnle", 6) + .Case("@ccno", 5) + .Case("@ccnp", 5) + .Case("@ccns", 5) + .Case("@cco", 4) + .Case("@ccp", 4) + .Case("@ccs", 4) + .Default(0); + return RV; +} + bool X86TargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { @@ -1636,6 +1689,14 @@ bool X86TargetInfo::validateAsmConstraint( case 'C': // SSE floating point constant. case 'G': // x87 floating point constant. return true; + case '@': + // CC condition changes. + if (auto Len = matchAsmCCConstraint(Name)) { + Name += Len - 1; + Info.setAllowsRegister(); + return true; + } + return false; } } @@ -1707,6 +1768,13 @@ bool X86TargetInfo::validateOperandSize(StringRef Constraint, std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { switch (*Constraint) { + case '@': + if (auto Len = matchAsmCCConstraint(Constraint)) { + std::string Converted = "{" + std::string(Constraint, Len) + "}"; + Constraint += Len - 1; + return Converted; + } + return std::string(1, *Constraint); case 'a': return std::string("{ax}"); case 'b': @@ -1769,10 +1837,9 @@ void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { #define PROC(ENUM, STRING, IS64BIT) \ if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ Values.emplace_back(STRING); - // Go through CPUKind checking to ensure that the alias is de-aliased and - // 64 bit-ness is checked. + // For aliases we need to lookup the CPUKind to check get the 64-bit ness. #define PROC_ALIAS(ENUM, ALIAS) \ - if (checkCPUKind(getCPUKind(ALIAS))) \ + if (checkCPUKind(CK_##ENUM)) \ Values.emplace_back(ALIAS); #include "clang/Basic/X86Target.def" } diff --git a/lib/Basic/Targets/X86.h b/lib/Basic/Targets/X86.h index 05930ae9ee..d7a87f8d7c 100644 --- a/lib/Basic/Targets/X86.h +++ b/lib/Basic/Targets/X86.h @@ -1,9 +1,8 @@ //===--- X86.h - Declare X86 target feature support -------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -69,6 +68,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasAVX512CD = false; bool HasAVX512VPOPCNTDQ = false; bool HasAVX512VNNI = false; + bool HasAVX512BF16 = false; bool HasAVX512ER = false; bool HasAVX512PF = false; bool HasAVX512DQ = false; @@ -82,6 +82,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasMPX = false; bool HasSHSTK = false; bool HasSGX = false; + bool HasCX8 = false; bool HasCX16 = false; bool HasFXSR = false; bool HasXSAVE = false; @@ -122,8 +123,6 @@ protected: CPUKind getCPUKind(StringRef CPU) const; - std::string getCPUKindCanonicalName(CPUKind Kind) const; - enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default; public: @@ -199,7 +198,7 @@ public: StringRef Expression) const override { StringRef::iterator I, E; for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { - if (isalpha(*I)) + if (isalpha(*I) || *I == '@') break; } if (I == E) @@ -347,9 +346,8 @@ public: (1 << TargetInfo::LongDouble)); // x86-32 has atomics up to 8 bytes - // FIXME: Check that we actually have cmpxchg8b before setting - // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) - MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; + MaxAtomicPromoteWidth = 64; + MaxAtomicInlineWidth = 32; } BuiltinVaListKind getBuiltinVaListKind() const override { @@ -385,6 +383,11 @@ public: return X86TargetInfo::validateOperandSize(Constraint, Size); } + void setMaxAtomicWidth() override { + if (hasFeature("cx8")) + MaxAtomicInlineWidth = 64; + } + ArrayRef<Builtin::Info> getTargetBuiltins() const override; }; diff --git a/lib/Basic/Targets/XCore.cpp b/lib/Basic/Targets/XCore.cpp index 793dca702d..da614f10e3 100644 --- a/lib/Basic/Targets/XCore.cpp +++ b/lib/Basic/Targets/XCore.cpp @@ -1,9 +1,8 @@ //===--- XCore.cpp - Implement XCore target feature support ---------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // diff --git a/lib/Basic/Targets/XCore.h b/lib/Basic/Targets/XCore.h index 346e0eee15..c94f93a99b 100644 --- a/lib/Basic/Targets/XCore.h +++ b/lib/Basic/Targets/XCore.h @@ -1,9 +1,8 @@ //===--- XCore.h - Declare XCore target feature support ---------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // |