diff options
Diffstat (limited to 'lib/Basic/Targets/X86.cpp')
-rw-r--r-- | lib/Basic/Targets/X86.cpp | 127 |
1 files changed, 97 insertions, 30 deletions
diff --git a/lib/Basic/Targets/X86.cpp b/lib/Basic/Targets/X86.cpp index 53b4c153e9..b83c9382fc 100644 --- a/lib/Basic/Targets/X86.cpp +++ b/lib/Basic/Targets/X86.cpp @@ -1,9 +1,8 @@ //===--- X86.cpp - Implement X86 target feature support -------------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -116,6 +115,11 @@ bool X86TargetInfo::initFeatureMap( if (Kind != CK_Lakemont) setFeatureEnabledImpl(Features, "x87", true); + // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards + // compatibility. + if (Kind >= CK_i586 || Kind == CK_Generic) + setFeatureEnabledImpl(Features, "cx8", true); + switch (Kind) { case CK_Generic: case CK_i386: @@ -123,6 +127,7 @@ bool X86TargetInfo::initFeatureMap( case CK_i586: case CK_Pentium: case CK_PentiumPro: + case CK_i686: case CK_Lakemont: break; @@ -215,11 +220,12 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "sahf", true); LLVM_FALLTHROUGH; + case CK_Nocona: + setFeatureEnabledImpl(Features, "cx16", true); + LLVM_FALLTHROUGH; case CK_Yonah: case CK_Prescott: - case CK_Nocona: setFeatureEnabledImpl(Features, "sse3", true); - setFeatureEnabledImpl(Features, "cx16", true); LLVM_FALLTHROUGH; case CK_PentiumM: case CK_Pentium4: @@ -348,6 +354,11 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sahf", true); break; + case CK_ZNVER2: + setFeatureEnabledImpl(Features, "clwb", true); + setFeatureEnabledImpl(Features, "rdpid", true); + setFeatureEnabledImpl(Features, "wbnoinvd", true); + LLVM_FALLTHROUGH; case CK_ZNVER1: setFeatureEnabledImpl(Features, "adx", true); setFeatureEnabledImpl(Features, "aes", true); @@ -416,23 +427,20 @@ bool X86TargetInfo::initFeatureMap( // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. auto I = Features.find("sse4.2"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end()) Features["popcnt"] = true; // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. I = Features.find("3dnow"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end()) Features["prfchw"] = true; // Additionally, if SSE is enabled and mmx is not explicitly disabled, // then enable MMX. I = Features.find("sse"); if (I != Features.end() && I->getValue() && - std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == - FeaturesVec.end()) + llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end()) Features["mmx"] = true; return true; @@ -513,6 +521,7 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, Features["avx512ifma"] = Features["avx512vpopcntdq"] = Features["avx512bitalg"] = Features["avx512vnni"] = Features["avx512vbmi2"] = false; + Features["avx512bf16"] = false; break; } } @@ -644,16 +653,22 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || Name == "avx512vbmi" || Name == "avx512ifma" || Name == "avx512vpopcntdq" || Name == "avx512bitalg" || + Name == "avx512bf16" || Name == "avx512vnni" || Name == "avx512vbmi2") { if (Enabled) setSSELevel(Features, AVX512F, Enabled); // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled. if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled) Features["avx512bw"] = true; + if (Name == "avx512bf16" && Enabled) + Features["avx512bw"] = Features["avx512vl"] = true; // Also disable VBMI/VBMI2/BITALG if BWI is being disabled. if (Name == "avx512bw" && !Enabled) Features["avx512vbmi"] = Features["avx512vbmi2"] = + Features["avx512bf16"] = Features["avx512bitalg"] = false; + if (Name == "avx512vl" && !Enabled) + Features["avx512bf16"] = false; } else if (Name == "fma") { if (Enabled) setSSELevel(Features, AVX, Enabled); @@ -743,6 +758,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAVX512VPOPCNTDQ = true; } else if (Feature == "+avx512vnni") { HasAVX512VNNI = true; + } else if (Feature == "+avx512bf16") { + HasAVX512BF16 = true; } else if (Feature == "+avx512er") { HasAVX512ER = true; } else if (Feature == "+avx512pf") { @@ -771,6 +788,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasMOVBE = true; } else if (Feature == "+sgx") { HasSGX = true; + } else if (Feature == "+cx8") { + HasCX8 = true; } else if (Feature == "+cx16") { HasCX16 = true; } else if (Feature == "+fxsr") { @@ -865,6 +884,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, /// definitions for this particular subtarget. void X86TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { + // Inline assembly supports X86 flag outputs. + Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__"); + std::string CodeModel = getTargetOpts().CodeModel; if (CodeModel == "default") CodeModel = "small"; @@ -918,6 +940,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__tune_pentium2__"); LLVM_FALLTHROUGH; case CK_PentiumPro: + case CK_i686: defineCPUMacros(Builder, "i686"); defineCPUMacros(Builder, "pentiumpro"); break; @@ -1028,6 +1051,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_ZNVER1: defineCPUMacros(Builder, "znver1"); break; + case CK_ZNVER2: + defineCPUMacros(Builder, "znver2"); + break; case CK_Geode: defineCPUMacros(Builder, "geode"); break; @@ -1124,6 +1150,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AVX512VPOPCNTDQ__"); if (HasAVX512VNNI) Builder.defineMacro("__AVX512VNNI__"); + if (HasAVX512BF16) + Builder.defineMacro("__AVX512BF16__"); if (HasAVX512ER) Builder.defineMacro("__AVX512ER__"); if (HasAVX512PF) @@ -1262,14 +1290,14 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, break; } - if (CPU >= CK_i486) { + if (CPU >= CK_i486 || CPU == CK_Generic) { Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); } - if (CPU >= CK_i586) + if (HasCX8) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - if (HasCX16) + if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); if (HasFloat128) @@ -1288,6 +1316,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("avx512cd", true) .Case("avx512vpopcntdq", true) .Case("avx512vnni", true) + .Case("avx512bf16", true) .Case("avx512er", true) .Case("avx512pf", true) .Case("avx512dq", true) @@ -1366,6 +1395,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("avx512cd", HasAVX512CD) .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512vnni", HasAVX512VNNI) + .Case("avx512bf16", HasAVX512BF16) .Case("avx512er", HasAVX512ER) .Case("avx512pf", HasAVX512PF) .Case("avx512dq", HasAVX512DQ) @@ -1381,6 +1411,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("clflushopt", HasCLFLUSHOPT) .Case("clwb", HasCLWB) .Case("clzero", HasCLZERO) + .Case("cx8", HasCX8) .Case("cx16", HasCX16) .Case("f16c", HasF16C) .Case("fma", HasFMA) @@ -1527,18 +1558,6 @@ void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); } -std::string X86TargetInfo::getCPUKindCanonicalName(CPUKind Kind) const { - switch (Kind) { - case CK_Generic: - return ""; -#define PROC(ENUM, STRING, IS64BIT) \ - case CK_##ENUM: \ - return STRING; -#include "clang/Basic/X86Target.def" - } - llvm_unreachable("Invalid CPUKind"); -} - // We can't use a generic validation scheme for the cpus accepted here // versus subtarget cpus accepted in the target attribute because the // variables intitialized by the runtime only support the below currently @@ -1554,6 +1573,40 @@ bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const { .Default(false); } +static unsigned matchAsmCCConstraint(const char *&Name) { + auto RV = llvm::StringSwitch<unsigned>(Name) + .Case("@cca", 4) + .Case("@ccae", 5) + .Case("@ccb", 4) + .Case("@ccbe", 5) + .Case("@ccc", 4) + .Case("@cce", 4) + .Case("@ccz", 4) + .Case("@ccg", 4) + .Case("@ccge", 5) + .Case("@ccl", 4) + .Case("@ccle", 5) + .Case("@ccna", 5) + .Case("@ccnae", 6) + .Case("@ccnb", 5) + .Case("@ccnbe", 6) + .Case("@ccnc", 5) + .Case("@ccne", 5) + .Case("@ccnz", 5) + .Case("@ccng", 5) + .Case("@ccnge", 6) + .Case("@ccnl", 5) + .Case("@ccnle", 6) + .Case("@ccno", 5) + .Case("@ccnp", 5) + .Case("@ccns", 5) + .Case("@cco", 4) + .Case("@ccp", 4) + .Case("@ccs", 4) + .Default(0); + return RV; +} + bool X86TargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { switch (*Name) { @@ -1636,6 +1689,14 @@ bool X86TargetInfo::validateAsmConstraint( case 'C': // SSE floating point constant. case 'G': // x87 floating point constant. return true; + case '@': + // CC condition changes. + if (auto Len = matchAsmCCConstraint(Name)) { + Name += Len - 1; + Info.setAllowsRegister(); + return true; + } + return false; } } @@ -1707,6 +1768,13 @@ bool X86TargetInfo::validateOperandSize(StringRef Constraint, std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { switch (*Constraint) { + case '@': + if (auto Len = matchAsmCCConstraint(Constraint)) { + std::string Converted = "{" + std::string(Constraint, Len) + "}"; + Constraint += Len - 1; + return Converted; + } + return std::string(1, *Constraint); case 'a': return std::string("{ax}"); case 'b': @@ -1769,10 +1837,9 @@ void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { #define PROC(ENUM, STRING, IS64BIT) \ if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \ Values.emplace_back(STRING); - // Go through CPUKind checking to ensure that the alias is de-aliased and - // 64 bit-ness is checked. + // For aliases we need to lookup the CPUKind to check get the 64-bit ness. #define PROC_ALIAS(ENUM, ALIAS) \ - if (checkCPUKind(getCPUKind(ALIAS))) \ + if (checkCPUKind(CK_##ENUM)) \ Values.emplace_back(ALIAS); #include "clang/Basic/X86Target.def" } |