diff options
author | Martyn Capewell <martyn.capewell@arm.com> | 2018-02-15 11:31:30 +0000 |
---|---|---|
committer | Pierre Langlois <pierre.langlois@arm.com> | 2018-02-15 11:31:44 +0000 |
commit | a41e43456668ac1e9627246cbdca9f16f42afff2 (patch) | |
tree | 39673ce46fada80904ade4e48410da4d393a4eea | |
parent | 41aa0c12fe855700ebf339126df9dec7fe1a0644 (diff) |
Add support for CSDB in AArch64
Add support for CSDB, equivalent to hint #20, in the system instruction space.
Additionally, relax the "unallocated" identification of hint instructions that
we don't support, such that they'll now disassemble as "unimplemented (System)"
rather than "unallocated".
Change-Id: I87f8d2688f1203ca77cb717de19702cc53328e0f
-rw-r--r-- | src/aarch64/assembler-aarch64.cc | 1 | ||||
-rw-r--r-- | src/aarch64/assembler-aarch64.h | 3 | ||||
-rw-r--r-- | src/aarch64/constants-aarch64.h | 3 | ||||
-rw-r--r-- | src/aarch64/decoder-aarch64.cc | 5 | ||||
-rw-r--r-- | src/aarch64/disasm-aarch64.cc | 5 | ||||
-rw-r--r-- | src/aarch64/macro-assembler-aarch64.h | 5 | ||||
-rw-r--r-- | src/aarch64/simulator-aarch64.cc | 1 | ||||
-rw-r--r-- | test/aarch64/test-assembler-aarch64.cc | 3 | ||||
-rw-r--r-- | test/aarch64/test-disasm-aarch64.cc | 3 |
9 files changed, 22 insertions, 7 deletions
diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc index db30811a..2606dbea 100644 --- a/src/aarch64/assembler-aarch64.cc +++ b/src/aarch64/assembler-aarch64.cc @@ -2075,6 +2075,7 @@ void Assembler::isb() { Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll)); } +void Assembler::csdb() { hint(CSDB); } void Assembler::fmov(const VRegister& vd, double imm) { if (vd.IsScalar()) { diff --git a/src/aarch64/assembler-aarch64.h b/src/aarch64/assembler-aarch64.h index 0931f46f..8d0fcd0c 100644 --- a/src/aarch64/assembler-aarch64.h +++ b/src/aarch64/assembler-aarch64.h @@ -1264,6 +1264,9 @@ class Assembler : public vixl::internal::AssemblerBase { // Instruction synchronization barrier. void isb(); + // Conditional speculation dependency barrier. + void csdb(); + // Alias for system instructions. // No-op. void nop() { hint(NOP); } diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h index 984c765d..b9b9064e 100644 --- a/src/aarch64/constants-aarch64.h +++ b/src/aarch64/constants-aarch64.h @@ -299,7 +299,8 @@ enum SystemHint { WFE = 2, WFI = 3, SEV = 4, - SEVL = 5 + SEVL = 5, + CSDB = 20 }; enum BarrierDomain { diff --git a/src/aarch64/decoder-aarch64.cc b/src/aarch64/decoder-aarch64.cc index cc4e1a74..ef3c9247 100644 --- a/src/aarch64/decoder-aarch64.cc +++ b/src/aarch64/decoder-aarch64.cc @@ -246,11 +246,6 @@ void Decoder::DecodeBranchSystemException(const Instruction* instr) { (instr->Mask(0x0039E000) == 0x00002000) || (instr->Mask(0x003AE000) == 0x00002000) || (instr->Mask(0x003CE000) == 0x00042000) || - (instr->Mask(0x003FFFC0) == 0x000320C0) || - (instr->Mask(0x003FF100) == 0x00032100) || - (instr->Mask(0x003FF200) == 0x00032200) || - (instr->Mask(0x003FF400) == 0x00032400) || - (instr->Mask(0x003FF800) == 0x00032800) || (instr->Mask(0x0038F000) == 0x00005000) || (instr->Mask(0x0038E000) == 0x00006000)) { VisitUnallocated(instr); diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc index c6d7a8e6..f4dcc621 100644 --- a/src/aarch64/disasm-aarch64.cc +++ b/src/aarch64/disasm-aarch64.cc @@ -1752,8 +1752,13 @@ void Disassembler::VisitSystem(const Instruction *instr) { } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) { switch (instr->GetImmHint()) { case NOP: { + form = NULL; mnemonic = "nop"; + break; + } + case CSDB: { form = NULL; + mnemonic = "csdb"; break; } } diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h index 84aef1ea..77444182 100644 --- a/src/aarch64/macro-assembler-aarch64.h +++ b/src/aarch64/macro-assembler-aarch64.h @@ -1109,6 +1109,11 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { SingleEmissionCheckScope guard(this); cneg(rd, rn, cond); } + void Csdb() { + VIXL_ASSERT(allow_macro_instructions_); + SingleEmissionCheckScope guard(this); + csdb(); + } void Cset(const Register& rd, Condition cond) { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(!rd.IsZero()); diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index 8214f583..66ae820d 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -2918,6 +2918,7 @@ void Simulator::VisitSystem(const Instruction* instr) { VIXL_ASSERT(instr->Mask(SystemHintMask) == HINT); switch (instr->GetImmHint()) { case NOP: + case CSDB: break; default: VIXL_UNIMPLEMENTED(); diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc index f365dd25..9da96488 100644 --- a/test/aarch64/test-assembler-aarch64.cc +++ b/test/aarch64/test-assembler-aarch64.cc @@ -13366,13 +13366,14 @@ TEST(system_msr) { } -TEST(system_nop) { +TEST(system) { SETUP(); RegisterDump before; START(); before.Dump(&masm); __ Nop(); + __ Csdb(); END(); RUN(); diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc index f78abb95..df8de85c 100644 --- a/test/aarch64/test-disasm-aarch64.cc +++ b/test/aarch64/test-disasm-aarch64.cc @@ -3068,6 +3068,9 @@ TEST(barriers) { // ISB COMPARE_MACRO(Isb(), "isb"); + // CSDB + COMPARE_MACRO(Csdb(), "csdb"); + CLEANUP(); } |