Implement CPU Feature selection.

The new CPUFeatures class provides feature selection based on the ID registers
in the latest (Armv8.3) Architecture Reference Manual.

This patch adds the CPUFeatures class and associated tests, but does not change
existing VIXL behaviour. Follow-up patches will add checks and assertions to the
various VIXL components.

Change-Id: I51f81b43676f7a94f406be697ca9721fd3a90fa0

3 files changed, 883 insertions, 0 deletions

diff --git a/src/cpu-features.cc b/src/cpu-features.cc
new file mode 100644
index 00000000..7843eeb4
--- /dev/null
+++ b/src/cpu-features.cc
@@ -0,0 +1,206 @@
+// Copyright 2018, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <ostream>
+
+#include "cpu-features.h"
+#include "globals-vixl.h"
+#include "utils-vixl.h"
+
+namespace vixl {
+
+static uint64_t MakeFeatureMask(CPUFeatures::Feature feature) {
+  if (feature == CPUFeatures::kNone) {
+    return 0;
+  } else {
+    // Check that the shift is well-defined, and that the feature is valid.
+    VIXL_STATIC_ASSERT(CPUFeatures::kNumberOfFeatures <=
+                       (sizeof(uint64_t) * 8));
+    VIXL_ASSERT(feature < CPUFeatures::kNumberOfFeatures);
+    return UINT64_C(1) << feature;
+  }
+}
+
+CPUFeatures::CPUFeatures(Feature feature0,
+                         Feature feature1,
+                         Feature feature2,
+                         Feature feature3)
+    : features_(0) {
+  Combine(feature0, feature1, feature2, feature3);
+}
+
+CPUFeatures CPUFeatures::All() {
+  CPUFeatures all;
+  // Check that the shift is well-defined.
+  VIXL_STATIC_ASSERT(CPUFeatures::kNumberOfFeatures < (sizeof(uint64_t) * 8));
+  all.features_ = (UINT64_C(1) << kNumberOfFeatures) - 1;
+  return all;
+}
+
+CPUFeatures CPUFeatures::InferFromOS() {
+  // TODO: Actually infer features from the OS.
+  return CPUFeatures();
+}
+
+void CPUFeatures::Combine(const CPUFeatures& other) {
+  features_ |= other.features_;
+}
+
+void CPUFeatures::Combine(Feature feature0,
+                          Feature feature1,
+                          Feature feature2,
+                          Feature feature3) {
+  features_ |= MakeFeatureMask(feature0);
+  features_ |= MakeFeatureMask(feature1);
+  features_ |= MakeFeatureMask(feature2);
+  features_ |= MakeFeatureMask(feature3);
+}
+
+void CPUFeatures::Remove(const CPUFeatures& other) {
+  features_ &= ~other.features_;
+}
+
+void CPUFeatures::Remove(Feature feature0,
+                         Feature feature1,
+                         Feature feature2,
+                         Feature feature3) {
+  features_ &= ~MakeFeatureMask(feature0);
+  features_ &= ~MakeFeatureMask(feature1);
+  features_ &= ~MakeFeatureMask(feature2);
+  features_ &= ~MakeFeatureMask(feature3);
+}
+
+CPUFeatures CPUFeatures::With(const CPUFeatures& other) const {
+  CPUFeatures f(*this);
+  f.Combine(other);
+  return f;
+}
+
+CPUFeatures CPUFeatures::With(Feature feature0,
+                              Feature feature1,
+                              Feature feature2,
+                              Feature feature3) const {
+  CPUFeatures f(*this);
+  f.Combine(feature0, feature1, feature2, feature3);
+  return f;
+}
+
+CPUFeatures CPUFeatures::Without(const CPUFeatures& other) const {
+  CPUFeatures f(*this);
+  f.Remove(other);
+  return f;
+}
+
+CPUFeatures CPUFeatures::Without(Feature feature0,
+                                 Feature feature1,
+                                 Feature feature2,
+                                 Feature feature3) const {
+  CPUFeatures f(*this);
+  f.Remove(feature0, feature1, feature2, feature3);
+  return f;
+}
+
+bool CPUFeatures::Has(const CPUFeatures& other) const {
+  return (features_ & other.features_) == other.features_;
+}
+
+bool CPUFeatures::Has(Feature feature0,
+                      Feature feature1,
+                      Feature feature2,
+                      Feature feature3) const {
+  uint64_t mask = MakeFeatureMask(feature0) | MakeFeatureMask(feature1) |
+                  MakeFeatureMask(feature2) | MakeFeatureMask(feature3);
+  return (features_ & mask) == mask;
+}
+
+std::ostream& operator<<(std::ostream& os, CPUFeatures::Feature feature) {
+  // clang-format off
+  switch (feature) {
+#define VIXL_FORMAT_FEATURE(SYMBOL, NAME, CPUINFO) \
+    case CPUFeatures::SYMBOL:                      \
+      return os << NAME;
+VIXL_CPU_FEATURE_LIST(VIXL_FORMAT_FEATURE)
+#undef VIXL_FORMAT_FEATURE
+    case CPUFeatures::kNone:
+      return os << "none";
+  }
+  // clang-format on
+  VIXL_UNREACHABLE();
+  return os;
+}
+
+CPUFeatures::const_iterator CPUFeatures::begin() const {
+  if (features_ == 0) return const_iterator(this, kNone);
+
+  int feature_number = CountTrailingZeros(features_);
+  vixl::CPUFeatures::Feature feature =
+      static_cast<CPUFeatures::Feature>(feature_number);
+  return const_iterator(this, feature);
+}
+
+CPUFeatures::const_iterator CPUFeatures::end() const {
+  return const_iterator(this, kNone);
+}
+
+std::ostream& operator<<(std::ostream& os, const CPUFeatures& features) {
+  CPUFeatures::const_iterator it = features.begin();
+  while (it != features.end()) {
+    os << *it;
+    ++it;
+    if (it != features.end()) os << ", ";
+  }
+  return os;
+}
+
+bool CPUFeaturesConstIterator::operator==(
+    const CPUFeaturesConstIterator& other) const {
+  VIXL_ASSERT(IsValid());
+  return (cpu_features_ == other.cpu_features_) && (feature_ == other.feature_);
+}
+
+CPUFeatures::Feature CPUFeaturesConstIterator::operator++() {  // Prefix
+  VIXL_ASSERT(IsValid());
+  do {
+    // Find the next feature. The order is unspecified.
+    VIXL_STATIC_ASSERT(CPUFeatures::kNone == CPUFeatures::kNumberOfFeatures);
+    if (feature_ == CPUFeatures::kNone) {
+      feature_ = static_cast<CPUFeatures::Feature>(0);
+    } else {
+      feature_ = static_cast<CPUFeatures::Feature>(feature_ + 1);
+    }
+    // cpu_features_->Has(kNone) is always true, so this will terminate even if
+    // the features list is empty.
+  } while (!cpu_features_->Has(feature_));
+  return feature_;
+}
+
+CPUFeatures::Feature CPUFeaturesConstIterator::operator++(int) {  // Postfix
+  CPUFeatures::Feature result = feature_;
+  ++(*this);
+  return result;
+}
+
+}  // namespace vixl
diff --git a/src/cpu-features.h b/src/cpu-features.h
new file mode 100644
index 00000000..649e46c3
--- /dev/null
+++ b/src/cpu-features.h
@@ -0,0 +1,338 @@
+// Copyright 2018, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef VIXL_CPU_FEATURES_H
+#define VIXL_CPU_FEATURES_H
+
+#include <ostream>
+
+#include "globals-vixl.h"
+
+namespace vixl {
+
+
+// clang-format off
+#define VIXL_CPU_FEATURE_LIST(V)                                               \
+  /* If set, the OS traps and emulates MRS accesses to relevant (EL1) ID_*  */ \
+  /* registers, so that the detailed feature registers can be read          */ \
+  /* directly.                                                              */ \
+  V(kIDRegisterEmulation, "ID register emulation",  "cpuid")                   \
+                                                                               \
+  V(kFP,                  "FP",                     "fp")                      \
+  V(kNEON,                "NEON",                   "asimd")                   \
+  V(kCRC32,               "CRC32",                  "crc32")                   \
+  /* Cryptographic support instructions.                                    */ \
+  V(kAES,                 "AES",                    "aes")                     \
+  V(kSHA1,                "SHA1",                   "sha1")                    \
+  V(kSHA2,                "SHA2",                   "sha2")                    \
+  /* A form of PMULL{2} with a 128-bit (1Q) result.                         */ \
+  V(kPmull1Q,             "Pmull1Q",                "pmull")                   \
+  /* Atomic operations on memory: CAS, LDADD, STADD, SWP, etc.              */ \
+  V(kAtomics,             "Atomics",                "atomics")                 \
+  /* Limited ordering regions: LDLAR, STLLR and their variants.             */ \
+  V(kLORegions,           "LORegions",              NULL)                      \
+  /* Rounding doubling multiply add/subtract: SQRDMLAH and SQRDMLSH.        */ \
+  V(kRDM,                 "RDM",                    "asimdrdm")                \
+  /* SDOT and UDOT support (in NEON).                                       */ \
+  V(kDotProduct,          "DotProduct",             "asimddp")                 \
+  /* Half-precision (FP16) support for FP and NEON, respectively.           */ \
+  V(kFPHalf,              "FPHalf",                 "fphp")                    \
+  V(kNEONHalf,            "NEONHalf",               "asimdhp")                 \
+  /* Data cache clean to the point of persistence: DC CVAP.                 */ \
+  V(kDCPoP,               "DCPoP",                  "dcpop")                   \
+  /* Cryptographic support instructions.                                    */ \
+  V(kSHA3,                "SHA3",                   "sha3")                    \
+  V(kSHA512,              "SHA512",                 "sha512")                  \
+  V(kSM3,                 "SM3",                    "sm3")                     \
+  V(kSM4,                 "SM4",                    "sm4")                     \
+  /* Pointer authentication for addresses.                                  */ \
+  V(kPAuth,               "PAuth",                  NULL)                      \
+  /* Pointer authentication for addresses uses QARMA.                       */ \
+  V(kPAuthQARMA,          "PAuthQARMA",             NULL)                      \
+  /* Generic authentication (using the PACGA instruction).                  */ \
+  V(kPAuthGeneric,        "PAuthGeneric",           NULL)                      \
+  /* Generic authentication uses QARMA.                                     */ \
+  V(kPAuthGenericQARMA,   "PAuthGenericQARMA",      NULL)                      \
+  /* JavaScript-style FP <-> integer conversion instruction: FJCVTZS.       */ \
+  V(kJSCVT,               "JSCVT",                  "jscvt")                   \
+  /* RCpc-based model (for weaker release consistency): LDAPR and variants. */ \
+  V(kRCpc,                "RCpc",                   "lrcpc")                   \
+  /* Complex number support for NEON: FCMLA and FCADD.                      */ \
+  V(kFcma,                "Fcma",                   "fcma")
+// clang-format on
+
+
+class CPUFeaturesConstIterator;
+
+// A representation of the set of features known to be supported by the target
+// device. Each feature is represented by a simple boolean flag.
+//
+//   - TODO: When the Assembler is asked to assemble an instruction, it should
+//     assert (in debug mode) that the necessary features are available.
+//
+//   - TODO: The Simulator assumes that all features are available by default,
+//     but it should be possible to configure it to either warn or fail if the
+//     simulated code uses features that are not enabled.
+//
+//   - TODO: The Disassembler disassembles all instructions that it knows, but
+//     it could be (optionally) configured to warn if the code uses features or
+//     instructions that are not available.
+//
+//   - TODO: The MacroAssembler relies on the Assembler's assertions, but in
+//     some cases it may be useful for macros to generate a fall-back sequence
+//     in case features are not available.
+//
+// Expected usage:
+//
+//     // By default, VIXL uses CPUFeatures::AArch64LegacyBaseline(), for
+//     // compatibility with older version of VIXL.
+//     MacroAssembler masm;
+//
+//     // Generate code only for the current CPU.
+//     masm.SetCPUFeatures(CPUFeatures::InferFromOS());
+//
+//     // Turn off feature checking entirely.
+//     masm.SetCPUFeatures(CPUFeatures::All());
+//
+// Feature set manipulation:
+//
+//     CPUFeatures f;  // The default constructor gives an empty set.
+//     // Individual features can be added (or removed).
+//     f.Combine(CPUFeatures::kFP, CPUFeatures::kNEON, CPUFeatures::AES);
+//     f.Remove(CPUFeatures::kNEON);
+//
+//     // Some helpers exist for extensions that provide several features.
+//     f.Remove(CPUFeatures::All());
+//     f.Combine(CPUFeatures::AArch64LegacyBaseline());
+//
+//     // Chained construction is also possible.
+//     CPUFeatures g =
+//         f.With(CPUFeatures::kPmull1Q).Without(CPUFeatures::kCRC32);
+//
+//     // Features can be queried. Where multiple features are given, they are
+//     // combined with logical AND.
+//     if (h.Has(CPUFeatures::kNEON)) { ... }
+//     if (h.Has(CPUFeatures::kFP, CPUFeatures::kNEON)) { ... }
+//     if (h.Has(g)) { ... }
+//     // If the empty set is requested, the result is always 'true'.
+//     VIXL_ASSERT(h.Has(CPUFeatures()));
+//
+//     // For debug and reporting purposes, features can be enumerated (or
+//     // printed directly):
+//     std::cout << CPUFeatures::kNEON;  // Prints something like "NEON".
+//     std::cout << f;  // Prints something like "FP, NEON, CRC32".
+class CPUFeatures {
+ public:
+  // clang-format off
+  // Individual features.
+  // These should be treated as opaque tokens. User code should not rely on
+  // specific numeric values or ordering.
+  enum Feature {
+    // Refer to VIXL_CPU_FEATURE_LIST (above) for the list of feature names that
+    // this class supports.
+
+#define VIXL_DECLARE_FEATURE(SYMBOL, NAME, CPUINFO) SYMBOL,
+    VIXL_CPU_FEATURE_LIST(VIXL_DECLARE_FEATURE)
+#undef VIXL_DECLARE_FEATURE
+    kNone,
+    kNumberOfFeatures = kNone
+  };
+  // clang-format on
+
+  // By default, construct with no features enabled.
+  CPUFeatures() : features_(0) {}
+
+  // Construct with some features already enabled.
+  CPUFeatures(Feature feature0,
+              Feature feature1 = kNone,
+              Feature feature2 = kNone,
+              Feature feature3 = kNone);
+
+  // Construct with all features enabled. This can be used to disable feature
+  // checking: `Has(...)` returns true regardless of the argument.
+  static CPUFeatures All();
+
+  // The presence of these features was assumed by version of VIXL before this
+  // API was added, so using this set by default ensures API compatibility.
+  static CPUFeatures AArch64LegacyBaseline() {
+    return CPUFeatures(kFP, kNEON, kCRC32);
+  }
+
+  // Construct a new CPUFeatures object based on what the OS reports.
+  static CPUFeatures InferFromOS();
+
+  // Combine another CPUFeatures object into this one. Features that already
+  // exist in this set are left unchanged.
+  void Combine(const CPUFeatures& other);
+
+  // Combine specific features into this set. Features that already exist in
+  // this set are left unchanged.
+  void Combine(Feature feature0,
+               Feature feature1 = kNone,
+               Feature feature2 = kNone,
+               Feature feature3 = kNone);
+
+  // Remove features in another CPUFeatures object from this one.
+  void Remove(const CPUFeatures& other);
+
+  // Remove specific features from this set.
+  void Remove(Feature feature0,
+              Feature feature1 = kNone,
+              Feature feature2 = kNone,
+              Feature feature3 = kNone);
+
+  // Chaining helpers for convenient construction.
+  CPUFeatures With(const CPUFeatures& other) const;
+  CPUFeatures With(Feature feature0,
+                   Feature feature1 = kNone,
+                   Feature feature2 = kNone,
+                   Feature feature3 = kNone) const;
+  CPUFeatures Without(const CPUFeatures& other) const;
+  CPUFeatures Without(Feature feature0,
+                      Feature feature1 = kNone,
+                      Feature feature2 = kNone,
+                      Feature feature3 = kNone) const;
+
+  // Query features.
+  // Note that an empty query (like `Has(kNone)`) always returns true.
+  bool Has(const CPUFeatures& other) const;
+  bool Has(Feature feature0,
+           Feature feature1 = kNone,
+           Feature feature2 = kNone,
+           Feature feature3 = kNone) const;
+
+  typedef CPUFeaturesConstIterator const_iterator;
+
+  const_iterator begin() const;
+  const_iterator end() const;
+
+ private:
+  // Each bit represents a feature. This field will be replaced as needed if
+  // features are added.
+  uint64_t features_;
+
+  friend std::ostream& operator<<(std::ostream& os,
+                                  const vixl::CPUFeatures& features);
+};
+
+std::ostream& operator<<(std::ostream& os, vixl::CPUFeatures::Feature feature);
+std::ostream& operator<<(std::ostream& os, const vixl::CPUFeatures& features);
+
+// This is not a proper C++ iterator type, but it simulates enough of
+// ForwardIterator that simple loops can be written.
+class CPUFeaturesConstIterator {
+ public:
+  CPUFeaturesConstIterator(const CPUFeatures* cpu_features = NULL,
+                           CPUFeatures::Feature start = CPUFeatures::kNone)
+      : cpu_features_(cpu_features), feature_(start) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  bool operator==(const CPUFeaturesConstIterator& other) const;
+  bool operator!=(const CPUFeaturesConstIterator& other) const {
+    return !(*this == other);
+  }
+  CPUFeatures::Feature operator++();
+  CPUFeatures::Feature operator++(int);
+
+  CPUFeatures::Feature operator*() const {
+    VIXL_ASSERT(IsValid());
+    return feature_;
+  }
+
+  // For proper support of C++'s simplest "Iterator" concept, this class would
+  // have to define member types (such as CPUFeaturesIterator::pointer) to make
+  // it appear as if it iterates over Feature objects in memory. That is, we'd
+  // need CPUFeatures::iterator to behave like std::vector<Feature>::iterator.
+  // This is at least partially possible -- the std::vector<bool> specialisation
+  // does something similar -- but it doesn't seem worthwhile for a
+  // special-purpose debug helper, so they are omitted here.
+ private:
+  const CPUFeatures* cpu_features_;
+  CPUFeatures::Feature feature_;
+
+  bool IsValid() const {
+    return ((cpu_features_ == NULL) && (feature_ == CPUFeatures::kNone)) ||
+           cpu_features_->Has(feature_);
+  }
+};
+
+// A convenience scope for temporarily modifying a CPU features object. This
+// allows features to be enabled for short sequences.
+//
+// Expected usage:
+//
+//  {
+//    CPUFeaturesScope cpu(&masm, CPUFeatures::kCRC32);
+//    // This scope can now use CRC32, as well as anything else that was enabled
+//    // before the scope.
+//
+//    ...
+//
+//    // At the end of the scope, the original CPU features are restored.
+//  }
+class CPUFeaturesScope {
+ public:
+  // Start a CPUFeaturesScope on any object that implements
+  // `CPUFeatures* GetCPUFeatures()`.
+  template <typename T>
+  explicit CPUFeaturesScope(T* cpu_features_wrapper,
+                            CPUFeatures::Feature feature0 = CPUFeatures::kNone,
+                            CPUFeatures::Feature feature1 = CPUFeatures::kNone,
+                            CPUFeatures::Feature feature2 = CPUFeatures::kNone,
+                            CPUFeatures::Feature feature3 = CPUFeatures::kNone)
+      : cpu_features_(cpu_features_wrapper->GetCPUFeatures()),
+        old_features_(*cpu_features_) {
+    cpu_features_->Combine(feature0, feature1, feature2, feature3);
+  }
+
+  template <typename T>
+  CPUFeaturesScope(T* cpu_features_wrapper, const CPUFeatures& other)
+      : cpu_features_(cpu_features_wrapper->GetCPUFeatures()),
+        old_features_(*cpu_features_) {
+    cpu_features_->Combine(other);
+  }
+
+  ~CPUFeaturesScope() { *cpu_features_ = old_features_; }
+
+  // For advanced usage, the CPUFeatures object can be accessed directly.
+  // The scope will restore the original state when it ends.
+
+  CPUFeatures* GetCPUFeatures() const { return cpu_features_; }
+
+  void SetCPUFeatures(const CPUFeatures& cpu_features) {
+    *cpu_features_ = cpu_features;
+  }
+
+ private:
+  CPUFeatures* const cpu_features_;
+  const CPUFeatures old_features_;
+};
+
+
+}  // namespace vixl
+
+#endif  // VIXL_CPU_FEATURES_H
diff --git a/test/test-api.cc b/test/test-api.cc
index a0c3e7fb..fb7e9c70 100644
--- a/test/test-api.cc
+++ b/test/test-api.cc
@@ -24,10 +24,20 @@
 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+#include <iostream>
+#include <set>
+#include <sstream>
+#include <vector>
+
 #include "test-runner.h"
 
+#include "cpu-features.h"
 #include "utils-vixl.h"
 
+#if __cplusplus >= 201103L
+#include <type_traits>
+#endif
+
 #define TEST(name) TEST_(API_##name)
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
@@ -176,4 +186,333 @@ TEST(IsUint_IsInt) {
 #undef TEST_LIST
 }
 
+
+TEST(CPUFeatures_iterator_api) {
+  // CPUFeaturesIterator does not fully satisfy the requirements of C++'s
+  // iterator concepts, but it should implement enough for some basic usage.
+
+  // Arbitrary feature lists.
+  CPUFeatures f1(CPUFeatures::kFP, CPUFeatures::kNEON);
+  CPUFeatures f2(CPUFeatures::kFP, CPUFeatures::kNEON, CPUFeatures::kCRC32);
+  CPUFeatures f3;
+
+  typedef CPUFeatures::const_iterator It;
+
+  It it0;
+  It it1_neon(&f1, CPUFeatures::kNEON);
+  It it2_neon(&f2, CPUFeatures::kNEON);
+  It it2_crc32(&f2, CPUFeatures::kCRC32);
+  It it3(&f3);
+
+  // Equality
+  VIXL_CHECK(it0 == it0);
+  VIXL_CHECK(it1_neon == it1_neon);
+  VIXL_CHECK(it2_neon == it2_neon);
+  VIXL_CHECK(it2_crc32 == it2_crc32);
+  VIXL_CHECK(it3 == it3);
+  VIXL_CHECK(!(it0 == it1_neon));
+  VIXL_CHECK(!(it0 == it3));
+  VIXL_CHECK(!(it1_neon == it2_neon));
+  VIXL_CHECK(!(it1_neon == it2_crc32));
+  VIXL_CHECK(!(it1_neon == it3));
+  VIXL_CHECK(!(it2_neon == it2_crc32));
+  VIXL_CHECK(!(it3 == it0));
+  VIXL_CHECK(!(it3 == it1_neon));
+
+  // Inequality
+  //   (a == b)  <->  !(a != b)
+  VIXL_CHECK(!(it0 != it0));
+  VIXL_CHECK(!(it1_neon != it1_neon));
+  VIXL_CHECK(!(it2_neon != it2_neon));
+  VIXL_CHECK(!(it2_crc32 != it2_crc32));
+  VIXL_CHECK(!(it3 != it3));
+  //   !(a == b)  <->  (a != b)
+  VIXL_CHECK(it0 != it1_neon);
+  VIXL_CHECK(it0 != it3);
+  VIXL_CHECK(it1_neon != it2_neon);
+  VIXL_CHECK(it1_neon != it2_crc32);
+  VIXL_CHECK(it1_neon != it3);
+  VIXL_CHECK(it2_neon != it2_crc32);
+  VIXL_CHECK(it3 != it0);
+  VIXL_CHECK(it3 != it1_neon);
+
+  // Dereferenceable
+  VIXL_CHECK(*it0 == CPUFeatures::kNone);
+  VIXL_CHECK(*it1_neon == CPUFeatures::kNEON);
+  VIXL_CHECK(*it2_neon == CPUFeatures::kNEON);
+  VIXL_CHECK(*it2_crc32 == CPUFeatures::kCRC32);
+  VIXL_CHECK(*it3 == CPUFeatures::kNone);
+
+#if __cplusplus >= 201103L
+  VIXL_STATIC_ASSERT(std::is_copy_constructible<It>::value);
+  VIXL_STATIC_ASSERT(std::is_copy_assignable<It>::value);
+  VIXL_STATIC_ASSERT(std::is_destructible<It>::value);
+#endif
+  // Copy constructable
+  It test0 = it0;
+  It test1 = it1_neon;
+  It test2(it2_neon);
+  VIXL_CHECK(test0 == It(NULL, CPUFeatures::kNone));
+  VIXL_CHECK(test1 == It(&f1, CPUFeatures::kNEON));
+  VIXL_CHECK(test2 == It(&f2, CPUFeatures::kNEON));
+
+  // Copy assignable
+  test2 = it2_crc32;
+  VIXL_CHECK(test2 == It(&f2, CPUFeatures::kCRC32));
+
+  // Incrementable
+  // - Incrementing has no effect on an empty CPUFeatures.
+  VIXL_CHECK(it3++ == CPUFeatures::kNone);
+  VIXL_CHECK(++it3 == CPUFeatures::kNone);
+  VIXL_CHECK(it3 == It(&f3, CPUFeatures::kNone));
+  // - Incrementing moves to the next feature, wrapping around (through kNone).
+  //   This test will need to be updated if the Feature enum is reordered.
+  VIXL_CHECK(it2_neon++ == CPUFeatures::kNEON);
+  VIXL_CHECK(it2_neon++ == CPUFeatures::kCRC32);
+  VIXL_CHECK(it2_neon++ == CPUFeatures::kNone);
+  VIXL_CHECK(it2_neon++ == CPUFeatures::kFP);
+  VIXL_CHECK(it2_neon == It(&f2, CPUFeatures::kNEON));
+  VIXL_CHECK(++it2_crc32 == CPUFeatures::kNone);
+  VIXL_CHECK(++it2_crc32 == CPUFeatures::kFP);
+  VIXL_CHECK(++it2_crc32 == CPUFeatures::kNEON);
+  VIXL_CHECK(++it2_crc32 == CPUFeatures::kCRC32);
+  VIXL_CHECK(it2_crc32 == It(&f2, CPUFeatures::kCRC32));
+}
+
+
+TEST(CPUFeatures_iterator_loops) {
+  // Check that CPUFeaturesIterator can be used for some simple loops.
+
+  // Arbitrary feature lists.
+  CPUFeatures f1(CPUFeatures::kFP, CPUFeatures::kNEON);
+  CPUFeatures f2(CPUFeatures::kFP, CPUFeatures::kNEON, CPUFeatures::kCRC32);
+  CPUFeatures f3;
+
+  // This test will need to be updated if the Feature enum is reordered.
+
+  std::vector<CPUFeatures::Feature> f1_list;
+  for (CPUFeatures::const_iterator it = f1.begin(); it != f1.end(); ++it) {
+    f1_list.push_back(*it);
+  }
+  VIXL_CHECK(f1_list.size() == 2);
+  VIXL_CHECK(f1_list[0] == CPUFeatures::kFP);
+  VIXL_CHECK(f1_list[1] == CPUFeatures::kNEON);
+
+  std::vector<CPUFeatures::Feature> f2_list;
+  for (CPUFeatures::const_iterator it = f2.begin(); it != f2.end(); ++it) {
+    f2_list.push_back(*it);
+  }
+  VIXL_CHECK(f2_list.size() == 3);
+  VIXL_CHECK(f2_list[0] == CPUFeatures::kFP);
+  VIXL_CHECK(f2_list[1] == CPUFeatures::kNEON);
+  VIXL_CHECK(f2_list[2] == CPUFeatures::kCRC32);
+
+  std::vector<CPUFeatures::Feature> f3_list;
+  for (CPUFeatures::const_iterator it = f3.begin(); it != f3.end(); ++it) {
+    f3_list.push_back(*it);
+  }
+  VIXL_CHECK(f3_list.size() == 0);
+
+#if __cplusplus >= 201103L
+  std::vector<CPUFeatures::Feature> f2_list_cxx11;
+  for (auto&& feature : f2) {
+    f2_list_cxx11.push_back(feature);
+  }
+  VIXL_CHECK(f2_list_cxx11.size() == 3);
+  VIXL_CHECK(f2_list_cxx11[0] == CPUFeatures::kFP);
+  VIXL_CHECK(f2_list_cxx11[1] == CPUFeatures::kNEON);
+  VIXL_CHECK(f2_list_cxx11[2] == CPUFeatures::kCRC32);
+
+  std::vector<CPUFeatures::Feature> f3_list_cxx11;
+  for (auto&& feature : f3) {
+    f3_list_cxx11.push_back(feature);
+  }
+  VIXL_CHECK(f3_list_cxx11.size() == 0);
+#endif
+}
+
+
+TEST(CPUFeatures_empty) {
+  // A default-constructed CPUFeatures has no features enabled.
+  CPUFeatures f;
+  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
+    VIXL_ABORT();
+  }
+}
+
+
+static void CPUFeaturesFormatHelper(const char* expected,
+                                    const CPUFeatures& features) {
+  std::stringstream os;
+  os << features;
+  std::string os_str = os.str();
+  if (os_str != expected) {
+    std::cout << "Found: " << os_str << "\n";
+    std::cout << "Expected: " << expected << "\n";
+    VIXL_ABORT();
+  }
+}
+
+
+TEST(CPUFeatures_format) {
+  // Check that the debug output is complete and accurate.
+
+  // Individual features.
+  CPUFeaturesFormatHelper("", CPUFeatures(CPUFeatures::kNone));
+  CPUFeaturesFormatHelper("FP", CPUFeatures(CPUFeatures::kFP));
+  CPUFeaturesFormatHelper("NEON", CPUFeatures(CPUFeatures::kNEON));
+  CPUFeaturesFormatHelper("AES", CPUFeatures(CPUFeatures::kAES));
+  CPUFeaturesFormatHelper("Pmull1Q", CPUFeatures(CPUFeatures::kPmull1Q));
+  CPUFeaturesFormatHelper("SHA1", CPUFeatures(CPUFeatures::kSHA1));
+  CPUFeaturesFormatHelper("SHA2", CPUFeatures(CPUFeatures::kSHA2));
+  CPUFeaturesFormatHelper("CRC32", CPUFeatures(CPUFeatures::kCRC32));
+
+  // Combinations of (arbitrary) features.
+  // This test will need to be updated if the Feature enum is reordered.
+  CPUFeatures f(CPUFeatures::kFP, CPUFeatures::kNEON);
+  CPUFeaturesFormatHelper("FP, NEON", f);
+  f.Combine(CPUFeatures::kCRC32);
+  CPUFeaturesFormatHelper("FP, NEON, CRC32", f);
+  f.Combine(CPUFeatures::kFcma);
+  CPUFeaturesFormatHelper("FP, NEON, CRC32, Fcma", f);
+  f.Combine(CPUFeatures::kSHA1);
+  CPUFeaturesFormatHelper("FP, NEON, CRC32, SHA1, Fcma", f);
+
+  CPUFeaturesFormatHelper(
+      "ID register emulation, "
+      // Armv8.0
+      "FP, NEON, CRC32, "
+      "AES, SHA1, SHA2, Pmull1Q, "
+      // Armv8.1
+      "Atomics, LORegions, RDM, "
+      // Armv8.2
+      "DotProduct, FPHalf, NEONHalf, DCPoP, SHA3, SHA512, SM3, SM4, "
+      // Armv8.3
+      "PAuth, PAuthQARMA, PAuthGeneric, PAuthGenericQARMA, JSCVT, RCpc, Fcma",
+      CPUFeatures::All());
+}
+
+
+static void CPUFeaturesPredefinedResultCheckHelper(
+    const std::set<CPUFeatures::Feature>& unexpected,
+    const std::set<CPUFeatures::Feature>& expected) {
+  // Print a helpful diagnostic before checking the result.
+  typedef std::set<CPUFeatures::Feature>::const_iterator It;
+  if (!unexpected.empty()) {
+    std::cout << "Unexpected features:\n";
+    for (It it = unexpected.begin(); it != unexpected.end(); ++it) {
+      std::cout << "  " << *it << "\n";
+    }
+  }
+  if (!expected.empty()) {
+    std::cout << "Missing features:\n";
+    for (It it = expected.begin(); it != expected.end(); ++it) {
+      std::cout << "  " << *it << "\n";
+    }
+  }
+  VIXL_CHECK(unexpected.empty() && expected.empty());
+}
+
+
+TEST(CPUFeatures_predefined_legacy) {
+  CPUFeatures f = CPUFeatures::AArch64LegacyBaseline();
+  std::set<CPUFeatures::Feature> unexpected;
+  std::set<CPUFeatures::Feature> expected;
+  expected.insert(CPUFeatures::kFP);
+  expected.insert(CPUFeatures::kNEON);
+  expected.insert(CPUFeatures::kCRC32);
+
+  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
+    if (expected.erase(*it) == 0) unexpected.insert(*it);
+  }
+  CPUFeaturesPredefinedResultCheckHelper(unexpected, expected);
+}
+
+
+TEST(CPUFeatures_predefined_all) {
+  CPUFeatures f = CPUFeatures::All();
+  std::set<CPUFeatures::Feature> found;
+
+  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
+    found.insert(*it);
+  }
+  VIXL_CHECK(found.size() == CPUFeatures::kNumberOfFeatures);
+}
+
+// The CPUFeaturesScope constructor is templated, and needs an object which
+// implements `CPUFeatures* GetCPUFeatures()`. This is normally something like
+// the Assembler, but for the tests we use an architecture-independent wrapper.
+class GetCPUFeaturesWrapper {
+ public:
+  explicit GetCPUFeaturesWrapper(CPUFeatures* cpu_features)
+      : cpu_features_(cpu_features) {}
+
+  CPUFeatures* GetCPUFeatures() const { return cpu_features_; }
+
+ private:
+  CPUFeatures* cpu_features_;
+};
+
+TEST(CPUFeaturesScope) {
+  // Test that CPUFeaturesScope properly preserves state.
+
+  CPUFeatures cpu(CPUFeatures::kCRC32, CPUFeatures::kSHA1, CPUFeatures::kAES);
+  GetCPUFeaturesWrapper top_level(&cpu);
+
+  const CPUFeatures original_outer = cpu;
+
+  {  // Test setting both new and existing features.
+    CPUFeaturesScope outer(&top_level, CPUFeatures::kSHA2, CPUFeatures::kAES);
+    VIXL_CHECK(outer.GetCPUFeatures() == &cpu);
+    VIXL_CHECK(cpu.Has(CPUFeatures::kCRC32,
+                       CPUFeatures::kSHA1,
+                       CPUFeatures::kSHA2,
+                       CPUFeatures::kAES));
+
+    // Features can be added or removed directly, in the usual fashion.
+    // (The scope will restore their original status when it ends.)
+    cpu.Combine(CPUFeatures::kSHA1, CPUFeatures::kAtomics);
+    VIXL_CHECK(cpu.Has(CPUFeatures::kCRC32,
+                       CPUFeatures::kSHA1,
+                       CPUFeatures::kSHA2,
+                       CPUFeatures::kAES));
+    VIXL_CHECK(cpu.Has(CPUFeatures::kAtomics));
+
+    cpu.Remove(CPUFeatures::kSHA2, CPUFeatures::kAES);
+    VIXL_CHECK(!cpu.Has(CPUFeatures::kSHA2, CPUFeatures::kAES));
+    VIXL_CHECK(cpu.Has(CPUFeatures::kCRC32,
+                       CPUFeatures::kSHA1,
+                       CPUFeatures::kAtomics));
+
+    const CPUFeatures original_inner = cpu;
+
+    // Scopes can be nested.
+    {
+      // A CPUFeaturesScope can be constructed from a CPUFeatures*, or any
+      // (non-local) object that implements `CPUFeatures* GetCPUFeatures()`.
+      // Typically, this would be an Assembler or MacroAssembler, but
+      // CPUFeatureScope itself provides this method, and allows the test to
+      // remain architecture-agnostic.
+
+      CPUFeatures auth(CPUFeatures::kPAuth,
+                       CPUFeatures::kPAuthQARMA,
+                       CPUFeatures::kPAuthGeneric,
+                       CPUFeatures::kPAuthGenericQARMA);
+
+      CPUFeaturesScope inner(&outer, auth);
+      VIXL_CHECK(inner.GetCPUFeatures() == &cpu);
+      VIXL_CHECK(cpu.Has(auth.With(CPUFeatures::kCRC32,
+                                   CPUFeatures::kSHA1,
+                                   CPUFeatures::kAtomics)));
+    }
+    // Check for equivalence.
+    VIXL_CHECK(cpu.Has(original_inner));
+    VIXL_CHECK(original_inner.Has(cpu));
+  }
+
+  // Check for equivalence.
+  VIXL_CHECK(cpu.Has(original_outer));
+  VIXL_CHECK(original_outer.Has(cpu));
+}
+
 }  // namespace vixl