blob: 0e3cc34bcc2207f88c5179a60abcadefb2dcbeac [file] [log] [blame]
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
David Sterbae7bf0682010-12-27 16:51:15 +01003 * This driver supports the memory controllers found on the Intel
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03004 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030012 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Nils Carlson535e9c72011-08-08 06:21:26 -030034#include <linux/dmi.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030035#include <linux/edac.h>
36#include <linux/mmzone.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Borislav Petkov4140c542011-07-18 11:24:46 -030038#include <asm/mce.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030039#include <asm/processor.h>
Sedat Dilek4fad8092011-09-21 23:44:52 -030040#include <asm/div64.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030041
42#include "edac_core.h"
43
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030044/* Static vars */
45static LIST_HEAD(i7core_edac_list);
46static DEFINE_MUTEX(i7core_edac_lock);
47static int probed;
48
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -030049static int use_pci_fixup;
50module_param(use_pci_fixup, int, 0444);
51MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030052/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030053 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
57 */
58#define MAX_SOCKET_BUSES 2
59
60
61/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062 * Alter this version for the module when modifications are made
63 */
Michal Marek152ba392011-04-01 12:41:20 +020064#define I7CORE_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030065#define EDAC_MOD_STR "i7core_edac"
66
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030067/*
68 * Debug macros
69 */
70#define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
72
73#define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75
76/*
77 * i7core Memory Controller Registers
78 */
79
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030080 /* OFFSETS for Device 0 Function 0 */
81
82#define MC_CFG_CONTROL 0x90
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -030083 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030085
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030086 /* OFFSETS for Device 3 Function 0 */
87
88#define MC_CONTROL 0x48
89#define MC_STATUS 0x4c
90#define MC_MAX_DOD 0x64
91
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030092/*
93 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
94 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
95 */
96
97#define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
99
100#define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
103
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300104/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300105#define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
109
110#define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
Nils Carlson535e9c72011-08-08 06:21:26 -0300112 #define SCRUBINTERVAL_MASK 0xffffff
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300113
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300114#define MC_COR_ECC_CNT_0 0x80
115#define MC_COR_ECC_CNT_1 0x84
116#define MC_COR_ECC_CNT_2 0x88
117#define MC_COR_ECC_CNT_3 0x8c
118#define MC_COR_ECC_CNT_4 0x90
119#define MC_COR_ECC_CNT_5 0x94
120
121#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
123
124
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
126
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300127#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
132
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300133#define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
136
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300137#define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
139
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300140#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300141#define MC_CHANNEL_ERROR_MASK 0xf8
142#define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300151
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300153
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300154#define MC_DOD_CH_DIMM0 0x48
155#define MC_DOD_CH_DIMM1 0x4c
156#define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300169
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300170#define MC_RANK_PRESENT 0x7c
171
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300172#define MC_SAG_CH_0 0x80
173#define MC_SAG_CH_1 0x84
174#define MC_SAG_CH_2 0x88
175#define MC_SAG_CH_3 0x8c
176#define MC_SAG_CH_4 0x90
177#define MC_SAG_CH_5 0x94
178#define MC_SAG_CH_6 0x98
179#define MC_SAG_CH_7 0x9c
180
181#define MC_RIR_LIMIT_CH_0 0x40
182#define MC_RIR_LIMIT_CH_1 0x44
183#define MC_RIR_LIMIT_CH_2 0x48
184#define MC_RIR_LIMIT_CH_3 0x4C
185#define MC_RIR_LIMIT_CH_4 0x50
186#define MC_RIR_LIMIT_CH_5 0x54
187#define MC_RIR_LIMIT_CH_6 0x58
188#define MC_RIR_LIMIT_CH_7 0x5C
189#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190
191#define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
194
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300195/*
196 * i7core structs
197 */
198
199#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300200#define MAX_DIMMS 3 /* Max DIMMS per channel */
201#define MAX_MCR_FUNC 4
202#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203
204struct i7core_info {
205 u32 mc_control;
206 u32 mc_status;
207 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300208 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300209};
210
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300211
212struct i7core_inject {
213 int enable;
214
215 u32 section;
216 u32 type;
217 u32 eccmask;
218
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
221};
222
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300223struct i7core_channel {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300224 u32 ranks;
225 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300226};
227
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300228struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300229 int dev;
230 int func;
231 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300232 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300233};
234
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300235struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300236 const struct pci_id_descr *descr;
237 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300238};
239
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300240struct i7core_dev {
241 struct list_head list;
242 u8 socket;
243 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300244 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300245 struct mem_ctl_info *mci;
246};
247
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300248struct i7core_pvt {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300249 struct pci_dev *pci_noncore;
250 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
251 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
252
253 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300254
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300255 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300256 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300257 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300258
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300259 int ce_count_available;
260 int csrow_map[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300261
262 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300263 unsigned long udimm_ce_count[MAX_DIMMS];
264 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300265 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300266 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
267 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300268
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -0300269 bool is_registered, enable_scrub;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300270
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300271 /* Fifo double buffers */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300272 struct mce mce_entry[MCE_LOG_LEN];
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300273 struct mce mce_outentry[MCE_LOG_LEN];
274
275 /* Fifo in/out counters */
276 unsigned mce_in, mce_out;
277
278 /* Count indicator to show errors not got */
279 unsigned mce_overrun;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300280
Nils Carlson535e9c72011-08-08 06:21:26 -0300281 /* DCLK Frequency used for computing scrub rate */
282 int dclk_freq;
283
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300284 /* Struct to control EDAC polling */
285 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300286};
287
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300288#define PCI_DESCR(device, function, device_id) \
289 .dev = (device), \
290 .func = (function), \
291 .dev_id = (device_id)
292
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300293static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300294 /* Memory controller */
295 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
296 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300297 /* Exists only for RDIMM */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300298 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300299 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
300
301 /* Channel 0 */
302 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
303 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
304 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
305 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
306
307 /* Channel 1 */
308 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
309 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
310 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
311 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
312
313 /* Channel 2 */
314 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
315 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
316 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
317 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300318
319 /* Generic Non-core registers */
320 /*
321 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
322 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
323 * the probing code needs to test for the other address in case of
324 * failure of this one
325 */
326 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
327
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300328};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300329
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300330static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300331 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
332 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
333 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
334
335 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
336 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
337 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
338 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
339
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300340 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
341 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
342 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
343 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300344
345 /*
346 * This is the PCI device has an alternate address on some
347 * processors like Core i7 860
348 */
349 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300350};
351
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300352static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300353 /* Memory controller */
354 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
355 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
356 /* Exists only for RDIMM */
357 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
358 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
359
360 /* Channel 0 */
361 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
362 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
363 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
364 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
365
366 /* Channel 1 */
367 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
368 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
369 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
370 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
371
372 /* Channel 2 */
373 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
374 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
375 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
376 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300377
378 /* Generic Non-core registers */
379 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
380
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300381};
382
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300383#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
384static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300385 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
386 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
387 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -0200388 {0,} /* 0 terminated list. */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300389};
390
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300391/*
392 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300393 */
Lionel Debroux36c46f32012-02-27 07:41:47 +0100394static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300396 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300397 {0,} /* 0 terminated list. */
398};
399
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300400/****************************************************************************
401 Anciliary status routines
402 ****************************************************************************/
403
404 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300405#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
406#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300407
408 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300409#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300410#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300411
412 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300413static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300414{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300415 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300416}
417
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300418static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300419{
420 static int ranks[4] = { 1, 2, 4, -EINVAL };
421
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300422 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300423}
424
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300425static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300426{
427 static int banks[4] = { 4, 8, 16, -EINVAL };
428
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300429 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300430}
431
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300432static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300433{
434 static int rows[8] = {
435 1 << 12, 1 << 13, 1 << 14, 1 << 15,
436 1 << 16, -EINVAL, -EINVAL, -EINVAL,
437 };
438
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300439 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300440}
441
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300442static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300443{
444 static int cols[8] = {
445 1 << 10, 1 << 11, 1 << 12, -EINVAL,
446 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300447 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300448}
449
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300450static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300451{
452 struct i7core_dev *i7core_dev;
453
454 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
455 if (i7core_dev->socket == socket)
456 return i7core_dev;
457 }
458
459 return NULL;
460}
461
Hidetoshi Seto848b2f72010-08-20 04:24:44 -0300462static struct i7core_dev *alloc_i7core_dev(u8 socket,
463 const struct pci_id_table *table)
464{
465 struct i7core_dev *i7core_dev;
466
467 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
468 if (!i7core_dev)
469 return NULL;
470
471 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
472 GFP_KERNEL);
473 if (!i7core_dev->pdev) {
474 kfree(i7core_dev);
475 return NULL;
476 }
477
478 i7core_dev->socket = socket;
479 i7core_dev->n_devs = table->n_devs;
480 list_add_tail(&i7core_dev->list, &i7core_edac_list);
481
482 return i7core_dev;
483}
484
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -0300485static void free_i7core_dev(struct i7core_dev *i7core_dev)
486{
487 list_del(&i7core_dev->list);
488 kfree(i7core_dev->pdev);
489 kfree(i7core_dev);
490}
491
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300492/****************************************************************************
493 Memory check routines
494 ****************************************************************************/
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300495static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
496 unsigned func)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300497{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300498 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300499 int i;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300500
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300501 if (!i7core_dev)
502 return NULL;
503
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300504 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300505 if (!i7core_dev->pdev[i])
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300506 continue;
507
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300508 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
509 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
510 return i7core_dev->pdev[i];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300511 }
512 }
513
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300514 return NULL;
515}
516
Mauro Carvalho Chehabec6df242009-07-18 10:44:30 -0300517/**
518 * i7core_get_active_channels() - gets the number of channels and csrows
519 * @socket: Quick Path Interconnect socket
520 * @channels: Number of channels that will be returned
521 * @csrows: Number of csrows found
522 *
523 * Since EDAC core needs to know in advance the number of available channels
524 * and csrows, in order to allocate memory for csrows/channels, it is needed
525 * to run two similar steps. At the first step, implemented on this function,
526 * it checks the number of csrows/channels present at one socket.
527 * this is used in order to properly allocate the size of mci components.
528 *
529 * It should be noticed that none of the current available datasheets explain
530 * or even mention how csrows are seen by the memory controller. So, we need
531 * to add a fake description for csrows.
532 * So, this driver is attributing one DIMM memory for one csrow.
533 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300534static int i7core_get_active_channels(const u8 socket, unsigned *channels,
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300535 unsigned *csrows)
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300536{
537 struct pci_dev *pdev = NULL;
538 int i, j;
539 u32 status, control;
540
541 *channels = 0;
542 *csrows = 0;
543
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300544 pdev = get_pdev_slot_func(socket, 3, 0);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300545 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300546 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
547 socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300548 return -ENODEV;
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300549 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300550
551 /* Device 3 function 0 reads */
552 pci_read_config_dword(pdev, MC_STATUS, &status);
553 pci_read_config_dword(pdev, MC_CONTROL, &control);
554
555 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300556 u32 dimm_dod[3];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300557 /* Check if the channel is active */
558 if (!(control & (1 << (8 + i))))
559 continue;
560
561 /* Check if the channel is disabled */
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300562 if (status & (1 << i))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300563 continue;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300564
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300565 pdev = get_pdev_slot_func(socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300566 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300567 i7core_printk(KERN_ERR, "Couldn't find socket %d "
568 "fn %d.%d!!!\n",
569 socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300570 return -ENODEV;
571 }
572 /* Devices 4-6 function 1 */
573 pci_read_config_dword(pdev,
574 MC_DOD_CH_DIMM0, &dimm_dod[0]);
575 pci_read_config_dword(pdev,
576 MC_DOD_CH_DIMM1, &dimm_dod[1]);
577 pci_read_config_dword(pdev,
578 MC_DOD_CH_DIMM2, &dimm_dod[2]);
579
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300580 (*channels)++;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300581
582 for (j = 0; j < 3; j++) {
583 if (!DIMM_PRESENT(dimm_dod[j]))
584 continue;
585 (*csrows)++;
586 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300587 }
588
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -0300589 debugf0("Number of active channels on socket %d: %d\n",
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300590 socket, *channels);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300591
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300592 return 0;
593}
594
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300595static int get_dimm_config(struct mem_ctl_info *mci)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300596{
597 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300598 struct csrow_info *csr;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300599 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300600 int i, j;
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300601 int csrow = 0;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300602 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300603 enum mem_type mtype;
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300604 struct dimm_info *dimm;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300605
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300606 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300607 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300608 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300609 return -ENODEV;
610
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300611 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300612 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
613 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
614 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
615 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300616
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300617 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
Mauro Carvalho Chehab4af91882009-09-24 09:58:26 -0300618 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300619 pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300620
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300621 if (ECC_ENABLED(pvt)) {
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300622 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300623 if (ECCx8(pvt))
624 mode = EDAC_S8ECD8ED;
625 else
626 mode = EDAC_S4ECD4ED;
627 } else {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300628 debugf0("ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300629 mode = EDAC_NONE;
630 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300631
632 /* FIXME: need to handle the error codes */
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300633 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
634 "x%x x 0x%x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300635 numdimms(pvt->info.max_dod),
636 numrank(pvt->info.max_dod >> 2),
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300637 numbank(pvt->info.max_dod >> 4),
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300638 numrow(pvt->info.max_dod >> 6),
639 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300640
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300641 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300642 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300643
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300644 if (!pvt->pci_ch[i][0])
645 continue;
646
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300647 if (!CH_ACTIVE(pvt, i)) {
648 debugf0("Channel %i is not active\n", i);
649 continue;
650 }
651 if (CH_DISABLED(pvt, i)) {
652 debugf0("Channel %i is disabled\n", i);
653 continue;
654 }
655
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300656 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300657 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300658 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
659
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300660 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300661 4 : 2;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300662
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300663 if (data & REGISTERED_DIMM)
664 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300665 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300666 mtype = MEM_DDR3;
667#if 0
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300668 if (data & THREE_DIMMS_PRESENT)
669 pvt->channel[i].dimms = 3;
670 else if (data & SINGLE_QUAD_RANK_PRESENT)
671 pvt->channel[i].dimms = 1;
672 else
673 pvt->channel[i].dimms = 2;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300674#endif
675
676 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300677 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300678 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300679 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300680 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300681 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300682 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300683
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300684 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300685 "%d ranks, %cDIMMs\n",
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300686 i,
687 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
688 data,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300689 pvt->channel[i].ranks,
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300690 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300691
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300692 for (j = 0; j < 3; j++) {
693 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300694 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300695
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300696 if (!DIMM_PRESENT(dimm_dod[j]))
697 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300698
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300699 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
700 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
701 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
702 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300703
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300704 /* DDR3 has 8 I/O banks */
705 size = (rows * cols * banks * ranks) >> (20 - 3);
706
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300707 pvt->channel[i].dimms++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300708
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300709 debugf0("\tdimm %d %d Mb offset: %x, "
710 "bank: %d, rank: %d, row: %#x, col: %#x\n",
711 j, size,
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300712 RANKOFFSET(dimm_dod[j]),
713 banks, ranks, rows, cols);
714
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300715 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300716
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300717 csr = &mci->csrows[csrow];
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300718
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300719 pvt->csrow_map[i][j] = csrow;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300720
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300721 dimm = csr->channels[0].dimm;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300722 dimm->nr_pages = npages;
723
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300724 switch (banks) {
725 case 4:
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300726 dimm->dtype = DEV_X4;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300727 break;
728 case 8:
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300729 dimm->dtype = DEV_X8;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300730 break;
731 case 16:
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300732 dimm->dtype = DEV_X16;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300733 break;
734 default:
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300735 dimm->dtype = DEV_UNKNOWN;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300736 }
737
Mauro Carvalho Chehab084a4fcc2012-01-27 18:38:08 -0300738 snprintf(dimm->label, sizeof(dimm->label),
739 "CPU#%uChannel#%u_DIMM#%u",
740 pvt->i7core_dev->socket, i, j);
741 dimm->grain = 8;
742 dimm->edac_mode = mode;
743 dimm->mtype = mtype;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300744 csrow++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300745 }
746
747 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
748 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
749 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
750 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
751 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
752 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
753 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
754 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300755 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300756 for (j = 0; j < 8; j++)
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300757 debugf1("\t\t%#x\t%#x\t%#x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300758 (value[j] >> 27) & 0x1,
759 (value[j] >> 24) & 0x7,
David Sterba80b8ce82010-12-27 15:39:12 +0000760 (value[j] & ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300761 }
762
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300763 return 0;
764}
765
766/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300767 Error insertion routines
768 ****************************************************************************/
769
770/* The i7core has independent error injection features per channel.
771 However, to have a simpler code, we don't allow enabling error injection
772 on more than one channel.
773 Also, since a change at an inject parameter will be applied only at enable,
774 we're disabling error injection on all write calls to the sysfs nodes that
775 controls the error code injection.
776 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300777static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300778{
779 struct i7core_pvt *pvt = mci->pvt_info;
780
781 pvt->inject.enable = 0;
782
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300783 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300784 return -ENODEV;
785
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300786 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300787 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300788
789 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300790}
791
792/*
793 * i7core inject inject.section
794 *
795 * accept and store error injection inject.section value
796 * bit 0 - refers to the lower 32-byte half cacheline
797 * bit 1 - refers to the upper 32-byte half cacheline
798 */
799static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
800 const char *data, size_t count)
801{
802 struct i7core_pvt *pvt = mci->pvt_info;
803 unsigned long value;
804 int rc;
805
806 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300807 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300808
809 rc = strict_strtoul(data, 10, &value);
810 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300811 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300812
813 pvt->inject.section = (u32) value;
814 return count;
815}
816
817static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
818 char *data)
819{
820 struct i7core_pvt *pvt = mci->pvt_info;
821 return sprintf(data, "0x%08x\n", pvt->inject.section);
822}
823
824/*
825 * i7core inject.type
826 *
827 * accept and store error injection inject.section value
828 * bit 0 - repeat enable - Enable error repetition
829 * bit 1 - inject ECC error
830 * bit 2 - inject parity error
831 */
832static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
833 const char *data, size_t count)
834{
835 struct i7core_pvt *pvt = mci->pvt_info;
836 unsigned long value;
837 int rc;
838
839 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300840 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300841
842 rc = strict_strtoul(data, 10, &value);
843 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300844 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300845
846 pvt->inject.type = (u32) value;
847 return count;
848}
849
850static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
851 char *data)
852{
853 struct i7core_pvt *pvt = mci->pvt_info;
854 return sprintf(data, "0x%08x\n", pvt->inject.type);
855}
856
857/*
858 * i7core_inject_inject.eccmask_store
859 *
860 * The type of error (UE/CE) will depend on the inject.eccmask value:
861 * Any bits set to a 1 will flip the corresponding ECC bit
862 * Correctable errors can be injected by flipping 1 bit or the bits within
863 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
864 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
865 * uncorrectable error to be injected.
866 */
867static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
868 const char *data, size_t count)
869{
870 struct i7core_pvt *pvt = mci->pvt_info;
871 unsigned long value;
872 int rc;
873
874 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300875 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300876
877 rc = strict_strtoul(data, 10, &value);
878 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300879 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300880
881 pvt->inject.eccmask = (u32) value;
882 return count;
883}
884
885static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
886 char *data)
887{
888 struct i7core_pvt *pvt = mci->pvt_info;
889 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
890}
891
892/*
893 * i7core_addrmatch
894 *
895 * The type of error (UE/CE) will depend on the inject.eccmask value:
896 * Any bits set to a 1 will flip the corresponding ECC bit
897 * Correctable errors can be injected by flipping 1 bit or the bits within
898 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
899 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
900 * uncorrectable error to be injected.
901 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300902
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300903#define DECLARE_ADDR_MATCH(param, limit) \
904static ssize_t i7core_inject_store_##param( \
905 struct mem_ctl_info *mci, \
906 const char *data, size_t count) \
907{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300908 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300909 long value; \
910 int rc; \
911 \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300912 debugf1("%s()\n", __func__); \
913 pvt = mci->pvt_info; \
914 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300915 if (pvt->inject.enable) \
916 disable_inject(mci); \
917 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300918 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300919 value = -1; \
920 else { \
921 rc = strict_strtoul(data, 10, &value); \
922 if ((rc < 0) || (value >= limit)) \
923 return -EIO; \
924 } \
925 \
926 pvt->inject.param = value; \
927 \
928 return count; \
929} \
930 \
931static ssize_t i7core_inject_show_##param( \
932 struct mem_ctl_info *mci, \
933 char *data) \
934{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300935 struct i7core_pvt *pvt; \
936 \
937 pvt = mci->pvt_info; \
938 debugf1("%s() pvt=%p\n", __func__, pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300939 if (pvt->inject.param < 0) \
940 return sprintf(data, "any\n"); \
941 else \
942 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300943}
944
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300945#define ATTR_ADDR_MATCH(param) \
946 { \
947 .attr = { \
948 .name = #param, \
949 .mode = (S_IRUGO | S_IWUSR) \
950 }, \
951 .show = i7core_inject_show_##param, \
952 .store = i7core_inject_store_##param, \
953 }
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300954
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300955DECLARE_ADDR_MATCH(channel, 3);
956DECLARE_ADDR_MATCH(dimm, 3);
957DECLARE_ADDR_MATCH(rank, 4);
958DECLARE_ADDR_MATCH(bank, 32);
959DECLARE_ADDR_MATCH(page, 0x10000);
960DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300961
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300962static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300963{
964 u32 read;
965 int count;
966
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300967 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
968 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
969 where, val);
970
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300971 for (count = 0; count < 10; count++) {
972 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300973 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300974 pci_write_config_dword(dev, where, val);
975 pci_read_config_dword(dev, where, &read);
976
977 if (read == val)
978 return 0;
979 }
980
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300981 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
982 "write=%08x. Read=%08x\n",
983 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
984 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300985
986 return -EINVAL;
987}
988
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300989/*
990 * This routine prepares the Memory Controller for error injection.
991 * The error will be injected when some process tries to write to the
992 * memory that matches the given criteria.
993 * The criteria can be set in terms of a mask where dimm, rank, bank, page
994 * and col can be specified.
995 * A -1 value for any of the mask items will make the MCU to ignore
996 * that matching criteria for error injection.
997 *
998 * It should be noticed that the error will only happen after a write operation
999 * on a memory that matches the condition. if REPEAT_EN is not enabled at
1000 * inject mask, then it will produce just one error. Otherwise, it will repeat
1001 * until the injectmask would be cleaned.
1002 *
1003 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
1004 * is reliable enough to check if the MC is using the
1005 * three channels. However, this is not clear at the datasheet.
1006 */
1007static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
1008 const char *data, size_t count)
1009{
1010 struct i7core_pvt *pvt = mci->pvt_info;
1011 u32 injectmask;
1012 u64 mask = 0;
1013 int rc;
1014 long enable;
1015
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001016 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001017 return 0;
1018
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001019 rc = strict_strtoul(data, 10, &enable);
1020 if ((rc < 0))
1021 return 0;
1022
1023 if (enable) {
1024 pvt->inject.enable = 1;
1025 } else {
1026 disable_inject(mci);
1027 return count;
1028 }
1029
1030 /* Sets pvt->inject.dimm mask */
1031 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001032 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001033 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001034 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -02001035 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001036 else
Alan Cox486dd092009-11-08 01:34:27 -02001037 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001038 }
1039
1040 /* Sets pvt->inject.rank mask */
1041 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001042 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001043 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001044 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -02001045 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001046 else
Alan Cox486dd092009-11-08 01:34:27 -02001047 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001048 }
1049
1050 /* Sets pvt->inject.bank mask */
1051 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001052 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001053 else
Alan Cox486dd092009-11-08 01:34:27 -02001054 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001055
1056 /* Sets pvt->inject.page mask */
1057 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001058 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001059 else
Alan Cox486dd092009-11-08 01:34:27 -02001060 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001061
1062 /* Sets pvt->inject.column mask */
1063 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001064 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001065 else
Alan Cox486dd092009-11-08 01:34:27 -02001066 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001067
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001068 /*
1069 * bit 0: REPEAT_EN
1070 * bits 1-2: MASK_HALF_CACHELINE
1071 * bit 3: INJECT_ECC
1072 * bit 4: INJECT_ADDR_PARITY
1073 */
1074
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001075 injectmask = (pvt->inject.type & 1) |
1076 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001077 (pvt->inject.type & 0x6) << (3 - 1);
1078
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001079 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001080 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001081 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001082
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001083 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001084 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001085 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001086 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1087
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001088 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001089 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1090
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001091 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001092 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001093
1094 /*
1095 * This is something undocumented, based on my tests
1096 * Without writing 8 to this register, errors aren't injected. Not sure
1097 * why.
1098 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001099 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001100 MC_CFG_CONTROL, 8);
1101
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03001102 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1103 " inject 0x%08x\n",
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001104 mask, pvt->inject.eccmask, injectmask);
1105
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001106
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001107 return count;
1108}
1109
1110static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1111 char *data)
1112{
1113 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001114 u32 injectmask;
1115
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -03001116 if (!pvt->pci_ch[pvt->inject.channel][0])
1117 return 0;
1118
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001119 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001120 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001121
1122 debugf0("Inject error read: 0x%018x\n", injectmask);
1123
1124 if (injectmask & 0x0c)
1125 pvt->inject.enable = 1;
1126
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001127 return sprintf(data, "%d\n", pvt->inject.enable);
1128}
1129
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001130#define DECLARE_COUNTER(param) \
1131static ssize_t i7core_show_counter_##param( \
1132 struct mem_ctl_info *mci, \
1133 char *data) \
1134{ \
1135 struct i7core_pvt *pvt = mci->pvt_info; \
1136 \
1137 debugf1("%s() \n", __func__); \
1138 if (!pvt->ce_count_available || (pvt->is_registered)) \
1139 return sprintf(data, "data unavailable\n"); \
1140 return sprintf(data, "%lu\n", \
1141 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001142}
1143
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001144#define ATTR_COUNTER(param) \
1145 { \
1146 .attr = { \
1147 .name = __stringify(udimm##param), \
1148 .mode = (S_IRUGO | S_IWUSR) \
1149 }, \
1150 .show = i7core_show_counter_##param \
1151 }
1152
1153DECLARE_COUNTER(0);
1154DECLARE_COUNTER(1);
1155DECLARE_COUNTER(2);
1156
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001157/*
1158 * Sysfs struct
1159 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001160
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001161static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001162 ATTR_ADDR_MATCH(channel),
1163 ATTR_ADDR_MATCH(dimm),
1164 ATTR_ADDR_MATCH(rank),
1165 ATTR_ADDR_MATCH(bank),
1166 ATTR_ADDR_MATCH(page),
1167 ATTR_ADDR_MATCH(col),
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001168 { } /* End of list */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001169};
1170
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001171static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001172 .name = "inject_addrmatch",
1173 .mcidev_attr = i7core_addrmatch_attrs,
1174};
1175
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001176static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001177 ATTR_COUNTER(0),
1178 ATTR_COUNTER(1),
1179 ATTR_COUNTER(2),
Marcin Slusarz64aab722010-09-30 15:15:30 -07001180 { .attr = { .name = NULL } }
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001181};
1182
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001183static const struct mcidev_sysfs_group i7core_udimm_counters = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001184 .name = "all_channel_counts",
1185 .mcidev_attr = i7core_udimm_counters_attrs,
1186};
1187
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001188static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001189 {
1190 .attr = {
1191 .name = "inject_section",
1192 .mode = (S_IRUGO | S_IWUSR)
1193 },
1194 .show = i7core_inject_section_show,
1195 .store = i7core_inject_section_store,
1196 }, {
1197 .attr = {
1198 .name = "inject_type",
1199 .mode = (S_IRUGO | S_IWUSR)
1200 },
1201 .show = i7core_inject_type_show,
1202 .store = i7core_inject_type_store,
1203 }, {
1204 .attr = {
1205 .name = "inject_eccmask",
1206 .mode = (S_IRUGO | S_IWUSR)
1207 },
1208 .show = i7core_inject_eccmask_show,
1209 .store = i7core_inject_eccmask_store,
1210 }, {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001211 .grp = &i7core_inject_addrmatch,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001212 }, {
1213 .attr = {
1214 .name = "inject_enable",
1215 .mode = (S_IRUGO | S_IWUSR)
1216 },
1217 .show = i7core_inject_enable_show,
1218 .store = i7core_inject_enable_store,
1219 },
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001220 { } /* End of list */
1221};
1222
1223static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1224 {
1225 .attr = {
1226 .name = "inject_section",
1227 .mode = (S_IRUGO | S_IWUSR)
1228 },
1229 .show = i7core_inject_section_show,
1230 .store = i7core_inject_section_store,
1231 }, {
1232 .attr = {
1233 .name = "inject_type",
1234 .mode = (S_IRUGO | S_IWUSR)
1235 },
1236 .show = i7core_inject_type_show,
1237 .store = i7core_inject_type_store,
1238 }, {
1239 .attr = {
1240 .name = "inject_eccmask",
1241 .mode = (S_IRUGO | S_IWUSR)
1242 },
1243 .show = i7core_inject_eccmask_show,
1244 .store = i7core_inject_eccmask_store,
1245 }, {
1246 .grp = &i7core_inject_addrmatch,
1247 }, {
1248 .attr = {
1249 .name = "inject_enable",
1250 .mode = (S_IRUGO | S_IWUSR)
1251 },
1252 .show = i7core_inject_enable_show,
1253 .store = i7core_inject_enable_store,
1254 }, {
1255 .grp = &i7core_udimm_counters,
1256 },
1257 { } /* End of list */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001258};
1259
1260/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001261 Device initialization routines: put/get, init/exit
1262 ****************************************************************************/
1263
1264/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001265 * i7core_put_all_devices 'put' all the devices that we have
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001266 * reserved via 'get'
1267 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001268static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001269{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001270 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001271
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001272 debugf0(__FILE__ ": %s()\n", __func__);
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001273 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001274 struct pci_dev *pdev = i7core_dev->pdev[i];
1275 if (!pdev)
1276 continue;
1277 debugf0("Removing dev %02x:%02x.%d\n",
1278 pdev->bus->number,
1279 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1280 pci_dev_put(pdev);
1281 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001282}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001283
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001284static void i7core_put_all_devices(void)
1285{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001286 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001287
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001288 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001289 i7core_put_devices(i7core_dev);
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -03001290 free_i7core_dev(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001291 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001292}
1293
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001294static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001295{
1296 struct pci_dev *pdev = NULL;
1297 int i;
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03001298
Keith Manntheybc2d7242009-09-03 00:05:05 -03001299 /*
David Sterbae7bf0682010-12-27 16:51:15 +01001300 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
Keith Manntheybc2d7242009-09-03 00:05:05 -03001301 * aren't announced by acpi. So, we need to use a legacy scan probing
1302 * to detect them
1303 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001304 while (table && table->descr) {
1305 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1306 if (unlikely(!pdev)) {
1307 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1308 pcibios_scan_specific_bus(255-i);
1309 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001310 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001311 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001312 }
1313}
1314
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001315static unsigned i7core_pci_lastbus(void)
1316{
1317 int last_bus = 0, bus;
1318 struct pci_bus *b = NULL;
1319
1320 while ((b = pci_find_next_bus(b)) != NULL) {
1321 bus = b->number;
1322 debugf0("Found bus %d\n", bus);
1323 if (bus > last_bus)
1324 last_bus = bus;
1325 }
1326
1327 debugf0("Last bus %d\n", last_bus);
1328
1329 return last_bus;
1330}
1331
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001332/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001333 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001334 * device/functions we want to reference for this driver
1335 *
1336 * Need to 'get' device 16 func 1 and func 2
1337 */
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001338static int i7core_get_onedevice(struct pci_dev **prev,
1339 const struct pci_id_table *table,
1340 const unsigned devno,
1341 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001342{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001343 struct i7core_dev *i7core_dev;
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001344 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001345
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001346 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001347 u8 bus = 0;
1348 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001349
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001350 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001351 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001352
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001353 /*
1354 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1355 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1356 * to probe for the alternate address in case of failure
1357 */
1358 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1359 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1360 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1361
1362 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1363 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1364 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1365 *prev);
1366
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001367 if (!pdev) {
1368 if (*prev) {
1369 *prev = pdev;
1370 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001371 }
1372
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001373 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001374 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001375
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001376 if (devno == 0)
1377 return -ENODEV;
1378
Daniel J Bluemanab089372010-07-23 23:16:52 +01001379 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001380 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001381 dev_descr->dev, dev_descr->func,
1382 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001383
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001384 /* End of list, leave */
1385 return -ENODEV;
1386 }
1387 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001388
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001389 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001390
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001391 i7core_dev = get_i7core_dev(socket);
1392 if (!i7core_dev) {
Hidetoshi Seto848b2f72010-08-20 04:24:44 -03001393 i7core_dev = alloc_i7core_dev(socket, table);
Hidetoshi Seto28966372010-08-20 04:28:51 -03001394 if (!i7core_dev) {
1395 pci_dev_put(pdev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001396 return -ENOMEM;
Hidetoshi Seto28966372010-08-20 04:28:51 -03001397 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001398 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001399
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001400 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001401 i7core_printk(KERN_ERR,
1402 "Duplicated device for "
1403 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001404 bus, dev_descr->dev, dev_descr->func,
1405 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001406 pci_dev_put(pdev);
1407 return -ENODEV;
1408 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001409
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001410 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001411
1412 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001413 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1414 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001415 i7core_printk(KERN_ERR,
1416 "Device PCI ID %04x:%04x "
1417 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001418 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001419 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001420 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001421 return -ENODEV;
1422 }
1423
1424 /* Be sure that the device is enabled */
1425 if (unlikely(pci_enable_device(pdev) < 0)) {
1426 i7core_printk(KERN_ERR,
1427 "Couldn't enable "
1428 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001429 bus, dev_descr->dev, dev_descr->func,
1430 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001431 return -ENODEV;
1432 }
1433
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001434 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001435 socket, bus, dev_descr->dev,
1436 dev_descr->func,
1437 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001438
Mauro Carvalho Chehaba3e15412010-08-21 08:52:41 -03001439 /*
1440 * As stated on drivers/pci/search.c, the reference count for
1441 * @from is always decremented if it is not %NULL. So, as we need
1442 * to get all devices up to null, we need to do a get for the device
1443 */
1444 pci_dev_get(pdev);
1445
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001446 *prev = pdev;
1447
1448 return 0;
1449}
1450
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001451static int i7core_get_all_devices(void)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001452{
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001453 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001454 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001455 const struct pci_id_table *table = pci_dev_table;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001456
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001457 last_bus = i7core_pci_lastbus();
1458
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001459 while (table && table->descr) {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001460 for (i = 0; i < table->n_devs; i++) {
1461 pdev = NULL;
1462 do {
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001463 rc = i7core_get_onedevice(&pdev, table, i,
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001464 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001465 if (rc < 0) {
1466 if (i == 0) {
1467 i = table->n_devs;
1468 break;
1469 }
1470 i7core_put_all_devices();
1471 return -ENODEV;
1472 }
1473 } while (pdev);
1474 }
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001475 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001476 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001477
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001478 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001479}
1480
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001481static int mci_bind_devs(struct mem_ctl_info *mci,
1482 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001483{
1484 struct i7core_pvt *pvt = mci->pvt_info;
1485 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001486 int i, func, slot;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001487 char *family;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001488
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001489 pvt->is_registered = false;
1490 pvt->enable_scrub = false;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001491 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001492 pdev = i7core_dev->pdev[i];
1493 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001494 continue;
1495
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001496 func = PCI_FUNC(pdev->devfn);
1497 slot = PCI_SLOT(pdev->devfn);
1498 if (slot == 3) {
1499 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001500 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001501 pvt->pci_mcr[func] = pdev;
1502 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1503 if (unlikely(func > MAX_CHAN_FUNC))
1504 goto error;
1505 pvt->pci_ch[slot - 4][func] = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001506 } else if (!slot && !func) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001507 pvt->pci_noncore = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001508
1509 /* Detect the processor family */
1510 switch (pdev->device) {
1511 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1512 family = "Xeon 35xx/ i7core";
1513 pvt->enable_scrub = false;
1514 break;
1515 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1516 family = "i7-800/i5-700";
1517 pvt->enable_scrub = false;
1518 break;
1519 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1520 family = "Xeon 34xx";
1521 pvt->enable_scrub = false;
1522 break;
1523 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1524 family = "Xeon 55xx";
1525 pvt->enable_scrub = true;
1526 break;
1527 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1528 family = "Xeon 56xx / i7-900";
1529 pvt->enable_scrub = true;
1530 break;
1531 default:
1532 family = "unknown";
1533 pvt->enable_scrub = false;
1534 }
1535 debugf0("Detected a processor type %s\n", family);
1536 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001537 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001538
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001539 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1540 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1541 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001542
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001543 if (PCI_SLOT(pdev->devfn) == 3 &&
1544 PCI_FUNC(pdev->devfn) == 2)
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001545 pvt->is_registered = true;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001546 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001547
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001548 return 0;
1549
1550error:
1551 i7core_printk(KERN_ERR, "Device %d, function %d "
1552 "is out of the expected range\n",
1553 slot, func);
1554 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001555}
1556
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001557/****************************************************************************
1558 Error check routines
1559 ****************************************************************************/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001560static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001561 const int chan,
1562 const int dimm,
1563 const int add)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001564{
1565 char *msg;
1566 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001567 int row = pvt->csrow_map[chan][dimm], i;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001568
1569 for (i = 0; i < add; i++) {
1570 msg = kasprintf(GFP_KERNEL, "Corrected error "
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001571 "(Socket=%d channel=%d dimm=%d)",
1572 pvt->i7core_dev->socket, chan, dimm);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001573
1574 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1575 kfree (msg);
1576 }
1577}
1578
1579static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001580 const int chan,
1581 const int new0,
1582 const int new1,
1583 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001584{
1585 struct i7core_pvt *pvt = mci->pvt_info;
1586 int add0 = 0, add1 = 0, add2 = 0;
1587 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001588 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001589 /* Updates CE counters */
1590
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001591 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1592 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1593 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001594
1595 if (add2 < 0)
1596 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001597 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001598
1599 if (add1 < 0)
1600 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001601 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001602
1603 if (add0 < 0)
1604 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001605 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001606 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001607 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001608
1609 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001610 pvt->rdimm_last_ce_count[chan][2] = new2;
1611 pvt->rdimm_last_ce_count[chan][1] = new1;
1612 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001613
1614 /*updated the edac core */
1615 if (add0 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001616 i7core_rdimm_update_csrow(mci, chan, 0, add0);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001617 if (add1 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001618 i7core_rdimm_update_csrow(mci, chan, 1, add1);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001619 if (add2 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001620 i7core_rdimm_update_csrow(mci, chan, 2, add2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001621
1622}
1623
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001624static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001625{
1626 struct i7core_pvt *pvt = mci->pvt_info;
1627 u32 rcv[3][2];
1628 int i, new0, new1, new2;
1629
1630 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001631 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001632 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001633 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001634 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001635 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001636 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001637 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001638 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001639 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001640 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001641 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001642 &rcv[2][1]);
1643 for (i = 0 ; i < 3; i++) {
1644 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1645 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1646 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001647 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001648 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1649 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1650 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1651 } else {
1652 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1653 DIMM_BOT_COR_ERR(rcv[i][0]);
1654 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1655 DIMM_BOT_COR_ERR(rcv[i][1]);
1656 new2 = 0;
1657 }
1658
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001659 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001660 }
1661}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001662
1663/* This function is based on the device 3 function 4 registers as described on:
1664 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1665 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1666 * also available at:
1667 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1668 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001669static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001670{
1671 struct i7core_pvt *pvt = mci->pvt_info;
1672 u32 rcv1, rcv0;
1673 int new0, new1, new2;
1674
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001675 if (!pvt->pci_mcr[4]) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001676 debugf0("%s MCR registers not found\n", __func__);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001677 return;
1678 }
1679
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001680 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001681 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1682 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001683
1684 /* Store the new values */
1685 new2 = DIMM2_COR_ERR(rcv1);
1686 new1 = DIMM1_COR_ERR(rcv0);
1687 new0 = DIMM0_COR_ERR(rcv0);
1688
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001689 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001690 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001691 /* Updates CE counters */
1692 int add0, add1, add2;
1693
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001694 add2 = new2 - pvt->udimm_last_ce_count[2];
1695 add1 = new1 - pvt->udimm_last_ce_count[1];
1696 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001697
1698 if (add2 < 0)
1699 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001700 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001701
1702 if (add1 < 0)
1703 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001704 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001705
1706 if (add0 < 0)
1707 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001708 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001709
1710 if (add0 | add1 | add2)
1711 i7core_printk(KERN_ERR, "New Corrected error(s): "
1712 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1713 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001714 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001715 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001716
1717 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001718 pvt->udimm_last_ce_count[2] = new2;
1719 pvt->udimm_last_ce_count[1] = new1;
1720 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001721}
1722
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001723/*
1724 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1725 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001726 * Nehalem are defined as family 0x06, model 0x1a
1727 *
1728 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001729 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001730 * m->status MSR_IA32_MC8_STATUS
1731 * m->addr MSR_IA32_MC8_ADDR
1732 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001733 * In the case of Nehalem, the error information is masked at .status and .misc
1734 * fields
1735 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001736static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001737 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001738{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001739 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001740 char *type, *optype, *err, *msg;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001741 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001742 u32 optypenum = (m->status >> 4) & 0x07;
Mathias Krause8cf2d232011-08-18 09:17:00 +02001743 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001744 u32 dimm = (m->misc >> 16) & 0x3;
1745 u32 channel = (m->misc >> 18) & 0x3;
1746 u32 syndrome = m->misc >> 32;
1747 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001748 int csrow;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001749
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001750 if (m->mcgstatus & 1)
1751 type = "FATAL";
1752 else
1753 type = "NON_FATAL";
1754
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001755 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001756 case 0:
1757 optype = "generic undef request";
1758 break;
1759 case 1:
1760 optype = "read error";
1761 break;
1762 case 2:
1763 optype = "write error";
1764 break;
1765 case 3:
1766 optype = "addr/cmd error";
1767 break;
1768 case 4:
1769 optype = "scrubbing error";
1770 break;
1771 default:
1772 optype = "reserved";
1773 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001774 }
1775
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001776 switch (errnum) {
1777 case 16:
1778 err = "read ECC error";
1779 break;
1780 case 17:
1781 err = "RAS ECC error";
1782 break;
1783 case 18:
1784 err = "write parity error";
1785 break;
1786 case 19:
1787 err = "redundacy loss";
1788 break;
1789 case 20:
1790 err = "reserved";
1791 break;
1792 case 21:
1793 err = "memory range error";
1794 break;
1795 case 22:
1796 err = "RTID out of range";
1797 break;
1798 case 23:
1799 err = "address parity error";
1800 break;
1801 case 24:
1802 err = "byte enable parity error";
1803 break;
1804 default:
1805 err = "unknown";
1806 }
1807
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001808 /* FIXME: should convert addr into bank and rank information */
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001809 msg = kasprintf(GFP_ATOMIC,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001810 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001811 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001812 type, (long long) m->addr, m->cpu, dimm, channel,
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001813 syndrome, core_err_cnt, (long long)m->status,
1814 (long long)m->misc, optype, err);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001815
1816 debugf0("%s", msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001817
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001818 csrow = pvt->csrow_map[channel][dimm];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001819
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001820 /* Call the helper to output message */
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001821 if (m->mcgstatus & 1)
1822 edac_mc_handle_fbd_ue(mci, csrow, 0,
1823 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001824 else if (!pvt->is_registered)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001825 edac_mc_handle_fbd_ce(mci, csrow,
1826 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001827
1828 kfree(msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001829}
1830
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001831/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001832 * i7core_check_error Retrieve and process errors reported by the
1833 * hardware. Called by the Core module.
1834 */
1835static void i7core_check_error(struct mem_ctl_info *mci)
1836{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001837 struct i7core_pvt *pvt = mci->pvt_info;
1838 int i;
1839 unsigned count = 0;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001840 struct mce *m;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001841
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001842 /*
1843 * MCE first step: Copy all mce errors into a temporary buffer
1844 * We use a double buffering here, to reduce the risk of
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001845 * losing an error.
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001846 */
1847 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001848 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1849 % MCE_LOG_LEN;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001850 if (!count)
Vernon Mauery8a311e12010-04-16 19:40:19 -03001851 goto check_ce_error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001852
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001853 m = pvt->mce_outentry;
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001854 if (pvt->mce_in + count > MCE_LOG_LEN) {
1855 unsigned l = MCE_LOG_LEN - pvt->mce_in;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001856
1857 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1858 smp_wmb();
1859 pvt->mce_in = 0;
1860 count -= l;
1861 m += l;
1862 }
1863 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1864 smp_wmb();
1865 pvt->mce_in += count;
1866
1867 smp_rmb();
1868 if (pvt->mce_overrun) {
1869 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1870 pvt->mce_overrun);
1871 smp_wmb();
1872 pvt->mce_overrun = 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001873 }
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001874
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001875 /*
1876 * MCE second step: parse errors and display
1877 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001878 for (i = 0; i < count; i++)
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001879 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001880
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001881 /*
1882 * Now, let's increment CE error counts
1883 */
Vernon Mauery8a311e12010-04-16 19:40:19 -03001884check_ce_error:
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001885 if (!pvt->is_registered)
1886 i7core_udimm_check_mc_ecc_err(mci);
1887 else
1888 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001889}
1890
1891/*
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001892 * i7core_mce_check_error Replicates mcelog routine to get errors
1893 * This routine simply queues mcelog errors, and
1894 * return. The error itself should be handled later
1895 * by i7core_check_error.
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001896 * WARNING: As this routine should be called at NMI time, extra care should
1897 * be taken to avoid deadlocks, and to be as fast as possible.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001898 */
Borislav Petkov4140c542011-07-18 11:24:46 -03001899static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1900 void *data)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001901{
Borislav Petkov4140c542011-07-18 11:24:46 -03001902 struct mce *mce = (struct mce *)data;
1903 struct i7core_dev *i7_dev;
1904 struct mem_ctl_info *mci;
1905 struct i7core_pvt *pvt;
1906
1907 i7_dev = get_i7core_dev(mce->socketid);
1908 if (!i7_dev)
1909 return NOTIFY_BAD;
1910
1911 mci = i7_dev->mci;
1912 pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001913
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001914 /*
1915 * Just let mcelog handle it if the error is
1916 * outside the memory controller
1917 */
1918 if (((mce->status & 0xffff) >> 7) != 1)
Borislav Petkov4140c542011-07-18 11:24:46 -03001919 return NOTIFY_DONE;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001920
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001921 /* Bank 8 registers are the only ones that we know how to handle */
1922 if (mce->bank != 8)
Borislav Petkov4140c542011-07-18 11:24:46 -03001923 return NOTIFY_DONE;
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001924
Randy Dunlap3b918c12009-11-08 01:36:40 -02001925#ifdef CONFIG_SMP
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001926 /* Only handle if it is the right mc controller */
Thomas Renninger50340862011-06-22 05:40:06 -03001927 if (mce->socketid != pvt->i7core_dev->socket)
Borislav Petkov4140c542011-07-18 11:24:46 -03001928 return NOTIFY_DONE;
Randy Dunlap3b918c12009-11-08 01:36:40 -02001929#endif
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001930
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001931 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001932 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001933 smp_wmb();
1934 pvt->mce_overrun++;
Borislav Petkov4140c542011-07-18 11:24:46 -03001935 return NOTIFY_DONE;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001936 }
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001937
1938 /* Copy memory error at the ringbuffer */
1939 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001940 smp_wmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001941 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001942
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001943 /* Handle fatal errors immediately */
1944 if (mce->mcgstatus & 1)
1945 i7core_check_error(mci);
1946
David Sterbae7bf0682010-12-27 16:51:15 +01001947 /* Advise mcelog that the errors were handled */
Borislav Petkov4140c542011-07-18 11:24:46 -03001948 return NOTIFY_STOP;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001949}
1950
Borislav Petkov4140c542011-07-18 11:24:46 -03001951static struct notifier_block i7_mce_dec = {
1952 .notifier_call = i7core_mce_check_error,
1953};
1954
Nils Carlson535e9c72011-08-08 06:21:26 -03001955struct memdev_dmi_entry {
1956 u8 type;
1957 u8 length;
1958 u16 handle;
1959 u16 phys_mem_array_handle;
1960 u16 mem_err_info_handle;
1961 u16 total_width;
1962 u16 data_width;
1963 u16 size;
1964 u8 form;
1965 u8 device_set;
1966 u8 device_locator;
1967 u8 bank_locator;
1968 u8 memory_type;
1969 u16 type_detail;
1970 u16 speed;
1971 u8 manufacturer;
1972 u8 serial_number;
1973 u8 asset_tag;
1974 u8 part_number;
1975 u8 attributes;
1976 u32 extended_size;
1977 u16 conf_mem_clk_speed;
1978} __attribute__((__packed__));
1979
1980
1981/*
1982 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1983 * memory devices show the same speed, and if they don't then consider
1984 * all speeds to be invalid.
1985 */
1986static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1987{
1988 int *dclk_freq = _dclk_freq;
1989 u16 dmi_mem_clk_speed;
1990
1991 if (*dclk_freq == -1)
1992 return;
1993
1994 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1995 struct memdev_dmi_entry *memdev_dmi_entry =
1996 (struct memdev_dmi_entry *)dh;
1997 unsigned long conf_mem_clk_speed_offset =
1998 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1999 (unsigned long)&memdev_dmi_entry->type;
2000 unsigned long speed_offset =
2001 (unsigned long)&memdev_dmi_entry->speed -
2002 (unsigned long)&memdev_dmi_entry->type;
2003
2004 /* Check that a DIMM is present */
2005 if (memdev_dmi_entry->size == 0)
2006 return;
2007
2008 /*
2009 * Pick the configured speed if it's available, otherwise
2010 * pick the DIMM speed, or we don't have a speed.
2011 */
2012 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
2013 dmi_mem_clk_speed =
2014 memdev_dmi_entry->conf_mem_clk_speed;
2015 } else if (memdev_dmi_entry->length > speed_offset) {
2016 dmi_mem_clk_speed = memdev_dmi_entry->speed;
2017 } else {
2018 *dclk_freq = -1;
2019 return;
2020 }
2021
2022 if (*dclk_freq == 0) {
2023 /* First pass, speed was 0 */
2024 if (dmi_mem_clk_speed > 0) {
2025 /* Set speed if a valid speed is read */
2026 *dclk_freq = dmi_mem_clk_speed;
2027 } else {
2028 /* Otherwise we don't have a valid speed */
2029 *dclk_freq = -1;
2030 }
2031 } else if (*dclk_freq > 0 &&
2032 *dclk_freq != dmi_mem_clk_speed) {
2033 /*
2034 * If we have a speed, check that all DIMMS are the same
2035 * speed, otherwise set the speed as invalid.
2036 */
2037 *dclk_freq = -1;
2038 }
2039 }
2040}
2041
2042/*
2043 * The default DCLK frequency is used as a fallback if we
2044 * fail to find anything reliable in the DMI. The value
2045 * is taken straight from the datasheet.
2046 */
2047#define DEFAULT_DCLK_FREQ 800
2048
2049static int get_dclk_freq(void)
2050{
2051 int dclk_freq = 0;
2052
2053 dmi_walk(decode_dclk, (void *)&dclk_freq);
2054
2055 if (dclk_freq < 1)
2056 return DEFAULT_DCLK_FREQ;
2057
2058 return dclk_freq;
2059}
2060
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002061/*
2062 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
2063 * to hardware according to SCRUBINTERVAL formula
2064 * found in datasheet.
2065 */
2066static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
2067{
2068 struct i7core_pvt *pvt = mci->pvt_info;
2069 struct pci_dev *pdev;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002070 u32 dw_scrub;
2071 u32 dw_ssr;
2072
2073 /* Get data from the MC register, function 2 */
2074 pdev = pvt->pci_mcr[2];
2075 if (!pdev)
2076 return -ENODEV;
2077
2078 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
2079
2080 if (new_bw == 0) {
2081 /* Prepare to disable petrol scrub */
2082 dw_scrub &= ~STARTSCRUB;
2083 /* Stop the patrol scrub engine */
Nils Carlson535e9c72011-08-08 06:21:26 -03002084 write_and_test(pdev, MC_SCRUB_CONTROL,
2085 dw_scrub & ~SCRUBINTERVAL_MASK);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002086
2087 /* Get current status of scrub rate and set bit to disable */
2088 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2089 dw_ssr &= ~SSR_MODE_MASK;
2090 dw_ssr |= SSR_MODE_DISABLE;
2091 } else {
Nils Carlson535e9c72011-08-08 06:21:26 -03002092 const int cache_line_size = 64;
2093 const u32 freq_dclk_mhz = pvt->dclk_freq;
2094 unsigned long long scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002095 /*
2096 * Translate the desired scrub rate to a register value and
Nils Carlson535e9c72011-08-08 06:21:26 -03002097 * program the corresponding register value.
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002098 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002099 scrub_interval = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002100 cache_line_size * 1000000;
2101 do_div(scrub_interval, new_bw);
Nils Carlson535e9c72011-08-08 06:21:26 -03002102
2103 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
2104 return -EINVAL;
2105
2106 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002107
2108 /* Start the patrol scrub engine */
2109 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2110 STARTSCRUB | dw_scrub);
2111
2112 /* Get current status of scrub rate and set bit to enable */
2113 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2114 dw_ssr &= ~SSR_MODE_MASK;
2115 dw_ssr |= SSR_MODE_ENABLE;
2116 }
2117 /* Disable or enable scrubbing */
2118 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2119
2120 return new_bw;
2121}
2122
2123/*
2124 * get_sdram_scrub_rate This routine convert current scrub rate value
2125 * into byte/sec bandwidth accourding to
2126 * SCRUBINTERVAL formula found in datasheet.
2127 */
2128static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2129{
2130 struct i7core_pvt *pvt = mci->pvt_info;
2131 struct pci_dev *pdev;
2132 const u32 cache_line_size = 64;
Nils Carlson535e9c72011-08-08 06:21:26 -03002133 const u32 freq_dclk_mhz = pvt->dclk_freq;
2134 unsigned long long scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002135 u32 scrubval;
2136
2137 /* Get data from the MC register, function 2 */
2138 pdev = pvt->pci_mcr[2];
2139 if (!pdev)
2140 return -ENODEV;
2141
2142 /* Get current scrub control data */
2143 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2144
2145 /* Mask highest 8-bits to 0 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002146 scrubval &= SCRUBINTERVAL_MASK;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002147 if (!scrubval)
2148 return 0;
2149
2150 /* Calculate scrub rate value into byte/sec bandwidth */
Nils Carlson535e9c72011-08-08 06:21:26 -03002151 scrub_rate = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002152 1000000 * cache_line_size;
2153 do_div(scrub_rate, scrubval);
Nils Carlson535e9c72011-08-08 06:21:26 -03002154 return (int)scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002155}
2156
2157static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2158{
2159 struct i7core_pvt *pvt = mci->pvt_info;
2160 u32 pci_lock;
2161
2162 /* Unlock writes to pci registers */
2163 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2164 pci_lock &= ~0x3;
2165 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2166 pci_lock | MC_CFG_UNLOCK);
2167
2168 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2169 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2170}
2171
2172static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2173{
2174 struct i7core_pvt *pvt = mci->pvt_info;
2175 u32 pci_lock;
2176
2177 /* Lock writes to pci registers */
2178 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2179 pci_lock &= ~0x3;
2180 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2181 pci_lock | MC_CFG_LOCK);
2182}
2183
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002184static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2185{
2186 pvt->i7core_pci = edac_pci_create_generic_ctl(
2187 &pvt->i7core_dev->pdev[0]->dev,
2188 EDAC_MOD_STR);
2189 if (unlikely(!pvt->i7core_pci))
Mauro Carvalho Chehabf9902f22010-08-21 09:42:05 -03002190 i7core_printk(KERN_WARNING,
2191 "Unable to setup PCI error report via EDAC\n");
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002192}
2193
2194static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2195{
2196 if (likely(pvt->i7core_pci))
2197 edac_pci_release_generic_ctl(pvt->i7core_pci);
2198 else
2199 i7core_printk(KERN_ERR,
2200 "Couldn't find mem_ctl_info for socket %d\n",
2201 pvt->i7core_dev->socket);
2202 pvt->i7core_pci = NULL;
2203}
2204
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002205static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2206{
2207 struct mem_ctl_info *mci = i7core_dev->mci;
2208 struct i7core_pvt *pvt;
2209
2210 if (unlikely(!mci || !mci->pvt_info)) {
2211 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2212 __func__, &i7core_dev->pdev[0]->dev);
2213
2214 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2215 return;
2216 }
2217
2218 pvt = mci->pvt_info;
2219
2220 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2221 __func__, mci, &i7core_dev->pdev[0]->dev);
2222
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002223 /* Disable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002224 if (pvt->enable_scrub)
2225 disable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002226
Borislav Petkov3653ada2011-12-04 15:12:09 +01002227 mce_unregister_decode_chain(&i7_mce_dec);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002228
2229 /* Disable EDAC polling */
2230 i7core_pci_ctl_release(pvt);
2231
2232 /* Remove MC sysfs nodes */
2233 edac_mc_del_mc(mci->dev);
2234
2235 debugf1("%s: free mci struct\n", mci->ctl_name);
2236 kfree(mci->ctl_name);
2237 edac_mc_free(mci);
2238 i7core_dev->mci = NULL;
2239}
2240
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002241static int i7core_register_mci(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002242{
2243 struct mem_ctl_info *mci;
2244 struct i7core_pvt *pvt;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002245 int rc, channels, csrows;
2246
2247 /* Check the number of active and not disabled channels */
2248 rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
2249 if (unlikely(rc < 0))
2250 return rc;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002251
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002252 /* allocate a new MC control structure */
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002253 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002254 if (unlikely(!mci))
2255 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002256
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03002257 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2258 __func__, mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002259
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002260 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002261 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03002262
Mauro Carvalho Chehab6d37d242010-08-20 12:48:26 -03002263 /* Associates i7core_dev and mci for future usage */
2264 pvt->i7core_dev = i7core_dev;
2265 i7core_dev->mci = mci;
2266
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002267 /*
2268 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2269 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2270 * memory channels
2271 */
2272 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002273 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2274 mci->edac_cap = EDAC_FLAG_NONE;
2275 mci->mod_name = "i7core_edac.c";
2276 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002277 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2278 i7core_dev->socket);
2279 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002280 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03002281
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002282 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002283 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002284 if (unlikely(rc < 0))
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002285 goto fail0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002286
Hidetoshi Seto59398132010-08-20 04:28:25 -03002287 if (pvt->is_registered)
2288 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
2289 else
2290 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
2291
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002292 /* Get dimm basic config */
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -03002293 get_dimm_config(mci);
Hidetoshi Seto59398132010-08-20 04:28:25 -03002294 /* record ptr to the generic device */
2295 mci->dev = &i7core_dev->pdev[0]->dev;
2296 /* Set the function pointer to an actual operation function */
2297 mci->edac_check = i7core_check_error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002298
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002299 /* Enable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002300 if (pvt->enable_scrub)
2301 enable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002302
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002303 /* add this new MC control structure to EDAC's list of MCs */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002304 if (unlikely(edac_mc_add_mc(mci))) {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002305 debugf0("MC: " __FILE__
2306 ": %s(): failed edac_mc_add_mc()\n", __func__);
2307 /* FIXME: perhaps some code should go here that disables error
2308 * reporting if we just enabled it
2309 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002310
2311 rc = -EINVAL;
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002312 goto fail0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002313 }
2314
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002315 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002316 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002317 pvt->inject.dimm = -1;
2318 pvt->inject.rank = -1;
2319 pvt->inject.bank = -1;
2320 pvt->inject.page = -1;
2321 pvt->inject.col = -1;
2322
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002323 /* allocating generic PCI control info */
2324 i7core_pci_ctl_create(pvt);
2325
Nils Carlson535e9c72011-08-08 06:21:26 -03002326 /* DCLK for scrub rate setting */
2327 pvt->dclk_freq = get_dclk_freq();
2328
Borislav Petkov3653ada2011-12-04 15:12:09 +01002329 mce_register_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002330
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002331 return 0;
2332
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002333fail0:
2334 kfree(mci->ctl_name);
2335 edac_mc_free(mci);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002336 i7core_dev->mci = NULL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002337 return rc;
2338}
2339
2340/*
2341 * i7core_probe Probe for ONE instance of device to see if it is
2342 * present.
2343 * return:
2344 * 0 for FOUND a device
2345 * < 0 for error code
2346 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002347
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002348static int __devinit i7core_probe(struct pci_dev *pdev,
2349 const struct pci_device_id *id)
2350{
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002351 int rc, count = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002352 struct i7core_dev *i7core_dev;
2353
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002354 /* get the pci devices we want to reserve for our use */
2355 mutex_lock(&i7core_edac_lock);
2356
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002357 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002358 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002359 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002360 if (unlikely(probed >= 1)) {
2361 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehab76a7bd82010-10-24 11:36:19 -02002362 return -ENODEV;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002363 }
2364 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002365
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002366 rc = i7core_get_all_devices();
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002367 if (unlikely(rc < 0))
2368 goto fail0;
2369
2370 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002371 count++;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002372 rc = i7core_register_mci(i7core_dev);
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002373 if (unlikely(rc < 0))
2374 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002375 }
2376
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002377 /*
2378 * Nehalem-EX uses a different memory controller. However, as the
2379 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2380 * need to indirectly probe via a X58 PCI device. The same devices
2381 * are found on (some) Nehalem-EX. So, on those machines, the
2382 * probe routine needs to return -ENODEV, as the actual Memory
2383 * Controller registers won't be detected.
2384 */
2385 if (!count) {
2386 rc = -ENODEV;
2387 goto fail1;
2388 }
2389
2390 i7core_printk(KERN_INFO,
2391 "Driver loaded, %d memory controller(s) found.\n",
2392 count);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002393
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002394 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002395 return 0;
2396
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002397fail1:
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002398 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2399 i7core_unregister_mci(i7core_dev);
2400
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002401 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002402fail0:
2403 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002404 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002405}
2406
2407/*
2408 * i7core_remove destructor for one instance of device
2409 *
2410 */
2411static void __devexit i7core_remove(struct pci_dev *pdev)
2412{
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002413 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002414
2415 debugf0(__FILE__ ": %s()\n", __func__);
2416
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002417 /*
2418 * we have a trouble here: pdev value for removal will be wrong, since
2419 * it will point to the X58 register used to detect that the machine
2420 * is a Nehalem or upper design. However, due to the way several PCI
2421 * devices are grouped together to provide MC functionality, we need
2422 * to use a different method for releasing the devices
2423 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002424
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002425 mutex_lock(&i7core_edac_lock);
Hidetoshi Seto71fe0172010-08-20 04:29:47 -03002426
2427 if (unlikely(!probed)) {
2428 mutex_unlock(&i7core_edac_lock);
2429 return;
2430 }
2431
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002432 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2433 i7core_unregister_mci(i7core_dev);
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002434
2435 /* Release PCI resources */
2436 i7core_put_all_devices();
2437
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002438 probed--;
2439
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002440 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002441}
2442
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002443MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2444
2445/*
2446 * i7core_driver pci_driver structure for this module
2447 *
2448 */
2449static struct pci_driver i7core_driver = {
2450 .name = "i7core_edac",
2451 .probe = i7core_probe,
2452 .remove = __devexit_p(i7core_remove),
2453 .id_table = i7core_pci_tbl,
2454};
2455
2456/*
2457 * i7core_init Module entry function
2458 * Try to initialize this module for its devices
2459 */
2460static int __init i7core_init(void)
2461{
2462 int pci_rc;
2463
2464 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2465
2466 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2467 opstate_init();
2468
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03002469 if (use_pci_fixup)
2470 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002471
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002472 pci_rc = pci_register_driver(&i7core_driver);
2473
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002474 if (pci_rc >= 0)
2475 return 0;
2476
2477 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2478 pci_rc);
2479
2480 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002481}
2482
2483/*
2484 * i7core_exit() Module exit function
2485 * Unregister the driver
2486 */
2487static void __exit i7core_exit(void)
2488{
2489 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2490 pci_unregister_driver(&i7core_driver);
2491}
2492
2493module_init(i7core_init);
2494module_exit(i7core_exit);
2495
2496MODULE_LICENSE("GPL");
2497MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2498MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2499MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2500 I7CORE_REVISION);
2501
2502module_param(edac_op_state, int, 0444);
2503MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");