blob: 20847a2fc4dc61bc1890c3f5be154d0baaa87761 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
36#include <linux/i2c.h>
37#include <linux/i2c-id.h>
38#include <linux/i2c-algo-bit.h>
Jerome Glissec93bb852009-07-13 21:04:08 +020039#include "radeon_fixed.h"
40
41struct radeon_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020042
43#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
44#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
45#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
46#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
47
48enum radeon_connector_type {
49 CONNECTOR_NONE,
50 CONNECTOR_VGA,
51 CONNECTOR_DVI_I,
52 CONNECTOR_DVI_D,
53 CONNECTOR_DVI_A,
54 CONNECTOR_STV,
55 CONNECTOR_CTV,
56 CONNECTOR_LVDS,
57 CONNECTOR_DIGITAL,
58 CONNECTOR_SCART,
59 CONNECTOR_HDMI_TYPE_A,
60 CONNECTOR_HDMI_TYPE_B,
61 CONNECTOR_0XC,
62 CONNECTOR_0XD,
63 CONNECTOR_DIN,
64 CONNECTOR_DISPLAY_PORT,
65 CONNECTOR_UNSUPPORTED
66};
67
68enum radeon_dvi_type {
69 DVI_AUTO,
70 DVI_DIGITAL,
71 DVI_ANALOG
72};
73
74enum radeon_rmx_type {
75 RMX_OFF,
76 RMX_FULL,
77 RMX_CENTER,
78 RMX_ASPECT
79};
80
81enum radeon_tv_std {
82 TV_STD_NTSC,
83 TV_STD_PAL,
84 TV_STD_PAL_M,
85 TV_STD_PAL_60,
86 TV_STD_NTSC_J,
87 TV_STD_SCART_PAL,
88 TV_STD_SECAM,
89 TV_STD_PAL_CN,
90};
91
Alex Deucher9b9fe722009-11-10 15:59:44 -050092/* radeon gpio-based i2c
93 * 1. "mask" reg and bits
94 * grabs the gpio pins for software use
95 * 0=not held 1=held
96 * 2. "a" reg and bits
97 * output pin value
98 * 0=low 1=high
99 * 3. "en" reg and bits
100 * sets the pin direction
101 * 0=input 1=output
102 * 4. "y" reg and bits
103 * input pin value
104 * 0=low 1=high
105 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200106struct radeon_i2c_bus_rec {
107 bool valid;
108 uint32_t mask_clk_reg;
109 uint32_t mask_data_reg;
110 uint32_t a_clk_reg;
111 uint32_t a_data_reg;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500112 uint32_t en_clk_reg;
113 uint32_t en_data_reg;
114 uint32_t y_clk_reg;
115 uint32_t y_data_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200116 uint32_t mask_clk_mask;
117 uint32_t mask_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200118 uint32_t a_clk_mask;
119 uint32_t a_data_mask;
Alex Deucher9b9fe722009-11-10 15:59:44 -0500120 uint32_t en_clk_mask;
121 uint32_t en_data_mask;
122 uint32_t y_clk_mask;
123 uint32_t y_data_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200124};
125
126struct radeon_tmds_pll {
127 uint32_t freq;
128 uint32_t value;
129};
130
131#define RADEON_MAX_BIOS_CONNECTOR 16
132
133#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
134#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
135#define RADEON_PLL_USE_REF_DIV (1 << 2)
136#define RADEON_PLL_LEGACY (1 << 3)
137#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
138#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
139#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
140#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
141#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
142#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
143#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
Alex Deucherd0e275a2009-07-13 11:08:18 -0400144#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145
146struct radeon_pll {
147 uint16_t reference_freq;
148 uint16_t reference_div;
149 uint32_t pll_in_min;
150 uint32_t pll_in_max;
151 uint32_t pll_out_min;
152 uint32_t pll_out_max;
153 uint16_t xclk;
154
155 uint32_t min_ref_div;
156 uint32_t max_ref_div;
157 uint32_t min_post_div;
158 uint32_t max_post_div;
159 uint32_t min_feedback_div;
160 uint32_t max_feedback_div;
161 uint32_t min_frac_feedback_div;
162 uint32_t max_frac_feedback_div;
163 uint32_t best_vco;
164};
165
166struct radeon_i2c_chan {
167 struct drm_device *dev;
168 struct i2c_adapter adapter;
169 struct i2c_algo_bit_data algo;
170 struct radeon_i2c_bus_rec rec;
171};
172
173/* mostly for macs, but really any system without connector tables */
174enum radeon_connector_table {
175 CT_NONE,
176 CT_GENERIC,
177 CT_IBOOK,
178 CT_POWERBOOK_EXTERNAL,
179 CT_POWERBOOK_INTERNAL,
180 CT_POWERBOOK_VGA,
181 CT_MINI_EXTERNAL,
182 CT_MINI_INTERNAL,
183 CT_IMAC_G5_ISIGHT,
184 CT_EMAC,
185};
186
187struct radeon_mode_info {
188 struct atom_context *atom_context;
Mathias Fröhlich61c4b242009-10-27 15:08:01 -0400189 struct card_info *atom_card_info;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190 enum radeon_connector_table connector_table;
191 bool mode_config_initialized;
Jerome Glissec93bb852009-07-13 21:04:08 +0200192 struct radeon_crtc *crtcs[2];
Dave Airlie445282d2009-09-09 17:40:54 +1000193 /* DVI-I properties */
194 struct drm_property *coherent_mode_property;
195 /* DAC enable load detect */
196 struct drm_property *load_detect_property;
197 /* TV standard load detect */
198 struct drm_property *tv_std_property;
199 /* legacy TMDS PLL detect */
200 struct drm_property *tmds_pll_property;
201
Jerome Glissec93bb852009-07-13 21:04:08 +0200202};
203
Dave Airlie4ce001a2009-08-13 16:32:14 +1000204#define MAX_H_CODE_TIMING_LEN 32
205#define MAX_V_CODE_TIMING_LEN 32
206
207/* need to store these as reading
208 back code tables is excessive */
209struct radeon_tv_regs {
210 uint32_t tv_uv_adr;
211 uint32_t timing_cntl;
212 uint32_t hrestart;
213 uint32_t vrestart;
214 uint32_t frestart;
215 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
216 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
217};
218
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219struct radeon_crtc {
220 struct drm_crtc base;
221 int crtc_id;
222 u16 lut_r[256], lut_g[256], lut_b[256];
223 bool enabled;
224 bool can_tile;
225 uint32_t crtc_offset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226 struct drm_gem_object *cursor_bo;
227 uint64_t cursor_addr;
228 int cursor_width;
229 int cursor_height;
Dave Airlie41623382009-07-09 15:04:19 +1000230 uint32_t legacy_display_base_addr;
Alex Deucherc836e862009-07-13 13:51:03 -0400231 uint32_t legacy_cursor_offset;
Jerome Glissec93bb852009-07-13 21:04:08 +0200232 enum radeon_rmx_type rmx_type;
Jerome Glissec93bb852009-07-13 21:04:08 +0200233 fixed20_12 vsc;
234 fixed20_12 hsc;
Alex Deucherde2103e2009-10-09 15:14:30 -0400235 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200236};
237
238struct radeon_encoder_primary_dac {
239 /* legacy primary dac */
240 uint32_t ps2_pdac_adj;
241};
242
243struct radeon_encoder_lvds {
244 /* legacy lvds */
245 uint16_t panel_vcc_delay;
246 uint8_t panel_pwr_delay;
247 uint8_t panel_digon_delay;
248 uint8_t panel_blon_delay;
249 uint16_t panel_ref_divider;
250 uint8_t panel_post_divider;
251 uint16_t panel_fb_divider;
252 bool use_bios_dividers;
253 uint32_t lvds_gen_cntl;
254 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400255 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256};
257
258struct radeon_encoder_tv_dac {
259 /* legacy tv dac */
260 uint32_t ps2_tvdac_adj;
261 uint32_t ntsc_tvdac_adj;
262 uint32_t pal_tvdac_adj;
263
Dave Airlie4ce001a2009-08-13 16:32:14 +1000264 int h_pos;
265 int v_pos;
266 int h_size;
267 int supported_tv_stds;
268 bool tv_on;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269 enum radeon_tv_std tv_std;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000270 struct radeon_tv_regs tv;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200271};
272
273struct radeon_encoder_int_tmds {
274 /* legacy int tmds */
275 struct radeon_tmds_pll tmds_pll[4];
276};
277
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400278/* spread spectrum */
279struct radeon_atom_ss {
280 uint16_t percentage;
281 uint8_t type;
282 uint8_t step;
283 uint8_t delay;
284 uint8_t range;
285 uint8_t refdiv;
286};
287
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200288struct radeon_encoder_atom_dig {
289 /* atom dig */
290 bool coherent_mode;
291 int dig_block;
292 /* atom lvds */
293 uint32_t lvds_misc;
294 uint16_t panel_pwr_delay;
Alex Deucherebbe1cb2009-10-16 11:15:25 -0400295 struct radeon_atom_ss *ss;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200296 /* panel mode */
Alex Deucherde2103e2009-10-09 15:14:30 -0400297 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200298};
299
Dave Airlie4ce001a2009-08-13 16:32:14 +1000300struct radeon_encoder_atom_dac {
301 enum radeon_tv_std tv_std;
302};
303
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200304struct radeon_encoder {
305 struct drm_encoder base;
306 uint32_t encoder_id;
307 uint32_t devices;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000308 uint32_t active_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200309 uint32_t flags;
310 uint32_t pixel_clock;
311 enum radeon_rmx_type rmx_type;
Alex Deucherde2103e2009-10-09 15:14:30 -0400312 struct drm_display_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200313 void *enc_priv;
314};
315
316struct radeon_connector_atom_dig {
317 uint32_t igp_lane_info;
318 bool linkb;
319};
320
321struct radeon_connector {
322 struct drm_connector base;
323 uint32_t connector_id;
324 uint32_t devices;
325 struct radeon_i2c_chan *ddc_bus;
Alex Deucher0294cf4f2009-10-15 16:16:35 -0400326 /* some systems have a an hdmi and vga port with a shared ddc line */
327 bool shared_ddc;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000328 bool use_digital;
329 /* we need to mind the EDID between detect
330 and get modes due to analog/digital/tvencoder */
331 struct edid *edid;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 void *con_priv;
Dave Airlie445282d2009-09-09 17:40:54 +1000333 bool dac_load_detect;
Alex Deucherb75fad02009-11-05 13:16:01 -0500334 uint16_t connector_object_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200335};
336
337struct radeon_framebuffer {
338 struct drm_framebuffer base;
339 struct drm_gem_object *obj;
340};
341
342extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
343 struct radeon_i2c_bus_rec *rec,
344 const char *name);
345extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
346extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
347extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
348
349extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
350
351extern void radeon_compute_pll(struct radeon_pll *pll,
352 uint64_t freq,
353 uint32_t *dot_clock_p,
354 uint32_t *fb_div_p,
355 uint32_t *frac_fb_div_p,
356 uint32_t *ref_div_p,
357 uint32_t *post_div_p,
358 int flags);
359
360struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
361struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
362struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
363struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
364struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
365extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
366extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000367extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200368
369extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
370extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
371 struct drm_framebuffer *old_fb);
372extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
373 struct drm_display_mode *mode,
374 struct drm_display_mode *adjusted_mode,
375 int x, int y,
376 struct drm_framebuffer *old_fb);
377extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
378
379extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
380 struct drm_framebuffer *old_fb);
381extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
382
383extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
384 struct drm_file *file_priv,
385 uint32_t handle,
386 uint32_t width,
387 uint32_t height);
388extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
389 int x, int y);
390
391extern bool radeon_atom_get_clock_info(struct drm_device *dev);
392extern bool radeon_combios_get_clock_info(struct drm_device *dev);
393extern struct radeon_encoder_atom_dig *
394radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
Dave Airlie445282d2009-09-09 17:40:54 +1000395bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
396 struct radeon_encoder_int_tmds *tmds);
397bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
398 struct radeon_encoder_int_tmds *tmds);
399bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
400 struct radeon_encoder_int_tmds *tmds);
Alex Deucher6fe7ac32009-06-12 17:26:08 +0000401extern struct radeon_encoder_primary_dac *
402radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
403extern struct radeon_encoder_tv_dac *
404radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200405extern struct radeon_encoder_lvds *
406radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200407extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
408extern struct radeon_encoder_tv_dac *
409radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
410extern struct radeon_encoder_primary_dac *
411radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
412extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
413extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
414extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
415extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
Yang Zhaof657c2a2009-09-15 12:21:01 +1000416extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
417extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200418extern void
419radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
420extern void
421radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
422extern void
423radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
424extern void
425radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
426extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
427 u16 blue, int regno);
Dave Airlieb8c00ac2009-10-06 13:54:01 +1000428extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
429 u16 *blue, int regno);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200430struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
431 struct drm_mode_fb_cmd *mode_cmd,
432 struct drm_gem_object *obj);
433
434int radeonfb_probe(struct drm_device *dev);
435
436int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
437bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
438bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
439void radeon_atombios_init_crtc(struct drm_device *dev,
440 struct radeon_crtc *radeon_crtc);
441void radeon_legacy_init_crtc(struct drm_device *dev,
442 struct radeon_crtc *radeon_crtc);
Alex Deucherab1e9ea2009-11-05 18:27:30 -0500443extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200444
445void radeon_get_clock_info(struct drm_device *dev);
446
447extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
448extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
449
450void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
451 struct drm_display_mode *mode,
452 struct drm_display_mode *adjusted_mode);
453void radeon_enc_destroy(struct drm_encoder *encoder);
454void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
455void radeon_combios_asic_init(struct drm_device *dev);
456extern int radeon_static_clocks_init(struct drm_device *dev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200457bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
458 struct drm_display_mode *mode,
459 struct drm_display_mode *adjusted_mode);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000460void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200461
Dave Airlie4ce001a2009-08-13 16:32:14 +1000462/* legacy tv */
463void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
464 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
465 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
466void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
467 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
468 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
469void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
470 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
471 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
472void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
473 struct drm_display_mode *mode,
474 struct drm_display_mode *adjusted_mode);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200475#endif