blob: 38c1dd082441ebd8771f3bc03076e3e078c7f635 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
36#include <linux/i2c.h>
37#include <linux/i2c-id.h>
38#include <linux/i2c-algo-bit.h>
39
40#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
41#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
42#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
43#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
44
45enum radeon_connector_type {
46 CONNECTOR_NONE,
47 CONNECTOR_VGA,
48 CONNECTOR_DVI_I,
49 CONNECTOR_DVI_D,
50 CONNECTOR_DVI_A,
51 CONNECTOR_STV,
52 CONNECTOR_CTV,
53 CONNECTOR_LVDS,
54 CONNECTOR_DIGITAL,
55 CONNECTOR_SCART,
56 CONNECTOR_HDMI_TYPE_A,
57 CONNECTOR_HDMI_TYPE_B,
58 CONNECTOR_0XC,
59 CONNECTOR_0XD,
60 CONNECTOR_DIN,
61 CONNECTOR_DISPLAY_PORT,
62 CONNECTOR_UNSUPPORTED
63};
64
65enum radeon_dvi_type {
66 DVI_AUTO,
67 DVI_DIGITAL,
68 DVI_ANALOG
69};
70
71enum radeon_rmx_type {
72 RMX_OFF,
73 RMX_FULL,
74 RMX_CENTER,
75 RMX_ASPECT
76};
77
78enum radeon_tv_std {
79 TV_STD_NTSC,
80 TV_STD_PAL,
81 TV_STD_PAL_M,
82 TV_STD_PAL_60,
83 TV_STD_NTSC_J,
84 TV_STD_SCART_PAL,
85 TV_STD_SECAM,
86 TV_STD_PAL_CN,
87};
88
89struct radeon_i2c_bus_rec {
90 bool valid;
91 uint32_t mask_clk_reg;
92 uint32_t mask_data_reg;
93 uint32_t a_clk_reg;
94 uint32_t a_data_reg;
95 uint32_t put_clk_reg;
96 uint32_t put_data_reg;
97 uint32_t get_clk_reg;
98 uint32_t get_data_reg;
99 uint32_t mask_clk_mask;
100 uint32_t mask_data_mask;
101 uint32_t put_clk_mask;
102 uint32_t put_data_mask;
103 uint32_t get_clk_mask;
104 uint32_t get_data_mask;
105 uint32_t a_clk_mask;
106 uint32_t a_data_mask;
107};
108
109struct radeon_tmds_pll {
110 uint32_t freq;
111 uint32_t value;
112};
113
114#define RADEON_MAX_BIOS_CONNECTOR 16
115
116#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
117#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
118#define RADEON_PLL_USE_REF_DIV (1 << 2)
119#define RADEON_PLL_LEGACY (1 << 3)
120#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
121#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
122#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
123#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
124#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
Alex Deucherd0e275a2009-07-13 11:08:18 -0400127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128
129struct radeon_pll {
130 uint16_t reference_freq;
131 uint16_t reference_div;
132 uint32_t pll_in_min;
133 uint32_t pll_in_max;
134 uint32_t pll_out_min;
135 uint32_t pll_out_max;
136 uint16_t xclk;
137
138 uint32_t min_ref_div;
139 uint32_t max_ref_div;
140 uint32_t min_post_div;
141 uint32_t max_post_div;
142 uint32_t min_feedback_div;
143 uint32_t max_feedback_div;
144 uint32_t min_frac_feedback_div;
145 uint32_t max_frac_feedback_div;
146 uint32_t best_vco;
147};
148
149struct radeon_i2c_chan {
150 struct drm_device *dev;
151 struct i2c_adapter adapter;
152 struct i2c_algo_bit_data algo;
153 struct radeon_i2c_bus_rec rec;
154};
155
156/* mostly for macs, but really any system without connector tables */
157enum radeon_connector_table {
158 CT_NONE,
159 CT_GENERIC,
160 CT_IBOOK,
161 CT_POWERBOOK_EXTERNAL,
162 CT_POWERBOOK_INTERNAL,
163 CT_POWERBOOK_VGA,
164 CT_MINI_EXTERNAL,
165 CT_MINI_INTERNAL,
166 CT_IMAC_G5_ISIGHT,
167 CT_EMAC,
168};
169
170struct radeon_mode_info {
171 struct atom_context *atom_context;
172 enum radeon_connector_table connector_table;
173 bool mode_config_initialized;
174};
175
176struct radeon_crtc {
177 struct drm_crtc base;
178 int crtc_id;
179 u16 lut_r[256], lut_g[256], lut_b[256];
180 bool enabled;
181 bool can_tile;
182 uint32_t crtc_offset;
183 struct radeon_framebuffer *fbdev_fb;
184 struct drm_mode_set mode_set;
185 struct drm_gem_object *cursor_bo;
186 uint64_t cursor_addr;
187 int cursor_width;
188 int cursor_height;
Dave Airlie41623382009-07-09 15:04:19 +1000189 uint32_t legacy_display_base_addr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190};
191
192#define RADEON_USE_RMX 1
193
194struct radeon_native_mode {
195 /* preferred mode */
196 uint32_t panel_xres, panel_yres;
197 uint32_t hoverplus, hsync_width;
198 uint32_t hblank;
199 uint32_t voverplus, vsync_width;
200 uint32_t vblank;
201 uint32_t dotclock;
202 uint32_t flags;
203};
204
205struct radeon_encoder_primary_dac {
206 /* legacy primary dac */
207 uint32_t ps2_pdac_adj;
208};
209
210struct radeon_encoder_lvds {
211 /* legacy lvds */
212 uint16_t panel_vcc_delay;
213 uint8_t panel_pwr_delay;
214 uint8_t panel_digon_delay;
215 uint8_t panel_blon_delay;
216 uint16_t panel_ref_divider;
217 uint8_t panel_post_divider;
218 uint16_t panel_fb_divider;
219 bool use_bios_dividers;
220 uint32_t lvds_gen_cntl;
221 /* panel mode */
222 struct radeon_native_mode native_mode;
223};
224
225struct radeon_encoder_tv_dac {
226 /* legacy tv dac */
227 uint32_t ps2_tvdac_adj;
228 uint32_t ntsc_tvdac_adj;
229 uint32_t pal_tvdac_adj;
230
231 enum radeon_tv_std tv_std;
232};
233
234struct radeon_encoder_int_tmds {
235 /* legacy int tmds */
236 struct radeon_tmds_pll tmds_pll[4];
237};
238
239struct radeon_encoder_atom_dig {
240 /* atom dig */
241 bool coherent_mode;
242 int dig_block;
243 /* atom lvds */
244 uint32_t lvds_misc;
245 uint16_t panel_pwr_delay;
246 /* panel mode */
247 struct radeon_native_mode native_mode;
248};
249
250struct radeon_encoder {
251 struct drm_encoder base;
252 uint32_t encoder_id;
253 uint32_t devices;
254 uint32_t flags;
255 uint32_t pixel_clock;
256 enum radeon_rmx_type rmx_type;
257 struct radeon_native_mode native_mode;
258 void *enc_priv;
259};
260
261struct radeon_connector_atom_dig {
262 uint32_t igp_lane_info;
263 bool linkb;
264};
265
266struct radeon_connector {
267 struct drm_connector base;
268 uint32_t connector_id;
269 uint32_t devices;
270 struct radeon_i2c_chan *ddc_bus;
271 int use_digital;
272 void *con_priv;
273};
274
275struct radeon_framebuffer {
276 struct drm_framebuffer base;
277 struct drm_gem_object *obj;
278};
279
280extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
281 struct radeon_i2c_bus_rec *rec,
282 const char *name);
283extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
284extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
285extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
286
287extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
288
289extern void radeon_compute_pll(struct radeon_pll *pll,
290 uint64_t freq,
291 uint32_t *dot_clock_p,
292 uint32_t *fb_div_p,
293 uint32_t *frac_fb_div_p,
294 uint32_t *ref_div_p,
295 uint32_t *post_div_p,
296 int flags);
297
298struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
299struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
300struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
301struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
302struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
303extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
304extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
305
306extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
307extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
308 struct drm_framebuffer *old_fb);
309extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
310 struct drm_display_mode *mode,
311 struct drm_display_mode *adjusted_mode,
312 int x, int y,
313 struct drm_framebuffer *old_fb);
314extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
315
316extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
317 struct drm_framebuffer *old_fb);
318extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
319
320extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
321 struct drm_file *file_priv,
322 uint32_t handle,
323 uint32_t width,
324 uint32_t height);
325extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
326 int x, int y);
327
328extern bool radeon_atom_get_clock_info(struct drm_device *dev);
329extern bool radeon_combios_get_clock_info(struct drm_device *dev);
330extern struct radeon_encoder_atom_dig *
331radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
332extern struct radeon_encoder_int_tmds *
333radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
Alex Deucher6fe7ac32009-06-12 17:26:08 +0000334extern struct radeon_encoder_primary_dac *
335radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
336extern struct radeon_encoder_tv_dac *
337radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200338extern struct radeon_encoder_lvds *
339radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
340extern struct radeon_encoder_int_tmds *
341radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
342extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
343extern struct radeon_encoder_tv_dac *
344radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
345extern struct radeon_encoder_primary_dac *
346radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
347extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
348extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
349extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
350extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
351extern void
352radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
353extern void
354radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
355extern void
356radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
357extern void
358radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
359extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
360 u16 blue, int regno);
361struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
362 struct drm_mode_fb_cmd *mode_cmd,
363 struct drm_gem_object *obj);
364
365int radeonfb_probe(struct drm_device *dev);
366
367int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
368bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
369bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
370void radeon_atombios_init_crtc(struct drm_device *dev,
371 struct radeon_crtc *radeon_crtc);
372void radeon_legacy_init_crtc(struct drm_device *dev,
373 struct radeon_crtc *radeon_crtc);
374void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
375
376void radeon_get_clock_info(struct drm_device *dev);
377
378extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
379extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
380
381void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
382 struct drm_display_mode *mode,
383 struct drm_display_mode *adjusted_mode);
384void radeon_enc_destroy(struct drm_encoder *encoder);
385void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
386void radeon_combios_asic_init(struct drm_device *dev);
387extern int radeon_static_clocks_init(struct drm_device *dev);
388void radeon_init_disp_bw_legacy(struct drm_device *dev,
389 struct drm_display_mode *mode1,
390 uint32_t pixel_bytes1,
391 struct drm_display_mode *mode2,
392 uint32_t pixel_bytes2);
393void radeon_init_disp_bw_avivo(struct drm_device *dev,
394 struct drm_display_mode *mode1,
395 uint32_t pixel_bytes1,
396 struct drm_display_mode *mode2,
397 uint32_t pixel_bytes2);
398void radeon_init_disp_bandwidth(struct drm_device *dev);
399
400#endif