blob: 1a7a72fb77d6292f9c6fb3576eae7698577ff2ae [file] [log] [blame]
Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
4 *
Michael Büscheb032b92011-07-04 20:50:05 +02005 * Copyright 2009, Michael Buesch <m@bues.ch>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02006 * Copyright 2007, Broadcom Corporation
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
Paul Gortmaker44a8e372011-07-27 21:21:04 -040012#include <linux/export.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020013#include <linux/bcma/bcma.h>
14
Hauke Mehrtens908debc2011-07-23 01:20:11 +020015static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
16{
17 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
18 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
19 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
20}
21
Rafał Miłecki3861b2c2011-09-16 12:33:58 +020022void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020023{
Rafał Miłecki3861b2c2011-09-16 12:33:58 +020024 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
25 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
26 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
27}
28EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020029
Rafał Miłecki3861b2c2011-09-16 12:33:58 +020030void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
31 u32 set)
32{
33 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
34 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
35 bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
36}
37EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
38
39void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
40 u32 offset, u32 mask, u32 set)
41{
Rafał Miłecki8369ae32011-05-09 18:56:46 +020042 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
43 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
Rafał Miłecki3861b2c2011-09-16 12:33:58 +020044 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020045}
Rafał Miłecki3861b2c2011-09-16 12:33:58 +020046EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
47
48void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
49 u32 set)
50{
51 bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
52 bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
53 bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
54}
55EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020056
Rafał Miłecki8369ae32011-05-09 18:56:46 +020057static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
58{
59 struct bcma_bus *bus = cc->core->bus;
60 u32 min_msk = 0, max_msk = 0;
61
62 switch (bus->chipinfo.id) {
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +020063 case BCMA_CHIP_ID_BCM4313:
Rafał Miłecki8369ae32011-05-09 18:56:46 +020064 min_msk = 0x200D;
65 max_msk = 0xFFFF;
66 break;
Rafał Miłecki8369ae32011-05-09 18:56:46 +020067 default:
Hauke Mehrtens6270d1c2012-06-30 01:44:43 +020068 pr_debug("PMU resource config unknown or not needed for device 0x%04X\n",
69 bus->chipinfo.id);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020070 }
71
72 /* Set the resource masks. */
73 if (min_msk)
74 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
75 if (max_msk)
76 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
77}
78
Rafał Miłecki984e5be2011-08-11 23:46:44 +020079/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
80void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
81{
82 struct bcma_bus *bus = cc->core->bus;
83 u32 val;
84
85 val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
86 if (enable) {
87 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
88 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
89 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
Hauke Mehrtens00eeedc2012-06-30 01:44:37 +020090 else if (bus->chipinfo.rev > 0)
91 val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
Rafał Miłecki984e5be2011-08-11 23:46:44 +020092 } else {
93 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
Hauke Mehrtens00eeedc2012-06-30 01:44:37 +020094 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
Rafał Miłecki984e5be2011-08-11 23:46:44 +020095 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
96 }
97 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
98}
99
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200100void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
101{
102 struct bcma_bus *bus = cc->core->bus;
103
104 switch (bus->chipinfo.id) {
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200105 case BCMA_CHIP_ID_BCM4313:
Hauke Mehrtensb9562542012-06-30 01:44:41 +0200106 /* enable 12 mA drive strenth for 4313 and set chipControl
107 register bit 1 */
108 bcma_chipco_chipctl_maskset(cc, 0,
109 BCMA_CCTRL_4313_12MA_LED_DRIVE,
110 BCMA_CCTRL_4313_12MA_LED_DRIVE);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200111 break;
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200112 case BCMA_CHIP_ID_BCM4331:
113 case BCMA_CHIP_ID_BCM43431:
Seth Forshee69aaedd2012-06-01 09:13:17 -0500114 /* Ext PA lines must be enabled for tx on BCM4331 */
115 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200116 break;
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200117 case BCMA_CHIP_ID_BCM43224:
Hauke Mehrtensb9562542012-06-30 01:44:41 +0200118 case BCMA_CHIP_ID_BCM43421:
119 /* enable 12 mA drive strenth for 43224 and set chipControl
120 register bit 15 */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200121 if (bus->chipinfo.rev == 0) {
Hauke Mehrtensb9562542012-06-30 01:44:41 +0200122 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
123 BCMA_CCTRL_43224_GPIO_TOGGLE,
124 BCMA_CCTRL_43224_GPIO_TOGGLE);
125 bcma_chipco_chipctl_maskset(cc, 0,
126 BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
127 BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200128 } else {
Hauke Mehrtensb9562542012-06-30 01:44:41 +0200129 bcma_chipco_chipctl_maskset(cc, 0,
130 BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
131 BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200132 }
133 break;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200134 default:
Hauke Mehrtens6270d1c2012-06-30 01:44:43 +0200135 pr_debug("Workarounds unknown or not needed for device 0x%04X\n",
136 bus->chipinfo.id);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200137 }
138}
139
140void bcma_pmu_init(struct bcma_drv_cc *cc)
141{
142 u32 pmucap;
143
144 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
145 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
146
147 pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
148 pmucap);
149
150 if (cc->pmu.rev == 1)
151 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
152 ~BCMA_CC_PMU_CTL_NOILPONW);
153 else
154 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
155 BCMA_CC_PMU_CTL_NOILPONW);
156
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200157 bcma_pmu_resources_init(cc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200158 bcma_pmu_workarounds(cc);
159}
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200160
161u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
162{
163 struct bcma_bus *bus = cc->core->bus;
164
165 switch (bus->chipinfo.id) {
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200166 case BCMA_CHIP_ID_BCM4716:
167 case BCMA_CHIP_ID_BCM4748:
168 case BCMA_CHIP_ID_BCM47162:
169 case BCMA_CHIP_ID_BCM4313:
170 case BCMA_CHIP_ID_BCM5357:
171 case BCMA_CHIP_ID_BCM4749:
172 case BCMA_CHIP_ID_BCM53572:
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200173 /* always 20Mhz */
174 return 20000 * 1000;
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200175 case BCMA_CHIP_ID_BCM5356:
176 case BCMA_CHIP_ID_BCM4706:
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200177 /* always 25Mhz */
178 return 25000 * 1000;
179 default:
180 pr_warn("No ALP clock specified for %04X device, "
181 "pmu rev. %d, using default %d Hz\n",
182 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
183 }
184 return BCMA_CC_PMU_ALP_CLOCK;
185}
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200186
187/* Find the output of the "m" pll divider given pll controls that start with
188 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
189 */
190static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
191{
192 u32 tmp, div, ndiv, p1, p2, fc;
193 struct bcma_bus *bus = cc->core->bus;
194
195 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
196
197 BUG_ON(!m || m > 4);
198
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200199 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
200 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200201 /* Detect failure in clock setting */
202 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
203 if (tmp & 0x40000)
204 return 133 * 1000000;
205 }
206
207 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
208 p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
209 p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
210
211 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
212 div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
213 BCMA_CC_PPL_MDIV_MASK;
214
215 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
216 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
217
218 /* Do calculation in Mhz */
219 fc = bcma_pmu_alp_clock(cc) / 1000000;
220 fc = (p1 * ndiv * fc) / p2;
221
222 /* Return clock in Hertz */
223 return (fc / div) * 1000000;
224}
225
226/* query bus clock frequency for PMU-enabled chipcommon */
227u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
228{
229 struct bcma_bus *bus = cc->core->bus;
230
231 switch (bus->chipinfo.id) {
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200232 case BCMA_CHIP_ID_BCM4716:
233 case BCMA_CHIP_ID_BCM4748:
234 case BCMA_CHIP_ID_BCM47162:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200235 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
236 BCMA_CC_PMU5_MAINPLL_SSB);
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200237 case BCMA_CHIP_ID_BCM5356:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200238 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
239 BCMA_CC_PMU5_MAINPLL_SSB);
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200240 case BCMA_CHIP_ID_BCM5357:
241 case BCMA_CHIP_ID_BCM4749:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200242 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
243 BCMA_CC_PMU5_MAINPLL_SSB);
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200244 case BCMA_CHIP_ID_BCM4706:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200245 return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
246 BCMA_CC_PMU5_MAINPLL_SSB);
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200247 case BCMA_CHIP_ID_BCM53572:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200248 return 75000000;
249 default:
250 pr_warn("No backplane clock specified for %04X device, "
251 "pmu rev. %d, using default %d Hz\n",
252 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
253 }
254 return BCMA_CC_PMU_HT_CLOCK;
255}
256
257/* query cpu clock frequency for PMU-enabled chipcommon */
258u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
259{
260 struct bcma_bus *bus = cc->core->bus;
261
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200262 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200263 return 300000000;
264
265 if (cc->pmu.rev >= 5) {
266 u32 pll;
267 switch (bus->chipinfo.id) {
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200268 case BCMA_CHIP_ID_BCM5356:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200269 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
270 break;
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200271 case BCMA_CHIP_ID_BCM5357:
272 case BCMA_CHIP_ID_BCM4749:
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200273 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
274 break;
275 default:
276 pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
277 break;
278 }
279
Hauke Mehrtens4b4f5be2012-06-30 01:44:38 +0200280 /* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
Hauke Mehrtens908debc2011-07-23 01:20:11 +0200281 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
282 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
283 }
284
285 return bcma_pmu_get_clockcontrol(cc);
286}