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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Tejun Heo8c3d3d42013-05-14 11:09:50 -07004 * Maintained by: Tejun Heo <tj@kernel.org>
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04005 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
Alessandro Rubini318893e2012-01-06 13:33:39 +010055 AHCI_PCI_BAR_STA2X11 = 0,
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -080056 AHCI_PCI_BAR_ENMOTUS = 2,
Alessandro Rubini318893e2012-01-06 13:33:39 +010057 AHCI_PCI_BAR_STANDARD = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090058};
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Tejun Heo441577e2010-03-29 10:32:39 +090060enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
Levente Kurusaaa5b8c42014-02-18 10:22:17 -050064 board_ahci_noncq,
Tejun Heo441577e2010-03-29 10:32:39 +090065 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020066 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090067
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090070 board_ahci_mcp77,
71 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090072 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090081 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070082};
83
Jeff Garzik2dcb4072007-10-19 06:42:56 -040084static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heoa1efdab2008-03-25 12:22:50 +090085static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090089#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090090static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090092#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Tejun Heofad16e72010-09-21 09:25:48 +020094static struct scsi_host_template ahci_sht = {
95 AHCI_SHT("ahci"),
96};
97
Tejun Heo029cfd62008-03-25 12:22:49 +090098static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900100 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900101};
102
Tejun Heo029cfd62008-03-25 12:22:49 +0900103static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900105 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900106};
107
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100108static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900109 /* by features */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530110 [board_ahci] = {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900111 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100112 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400113 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 .port_ops = &ahci_ops,
115 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530116 [board_ahci_ign_iferr] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100119 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400120 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900121 .port_ops = &ahci_ops,
122 },
Levente Kurusaaa5b8c42014-02-18 10:22:17 -0500123 [board_ahci_noncq] = {
124 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
125 .flags = AHCI_FLAG_COMMON,
126 .pio_mask = ATA_PIO4,
127 .udma_mask = ATA_UDMA6,
128 .port_ops = &ahci_ops,
129 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530130 [board_ahci_nosntf] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900131 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530137 [board_ahci_yes_fbs] = {
Tejun Heo5f173102010-07-24 16:53:48 +0200138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
Tejun Heo441577e2010-03-29 10:32:39 +0900144 /* by chipsets */
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530145 [board_ahci_mcp65] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 AHCI_HFLAG_YES_NCQ),
Tejun Heoae01b242011-03-16 11:14:55 +0100148 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
Tejun Heo83f2b962010-03-30 10:28:32 +0900149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530153 [board_ahci_mcp77] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
159 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530160 [board_ahci_mcp89] = {
Tejun Heo83f2b962010-03-30 10:28:32 +0900161 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530167 [board_ahci_mv] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
Tejun Heo441577e2010-03-29 10:32:39 +0900171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530175 [board_ahci_sb600] = {
Tejun Heo417a1a62007-09-23 13:19:55 +0900176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900179 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100180 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400181 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800182 .port_ops = &ahci_pmp_retry_srst_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800183 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530184 [board_ahci_sb700] = { /* for SB700 and SB800 */
Shane Huangbd172432008-06-10 15:52:04 +0800185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800186 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100187 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800188 .udma_mask = ATA_UDMA6,
Yuan-Hsin Chen345347c2011-06-21 17:17:38 +0800189 .port_ops = &ahci_pmp_retry_srst_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800190 },
Jeffrin Josefacb8fa2012-06-05 01:33:37 +0530191 [board_ahci_vt8251] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900192 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900193 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100194 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900195 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900196 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800197 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198};
199
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500200static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400201 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400202 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
203 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
204 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
205 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
206 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900207 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400208 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900212 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800213 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900214 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400229 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
230 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800231 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500232 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800233 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500234 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
235 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700236 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700237 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500238 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700239 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700240 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500241 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800242 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Seth Heasley992b3fb2010-09-09 09:44:56 -0700248 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
249 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
250 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
Seth Heasley64a39032011-03-11 11:57:42 -0800251 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
Seth Heasleya4a461a2011-01-10 12:57:17 -0800252 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
Seth Heasley181e3ce2011-04-20 08:45:20 -0700253 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
256 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
Seth Heasley2cab7a42011-07-14 16:50:49 -0700259 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
Seth Heasleyea4ace62012-01-23 16:27:30 -0800260 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
261 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
263 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
James Ralston77b12bc92012-08-09 09:02:31 -0700268 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
269 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
271 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
Seth Heasley29e674d2013-01-25 12:01:05 -0800276 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
James Ralstonefda3322013-02-21 11:08:51 -0800292 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
James Ralston151743f2013-02-08 17:34:47 -0800294 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
295 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
299 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
300 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
Seth Heasley21e8e042013-06-19 16:36:45 -0700302 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
James Ralston296cfde2013-11-04 09:24:58 -0800303 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
305 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
James Ralstonf714be22014-08-27 14:29:07 -0700307 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
308 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
309 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
310 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
311 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400315
Tejun Heoe34bb372007-02-26 20:24:03 +0900316 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
317 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
318 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Ben Hutchings1fefb8f2012-09-10 01:09:04 +0100319 /* JMicron 362B and 362C have an AHCI function with IDE class code */
320 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
321 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400322
323 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800324 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800325 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
326 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400331
Shane Huange2dd90b2009-07-29 11:34:49 +0800332 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800333 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huang7d31ea02013-06-03 18:24:10 +0800334 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
Shane Huange2dd90b2009-07-29 11:34:49 +0800335 /* AMD is using RAID class only for ahci controllers */
336 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
337 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
338
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400339 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400340 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900341 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400342
343 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900344 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900352 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400428
Jeff Garzik95916ed2006-07-29 04:10:14 -0400429 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900430 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
431 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
432 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400433
Alessandro Rubini318893e2012-01-06 13:33:39 +0100434 /* ST Microelectronics */
435 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
436
Jeff Garzikcd70c262007-07-08 02:29:42 -0400437 /* Marvell */
438 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100439 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
Anssi Hannula10aca062011-01-18 20:03:26 -0500441 .class = PCI_CLASS_STORAGE_SATA_AHCI,
442 .class_mask = 0xffffff,
Tejun Heo5f173102010-07-24 16:53:48 +0200443 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
Per Jessen467b41c2011-02-08 13:54:32 +0100445 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
Simon Guinot6e3eb162013-12-23 13:24:35 +0100446 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
447 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
Matt Johnson642d8922012-04-27 01:42:30 -0500450 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
George Spelvinfcce9a32013-05-29 10:20:35 +0900451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
Murali Karicheri4e2bd062014-09-05 13:21:00 -0400452 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
George Spelvinfcce9a32013-05-29 10:20:35 +0900454 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
Myron Stowe69fd3152013-04-08 11:32:49 -0600455 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
Alan Cox17c60c62012-09-04 16:07:18 +0100456 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
Andreas Schrägle7d872bd2014-05-24 16:35:43 +0200457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
458 .driver_data = board_ahci_yes_fbs },
Myron Stowe69fd3152013-04-08 11:32:49 -0600459 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
Tejun Heo50be5e32010-11-29 15:57:14 +0100460 .driver_data = board_ahci_yes_fbs },
Samir Benmendil61688ba2013-11-17 23:56:17 +0100461 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
462 .driver_data = board_ahci_yes_fbs },
Jérôme Carretero18958492014-06-03 14:56:25 -0400463 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
464 .driver_data = board_ahci_yes_fbs },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400465
Mark Nelsonc77a0362008-10-23 14:08:16 +1100466 /* Promise */
467 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
Romain Degezd35acb62014-07-11 18:08:13 +0200468 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
Mark Nelsonc77a0362008-10-23 14:08:16 +1100469
Keng-Yu Linc9703762011-11-09 01:47:36 -0500470 /* Asmedia */
Alan Cox7b4f6ec2012-09-04 16:25:25 +0100471 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
472 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
473 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
474 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
Keng-Yu Linc9703762011-11-09 01:47:36 -0500475
Levente Kurusaaa5b8c42014-02-18 10:22:17 -0500476 /*
477 * Samsung SSDs found on some macbooks. NCQ times out.
478 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
479 */
480 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
481
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -0800482 /* Enmotus */
483 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
484
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500485 /* Generic, PCI class code for AHCI */
486 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500487 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500488
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 { } /* terminate list */
490};
491
492
493static struct pci_driver ahci_pci_driver = {
494 .name = DRV_NAME,
495 .id_table = ahci_pci_tbl,
496 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900497 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900498#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900499 .suspend = ahci_pci_device_suspend,
500 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900501#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502};
503
Alan Cox5b66c822008-09-03 14:48:34 +0100504#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
505static int marvell_enable;
506#else
507static int marvell_enable = 1;
508#endif
509module_param(marvell_enable, int, 0644);
510MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
511
512
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300513static void ahci_pci_save_initial_config(struct pci_dev *pdev,
514 struct ahci_host_priv *hpriv)
515{
516 unsigned int force_port_map = 0;
517 unsigned int mask_port_map = 0;
518
519 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
520 dev_info(&pdev->dev, "JMB361 has only one port\n");
521 force_port_map = 1;
522 }
523
524 /*
525 * Temporary Marvell 6145 hack: PATA port presence
526 * is asserted through the standard AHCI port
527 * presence register, as bit 4 (counting from 0)
528 */
529 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
530 if (pdev->device == 0x6121)
531 mask_port_map = 0x3;
532 else
533 mask_port_map = 0xf;
534 dev_info(&pdev->dev,
535 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
536 }
537
Anton Vorontsov1d513352010-03-03 20:17:37 +0300538 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
539 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300540}
541
Anton Vorontsov33030402010-03-03 20:17:39 +0300542static int ahci_pci_reset_controller(struct ata_host *host)
543{
544 struct pci_dev *pdev = to_pci_dev(host->dev);
545
546 ahci_reset_controller(host);
547
Tejun Heod91542c2006-07-26 15:59:26 +0900548 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300549 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900550 u16 tmp16;
551
552 /* configure PCS */
553 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900554 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
555 tmp16 |= hpriv->port_map;
556 pci_write_config_word(pdev, 0x92, tmp16);
557 }
Tejun Heod91542c2006-07-26 15:59:26 +0900558 }
559
560 return 0;
561}
562
Anton Vorontsov781d6552010-03-03 20:17:42 +0300563static void ahci_pci_init_controller(struct ata_host *host)
564{
565 struct ahci_host_priv *hpriv = host->private_data;
566 struct pci_dev *pdev = to_pci_dev(host->dev);
567 void __iomem *port_mmio;
568 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100569 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900570
Tejun Heo417a1a62007-09-23 13:19:55 +0900571 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100572 if (pdev->device == 0x6121)
573 mv = 2;
574 else
575 mv = 4;
576 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400577
578 writel(0, port_mmio + PORT_IRQ_MASK);
579
580 /* clear port IRQ */
581 tmp = readl(port_mmio + PORT_IRQ_STAT);
582 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
583 if (tmp)
584 writel(tmp, port_mmio + PORT_IRQ_STAT);
585 }
586
Anton Vorontsov781d6552010-03-03 20:17:42 +0300587 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900588}
589
Tejun Heocc0680a2007-08-06 18:36:23 +0900590static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900591 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900592{
Tejun Heocc0680a2007-08-06 18:36:23 +0900593 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +0900594 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900595 int rc;
596
597 DPRINTK("ENTER\n");
598
Tejun Heo4447d352007-04-17 23:44:08 +0900599 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900600
Tejun Heocc0680a2007-08-06 18:36:23 +0900601 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900602 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900603
Tejun Heo4447d352007-04-17 23:44:08 +0900604 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900605
606 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
607
608 /* vt8251 doesn't clear BSY on signature FIS reception,
609 * request follow-up softreset.
610 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900611 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900612}
613
Tejun Heoedc93052007-10-25 14:59:16 +0900614static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
615 unsigned long deadline)
616{
617 struct ata_port *ap = link->ap;
618 struct ahci_port_priv *pp = ap->private_data;
619 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
620 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900621 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900622 int rc;
623
624 ahci_stop_engine(ap);
625
626 /* clear D2H reception area to properly wait for D2H FIS */
627 ata_tf_init(link->device, &tf);
628 tf.command = 0x80;
629 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
630
631 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900632 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900633
634 ahci_start_engine(ap);
635
Tejun Heoedc93052007-10-25 14:59:16 +0900636 /* The pseudo configuration device on SIMG4726 attached to
637 * ASUS P5W-DH Deluxe doesn't send signature FIS after
638 * hardreset if no device is attached to the first downstream
639 * port && the pseudo device locks up on SRST w/ PMP==0. To
640 * work around this, wait for !BSY only briefly. If BSY isn't
641 * cleared, perform CLO and proceed to IDENTIFY (achieved by
642 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
643 *
644 * Wait for two seconds. Devices attached to downstream port
645 * which can't process the following IDENTIFY after this will
646 * have to be reset again. For most cases, this should
647 * suffice while making probing snappish enough.
648 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900649 if (online) {
650 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
651 ahci_check_ready);
652 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800653 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900654 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900655 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900656}
657
Tejun Heo438ac6d2007-03-02 17:31:26 +0900658#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900659static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
660{
Jeff Garzikcca39742006-08-24 03:19:22 -0400661 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900662 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300663 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900664 u32 ctl;
665
Tejun Heo9b10ae82009-05-30 20:50:12 +0900666 if (mesg.event & PM_EVENT_SUSPEND &&
667 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700668 dev_err(&pdev->dev,
669 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +0900670 return -EIO;
671 }
672
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100673 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900674 /* AHCI spec rev1.1 section 8.3.3:
675 * Software must disable interrupts prior to requesting a
676 * transition of the HBA to D3 state.
677 */
678 ctl = readl(mmio + HOST_CTL);
679 ctl &= ~HOST_IRQ_EN;
680 writel(ctl, mmio + HOST_CTL);
681 readl(mmio + HOST_CTL); /* flush */
682 }
683
684 return ata_pci_device_suspend(pdev, mesg);
685}
686
687static int ahci_pci_device_resume(struct pci_dev *pdev)
688{
Jeff Garzikcca39742006-08-24 03:19:22 -0400689 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +0900690 int rc;
691
Tejun Heo553c4aa2006-12-26 19:39:50 +0900692 rc = ata_pci_device_do_resume(pdev);
693 if (rc)
694 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900695
696 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300697 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900698 if (rc)
699 return rc;
700
Anton Vorontsov781d6552010-03-03 20:17:42 +0300701 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900702 }
703
Jeff Garzikcca39742006-08-24 03:19:22 -0400704 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900705
706 return 0;
707}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900708#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900709
Tejun Heo4447d352007-04-17 23:44:08 +0900710static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713
Alessandro Rubini318893e2012-01-06 13:33:39 +0100714 /*
715 * If the device fixup already set the dma_mask to some non-standard
716 * value, don't extend it here. This happens on STA2X11, for example.
717 */
718 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
719 return 0;
720
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700722 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
723 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700725 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700727 dev_err(&pdev->dev,
728 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 return rc;
730 }
731 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700733 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700735 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 return rc;
737 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700738 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700740 dev_err(&pdev->dev,
741 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742 return rc;
743 }
744 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 return 0;
746}
747
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300748static void ahci_pci_print_info(struct ata_host *host)
749{
750 struct pci_dev *pdev = to_pci_dev(host->dev);
751 u16 cc;
752 const char *scc_s;
753
754 pci_read_config_word(pdev, 0x0a, &cc);
755 if (cc == PCI_CLASS_STORAGE_IDE)
756 scc_s = "IDE";
757 else if (cc == PCI_CLASS_STORAGE_SATA)
758 scc_s = "SATA";
759 else if (cc == PCI_CLASS_STORAGE_RAID)
760 scc_s = "RAID";
761 else
762 scc_s = "unknown";
763
764 ahci_print_info(host, scc_s);
765}
766
Tejun Heoedc93052007-10-25 14:59:16 +0900767/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
768 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
769 * support PMP and the 4726 either directly exports the device
770 * attached to the first downstream port or acts as a hardware storage
771 * controller and emulate a single ATA device (can be RAID 0/1 or some
772 * other configuration).
773 *
774 * When there's no device attached to the first downstream port of the
775 * 4726, "Config Disk" appears, which is a pseudo ATA device to
776 * configure the 4726. However, ATA emulation of the device is very
777 * lame. It doesn't send signature D2H Reg FIS after the initial
778 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
779 *
780 * The following function works around the problem by always using
781 * hardreset on the port and not depending on receiving signature FIS
782 * afterward. If signature FIS isn't received soon, ATA class is
783 * assumed without follow-up softreset.
784 */
785static void ahci_p5wdh_workaround(struct ata_host *host)
786{
787 static struct dmi_system_id sysids[] = {
788 {
789 .ident = "P5W DH Deluxe",
790 .matches = {
791 DMI_MATCH(DMI_SYS_VENDOR,
792 "ASUSTEK COMPUTER INC"),
793 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
794 },
795 },
796 { }
797 };
798 struct pci_dev *pdev = to_pci_dev(host->dev);
799
800 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
801 dmi_check_system(sysids)) {
802 struct ata_port *ap = host->ports[1];
803
Joe Perchesa44fec12011-04-15 15:51:58 -0700804 dev_info(&pdev->dev,
805 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
Tejun Heoedc93052007-10-25 14:59:16 +0900806
807 ap->ops = &ahci_p5wdh_ops;
808 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
809 }
810}
811
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900812/* only some SB600 ahci controllers can do 64bit DMA */
813static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800814{
815 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900816 /*
817 * The oldest version known to be broken is 0901 and
818 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900819 * Enable 64bit DMA on 1501 and anything newer.
820 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900821 * Please read bko#9412 for more info.
822 */
Shane Huang58a09b32009-05-27 15:04:43 +0800823 {
824 .ident = "ASUS M2A-VM",
825 .matches = {
826 DMI_MATCH(DMI_BOARD_VENDOR,
827 "ASUSTeK Computer INC."),
828 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
829 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900830 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800831 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100832 /*
833 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
834 * support 64bit DMA.
835 *
836 * BIOS versions earlier than 1.5 had the Manufacturer DMI
837 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
838 * This spelling mistake was fixed in BIOS version 1.5, so
839 * 1.5 and later have the Manufacturer as
840 * "MICRO-STAR INTERNATIONAL CO.,LTD".
841 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
842 *
843 * BIOS versions earlier than 1.9 had a Board Product Name
844 * DMI field of "MS-7376". This was changed to be
845 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
846 * match on DMI_BOARD_NAME of "MS-7376".
847 */
848 {
849 .ident = "MSI K9A2 Platinum",
850 .matches = {
851 DMI_MATCH(DMI_BOARD_VENDOR,
852 "MICRO-STAR INTER"),
853 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
854 },
855 },
Mark Nelson3c4aa912011-06-27 16:33:44 +1000856 /*
Mark Nelsonff0173c2012-06-28 12:32:14 +1000857 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
858 * 64bit DMA.
859 *
860 * This board also had the typo mentioned above in the
861 * Manufacturer DMI field (fixed in BIOS version 1.5), so
862 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
863 */
864 {
865 .ident = "MSI K9AGM2",
866 .matches = {
867 DMI_MATCH(DMI_BOARD_VENDOR,
868 "MICRO-STAR INTER"),
869 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
870 },
871 },
872 /*
Mark Nelson3c4aa912011-06-27 16:33:44 +1000873 * All BIOS versions for the Asus M3A support 64bit DMA.
874 * (all release versions from 0301 to 1206 were tested)
875 */
876 {
877 .ident = "ASUS M3A",
878 .matches = {
879 DMI_MATCH(DMI_BOARD_VENDOR,
880 "ASUSTeK Computer INC."),
881 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
882 },
883 },
Shane Huang58a09b32009-05-27 15:04:43 +0800884 { }
885 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900886 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900887 int year, month, date;
888 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800889
Tejun Heo03d783b2009-08-16 21:04:02 +0900890 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800891 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900892 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800893 return false;
894
Mark Nelsone65cc192009-11-03 20:06:48 +1100895 if (!match->driver_data)
896 goto enable_64bit;
897
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900898 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
899 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800900
Mark Nelsone65cc192009-11-03 20:06:48 +1100901 if (strcmp(buf, match->driver_data) >= 0)
902 goto enable_64bit;
903 else {
Joe Perchesa44fec12011-04-15 15:51:58 -0700904 dev_warn(&pdev->dev,
905 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
906 match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900907 return false;
908 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100909
910enable_64bit:
Joe Perchesa44fec12011-04-15 15:51:58 -0700911 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
Mark Nelsone65cc192009-11-03 20:06:48 +1100912 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800913}
914
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100915static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
916{
917 static const struct dmi_system_id broken_systems[] = {
918 {
919 .ident = "HP Compaq nx6310",
920 .matches = {
921 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
923 },
924 /* PCI slot number of the controller */
925 .driver_data = (void *)0x1FUL,
926 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100927 {
928 .ident = "HP Compaq 6720s",
929 .matches = {
930 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
931 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
932 },
933 /* PCI slot number of the controller */
934 .driver_data = (void *)0x1FUL,
935 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100936
937 { } /* terminate list */
938 };
939 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
940
941 if (dmi) {
942 unsigned long slot = (unsigned long)dmi->driver_data;
943 /* apply the quirk only to on-board controllers */
944 return slot == PCI_SLOT(pdev->devfn);
945 }
946
947 return false;
948}
949
Tejun Heo9b10ae82009-05-30 20:50:12 +0900950static bool ahci_broken_suspend(struct pci_dev *pdev)
951{
952 static const struct dmi_system_id sysids[] = {
953 /*
954 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
955 * to the harddisk doesn't become online after
956 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900957 *
958 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
959 *
960 * Use dates instead of versions to match as HP is
961 * apparently recycling both product and version
962 * strings.
963 *
964 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900965 */
966 {
967 .ident = "dv4",
968 .matches = {
969 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
970 DMI_MATCH(DMI_PRODUCT_NAME,
971 "HP Pavilion dv4 Notebook PC"),
972 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900973 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900974 },
975 {
976 .ident = "dv5",
977 .matches = {
978 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
979 DMI_MATCH(DMI_PRODUCT_NAME,
980 "HP Pavilion dv5 Notebook PC"),
981 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900982 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900983 },
984 {
985 .ident = "dv6",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
988 DMI_MATCH(DMI_PRODUCT_NAME,
989 "HP Pavilion dv6 Notebook PC"),
990 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900991 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900992 },
993 {
994 .ident = "HDX18",
995 .matches = {
996 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
997 DMI_MATCH(DMI_PRODUCT_NAME,
998 "HP HDX18 Notebook PC"),
999 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001000 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +09001001 },
Tejun Heocedc9bf2010-01-28 16:04:15 +09001002 /*
1003 * Acer eMachines G725 has the same problem. BIOS
1004 * V1.03 is known to be broken. V3.04 is known to
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001005 * work. Between, there are V1.06, V2.06 and V3.03
Tejun Heocedc9bf2010-01-28 16:04:15 +09001006 * that we don't have much idea about. For now,
1007 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +09001008 *
1009 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +09001010 */
1011 {
1012 .ident = "G725",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1016 },
Tejun Heo9deb3432010-03-16 09:50:26 +09001017 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +09001018 },
Tejun Heo9b10ae82009-05-30 20:50:12 +09001019 { } /* terminate list */
1020 };
1021 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +09001022 int year, month, date;
1023 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +09001024
1025 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1026 return false;
1027
Tejun Heo9deb3432010-03-16 09:50:26 +09001028 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1029 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +09001030
Tejun Heo9deb3432010-03-16 09:50:26 +09001031 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +09001032}
1033
Tejun Heo55946392009-08-04 14:30:08 +09001034static bool ahci_broken_online(struct pci_dev *pdev)
1035{
1036#define ENCODE_BUSDEVFN(bus, slot, func) \
1037 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1038 static const struct dmi_system_id sysids[] = {
1039 /*
1040 * There are several gigabyte boards which use
1041 * SIMG5723s configured as hardware RAID. Certain
1042 * 5723 firmware revisions shipped there keep the link
1043 * online but fail to answer properly to SRST or
1044 * IDENTIFY when no device is attached downstream
1045 * causing libata to retry quite a few times leading
1046 * to excessive detection delay.
1047 *
1048 * As these firmwares respond to the second reset try
1049 * with invalid device signature, considering unknown
1050 * sig as offline works around the problem acceptably.
1051 */
1052 {
1053 .ident = "EP45-DQ6",
1054 .matches = {
1055 DMI_MATCH(DMI_BOARD_VENDOR,
1056 "Gigabyte Technology Co., Ltd."),
1057 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1058 },
1059 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1060 },
1061 {
1062 .ident = "EP45-DS5",
1063 .matches = {
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "Gigabyte Technology Co., Ltd."),
1066 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1067 },
1068 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1069 },
1070 { } /* terminate list */
1071 };
1072#undef ENCODE_BUSDEVFN
1073 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1074 unsigned int val;
1075
1076 if (!dmi)
1077 return false;
1078
1079 val = (unsigned long)dmi->driver_data;
1080
1081 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1082}
1083
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001084#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +09001085static void ahci_gtf_filter_workaround(struct ata_host *host)
1086{
1087 static const struct dmi_system_id sysids[] = {
1088 /*
1089 * Aspire 3810T issues a bunch of SATA enable commands
1090 * via _GTF including an invalid one and one which is
1091 * rejected by the device. Among the successful ones
1092 * is FPDMA non-zero offset enable which when enabled
1093 * only on the drive side leads to NCQ command
1094 * failures. Filter it out.
1095 */
1096 {
1097 .ident = "Aspire 3810T",
1098 .matches = {
1099 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1101 },
1102 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1103 },
1104 { }
1105 };
1106 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1107 unsigned int filter;
1108 int i;
1109
1110 if (!dmi)
1111 return;
1112
1113 filter = (unsigned long)dmi->driver_data;
Joe Perchesa44fec12011-04-15 15:51:58 -07001114 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1115 filter, dmi->ident);
Tejun Heof80ae7e2009-09-16 04:18:03 +09001116
1117 for (i = 0; i < host->n_ports; i++) {
1118 struct ata_port *ap = host->ports[i];
1119 struct ata_link *link;
1120 struct ata_device *dev;
1121
1122 ata_for_each_link(link, ap, EDGE)
1123 ata_for_each_dev(dev, link, ALL)
1124 dev->gtf_filter |= filter;
1125 }
1126}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001127#else
1128static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1129{}
1130#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001131
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001132int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1133{
1134 int rc;
1135 unsigned int maxvec;
1136
1137 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1138 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1139 if (rc > 0) {
1140 if ((rc == maxvec) || (rc == 1))
1141 return rc;
1142 /*
1143 * Assume that advantage of multipe MSIs is negated,
1144 * so fallback to single MSI mode to save resources
1145 */
1146 pci_disable_msi(pdev);
1147 if (!pci_enable_msi(pdev))
1148 return 1;
1149 }
1150 }
1151
1152 pci_intx(pdev, 1);
1153 return 0;
1154}
1155
1156/**
1157 * ahci_host_activate - start AHCI host, request IRQs and register it
1158 * @host: target ATA host
1159 * @irq: base IRQ number to request
1160 * @n_msis: number of MSIs allocated for this host
1161 * @irq_handler: irq_handler used when requesting IRQs
1162 * @irq_flags: irq_flags used when requesting IRQs
1163 *
1164 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1165 * when multiple MSIs were allocated. That is one MSI per port, starting
1166 * from @irq.
1167 *
1168 * LOCKING:
1169 * Inherited from calling layer (may sleep).
1170 *
1171 * RETURNS:
1172 * 0 on success, -errno otherwise.
1173 */
1174int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1175{
1176 int i, rc;
1177
1178 /* Sharing Last Message among several ports is not supported */
1179 if (n_msis < host->n_ports)
1180 return -EINVAL;
1181
1182 rc = ata_host_start(host);
1183 if (rc)
1184 return rc;
1185
1186 for (i = 0; i < host->n_ports; i++) {
1187 rc = devm_request_threaded_irq(host->dev,
1188 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1189 dev_driver_string(host->dev), host->ports[i]);
1190 if (rc)
1191 goto out_free_irqs;
1192 }
1193
1194 for (i = 0; i < host->n_ports; i++)
1195 ata_port_desc(host->ports[i], "irq %d", irq + i);
1196
1197 rc = ata_host_register(host, &ahci_sht);
1198 if (rc)
1199 goto out_free_all_irqs;
1200
1201 return 0;
1202
1203out_free_all_irqs:
1204 i = host->n_ports;
1205out_free_irqs:
1206 for (i--; i >= 0; i--)
1207 devm_free_irq(host->dev, irq + i, host->ports[i]);
1208
1209 return rc;
1210}
1211
Tejun Heo24dc5f32007-01-20 16:00:28 +09001212static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213{
Tejun Heoe297d992008-06-10 00:13:04 +09001214 unsigned int board_id = ent->driver_data;
1215 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001216 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001217 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001219 struct ata_host *host;
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001220 int n_ports, n_msis, i, rc;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001221 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222
1223 VPRINTK("ENTER\n");
1224
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001225 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001226
Joe Perches06296a12011-04-15 15:52:00 -07001227 ata_print_version_once(&pdev->dev, DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228
Alan Cox5b66c822008-09-03 14:48:34 +01001229 /* The AHCI driver can only drive the SATA ports, the PATA driver
1230 can drive them all so if both drivers are selected make sure
1231 AHCI stays out of the way */
1232 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1233 return -ENODEV;
1234
Tejun Heoc6353b42010-06-17 11:42:22 +02001235 /*
1236 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1237 * ahci, use ata_generic instead.
1238 */
1239 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1240 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1241 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1242 pdev->subsystem_device == 0xcb89)
1243 return -ENODEV;
1244
Mark Nelson7a022672009-11-22 12:07:41 +11001245 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1246 * At the moment, we can only use the AHCI mode. Let the users know
1247 * that for SAS drives they're out of luck.
1248 */
1249 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
Joe Perchesa44fec12011-04-15 15:51:58 -07001250 dev_info(&pdev->dev,
1251 "PDC42819 can only drive SATA devices with this driver\n");
Mark Nelson7a022672009-11-22 12:07:41 +11001252
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001253 /* Both Connext and Enmotus devices use non-standard BARs */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001254 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1255 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
Hugh Daschbach7f9c9f82013-01-04 14:39:09 -08001256 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1257 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
Alessandro Rubini318893e2012-01-06 13:33:39 +01001258
Tejun Heo4447d352007-04-17 23:44:08 +09001259 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001260 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001261 if (rc)
1262 return rc;
1263
Tejun Heodea55132008-03-11 19:52:31 +09001264 /* AHCI controllers often implement SFF compatible interface.
1265 * Grab all PCI BARs just in case.
1266 */
Alessandro Rubini318893e2012-01-06 13:33:39 +01001267 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001268 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001269 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001270 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001271 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272
Tejun Heoc4f77922007-12-06 15:09:43 +09001273 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1274 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1275 u8 map;
1276
1277 /* ICH6s share the same PCI ID for both piix and ahci
1278 * modes. Enabling ahci mode while MAP indicates
1279 * combined mode is a bad idea. Yield to ata_piix.
1280 */
1281 pci_read_config_byte(pdev, ICH_MAP, &map);
1282 if (map & 0x3) {
Joe Perchesa44fec12011-04-15 15:51:58 -07001283 dev_info(&pdev->dev,
1284 "controller is in combined mode, can't enable AHCI mode\n");
Tejun Heoc4f77922007-12-06 15:09:43 +09001285 return -ENODEV;
1286 }
1287 }
1288
Tejun Heo24dc5f32007-01-20 16:00:28 +09001289 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1290 if (!hpriv)
1291 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001292 hpriv->flags |= (unsigned long)pi.private_data;
1293
Tejun Heoe297d992008-06-10 00:13:04 +09001294 /* MCP65 revision A1 and A2 can't do MSI */
1295 if (board_id == board_ahci_mcp65 &&
1296 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1297 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1298
Shane Huange427fe02008-12-30 10:53:41 +08001299 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1300 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1301 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1302
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001303 /* only some SB600s can do 64bit DMA */
1304 if (ahci_sb600_enable_64bit(pdev))
1305 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001306
Alessandro Rubini318893e2012-01-06 13:33:39 +01001307 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
Anton Vorontsovd8993342010-03-03 20:17:34 +03001308
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001309 n_msis = ahci_init_interrupts(pdev, hpriv);
1310 if (n_msis > 1)
1311 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1312
Tejun Heo4447d352007-04-17 23:44:08 +09001313 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001314 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315
Tejun Heo4447d352007-04-17 23:44:08 +09001316 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001317 if (hpriv->cap & HOST_CAP_NCQ) {
1318 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001319 /*
1320 * Auto-activate optimization is supposed to be
1321 * supported on all AHCI controllers indicating NCQ
1322 * capability, but it seems to be broken on some
1323 * chipsets including NVIDIAs.
1324 */
1325 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001326 pi.flags |= ATA_FLAG_FPDMA_AA;
1327 }
Tejun Heo4447d352007-04-17 23:44:08 +09001328
Tejun Heo7d50b602007-09-23 13:19:54 +09001329 if (hpriv->cap & HOST_CAP_PMP)
1330 pi.flags |= ATA_FLAG_PMP;
1331
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001332 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001333
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001334 if (ahci_broken_system_poweroff(pdev)) {
1335 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1336 dev_info(&pdev->dev,
1337 "quirky BIOS, skipping spindown on poweroff\n");
1338 }
1339
Tejun Heo9b10ae82009-05-30 20:50:12 +09001340 if (ahci_broken_suspend(pdev)) {
1341 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
Joe Perchesa44fec12011-04-15 15:51:58 -07001342 dev_warn(&pdev->dev,
1343 "BIOS update required for suspend/resume\n");
Tejun Heo9b10ae82009-05-30 20:50:12 +09001344 }
1345
Tejun Heo55946392009-08-04 14:30:08 +09001346 if (ahci_broken_online(pdev)) {
1347 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1348 dev_info(&pdev->dev,
1349 "online status unreliable, applying workaround\n");
1350 }
1351
Tejun Heo837f5f82008-02-06 15:13:51 +09001352 /* CAP.NP sometimes indicate the index of the last enabled
1353 * port, at other times, that of the last possible port, so
1354 * determining the maximum port number requires looking at
1355 * both CAP.NP and port_map.
1356 */
1357 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1358
1359 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001360 if (!host)
1361 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001362 host->private_data = hpriv;
1363
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001364 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001365 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001366 else
1367 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001368
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001369 if (pi.flags & ATA_FLAG_EM)
1370 ahci_reset_em(host);
1371
Tejun Heo4447d352007-04-17 23:44:08 +09001372 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001373 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001374
Alessandro Rubini318893e2012-01-06 13:33:39 +01001375 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1376 ata_port_pbar_desc(ap, ahci_pci_bar,
Tejun Heocbcdd872007-08-18 13:14:55 +09001377 0x100 + ap->port_no * 0x80, "port");
1378
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001379 /* set enclosure management message type */
1380 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001381 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001382
1383
Jeff Garzikdab632e2007-05-28 08:33:01 -04001384 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001385 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001386 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001387 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388
Tejun Heoedc93052007-10-25 14:59:16 +09001389 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1390 ahci_p5wdh_workaround(host);
1391
Tejun Heof80ae7e2009-09-16 04:18:03 +09001392 /* apply gtf filter quirk */
1393 ahci_gtf_filter_workaround(host);
1394
Linus Torvalds1da177e2005-04-16 15:20:36 -07001395 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001396 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001398 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399
Anton Vorontsov33030402010-03-03 20:17:39 +03001400 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001401 if (rc)
1402 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001403
Anton Vorontsov781d6552010-03-03 20:17:42 +03001404 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001405 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406
Tejun Heo4447d352007-04-17 23:44:08 +09001407 pci_set_master(pdev);
Alexander Gordeev5ca72c42012-11-19 16:02:48 +01001408
1409 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1410 return ahci_host_activate(host, pdev->irq, n_msis);
1411
Tejun Heo4447d352007-04-17 23:44:08 +09001412 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1413 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001414}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415
Axel Lin2fc75da2012-04-19 13:43:05 +08001416module_pci_driver(ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
1418MODULE_AUTHOR("Jeff Garzik");
1419MODULE_DESCRIPTION("AHCI SATA low-level driver");
1420MODULE_LICENSE("GPL");
1421MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001422MODULE_VERSION(DRV_VERSION);