blob: 294f55788f0b3c30dde8689cadee2a5837228866 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070031#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100038#include "drm_dp_helper.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070039
Jesse Barnesa2006cf2011-09-22 11:15:58 +053040#define DP_RECEIVER_CAP_SIZE 0xf
Keith Packarda4fc5ed2009-04-07 16:16:42 -070041#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
Chris Wilsonea5b2132010-08-04 13:50:23 +010046struct intel_dp {
47 struct intel_encoder base;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070048 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -070051 bool has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +010052 int force_audio;
Chris Wilsone953fd72011-02-21 22:23:52 +000053 uint32_t color_range;
Keith Packardd2b996a2011-07-25 22:37:51 -070054 int dpms_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070055 uint8_t link_bw;
56 uint8_t lane_count;
Jesse Barnesa2006cf2011-09-22 11:15:58 +053057 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -070058 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
Adam Jacksonf0917372010-07-16 14:46:27 -040060 bool is_pch_edp;
Jesse Barnes33a34e42010-09-08 12:42:02 -070061 uint8_t train_set[4];
Keith Packardf01eca22011-09-28 16:48:10 -070062 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
Keith Packardd15456d2011-09-18 17:35:47 -070067 struct drm_display_mode *panel_fixed_mode; /* for eDP */
Keith Packardbd943152011-09-18 23:09:52 -070068 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
Keith Packarda4fc5ed2009-04-07 16:16:42 -070070};
71
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070072/**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79static bool is_edp(struct intel_dp *intel_dp)
80{
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82}
83
84/**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92static bool is_pch_edp(struct intel_dp *intel_dp)
93{
94 return intel_dp->is_pch_edp;
95}
96
Adam Jackson1c958222011-10-14 17:22:25 -040097/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
Chris Wilsonea5b2132010-08-04 13:50:23 +0100108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100110 return container_of(encoder, struct intel_dp, base.base);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100111}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700112
Chris Wilsondf0e9242010-09-09 16:20:55 +0100113static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114{
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117}
118
Jesse Barnes814948a2010-10-07 16:01:09 -0700119/**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127{
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136}
137
Jesse Barnes33a34e42010-09-08 12:42:02 -0700138static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100140static void intel_dp_link_down(struct intel_dp *intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700141
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800142void
Akshay Joshi0206e352011-08-16 15:34:10 -0400143intel_edp_link_config(struct intel_encoder *intel_encoder,
Chris Wilsonea5b2132010-08-04 13:50:23 +0100144 int *lane_num, int *link_bw)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800145{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800147
Chris Wilsonea5b2132010-08-04 13:50:23 +0100148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800150 *link_bw = 162000;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800152 *link_bw = 270000;
153}
154
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700155static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100156intel_dp_max_lane_count(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700157{
Keith Packard9a10f402011-11-02 13:03:47 -0700158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
159 switch (max_lane_count) {
160 case 1: case 2: case 4:
161 break;
162 default:
163 max_lane_count = 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700164 }
165 return max_lane_count;
166}
167
168static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100169intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700170{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700172
173 switch (max_link_bw) {
174 case DP_LINK_BW_1_62:
175 case DP_LINK_BW_2_7:
176 break;
177 default:
178 max_link_bw = DP_LINK_BW_1_62;
179 break;
180 }
181 return max_link_bw;
182}
183
184static int
185intel_dp_link_clock(uint8_t link_bw)
186{
187 if (link_bw == DP_LINK_BW_2_7)
188 return 270000;
189 else
190 return 162000;
191}
192
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400193/*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700210static int
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400211intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700212{
Jesse Barnes89c61432011-06-24 12:19:28 -0700213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
215 int bpp = 24;
Zhenyu Wang885a5fb2010-01-12 05:38:31 +0800216
Jesse Barnes89c61432011-06-24 12:19:28 -0700217 if (intel_crtc)
218 bpp = intel_crtc->bpp;
219
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400220 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700221}
222
223static int
Dave Airliefe27d532010-06-30 11:46:17 +1000224intel_dp_max_data_rate(int max_link_clock, int max_lanes)
225{
226 return (max_link_clock * max_lanes * 8) / 10;
227}
228
229static int
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700230intel_dp_mode_valid(struct drm_connector *connector,
231 struct drm_display_mode *mode)
232{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100233 struct intel_dp *intel_dp = intel_attached_dp(connector);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100234 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
235 int max_lanes = intel_dp_max_lane_count(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700236
Keith Packardd15456d2011-09-18 17:35:47 -0700237 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
238 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100239 return MODE_PANEL;
240
Keith Packardd15456d2011-09-18 17:35:47 -0700241 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100242 return MODE_PANEL;
243 }
244
Adam Jacksondc22ee62011-10-14 12:43:50 -0400245 if (intel_dp_link_required(intel_dp, mode->clock)
246 > intel_dp_max_data_rate(max_link_clock, max_lanes))
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700247 return MODE_CLOCK_HIGH;
248
249 if (mode->clock < 10000)
250 return MODE_CLOCK_LOW;
251
252 return MODE_OK;
253}
254
255static uint32_t
256pack_aux(uint8_t *src, int src_bytes)
257{
258 int i;
259 uint32_t v = 0;
260
261 if (src_bytes > 4)
262 src_bytes = 4;
263 for (i = 0; i < src_bytes; i++)
264 v |= ((uint32_t) src[i]) << ((3-i) * 8);
265 return v;
266}
267
268static void
269unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
270{
271 int i;
272 if (dst_bytes > 4)
273 dst_bytes = 4;
274 for (i = 0; i < dst_bytes; i++)
275 dst[i] = src >> ((3-i) * 8);
276}
277
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700278/* hrawclock is 1/4 the FSB frequency */
279static int
280intel_hrawclk(struct drm_device *dev)
281{
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 uint32_t clkcfg;
284
285 clkcfg = I915_READ(CLKCFG);
286 switch (clkcfg & CLKCFG_FSB_MASK) {
287 case CLKCFG_FSB_400:
288 return 100;
289 case CLKCFG_FSB_533:
290 return 133;
291 case CLKCFG_FSB_667:
292 return 166;
293 case CLKCFG_FSB_800:
294 return 200;
295 case CLKCFG_FSB_1067:
296 return 266;
297 case CLKCFG_FSB_1333:
298 return 333;
299 /* these two are just a guess; one of them might be right */
300 case CLKCFG_FSB_1600:
301 case CLKCFG_FSB_1600_ALT:
302 return 400;
303 default:
304 return 133;
305 }
306}
307
Keith Packardebf33b12011-09-29 15:53:27 -0700308static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
309{
310 struct drm_device *dev = intel_dp->base.base.dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
312
313 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
314}
315
316static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
317{
318 struct drm_device *dev = intel_dp->base.base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320
321 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
322}
323
Keith Packard9b984da2011-09-19 13:54:47 -0700324static void
325intel_dp_check_edp(struct intel_dp *intel_dp)
326{
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700329
Keith Packard9b984da2011-09-19 13:54:47 -0700330 if (!is_edp(intel_dp))
331 return;
Keith Packardebf33b12011-09-29 15:53:27 -0700332 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700333 WARN(1, "eDP powered off while attempting aux channel communication.\n");
334 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Keith Packardebf33b12011-09-29 15:53:27 -0700335 I915_READ(PCH_PP_STATUS),
Keith Packard9b984da2011-09-19 13:54:47 -0700336 I915_READ(PCH_PP_CONTROL));
337 }
338}
339
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700340static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100341intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700342 uint8_t *send, int send_bytes,
343 uint8_t *recv, int recv_size)
344{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100345 uint32_t output_reg = intel_dp->output_reg;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100346 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700347 struct drm_i915_private *dev_priv = dev->dev_private;
348 uint32_t ch_ctl = output_reg + 0x10;
349 uint32_t ch_data = ch_ctl + 4;
350 int i;
351 int recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700352 uint32_t status;
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700353 uint32_t aux_clock_divider;
Zhenyu Wange3421a12010-04-08 09:43:27 +0800354 int try, precharge;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700355
Keith Packard9b984da2011-09-19 13:54:47 -0700356 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700357 /* The clock divider is based off the hrawclk,
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700358 * and would like to run at 2MHz. So, take the
359 * hrawclk value and divide by 2 and use that
Jesse Barnes6176b8f2010-09-08 12:42:00 -0700360 *
361 * Note that PCH attached eDP panels should use a 125MHz input
362 * clock divider.
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700363 */
Adam Jackson1c958222011-10-14 17:22:25 -0400364 if (is_cpu_edp(intel_dp)) {
Keith Packard1a2eb462011-11-16 16:26:07 -0800365 if (IS_GEN6(dev) || IS_GEN7(dev))
366 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
Zhenyu Wange3421a12010-04-08 09:43:27 +0800367 else
368 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
369 } else if (HAS_PCH_SPLIT(dev))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500370 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800371 else
372 aux_clock_divider = intel_hrawclk(dev) / 2;
373
Zhenyu Wange3421a12010-04-08 09:43:27 +0800374 if (IS_GEN6(dev))
375 precharge = 3;
376 else
377 precharge = 5;
378
Jesse Barnes11bee432011-08-01 15:02:20 -0700379 /* Try to wait for any previous AUX channel activity */
380 for (try = 0; try < 3; try++) {
381 status = I915_READ(ch_ctl);
382 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
383 break;
384 msleep(1);
385 }
386
387 if (try == 3) {
388 WARN(1, "dp_aux_ch not started status 0x%08x\n",
389 I915_READ(ch_ctl));
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100390 return -EBUSY;
391 }
392
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700393 /* Must try at least 3 times according to DP spec */
394 for (try = 0; try < 5; try++) {
395 /* Load the send data into the aux channel data registers */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100396 for (i = 0; i < send_bytes; i += 4)
397 I915_WRITE(ch_data + i,
398 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400399
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700400 /* Send the command and wait for it to complete */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100401 I915_WRITE(ch_ctl,
402 DP_AUX_CH_CTL_SEND_BUSY |
403 DP_AUX_CH_CTL_TIME_OUT_400us |
404 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
405 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
406 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
407 DP_AUX_CH_CTL_DONE |
408 DP_AUX_CH_CTL_TIME_OUT_ERROR |
409 DP_AUX_CH_CTL_RECEIVE_ERROR);
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700410 for (;;) {
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700411 status = I915_READ(ch_ctl);
412 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
413 break;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100414 udelay(100);
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700415 }
Akshay Joshi0206e352011-08-16 15:34:10 -0400416
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700417 /* Clear done status and any errors */
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100418 I915_WRITE(ch_ctl,
419 status |
420 DP_AUX_CH_CTL_DONE |
421 DP_AUX_CH_CTL_TIME_OUT_ERROR |
422 DP_AUX_CH_CTL_RECEIVE_ERROR);
423 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700424 break;
425 }
426
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700427 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700428 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700429 return -EBUSY;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700430 }
431
432 /* Check for timeout or receive error.
433 * Timeouts occur when the sink is not connected
434 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700435 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700436 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700437 return -EIO;
438 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700439
440 /* Timeouts occur when the device isn't connected, so they're
441 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700442 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800443 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Keith Packarda5b3da52009-06-11 22:30:32 -0700444 return -ETIMEDOUT;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700445 }
446
447 /* Unload any bytes sent back from the other side */
448 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
449 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700450 if (recv_bytes > recv_size)
451 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400452
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100453 for (i = 0; i < recv_bytes; i += 4)
454 unpack_aux(I915_READ(ch_data + i),
455 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700456
457 return recv_bytes;
458}
459
460/* Write data to the aux channel in native mode */
461static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100462intel_dp_aux_native_write(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
Keith Packard9b984da2011-09-19 13:54:47 -0700470 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
Zhenyu Wangeebc8632009-07-24 01:00:30 +0800475 msg[2] = address & 0xff;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700488 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700496 uint16_t address, uint8_t byte)
497{
Chris Wilsonea5b2132010-08-04 13:50:23 +0100498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700499}
500
501/* read bytes from a native aux channel */
502static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100503intel_dp_aux_native_read(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
Keith Packard9b984da2011-09-19 13:54:47 -0700513 intel_dp_check_edp(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700524 reply, reply_bytes);
Keith Packarda5b3da52009-06-11 22:30:32 -0700525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
Keith Packarda5b3da52009-06-11 22:30:32 -0700537 return -EIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700538 }
539}
540
541static int
Dave Airlieab2c0672009-12-04 10:55:24 +1000542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700544{
Dave Airlieab2c0672009-12-04 10:55:24 +1000545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
Dave Airlieab2c0672009-12-04 10:55:24 +1000549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
David Flynn8316f332010-12-08 16:10:21 +0000552 unsigned retry;
Dave Airlieab2c0672009-12-04 10:55:24 +1000553 int msg_bytes;
554 int reply_bytes;
555 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700556
Keith Packard9b984da2011-09-19 13:54:47 -0700557 intel_dp_check_edp(intel_dp);
Dave Airlieab2c0672009-12-04 10:55:24 +1000558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
566
567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
David Flynn8316f332010-12-08 16:10:21 +0000588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
Dave Airlieab2c0672009-12-04 10:55:24 +1000592 if (ret < 0) {
Dave Airlie3ff99162009-12-08 14:03:47 +1000593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
Dave Airlieab2c0672009-12-04 10:55:24 +1000594 return ret;
595 }
David Flynn8316f332010-12-08 16:10:21 +0000596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
Dave Airlieab2c0672009-12-04 10:55:24 +1000615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
David Flynn8316f332010-12-08 16:10:21 +0000622 DRM_DEBUG_KMS("aux_i2c nack\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
David Flynn8316f332010-12-08 16:10:21 +0000625 DRM_DEBUG_KMS("aux_i2c defer\n");
Dave Airlieab2c0672009-12-04 10:55:24 +1000626 udelay(100);
627 break;
628 default:
David Flynn8316f332010-12-08 16:10:21 +0000629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
Dave Airlieab2c0672009-12-04 10:55:24 +1000630 return -EREMOTEIO;
631 }
632 }
David Flynn8316f332010-12-08 16:10:21 +0000633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700636}
637
Keith Packard0b5c5412011-09-28 16:41:05 -0700638static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -0700639static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Keith Packard0b5c5412011-09-28 16:41:05 -0700640
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700641static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100642intel_dp_i2c_init(struct intel_dp *intel_dp,
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800643 struct intel_connector *intel_connector, const char *name)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700644{
Keith Packard0b5c5412011-09-28 16:41:05 -0700645 int ret;
646
Zhenyu Wangd54e9d22009-10-19 15:43:51 +0800647 DRM_DEBUG_KMS("i2c_init %s\n", name);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100648 intel_dp->algo.running = false;
649 intel_dp->algo.address = 0;
650 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700651
Akshay Joshi0206e352011-08-16 15:34:10 -0400652 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100653 intel_dp->adapter.owner = THIS_MODULE;
654 intel_dp->adapter.class = I2C_CLASS_DDC;
Akshay Joshi0206e352011-08-16 15:34:10 -0400655 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100656 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
657 intel_dp->adapter.algo_data = &intel_dp->algo;
658 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
659
Keith Packard0b5c5412011-09-28 16:41:05 -0700660 ironlake_edp_panel_vdd_on(intel_dp);
661 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
Keith Packardbd943152011-09-18 23:09:52 -0700662 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard0b5c5412011-09-28 16:41:05 -0700663 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700664}
665
666static bool
667intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
668 struct drm_display_mode *adjusted_mode)
669{
Zhao Yakui0d3a1bee2010-07-19 09:43:13 +0100670 struct drm_device *dev = encoder->dev;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100671 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700672 int lane_count, clock;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100673 int max_lane_count = intel_dp_max_lane_count(intel_dp);
674 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700675 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
676
Keith Packardd15456d2011-09-18 17:35:47 -0700677 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
678 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
Chris Wilson1d8e1c72010-08-07 11:01:28 +0100679 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
680 mode, adjusted_mode);
Zhao Yakui0d3a1bee2010-07-19 09:43:13 +0100681 /*
682 * the mode->clock is used to calculate the Data&Link M/N
683 * of the pipe. For the eDP the fixed clock should be used.
684 */
Keith Packardd15456d2011-09-18 17:35:47 -0700685 mode->clock = intel_dp->panel_fixed_mode->clock;
Zhao Yakui0d3a1bee2010-07-19 09:43:13 +0100686 }
687
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700688 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
689 for (clock = 0; clock <= max_clock; clock++) {
Dave Airliefe27d532010-06-30 11:46:17 +1000690 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700691
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400692 if (intel_dp_link_required(intel_dp, mode->clock)
Zhenyu Wang885a5fb2010-01-12 05:38:31 +0800693 <= link_avail) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100694 intel_dp->link_bw = bws[clock];
695 intel_dp->lane_count = lane_count;
696 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
Zhao Yakui28c97732009-10-09 11:39:41 +0800697 DRM_DEBUG_KMS("Display port link bw %02x lane "
698 "count %d clock %d\n",
Chris Wilsonea5b2132010-08-04 13:50:23 +0100699 intel_dp->link_bw, intel_dp->lane_count,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700700 adjusted_mode->clock);
701 return true;
702 }
703 }
704 }
Dave Airliefe27d532010-06-30 11:46:17 +1000705
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700706 return false;
707}
708
709struct intel_dp_m_n {
710 uint32_t tu;
711 uint32_t gmch_m;
712 uint32_t gmch_n;
713 uint32_t link_m;
714 uint32_t link_n;
715};
716
717static void
718intel_reduce_ratio(uint32_t *num, uint32_t *den)
719{
720 while (*num > 0xffffff || *den > 0xffffff) {
721 *num >>= 1;
722 *den >>= 1;
723 }
724}
725
726static void
Zhao Yakui36e83a12010-06-12 14:32:21 +0800727intel_dp_compute_m_n(int bpp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700728 int nlanes,
729 int pixel_clock,
730 int link_clock,
731 struct intel_dp_m_n *m_n)
732{
733 m_n->tu = 64;
Zhao Yakui36e83a12010-06-12 14:32:21 +0800734 m_n->gmch_m = (pixel_clock * bpp) >> 3;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700735 m_n->gmch_n = link_clock * nlanes;
736 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
737 m_n->link_m = pixel_clock;
738 m_n->link_n = link_clock;
739 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
740}
741
742void
743intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
744 struct drm_display_mode *adjusted_mode)
745{
746 struct drm_device *dev = crtc->dev;
747 struct drm_mode_config *mode_config = &dev->mode_config;
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800748 struct drm_encoder *encoder;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700749 struct drm_i915_private *dev_priv = dev->dev_private;
750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes858fa0352011-06-24 12:19:24 -0700751 int lane_count = 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700752 struct intel_dp_m_n m_n;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800753 int pipe = intel_crtc->pipe;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700754
755 /*
Eric Anholt21d40d32010-03-25 11:11:14 -0700756 * Find the lane count in the intel_encoder private
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700757 */
Zhenyu Wang55f78c42010-03-29 16:13:57 +0800758 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100759 struct intel_dp *intel_dp;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700760
Dan Carpenterd8201ab2010-05-07 10:39:00 +0200761 if (encoder->crtc != crtc)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700762 continue;
763
Chris Wilsonea5b2132010-08-04 13:50:23 +0100764 intel_dp = enc_to_intel_dp(encoder);
Keith Packard9a10f402011-11-02 13:03:47 -0700765 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
766 intel_dp->base.type == INTEL_OUTPUT_EDP)
767 {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100768 lane_count = intel_dp->lane_count;
Jesse Barnes51190662010-10-07 16:01:08 -0700769 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700770 }
771 }
772
773 /*
774 * Compute the GMCH and Link ratios. The '3' here is
775 * the number of bytes_per_pixel post-LUT, which we always
776 * set up for 8-bits of R/G/B, or 3 bytes total.
777 */
Jesse Barnes858fa0352011-06-24 12:19:24 -0700778 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700779 mode->clock, adjusted_mode->clock, &m_n);
780
Eric Anholtc619eed2010-01-28 16:45:52 -0800781 if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800782 I915_WRITE(TRANSDATA_M1(pipe),
783 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
784 m_n.gmch_m);
785 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
786 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
787 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700788 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800789 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
790 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
791 m_n.gmch_m);
792 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
793 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
794 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700795 }
796}
797
Keith Packardf01eca22011-09-28 16:48:10 -0700798static void ironlake_edp_pll_on(struct drm_encoder *encoder);
799static void ironlake_edp_pll_off(struct drm_encoder *encoder);
800
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700801static void
802intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
803 struct drm_display_mode *adjusted_mode)
804{
Zhenyu Wange3421a12010-04-08 09:43:27 +0800805 struct drm_device *dev = encoder->dev;
Keith Packard417e8222011-11-01 19:54:11 -0700806 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100807 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Chris Wilson4ef69c72010-09-09 15:14:28 +0100808 struct drm_crtc *crtc = intel_dp->base.base.crtc;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
810
Keith Packardf01eca22011-09-28 16:48:10 -0700811 /* Turn on the eDP PLL if needed */
812 if (is_edp(intel_dp)) {
813 if (!is_pch_edp(intel_dp))
814 ironlake_edp_pll_on(encoder);
815 else
816 ironlake_edp_pll_off(encoder);
817 }
818
Keith Packard417e8222011-11-01 19:54:11 -0700819 /*
Keith Packard1a2eb462011-11-16 16:26:07 -0800820 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -0700821 *
822 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -0800823 * SNB CPU
824 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -0700825 * CPT PCH
826 *
827 * IBX PCH and CPU are the same for almost everything,
828 * except that the CPU DP PLL is configured in this
829 * register
830 *
831 * CPT PCH is quite different, having many bits moved
832 * to the TRANS_DP_CTL register instead. That
833 * configuration happens (oddly) in ironlake_pch_enable
834 */
Adam Jackson9c9e7922010-04-05 17:57:59 -0400835
Keith Packard417e8222011-11-01 19:54:11 -0700836 /* Preserve the BIOS-computed detected bit. This is
837 * supposed to be read-only.
838 */
839 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
840 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700841
Keith Packard417e8222011-11-01 19:54:11 -0700842 /* Handle DP bits in common between all three register formats */
843
844 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700845
Chris Wilsonea5b2132010-08-04 13:50:23 +0100846 switch (intel_dp->lane_count) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700847 case 1:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100848 intel_dp->DP |= DP_PORT_WIDTH_1;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700849 break;
850 case 2:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100851 intel_dp->DP |= DP_PORT_WIDTH_2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700852 break;
853 case 4:
Chris Wilsonea5b2132010-08-04 13:50:23 +0100854 intel_dp->DP |= DP_PORT_WIDTH_4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700855 break;
856 }
Wu Fengguange0dac652011-09-05 14:25:34 +0800857 if (intel_dp->has_audio) {
858 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
859 pipe_name(intel_crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100860 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Wu Fengguange0dac652011-09-05 14:25:34 +0800861 intel_write_eld(encoder, adjusted_mode);
862 }
Chris Wilsonea5b2132010-08-04 13:50:23 +0100863 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
864 intel_dp->link_configuration[0] = intel_dp->link_bw;
865 intel_dp->link_configuration[1] = intel_dp->lane_count;
Adam Jacksona2cab1b2011-07-12 17:38:05 -0400866 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700867 /*
Adam Jackson9962c922010-05-13 14:45:42 -0400868 * Check for DPCD version > 1.1 and enhanced framing support
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700869 */
Jesse Barnes7183dc22011-07-07 11:10:58 -0700870 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
871 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100872 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700873 }
874
Keith Packard417e8222011-11-01 19:54:11 -0700875 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800876
Keith Packard1a2eb462011-11-16 16:26:07 -0800877 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 intel_dp->DP |= DP_SYNC_HS_HIGH;
880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
881 intel_dp->DP |= DP_SYNC_VS_HIGH;
882 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
883
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
886
887 intel_dp->DP |= intel_crtc->pipe << 29;
888
889 /* don't miss out required setting for eDP */
890 intel_dp->DP |= DP_PLL_ENABLE;
891 if (adjusted_mode->clock < 200000)
892 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893 else
894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
895 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
Keith Packard417e8222011-11-01 19:54:11 -0700896 intel_dp->DP |= intel_dp->color_range;
897
898 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
899 intel_dp->DP |= DP_SYNC_HS_HIGH;
900 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
901 intel_dp->DP |= DP_SYNC_VS_HIGH;
902 intel_dp->DP |= DP_LINK_TRAIN_OFF;
903
904 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
905 intel_dp->DP |= DP_ENHANCED_FRAMING;
906
907 if (intel_crtc->pipe == 1)
908 intel_dp->DP |= DP_PIPEB_SELECT;
909
910 if (is_cpu_edp(intel_dp)) {
911 /* don't miss out required setting for eDP */
912 intel_dp->DP |= DP_PLL_ENABLE;
913 if (adjusted_mode->clock < 200000)
914 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915 else
916 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
917 }
918 } else {
919 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800920 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700921}
922
Keith Packard99ea7122011-11-01 19:57:50 -0700923#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
924#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
925
926#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
927#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
928
929#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
930#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
931
932static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
933 u32 mask,
934 u32 value)
935{
936 struct drm_device *dev = intel_dp->base.base.dev;
937 struct drm_i915_private *dev_priv = dev->dev_private;
938
939 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
940 mask, value,
941 I915_READ(PCH_PP_STATUS),
942 I915_READ(PCH_PP_CONTROL));
943
944 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
945 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
946 I915_READ(PCH_PP_STATUS),
947 I915_READ(PCH_PP_CONTROL));
948 }
949}
950
951static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
952{
953 DRM_DEBUG_KMS("Wait for panel power on\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
955}
956
Keith Packardbd943152011-09-18 23:09:52 -0700957static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
958{
Keith Packardbd943152011-09-18 23:09:52 -0700959 DRM_DEBUG_KMS("Wait for panel power off time\n");
Keith Packard99ea7122011-11-01 19:57:50 -0700960 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -0700961}
Keith Packardbd943152011-09-18 23:09:52 -0700962
Keith Packard99ea7122011-11-01 19:57:50 -0700963static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
964{
965 DRM_DEBUG_KMS("Wait for panel power cycle\n");
966 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
967}
Keith Packardbd943152011-09-18 23:09:52 -0700968
Keith Packard99ea7122011-11-01 19:57:50 -0700969
Keith Packard832dd3c2011-11-01 19:34:06 -0700970/* Read the current pp_control value, unlocking the register if it
971 * is locked
972 */
973
974static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
975{
976 u32 control = I915_READ(PCH_PP_CONTROL);
977
978 control &= ~PANEL_UNLOCK_MASK;
979 control |= PANEL_UNLOCK_REGS;
980 return control;
Keith Packardbd943152011-09-18 23:09:52 -0700981}
982
Jesse Barnes5d613502011-01-24 17:10:54 -0800983static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
984{
985 struct drm_device *dev = intel_dp->base.base.dev;
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 u32 pp;
988
Keith Packard97af61f572011-09-28 16:23:51 -0700989 if (!is_edp(intel_dp))
990 return;
Keith Packardf01eca22011-09-28 16:48:10 -0700991 DRM_DEBUG_KMS("Turn eDP VDD on\n");
Jesse Barnes5d613502011-01-24 17:10:54 -0800992
Keith Packardbd943152011-09-18 23:09:52 -0700993 WARN(intel_dp->want_panel_vdd,
994 "eDP VDD already requested on\n");
995
996 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -0700997
Keith Packardbd943152011-09-18 23:09:52 -0700998 if (ironlake_edp_have_panel_vdd(intel_dp)) {
999 DRM_DEBUG_KMS("eDP VDD already on\n");
1000 return;
1001 }
1002
Keith Packard99ea7122011-11-01 19:57:50 -07001003 if (!ironlake_edp_have_panel_power(intel_dp))
1004 ironlake_wait_panel_power_cycle(intel_dp);
1005
Keith Packard832dd3c2011-11-01 19:34:06 -07001006 pp = ironlake_get_pp_control(dev_priv);
Jesse Barnes5d613502011-01-24 17:10:54 -08001007 pp |= EDP_FORCE_VDD;
1008 I915_WRITE(PCH_PP_CONTROL, pp);
1009 POSTING_READ(PCH_PP_CONTROL);
Keith Packardf01eca22011-09-28 16:48:10 -07001010 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1011 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
Keith Packardebf33b12011-09-29 15:53:27 -07001012
1013 /*
1014 * If the panel wasn't on, delay before accessing aux channel
1015 */
1016 if (!ironlake_edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -07001017 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -07001018 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001019 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001020}
1021
Keith Packardbd943152011-09-18 23:09:52 -07001022static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001023{
1024 struct drm_device *dev = intel_dp->base.base.dev;
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 u32 pp;
1027
Keith Packardbd943152011-09-18 23:09:52 -07001028 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
Keith Packard832dd3c2011-11-01 19:34:06 -07001029 pp = ironlake_get_pp_control(dev_priv);
Keith Packardbd943152011-09-18 23:09:52 -07001030 pp &= ~EDP_FORCE_VDD;
1031 I915_WRITE(PCH_PP_CONTROL, pp);
1032 POSTING_READ(PCH_PP_CONTROL);
Jesse Barnes5d613502011-01-24 17:10:54 -08001033
Keith Packardbd943152011-09-18 23:09:52 -07001034 /* Make sure sequencer is idle before allowing subsequent activity */
1035 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1036 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
Keith Packard99ea7122011-11-01 19:57:50 -07001037
1038 msleep(intel_dp->panel_power_down_delay);
Keith Packardbd943152011-09-18 23:09:52 -07001039 }
1040}
1041
1042static void ironlake_panel_vdd_work(struct work_struct *__work)
1043{
1044 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1045 struct intel_dp, panel_vdd_work);
1046 struct drm_device *dev = intel_dp->base.base.dev;
1047
Keith Packard627f7672011-10-31 11:30:10 -07001048 mutex_lock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001049 ironlake_panel_vdd_off_sync(intel_dp);
Keith Packard627f7672011-10-31 11:30:10 -07001050 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001051}
1052
1053static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1054{
Keith Packard97af61f572011-09-28 16:23:51 -07001055 if (!is_edp(intel_dp))
1056 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001057
Keith Packardbd943152011-09-18 23:09:52 -07001058 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1059 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
Keith Packardf2e8b182011-11-01 20:01:35 -07001060
Keith Packardbd943152011-09-18 23:09:52 -07001061 intel_dp->want_panel_vdd = false;
1062
1063 if (sync) {
1064 ironlake_panel_vdd_off_sync(intel_dp);
1065 } else {
1066 /*
1067 * Queue the timer to fire a long
1068 * time from now (relative to the power down delay)
1069 * to keep the panel power up across a sequence of operations
1070 */
1071 schedule_delayed_work(&intel_dp->panel_vdd_work,
1072 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1073 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001074}
1075
Keith Packard86a30732011-10-20 13:40:33 -07001076static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001077{
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001078 struct drm_device *dev = intel_dp->base.base.dev;
Jesse Barnes9934c132010-07-22 13:18:19 -07001079 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001080 u32 pp;
Jesse Barnes9934c132010-07-22 13:18:19 -07001081
Keith Packard97af61f572011-09-28 16:23:51 -07001082 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001083 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001084
1085 DRM_DEBUG_KMS("Turn eDP power on\n");
1086
1087 if (ironlake_edp_have_panel_power(intel_dp)) {
1088 DRM_DEBUG_KMS("eDP power already on\n");
Keith Packard7d639f32011-09-29 16:05:34 -07001089 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001090 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001091
Keith Packard99ea7122011-11-01 19:57:50 -07001092 ironlake_wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001093
Keith Packard832dd3c2011-11-01 19:34:06 -07001094 pp = ironlake_get_pp_control(dev_priv);
Keith Packard05ce1a42011-09-29 16:33:01 -07001095 if (IS_GEN5(dev)) {
1096 /* ILK workaround: disable reset around power sequence */
1097 pp &= ~PANEL_POWER_RESET;
1098 I915_WRITE(PCH_PP_CONTROL, pp);
1099 POSTING_READ(PCH_PP_CONTROL);
1100 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001101
Keith Packard1c0ae802011-09-19 13:59:29 -07001102 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07001103 if (!IS_GEN5(dev))
1104 pp |= PANEL_POWER_RESET;
1105
Jesse Barnes9934c132010-07-22 13:18:19 -07001106 I915_WRITE(PCH_PP_CONTROL, pp);
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001107 POSTING_READ(PCH_PP_CONTROL);
Jesse Barnes9934c132010-07-22 13:18:19 -07001108
Keith Packard99ea7122011-11-01 19:57:50 -07001109 ironlake_wait_panel_on(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001110
Keith Packard05ce1a42011-09-29 16:33:01 -07001111 if (IS_GEN5(dev)) {
1112 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001116}
1117
Keith Packard99ea7122011-11-01 19:57:50 -07001118static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001119{
Keith Packard99ea7122011-11-01 19:57:50 -07001120 struct drm_device *dev = intel_dp->base.base.dev;
Jesse Barnes9934c132010-07-22 13:18:19 -07001121 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001122 u32 pp;
Jesse Barnes9934c132010-07-22 13:18:19 -07001123
Keith Packard97af61f572011-09-28 16:23:51 -07001124 if (!is_edp(intel_dp))
1125 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001126
Keith Packard99ea7122011-11-01 19:57:50 -07001127 DRM_DEBUG_KMS("Turn eDP power off\n");
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001128
Keith Packard99ea7122011-11-01 19:57:50 -07001129 WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
Jesse Barnes9934c132010-07-22 13:18:19 -07001130
Keith Packard832dd3c2011-11-01 19:34:06 -07001131 pp = ironlake_get_pp_control(dev_priv);
Keith Packard99ea7122011-11-01 19:57:50 -07001132 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1133 I915_WRITE(PCH_PP_CONTROL, pp);
1134 POSTING_READ(PCH_PP_CONTROL);
Jesse Barnes9934c132010-07-22 13:18:19 -07001135
Keith Packard99ea7122011-11-01 19:57:50 -07001136 ironlake_wait_panel_off(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001137}
1138
Keith Packard86a30732011-10-20 13:40:33 -07001139static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001140{
Keith Packardf01eca22011-09-28 16:48:10 -07001141 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 u32 pp;
1144
Keith Packardf01eca22011-09-28 16:48:10 -07001145 if (!is_edp(intel_dp))
1146 return;
1147
Zhao Yakui28c97732009-10-09 11:39:41 +08001148 DRM_DEBUG_KMS("\n");
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001149 /*
1150 * If we enable the backlight right away following a panel power
1151 * on, we may see slight flicker as the panel syncs with the eDP
1152 * link. So delay a bit to make sure the image is solid before
1153 * allowing it to appear.
1154 */
Keith Packardf01eca22011-09-28 16:48:10 -07001155 msleep(intel_dp->backlight_on_delay);
Keith Packard832dd3c2011-11-01 19:34:06 -07001156 pp = ironlake_get_pp_control(dev_priv);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001157 pp |= EDP_BLC_ENABLE;
1158 I915_WRITE(PCH_PP_CONTROL, pp);
Keith Packardf01eca22011-09-28 16:48:10 -07001159 POSTING_READ(PCH_PP_CONTROL);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001160}
1161
Keith Packard86a30732011-10-20 13:40:33 -07001162static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001163{
Keith Packardf01eca22011-09-28 16:48:10 -07001164 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 pp;
1167
Keith Packardf01eca22011-09-28 16:48:10 -07001168 if (!is_edp(intel_dp))
1169 return;
1170
Zhao Yakui28c97732009-10-09 11:39:41 +08001171 DRM_DEBUG_KMS("\n");
Keith Packard832dd3c2011-11-01 19:34:06 -07001172 pp = ironlake_get_pp_control(dev_priv);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001173 pp &= ~EDP_BLC_ENABLE;
1174 I915_WRITE(PCH_PP_CONTROL, pp);
Keith Packardf01eca22011-09-28 16:48:10 -07001175 POSTING_READ(PCH_PP_CONTROL);
1176 msleep(intel_dp->backlight_off_delay);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001177}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001178
Jesse Barnesd240f202010-08-13 15:43:26 -07001179static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1180{
1181 struct drm_device *dev = encoder->dev;
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 dpa_ctl;
1184
1185 DRM_DEBUG_KMS("\n");
1186 dpa_ctl = I915_READ(DP_A);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001187 dpa_ctl |= DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001188 I915_WRITE(DP_A, dpa_ctl);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001189 POSTING_READ(DP_A);
1190 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001191}
1192
1193static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1194{
1195 struct drm_device *dev = encoder->dev;
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 u32 dpa_ctl;
1198
1199 dpa_ctl = I915_READ(DP_A);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001200 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001201 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001202 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001203 udelay(200);
1204}
1205
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001206/* If the sink supports it, try to set the power state appropriately */
1207static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1208{
1209 int ret, i;
1210
1211 /* Should have a valid DPCD by this point */
1212 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1213 return;
1214
1215 if (mode != DRM_MODE_DPMS_ON) {
1216 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1217 DP_SET_POWER_D3);
1218 if (ret != 1)
1219 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1220 } else {
1221 /*
1222 * When turning on, we need to retry for 1ms to give the sink
1223 * time to wake up.
1224 */
1225 for (i = 0; i < 3; i++) {
1226 ret = intel_dp_aux_native_write_1(intel_dp,
1227 DP_SET_POWER,
1228 DP_SET_POWER_D0);
1229 if (ret == 1)
1230 break;
1231 msleep(1);
1232 }
1233 }
1234}
1235
Jesse Barnesd240f202010-08-13 15:43:26 -07001236static void intel_dp_prepare(struct drm_encoder *encoder)
1237{
1238 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jesse Barnesd240f202010-08-13 15:43:26 -07001239
Keith Packard21264c62011-11-01 20:25:21 -07001240 ironlake_edp_backlight_off(intel_dp);
1241 ironlake_edp_panel_off(intel_dp);
1242
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001243 /* Wake up the sink first */
Keith Packardf58ff852011-09-28 16:44:14 -07001244 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001245 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Keith Packard21264c62011-11-01 20:25:21 -07001246 intel_dp_link_down(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001247 ironlake_edp_panel_vdd_off(intel_dp, false);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001248
Keith Packardf01eca22011-09-28 16:48:10 -07001249 /* Make sure the panel is off before trying to
1250 * change the mode
1251 */
Jesse Barnesd240f202010-08-13 15:43:26 -07001252}
1253
1254static void intel_dp_commit(struct drm_encoder *encoder)
1255{
1256 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Jesse Barnesd4270e52011-10-11 10:43:02 -07001257 struct drm_device *dev = encoder->dev;
1258 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
Jesse Barnesd240f202010-08-13 15:43:26 -07001259
Keith Packard97af61f572011-09-28 16:23:51 -07001260 ironlake_edp_panel_vdd_on(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001261 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001262 intel_dp_start_link_train(intel_dp);
Keith Packard97af61f572011-09-28 16:23:51 -07001263 ironlake_edp_panel_on(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001264 ironlake_edp_panel_vdd_off(intel_dp, true);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001265 intel_dp_complete_link_train(intel_dp);
Keith Packardf01eca22011-09-28 16:48:10 -07001266 ironlake_edp_backlight_on(intel_dp);
Keith Packardd2b996a2011-07-25 22:37:51 -07001267
1268 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
Jesse Barnesd4270e52011-10-11 10:43:02 -07001269
1270 if (HAS_PCH_CPT(dev))
1271 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnesd240f202010-08-13 15:43:26 -07001272}
1273
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001274static void
1275intel_dp_dpms(struct drm_encoder *encoder, int mode)
1276{
Chris Wilsonea5b2132010-08-04 13:50:23 +01001277 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08001278 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001279 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001280 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001281
1282 if (mode != DRM_MODE_DPMS_ON) {
Keith Packard21264c62011-11-01 20:25:21 -07001283 ironlake_edp_backlight_off(intel_dp);
1284 ironlake_edp_panel_off(intel_dp);
1285
Keith Packard245e2702011-10-05 19:53:09 -07001286 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001287 intel_dp_sink_dpms(intel_dp, mode);
Jesse Barnes736085b2010-10-08 10:35:55 -07001288 intel_dp_link_down(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001289 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard21264c62011-11-01 20:25:21 -07001290
1291 if (is_cpu_edp(intel_dp))
1292 ironlake_edp_pll_off(encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001293 } else {
Keith Packard21264c62011-11-01 20:25:21 -07001294 if (is_cpu_edp(intel_dp))
1295 ironlake_edp_pll_on(encoder);
1296
Keith Packard97af61f572011-09-28 16:23:51 -07001297 ironlake_edp_panel_vdd_on(intel_dp);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001298 intel_dp_sink_dpms(intel_dp, mode);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001299 if (!(dp_reg & DP_PORT_EN)) {
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001300 intel_dp_start_link_train(intel_dp);
Keith Packard97af61f572011-09-28 16:23:51 -07001301 ironlake_edp_panel_on(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001302 ironlake_edp_panel_vdd_off(intel_dp, true);
Jesse Barnes33a34e42010-09-08 12:42:02 -07001303 intel_dp_complete_link_train(intel_dp);
Keith Packardbee7eb22011-09-28 16:28:00 -07001304 } else
Keith Packardbd943152011-09-18 23:09:52 -07001305 ironlake_edp_panel_vdd_off(intel_dp, false);
1306 ironlake_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001307 }
Keith Packardd2b996a2011-07-25 22:37:51 -07001308 intel_dp->dpms_mode = mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001309}
1310
1311/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001312 * Native read with retry for link status and receiver capability reads for
1313 * cases where the sink may still be asleep.
1314 */
1315static bool
1316intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1317 uint8_t *recv, int recv_bytes)
1318{
1319 int ret, i;
1320
1321 /*
1322 * Sinks are *supposed* to come up within 1ms from an off state,
1323 * but we're also supposed to retry 3 times per the spec.
1324 */
1325 for (i = 0; i < 3; i++) {
1326 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1327 recv_bytes);
1328 if (ret == recv_bytes)
1329 return true;
1330 msleep(1);
1331 }
1332
1333 return false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001334}
1335
1336/*
1337 * Fetch AUX CH registers 0x202 - 0x207 which contain
1338 * link status information
1339 */
1340static bool
Keith Packard93f62da2011-11-01 19:45:03 -07001341intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001342{
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001343 return intel_dp_aux_native_read_retry(intel_dp,
1344 DP_LANE0_1_STATUS,
Keith Packard93f62da2011-11-01 19:45:03 -07001345 link_status,
Jesse Barnesdf0c2372011-07-07 11:11:02 -07001346 DP_LINK_STATUS_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001347}
1348
1349static uint8_t
1350intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1351 int r)
1352{
1353 return link_status[r - DP_LANE0_1_STATUS];
1354}
1355
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001356static uint8_t
Keith Packard93f62da2011-11-01 19:45:03 -07001357intel_get_adjust_request_voltage(uint8_t adjust_request[2],
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001358 int lane)
1359{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001360 int s = ((lane & 1) ?
1361 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1362 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
Keith Packard93f62da2011-11-01 19:45:03 -07001363 uint8_t l = adjust_request[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001364
1365 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1366}
1367
1368static uint8_t
Keith Packard93f62da2011-11-01 19:45:03 -07001369intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001370 int lane)
1371{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001372 int s = ((lane & 1) ?
1373 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1374 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
Keith Packard93f62da2011-11-01 19:45:03 -07001375 uint8_t l = adjust_request[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001376
1377 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1378}
1379
1380
1381#if 0
1382static char *voltage_names[] = {
1383 "0.4V", "0.6V", "0.8V", "1.2V"
1384};
1385static char *pre_emph_names[] = {
1386 "0dB", "3.5dB", "6dB", "9.5dB"
1387};
1388static char *link_train_names[] = {
1389 "pattern 1", "pattern 2", "idle", "off"
1390};
1391#endif
1392
1393/*
1394 * These are source-specific values; current Intel hardware supports
1395 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1396 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001397
1398static uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08001399intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001400{
Keith Packard1a2eb462011-11-16 16:26:07 -08001401 struct drm_device *dev = intel_dp->base.base.dev;
1402
1403 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1404 return DP_TRAIN_VOLTAGE_SWING_800;
1405 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1406 return DP_TRAIN_VOLTAGE_SWING_1200;
1407 else
1408 return DP_TRAIN_VOLTAGE_SWING_800;
1409}
1410
1411static uint8_t
1412intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1413{
1414 struct drm_device *dev = intel_dp->base.base.dev;
1415
1416 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1417 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1418 case DP_TRAIN_VOLTAGE_SWING_400:
1419 return DP_TRAIN_PRE_EMPHASIS_6;
1420 case DP_TRAIN_VOLTAGE_SWING_600:
1421 case DP_TRAIN_VOLTAGE_SWING_800:
1422 return DP_TRAIN_PRE_EMPHASIS_3_5;
1423 default:
1424 return DP_TRAIN_PRE_EMPHASIS_0;
1425 }
1426 } else {
1427 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1428 case DP_TRAIN_VOLTAGE_SWING_400:
1429 return DP_TRAIN_PRE_EMPHASIS_6;
1430 case DP_TRAIN_VOLTAGE_SWING_600:
1431 return DP_TRAIN_PRE_EMPHASIS_6;
1432 case DP_TRAIN_VOLTAGE_SWING_800:
1433 return DP_TRAIN_PRE_EMPHASIS_3_5;
1434 case DP_TRAIN_VOLTAGE_SWING_1200:
1435 default:
1436 return DP_TRAIN_PRE_EMPHASIS_0;
1437 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001438 }
1439}
1440
1441static void
Keith Packard93f62da2011-11-01 19:45:03 -07001442intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001443{
1444 uint8_t v = 0;
1445 uint8_t p = 0;
1446 int lane;
Keith Packard93f62da2011-11-01 19:45:03 -07001447 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
Keith Packard1a2eb462011-11-16 16:26:07 -08001448 uint8_t voltage_max;
1449 uint8_t preemph_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001450
Jesse Barnes33a34e42010-09-08 12:42:02 -07001451 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Keith Packard93f62da2011-11-01 19:45:03 -07001452 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1453 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001454
1455 if (this_v > v)
1456 v = this_v;
1457 if (this_p > p)
1458 p = this_p;
1459 }
1460
Keith Packard1a2eb462011-11-16 16:26:07 -08001461 voltage_max = intel_dp_voltage_max(intel_dp);
Keith Packard417e8222011-11-01 19:54:11 -07001462 if (v >= voltage_max)
1463 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001464
Keith Packard1a2eb462011-11-16 16:26:07 -08001465 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1466 if (p >= preemph_max)
1467 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001468
1469 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07001470 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001471}
1472
1473static uint32_t
Keith Packard93f62da2011-11-01 19:45:03 -07001474intel_dp_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001475{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001476 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001477
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001478 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001479 case DP_TRAIN_VOLTAGE_SWING_400:
1480 default:
1481 signal_levels |= DP_VOLTAGE_0_4;
1482 break;
1483 case DP_TRAIN_VOLTAGE_SWING_600:
1484 signal_levels |= DP_VOLTAGE_0_6;
1485 break;
1486 case DP_TRAIN_VOLTAGE_SWING_800:
1487 signal_levels |= DP_VOLTAGE_0_8;
1488 break;
1489 case DP_TRAIN_VOLTAGE_SWING_1200:
1490 signal_levels |= DP_VOLTAGE_1_2;
1491 break;
1492 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001493 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001494 case DP_TRAIN_PRE_EMPHASIS_0:
1495 default:
1496 signal_levels |= DP_PRE_EMPHASIS_0;
1497 break;
1498 case DP_TRAIN_PRE_EMPHASIS_3_5:
1499 signal_levels |= DP_PRE_EMPHASIS_3_5;
1500 break;
1501 case DP_TRAIN_PRE_EMPHASIS_6:
1502 signal_levels |= DP_PRE_EMPHASIS_6;
1503 break;
1504 case DP_TRAIN_PRE_EMPHASIS_9_5:
1505 signal_levels |= DP_PRE_EMPHASIS_9_5;
1506 break;
1507 }
1508 return signal_levels;
1509}
1510
Zhenyu Wange3421a12010-04-08 09:43:27 +08001511/* Gen6's DP voltage swing and pre-emphasis control */
1512static uint32_t
1513intel_gen6_edp_signal_levels(uint8_t train_set)
1514{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001515 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1516 DP_TRAIN_PRE_EMPHASIS_MASK);
1517 switch (signal_levels) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08001518 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001519 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1520 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1521 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1522 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001523 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001524 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1525 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001526 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001527 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1528 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001529 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001530 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1531 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001532 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08001533 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1534 "0x%x\n", signal_levels);
1535 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001536 }
1537}
1538
Keith Packard1a2eb462011-11-16 16:26:07 -08001539/* Gen7's DP voltage swing and pre-emphasis control */
1540static uint32_t
1541intel_gen7_edp_signal_levels(uint8_t train_set)
1542{
1543 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1544 DP_TRAIN_PRE_EMPHASIS_MASK);
1545 switch (signal_levels) {
1546 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1547 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1548 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1549 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1550 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1551 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1552
1553 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1554 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1555 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1556 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1557
1558 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1559 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1560 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1561 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1562
1563 default:
1564 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1565 "0x%x\n", signal_levels);
1566 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1567 }
1568}
1569
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001570static uint8_t
1571intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1572 int lane)
1573{
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001574 int s = (lane & 1) * 4;
Keith Packard93f62da2011-11-01 19:45:03 -07001575 uint8_t l = link_status[lane>>1];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001576
1577 return (l >> s) & 0xf;
1578}
1579
1580/* Check for clock recovery is done on all channels */
1581static bool
1582intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1583{
1584 int lane;
1585 uint8_t lane_status;
1586
1587 for (lane = 0; lane < lane_count; lane++) {
1588 lane_status = intel_get_lane_status(link_status, lane);
1589 if ((lane_status & DP_LANE_CR_DONE) == 0)
1590 return false;
1591 }
1592 return true;
1593}
1594
1595/* Check to see if channel eq is done on all channels */
1596#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1597 DP_LANE_CHANNEL_EQ_DONE|\
1598 DP_LANE_SYMBOL_LOCKED)
1599static bool
Keith Packard93f62da2011-11-01 19:45:03 -07001600intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001601{
1602 uint8_t lane_align;
1603 uint8_t lane_status;
1604 int lane;
1605
Keith Packard93f62da2011-11-01 19:45:03 -07001606 lane_align = intel_dp_link_status(link_status,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001607 DP_LANE_ALIGN_STATUS_UPDATED);
1608 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1609 return false;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001610 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Keith Packard93f62da2011-11-01 19:45:03 -07001611 lane_status = intel_get_lane_status(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001612 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1613 return false;
1614 }
1615 return true;
1616}
1617
1618static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01001619intel_dp_set_link_train(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001620 uint32_t dp_reg_value,
Chris Wilson58e10eb2010-10-03 10:56:11 +01001621 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001622{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001623 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001624 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001625 int ret;
1626
Chris Wilsonea5b2132010-08-04 13:50:23 +01001627 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1628 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001629
Chris Wilsonea5b2132010-08-04 13:50:23 +01001630 intel_dp_aux_native_write_1(intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001631 DP_TRAINING_PATTERN_SET,
1632 dp_train_pat);
1633
Chris Wilsonea5b2132010-08-04 13:50:23 +01001634 ret = intel_dp_aux_native_write(intel_dp,
Chris Wilson58e10eb2010-10-03 10:56:11 +01001635 DP_TRAINING_LANE0_SET,
Keith Packardb34f1f02011-11-02 10:17:59 -07001636 intel_dp->train_set,
1637 intel_dp->lane_count);
1638 if (ret != intel_dp->lane_count)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001639 return false;
1640
1641 return true;
1642}
1643
Jesse Barnes33a34e42010-09-08 12:42:02 -07001644/* Enable corresponding port and start training pattern 1 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001645static void
Jesse Barnes33a34e42010-09-08 12:42:02 -07001646intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001647{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001648 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001649 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001650 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001651 int i;
1652 uint8_t voltage;
1653 bool clock_recovery = false;
Keith Packardcdb0e952011-11-01 20:00:06 -07001654 int voltage_tries, loop_tries;
Zhenyu Wange3421a12010-04-08 09:43:27 +08001655 u32 reg;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001656 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001657
Adam Jacksone8519462011-07-21 17:48:38 -04001658 /*
1659 * On CPT we have to enable the port in training pattern 1, which
1660 * will happen below in intel_dp_set_link_train. Otherwise, enable
1661 * the port and wait for it to become active.
1662 */
1663 if (!HAS_PCH_CPT(dev)) {
1664 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1665 POSTING_READ(intel_dp->output_reg);
1666 intel_wait_for_vblank(dev, intel_crtc->pipe);
1667 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001668
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001669 /* Write the link configuration data */
1670 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1671 intel_dp->link_configuration,
1672 DP_LINK_CONFIGURATION_SIZE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001673
1674 DP |= DP_PORT_EN;
Keith Packard1a2eb462011-11-16 16:26:07 -08001675
1676 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001677 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1678 else
1679 DP &= ~DP_LINK_TRAIN_MASK;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001680 memset(intel_dp->train_set, 0, 4);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001681 voltage = 0xff;
Keith Packardcdb0e952011-11-01 20:00:06 -07001682 voltage_tries = 0;
1683 loop_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001684 clock_recovery = false;
1685 for (;;) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001686 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
Keith Packard93f62da2011-11-01 19:45:03 -07001687 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08001688 uint32_t signal_levels;
Keith Packard417e8222011-11-01 19:54:11 -07001689
Keith Packard1a2eb462011-11-16 16:26:07 -08001690
1691 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1692 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1693 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1694 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001695 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001696 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1697 } else {
Keith Packard93f62da2011-11-01 19:45:03 -07001698 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1699 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001700 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1701 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001702
Keith Packard1a2eb462011-11-16 16:26:07 -08001703 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001704 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1705 else
1706 reg = DP | DP_LINK_TRAIN_PAT_1;
1707
Chris Wilsonea5b2132010-08-04 13:50:23 +01001708 if (!intel_dp_set_link_train(intel_dp, reg,
Adam Jackson81055852011-07-21 17:48:37 -04001709 DP_TRAINING_PATTERN_1 |
1710 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001711 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001712 /* Set training pattern 1 */
1713
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001714 udelay(100);
Keith Packard93f62da2011-11-01 19:45:03 -07001715 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1716 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001717 break;
Keith Packard93f62da2011-11-01 19:45:03 -07001718 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001719
Keith Packard93f62da2011-11-01 19:45:03 -07001720 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1721 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001722 clock_recovery = true;
1723 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001724 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001725
1726 /* Check to see if we've tried the max voltage */
1727 for (i = 0; i < intel_dp->lane_count; i++)
1728 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1729 break;
Keith Packardcdb0e952011-11-01 20:00:06 -07001730 if (i == intel_dp->lane_count) {
1731 ++loop_tries;
1732 if (loop_tries == 5) {
1733 DRM_DEBUG_KMS("too many full retries, give up\n");
1734 break;
1735 }
1736 memset(intel_dp->train_set, 0, 4);
1737 voltage_tries = 0;
1738 continue;
1739 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001740
1741 /* Check to see if we've tried the same voltage 5 times */
1742 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
Keith Packardcdb0e952011-11-01 20:00:06 -07001743 ++voltage_tries;
1744 if (voltage_tries == 5) {
1745 DRM_DEBUG_KMS("too many voltage retries, give up\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001746 break;
Keith Packardcdb0e952011-11-01 20:00:06 -07001747 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001748 } else
Keith Packardcdb0e952011-11-01 20:00:06 -07001749 voltage_tries = 0;
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001750 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1751
1752 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07001753 intel_get_adjust_train(intel_dp, link_status);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001754 }
1755
Jesse Barnes33a34e42010-09-08 12:42:02 -07001756 intel_dp->DP = DP;
1757}
1758
1759static void
1760intel_dp_complete_link_train(struct intel_dp *intel_dp)
1761{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001762 struct drm_device *dev = intel_dp->base.base.dev;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08001765 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07001766 u32 reg;
1767 uint32_t DP = intel_dp->DP;
1768
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001769 /* channel equalization */
1770 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08001771 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001772 channel_eq = false;
1773 for (;;) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001774 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
Zhenyu Wange3421a12010-04-08 09:43:27 +08001775 uint32_t signal_levels;
Keith Packard93f62da2011-11-01 19:45:03 -07001776 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08001777
Jesse Barnes37f80972011-01-05 14:45:24 -08001778 if (cr_tries > 5) {
1779 DRM_ERROR("failed to train DP, aborting\n");
1780 intel_dp_link_down(intel_dp);
1781 break;
1782 }
1783
Keith Packard1a2eb462011-11-16 16:26:07 -08001784 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1785 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1786 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1787 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
Jesse Barnes33a34e42010-09-08 12:42:02 -07001788 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001789 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1790 } else {
Keith Packard93f62da2011-11-01 19:45:03 -07001791 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001792 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1793 }
1794
Keith Packard1a2eb462011-11-16 16:26:07 -08001795 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001796 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1797 else
1798 reg = DP | DP_LINK_TRAIN_PAT_2;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001799
1800 /* channel eq pattern */
Chris Wilsonea5b2132010-08-04 13:50:23 +01001801 if (!intel_dp_set_link_train(intel_dp, reg,
Adam Jackson81055852011-07-21 17:48:37 -04001802 DP_TRAINING_PATTERN_2 |
1803 DP_LINK_SCRAMBLING_DISABLE))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001804 break;
1805
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001806 udelay(400);
Keith Packard93f62da2011-11-01 19:45:03 -07001807 if (!intel_dp_get_link_status(intel_dp, link_status))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001808 break;
Jesse Barnes869184a2010-10-07 16:01:22 -07001809
Jesse Barnes37f80972011-01-05 14:45:24 -08001810 /* Make sure clock is still ok */
Keith Packard93f62da2011-11-01 19:45:03 -07001811 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08001812 intel_dp_start_link_train(intel_dp);
1813 cr_tries++;
1814 continue;
1815 }
1816
Keith Packard93f62da2011-11-01 19:45:03 -07001817 if (intel_channel_eq_ok(intel_dp, link_status)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001818 channel_eq = true;
1819 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001820 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001821
Jesse Barnes37f80972011-01-05 14:45:24 -08001822 /* Try 5 times, then try clock recovery if that fails */
1823 if (tries > 5) {
1824 intel_dp_link_down(intel_dp);
1825 intel_dp_start_link_train(intel_dp);
1826 tries = 0;
1827 cr_tries++;
1828 continue;
1829 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001830
1831 /* Compute new intel_dp->train_set as requested by target */
Keith Packard93f62da2011-11-01 19:45:03 -07001832 intel_get_adjust_train(intel_dp, link_status);
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001833 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001834 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00001835
Keith Packard1a2eb462011-11-16 16:26:07 -08001836 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
Zhenyu Wange3421a12010-04-08 09:43:27 +08001837 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1838 else
1839 reg = DP | DP_LINK_TRAIN_OFF;
1840
Chris Wilsonea5b2132010-08-04 13:50:23 +01001841 I915_WRITE(intel_dp->output_reg, reg);
1842 POSTING_READ(intel_dp->output_reg);
1843 intel_dp_aux_native_write_1(intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001844 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1845}
1846
1847static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01001848intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001849{
Chris Wilson4ef69c72010-09-09 15:14:28 +01001850 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001851 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001852 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001853
Chris Wilson1b39d6f2010-12-06 11:20:45 +00001854 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1855 return;
1856
Zhao Yakui28c97732009-10-09 11:39:41 +08001857 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001858
Jesse Barnescfcb0fc2010-10-07 16:01:06 -07001859 if (is_edp(intel_dp)) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001860 DP &= ~DP_PLL_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001861 I915_WRITE(intel_dp->output_reg, DP);
1862 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001863 udelay(100);
1864 }
1865
Keith Packard1a2eb462011-11-16 16:26:07 -08001866 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08001867 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001868 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001869 } else {
1870 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001871 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08001872 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01001873 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001874
Chris Wilsonfe255d02010-09-11 21:37:48 +01001875 msleep(17);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08001876
Keith Packard417e8222011-11-01 19:54:11 -07001877 if (is_edp(intel_dp)) {
Keith Packard1a2eb462011-11-16 16:26:07 -08001878 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
Keith Packard417e8222011-11-01 19:54:11 -07001879 DP |= DP_LINK_TRAIN_OFF_CPT;
1880 else
1881 DP |= DP_LINK_TRAIN_OFF;
1882 }
Eric Anholt5bddd172010-11-18 09:32:59 +08001883
Chris Wilson1b39d6f2010-12-06 11:20:45 +00001884 if (!HAS_PCH_CPT(dev) &&
1885 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Chris Wilson31acbcc2011-04-17 06:38:35 +01001886 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1887
Eric Anholt5bddd172010-11-18 09:32:59 +08001888 /* Hardware workaround: leaving our transcoder select
1889 * set to transcoder B while it's off will prevent the
1890 * corresponding HDMI output on transcoder A.
1891 *
1892 * Combine this with another hardware workaround:
1893 * transcoder select bit can only be cleared while the
1894 * port is enabled.
1895 */
1896 DP &= ~DP_PIPEB_SELECT;
1897 I915_WRITE(intel_dp->output_reg, DP);
1898
1899 /* Changes to enable or select take place the vblank
1900 * after being written.
1901 */
Chris Wilson31acbcc2011-04-17 06:38:35 +01001902 if (crtc == NULL) {
1903 /* We can arrive here never having been attached
1904 * to a CRTC, for instance, due to inheriting
1905 * random state from the BIOS.
1906 *
1907 * If the pipe is not running, play safe and
1908 * wait for the clocks to stabilise before
1909 * continuing.
1910 */
1911 POSTING_READ(intel_dp->output_reg);
1912 msleep(50);
1913 } else
1914 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08001915 }
1916
Chris Wilsonea5b2132010-08-04 13:50:23 +01001917 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1918 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07001919 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001920}
1921
Keith Packard26d61aa2011-07-25 20:01:09 -07001922static bool
1923intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07001924{
Keith Packard92fd8fd2011-07-25 19:50:10 -07001925 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
Akshay Joshi0206e352011-08-16 15:34:10 -04001926 sizeof(intel_dp->dpcd)) &&
Keith Packard92fd8fd2011-07-25 19:50:10 -07001927 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
Keith Packard26d61aa2011-07-25 20:01:09 -07001928 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07001929 }
1930
Keith Packard26d61aa2011-07-25 20:01:09 -07001931 return false;
Keith Packard92fd8fd2011-07-25 19:50:10 -07001932}
1933
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001934static bool
1935intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1936{
1937 int ret;
1938
1939 ret = intel_dp_aux_native_read_retry(intel_dp,
1940 DP_DEVICE_SERVICE_IRQ_VECTOR,
1941 sink_irq_vector, 1);
1942 if (!ret)
1943 return false;
1944
1945 return true;
1946}
1947
1948static void
1949intel_dp_handle_test_request(struct intel_dp *intel_dp)
1950{
1951 /* NAK by default */
1952 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1953}
1954
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001955/*
1956 * According to DP spec
1957 * 5.1.2:
1958 * 1. Read DPCD
1959 * 2. Configure link according to Receiver Capabilities
1960 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1961 * 4. Check link status on receipt of hot-plug interrupt
1962 */
1963
1964static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01001965intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001966{
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001967 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07001968 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001969
Keith Packardd2b996a2011-07-25 22:37:51 -07001970 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1971 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07001972
Chris Wilson4ef69c72010-09-09 15:14:28 +01001973 if (!intel_dp->base.base.crtc)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001974 return;
1975
Keith Packard92fd8fd2011-07-25 19:50:10 -07001976 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07001977 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01001978 intel_dp_link_down(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001979 return;
1980 }
1981
Keith Packard92fd8fd2011-07-25 19:50:10 -07001982 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07001983 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07001984 intel_dp_link_down(intel_dp);
1985 return;
1986 }
1987
Jesse Barnesa60f0e32011-10-20 15:09:17 -07001988 /* Try to read the source of the interrupt */
1989 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1990 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1991 /* Clear interrupt source */
1992 intel_dp_aux_native_write_1(intel_dp,
1993 DP_DEVICE_SERVICE_IRQ_VECTOR,
1994 sink_irq_vector);
1995
1996 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1997 intel_dp_handle_test_request(intel_dp);
1998 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1999 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2000 }
2001
Keith Packard93f62da2011-11-01 19:45:03 -07002002 if (!intel_channel_eq_ok(intel_dp, link_status)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07002003 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2004 drm_get_encoder_name(&intel_dp->base.base));
Jesse Barnes33a34e42010-09-08 12:42:02 -07002005 intel_dp_start_link_train(intel_dp);
2006 intel_dp_complete_link_train(intel_dp);
2007 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002008}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002009
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002010static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07002011intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04002012{
Keith Packard26d61aa2011-07-25 20:01:09 -07002013 if (intel_dp_get_dpcd(intel_dp))
2014 return connector_status_connected;
2015 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04002016}
2017
2018static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002019ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002020{
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002021 enum drm_connector_status status;
2022
Chris Wilsonfe16d942011-02-12 10:29:38 +00002023 /* Can't disconnect eDP, but you can close the lid... */
2024 if (is_edp(intel_dp)) {
2025 status = intel_panel_detect(intel_dp->base.base.dev);
2026 if (status == connector_status_unknown)
2027 status = connector_status_connected;
2028 return status;
2029 }
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07002030
Keith Packard26d61aa2011-07-25 20:01:09 -07002031 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002032}
2033
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002034static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002035g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002036{
Chris Wilson4ef69c72010-09-09 15:14:28 +01002037 struct drm_device *dev = intel_dp->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002038 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002039 uint32_t temp, bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002040
Chris Wilsonea5b2132010-08-04 13:50:23 +01002041 switch (intel_dp->output_reg) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002042 case DP_B:
2043 bit = DPB_HOTPLUG_INT_STATUS;
2044 break;
2045 case DP_C:
2046 bit = DPC_HOTPLUG_INT_STATUS;
2047 break;
2048 case DP_D:
2049 bit = DPD_HOTPLUG_INT_STATUS;
2050 break;
2051 default:
2052 return connector_status_unknown;
2053 }
2054
2055 temp = I915_READ(PORT_HOTPLUG_STAT);
2056
2057 if ((temp & bit) == 0)
2058 return connector_status_disconnected;
2059
Keith Packard26d61aa2011-07-25 20:01:09 -07002060 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002061}
2062
Keith Packard8c241fe2011-09-28 16:38:44 -07002063static struct edid *
2064intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2065{
2066 struct intel_dp *intel_dp = intel_attached_dp(connector);
2067 struct edid *edid;
2068
2069 ironlake_edp_panel_vdd_on(intel_dp);
2070 edid = drm_get_edid(connector, adapter);
Keith Packardbd943152011-09-18 23:09:52 -07002071 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard8c241fe2011-09-28 16:38:44 -07002072 return edid;
2073}
2074
2075static int
2076intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2077{
2078 struct intel_dp *intel_dp = intel_attached_dp(connector);
2079 int ret;
2080
2081 ironlake_edp_panel_vdd_on(intel_dp);
2082 ret = intel_ddc_get_modes(connector, adapter);
Keith Packardbd943152011-09-18 23:09:52 -07002083 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard8c241fe2011-09-28 16:38:44 -07002084 return ret;
2085}
2086
2087
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002088/**
2089 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2090 *
2091 * \return true if DP port is connected.
2092 * \return false if DP port is disconnected.
2093 */
2094static enum drm_connector_status
2095intel_dp_detect(struct drm_connector *connector, bool force)
2096{
2097 struct intel_dp *intel_dp = intel_attached_dp(connector);
2098 struct drm_device *dev = intel_dp->base.base.dev;
2099 enum drm_connector_status status;
2100 struct edid *edid = NULL;
2101
2102 intel_dp->has_audio = false;
2103
2104 if (HAS_PCH_SPLIT(dev))
2105 status = ironlake_dp_detect(intel_dp);
2106 else
2107 status = g4x_dp_detect(intel_dp);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04002108
Adam Jacksonac66ae82011-07-12 17:38:03 -04002109 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2110 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2111 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2112 intel_dp->dpcd[6], intel_dp->dpcd[7]);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04002113
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002114 if (status != connector_status_connected)
2115 return status;
2116
Chris Wilsonf6849602010-09-19 09:29:33 +01002117 if (intel_dp->force_audio) {
2118 intel_dp->has_audio = intel_dp->force_audio > 0;
2119 } else {
Keith Packard8c241fe2011-09-28 16:38:44 -07002120 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilsonf6849602010-09-19 09:29:33 +01002121 if (edid) {
2122 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2123 connector->display_info.raw_edid = NULL;
2124 kfree(edid);
2125 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08002126 }
2127
2128 return connector_status_connected;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002129}
2130
2131static int intel_dp_get_modes(struct drm_connector *connector)
2132{
Chris Wilsondf0e9242010-09-09 16:20:55 +01002133 struct intel_dp *intel_dp = intel_attached_dp(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01002134 struct drm_device *dev = intel_dp->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002137
2138 /* We should parse the EDID data and find out if it has an audio sink
2139 */
2140
Keith Packard8c241fe2011-09-28 16:38:44 -07002141 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
Zhao Yakuib9efc482010-07-19 09:43:11 +01002142 if (ret) {
Keith Packardd15456d2011-09-18 17:35:47 -07002143 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
Zhao Yakuib9efc482010-07-19 09:43:11 +01002144 struct drm_display_mode *newmode;
2145 list_for_each_entry(newmode, &connector->probed_modes,
2146 head) {
Keith Packardd15456d2011-09-18 17:35:47 -07002147 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2148 intel_dp->panel_fixed_mode =
Zhao Yakuib9efc482010-07-19 09:43:11 +01002149 drm_mode_duplicate(dev, newmode);
2150 break;
2151 }
2152 }
2153 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002154 return ret;
Zhao Yakuib9efc482010-07-19 09:43:11 +01002155 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002156
2157 /* if eDP has no EDID, try to use fixed panel mode from VBT */
Jesse Barnes4d926462010-10-07 16:01:07 -07002158 if (is_edp(intel_dp)) {
Keith Packard47f0eb22011-09-19 14:33:26 -07002159 /* initialize panel mode from VBT if available for eDP */
Keith Packardd15456d2011-09-18 17:35:47 -07002160 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2161 intel_dp->panel_fixed_mode =
Keith Packard47f0eb22011-09-19 14:33:26 -07002162 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
Keith Packardd15456d2011-09-18 17:35:47 -07002163 if (intel_dp->panel_fixed_mode) {
2164 intel_dp->panel_fixed_mode->type |=
Keith Packard47f0eb22011-09-19 14:33:26 -07002165 DRM_MODE_TYPE_PREFERRED;
2166 }
2167 }
Keith Packardd15456d2011-09-18 17:35:47 -07002168 if (intel_dp->panel_fixed_mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002169 struct drm_display_mode *mode;
Keith Packardd15456d2011-09-18 17:35:47 -07002170 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002171 drm_mode_probed_add(connector, mode);
2172 return 1;
2173 }
2174 }
2175 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002176}
2177
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002178static bool
2179intel_dp_detect_audio(struct drm_connector *connector)
2180{
2181 struct intel_dp *intel_dp = intel_attached_dp(connector);
2182 struct edid *edid;
2183 bool has_audio = false;
2184
Keith Packard8c241fe2011-09-28 16:38:44 -07002185 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002186 if (edid) {
2187 has_audio = drm_detect_monitor_audio(edid);
2188
2189 connector->display_info.raw_edid = NULL;
2190 kfree(edid);
2191 }
2192
2193 return has_audio;
2194}
2195
Chris Wilsonf6849602010-09-19 09:29:33 +01002196static int
2197intel_dp_set_property(struct drm_connector *connector,
2198 struct drm_property *property,
2199 uint64_t val)
2200{
Chris Wilsone953fd72011-02-21 22:23:52 +00002201 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Chris Wilsonf6849602010-09-19 09:29:33 +01002202 struct intel_dp *intel_dp = intel_attached_dp(connector);
2203 int ret;
2204
2205 ret = drm_connector_property_set_value(connector, property, val);
2206 if (ret)
2207 return ret;
2208
Chris Wilson3f43c482011-05-12 22:17:24 +01002209 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002210 int i = val;
2211 bool has_audio;
2212
2213 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01002214 return 0;
2215
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002216 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01002217
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002218 if (i == 0)
2219 has_audio = intel_dp_detect_audio(connector);
2220 else
2221 has_audio = i > 0;
2222
2223 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01002224 return 0;
2225
Chris Wilson1aad7ac2011-02-09 18:46:58 +00002226 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01002227 goto done;
2228 }
2229
Chris Wilsone953fd72011-02-21 22:23:52 +00002230 if (property == dev_priv->broadcast_rgb_property) {
2231 if (val == !!intel_dp->color_range)
2232 return 0;
2233
2234 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2235 goto done;
2236 }
2237
Chris Wilsonf6849602010-09-19 09:29:33 +01002238 return -EINVAL;
2239
2240done:
2241 if (intel_dp->base.base.crtc) {
2242 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2243 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2244 crtc->x, crtc->y,
2245 crtc->fb);
2246 }
2247
2248 return 0;
2249}
2250
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002251static void
Akshay Joshi0206e352011-08-16 15:34:10 -04002252intel_dp_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002253{
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02002254 struct drm_device *dev = connector->dev;
2255
2256 if (intel_dpd_is_edp(dev))
2257 intel_panel_destroy_backlight(dev);
2258
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002259 drm_sysfs_connector_remove(connector);
2260 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002261 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002262}
2263
Daniel Vetter24d05922010-08-20 18:08:28 +02002264static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2265{
2266 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2267
2268 i2c_del_adapter(&intel_dp->adapter);
2269 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07002270 if (is_edp(intel_dp)) {
2271 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2272 ironlake_panel_vdd_off_sync(intel_dp);
2273 }
Daniel Vetter24d05922010-08-20 18:08:28 +02002274 kfree(intel_dp);
2275}
2276
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002277static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2278 .dpms = intel_dp_dpms,
2279 .mode_fixup = intel_dp_mode_fixup,
Jesse Barnesd240f202010-08-13 15:43:26 -07002280 .prepare = intel_dp_prepare,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002281 .mode_set = intel_dp_mode_set,
Jesse Barnesd240f202010-08-13 15:43:26 -07002282 .commit = intel_dp_commit,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002283};
2284
2285static const struct drm_connector_funcs intel_dp_connector_funcs = {
2286 .dpms = drm_helper_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002287 .detect = intel_dp_detect,
2288 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01002289 .set_property = intel_dp_set_property,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002290 .destroy = intel_dp_destroy,
2291};
2292
2293static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2294 .get_modes = intel_dp_get_modes,
2295 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01002296 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002297};
2298
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002299static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Daniel Vetter24d05922010-08-20 18:08:28 +02002300 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002301};
2302
Chris Wilson995b6762010-08-20 13:23:26 +01002303static void
Eric Anholt21d40d32010-03-25 11:11:14 -07002304intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07002305{
Chris Wilsonea5b2132010-08-04 13:50:23 +01002306 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
Keith Packardc8110e52009-05-06 11:51:10 -07002307
Jesse Barnes885a5012011-07-07 11:11:01 -07002308 intel_dp_check_link_status(intel_dp);
Keith Packardc8110e52009-05-06 11:51:10 -07002309}
2310
Zhenyu Wange3421a12010-04-08 09:43:27 +08002311/* Return which DP Port should be selected for Transcoder DP control */
2312int
Akshay Joshi0206e352011-08-16 15:34:10 -04002313intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08002314{
2315 struct drm_device *dev = crtc->dev;
2316 struct drm_mode_config *mode_config = &dev->mode_config;
2317 struct drm_encoder *encoder;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002318
2319 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002320 struct intel_dp *intel_dp;
2321
Dan Carpenterd8201ab2010-05-07 10:39:00 +02002322 if (encoder->crtc != crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08002323 continue;
2324
Chris Wilsonea5b2132010-08-04 13:50:23 +01002325 intel_dp = enc_to_intel_dp(encoder);
Keith Packard417e8222011-11-01 19:54:11 -07002326 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2327 intel_dp->base.type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01002328 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002329 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01002330
Zhenyu Wange3421a12010-04-08 09:43:27 +08002331 return -1;
2332}
2333
Zhao Yakui36e83a12010-06-12 14:32:21 +08002334/* check the VBT to see whether the eDP is on DP-D port */
Adam Jacksoncb0953d2010-07-16 14:46:29 -04002335bool intel_dpd_is_edp(struct drm_device *dev)
Zhao Yakui36e83a12010-06-12 14:32:21 +08002336{
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct child_device_config *p_child;
2339 int i;
2340
2341 if (!dev_priv->child_dev_num)
2342 return false;
2343
2344 for (i = 0; i < dev_priv->child_dev_num; i++) {
2345 p_child = dev_priv->child_dev + i;
2346
2347 if (p_child->dvo_port == PORT_IDPD &&
2348 p_child->device_type == DEVICE_TYPE_eDP)
2349 return true;
2350 }
2351 return false;
2352}
2353
Chris Wilsonf6849602010-09-19 09:29:33 +01002354static void
2355intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2356{
Chris Wilson3f43c482011-05-12 22:17:24 +01002357 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00002358 intel_attach_broadcast_rgb_property(connector);
Chris Wilsonf6849602010-09-19 09:29:33 +01002359}
2360
Keith Packardc8110e52009-05-06 11:51:10 -07002361void
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002362intel_dp_init(struct drm_device *dev, int output_reg)
2363{
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct drm_connector *connector;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002366 struct intel_dp *intel_dp;
Eric Anholt21d40d32010-03-25 11:11:14 -07002367 struct intel_encoder *intel_encoder;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002368 struct intel_connector *intel_connector;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002369 const char *name = NULL;
Adam Jacksonb3295302010-07-16 14:46:28 -04002370 int type;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002371
Chris Wilsonea5b2132010-08-04 13:50:23 +01002372 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2373 if (!intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002374 return;
2375
Chris Wilson3d3dc142011-02-12 10:33:12 +00002376 intel_dp->output_reg = output_reg;
Keith Packardd2b996a2011-07-25 22:37:51 -07002377 intel_dp->dpms_mode = -1;
Chris Wilson3d3dc142011-02-12 10:33:12 +00002378
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002379 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2380 if (!intel_connector) {
Chris Wilsonea5b2132010-08-04 13:50:23 +01002381 kfree(intel_dp);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002382 return;
2383 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01002384 intel_encoder = &intel_dp->base;
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002385
Chris Wilsonea5b2132010-08-04 13:50:23 +01002386 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
Adam Jacksonb3295302010-07-16 14:46:28 -04002387 if (intel_dpd_is_edp(dev))
Chris Wilsonea5b2132010-08-04 13:50:23 +01002388 intel_dp->is_pch_edp = true;
Adam Jacksonb3295302010-07-16 14:46:28 -04002389
Jesse Barnescfcb0fc2010-10-07 16:01:06 -07002390 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
Adam Jacksonb3295302010-07-16 14:46:28 -04002391 type = DRM_MODE_CONNECTOR_eDP;
2392 intel_encoder->type = INTEL_OUTPUT_EDP;
2393 } else {
2394 type = DRM_MODE_CONNECTOR_DisplayPort;
2395 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2396 }
2397
Zhenyu Wang55f78c42010-03-29 16:13:57 +08002398 connector = &intel_connector->base;
Adam Jacksonb3295302010-07-16 14:46:28 -04002399 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002400 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2401
Dave Airlieeb1f8e42010-05-07 06:42:51 +00002402 connector->polled = DRM_CONNECTOR_POLL_HPD;
2403
Zhao Yakui652af9d2009-12-02 10:03:33 +08002404 if (output_reg == DP_B || output_reg == PCH_DP_B)
Eric Anholt21d40d32010-03-25 11:11:14 -07002405 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
Zhao Yakui652af9d2009-12-02 10:03:33 +08002406 else if (output_reg == DP_C || output_reg == PCH_DP_C)
Eric Anholt21d40d32010-03-25 11:11:14 -07002407 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
Zhao Yakui652af9d2009-12-02 10:03:33 +08002408 else if (output_reg == DP_D || output_reg == PCH_DP_D)
Eric Anholt21d40d32010-03-25 11:11:14 -07002409 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
Ma Lingf8aed702009-08-24 13:50:24 +08002410
Keith Packardbd943152011-09-18 23:09:52 -07002411 if (is_edp(intel_dp)) {
Eric Anholt21d40d32010-03-25 11:11:14 -07002412 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
Keith Packardbd943152011-09-18 23:09:52 -07002413 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2414 ironlake_panel_vdd_work);
2415 }
Zhenyu Wang6251ec02010-01-12 05:38:32 +08002416
Jesse Barnes27f82272011-09-02 12:54:37 -07002417 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002418 connector->interlace_allowed = true;
2419 connector->doublescan_allowed = 0;
2420
Chris Wilson4ef69c72010-09-09 15:14:28 +01002421 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002422 DRM_MODE_ENCODER_TMDS);
Chris Wilson4ef69c72010-09-09 15:14:28 +01002423 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002424
Chris Wilsondf0e9242010-09-09 16:20:55 +01002425 intel_connector_attach_encoder(intel_connector, intel_encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002426 drm_sysfs_connector_add(connector);
2427
2428 /* Set up the DDC bus. */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002429 switch (output_reg) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002430 case DP_A:
2431 name = "DPDDC-A";
2432 break;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002433 case DP_B:
2434 case PCH_DP_B:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002435 dev_priv->hotplug_supported_mask |=
2436 HDMIB_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002437 name = "DPDDC-B";
2438 break;
2439 case DP_C:
2440 case PCH_DP_C:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002441 dev_priv->hotplug_supported_mask |=
2442 HDMIC_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002443 name = "DPDDC-C";
2444 break;
2445 case DP_D:
2446 case PCH_DP_D:
Jesse Barnesb01f2c32009-12-11 11:07:17 -08002447 dev_priv->hotplug_supported_mask |=
2448 HDMID_HOTPLUG_INT_STATUS;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08002449 name = "DPDDC-D";
2450 break;
2451 }
2452
Jesse Barnes89667382010-10-07 16:01:21 -07002453 /* Cache some DPCD data in the eDP case */
2454 if (is_edp(intel_dp)) {
Keith Packard59f3e272011-07-25 20:01:56 -07002455 bool ret;
Keith Packardf01eca22011-09-28 16:48:10 -07002456 struct edp_power_seq cur, vbt;
2457 u32 pp_on, pp_off, pp_div;
Jesse Barnes89667382010-10-07 16:01:21 -07002458
Jesse Barnes5d613502011-01-24 17:10:54 -08002459 pp_on = I915_READ(PCH_PP_ON_DELAYS);
Keith Packardf01eca22011-09-28 16:48:10 -07002460 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
Jesse Barnes5d613502011-01-24 17:10:54 -08002461 pp_div = I915_READ(PCH_PP_DIVISOR);
2462
Keith Packardf01eca22011-09-28 16:48:10 -07002463 /* Pull timing values out of registers */
2464 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2465 PANEL_POWER_UP_DELAY_SHIFT;
2466
2467 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2468 PANEL_LIGHT_ON_DELAY_SHIFT;
Keith Packardf2e8b182011-11-01 20:01:35 -07002469
Keith Packardf01eca22011-09-28 16:48:10 -07002470 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2471 PANEL_LIGHT_OFF_DELAY_SHIFT;
2472
2473 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2474 PANEL_POWER_DOWN_DELAY_SHIFT;
2475
2476 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2477 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2478
2479 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2480 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2481
2482 vbt = dev_priv->edp.pps;
2483
2484 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2485 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2486
2487#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2488
2489 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2490 intel_dp->backlight_on_delay = get_delay(t8);
2491 intel_dp->backlight_off_delay = get_delay(t9);
2492 intel_dp->panel_power_down_delay = get_delay(t10);
2493 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2494
2495 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2496 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2497 intel_dp->panel_power_cycle_delay);
2498
2499 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2500 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
Jesse Barnes5d613502011-01-24 17:10:54 -08002501
2502 ironlake_edp_panel_vdd_on(intel_dp);
Keith Packard59f3e272011-07-25 20:01:56 -07002503 ret = intel_dp_get_dpcd(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07002504 ironlake_edp_panel_vdd_off(intel_dp, false);
Keith Packard99ea7122011-11-01 19:57:50 -07002505
Keith Packard59f3e272011-07-25 20:01:56 -07002506 if (ret) {
Jesse Barnes7183dc22011-07-07 11:10:58 -07002507 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2508 dev_priv->no_aux_handshake =
2509 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
Jesse Barnes89667382010-10-07 16:01:21 -07002510 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2511 } else {
Chris Wilson3d3dc142011-02-12 10:33:12 +00002512 /* if this fails, presume the device is a ghost */
Takashi Iwai48898b02011-03-18 09:06:49 +00002513 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Chris Wilson3d3dc142011-02-12 10:33:12 +00002514 intel_dp_encoder_destroy(&intel_dp->base.base);
Takashi Iwai48898b02011-03-18 09:06:49 +00002515 intel_dp_destroy(&intel_connector->base);
Chris Wilson3d3dc142011-02-12 10:33:12 +00002516 return;
Jesse Barnes89667382010-10-07 16:01:21 -07002517 }
Jesse Barnes89667382010-10-07 16:01:21 -07002518 }
2519
Keith Packard552fb0b2011-09-28 16:31:53 -07002520 intel_dp_i2c_init(intel_dp, intel_connector, name);
2521
Eric Anholt21d40d32010-03-25 11:11:14 -07002522 intel_encoder->hot_plug = intel_dp_hot_plug;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002523
Jesse Barnes4d926462010-10-07 16:01:07 -07002524 if (is_edp(intel_dp)) {
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02002525 dev_priv->int_edp_connector = connector;
2526 intel_panel_setup_backlight(dev);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002527 }
2528
Chris Wilsonf6849602010-09-19 09:29:33 +01002529 intel_dp_add_properties(intel_dp, connector);
2530
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002531 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2532 * 0xd. Failure to do so will result in spurious interrupts being
2533 * generated on the port when a cable is not attached.
2534 */
2535 if (IS_G4X(dev) && !IS_GM45(dev)) {
2536 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2537 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2538 }
2539}