diff options
| -rw-r--r-- | target-sparc/cpu.h | 2 | ||||
| -rw-r--r-- | target-sparc/translate.c | 29 |
2 files changed, 22 insertions, 9 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index a7e4723190..a3d64a4e52 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -722,6 +722,7 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_MMU_MASK 7 #define TB_FLAG_FPU_ENABLED (1 << 4) #define TB_FLAG_AM_ENABLED (1 << 5) +#define TB_FLAG_ASI_SHIFT 24 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) @@ -739,6 +740,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, && (env->fprs & FPRS_FEF)) { flags |= TB_FLAG_FPU_ENABLED; } + flags |= env->asi << TB_FLAG_ASI_SHIFT; #else if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) { flags |= TB_FLAG_FPU_ENABLED; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 90c46dfb71..0b056e5cf7 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -53,7 +53,7 @@ static TCGv cpu_tbr; #endif static TCGv cpu_cond; #ifdef TARGET_SPARC64 -static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; +static TCGv_i32 cpu_xcc, cpu_fprs; static TCGv cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; @@ -81,6 +81,9 @@ typedef struct DisasContext { TCGv ttl[5]; int n_t32; int n_ttl; +#ifdef TARGET_SPARC64 + int asi; +#endif } DisasContext; typedef struct { @@ -1975,19 +1978,19 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) static TCGv_i32 gen_get_asi(DisasContext *dc, int insn) { - TCGv_i32 r_asi = tcg_temp_new_i32(); + int asi; if (IS_IMM) { #ifdef TARGET_SPARC64 - tcg_gen_mov_i32(r_asi, cpu_asi); + asi = dc->asi; #else gen_exception(dc, TT_ILL_INSN); - tcg_gen_movi_i32(r_asi, 0); + asi = 0; #endif } else { - tcg_gen_movi_i32(r_asi, GET_FIELD(insn, 19, 26)); + asi = GET_FIELD(insn, 19, 26); } - return r_asi; + return tcg_const_i32(asi); } static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, @@ -2688,7 +2691,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_store_gpr(dc, rd, cpu_dst); break; case 0x3: /* V9 rdasi */ - tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); + tcg_gen_movi_tl(cpu_dst, dc->asi); gen_store_gpr(dc, rd, cpu_dst); break; case 0x4: /* V9 rdtick */ @@ -3614,7 +3617,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x3: /* V9 wrasi */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); - tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0); + tcg_gen_st32_tl(cpu_tmp0, cpu_env, + offsetof(CPUSPARCState, asi)); + /* End TB to notice changed ASI. */ + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(0); + dc->is_br = 1; break; case 0x6: /* V9 wrfprs */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); @@ -5195,6 +5204,9 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->singlestep = (cs->singlestep_enabled || singlestep); +#ifdef TARGET_SPARC64 + dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; +#endif num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; @@ -5304,7 +5316,6 @@ void gen_intermediate_code_init(CPUSPARCState *env) static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = { #ifdef TARGET_SPARC64 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" }, - { &cpu_asi, offsetof(CPUSPARCState, asi), "asi" }, { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" }, #else { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" }, |