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-rw-r--r--target-alpha/STATUS2
-rw-r--r--target-microblaze/cpu.h2
-rw-r--r--target-microblaze/translate.c4
-rw-r--r--target-mips/cpu.h2
-rw-r--r--target-mips/machine.c2
-rw-r--r--target-ppc/cpu.h4
-rw-r--r--target-ppc/mfrom_table_gen.c2
-rw-r--r--target-ppc/op_helper.c4
-rw-r--r--target-sh4/helper.c2
-rw-r--r--target-sparc/TODO2
10 files changed, 13 insertions, 13 deletions
diff --git a/target-alpha/STATUS b/target-alpha/STATUS
index 353d543c4a..742e370b90 100644
--- a/target-alpha/STATUS
+++ b/target-alpha/STATUS
@@ -18,7 +18,7 @@ Linux user mode emulation status:
a few programs start to run. Most crash at a certain point, dereferencing a
NULL pointer. It seems that the UNIQUE register is not initialized properly.
It may appear that old executables, not relying on TLS support, run but
-this is to be prooved...
+this is to be proved...
Full system emulation status:
* Alpha PALCode emulation is in a very early stage and is not sufficient
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 35302863cb..1a307e312d 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -243,7 +243,7 @@ typedef struct CPUMBState {
#define DRTE_FLAG (1 << 17)
#define DRTB_FLAG (1 << 18)
#define D_FLAG (1 << 19) /* Bit in ESR. */
-/* TB dependant CPUState. */
+/* TB dependent CPUState. */
#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
uint32_t iflags;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 366fd3e607..d7f513d34d 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -120,7 +120,7 @@ static inline int sign_extend(unsigned int val, unsigned int width)
static inline void t_sync_flags(DisasContext *dc)
{
- /* Synch the tb dependant flags between translator and runtime. */
+ /* Synch the tb dependent flags between translator and runtime. */
if (dc->tb_flags != dc->synced_flags) {
tcg_gen_movi_tl(env_iflags, dc->tb_flags);
dc->synced_flags = dc->tb_flags;
@@ -1122,7 +1122,7 @@ static void dec_store(DisasContext *dc)
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
/* FIXME: if the alignment is wrong, we should restore the value
- * in memory. One possible way to acheive this is to probe
+ * in memory. One possible way to achieve this is to probe
* the MMU prior to the memaccess, thay way we could put
* the alignment checks in between the probe and the mem
* access.
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 79e25583ff..71cb4e8b02 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -678,7 +678,7 @@ static inline int mips_vpe_active(CPUState *env)
if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
active = 0;
}
- /* Check that the VPE is actived. */
+ /* Check that the VPE is activated. */
if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
active = 0;
}
diff --git a/target-mips/machine.c b/target-mips/machine.c
index be72b36de6..a506ee0b24 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -302,7 +302,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < MIPS_FPU_MAX; i++)
load_fpu(f, &env->fpus[i]);
- /* XXX: ensure compatiblity for halted bit ? */
+ /* XXX: ensure compatibility for halted bit ? */
tlb_flush(env, 1);
return 0;
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e84108c49a..2d67d1f4b8 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1004,7 +1004,7 @@ struct CPUPPCState {
int error_code;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
- /* This is the IRQ controller, which is implementation dependant
+ /* This is the IRQ controller, which is implementation dependent
* and only relevant when emulating a complete machine.
*/
uint32_t irq_input_state;
@@ -1024,7 +1024,7 @@ struct CPUPPCState {
/* Those resources are used only in Qemu core */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
- target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
+ target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */
/* Power management */
diff --git a/target-ppc/mfrom_table_gen.c b/target-ppc/mfrom_table_gen.c
index 4c06aa4e5e..a140ded47a 100644
--- a/target-ppc/mfrom_table_gen.c
+++ b/target-ppc/mfrom_table_gen.c
@@ -11,7 +11,7 @@ int main (void)
printf("static const uint8_t mfrom_ROM_table[602] =\n{\n ");
for (i = 0; i < 602; i++) {
- /* Extremly decomposed:
+ /* Extremely decomposed:
* -T0 / 256
* T0 = 256 * log10(10 + 1.0) + 0.5
*/
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 134b0c6587..6339c9559f 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1795,7 +1795,7 @@ void helper_rfsvc (void)
/* 602 specific instructions */
/* mfrom is the most crazy instruction ever seen, imho ! */
/* Real implementation uses a ROM table. Do the same */
-/* Extremly decomposed:
+/* Extremely decomposed:
* -arg / 256
* return 256 * log10(10 + 1.0) + 0.5
*/
@@ -3070,7 +3070,7 @@ static inline uint32_t word_reverse(uint32_t val)
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
}
-#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
+#define MASKBITS 16 // Random value - to be fixed (implementation dependent)
target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
{
uint32_t a, b, d, mask;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 5a1e15e63d..9df0719c5b 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -814,7 +814,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
/*
* TODO : Evaluate CCR and check if the cache is on or off.
* Now CCR is not in CPUSH4State, but in SH7750State.
- * When you move the ccr inot CPUSH4State, the code will be
+ * When you move the ccr into CPUSH4State, the code will be
* as follows.
*/
#if 0
diff --git a/target-sparc/TODO b/target-sparc/TODO
index c87459f50c..b8c727e858 100644
--- a/target-sparc/TODO
+++ b/target-sparc/TODO
@@ -15,7 +15,7 @@ CPU common:
- NPC/PC static optimisations (use JUMP_TB when possible)? (Is this
obsolete?)
- Synthetic instructions
- - MMU model dependant on CPU model
+ - MMU model dependent on CPU model
- Select ASI helper at translation time (on V9 only if known)
- KQemu/KVM support for VM only
- Hardware breakpoint/watchpoint support
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 09:18:01 +0000