diff options
| author | Christoffer Dall <christoffer.dall@linaro.org> | 2014-01-28 12:32:39 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-29 13:27:34 +0000 |
| commit | 984bc70fb5e6331cf3cbfa836373fefadf1435f9 (patch) | |
| tree | ba70e604782710cb682fec04fdfcd9a58b32cf21 | |
| parent | 5eed77b3f32f57b14e0c96da91df83867b1e3ba4 (diff) | |
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writespull-target-arm-20140129
Fix two bugs that would allow changing the state of SGIs through the
ICPENDR and ISPENDRs.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/intc/arm_gic.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 98c6ff5ccb..1c4a1143af 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -428,7 +428,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, if (irq >= s->num_irq) goto bad_reg; if (irq < GIC_NR_SGIS) { - irq = 0; + value = 0; } for (i = 0; i < 8; i++) { @@ -441,6 +441,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; + if (irq < GIC_NR_SGIS) { + value = 0; + } + for (i = 0; i < 8; i++) { /* ??? This currently clears the pending bit for all CPUs, even for per-CPU interrupts. It's unclear whether this is the |