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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-23 17:22:30 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-23 17:22:30 +0000 |
| commit | 550a04893c2bd4442211b353680b9a6408d94dba (patch) | |
| tree | f94497b3d10d6ab3c8f2ca83d2a3ec73502b91ae | |
| parent | 3944d58db3fc5bf131345a21a44013bc13849a12 (diff) | |
target/arm: Move computation of index in handle_simd_dupepull-target-arm-20200323
Coverity reports a BAD_SHIFT with ctz32(imm5), with imm5 == 0.
This is an invalid encoding, but we diagnose that just below
by rejecting size > 3. Avoid the warning by sinking the
computation of index below the check.
Reported-by: Coverity (CID 1421965)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200320160622.8040-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/translate-a64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 032478614c..7580e46367 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7422,7 +7422,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, int imm5) { int size = ctz32(imm5); - int index = imm5 >> (size + 1); + int index; if (size > 3 || (size == 3 && !is_q)) { unallocated_encoding(s); @@ -7433,6 +7433,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, return; } + index = imm5 >> (size + 1); tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd), vec_reg_offset(s, rn, index, size), is_q ? 16 : 8, vec_full_reg_size(s)); |