diff options
Diffstat (limited to 'drivers/video')
25 files changed, 17365 insertions, 13392 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index f30502f4c70..274e0acb76c 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -244,8 +244,6 @@ comment "Frame buffer hardware drivers" source "drivers/video/mcde/Kconfig" -source "drivers/video/av8100/Kconfig" - config FB_CIRRUS tristate "Cirrus Logic support" depends on FB && (ZORRO || PCI) @@ -2227,6 +2225,8 @@ source "drivers/video/omap2/Kconfig" source "drivers/video/backlight/Kconfig" source "drivers/video/display/Kconfig" +source "drivers/video/av8100/Kconfig" + if VT source "drivers/video/console/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a74a33bd5f0..c79033e839a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -127,7 +127,7 @@ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o obj-$(CONFIG_FB_OMAP) += omap/ obj-y += omap2/ obj-$(CONFIG_FB_MCDE) += mcde/ -obj-$(CONFIG_FB_HDMI) += av8100/ ++obj-$(CONFIG_AV8100) += av8100/ obj-y += b2r2/ obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o obj-$(CONFIG_FB_CARMINE) += carminefb.o diff --git a/drivers/video/av8100/Kconfig b/drivers/video/av8100/Kconfig index 959b986c6ce..12e44e2c430 100644 --- a/drivers/video/av8100/Kconfig +++ b/drivers/video/av8100/Kconfig @@ -1,6 +1,5 @@ -config FB_HDMI +config AV8100 tristate "AV8100 driver support(HDMI/CVBS)" - depends on (FB_MCDE) - default y + default n help - Please disable this feature if hdmi driver support not required. + Please enable this feature if hdmi/tvout driver support is required. diff --git a/drivers/video/av8100/Makefile b/drivers/video/av8100/Makefile index b834027d3ef..d857753b4bc 100644 --- a/drivers/video/av8100/Makefile +++ b/drivers/video/av8100/Makefile @@ -1,8 +1,7 @@ # Make file for compiling and loadable module HDMI -obj- := av8100.o # Dummy rule to force built-in.o to be made +obj-$(CONFIG_AV8100) += av8100.o hdmi.o -obj-$(CONFIG_FB_HDMI) += av8100.o -clean-files := av8100.o built-in.o modules.order +clean-files := av8100.o hdmi.o built-in.o modules.order diff --git a/drivers/video/av8100/av8100.c b/drivers/video/av8100/av8100.c index 631654ab02a..ccabeb8caa8 100644 --- a/drivers/video/av8100/av8100.c +++ b/drivers/video/av8100/av8100.c @@ -1,2432 +1,2898 @@ /* - * Copyright (C) ST-Ericsson SA 2010 + * Copyright (C) ST-Ericsson AB 2010 * - * License terms: + * AV8100 driver * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. */ -#include <linux/types.h> + #include <linux/kernel.h> -#include <linux/init.h> #include <linux/module.h> -#include <linux/delay.h> -#include <linux/proc_fs.h> -#include <linux/smp_lock.h> +#include <linux/device.h> #include <linux/miscdevice.h> #include <linux/platform_device.h> -#include <linux/poll.h> -#include <linux/interrupt.h> -#include <linux/device.h> #include <linux/i2c.h> -#include <linux/workqueue.h> +#include <linux/fs.h> +#include <linux/gpio.h> +#include <linux/delay.h> #include <linux/kthread.h> +#include <linux/interrupt.h> #include <linux/irq.h> -#include <asm/irq.h> -#include <asm/ioctl.h> -#include <asm/bitops.h> -#include <asm/io.h> -#include <asm/types.h> -#include <mach/hardware.h> -#include <mach/debug.h> -#include <linux/gpio.h> -#include <mach/mcde.h> -#include <mach/dsi.h> - -#include <mach/av8100_p.h> -#include <mach/av8100_fw.h> - -#define DRIVER_NAME (av8100_driver.driver.name) +#include <linux/timer.h> +#include <linux/mutex.h> + +#include "av8100_regs.h" +#include <video/av8100.h> +#include <video/hdmi.h> +#include "av8100_fw.h" + +#define AV8100_INT_EVENT 0x1 +#define AV8100_TIMER_INT_EVENT 0x2 + +#define AV8100_TIMER_INTERRUPT_POLLING_TIME 250 + +#define AV8100_DRIVER_MINOR_NUMBER 240 +#define GPIO_AV8100_RSTN 196 +#define AV8100_MASTER_CLOCK_TIMING 0x3 +#define AV8100_ON_TIME 1 +#define AV8100_OFF_TIME 0 +#define AV8100_COMMAND_OFFSET 0x10 +#define AV8100_COMMAND_MAX_LENGTH 0x81 + +#define AV8100_TE_LINE_NB_14 14 +#define AV8100_TE_LINE_NB_17 17 +#define AV8100_TE_LINE_NB_18 18 +#define AV8100_TE_LINE_NB_21 21 +#define AV8100_TE_LINE_NB_22 22 +#define AV8100_TE_LINE_NB_30 30 +#define AV8100_TE_LINE_NB_38 38 +#define AV8100_TE_LINE_NB_40 40 +#define AV8100_UI_X4_DEFAULT 6 + +#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2 +#define HDMI_CEC_MESSAGE_WRITE_BUFFER_SIZE 16 +#define HDMI_HDCP_SEND_KEY_SIZE 7 +#define HDMI_INFOFRAME_DATA_SIZE 28 +#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16 +#define HDMI_FUSE_AES_KEY_SIZE 16 + +#define REG_16_8_LSB(p) (u8)(p & 0xFF) +#define REG_16_8_MSB(p) (u8)((p & 0xFF00)>>8) +#define REG_32_8_MSB(p) (u8)((p & 0xFF000000)>>24) +#define REG_32_8_MMSB(p) (u8)((p & 0x00FF0000)>>16) +#define REG_32_8_MLSB(p) (u8)((p & 0x0000FF00)>>8) +#define REG_32_8_LSB(p) (u8)(p & 0x000000FF) +#define REG_10_8_MSB(p) (u8)((p & 0x300)>>8) + + +struct av8100_config_t { + struct i2c_client *client; + struct i2c_device_id *id; + struct av8100_video_input_format_cmd hdmi_video_input_cmd; + struct av8100_audio_input_format_cmd hdmi_audio_input_cmd; + struct av8100_video_output_format_cmd hdmi_video_output_cmd; + struct av8100_video_scaling_format_cmd hdmi_video_scaling_cmd; + struct av8100_color_space_conversion_format_cmd + hdmi_color_space_conversion_cmd; + struct av8100_cec_message_write_format_cmd + hdmi_cec_message_write_cmd; + struct av8100_cec_message_read_back_format_cmd + hdmi_cec_message_read_back_cmd; + struct av8100_denc_format_cmd hdmi_denc_cmd; + struct av8100_hdmi_cmd hdmi_cmd; + struct av8100_hdcp_send_key_format_cmd hdmi_hdcp_send_key_cmd; + struct av8100_hdcp_management_format_cmd + hdmi_hdcp_management_format_cmd; + struct av8100_infoframes_format_cmd hdmi_infoframes_cmd; + struct av8100_edid_section_readback_format_cmd + hdmi_edid_section_readback_cmd; + struct av8100_pattern_generator_format_cmd hdmi_pattern_generator_cmd; + struct av8100_fuse_aes_key_format_cmd hdmi_fuse_aes_key_cmd; +}; -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("JAYARAMI REDDY"); -MODULE_DESCRIPTION("AV8100 driver for U8500"); +/** + * struct av8100_cea - CEA(consumer electronic access) standard structure + * @cea_id: + * @cea_nb: + * @vtotale: + **/ -extern void u8500_mcde_tasklet_4(unsigned long); +struct av8100_cea { + char cea_id[40]; + int cea_nb; + int vtotale; + int vactive; + int vsbp; + int vslen; + int vsfp; + char vpol[5]; + int htotale; + int hactive; + int hbp; + int hslen; + int hfp; + int frequence; + char hpol[5]; + int reg_line_duration; + int blkoel_duration; + int uix4; + int pll_mult; + int pll_div; +}; -/*#define AV8100_USE_KERNEL_THREAD*/ +enum av8100_command_size { + AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17, + AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8, + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x1E, + AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x11, + AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x1D, + AV8100_COMMAND_CEC_MESSAGE_WRITE_SIZE = 0x12, + AV8100_COMMAND_CEC_MESSAGE_READ_BACK_SIZE = 0x1, + AV8100_COMMAND_DENC_SIZE = 0x6, + AV8100_COMMAND_HDMI_SIZE = 0x4, + AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0xA, + AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4, + AV8100_COMMAND_INFOFRAMES_SIZE = 0x21, + AV8100_COMMAND_EDID_SECTION_READBACK_SIZE = 0x3, + AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4, + AV8100_COMMAND_FUSE_AES_KEY_SIZE = 0x12, +}; -#if !defined CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI && \ - !defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI && \ - !defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV -#define TEST_PATTERN_TEST -#endif +DEFINE_MUTEX(av8100_hw_mutex); +#define LOCK_AV8100_HW mutex_lock(&av8100_hw_mutex) +#define UNLOCK_AV8100_HW mutex_unlock(&av8100_hw_mutex) -#define HDMI_LOGGING -#define CONFIG_MCDE_COLOURED_PRINTS - -#define PRNK_COL_BLACK 30 -#define PRNK_COL_RED 31 -#define PRNK_COL_GREEN 32 -#define PRNK_COL_YELLOW 33 -#define PRNK_COL_BLUE 34 -#define PRNK_COL_MAGENTA 35 -#define PRNK_COL_CYAN 36 -#define PRNK_COL_WHITE 37 - -#ifdef CONFIG_MCDE_COLOURED_PRINTS -#define PRNK_COL(_col) printk(KERN_ERR "%c[0;%d;40m\n", 0x1b, _col) -#else /* CONFIG_MCDE_COLOURED_PRINTS */ -#define PRNK_COL(_col) -#endif /* CONFIG_MCDE_COLOURED_PRINTS */ - -#ifdef HDMI_LOGGING -#define HDMI_TRACE do {\ - PRNK_COL(PRNK_COL_YELLOW);\ - printk(KERN_DEBUG "HDMI send cmd %s\n", __func__);\ - PRNK_COL(PRNK_COL_WHITE);\ -} while (0) -#else -#define HDMI_TRACE -#endif +#define AV8100_DEBUG_EXTRA +#define AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS static int av8100_open(struct inode *inode, struct file *filp); static int av8100_release(struct inode *inode, struct file *filp); -static int av8100_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg); -static void av8100_configure_hdmi(struct i2c_client *i2c); -static void av8100_configure_denc(struct av8100_data *av8100DataTemp); -static irqreturn_t av8100_intr_handler(int irq, void *p); - -static int av8100_write_multi_byte(struct i2c_client *client, unsigned char regOffset,unsigned char *buf,unsigned char nbytes); -static int av8100_write_single_byte(struct i2c_client *client, unsigned char reg,unsigned char data); -#if 0 -static int av8100_read_multi_byte(struct i2c_client *client,unsigned char reg,unsigned char *buf, unsigned char nbytes); -#endif -static int av8100_read_single_byte(struct i2c_client *client,unsigned char reg, unsigned char* val); -static void av8100_hdmi_on(struct av8100_data *av8100DataTemp); -static void av8100_hdmi_off(struct av8100_data *av8100DataTemp); -static int configure_av8100_video_input(char* buffer_temp); -static int configure_av8100_audio_input(char* buffer_temp); -static int configure_av8100_video_output(char* buffer_temp); -static int configure_av8100_video_scaling(char* buffer_temp); -static int configure_av8100_colorspace_conversion(char* buffer_temp); -static int configure_av8100_cec_message_write(char* buffer_temp); -static int configure_av8100_cec_message_read(char* buffer_temp); -static int configure_av8100_denc(char* buffer_temp); -static int configure_av8100_hdmi(char* buffer_temp); -static int configure_av8100_hdcp_senkey(char* buffer_temp); -static int configure_av8100_hdcp_management(char* buffer_temp); -static int configure_av8100_infoframe(char* buffer_temp); -static int configure_av8100_pattern_generator(char* buffer_temp); -#if 0 -static int read_edid_info(struct i2c_client *i2c, char* buff); -#endif -static int av8100_send_command (struct i2c_client *i2cClient, char command_type, enum interface if_type); -static int av8100_powerdown(void); -static int av8100_powerup(struct i2c_client *i2c, const struct i2c_device_id *id); -static int av8100_enable_interrupt(struct i2c_client *i2c); -static int av8100_probe(struct i2c_client *i2cClient,const struct i2c_device_id *id); -static int __exit av8100_remove(struct i2c_client *i2cClient); -static int av8100_download_firmware(struct i2c_client *i2c, char regoffset, char* fw_buff, int numOfBytes, enum interface if_type); -static unsigned short av8100_get_ui_x4(av8100_output_CEA_VESA output_video_format); -static unsigned short av8100_get_te_line_nb(av8100_output_CEA_VESA output_video_format); -static void av8100_init_config_params(void); -static void av8100_config_output_dep_params(void); -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV -static mcde_video_mode av8100_get_mcde_video_mode(av8100_output_CEA_VESA format); +static int av8100_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg); +static int __devinit av8100_probe(struct i2c_client *i2cClient, + const struct i2c_device_id *id); +static int __devexit av8100_remove(struct i2c_client *i2cClient); + +static struct av8100_config_t *av8100_config; +static struct av8100_status g_av8100_status = {0}; +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS +static struct timer_list av8100_timer; #endif -static void av8100_set_state(av8100_operating_mode state); -static av8100_operating_mode av8100_get_state(void); - -#define uint8 unsigned char - -/** global data */ -unsigned int g_av8100_cmd_length=0; -unsigned int g_dcs_data_count_index = 0; -unsigned int g_dcs_data_count_last = 0; -struct av8100_data *av8100Data; -av8100_operating_mode g_av8100_state = AV8100_OPMODE_SHUTDOWN; - -av8100_video_input_format_cmd hdmi_video_input_cmd; -av8100_video_output_format_cmd hdmi_video_output_cmd; -av8100_hdmi_cmd hdmi_cmd; -av8100_pattern_generator_cmd hdmi_pattern_generator_cmd; -av8100_audio_input_format_cmd hdmi_audio_input_cmd; -av8100_color_space_conversion_cmd hdmi_color_conversion_cmd; -av8100_denc_cmd hdmi_denc_cmd; - -wait_queue_head_t av8100_event; -bool av8100_flag = 0x0; - -int length = 0x0; -extern unsigned int isReady; -#define DSI_MAX_DATA_WRITE 15 - -av8100_cea av8100_all_cea[29] ={ -/* cea id cea_nr vtot vact vsbpp vslen vsfp vpol htot hact hbp hslen hfp freq hpol rld,bd,uix4,pm,pd */ -{ "0 CUSTOM " , 0 ,0 , 0 ,0 , 0 , 0 , "-" , 800 ,640 , 16 , 96 , 10, 25200000 ,"-",0,0,0,0,0},//Settings to be define -{ "1 CEA 1 VESA 4 640x480p @ 60 Hz " , 1 ,525 , 480 ,33 , 2 , 10 , "-" , 800 ,640 , 49 , 290 , 146, 25200000 ,"-",2438,1270,6,32,1},//RGB888 -{ "2 CEA 2 - 3 720x480p @ 60 Hz 4:3 " , 2 ,525 , 480 ,30 , 6 , 9 , "-" , 858 ,720 , 34 , 130 , 128, 27027000 ,"-",1828,0x3C0,8,24,1},//RGB565 -{ "3 CEA 4 1280x720p @ 60 Hz " , 4 ,750 , 720 ,20 , 5 , 5 , "+" , 1650 ,1280 , 114 , 39 , 228, 74250000 ,"+",1706,164,6,32,1},//RGB565 -{ "4 CEA 5 1920x1080i @ 60 Hz " , 5 ,1125 , 540 ,20 , 5 , 0 , "+" , 2200 ,1920 , 88 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define -{ "5 CEA 6-7 480i (NTSC) " , 6 ,525 , 240 ,44 , 5 , 0 , "-" , 1716 ,1440 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "6 CEA 14-15 480p @ 60 Hz " , 14 ,525 , 480 ,44 , 5 , 0 , "-" , 858 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "7 CEA 16 1920x1080p @ 60 Hz " , 16 ,1125 , 1080 ,36 , 5 , 0 , "+" , 1980 ,1280 , 440 , 40 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define -{ "8 CEA 17-18 720x576p @ 50 Hz " , 17 ,625 , 576 ,44 , 5 , 0 , "-" , 864 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "9 CEA 19 1280x720p @ 50 Hz " , 19 ,750 , 720 ,25 , 5 , 0 , "+" , 1980 ,1280 , 440 , 40 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define -{ "10 CEA 20 1920 x 1080i @ 50 Hz " , 20 ,1125 , 540 ,20 , 5 , 0 , "+" , 2640 ,1920 , 528 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define -{ "11 CEA 21-22 576i (PAL) " , 21 ,625 , 288 ,44 , 5 , 0 , "-" , 1728 ,1440 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "12 CEA 29/30 576p " , 29 ,625 , 576 ,44 , 5 , 0 , "-" , 864 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "13 CEA 31 1080p 50Hz " , 31 ,1125 , 1080 ,44 , 5 , 0 , "-" , 2750 ,1920 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define -{ "14 CEA 32 1920x1080p @ 24 Hz " , 32 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2750 ,1920 , 660 , 44 , 153, 74250000 ,"+",2844,0x530,6,32,1},//RGB565 -{ "15 CEA 33 1920x1080p @ 25 Hz " , 33 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2640 ,1920 , 528 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define -{ "16 CEA 34 1920x1080p @ 30Hz " , 34 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2200 ,1920 , 91 , 44 , 153, 74250000 ,"+",2275,0xAB,6,32,1},//RGB565 -{ "17 CEA 60 1280x720p @ 24 Hz " , 60 ,750 , 720 ,20 , 5 , 5 , "+" , 3300 ,1280 , 284 , 50 , 2276, 29700000 ,"+",4266,0xAD0,5,32,1},//RGB565 -{ "18 CEA 61 1280x720p @ 25 Hz " , 61 ,750 , 720 ,20 , 5 , 5 , "+" , 3960 ,1280 , 228 , 39 , 2503 ,30937500 ,"+",4096,0x500,5,32,1},//RGB565 -{ "19 CEA 62 1280x720p @ 30 Hz " , 62 ,750 , 720 ,20 , 5 , 5 , "+" , 3300 ,1280 , 228 , 39 , 1820, 37125000 ,"+",3413,0x770,5,32,1},//RGB565 -{ "20 VESA 9 800x600 @ 60 Hz " , 109 ,628 , 600 ,28 , 4 , 0 , "+" , 1056 ,800 , 40 , 128 , 10, 40000000 ,"+",0,0,0,0,0},//Settings to be define -{ "21 VESA 14 848x480 @ 60 Hz " , 114 ,500 , 480 ,20 , 5 , 0 , "+" , 1056 ,848 , 24 , 80 , 10, 31500000 ,"-",0,0,0,0,0},//Settings to be define -{ "22 VESA 16 1024x768 @ 60 Hz " , 116 ,806 , 768 ,38 , 6 , 0 , "-" , 1344 ,1024 , 24 , 135 , 10, 65000000 ,"-",0,0,0,0,0},//Settings to be define -{ "23 VESA 22 1280x768 @ 60 Hz " , 122 ,802 , 768 ,34 , 4 , 0 , "+" , 1688 ,1280 , 48 , 160 , 10, 81250000 ,"-",0,0,0,0,0},//Settings to be define -{ "24 VESA 23 1280x768 @ 60 Hz " , 123 ,798 , 768 ,30 , 7 , 0 , "+" , 1664 ,1280 , 64 , 128 , 10, 79500000 ,"-",0,0,0,0,0},//Settings to be define -{ "25 VESA 27 1280x800 @ 60 Hz " , 127 ,823 , 800 ,23 , 6 , 0 , "+" , 1440 ,1280 , 48 , 32 , 10, 71000000 ,"+",0,0,0,0,0},//Settings to be define -{ "26 VESA 28 1280x800 @ 60 Hz " , 128 ,831 , 800 ,31 , 6 , 0 , "+" , 1680 ,1280 , 72 , 128 , 10, 83500000 ,"-",0,0,0,0,0},//Settings to be define -{ "27 VESA 39 1360x768 @ 60 Hz " , 139 ,790 , 768 ,22 , 5 , 0 , "-" , 1520 ,1360 , 48 , 32 , 10, 72000000 ,"+",0,0,0,0,0},//Settings to be define -{ "28 VESA 81 1360x768 @ 60 Hz " , 181 ,798 , 768 ,30 , 5 , 0 , "+" , 1776 ,1360 , 72 , 136 , 10, 84750000 ,"-",0,0,0,0,0}//Settings to be define -}; +static wait_queue_head_t av8100_event; +static int av8100_flag = 0x0; -/** av8100 file operations */ -static struct file_operations av8100_fops = { +static const struct file_operations av8100_fops = { .owner = THIS_MODULE, .open = av8100_open, .release = av8100_release, .ioctl = av8100_ioctl }; -/** av8100 misc device structure */ -static struct miscdevice av8100_miscdev = -{ +static struct miscdevice av8100_miscdev = { AV8100_DRIVER_MINOR_NUMBER, "av8100", &av8100_fops }; -/** - * av8100_write_multi_byte() - Write a multiple bytes to av8100 chip(av8100) through i2c interface. - * @client: i2c client structure - * @buf: buffer to be written - * @nbytes: nunmber of bytes to be written - * - * This funtion uses smbus block write API's to write n number of bytes to the av8100 - **/ -static int av8100_write_multi_byte(struct i2c_client *client, uint8 regOffset, - uint8 *buf,uint8 nbytes) -{ - int ret = AV8100_OK; - //u8 temp; - - ret = i2c_smbus_write_i2c_block_data(client, regOffset,nbytes, buf); - if (ret < 0) { - printk("i2c smbus write multi byte error\n"); - return ret; - } - length += nbytes; - //printk("length:%d\n", length); -#if 0 - if(nbytes < 40) - { - for (temp = 0; temp < nbytes; temp++) - printk("value:%0x\n", buf[temp]); - printk("FW size:%d\n", length); - } -#endif +struct av8100_cea av8100_all_cea[29] = { +/* cea id + * cea_nr vtot vact vsbpp vslen + * vsfp vpol htot hact hbp hslen hfp freq + * hpol rld bd uix4 pm pd */ +{ "0 CUSTOM ", + 0, 0, 0, 0, 0, + 0, "-", 800, 640, 16, 96, 10, 25200000, + "-", 0, 0, 0, 0, 0},/*Settings to be defined*/ +{ "1 CEA 1 VESA 4 640x480p @ 60 Hz ", + 1, 525, 480, 33, 2, + 10, "-", 800, 640, 49, 290, 146, 25200000, + "-", 2438, 1270, 6, 32, 1},/*RGB888*/ +{ "2 CEA 2 - 3 720x480p @ 60 Hz 4:3 ", + 2, 525, 480, 30, 6, + 9, "-", 858, 720, 34, 130, 128, 27027000, + "-", 1828, 0x3C0, 8, 24, 1},/*RGB565*/ +{ "3 CEA 4 1280x720p @ 60 Hz ", + 4, 750, 720, 20, 5, + 5, "+", 1650, 1280, 114, 39, 228, 74250000, + "+", 1706, 164, 6, 32, 1},/*RGB565*/ +{ "4 CEA 5 1920x1080i @ 60 Hz ", + 5, 1125, 540, 20, 5, + 0, "+", 2200, 1920, 88, 44, 10, 74250000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "5 CEA 6-7 480i (NTSC) ", + 6, 525, 240, 44, 5, + 0, "-", 858, 720, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "6 CEA 14-15 480p @ 60 Hz ", + 14, 525, 480, 44, 5, + 0, "-", 858, 720, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "7 CEA 16 1920x1080p @ 60 Hz ", + 16, 1125, 1080, 36, 5, + 0, "+", 1980, 1280, 440, 40, 10, 74250000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "8 CEA 17-18 720x576p @ 50 Hz ", + 17, 625, 576, 44, 5, + 0, "-", 864, 720, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "9 CEA 19 1280x720p @ 50 Hz ", + 19, 750, 720, 25, 5, + 0, "+", 1980, 1280, 440, 40, 10, 74250000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "10 CEA 20 1920 x 1080i @ 50 Hz ", + 20, 1125, 540, 20, 5, + 0, "+", 2640, 1920, 528, 44, 10, 74250000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "11 CEA 21-22 576i (PAL) ", + 21, 625, 288, 44, 5, + 0, "-", 864, 720, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "12 CEA 29/30 576p ", + 29, 625, 576, 44, 5, + 0, "-", 864, 720, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "13 CEA 31 1080p 50Hz ", + 31, 1125, 1080, 44, 5, + 0, "-", 2750, 1920, 12, 64, 10, 27000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "14 CEA 32 1920x1080p @ 24 Hz ", + 32, 1125, 1080, 36, 5, + 4, "+", 2750, 1920, 660, 44, 153, 74250000, + "+", 2844, 0x530, 6, 32, 1},/*RGB565*/ +{ "15 CEA 33 1920x1080p @ 25 Hz ", + 33, 1125, 1080, 36, 5, + 4, "+", 2640, 1920, 528, 44, 10, 74250000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "16 CEA 34 1920x1080p @ 30Hz ", + 34, 1125, 1080, 36, 5, + 4, "+", 2200, 1920, 91, 44, 153, 74250000, + "+", 2275, 0xAB, 6, 32, 1},/*RGB565*/ +{ "17 CEA 60 1280x720p @ 24 Hz ", + 60, 750, 720, 20, 5, + 5, "+", 3300, 1280, 284, 50, 2276, 29700000, + "+", 4266, 0xAD0, 5, 32, 1},/*RGB565*/ +{ "18 CEA 61 1280x720p @ 25 Hz ", + 61, 750, 720, 20, 5, + 5, "+", 3960, 1280, 228, 39, 2503, 30937500, + "+", 4096, 0x500, 5, 32, 1},/*RGB565*/ +{ "19 CEA 62 1280x720p @ 30 Hz ", + 62, 750, 720, 20, 5, + 5, "+", 3300, 1280, 228, 39, 1820, 37125000, + "+", 3413, 0x770, 5, 32, 1},/*RGB565*/ +{ "20 VESA 9 800x600 @ 60 Hz ", + 109, 628, 600, 28, 4, + 0, "+", 1056, 800, 40, 128, 10, 40000000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "21 VESA 14 848x480 @ 60 Hz ", + 114, 500, 480, 20, 5, + 0, "+", 1056, 848, 24, 80, 10, 31500000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "22 VESA 16 1024x768 @ 60 Hz ", + 116, 806, 768, 38, 6, + 0, "-", 1344, 1024, 24, 135, 10, 65000000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "23 VESA 22 1280x768 @ 60 Hz ", + 122, 802, 768, 34, 4, + 0, "+", 1688, 1280, 48, 160, 10, 81250000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "24 VESA 23 1280x768 @ 60 Hz ", + 123, 798, 768, 30, 7, + 0, "+", 1664, 1280, 64, 128, 10, 79500000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "25 VESA 27 1280x800 @ 60 Hz ", + 127, 823, 800, 23, 6, + 0, "+", 1440, 1280, 48, 32, 10, 71000000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "26 VESA 28 1280x800 @ 60 Hz ", + 128, 831, 800, 31, 6, + 0, "+", 1680, 1280, 72, 128, 10, 83500000, + "-", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "27 VESA 39 1360x768 @ 60 Hz ", + 139, 790, 768, 22, 5, + 0, "-", 1520, 1360, 48, 32, 10, 72000000, + "+", 0, 0, 0, 0, 0},/*Settings to be define*/ +{ "28 VESA 81 1360x768 @ 60 Hz ", + 181, 798, 768, 30, 5, + 0, "+", 1776, 1360, 72, 136, 10, 84750000, + "-", 0, 0, 0, 0, 0} /*Settings to be define*/ +}; - /* FIXME- workaround,i2c_smbus_write_i2c_block_data doesn't work on this platform!*/ -#if 0 - for(temp=0;temp<nbytes-1;temp++) { - ret = i2c_smbus_write_byte_data(client,0xF/*(regOffset)*/,buf[temp]); - if (ret < 0) { - printk("i2c smbus write byte error\n"); - return ret; - }else - printk("av8100_write_multi_byte ret:%x\n", ret); - } -#endif - return ret; -} -/** - * av8100_write_single_byte() - Write a single byte to av8100 chip(av8100) through i2c interface. - * @client: i2c client structure - * @reg: register offset - * @data: data byte to be written - * - * This funtion uses smbus byte write API to write a single byte to av8100 - **/ -static int av8100_write_single_byte(struct i2c_client *client, uint8 reg, - uint8 data) -{ - int ret = AV8100_OK; +static const struct i2c_device_id av8100_id[] = { + { "av8100", 0 }, + { } +}; - //printk("av8100_write_single_byte: reg=%x,data = %x\n", reg,data); - ret = i2c_smbus_write_byte_data(client,reg,data); - if(ret < 0) { - printk("i2c smbus write byte failed\n"); - return ret; - } - return ret; -} +static struct i2c_driver av8100_driver = { + .probe = av8100_probe, + .remove = av8100_remove, + .driver = { + .name = "av8100", + }, + .id_table = av8100_id, +}; -/** - * av8100_read_multi_byte() - read multiple bytes from av8100 chip(av8100) through i2c interface - * @client: i2c client structure - * @reg: register offset - * @buf: read the data in this buffer - * @nbytes: number of bytes to read - * - * This funtion uses smbus read block API to read multiple bytes from the reg offset. - **/ -#if 0 -static int av8100_read_multi_byte(struct i2c_client *client,uint8 reg, - uint8 *buf, uint8 nbytes) +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS +static void av8100_timer_int(unsigned long value) { - int ret = AV8100_OK; + av8100_flag |= AV8100_TIMER_INT_EVENT; + wake_up_interruptible(&av8100_event); - ret = i2c_smbus_read_i2c_block_data(client,reg,nbytes,buf); - if(ret < 0){ - printk("i2c smbus read multi byte failed\n"); - return ret; + if (g_av8100_status.av8100_state >= AV8100_OPMODE_STANDBY) { + av8100_timer.expires = jiffies + + AV8100_TIMER_INTERRUPT_POLLING_TIME; + add_timer(&av8100_timer); } - if (ret < nbytes){ - printk("i2c smbus read multi byte failed\n"); - return -EIO; - } - return ret; } #endif -/** - * av8100_read_single_byte() - read single byte from av8100 chip(av8100) through i2c interface - * @client: i2c client structure - * @reg: register offset - * @val: register value - * - * This funtion uses smbus read block API to read single byte from the reg offset. - **/ -static int av8100_read_single_byte(struct i2c_client *client,uint8 reg, unsigned char* val) +static int av8100_thread(void *p) { - int ret = AV8100_OK; - int value = 0x0; - value = i2c_smbus_read_byte_data(client, reg); - if(value < 0){ - printk("i2c smbus read byte failed,read data = %x from offset: %x\n" ,value,reg); - return ret; - } - //printk("read data = %x from offset: %x\n" ,value,reg); - *val = value; - return ret; -} - -/** - * get_dcs_data_index_params() - This API is used to get the number of times the data to be sent with the commands. - **/ -void get_dcs_data_index_params(void) -{ - g_dcs_data_count_index = 0; - g_dcs_data_count_last = 0; - g_dcs_data_count_index = g_av8100_cmd_length/DSI_MAX_DATA_WRITE; - g_dcs_data_count_last = g_av8100_cmd_length%DSI_MAX_DATA_WRITE; -} + u8 cpd = 0; + u8 stby = 0; + u8 hpds = 0; + u8 cpds = 0; + u8 mclkrng = 0; + int ret = 0; +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS + u8 hpds_old = 0xf; + u8 cpds_old = 0xf; +#else + u8 sid = 0; + u8 oni = 0; + u8 hpdi = 0; + u8 cpdi = 0; +#endif -/** - * av8100_intr_handler() - To handle av8100 interrupts. - * @irq: irq context - * @av8100Data:av8100 data - * - * This funtion handles the av8100 interrupts. It handles the plugin and plugout(HDMI/CVBS) interrupts. - **/ -static irqreturn_t av8100_intr_handler(int irq, void *p) -{ + while (1) { + wait_event_interruptible(av8100_event, (av8100_flag != 0)); +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS + if (av8100_flag & AV8100_TIMER_INT_EVENT) { + if (g_av8100_status.av8100_state >= + AV8100_OPMODE_STANDBY) { + /* STANDBY */ + ret = av8100_register_standby_read( + &cpd, + &stby, + &hpds, + &cpds, + &mclkrng); + if (ret != 0) + printk(KERN_DEBUG "av8100_register_" + "standby_read fail\n"); + + /* TVout plugin change */ + if ((cpds == 1) && (cpds != cpds_old)) { + cpds_old = 1; + + g_av8100_status.av8100_plugin_status |= + AV8100_CVBS_PLUGIN; + + /* TODO: notify */ + printk(KERN_DEBUG "TVout plugin detected\n"); + } else if ((cpds == 0) && (cpds != cpds_old)) { + cpds_old = 0; + + g_av8100_status.av8100_plugin_status &= + ~AV8100_CVBS_PLUGIN; + + /* TODO: notify */ + printk(KERN_DEBUG "TVout plugout detected\n"); + } -#if 0 - struct av8100_data *av8100DataTemp = p; -#endif + /* HDMI plugin change */ + if ((hpds == 1) && (hpds != hpds_old)) { + hpds_old = 1; -#if 0 - char val = 0x0; - int retval = AV8100_OK; - char val1 = 0x0; - - //printk("av8100_intr_handler is called\n"); - //mdelay(100); - - av8100_read_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, &val); - printk("av8100_intr_handler is called, val:%x, av8100Data->client:%x\n",val, av8100DataTemp->client); - if (start == 0/*val && HDMI_HOTPLUG_INTERRUPT*/) - { - printk("hdmi cable plugin interrupt\n"); - g_av8100_plugin_status = AV8100_HDMI_PLUGIN; - av8100_set_state(AV8100_OPMODE_INIT); - val = 0x0;//~ HDMI_HOTPLUG_INTERRUPT_MASK; - start = 1; - - retval = av8100_write_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, val); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to the av8100 STANDBY_PENDING_INTERRUPT_REG register\n"); - return -EFAULT; - } - retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_VIDEO_INPUT_FORMAT, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n"); - return -EFAULT; - } + g_av8100_status.av8100_plugin_status |= + AV8100_HDMI_PLUGIN; - retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n"); - return -EFAULT; - } + /* TODO: notify */ + printk(KERN_DEBUG "HDMI plugin detected\n"); + } else if ((hpds == 0) && (hpds != hpds_old)) { + hpds_old = 0; - mcde_hdmi_display_init(); - mcde_configure_hdmi_channel(); + g_av8100_status.av8100_plugin_status &= + ~AV8100_HDMI_PLUGIN; - retval = av8100_write_single_byte(av8100DataTemp, GENERAL_INTERRUPT_MASK_REG, 0x60); /* enable TE */ - if(retval != AV8100_OK) - { - printk("Failed to write the value in to the av8100 register\n"); - return -EFAULT; + /* TODO: notify */ + printk(KERN_DEBUG "HDMI plugout detected\n"); + } + } } - - retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n"); - return -EFAULT; +#else + /* STANDBY_PENDING_INTERRUPT */ + ret = av8100_register_standby_pending_interrupt_read( + &hpdi, + &cpdi, + &oni, + &sid); + + if (ret) + printk(KERN_DEBUG "av8100_register_standby_" + "pending_interrupt_read failed\n"); + + if (hpdi | cpdi | oni) { + /* STANDBY */ + ret = av8100_register_standby_read( + &cpd, + &stby, + &hpds, + &cpds, + &mclkrng); + if (ret) + printk(KERN_DEBUG "av8100_register_standby_" + "read fail\n"); } - - } - else if (val && CVBS_PLUG_INTERRUPT) { - g_av8100_plugin_status = AV8100_CVBS_PLUGIN; - av8100_set_state(AV8100_OPMODE_INIT); - val = ~CVBS_PLUG_INTERRUPT_MASK; - av8100_write_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, val); - } - else { - g_av8100_plugin_status = AV8100_PLUGIN_NONE; - } - - retval = av8100_read_single_byte(av8100DataTemp->client, 0x0/*STANDBY_PENDING_INTERRUPT_REG*/, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the STANDBY_PENDING_INTERRUPT_REG\n"); - return -EFAULT; - } - - printk("av8100_read_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, &val1)\n"); - retval = av8100_read_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, &val1); - if(retval != AV8100_OK) - { - printk("Failed to read the GENERAL_INTERRUPT_REG\n"); - return -EFAULT; - } - - if(val1 && TE_INTERRUPT_MASK) - { - //printk("Received the TE interrupt\n"); - retval = av8100_write_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, TE_INTERRUPT_MASK); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to the av8100 GENERAL_INTERRUPT_REG register\n"); - return -EFAULT; + if (cpdi) { + /* TVout plugin change */ + if (cpds) + g_av8100_status.av8100_plugin_status |= + AV8100_CVBS_PLUGIN; + else + g_av8100_status.av8100_plugin_status &= + ~AV8100_CVBS_PLUGIN; + + /* TODO: notify */ + printk(KERN_DEBUG "TVout plugin: %d\n", ( + g_av8100_status.av8100_plugin_status & + AV8100_CVBS_PLUGIN) == AV8100_CVBS_PLUGIN); + } else if (hpdi) { + /* HDMI plugin change */ + if (hpds) + g_av8100_status.av8100_plugin_status |= + AV8100_HDMI_PLUGIN; + else + g_av8100_status.av8100_plugin_status &= + ~AV8100_HDMI_PLUGIN; + + /* TODO: notify */ + printk(KERN_DEBUG "HDMI plugin: %d\n", ( + g_av8100_status.av8100_plugin_status & + AV8100_HDMI_PLUGIN) == AV8100_HDMI_PLUGIN); } - } - if(val1 && UNDER_OVER_FLOW_INTERRUPT_MASK) - { - //printk("Received the underflow/overflow interrupt\n"); - retval = av8100_write_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, UNDER_OVER_FLOW_INTERRUPT_MASK); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to the av8100 GENERAL_INTERRUPT_REG register\n"); - return -EFAULT; + if (hpdi | cpdi | oni) { + /* Clear pending interrupts */ + ret = av8100_register_standby_pending_interrupt_write( + hpdi, + cpdi, + oni); + if (ret) + printk(KERN_DEBUG "av8100_register_standby_" + "read fail\n"); } - } #endif + av8100_flag = 0; + } -#ifdef AV8100_USE_KERNEL_THREAD - av8100_flag = 1; + return ret; +} + +static irqreturn_t av8100_intr_handler(int irq, void *p) +{ + av8100_flag |= AV8100_INT_EVENT; wake_up_interruptible(&av8100_event); -#else - u8500_mcde_tasklet_4(0); -#endif return IRQ_HANDLED; } - -/** - * av8100_configure_hdmi() - To configure the av8100 chip for hdmi. - * @av8100Data:av8100 data - * - * This funtion configures the video input, video output, test pattern and hdmi on commands. - **/ -static void av8100_configure_hdmi(struct i2c_client *i2c) +static u16 av8100_get_te_line_nb( + enum av8100_output_CEA_VESA output_video_format) { - char val = 0x0; - int retval = AV8100_OK; + u16 retval; -#if 0 - av8100_read_single_byte(i2c, STANDBY_PENDING_INTERRUPT_REG, &val); - printk("av8100_intr_handler is called, val:%x, av8100Data->client:%x\n",val, i2c); -#endif + switch (output_video_format) { + case AV8100_CEA1_640X480P_59_94HZ: + case AV8100_CEA2_3_720X480P_59_94HZ: + retval = AV8100_TE_LINE_NB_30; + break; - retval = av8100_write_single_byte(i2c, STANDBY_PENDING_INTERRUPT_REG, val); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to the av8100 STANDBY_PENDING_INTERRUPT_REG register\n"); - return; - } + case AV8100_CEA5_1920X1080I_60HZ: + case AV8100_CEA6_7_NTSC_60HZ: + case AV8100_CEA20_1920X1080I_50HZ: + retval = AV8100_TE_LINE_NB_18; + break; -#ifndef TEST_PATTERN_TEST - retval = av8100_send_command (i2c, AV8100_COMMAND_VIDEO_INPUT_FORMAT,/*DSI_INTERFACE*/I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n"); - return; - } + case AV8100_CEA4_1280X720P_60HZ: + retval = AV8100_TE_LINE_NB_21; + break; -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - retval = av8100_send_command (i2c, AV8100_COMMAND_COLORSPACECONVERSION, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_COLORSPACECONVERSION command\n"); - return; - } -#endif /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ + case AV8100_CEA17_18_720X576P_50HZ: + retval = AV8100_TE_LINE_NB_40; + break; -#else /* TEST_PATTERN_TEST */ -#ifndef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV + case AV8100_CEA19_1280X720P_50HZ: + retval = AV8100_TE_LINE_NB_22; + break; - retval = av8100_send_command (i2c, AV8100_COMMAND_PATTERNGENERATOR, /*DSI_INTERFACE*/I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_PATTERNGENERATOR command\n"); - return; - } -#endif /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ -#endif - retval = av8100_send_command (i2c, AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_VIDEO_OUTPUT_FORMAT command\n"); - return; - } -#ifndef TEST_PATTERN_TEST -#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI - mcde_hdmi_display_init_video_mode(); + case AV8100_CEA21_22_576I_PAL_50HZ: + /* Different values below come from LLD, + * TODO: check if this is really needed + * if not merge with AV8100_CEA6_7_NTSC_60HZ case + */ +#ifdef CONFIG_AV8100_SDTV + retval = AV8100_TE_LINE_NB_18; +#else + retval = AV8100_TE_LINE_NB_17; #endif - retval = av8100_send_command (i2c, AV8100_COMMAND_AUDIO_INPUT_FORMAT, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_AUDIO_INPUT_FORMAT command\n"); - return; + break; + + case AV8100_CEA32_1920X1080P_24HZ: + case AV8100_CEA33_1920X1080P_25HZ: + case AV8100_CEA34_1920X1080P_30HZ: + retval = AV8100_TE_LINE_NB_38; + break; + + case AV8100_CEA60_1280X720P_24HZ: + case AV8100_CEA62_1280X720P_30HZ: + retval = AV8100_TE_LINE_NB_21; + break; + + case AV8100_CEA14_15_480p_60HZ: + case AV8100_VESA14_848X480P_60HZ: + case AV8100_CEA61_1280X720P_25HZ: + case AV8100_CEA16_1920X1080P_60HZ: + case AV8100_CEA31_1920x1080P_50Hz: + case AV8100_CEA29_30_576P_50HZ: + case AV8100_VESA9_800X600P_60_32HZ: + case AV8100_VESA16_1024X768P_60HZ: + case AV8100_VESA22_1280X768P_59_99HZ: + case AV8100_VESA23_1280X768P_59_87HZ: + case AV8100_VESA27_1280X800P_59_91HZ: + case AV8100_VESA28_1280X800P_59_81HZ: + case AV8100_VESA39_1360X768P_60_02HZ: + case AV8100_VESA81_1366X768P_59_79HZ: + default: + /* TODO */ + retval = AV8100_TE_LINE_NB_14; + break; } -#endif /* TEST_PATTERN_TEST */ - av8100_configure_denc(av8100Data); - return; + + return retval; } -static void av8100_configure_denc(struct av8100_data *av8100DataTemp) +static u16 av8100_get_ui_x4( + enum av8100_output_CEA_VESA output_video_format) { - if (AV8100_OK != av8100_send_command(av8100DataTemp->client, - AV8100_COMMAND_DENC, I2C_INTERFACE)) { - printk("Failed to send the AV8100_COMMAND_DENC command\n"); - } - return; + return AV8100_UI_X4_DEFAULT; } -static void av8100_hdmi_on(struct av8100_data *av8100DataTemp) +static int av8100_config_video_output_dep(enum av8100_output_CEA_VESA + output_format) { - int retval = AV8100_OK; + int retval = 0; + union av8100_configuration config; + + /* video input */ + config.video_input_format.dsi_input_mode = + AV8100_HDMI_DSI_COMMAND_MODE; + config.video_input_format.input_pixel_format = AV8100_INPUT_PIX_RGB565; + config.video_input_format.total_horizontal_pixel = + av8100_all_cea[output_format].htotale; + config.video_input_format.total_horizontal_active_pixel = + av8100_all_cea[output_format].hactive; + config.video_input_format.total_vertical_lines = + av8100_all_cea[output_format].vtotale; + config.video_input_format.total_vertical_active_lines = + av8100_all_cea[output_format].vactive; + + switch (output_format) { + case AV8100_CEA5_1920X1080I_60HZ: + case AV8100_CEA20_1920X1080I_50HZ: + case AV8100_CEA21_22_576I_PAL_50HZ: + case AV8100_CEA6_7_NTSC_60HZ: + config.video_input_format.video_mode = + AV8100_VIDEO_INTERLACE; + break; - HDMI_TRACE; - hdmi_cmd.hdmi_mode = AV8100_HDMI_ON; - hdmi_cmd.hdmi_format = AV8100_HDMI; + default: + config.video_input_format.video_mode = + AV8100_VIDEO_PROGRESSIVE; + break; + } - retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_HDMI command\n"); - return; + config.video_input_format.nb_data_lane = + AV8100_DATA_LANES_USED_2; + config.video_input_format.nb_virtual_ch_command_mode = 0; + config.video_input_format.nb_virtual_ch_video_mode = 0; + config.video_input_format.ui_x4 = av8100_get_ui_x4(output_format); + config.video_input_format.TE_line_nb = av8100_get_te_line_nb( + output_format); + config.video_input_format.TE_config = AV8100_TE_IT_LINE; + config.video_input_format.master_clock_freq = 0; + + retval = av8100_configuration_prepare( + AV8100_COMMAND_VIDEO_INPUT_FORMAT, &config); + + /* DENC */ + switch (output_format) { + case AV8100_CEA21_22_576I_PAL_50HZ: + config.denc_format.cvbs_video_format = AV8100_CVBS_625; + config.denc_format.standard_selection = AV8100_PAL_BDGHI; + break; + + case AV8100_CEA6_7_NTSC_60HZ: + config.denc_format.cvbs_video_format = AV8100_CVBS_525; + config.denc_format.standard_selection = AV8100_NTSC_M; + break; + + default: + /* Not supported */ + break; } - return; + + return retval; } -static void av8100_hdmi_off(struct av8100_data *av8100DataTemp) +static int av8100_config_init(void) { - int retval = AV8100_OK; + int retval = 0; + union av8100_configuration config; - HDMI_TRACE; - hdmi_cmd.hdmi_mode = AV8100_HDMI_OFF; - hdmi_cmd.hdmi_format = AV8100_HDMI; + printk(KERN_DEBUG "%s\n", __func__); - retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE); - if(retval != AV8100_OK) - { - printk("Failed to send the AV8100_COMMAND_HDMI command\n"); - return; + av8100_config = kzalloc(sizeof(struct av8100_config_t), GFP_KERNEL); + if (!av8100_config) { + pr_err("%s: Failed to allocate config\n", __func__); + return AV8100_FAIL; } - return; -} -/** - * configure_av8100_video_input() - This function will be used to configure the video input of AV8100. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_video_input(char* buffer_temp) -{ - int retval = AV8100_OK; - - HDMI_TRACE; - buffer_temp[0] = hdmi_video_input_cmd.dsi_input_mode;//mcde_get_dsi_mode_config(); - buffer_temp[1] = hdmi_video_input_cmd.input_pixel_format;//mcde_get_input_bpp(); - buffer_temp[2] = REG_16_8_MSB(hdmi_video_input_cmd.total_horizontal_pixel); - buffer_temp[3] = REG_16_8_LSB(hdmi_video_input_cmd.total_horizontal_pixel); - buffer_temp[4] = REG_16_8_MSB(hdmi_video_input_cmd.total_horizontal_active_pixel); - buffer_temp[5] = REG_16_8_LSB(hdmi_video_input_cmd.total_horizontal_active_pixel); - - buffer_temp[6] = REG_16_8_MSB(hdmi_video_input_cmd.total_vertical_lines); - buffer_temp[7] = REG_16_8_LSB(hdmi_video_input_cmd.total_vertical_lines); - buffer_temp[8] = REG_16_8_MSB(hdmi_video_input_cmd.total_vertical_active_lines); - buffer_temp[9] = REG_16_8_LSB(hdmi_video_input_cmd.total_vertical_active_lines); - buffer_temp[10] = hdmi_video_input_cmd.video_mode;//mcde_get_hdmi_scan_mode(); - buffer_temp[11] = hdmi_video_input_cmd.nb_data_lane;//AV8100_DATA_LANES_USED_2; - buffer_temp[12] = hdmi_video_input_cmd.nb_virtual_ch_command_mode; - buffer_temp[13] = hdmi_video_input_cmd.nb_virtual_ch_video_mode; - buffer_temp[14] = REG_16_8_MSB(hdmi_video_input_cmd.TE_line_nb); - buffer_temp[15] = REG_16_8_LSB(hdmi_video_input_cmd.TE_line_nb); - buffer_temp[16] = hdmi_video_input_cmd.TE_config; - buffer_temp[17] = REG_32_8_MSB(hdmi_video_input_cmd.master_clock_freq); - buffer_temp[18] = REG_32_8_MMSB(hdmi_video_input_cmd.master_clock_freq); - buffer_temp[19] = REG_32_8_MLSB(hdmi_video_input_cmd.master_clock_freq); - buffer_temp[20] = REG_32_8_LSB(hdmi_video_input_cmd.master_clock_freq); - buffer_temp[21] = hdmi_video_input_cmd.ui_x4; /* UI value */ - - g_av8100_cmd_length = AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE - 1; + memset(&config, 0, sizeof(union av8100_configuration)); + memset(av8100_config, 0, sizeof(union av8100_configuration)); + + /* Color conversion */ + config.color_space_conversion_format.c0 = 0xFFDA; + config.color_space_conversion_format.c1 = 0xFFB6; + config.color_space_conversion_format.c2 = 0x0070; + config.color_space_conversion_format.c3 = 0x0042; + config.color_space_conversion_format.c4 = 0x0081; + config.color_space_conversion_format.c5 = 0x0019; + config.color_space_conversion_format.c6 = 0x0070; + config.color_space_conversion_format.c7 = 0xFFA2; + config.color_space_conversion_format.c8 = 0xFFEE; + config.color_space_conversion_format.aoffset = 0x007F; + config.color_space_conversion_format.boffset = 0x0010; + config.color_space_conversion_format.coffset = 0x007F; + config.color_space_conversion_format.lmax = 0xEB; + config.color_space_conversion_format.lmin = 0x10; + config.color_space_conversion_format.cmax = 0xF0; + config.color_space_conversion_format.cmin = 0x10; + retval = av8100_configuration_prepare( + AV8100_COMMAND_COLORSPACECONVERSION, &config); + if (retval) + return AV8100_FAIL; + + /* DENC */ + config.denc_format.cvbs_video_format = AV8100_CVBS_625; + config.denc_format.standard_selection = AV8100_PAL_BDGHI; + config.denc_format.on_off = 0; + config.denc_format.macrovision_on_off = 0; + config.denc_format.internal_generator = 0; + + /* Video output */ + config.video_output_format.video_output_cea_vesa = + AV8100_CEA4_1280X720P_60HZ; + + retval = av8100_configuration_prepare( + AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, &config); + if (retval) + return AV8100_FAIL; + + /* Video input */ + av8100_config_video_output_dep( + config.video_output_format.video_output_cea_vesa); + + /* Pattern generator */ + config.pattern_generator_format.pattern_audio_mode = + AV8100_PATTERN_AUDIO_OFF; + config.pattern_generator_format.pattern_type = + AV8100_PATTERN_GENERATOR; + config.pattern_generator_format.pattern_video_format = + AV8100_PATTERN_720P; + retval = av8100_configuration_prepare(AV8100_COMMAND_PATTERNGENERATOR, + &config); + if (retval) + return AV8100_FAIL; + + /* Audio input */ + config.audio_input_format.audio_input_if_format = + AV8100_AUDIO_I2SDELAYED_MODE; + config.audio_input_format.i2s_input_nb = 1; + config.audio_input_format.sample_audio_freq = AV8100_AUDIO_FREQ_48KHZ; + config.audio_input_format.audio_word_lg = AV8100_AUDIO_16BITS; + config.audio_input_format.audio_format = AV8100_AUDIO_LPCM_MODE; + config.audio_input_format.audio_if_mode = AV8100_AUDIO_MASTER; + config.audio_input_format.audio_mute = AV8100_AUDIO_MUTE_DISABLE; + retval = av8100_configuration_prepare( + AV8100_COMMAND_AUDIO_INPUT_FORMAT, &config); + if (retval) + return AV8100_FAIL; + + /* HDMI mode */ + config.hdmi_format.hdmi_mode = AV8100_HDMI_ON; + config.hdmi_format.hdmi_format = AV8100_HDMI; + config.hdmi_format.dvi_format = AV8100_DVI_CTRL_CTL0; + retval = av8100_configuration_prepare(AV8100_COMMAND_HDMI, &config); + if (retval) + return AV8100_FAIL; + + /* EDID section readback */ + config.edid_section_readback_format.address = 0xA0; + config.edid_section_readback_format.block_number = 0; + retval = av8100_configuration_prepare( + AV8100_COMMAND_EDID_SECTION_READBACK, &config); + if (retval) + return AV8100_FAIL; + return retval; +} +static void av8100_config_exit(void) +{ + printk(KERN_DEBUG "%s\n", __func__); + + kfree(av8100_config); + av8100_config = NULL; +} + +static void av8100_set_state(enum av8100_operating_mode state) +{ + g_av8100_status.av8100_state = state; } + /** - * configure_av8100_audio_output() - This function will be used to configure the audio input of AV8100. - * @buffer_temp: configuration pointer + * write_single_byte() - Write a single byte to av8100 + * through i2c interface. + * @client: i2c client structure + * @reg: register offset + * @data: data byte to be written * + * This funtion uses smbus byte write API to write a single byte to av8100 **/ -static int configure_av8100_audio_input(char* buffer_temp) +static int write_single_byte(struct i2c_client *client, u8 reg, + u8 data) { - int retval = AV8100_OK; + int ret; - HDMI_TRACE; - buffer_temp[0] = hdmi_audio_input_cmd.audio_input_if_format; - buffer_temp[1] = hdmi_audio_input_cmd.i2s_input_nb; - buffer_temp[2] = hdmi_audio_input_cmd.sample_audio_freq; - buffer_temp[3] = hdmi_audio_input_cmd.audio_word_lg; - buffer_temp[4] = hdmi_audio_input_cmd.audio_format; - buffer_temp[5] = hdmi_audio_input_cmd.audio_if_mode; - buffer_temp[6] = hdmi_audio_input_cmd.audio_mute; + ret = i2c_smbus_write_byte_data(client, reg, data); + if (ret < 0) + printk(KERN_DEBUG "i2c smbus write byte failed\n"); - g_av8100_cmd_length = AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE - 1; - return retval; + return ret; } /** - * configure_av8100_video_output() - This function will be used to configure the video output of AV8100. - * @buffer_temp: configuration pointer + * read_single_byte() - read single byte from av8100 + * through i2c interface + * @client: i2c client structure + * @reg: register offset + * @val: register value * + * This funtion uses smbus read block API to read single byte from the reg + * offset. **/ -static int configure_av8100_video_output(char* buffer_temp) -{ - int retval = AV8100_OK; - - HDMI_TRACE; - buffer_temp[0] = hdmi_video_output_cmd.video_output_cea_vesa; - - if (buffer_temp[0] == AV8100_CUSTOM) { - buffer_temp[1] = hdmi_video_output_cmd.vsync_polarity; - buffer_temp[2] = hdmi_video_output_cmd.hsync_polarity; - buffer_temp[3] = REG_16_8_MSB(hdmi_video_output_cmd.total_horizontal_pixel); - buffer_temp[4] = REG_16_8_LSB(hdmi_video_output_cmd.total_horizontal_pixel); - buffer_temp[5] = REG_16_8_MSB(hdmi_video_output_cmd.total_horizontal_active_pixel); - buffer_temp[6] = REG_16_8_LSB(hdmi_video_output_cmd.total_horizontal_active_pixel); - buffer_temp[7] = REG_16_8_MSB(hdmi_video_output_cmd.total_vertical_in_half_lines); - buffer_temp[8] = REG_16_8_LSB(hdmi_video_output_cmd.total_vertical_in_half_lines); - buffer_temp[9] = REG_16_8_MSB(hdmi_video_output_cmd.total_vertical_active_in_half_lines); - buffer_temp[10] = REG_16_8_LSB(hdmi_video_output_cmd.total_vertical_active_in_half_lines); - buffer_temp[11] = REG_16_8_MSB(hdmi_video_output_cmd.hsync_start_in_pixel); - buffer_temp[12] = REG_16_8_LSB(hdmi_video_output_cmd.hsync_start_in_pixel); - buffer_temp[13] = REG_16_8_MSB(hdmi_video_output_cmd.hsync_length_in_pixel); - buffer_temp[14] = REG_16_8_LSB(hdmi_video_output_cmd.hsync_length_in_pixel); - buffer_temp[15] = REG_16_8_MSB(hdmi_video_output_cmd.vsync_start_in_half_line); - buffer_temp[16] = REG_16_8_LSB(hdmi_video_output_cmd.vsync_start_in_half_line); - buffer_temp[17] = REG_16_8_MSB(hdmi_video_output_cmd.vsync_length_in_half_line); - buffer_temp[18] = REG_16_8_LSB(hdmi_video_output_cmd.vsync_length_in_half_line); - buffer_temp[19] = REG_32_8_MSB(hdmi_video_output_cmd.pixel_clock_freq_Hz); - buffer_temp[20] = REG_32_8_MMSB(hdmi_video_output_cmd.pixel_clock_freq_Hz); - buffer_temp[21] = REG_32_8_MLSB(hdmi_video_output_cmd.pixel_clock_freq_Hz); - buffer_temp[22] = REG_32_8_LSB(hdmi_video_output_cmd.pixel_clock_freq_Hz); - - g_av8100_cmd_length = AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE - 1; - } - else { - g_av8100_cmd_length = 1; +static int read_single_byte(struct i2c_client *client, u8 reg, u8 *val) +{ + int value; + + value = i2c_smbus_read_byte_data(client, reg); + if (value < 0) { + printk(KERN_DEBUG "i2c smbus read byte failed,read data = %x " + "from offset:%x\n" , value, reg); + return AV8100_FAIL; } - return retval; + *val = (u8) value; + return 0; } /** - * configure_av8100_video_scaling() - This function will be used to configure the video scaling params of AV8100. - * @buffer_temp: configuration pointer + * write_multi_byte() - Write a multiple bytes to av8100 through + * i2c interface. + * @client: i2c client structure + * @buf: buffer to be written + * @nbytes: nunmber of bytes to be written * + * This funtion uses smbus block write API's to write n number of bytes to the + * av8100 **/ -static int configure_av8100_video_scaling(char* buffer_temp) +static int write_multi_byte(struct i2c_client *client, u8 reg, + u8 *buf, u8 nbytes) { - int retval = AV8100_OK; + int ret; - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE - 1; - return retval; + ret = i2c_smbus_write_i2c_block_data(client, reg, nbytes, buf); + if (ret < 0) + printk(KERN_DEBUG "i2c smbus write multi byte error\n"); + + return ret; } -/** - * configure_av8100_colorspace_conversion() - This function will be used to configure the color conversion params of AV8100. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_colorspace_conversion(char* buffer_temp) -{ - int retval = AV8100_OK; - int i = 0; - - HDMI_TRACE; - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c0); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c0); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c1); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c1); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c2); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c2); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c3); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c3); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c4); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c4); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c5); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c5); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c6); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c6); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c7); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c7); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c8); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c8); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.a_offset); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.a_offset); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.b_offset); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.b_offset); - buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c_offset); - buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c_offset); - buffer_temp[i++] = hdmi_color_conversion_cmd.l_max; - buffer_temp[i++] = hdmi_color_conversion_cmd.l_min; - buffer_temp[i++] = hdmi_color_conversion_cmd.c_max; - buffer_temp[i++] = hdmi_color_conversion_cmd.c_min; - g_av8100_cmd_length = i; - return retval; +static int configuration_video_input_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_video_input_cmd.dsi_input_mode; + buffer[1] = av8100_config->hdmi_video_input_cmd.input_pixel_format; + buffer[2] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd. + total_horizontal_pixel); + buffer[3] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd. + total_horizontal_pixel); + buffer[4] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd. + total_horizontal_active_pixel); + buffer[5] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd. + total_horizontal_active_pixel); + buffer[6] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd. + total_vertical_lines); + buffer[7] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd. + total_vertical_lines); + buffer[8] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd. + total_vertical_active_lines); + buffer[9] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd. + total_vertical_active_lines); + buffer[10] = av8100_config->hdmi_video_input_cmd.video_mode; + buffer[11] = av8100_config->hdmi_video_input_cmd.nb_data_lane; + buffer[12] = av8100_config->hdmi_video_input_cmd. + nb_virtual_ch_command_mode; + buffer[13] = av8100_config->hdmi_video_input_cmd. + nb_virtual_ch_video_mode; + buffer[14] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd. + TE_line_nb); + buffer[15] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd. + TE_line_nb); + buffer[16] = av8100_config->hdmi_video_input_cmd.TE_config; + buffer[17] = REG_32_8_MSB(av8100_config->hdmi_video_input_cmd. + master_clock_freq); + buffer[18] = REG_32_8_MMSB(av8100_config->hdmi_video_input_cmd. + master_clock_freq); + buffer[19] = REG_32_8_MLSB(av8100_config->hdmi_video_input_cmd. + master_clock_freq); + buffer[20] = REG_32_8_LSB(av8100_config->hdmi_video_input_cmd. + master_clock_freq); + buffer[21] = av8100_config->hdmi_video_input_cmd.ui_x4; + + *length = AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE - 1; + return 0; + } -/** - * configure_av8100_cec_message_write() - This function will be used to configure the CEC message to AV8100. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_cec_message_write(char* buffer_temp) +static int configuration_audio_input_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_audio_input_cmd. + audio_input_if_format; + buffer[1] = av8100_config->hdmi_audio_input_cmd.i2s_input_nb; + buffer[2] = av8100_config->hdmi_audio_input_cmd.sample_audio_freq; + buffer[3] = av8100_config->hdmi_audio_input_cmd.audio_word_lg; + buffer[4] = av8100_config->hdmi_audio_input_cmd.audio_format; + buffer[5] = av8100_config->hdmi_audio_input_cmd.audio_if_mode; + buffer[6] = av8100_config->hdmi_audio_input_cmd.audio_mute; + + *length = AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE - 1; + return 0; +} + +static int configuration_video_output_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_video_output_cmd. + video_output_cea_vesa; + + if (buffer[0] == AV8100_CUSTOM) { + buffer[1] = av8100_config->hdmi_video_output_cmd. + vsync_polarity; + buffer[2] = av8100_config->hdmi_video_output_cmd. + hsync_polarity; + buffer[3] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.total_horizontal_pixel); + buffer[4] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.total_horizontal_pixel); + buffer[5] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.total_horizontal_active_pixel); + buffer[6] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.total_horizontal_active_pixel); + buffer[7] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.total_vertical_in_half_lines); + buffer[8] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.total_vertical_in_half_lines); + buffer[9] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd. + total_vertical_active_in_half_lines); + buffer[10] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd. + total_vertical_active_in_half_lines); + buffer[11] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.hsync_start_in_pixel); + buffer[12] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.hsync_start_in_pixel); + buffer[13] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.hsync_length_in_pixel); + buffer[14] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.hsync_length_in_pixel); + buffer[15] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.vsync_start_in_half_line); + buffer[16] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.vsync_start_in_half_line); + buffer[17] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.vsync_length_in_half_line); + buffer[18] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.vsync_length_in_half_line); + buffer[19] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.hor_video_start_pixel); + buffer[20] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.hor_video_start_pixel); + buffer[21] = REG_16_8_MSB(av8100_config-> + hdmi_video_output_cmd.vert_video_start_pixel); + buffer[22] = REG_16_8_LSB(av8100_config-> + hdmi_video_output_cmd.vert_video_start_pixel); + buffer[23] = av8100_config-> + hdmi_video_output_cmd.video_type; + buffer[24] = av8100_config-> + hdmi_video_output_cmd.pixel_repeat; + buffer[25] = REG_32_8_MSB(av8100_config-> + hdmi_video_output_cmd.pixel_clock_freq_Hz); + buffer[26] = REG_32_8_MMSB(av8100_config-> + hdmi_video_output_cmd.pixel_clock_freq_Hz); + buffer[27] = REG_32_8_MLSB(av8100_config-> + hdmi_video_output_cmd.pixel_clock_freq_Hz); + buffer[28] = REG_32_8_LSB(av8100_config-> + hdmi_video_output_cmd.pixel_clock_freq_Hz); + + *length = AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE - 1; + } else { + *length = 1; + } - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE; - return retval; + return 0; } -/** - * configure_av8100_cec_message_read() - This function will be used to read CEC message from AV8100. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_cec_message_read(char* buffer_temp) +static int configuration_video_scaling_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + h_start_in_pixel); + buffer[1] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + h_start_in_pixel); + buffer[2] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + h_stop_in_pixel); + buffer[3] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + h_stop_in_pixel); + buffer[4] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + v_start_in_line); + buffer[5] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + v_start_in_line); + buffer[6] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + v_stop_in_line); + buffer[7] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + v_stop_in_line); + buffer[8] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + h_start_out_pixel); + buffer[9] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd + .h_start_out_pixel); + buffer[10] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + h_stop_out_pixel); + buffer[11] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + h_stop_out_pixel); + buffer[12] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + v_start_out_line); + buffer[13] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + v_start_out_line); + buffer[14] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd. + v_stop_out_line); + buffer[15] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd. + v_stop_out_line); + + *length = AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE - 1; + return 0; +} - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE; - return retval; +static int configuration_colorspace_conversion_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c0); + buffer[1] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c0); + buffer[2] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c1); + buffer[3] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c1); + buffer[4] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c2); + buffer[5] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c2); + buffer[6] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c3); + buffer[7] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c3); + buffer[8] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c4); + buffer[9] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c4); + buffer[10] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c5); + buffer[11] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c5); + buffer[12] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c6); + buffer[13] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c6); + buffer[14] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c7); + buffer[15] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c7); + buffer[16] = REG_10_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.c8); + buffer[17] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.c8); + buffer[18] = REG_16_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.aoffset); + buffer[19] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.aoffset); + buffer[20] = REG_16_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.boffset); + buffer[21] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.boffset); + buffer[22] = REG_16_8_MSB(av8100_config-> + hdmi_color_space_conversion_cmd.coffset); + buffer[23] = REG_16_8_LSB(av8100_config-> + hdmi_color_space_conversion_cmd.coffset); + buffer[24] = av8100_config->hdmi_color_space_conversion_cmd.lmax; + buffer[25] = av8100_config->hdmi_color_space_conversion_cmd.lmin; + buffer[26] = av8100_config->hdmi_color_space_conversion_cmd.cmax; + buffer[27] = av8100_config->hdmi_color_space_conversion_cmd.cmin; + + *length = AV8100_COMMAND_COLORSPACECONVERSION_SIZE - 1; + return 0; } -/** - * configure_av8100_denc() - This function will be used to configure the denc, - * which is used for SDTV (CVBS). - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_denc(char* buffer_temp) +static int configuration_cec_message_write_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; - HDMI_TRACE; + buffer[0] = av8100_config->hdmi_cec_message_write_cmd.buffer_length; + memcpy(&buffer[1], av8100_config->hdmi_cec_message_write_cmd.buffer, + HDMI_CEC_MESSAGE_WRITE_BUFFER_SIZE); - /* Start with PAL std format */ - buffer_temp[0] = hdmi_denc_cmd.tv_lines; - buffer_temp[1] = hdmi_denc_cmd.tv_std; - buffer_temp[2] = hdmi_denc_cmd.denc; - buffer_temp[3] = hdmi_denc_cmd.macrovision; - buffer_temp[4] = hdmi_denc_cmd.internal_generator; - buffer_temp[5] = hdmi_denc_cmd.chroma; + *length = AV8100_COMMAND_CEC_MESSAGE_WRITE_SIZE - 1; + return 0; +} - g_av8100_cmd_length = AV8100_COMMAND_DENC_SIZE - 1; - return retval; +static int configuration_cec_message_read_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + /* No buffer data */ + *length = AV8100_COMMAND_CEC_MESSAGE_READ_BACK_SIZE - 1; + return 0; } -/** - * configure_av8100_hdmi() - This function will be used to configure the HDMI . - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_hdmi(char* buffer_temp) +static int configuration_denc_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; - HDMI_TRACE; - buffer_temp[0] = hdmi_cmd.hdmi_mode; - buffer_temp[1] = hdmi_cmd.hdmi_format; - buffer_temp[2] = hdmi_cmd.dvi_format; + buffer[0] = av8100_config->hdmi_denc_cmd.cvbs_video_format; + buffer[1] = av8100_config->hdmi_denc_cmd.standard_selection; + buffer[2] = av8100_config->hdmi_denc_cmd.on_off; + buffer[3] = av8100_config->hdmi_denc_cmd.macrovision_on_off; + buffer[4] = av8100_config->hdmi_denc_cmd.internal_generator; - g_av8100_cmd_length = AV8100_COMMAND_HDMI_SIZE - 1; - return retval; + *length = AV8100_COMMAND_DENC_SIZE - 1; + return 0; } -/** - * configure_av8100_hdcp_senkey() - This function will be used to configure the hdcp send key. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_hdcp_senkey(char* buffer_temp) +static int configuration_hdmi_get(char *buffer, unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_HDCP_SENDKEY_SIZE; - return retval; + buffer[0] = av8100_config->hdmi_cmd.hdmi_mode; + buffer[1] = av8100_config->hdmi_cmd.hdmi_format; + buffer[2] = av8100_config->hdmi_cmd.dvi_format; + + *length = AV8100_COMMAND_HDMI_SIZE - 1; + return 0; } -/** - * configure_av8100_hdcp_management() - This function will be used to configure the hdcp management. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_hdcp_management(char* buffer_temp) +static int configuration_hdcp_sendkey_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_HDCP_MANAGEMENT_SIZE; - return retval; + buffer[0] = av8100_config->hdmi_hdcp_send_key_cmd.key_number; + buffer[1] = 0; + memcpy(&buffer[2], av8100_config->hdmi_hdcp_send_key_cmd.key, + HDMI_HDCP_SEND_KEY_SIZE); + + *length = AV8100_COMMAND_HDCP_SENDKEY_SIZE - 1; + return 0; } -/** - * configure_av8100_infoframe() - This function will be used to configure the info frame. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_infoframe(char* buffer_temp) +static int configuration_hdcp_management_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_hdcp_management_format_cmd. + request_hdcp_revocation_list; + buffer[1] = av8100_config->hdmi_hdcp_management_format_cmd. + request_encrypted_transmission; + buffer[2] = av8100_config->hdmi_hdcp_management_format_cmd. + oess_eess_encryption_use; + + *length = AV8100_COMMAND_HDCP_MANAGEMENT_SIZE - 1; + return 0; +} + +static int configuration_infoframe_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_infoframes_cmd.type; + buffer[1] = av8100_config->hdmi_infoframes_cmd.version; + buffer[2] = av8100_config->hdmi_infoframes_cmd.length; + buffer[3] = av8100_config->hdmi_infoframes_cmd.crc; + memcpy(&buffer[4], av8100_config->hdmi_infoframes_cmd.data, + HDMI_INFOFRAME_DATA_SIZE); + + *length = AV8100_COMMAND_INFOFRAMES_SIZE - 1; + return 0; +} + +static int av8100_edid_section_readback_get(char *buffer, unsigned int *length) +{ + buffer[0] = av8100_config->hdmi_edid_section_readback_cmd.address; + buffer[1] = av8100_config->hdmi_edid_section_readback_cmd. + block_number; + + *length = AV8100_COMMAND_EDID_SECTION_READBACK_SIZE - 1; + return 0; +} + +static int configuration_pattern_generator_get(char *buffer, + unsigned int *length) +{ + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_pattern_generator_cmd.pattern_type; + buffer[1] = av8100_config->hdmi_pattern_generator_cmd. + pattern_video_format; + buffer[2] = av8100_config->hdmi_pattern_generator_cmd. + pattern_audio_mode; + + *length = AV8100_COMMAND_PATTERNGENERATOR_SIZE - 1; + return 0; +} + +static int configuration_fuse_aes_key_get(char *buffer, + unsigned int *length) { - int retval = AV8100_OK; + if (!av8100_config) + return AV8100_FAIL; + + buffer[0] = av8100_config->hdmi_fuse_aes_key_cmd.fuse_operation; + memcpy(&buffer[1], av8100_config->hdmi_fuse_aes_key_cmd.key, + HDMI_FUSE_AES_KEY_SIZE); + + *length = AV8100_COMMAND_FUSE_AES_KEY_SIZE - 1; + return 0; +} + +static int get_command_return_data(struct i2c_client *i2c, + enum av8100_command_type command_type, + u8 *command_buffer, + u8 *buffer_length, + u8 *buffer) +{ + int retval = 0; + char val; + int index = 0; + + /* Get the first return byte */ + retval = read_single_byte(i2c, AV8100_COMMAND_OFFSET, &val); + if (retval) + goto get_command_return_data_fail; + + if (val != (0x80 | command_type)) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + switch (command_type) { + case AV8100_COMMAND_VIDEO_INPUT_FORMAT: + case AV8100_COMMAND_AUDIO_INPUT_FORMAT: + case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: + case AV8100_COMMAND_VIDEO_SCALING_FORMAT: + case AV8100_COMMAND_COLORSPACECONVERSION: + case AV8100_COMMAND_CEC_MESSAGE_WRITE: + case AV8100_COMMAND_DENC: + case AV8100_COMMAND_HDMI: + case AV8100_COMMAND_HDCP_SENDKEY: + case AV8100_COMMAND_INFOFRAMES: + case AV8100_COMMAND_PATTERNGENERATOR: + /* Get the second return byte */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1, &val); + if (retval) + goto get_command_return_data_fail; + + if (val) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + break; + + case AV8100_COMMAND_CEC_MESSAGE_READ_BACK: + if ((buffer == NULL) || (buffer_length == NULL)) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + /* Get the return buffer length */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 3, &val); + if (retval) + goto get_command_return_data_fail; + + *buffer_length = val; + + if (*buffer_length > + HDMI_CEC_MESSAGE_READBACK_MAXSIZE) { + printk(KERN_DEBUG "CEC size too large %d\n", + *buffer_length); + *buffer_length = HDMI_CEC_MESSAGE_READBACK_MAXSIZE; + } + +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "return data: "); +#endif + + /* Get the return buffer */ + for (index = 0; index < *buffer_length; ++index) { + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 4 + index, + &val); + if (retval) { + *buffer_length = 0; + goto get_command_return_data_fail; + } else { + *(buffer + index) = val; +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "%02x ", *(buffer + index)); +#endif + } + } +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "\n"); +#endif + break; + + case AV8100_COMMAND_HDCP_MANAGEMENT: + if ((buffer == NULL) || (buffer_length == NULL) || + (command_buffer == NULL)) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + /* Get the second return byte */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1, &val); + if (retval) { + goto get_command_return_data_fail; + } else { + /* Check the second return byte */ + if (val) + goto get_command_return_data_fail; + } + + /* Get the return buffer length */ + if (command_buffer[0] == + HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT) { + *buffer_length = 0x1F; + } else { + *buffer_length = 0x0; + } + +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "return data: "); +#endif + /* Get the return buffer */ + for (index = 0; index < *buffer_length; ++index) { + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 2 + index, + &val); + if (retval) { + *buffer_length = 0; + goto get_command_return_data_fail; + } else { + *(buffer + index) = val; +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "%02x ", *(buffer + index)); +#endif + } + } +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "\n"); +#endif + break; + + case AV8100_COMMAND_EDID_SECTION_READBACK: + if ((buffer == NULL) || (buffer_length == NULL)) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + /* Return buffer length is fixed */ + *buffer_length = 0x80; + +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "return data: "); +#endif + /* Get the return buffer */ + for (index = 0; index < *buffer_length; ++index) { + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1 + index, + &val); + if (retval) { + *buffer_length = 0; + goto get_command_return_data_fail; + } else { + *(buffer + index) = val; +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "%02x ", *(buffer + index)); +#endif + } + } +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "\n"); +#endif + break; + + case AV8100_COMMAND_FUSE_AES_KEY: + if ((buffer == NULL) || (buffer_length == NULL)) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + /* Get the second return byte */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1, &val); + if (retval) + goto get_command_return_data_fail; + + /* Check the second return byte */ + if (val) { + retval = AV8100_FAIL; + goto get_command_return_data_fail; + } + + /* Return buffer length is fixed */ + *buffer_length = 0x2; + + /* Get CRC */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1, &val); + if (retval) + goto get_command_return_data_fail; + + *(buffer + 0) = val; +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "CRC:%02x ", val); +#endif + + /* Get programmed status */ + retval = read_single_byte(i2c, + AV8100_COMMAND_OFFSET + 1, &val); + if (retval) + goto get_command_return_data_fail; + + *(buffer + 1) = val; +#ifdef AV8100_DEBUG_EXTRA + printk(KERN_DEBUG "programmed:%02x ", val); +#endif + break; + + default: + retval = AV8100_INVALID_COMMAND; + break; + } - HDMI_TRACE; - g_av8100_cmd_length = AV8100_COMMAND_INFOFRAMES_SIZE; + return retval; +get_command_return_data_fail: + printk(KERN_DEBUG "get_command_return_data FAIL\n"); return retval; } -/** - * configure_av8100_pattern_generator() - This function will be used to configure the pattern generator. - * @buffer_temp: configuration pointer - * - **/ -static int configure_av8100_pattern_generator(char* buffer_temp) +int av8100_powerup(void) { - int retval = AV8100_OK; + int retval = 0; + struct i2c_client *i2c; + u8 cpd; + u8 stby; + u8 hpds; + u8 cpds; + u8 mclkrng; + u8 off_time; + u8 on_time; + u8 fdl; + u8 hld; + u8 wa; + u8 ra; + + if (!av8100_config) + return AV8100_FAIL; + + i2c = av8100_config->client; + + /* Reset av8100 */ + gpio_set_value(GPIO_AV8100_RSTN, 1); + av8100_set_state(AV8100_OPMODE_STANDBY); + + /* Master clock timing, running, search for plug */ + retval = av8100_register_standby_write(AV8100_STANDBY_CPD_HIGH, + AV8100_STANDBY_STBY_HIGH, AV8100_MASTER_CLOCK_TIMING); + if (retval) { + pr_err("Failed to write the value to av8100 register\n"); + return -EFAULT; + } + + retval = av8100_register_standby_read(&cpd, &stby, &hpds, &cpds, + &mclkrng); + if (retval) { + pr_err("Failed to read the value from av8100 register\n"); + return -EFAULT; + } else { + printk(KERN_DEBUG "STANDBY_REG register cpd:%d stby:%d " + "hpds:%d cpds:%d mclkrng:%0x\n", cpd, stby, hpds, + cpds, mclkrng); + } + + /* ON time & OFF time on 5v HDMI plug detect */ + retval = av8100_register_hdmi_5_volt_time_write(AV8100_OFF_TIME, + AV8100_ON_TIME); + if (retval) { + pr_err("Failed to write the value to av8100 register\n"); + return -EFAULT; + } + + retval = av8100_register_hdmi_5_volt_time_read(&off_time, &on_time); + if (retval) { + pr_err("Failed to read the value from av8100 register\n"); + return -EFAULT; + } else { + printk(KERN_DEBUG "AV8100_5_VOLT_TIME_REG register " + "off_time:%0x on_time:%0x\n", off_time, on_time); + } + + /* Device in hold mode, enable firmware download*/ + retval = av8100_register_general_control_write( + AV8100_GENERAL_CONTROL_FDL_HIGH, + AV8100_GENERAL_CONTROL_HLD_HIGH, + AV8100_GENERAL_CONTROL_WA_LOW, + AV8100_GENERAL_CONTROL_RA_LOW); + if (retval) { + pr_err("Failed to write the value to av8100 register\n"); + return -EFAULT; + } - HDMI_TRACE; - buffer_temp[0] = hdmi_pattern_generator_cmd.pattern_type; - buffer_temp[1] = hdmi_pattern_generator_cmd.pattern_video_format; - buffer_temp[2] = hdmi_pattern_generator_cmd.pattern_audio_mode; + retval = av8100_register_general_control_read(&fdl, &hld, &wa, &ra); + if (retval) { + pr_err("Failed to read the value from av8100 register\n"); + return -EFAULT; + } else { + printk(KERN_DEBUG "GENERAL_CONTROL_REG register fdl:%d " + "hld:%d wa:%d ra:%d\n", fdl, hld, wa, ra); + } - g_av8100_cmd_length = AV8100_COMMAND_PATTERNGENERATOR_SIZE - 1; + av8100_set_state(AV8100_OPMODE_SCAN); return retval; } -/** - * read_edid_info() - This function will be used to EDID info. - * @i2c: i2c client device - * @buff: pointer to EDID buffer - * - **/ -#if 0 -static int read_edid_info(struct i2c_client *i2c, char* buff) +int av8100_powerdown(void) { -int retval = AV8100_OK; -return retval; + gpio_set_value(GPIO_AV8100_RSTN, 0); + av8100_set_state(AV8100_OPMODE_SHUTDOWN); + + return 0; } -#endif -/** - * av8100_download_firmware() - This function will be used to download firmware. - * @i2c: i2c client device - * @fw_buff: pointer to firmware buffer - * @numOfBytes: number of bytes - * - **/ -static int av8100_download_firmware(struct i2c_client *i2c, char regOffset, char* fw_buff, int numOfBytes, enum interface if_type) +int av8100_download_firmware(char *fw_buff, int nbytes, + enum interface_type if_type) { - int retval = AV8100_OK; + int retval = 0; int temp = 0x0; - int increment = 15, index = 0; - int size = 0x0, tempnext = 0x0; - char val = 0x0 ; + int increment = 15; + int index = 0; + int size = 0x0; + int tempnext = 0x0; + char val = 0x0; char CheckSum = 0; int cnt = 10; + struct i2c_client *i2c; + u8 cecrec; + u8 cectrx; + u8 uc; + u8 onuvb; + u8 hdcps; + + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_download_firmware_out; + } - temp = numOfBytes % increment; - for(size=0;size<(numOfBytes-temp);size=size+increment, index+=increment) - { - if(if_type == I2C_INTERFACE) { - retval = av8100_write_multi_byte(i2c, regOffset, fw_buff + size, increment); - if(retval != AV8100_OK) { - printk("Failed to download the av8100 firmware\n"); - return -EFAULT; - } - } - else if(if_type == DSI_INTERFACE) { - retval = dsiLPdcslongwrite(0, 0x10, DCS_FW_DOWNLOAD,fw_buff[index],fw_buff[index + 1],fw_buff[index + 2], - fw_buff[index + 3],fw_buff[index + 4],fw_buff[index + 5],fw_buff[index + 6],fw_buff[index + 7], fw_buff[index + 8], - fw_buff[index + 9],fw_buff[index + 10],fw_buff[index + 11],fw_buff[index + 12],fw_buff[index + 13], fw_buff[index + 14], - CHANNEL_A, DSI_LINK2); - if(retval != AV8100_OK) { - printk("Failed to send the data through dsi interface\n"); - return retval; + if (fw_buff == NULL) { + /* use default fw buffer */ + fw_buff = av8100_fw_buff; + nbytes = AV8100_FW_SIZE; + } + + i2c = av8100_config->client; + + LOCK_AV8100_HW; + + temp = nbytes % increment; + for (size = 0; size < (nbytes-temp); size = size + increment, + index += increment) { + if (if_type == I2C_INTERFACE) { + retval = write_multi_byte(i2c, + AV8100_FIRMWARE_DOWNLOAD_ENTRY, fw_buff + size, + increment); + if (retval) { + printk(KERN_DEBUG "Failed to download the " + "av8100 firmware\n"); + retval = -EFAULT; + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; } + } else if (if_type == DSI_INTERFACE) { + printk(KERN_DEBUG "DSI_INTERFACE is currently not supported\n"); + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; + } else { + retval = AV8100_INVALID_INTERFACE; + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; } - else - return AV8100_INVALID_INTERFACE; - for(tempnext=size;tempnext<(increment+size);tempnext++) - ReceiveTab[tempnext] = fw_buff[tempnext]; + for (tempnext = size; tempnext < (increment+size); tempnext++) + av8100_receivetab[tempnext] = fw_buff[tempnext]; } - // Transfer last firmware bytes - if(if_type == I2C_INTERFACE) { - retval = av8100_write_multi_byte(i2c, regOffset, fw_buff + size, temp); - if(retval != AV8100_OK) { - printk("Failed to download the av8100 firmware\n"); - return -EFAULT; - } - } - else if(if_type == DSI_INTERFACE) { - retval = dsiLPdcslongwrite(0, temp+1, DCS_FW_DOWNLOAD,fw_buff[index],fw_buff[index + 1],fw_buff[index + 2], - fw_buff[index + 3],fw_buff[index + 4],fw_buff[index + 5],fw_buff[index + 6],fw_buff[index + 7], fw_buff[index + 8], - fw_buff[index + 9],fw_buff[index + 10],fw_buff[index + 11],fw_buff[index + 12],fw_buff[index + 13], fw_buff[index + 14], - CHANNEL_A, DSI_LINK2); - - if(retval != AV8100_OK) { - printk("Failed to send the data through dsi interface\n"); - return retval; + /* Transfer last firmware bytes */ + if (if_type == I2C_INTERFACE) { + retval = write_multi_byte(i2c, + AV8100_FIRMWARE_DOWNLOAD_ENTRY, fw_buff + size, temp); + if (retval) { + printk(KERN_DEBUG "Failed to download the av8100 firmware\n"); + retval = -EFAULT; + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; } + } else if (if_type == DSI_INTERFACE) { + /* TODO: Add support for DSI firmware download */ + retval = AV8100_INVALID_INTERFACE; + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; + } else { + retval = AV8100_INVALID_INTERFACE; + UNLOCK_AV8100_HW; + goto av8100_download_firmware_out; } - else - return AV8100_INVALID_INTERFACE; - for(tempnext=size;tempnext<(size+temp);tempnext++) { - ReceiveTab[tempnext] = fw_buff[tempnext]; - } + for (tempnext = size; tempnext < (size+temp); tempnext++) + av8100_receivetab[tempnext] = fw_buff[tempnext]; - // check transfer - for(size=0;size<numOfBytes;size++) { + /* check transfer*/ + for (size = 0; size < nbytes; size++) { CheckSum = CheckSum ^ fw_buff[size]; - if(ReceiveTab[size] != fw_buff[size]) { - printk(">Fw download fail....i=%d\n",size); - printk("Transm = %x, Receiv = %x\n",fw_buff[size],ReceiveTab[size]); + if (av8100_receivetab[size] != fw_buff[size]) { + printk(KERN_DEBUG ">Fw download fail....i=%d\n", size); + printk(KERN_DEBUG "Transm = %x, Receiv = %x\n", + fw_buff[size], av8100_receivetab[size]); } } - retval = av8100_read_single_byte(i2c, regOffset, &val); - if(retval != AV8100_OK) { - printk("Failed to read the value in to the av8100 register\n"); - return -EFAULT; + UNLOCK_AV8100_HW; + + retval = av8100_register_firmware_download_entry_read(&val); + if (retval) { + printk(KERN_DEBUG "Failed to read the value from the av8100 register\n"); + retval = -EFAULT; + goto av8100_download_firmware_out; } - printk("CheckSum:%x,val:%x\n",CheckSum,val); + printk(KERN_DEBUG "CheckSum:%x,val:%x\n", CheckSum, val); - if(CheckSum != val) { - printk(">Fw downloading.... FAIL CheckSum issue\n"); - printk("Checksum = %d\n",CheckSum); - printk("Checksum read: %d\n",val); - return AV8100_FWDOWNLOAD_FAIL; + if (CheckSum != val) { + printk(KERN_DEBUG ">Fw downloading.... FAIL CheckSum issue\n"); + printk(KERN_DEBUG "Checksum = %d\n", CheckSum); + printk(KERN_DEBUG "Checksum read: %d\n", val); + retval = AV8100_FWDOWNLOAD_FAIL; + goto av8100_download_firmware_out; + } else { + printk(KERN_DEBUG ">Fw downloading.... success\n"); } - else - printk(">Fw downloading.... success\n"); /* Set to idle mode */ - retval = av8100_write_single_byte(i2c, GENERAL_CONTROL_REG, 0x0); - if(retval != AV8100_OK) { - printk("Failed to write the value in to the av8100 registers\n"); - return -EFAULT; + av8100_register_general_control_write(AV8100_GENERAL_CONTROL_FDL_LOW, + AV8100_GENERAL_CONTROL_HLD_LOW, AV8100_GENERAL_CONTROL_WA_LOW, + AV8100_GENERAL_CONTROL_RA_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to the av8100 registers\n"); + retval = -EFAULT; + goto av8100_download_firmware_out; } /* Wait Internal Micro controler ready */ cnt = 3; - retval = av8100_read_single_byte(i2c, GENERAL_STATUS_REG, &val); - while((retval == AV8100_OK) && (val != AV8100_GENERAL_STATUS_UC_READY) && (cnt-- > 0)) { - printk("av8100 wait2\n"); + retval = av8100_register_general_status_read(&cecrec, &cectrx, &uc, + &onuvb, &hdcps); + while ((retval == 0) && (uc != 0x1) && (cnt-- > 0)) { + printk(KERN_DEBUG "av8100 wait2\n"); /* TODO */ - for(temp=0;temp<0xFFFFF;temp++); + for (temp = 0; temp < 0xFFFFF; temp++) + ; - retval = av8100_read_single_byte(i2c, GENERAL_STATUS_REG, &val); + retval = av8100_register_general_status_read(&cecrec, &cectrx, + &uc, &onuvb, &hdcps); } - if(retval != AV8100_OK) { - printk("Failed to read the value in to the av8100 register\n"); - return -EFAULT; + if (retval) { + printk(KERN_DEBUG "Failed to read the value from the av8100 register\n"); + retval = -EFAULT; + goto av8100_download_firmware_out; } av8100_set_state(AV8100_OPMODE_IDLE); + +av8100_download_firmware_out: return retval; } -/** - * av8100_send_command() - This function will be used to send the command to AV8100. - * @i2cClient: i2c client device - * @command_type: command type - * @if_type: interface type. - * - **/ -static int av8100_send_command (struct i2c_client *i2cClient, char command_type, enum interface if_type) +int av8100_disable_interrupt(void) { - int retval = AV8100_OK, temp = 0, index = 0; - char val = 0x0, val1 = 0x0; - //char val2 = 0x0, val3 = 0x0; - int reg_offset = AV8100_COMMAND_OFFSET + 1; - char buffer[AV8100_COMMAND_MAX_LENGTH]; + int retval; + struct i2c_client *i2c; - g_av8100_cmd_length=0; - memset(buffer, 0x00, AV8100_COMMAND_MAX_LENGTH); - switch(command_type) - { - case AV8100_COMMAND_VIDEO_INPUT_FORMAT: - configure_av8100_video_input(buffer); - break; - case AV8100_COMMAND_AUDIO_INPUT_FORMAT: - configure_av8100_audio_input(buffer); - break; - case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: - configure_av8100_video_output(buffer); - break; - case AV8100_COMMAND_VIDEO_SCALING_FORMAT: - configure_av8100_video_scaling(buffer); - break; - case AV8100_COMMAND_COLORSPACECONVERSION: - configure_av8100_colorspace_conversion(buffer); - break; - case AV8100_COMMAND_CEC_MESSAGEWRITE: - configure_av8100_cec_message_write(buffer); - break; - case AV8100_COMMAND_CEC_MESSAGEREAD_BACK: - configure_av8100_cec_message_read(buffer); - break; - case AV8100_COMMAND_DENC: - configure_av8100_denc(buffer); - break; - case AV8100_COMMAND_HDMI: - configure_av8100_hdmi(buffer); - break; - case AV8100_COMMAND_HDCP_SENDKEY: - configure_av8100_hdcp_senkey(buffer); - break; - case AV8100_COMMAND_HDCP_MANAGEMENT: - configure_av8100_hdcp_management(buffer); - break; - case AV8100_COMMAND_INFOFRAMES: - configure_av8100_infoframe(buffer); - break; - case AV8100_COMMAND_EDID_SECTIONREADBACK: - break; - case AV8100_COMMAND_PATTERNGENERATOR: - configure_av8100_pattern_generator(buffer); - break; - default: - printk(KERN_INFO "Invalid command type\n"); - retval = AV8100_INVALID_COMMAND; + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_disable_interrupt_out; + } + i2c = av8100_config->client; + + retval = av8100_register_standby_pending_interrupt_write( + AV8100_STANDBY_PENDING_INTERRUPT_HPDI_LOW, + AV8100_STANDBY_PENDING_INTERRUPT_CPDI_LOW, + AV8100_STANDBY_PENDING_INTERRUPT_ONI_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_disable_interrupt_out; } -#ifdef HDMI_LOGGING - PRNK_COL(PRNK_COL_YELLOW); - printk(KERN_DEBUG "HDMI send cmd parameters: "); - { int i; - for (i = 0; i < g_av8100_cmd_length; i++) - printk("0x%02x ", buffer[i]); + retval = av8100_register_general_interrupt_mask_write( + AV8100_GENERAL_INTERRUPT_MASK_EOCM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_VSIM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_VSOM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_CECM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_HDCPM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_UOVBM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_TEM_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_disable_interrupt_out; } - printk("\n"); - printk(KERN_DEBUG "HDMI send cmd: 0x%02x\n", command_type); - PRNK_COL(PRNK_COL_WHITE); -#endif /* HDMI_LOGGING */ - if(if_type == I2C_INTERFACE) - { - /* writing the command configuration */ - retval = av8100_write_multi_byte(i2cClient, reg_offset, buffer, g_av8100_cmd_length); - if(retval != AV8100_OK) - return retval; - /* writing the command */ - retval = av8100_write_single_byte(i2cClient, AV8100_COMMAND_OFFSET, command_type); - if(retval != AV8100_OK) - return retval; - mdelay(10); - retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET, &val); - if(retval != AV8100_OK) - return retval; + retval = av8100_register_standby_interrupt_mask_write( + AV8100_STANDBY_INTERRUPT_MASK_HPDM_LOW, + AV8100_STANDBY_INTERRUPT_MASK_CPDM_LOW, + AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_INPUT, + AV8100_STANDBY_INTERRUPT_MASK_IPOL_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_disable_interrupt_out; + } - if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier - return AV8100_COMMAND_FAIL; +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS + del_timer(&av8100_timer); +#endif - retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET+1, &val1); - if(retval != AV8100_OK) - return retval; +av8100_disable_interrupt_out: + return retval; +} - if(val1 != AV8100_OK) // 0x11 - return AV8100_COMMAND_FAIL; +int av8100_enable_interrupt(void) +{ + int retval; + struct i2c_client *i2c; + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_enable_interrupt_out; + } - }else - if(if_type == DSI_INTERFACE) - { - get_dcs_data_index_params(); - for (temp = 0, index = 0; temp < g_dcs_data_count_index; temp++, /*index++*/ index +=15) - { -#if 0 - retval = dsiLPdcslongwrite(0, 0x10, DCS_WRITE_UC,buffer[index],buffer[++index],buffer[++index], - buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index], - buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index], - CHANNEL_A, DSI_LINK2); - - if(retval != AV8100_OK) - { - printk("Failed to send the data through dsi interface\n"); - return retval; - } -#endif - mcde_send_hdmi_cmd_data(&buffer[index],0x10, DCS_WRITE_UC); + i2c = av8100_config->client; - } - if(g_dcs_data_count_last != 0) - { -#if 0 - retval = dsiLPdcslongwrite(0, g_dcs_data_count_last+1, DCS_WRITE_UC,buffer[index],buffer[++index],buffer[++index], - buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index], - buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index], - CHANNEL_A, DSI_LINK2); - if(retval != AV8100_OK) - { - printk("Failed to send the data through dsi interface\n"); - return retval; - } -#endif + retval = av8100_register_standby_pending_interrupt_write( + AV8100_STANDBY_PENDING_INTERRUPT_HPDI_LOW, + AV8100_STANDBY_PENDING_INTERRUPT_CPDI_LOW, + AV8100_STANDBY_PENDING_INTERRUPT_ONI_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_enable_interrupt_out; + } - mcde_send_hdmi_cmd_data(&buffer[index],g_dcs_data_count_last+1, DCS_WRITE_UC); - } -#if 0 - retval = dsiLPdcsshortwrite1parm(0, DCS_EXEC_UC,command_type, CHANNEL_A, DSI_LINK2); - if(retval != AV8100_OK) - { - printk("Failed to send the command through dsi interface\n"); - return retval; - } -#endif -#if 0 - mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC); - dsireaddata(&val, &val1, &val2, &val3, CHANNEL_A, DSI_LINK2); - printk("data read from dsi val:%x, val1:%x\n",val, val1); - if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier - return AV8100_COMMAND_FAIL; - if(val1 != AV8100_OK) // 0x11 - return AV8100_COMMAND_FAIL; - mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC); -#endif -#if 0 - /* writing the command */ - retval = av8100_write_single_byte(i2cClient, AV8100_COMMAND_OFFSET, command_type); - if(retval != AV8100_OK) - return retval; + retval = av8100_register_general_interrupt_mask_write( + AV8100_GENERAL_INTERRUPT_MASK_EOCM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_VSIM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_VSOM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_CECM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_HDCPM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_UOVBM_LOW, + AV8100_GENERAL_INTERRUPT_MASK_TEM_HIGH); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_enable_interrupt_out; + } + + retval = av8100_register_standby_interrupt_mask_write( + AV8100_STANDBY_INTERRUPT_MASK_HPDM_LOW, + AV8100_STANDBY_INTERRUPT_MASK_CPDM_LOW, + AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_INPUT, + AV8100_STANDBY_INTERRUPT_MASK_IPOL_LOW); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; + goto av8100_enable_interrupt_out; + } + +#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS + init_timer(&av8100_timer); + av8100_timer.expires = jiffies + AV8100_TIMER_INTERRUPT_POLLING_TIME; + av8100_timer.function = av8100_timer_int; + av8100_timer.data = 0; + add_timer(&av8100_timer); #endif - mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC); - mdelay(10); - retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET, &val); - if(retval != AV8100_OK) - return retval; - printk("value:%x\n", val); - if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier - return AV8100_COMMAND_FAIL; - retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET+1, &val1); - if(retval != AV8100_OK) - return retval; -printk("value1:%x\n", val1); - if(val1 != AV8100_OK) // 0x11 - return AV8100_COMMAND_FAIL; +av8100_enable_interrupt_out: + return retval; +} -printk("sending command is successful!!!val:%x, val1:%x\n", val, val1); - }else - { - retval = AV8100_INVALID_INTERFACE; - printk(KERN_INFO "Invalid command type\n"); +static int register_write_internal(u8 offset, u8 value) +{ + int retval; + struct i2c_client *i2c; + + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_register_write_out; + } + + i2c = av8100_config->client; + + /* Write to register */ + retval = write_single_byte(i2c, offset, value); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; } + +av8100_register_write_out: return retval; } -/** - * - * av8100_powerdown() - This function will be used to powerdown the AV8100. - * @i2c: i2c client device - * @id: device id - * - **/ -static int av8100_powerdown(void) +int av8100_register_standby_write( + u8 cpd, u8 stby, u8 mclkrng) { - int retval = AV8100_OK; + int retval; + u8 val; - /** reset the av8100 */ - gpio_set_value(GPIO_AV8100_RSTN,GPIO_LOW); + LOCK_AV8100_HW; - av8100_set_state(AV8100_OPMODE_SHUTDOWN); + /* Set register value */ + val = AV8100_STANDBY_CPD(cpd) | AV8100_STANDBY_STBY(stby) | + AV8100_STANDBY_MCLKRNG(mclkrng); + + /* Write to register */ + retval = register_write_internal(AV8100_STANDBY, val); + UNLOCK_AV8100_HW; return retval; } -/** - * - * av8100_powerup() - This function will be used to powerup the AV8100. - * @i2c: i2c client device - * @id: device id - * - **/ -static int av8100_powerup(struct i2c_client *i2c, const struct i2c_device_id *id) +int av8100_register_hdmi_5_volt_time_write(u8 off_time, u8 on_time) { - int retval = AV8100_OK; - char val = 0x0; + int retval; + u8 val; - /* configuration length */ - g_av8100_cmd_length = 6; - /** reset the av8100 */ - gpio_set_value(GPIO_AV8100_RSTN, 1); - av8100_set_state(AV8100_OPMODE_STANDBY); + LOCK_AV8100_HW; - retval = av8100_write_single_byte(i2c, STANDBY_REG, 0x3B); /* Device runing, master clock = 38.4Mhz, Enable searching CVBS cable*/ - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; - } + /* Set register value */ + val = AV8100_HDMI_5_VOLT_TIME_OFF_TIME(off_time) | + AV8100_HDMI_5_VOLT_TIME_ON_TIME(on_time); - retval = av8100_read_single_byte(i2c, STANDBY_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the value in to av8100 register\n"); - return -EFAULT; - }else - printk("STANDBY_REG register value:%0x\n",val); + /* Write to register */ + retval = register_write_internal(AV8100_HDMI_5_VOLT_TIME, val); + UNLOCK_AV8100_HW; + return retval; +} - retval = av8100_write_single_byte(i2c, AV8100_5_VOLT_TIME_REG, 0x20); /* Define ON TIME & OFF time on 5v HDMI plug detect*/ - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; +int av8100_register_standby_interrupt_mask_write( + u8 hpdm, u8 cpdm, u8 stbygpiocfg, u8 ipol) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_STANDBY_INTERRUPT_MASK_HPDM(hpdm) | + AV8100_STANDBY_INTERRUPT_MASK_CPDM(cpdm) | + AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG(stbygpiocfg) | + AV8100_STANDBY_INTERRUPT_MASK_IPOL(ipol); + + /* Write to register */ + retval = register_write_internal(AV8100_STANDBY_INTERRUPT_MASK, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_standby_pending_interrupt_write( + u8 hpdi, u8 cpdi, u8 oni) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_STANDBY_PENDING_INTERRUPT_HPDI(hpdi) | + AV8100_STANDBY_PENDING_INTERRUPT_CPDI(cpdi) | + AV8100_STANDBY_PENDING_INTERRUPT_ONI(oni); + + /* Write to register */ + retval = register_write_internal(AV8100_STANDBY_PENDING_INTERRUPT, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_general_interrupt_mask_write( + u8 eocm, u8 vsim, u8 vsom, u8 cecm, u8 hdcpm, u8 uovbm, u8 tem) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_GENERAL_INTERRUPT_MASK_EOCM(eocm) | + AV8100_GENERAL_INTERRUPT_MASK_VSIM(vsim) | + AV8100_GENERAL_INTERRUPT_MASK_VSOM(vsom) | + AV8100_GENERAL_INTERRUPT_MASK_CECM(cecm) | + AV8100_GENERAL_INTERRUPT_MASK_HDCPM(hdcpm) | + AV8100_GENERAL_INTERRUPT_MASK_UOVBM(uovbm) | + AV8100_GENERAL_INTERRUPT_MASK_TEM(tem); + + /* Write to register */ + retval = register_write_internal(AV8100_GENERAL_INTERRUPT_MASK, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_general_interrupt_write( + u8 eoci, u8 vsii, u8 vsoi, u8 ceci, u8 hdcpi, u8 uovbi) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_GENERAL_INTERRUPT_EOCI(eoci) | + AV8100_GENERAL_INTERRUPT_VSII(vsii) | + AV8100_GENERAL_INTERRUPT_VSOI(vsoi) | + AV8100_GENERAL_INTERRUPT_CECI(ceci) | + AV8100_GENERAL_INTERRUPT_HDCPI(hdcpi) | + AV8100_GENERAL_INTERRUPT_UOVBI(uovbi); + + /* Write to register */ + retval = register_write_internal(AV8100_GENERAL_INTERRUPT, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_gpio_configuration_write( + u8 dat3dir, u8 dat3val, u8 dat2dir, u8 dat2val, u8 dat1dir, + u8 dat1val, u8 ucdbg) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_GPIO_CONFIGURATION_DAT3DIR(dat3dir) | + AV8100_GPIO_CONFIGURATION_DAT3VAL(dat3val) | + AV8100_GPIO_CONFIGURATION_DAT2DIR(dat2dir) | + AV8100_GPIO_CONFIGURATION_DAT2VAL(dat2val) | + AV8100_GPIO_CONFIGURATION_DAT1DIR(dat1dir) | + AV8100_GPIO_CONFIGURATION_DAT1VAL(dat1val) | + AV8100_GPIO_CONFIGURATION_UCDBG(ucdbg); + + /* Write to register */ + retval = register_write_internal(AV8100_GPIO_CONFIGURATION, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_general_control_write( + u8 fdl, u8 hld, u8 wa, u8 ra) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_GENERAL_CONTROL_FDL(fdl) | + AV8100_GENERAL_CONTROL_HLD(hld) | + AV8100_GENERAL_CONTROL_WA(wa) | + AV8100_GENERAL_CONTROL_RA(ra); + + /* Write to register */ + retval = register_write_internal(AV8100_GENERAL_CONTROL, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_firmware_download_entry_write( + u8 mbyte_code_entry) +{ + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Set register value */ + val = AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY( + mbyte_code_entry); + + /* Write to register */ + retval = register_write_internal(AV8100_FIRMWARE_DOWNLOAD_ENTRY, val); + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_register_write( + u8 offset, u8 value) +{ + int retval = 0; + struct i2c_client *i2c; + + LOCK_AV8100_HW; + + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_register_write_out; } - retval = av8100_read_single_byte(i2c, AV8100_5_VOLT_TIME_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the value in to av8100 register\n"); - return -EFAULT; - }else - printk("AV8100_5_VOLT_TIME_REG register value:%0x\n",val); + i2c = av8100_config->client; - retval = av8100_write_single_byte(i2c, GENERAL_CONTROL_REG, 0x30); /* Device in hold mode + enable firmware download*/ - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; + /* Write to register */ + retval = write_single_byte(i2c, offset, value); + if (retval) { + printk(KERN_DEBUG "Failed to write the value to av8100 register\n"); + retval = -EFAULT; } - retval = av8100_read_single_byte(i2c, GENERAL_CONTROL_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the value in to av8100 register\n"); - return -EFAULT; - }else - printk("GENERAL_CONTROL_REG register value:%0x\n",val); - av8100_set_state(AV8100_OPMODE_SCAN); +av8100_register_write_out: + UNLOCK_AV8100_HW; return retval; } -/** - * - * av8100_enable_interrupt() - This function will enable the hdmi/tvout plugin interrupts. - * @i2c: i2c client device - * @id: device id - * - **/ -static int av8100_enable_interrupt(struct i2c_client *i2c) +int register_read_internal(u8 offset, u8 *value) { - int retval = AV8100_OK; -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI || \ - defined CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI|| \ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - char val = 0x0; -#endif + int retval = 0; + struct i2c_client *i2c; -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - val = TE_INTERRUPT; - retval = av8100_write_single_byte(i2c, GENERAL_INTERRUPT_MASK_REG, val); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_register_read_out; } - val = 0x0; - retval = av8100_write_single_byte(i2c, STANDBY_INTERRUPT_MASK_REG, val); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; - } -#endif + i2c = av8100_config->client; -#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI - val = 0x60;//0x60; // tearing & overflow/underflow interrupts - retval = av8100_write_single_byte(i2c, GENERAL_INTERRUPT_MASK_REG, val); - if(retval != AV8100_OK) - { - printk("Failed to write the value in to av8100 register\n"); - return -EFAULT; + /* Read from register */ + retval = read_single_byte(i2c, offset, value); + if (retval) { + printk(KERN_DEBUG "Failed to read the value from av8100 register\n"); + retval = -EFAULT; + goto av8100_register_read_out; } -#endif +av8100_register_read_out: return retval; } -/** - * av8100_open() - This function will be used to open the av8100 device. - * @inode: pointer to inode - * @filp: pointer to file structure - * - **/ -static int av8100_open(struct inode *inode, struct file *filp) +int av8100_register_standby_read( + u8 *cpd, u8 *stby, u8 *hpds, u8 *cpds, u8 *mclkrng) { - int retval = AV8100_OK; - printk("av8100_open is called\n"); + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Read from register */ + retval = register_read_internal(AV8100_STANDBY, &val); + + /* Set return params */ + *cpd = AV8100_STANDBY_CPD_GET(val); + *stby = AV8100_STANDBY_STBY_GET(val); + *hpds = AV8100_STANDBY_HPDS_GET(val); + *cpds = AV8100_STANDBY_CPDS_GET(val); + *mclkrng = AV8100_STANDBY_MCLKRNG_GET(val); + + UNLOCK_AV8100_HW; return retval; } -/** - * av8100_release() - This function will be used to close the av8100 device. - * @inode: pointer to inode - * @filp: pointer to file structure - * - **/ -static int av8100_release(struct inode *inode, struct file *filp) +int av8100_register_hdmi_5_volt_time_read( + u8 *off_time, u8 *on_time) { - int retval = AV8100_OK; - printk("av8100_release is called\n"); + int retval; + u8 val; + + LOCK_AV8100_HW; + + /* Read from register */ + retval = register_read_internal(AV8100_HDMI_5_VOLT_TIME, &val); + + /* Set return params */ + *off_time = AV8100_HDMI_5_VOLT_TIME_OFF_TIME_GET(val); + *on_time = AV8100_HDMI_5_VOLT_TIME_ON_TIME_GET(val); + + UNLOCK_AV8100_HW; return retval; } -/** - * av8100_ioctl - This routine implements av8100 supported ioctls - * @inode: inode pointer. - * @file: file pointer. - * @cmd : ioctl command. - * @arg: input argument for ioctl. - * - * This Api supports the IOC_AV8100_READ_REGISTER,IOC_AV8100_WRITE_REGISTER,IOC_AV8100_SEND_CONFIGURATION_COMMAND - * IOC_AV8100_READ_CONFIGURATION_COMMAND and IOC_AV8100_GET_STATUS ioctl commands. - */ -static int av8100_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - int retval = AV8100_OK; - struct av8100_register internalReg; - struct av8100_command_register commandReg; - struct av8100_status status; - av8100_output_CEA_VESA video_output_format; -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - mcde_video_mode mcde_mode; -#endif - char val = 0x0; - - /** Process actual ioctl */ - switch(cmd) - { - case IOC_AV8100_READ_REGISTER: - if(copy_from_user(&internalReg, (void *)arg, sizeof(struct av8100_register))) { - return -EFAULT; - } +int av8100_register_standby_interrupt_mask_read( + u8 *hpdm, u8 *cpdm, u8 *stbygpiocfg, u8 *ipol) +{ + int retval; + u8 val; - if (internalReg.offset <= FIRMWARE_DOWNLOAD_ENTRY_REG) { - retval = av8100_read_single_byte(av8100Data->client, internalReg.offset, &internalReg.value); + LOCK_AV8100_HW; - if(retval != AV8100_OK) { - printk("Failed to read the value in to the av8100 register\n"); - return -EFAULT; - } - } - else - return AV8100_INVALID_COMMAND; + /* Read from register */ + retval = register_read_internal(AV8100_STANDBY_INTERRUPT_MASK, &val); - if (copy_to_user((void *)arg, (void *)&internalReg, sizeof(struct av8100_register))) { - return -EFAULT; - } - break; + /* Set return params */ + *hpdm = AV8100_STANDBY_INTERRUPT_MASK_HPDM_GET(val); + *cpdm = AV8100_STANDBY_INTERRUPT_MASK_CPDM_GET(val); + *stbygpiocfg = AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_GET(val); + *ipol = AV8100_STANDBY_INTERRUPT_MASK_IPOL_GET(val); - case IOC_AV8100_WRITE_REGISTER: - if(copy_from_user(&internalReg, (void *)arg, sizeof(struct av8100_register))) { - return -EFAULT; - } + UNLOCK_AV8100_HW; + return retval; +} - if (internalReg.offset <= FIRMWARE_DOWNLOAD_ENTRY_REG) { - retval = av8100_write_single_byte(av8100Data->client, internalReg.offset, internalReg.value); - if(retval != AV8100_OK) { - printk("Failed to write the value in to the av8100 register\n"); - return -EFAULT; - } - } - else - return AV8100_INVALID_COMMAND; - //if(copy_to_user((void *)arg, (void *)&internalReg, sizeof(struct av8100_register))) { - // return -EFAULT; - //} - break; - - case IOC_AV8100_SEND_CONFIGURATION_COMMAND: - { - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_OK; - val = 0x0; +int av8100_register_standby_pending_interrupt_read( + u8 *hpdi, u8 *cpdi, u8 *oni, u8 *sid) +{ + int retval; + u8 val; - if(copy_from_user(&commandReg, (void *)arg, sizeof(struct av8100_command_register)) != 0) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 1\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } + LOCK_AV8100_HW; - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - if(commandReg.cmd_id >= AV8100_COMMAND_VIDEO_INPUT_FORMAT && commandReg.cmd_id <= AV8100_COMMAND_PATTERNGENERATOR) { - /* Writing the command buffer */ - retval = av8100_write_multi_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, commandReg.buf, commandReg.buf_len); - if(retval != AV8100_OK) { - printk("Failed to send the command to the av8100\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } - else { - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } + /* Read from register */ + retval = register_read_internal(AV8100_STANDBY_PENDING_INTERRUPT, &val); - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - /* Writing the command */ - retval = av8100_write_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET, commandReg.cmd_id); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 2\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } + /* Set return params */ + *hpdi = AV8100_STANDBY_PENDING_INTERRUPT_HPDI_GET(val); + *cpdi = AV8100_STANDBY_PENDING_INTERRUPT_CPDI_GET(val); + *oni = AV8100_STANDBY_PENDING_INTERRUPT_ONI_GET(val); + *sid = AV8100_STANDBY_PENDING_INTERRUPT_SID_GET(val); - /* TODO */ - mdelay(100); + UNLOCK_AV8100_HW; + return retval; +} - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - /* Getting the first return byte */ - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 3\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - /* Checking the first return byte */ - if(val != (0x80 | commandReg.cmd_id)) { //offset 0x10 == 0x80 | Identifier - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 4 %0x\n", val); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } - } +int av8100_register_general_interrupt_mask_read( + u8 *eocm, + u8 *vsim, + u8 *vsom, + u8 *cecm, + u8 *hdcpm, + u8 *uovbm, + u8 *tem) +{ + int retval; + u8 val; - commandReg.buf_len = 0; - - switch(commandReg.cmd_id) { - case AV8100_COMMAND_VIDEO_INPUT_FORMAT: - case AV8100_COMMAND_AUDIO_INPUT_FORMAT: - case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: - case AV8100_COMMAND_VIDEO_SCALING_FORMAT: - case AV8100_COMMAND_COLORSPACECONVERSION: - case AV8100_COMMAND_CEC_MESSAGEWRITE: - case AV8100_COMMAND_DENC: - case AV8100_COMMAND_HDMI: - case AV8100_COMMAND_HDCP_SENDKEY: - case AV8100_COMMAND_INFOFRAMES: - case AV8100_COMMAND_PATTERNGENERATOR: - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - /* Getting the second return byte */ - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 5\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - /* Checking the second return byte */ - if (val != AV8100_OK) { - printk("Invalid Response for the command %0x\n", val); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } - } - break; + LOCK_AV8100_HW; - case AV8100_COMMAND_CEC_MESSAGEREAD_BACK: - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { + /* Read from register */ + retval = register_read_internal(AV8100_GENERAL_INTERRUPT_MASK, &val); -#if 0 - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6a\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - printk("AV8100_COMMAND_OFFSET + 1:%x\n", val); - } + /* Set return params */ + *eocm = AV8100_GENERAL_INTERRUPT_MASK_EOCM_GET(val); + *vsim = AV8100_GENERAL_INTERRUPT_MASK_VSIM_GET(val); + *vsom = AV8100_GENERAL_INTERRUPT_MASK_VSOM_GET(val); + *cecm = AV8100_GENERAL_INTERRUPT_MASK_CECM_GET(val); + *hdcpm = AV8100_GENERAL_INTERRUPT_MASK_HDCPM_GET(val); + *uovbm = AV8100_GENERAL_INTERRUPT_MASK_UOVBM_GET(val); + *tem = AV8100_GENERAL_INTERRUPT_MASK_TEM_GET(val); - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 2, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6b\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - printk("AV8100_COMMAND_OFFSET + 2:%x\n", val); - } -#endif - /* Getting the buffer length */ - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 3, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - commandReg.buf_len = val; + UNLOCK_AV8100_HW; + return retval; +} - if (commandReg.buf_len > HDMI_CEC_MESSAGE_READBACK_MAXSIZE) { - printk("AV8100_COMMAND_CEC_MESSAGEREAD_BACK buf_len: %d larger than maxsize\n", commandReg.buf_len); - commandReg.buf_len = 16; - } - } - } +int av8100_register_general_interrupt_read( + u8 *eoci, + u8 *vsii, + u8 *vsoi, + u8 *ceci, + u8 *hdcpi, + u8 *uovbi, + u8 *tei) +{ + int retval; + u8 val; - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - int index = 0; - - /* Getting the buffer */ - while ((index < commandReg.buf_len) && (index < HDMI_CEC_MESSAGE_READBACK_MAXSIZE)) { - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 4 + index, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 7\n"); - commandReg.buf_len = 0; - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - break; - } - else { - commandReg.buf[index] = val; - } - - index++; - } - } - break; + LOCK_AV8100_HW; - case AV8100_COMMAND_HDCP_MANAGEMENT: - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { + /* Read from register */ + retval = register_read_internal(AV8100_GENERAL_INTERRUPT, &val); - /* Getting the second return byte */ - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 5\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - else { - /* Checking the second return byte */ - if (val != AV8100_OK) { - printk("Invalid Response for the command\n"); - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - } - } - } + /* Set return params */ + *eoci = AV8100_GENERAL_INTERRUPT_EOCI_GET(val); + *vsii = AV8100_GENERAL_INTERRUPT_VSII_GET(val); + *vsoi = AV8100_GENERAL_INTERRUPT_VSOI_GET(val); + *ceci = AV8100_GENERAL_INTERRUPT_CECI_GET(val); + *hdcpi = AV8100_GENERAL_INTERRUPT_HDCPI_GET(val); + *uovbi = AV8100_GENERAL_INTERRUPT_UOVBI_GET(val); + *tei = AV8100_GENERAL_INTERRUPT_TEI_GET(val); - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - int index = 0; + UNLOCK_AV8100_HW; + return retval; +} - /* Getting the buffer length */ - if(commandReg.buf[0] == HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT) { - commandReg.buf_len = 0x1F; - } - else { - commandReg.buf_len = 0x0; - } +int av8100_register_general_status_read( + u8 *cecrec, + u8 *cectrx, + u8 *uc, + u8 *onuvb, + u8 *hdcps) +{ + int retval; + u8 val; - /* Getting the buffer */ - while (index < commandReg.buf_len) { - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 2 + index, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 8\n"); - commandReg.buf_len = 0; - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - break; - } - else { - commandReg.buf[index] = val; - } - - index++; - } - } - break; - - case AV8100_COMMAND_EDID_SECTIONREADBACK: - if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) { - int index = 0; - - commandReg.buf_len = 0x80; - - /* Getting the buffer */ - while (index < commandReg.buf_len) { - retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1 + index, &val); - if(retval != AV8100_OK) { - printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 9\n"); - commandReg.buf_len = 0; - commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL; - break; - } - else { - commandReg.buf[index] = val; - } - - index++; - } - } - break; - } + LOCK_AV8100_HW; - if(copy_to_user((void *)arg, (void *)&commandReg, sizeof(struct av8100_command_register)) != 0) { - return -EFAULT; - } - } - break; -#if 0 - case IOC_AV8100_READ_CONFIGURATION_COMMAND: - if(copy_from_user(&commandReg, (void *)arg, sizeof(struct av8100_command_register))) { - return -EFAULT; - } + /* Read from register */ + retval = register_read_internal(AV8100_GENERAL_STATUS, &val); - if(copy_to_user((void *)arg, (void *)&commandReg, sizeof(struct av8100_command_register))) { - return -EFAULT; - } - break; -#endif - case IOC_AV8100_GET_STATUS: - { - char val = 0; + /* Set return params */ + *cecrec = AV8100_GENERAL_STATUS_CECREC_GET(val); + *cectrx = AV8100_GENERAL_STATUS_CECTRX_GET(val); + *uc = AV8100_GENERAL_STATUS_UC_GET(val); + *onuvb = AV8100_GENERAL_STATUS_ONUVB_GET(val); + *hdcps = AV8100_GENERAL_STATUS_HDCPS_GET(val); - status.av8100_state = av8100_get_state(); - status.av8100_plugin_status = 0; + UNLOCK_AV8100_HW; + return retval; +} - if(status.av8100_state != AV8100_OPMODE_SHUTDOWN) { - retval = av8100_read_single_byte(av8100Data->client, STANDBY_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the value in to av8100 register\n"); - return -EFAULT; - } +int av8100_register_gpio_configuration_read( + u8 *dat3dir, + u8 *dat3val, + u8 *dat2dir, + u8 *dat2val, + u8 *dat1dir, + u8 *dat1val, + u8 *ucdbg) +{ + int retval; + u8 val; - status.av8100_plugin_status = AV8100_PLUGIN_NONE; - if(val & STANDBY_HPDS_HDMI_PLUGGED) { - status.av8100_plugin_status |= AV8100_HDMI_PLUGIN; - } + LOCK_AV8100_HW; - if(val & STANDBY_CVBS_TV_CABLE_PLUGGED) { - status.av8100_plugin_status |= AV8100_CVBS_PLUGIN; - } - } + /* Read from register */ + retval = register_read_internal(AV8100_GPIO_CONFIGURATION, &val); - printk("av8100_state:%0x av8100_plugin_status:%0x\n", status.av8100_state, status.av8100_plugin_status); + /* Set return params */ + *dat3dir = AV8100_GPIO_CONFIGURATION_DAT3DIR_GET(val); + *dat3val = AV8100_GPIO_CONFIGURATION_DAT3VAL_GET(val); + *dat2dir = AV8100_GPIO_CONFIGURATION_DAT2DIR_GET(val); + *dat2val = AV8100_GPIO_CONFIGURATION_DAT2VAL_GET(val); + *dat1dir = AV8100_GPIO_CONFIGURATION_DAT1DIR_GET(val); + *dat1val = AV8100_GPIO_CONFIGURATION_DAT1VAL_GET(val); + *ucdbg = AV8100_GPIO_CONFIGURATION_UCDBG_GET(val); - if(copy_to_user((void *)arg, (void *)&status, sizeof(struct av8100_status))) { - return -EFAULT; - } - } - break; - - case IOC_AV8100_ENABLE: - /* Use the latest video mode */ -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - mcde_mode = av8100_get_mcde_video_mode(hdmi_video_output_cmd.video_output_cea_vesa); - mcde_hdmi_display_init_command_mode(mcde_mode); -#endif + UNLOCK_AV8100_HW; + return retval; +} - retval = av8100_powerup(av8100Data->client, 0); - if(retval != AV8100_OK){ - printk("error in av8100_powerup\n"); - break; - } +int av8100_register_general_control_read( + u8 *fdl, + u8 *hld, + u8 *wa, + u8 *ra) +{ + int retval; + u8 val; - g_av8100_state = AV8100_OPMODE_INIT; + LOCK_AV8100_HW; - retval = av8100_download_firmware(av8100Data->client, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE); - if(retval != AV8100_OK){ - printk("error in av8100_download_firmware\n"); - break; - } + /* Read from register */ + retval = register_read_internal(AV8100_GENERAL_CONTROL, &val); + /* Set return params */ + *fdl = AV8100_GENERAL_CONTROL_FDL_GET(val); + *hld = AV8100_GENERAL_CONTROL_HLD_GET(val); + *wa = AV8100_GENERAL_CONTROL_WA_GET(val); + *ra = AV8100_GENERAL_CONTROL_RA_GET(val); - av8100_configure_hdmi(av8100Data->client); - - retval = av8100_enable_interrupt(av8100Data->client); - if(retval != AV8100_OK){ - printk("error in av8100_enable_interrupt\n"); - break; - } + UNLOCK_AV8100_HW; + return retval; +} - av8100_hdmi_on(av8100Data); - break; +int av8100_register_firmware_download_entry_read( + u8 *mbyte_code_entry) +{ + int retval; + u8 val; - case IOC_AV8100_DISABLE: - av8100_hdmi_off(av8100Data); - av8100_powerdown(); - break; + LOCK_AV8100_HW; - case IOC_AV8100_SET_VIDEO_FORMAT: - printk(KERN_INFO "IOC_AV8100_SET_VIDEO_FORMAT\n"); + /* Read from register */ + retval = register_read_internal(AV8100_FIRMWARE_DOWNLOAD_ENTRY, &val); - if(copy_from_user(&video_output_format, (void *)arg, sizeof(av8100_output_CEA_VESA))) { - return -EFAULT; - } + /* Set return params */ + *mbyte_code_entry = + AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY_GET(val); - if (video_output_format < AV8100_VIDEO_OUTPUT_CEA_VESA_MAX) { - /* hdmi_off */ - av8100_hdmi_off(av8100Data); + UNLOCK_AV8100_HW; + return retval; +} - /* powerdown */ - av8100_powerdown(); +int av8100_register_read( + u8 offset, + u8 *value) +{ + int retval = 0; + struct i2c_client *i2c; - /* mcde */ - hdmi_video_output_cmd.video_output_cea_vesa = video_output_format; - av8100_config_output_dep_params(); -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - mcde_mode = av8100_get_mcde_video_mode(video_output_format); - mcde_hdmi_display_init_command_mode(mcde_mode); -#endif + LOCK_AV8100_HW; - /* powerup */ - retval = av8100_powerup(av8100Data->client, 0); - if(retval != AV8100_OK){ - printk("error in av8100_powerup\n"); - break; - } + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_register_read_out; + } - g_av8100_state = AV8100_OPMODE_INIT; + i2c = av8100_config->client; - /* download fw */ - retval = av8100_download_firmware(av8100Data->client, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE); - if(retval != AV8100_OK){ - printk("error in av8100_download_firmware\n"); - break; - } + /* Read from register */ + retval = read_single_byte(i2c, offset, value); + if (retval) { + printk(KERN_DEBUG "Failed to read the value from av8100 register\n"); + retval = -EFAULT; + goto av8100_register_read_out; + } - hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb(video_output_format); - hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4(video_output_format); +av8100_register_read_out: + UNLOCK_AV8100_HW; + return retval; +} - /* configure hdmi */ - av8100_configure_hdmi(av8100Data->client); +int av8100_configuration_get(enum av8100_command_type command_type, + union av8100_configuration *config) +{ + if (!av8100_config || !config) + return AV8100_FAIL; + + /* Put configuration data to the corresponding data struct depending + * on command type */ + switch (command_type) { + case AV8100_COMMAND_VIDEO_INPUT_FORMAT: + memcpy(&config->video_input_format, + &av8100_config->hdmi_video_input_cmd, + sizeof(struct av8100_video_input_format_cmd)); + break; - /* enable int */ - retval = av8100_enable_interrupt(av8100Data->client); - if(retval != AV8100_OK){ - printk("error in av8100_enable_interrupt\n"); - break; - } + case AV8100_COMMAND_AUDIO_INPUT_FORMAT: + memcpy(&config->audio_input_format, + &av8100_config->hdmi_audio_input_cmd, + sizeof(struct av8100_audio_input_format_cmd)); + break; - /* hdmi on */ - av8100_hdmi_on(av8100Data); - } - else { - retval = AV8100_INVALID_COMMAND; - } + case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: + memcpy(&config->video_output_format, + &av8100_config->hdmi_video_output_cmd, + sizeof(struct av8100_video_output_format_cmd)); break; -#if 1 -//Test - case IOC_AV8100_HDMI_ON: - printk(KERN_INFO "IOC_AV8100_HDMI_ON\n"); - av8100_hdmi_on(av8100Data); + case AV8100_COMMAND_VIDEO_SCALING_FORMAT: + memcpy(&config->video_scaling_format, + &av8100_config->hdmi_video_scaling_cmd, + sizeof(struct av8100_video_scaling_format_cmd)); break; - case IOC_AV8100_HDMI_OFF: - printk(KERN_INFO "IOC_AV8100_HDMI_OFF\n"); - av8100_hdmi_off(av8100Data); + case AV8100_COMMAND_COLORSPACECONVERSION: + memcpy(&config->color_space_conversion_format, + &av8100_config->hdmi_color_space_conversion_cmd, + sizeof(struct + av8100_color_space_conversion_format_cmd)); break; -#endif - default: - return AV8100_INVALID_IOCTL; - } - return retval; -} + case AV8100_COMMAND_CEC_MESSAGE_WRITE: + memcpy(&config->cec_message_write_format, + &av8100_config->hdmi_cec_message_write_cmd, + sizeof(struct av8100_cec_message_write_format_cmd)); + break; -static unsigned short av8100_get_te_line_nb(av8100_output_CEA_VESA output_video_format) -{ - unsigned short retval; + case AV8100_COMMAND_CEC_MESSAGE_READ_BACK: + memcpy(&config->cec_message_read_back_format, + &av8100_config->hdmi_cec_message_read_back_cmd, + sizeof(struct av8100_cec_message_read_back_format_cmd)); + break; - switch(output_video_format) { - case AV8100_CEA1_640X480P_59_94HZ: - case AV8100_CEA2_3_720X480P_59_94HZ: - retval = 30; + case AV8100_COMMAND_DENC: + memcpy(&config->denc_format, &av8100_config->hdmi_denc_cmd, + sizeof(struct av8100_denc_format_cmd)); break; - case AV8100_CEA5_1920X1080I_60HZ: - case AV8100_CEA6_7_NTSC_60HZ: - case AV8100_CEA20_1920X1080I_50HZ: - retval = 18; + case AV8100_COMMAND_HDMI: + memcpy(&config->hdmi_format, &av8100_config->hdmi_cmd, + sizeof(struct av8100_hdmi_cmd)); break; - case AV8100_CEA4_1280X720P_60HZ: - retval = 21; + case AV8100_COMMAND_HDCP_SENDKEY: + memcpy(&config->hdcp_send_key_format, + &av8100_config->hdmi_hdcp_send_key_cmd, + sizeof(struct av8100_hdcp_send_key_format_cmd)); break; - case AV8100_CEA17_18_720X576P_50HZ: - retval = 40; + case AV8100_COMMAND_HDCP_MANAGEMENT: + memcpy(&config->hdcp_management_format, + &av8100_config->hdmi_hdcp_management_format_cmd, + sizeof(struct av8100_hdcp_management_format_cmd)); break; - case AV8100_CEA19_1280X720P_50HZ: - retval = 22; + case AV8100_COMMAND_INFOFRAMES: + memcpy(&config->infoframes_format, + &av8100_config->hdmi_infoframes_cmd, + sizeof(struct av8100_infoframes_format_cmd)); break; - case AV8100_CEA21_22_576I_PAL_50HZ: - /* Different values below come from LLD, - * TODO: check if this is really needed - * if not merge with AV8100_CEA6_7_NTSC_60HZ case - */ -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - retval = 18; -#else - retval = 17; -#endif + case AV8100_COMMAND_EDID_SECTION_READBACK: + memcpy(&config->edid_section_readback_format, + &av8100_config->hdmi_edid_section_readback_cmd, + sizeof(struct + av8100_edid_section_readback_format_cmd)); break; - case AV8100_CEA32_1920X1080P_24HZ: - case AV8100_CEA33_1920X1080P_25HZ: - case AV8100_CEA34_1920X1080P_30HZ: - retval = 38; + case AV8100_COMMAND_PATTERNGENERATOR: + memcpy(&config->pattern_generator_format, + &av8100_config->hdmi_pattern_generator_cmd, + sizeof(struct av8100_pattern_generator_format_cmd)); break; - case AV8100_CEA60_1280X720P_24HZ: - case AV8100_CEA62_1280X720P_30HZ: - retval = 21; + case AV8100_COMMAND_FUSE_AES_KEY: + memcpy(&config->fuse_aes_key_format, + &av8100_config->hdmi_fuse_aes_key_cmd, + sizeof(struct av8100_fuse_aes_key_format_cmd)); break; - case AV8100_CEA14_15_480p_60HZ: - case AV8100_VESA14_848X480P_60HZ: - case AV8100_CEA61_1280X720P_25HZ: - case AV8100_CEA16_1920X1080P_60HZ: - case AV8100_CEA31_1920x1080P_50Hz: - case AV8100_CEA29_30_576P_50HZ: - case AV8100_VESA9_800X600P_60_32HZ: - case AV8100_VESA16_1024X768P_60HZ: - case AV8100_VESA22_1280X768P_59_99HZ: - case AV8100_VESA23_1280X768P_59_87HZ: - case AV8100_VESA27_1280X800P_59_91HZ: - case AV8100_VESA28_1280X800P_59_81HZ: - case AV8100_VESA39_1360X768P_60_02HZ: - case AV8100_VESA81_1366X768P_59_79HZ: default: - /* TODO */ - retval = 14; + return AV8100_FAIL; break; } - return retval; + return 0; } -static unsigned short av8100_get_ui_x4(av8100_output_CEA_VESA output_video_format) +int av8100_configuration_prepare(enum av8100_command_type command_type, + union av8100_configuration *config) { - unsigned short retval = 6; + if (!av8100_config || !config) + return AV8100_FAIL; + + /* Put configuration data to the corresponding data struct depending + * on command type */ + switch (command_type) { + case AV8100_COMMAND_VIDEO_INPUT_FORMAT: + memcpy(&av8100_config->hdmi_video_input_cmd, + &config->video_input_format, + sizeof(struct av8100_video_input_format_cmd)); + break; - switch(output_video_format) { - case AV8100_CEA1_640X480P_59_94HZ: - case AV8100_CEA2_3_720X480P_59_94HZ: - case AV8100_CEA4_1280X720P_60HZ: - case AV8100_CEA5_1920X1080I_60HZ: - case AV8100_CEA6_7_NTSC_60HZ: - case AV8100_CEA17_18_720X576P_50HZ: - case AV8100_CEA19_1280X720P_50HZ: - case AV8100_CEA20_1920X1080I_50HZ: - case AV8100_CEA21_22_576I_PAL_50HZ: - case AV8100_CEA32_1920X1080P_24HZ: - case AV8100_CEA33_1920X1080P_25HZ: - case AV8100_CEA34_1920X1080P_30HZ: - case AV8100_CEA60_1280X720P_24HZ: - case AV8100_CEA62_1280X720P_30HZ: - retval = 6; + case AV8100_COMMAND_AUDIO_INPUT_FORMAT: + memcpy(&av8100_config->hdmi_audio_input_cmd, + &config->audio_input_format, + sizeof(struct av8100_audio_input_format_cmd)); break; - case AV8100_CEA14_15_480p_60HZ: - case AV8100_VESA14_848X480P_60HZ: - case AV8100_CEA61_1280X720P_25HZ: - case AV8100_CEA16_1920X1080P_60HZ: - case AV8100_CEA31_1920x1080P_50Hz: - case AV8100_CEA29_30_576P_50HZ: - case AV8100_VESA9_800X600P_60_32HZ: - case AV8100_VESA16_1024X768P_60HZ: - case AV8100_VESA22_1280X768P_59_99HZ: - case AV8100_VESA23_1280X768P_59_87HZ: - case AV8100_VESA27_1280X800P_59_91HZ: - case AV8100_VESA28_1280X800P_59_81HZ: - case AV8100_VESA39_1360X768P_60_02HZ: - case AV8100_VESA81_1366X768P_59_79HZ: - default: - /* TODO */ - retval = 6; + case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: + memcpy(&av8100_config->hdmi_video_output_cmd, + &config->video_output_format, + sizeof(struct av8100_video_output_format_cmd)); + + /* Set params that depend on video output */ + av8100_config_video_output_dep(av8100_config-> + hdmi_video_output_cmd.video_output_cea_vesa); break; - } - return retval; -} + case AV8100_COMMAND_VIDEO_SCALING_FORMAT: + memcpy(&av8100_config->hdmi_video_scaling_cmd, + &config->video_scaling_format, + sizeof(struct av8100_video_scaling_format_cmd)); + break; -static void av8100_init_config_params(void) -{ - memset(&hdmi_video_output_cmd, 0x0, sizeof(av8100_video_output_format_cmd)); + case AV8100_COMMAND_COLORSPACECONVERSION: + memcpy(&av8100_config->hdmi_color_space_conversion_cmd, + &config->color_space_conversion_format, + sizeof(struct + av8100_color_space_conversion_format_cmd)); + break; + case AV8100_COMMAND_CEC_MESSAGE_WRITE: + memcpy(&av8100_config->hdmi_cec_message_write_cmd, + &config->cec_message_write_format, + sizeof(struct av8100_cec_message_write_format_cmd)); + break; - /* SDTV mode settings */ -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV + case AV8100_COMMAND_CEC_MESSAGE_READ_BACK: + memcpy(&av8100_config->hdmi_cec_message_read_back_cmd, + &config->cec_message_read_back_format, + sizeof(struct av8100_cec_message_read_back_format_cmd)); + break; - /* Default output mode */ - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ; -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ; -#elif defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA6_7_NTSC_60HZ; -#endif + case AV8100_COMMAND_DENC: + memcpy(&av8100_config->hdmi_denc_cmd, &config->denc_format, + sizeof(struct av8100_denc_format_cmd)); + break; - hdmi_color_conversion_cmd.c0 = 0xFFDA; - hdmi_color_conversion_cmd.c1 = 0xFFB6; - hdmi_color_conversion_cmd.c2 = 0x0070; - hdmi_color_conversion_cmd.c3 = 0x0042; - hdmi_color_conversion_cmd.c4 = 0x0081; - hdmi_color_conversion_cmd.c5 = 0x0019; - hdmi_color_conversion_cmd.c6 = 0x0070; - hdmi_color_conversion_cmd.c7 = 0xFFA2; - hdmi_color_conversion_cmd.c8 = 0xFFEE; - hdmi_color_conversion_cmd.a_offset = 0x007F; - hdmi_color_conversion_cmd.b_offset = 0x0010; - hdmi_color_conversion_cmd.c_offset = 0x007F; - hdmi_color_conversion_cmd.l_max = 0xEB; - hdmi_color_conversion_cmd.l_min = 0x10; - hdmi_color_conversion_cmd.c_max = 0xF0; - hdmi_color_conversion_cmd.c_min = 0x10; - -#else /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ - - /* Default output mode */ - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA4_1280X720P_60HZ; - - /* HDMI mode settings */ -#ifdef CONFIG_FB_U8500_MCDE_HDMI_640x480P60 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA1_640X480P_59_94HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x480P60 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA2_3_720X480P_59_94HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_1280x720P60 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA4_1280X720P_60HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080I60 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA5_1920X1080I_60HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080I50 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA20_1920X1080I_50HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080P30 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA34_1920X1080P_30HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x576I50 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ; -#endif -#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x480I60 - hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA6_7_NTSC_60HZ; -#endif -#endif /* else of if CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ - av8100_config_output_dep_params(); -} - -static void av8100_config_output_dep_params(void) -{ - memset(&hdmi_cmd, 0x0, sizeof(av8100_hdmi_cmd)); - memset(&hdmi_video_input_cmd, 0x0, sizeof(av8100_video_input_format_cmd)); - memset(&hdmi_pattern_generator_cmd, 0x0, sizeof(av8100_pattern_generator_cmd)); - memset(&hdmi_audio_input_cmd, 0x0, sizeof(av8100_audio_input_format_cmd)); - memset(&hdmi_denc_cmd, 0x0, sizeof(av8100_denc_cmd)); - - hdmi_video_input_cmd.dsi_input_mode = AV8100_HDMI_DSI_COMMAND_MODE; - hdmi_video_input_cmd.total_horizontal_pixel = av8100_all_cea[ - hdmi_video_output_cmd.video_output_cea_vesa].htotale; - hdmi_video_input_cmd.total_horizontal_active_pixel = av8100_all_cea[ - hdmi_video_output_cmd.video_output_cea_vesa].hactive; - hdmi_video_input_cmd.total_vertical_lines = av8100_all_cea[ - hdmi_video_output_cmd.video_output_cea_vesa].vtotale; - hdmi_video_input_cmd.total_vertical_active_lines = av8100_all_cea[ - hdmi_video_output_cmd.video_output_cea_vesa].vactive; - - hdmi_video_input_cmd.nb_data_lane = AV8100_DATA_LANES_USED_2; -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - /* hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_YCBCR422; - */ - hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_RGB565; - hdmi_video_input_cmd.video_mode = AV8100_VIDEO_INTERLACE; - - /* only shared for channel A */ - hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4( - hdmi_video_output_cmd.video_output_cea_vesa); - hdmi_video_input_cmd.TE_config = AV8100_TE_IT_LINE; - hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb( - hdmi_video_output_cmd.video_output_cea_vesa); - - if (hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA21_22_576I_PAL_50HZ - ) { - hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_625; - hdmi_denc_cmd.tv_std = AV8100_TV_STD_PALBDGHI; - } else if ( - hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA6_7_NTSC_60HZ - ) { - hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_525; - hdmi_denc_cmd.tv_std = AV8100_TV_STD_NTSCM; - } else { - printk(KERN_WARNING "AV8100: unsupported video mode, using default\n"); - hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_625; - } - hdmi_denc_cmd.denc = AV8100_DENC_ON; - hdmi_denc_cmd.macrovision = AV8100_MACROVISION_OFF; + case AV8100_COMMAND_HDMI: + memcpy(&av8100_config->hdmi_cmd, &config->hdmi_format, + sizeof(struct av8100_hdmi_cmd)); + break; -#ifdef TEST_PATTERN_TEST - hdmi_denc_cmd.internal_generator = AV8100_INTERNAL_GENERATOR_ON; - hdmi_denc_cmd.chroma = AV8100_CHROMA_CWS_CAPTURE_ON; -#else - hdmi_denc_cmd.internal_generator = AV8100_INTERNAL_GENERATOR_OFF; - hdmi_denc_cmd.chroma = AV8100_CHROMA_CWS_CAPTURE_OFF; -#endif /* CONFIG_AV8100_TEST_PATTERN */ - -#else /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ - - /** Config for command mode **/ -#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI - hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4(hdmi_video_output_cmd.video_output_cea_vesa); - hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb(hdmi_video_output_cmd.video_output_cea_vesa); - // hdmi_video_input_cmd.TE_config = AV8100_TE_DSI_IT; // IT on both I/F (DSI & GPIO) - hdmi_video_input_cmd.TE_config = AV8100_TE_IT_LINE; // IT on both I/F (DSI & GPIO) -#endif + case AV8100_COMMAND_HDCP_SENDKEY: + memcpy(&av8100_config->hdmi_hdcp_send_key_cmd, + &config->hdcp_send_key_format, + sizeof(struct av8100_hdcp_send_key_format_cmd)); + break; -#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI - /** Config for video mode **/ - hdmi_video_input_cmd.dsi_input_mode = AV8100_HDMI_DSI_VIDEO_MODE; - hdmi_video_input_cmd.TE_line_nb = 0; - hdmi_video_input_cmd.TE_config = AV8100_TE_OFF; // No TE IT -#endif + case AV8100_COMMAND_HDCP_MANAGEMENT: + memcpy(&av8100_config->hdmi_hdcp_management_format_cmd, + &config->hdcp_management_format, + sizeof(struct av8100_hdcp_management_format_cmd)); + break; - hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_RGB565; - if (hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA5_1920X1080I_60HZ - || - hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA20_1920X1080I_50HZ - || - hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA21_22_576I_PAL_50HZ - || - hdmi_video_output_cmd.video_output_cea_vesa == - AV8100_CEA6_7_NTSC_60HZ - ) { - hdmi_video_input_cmd.video_mode = AV8100_VIDEO_INTERLACE; - } else { - hdmi_video_input_cmd.video_mode = AV8100_VIDEO_PROGRESSIVE; - } + case AV8100_COMMAND_INFOFRAMES: + memcpy(&av8100_config->hdmi_infoframes_cmd, + &config->infoframes_format, + sizeof(struct av8100_infoframes_format_cmd)); + break; - hdmi_pattern_generator_cmd.pattern_audio_mode = AV8100_PATTERN_AUDIO_OFF; - hdmi_pattern_generator_cmd.pattern_type = AV8100_PATTERN_GENERATOR; + case AV8100_COMMAND_EDID_SECTION_READBACK: + memcpy(&av8100_config->hdmi_edid_section_readback_cmd, + &config->edid_section_readback_format, + sizeof(struct + av8100_edid_section_readback_format_cmd)); + break; - if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA4_1280X720P_60HZ) - hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_720P; - else if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA1_640X480P_59_94HZ) - hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_VGA; - else if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA34_1920X1080P_30HZ) - hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_1080P; - else - hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_720P; + case AV8100_COMMAND_PATTERNGENERATOR: + memcpy(&av8100_config->hdmi_pattern_generator_cmd, + &config->pattern_generator_format, + sizeof(struct av8100_pattern_generator_format_cmd)); + break; - hdmi_denc_cmd.denc = AV8100_DENC_OFF; + case AV8100_COMMAND_FUSE_AES_KEY: + memcpy(&av8100_config->hdmi_fuse_aes_key_cmd, + &config->fuse_aes_key_format, + sizeof(struct av8100_fuse_aes_key_format_cmd)); + break; - /* default audio configurations in i2s mode*/ - hdmi_audio_input_cmd.audio_input_if_format = AV8100_AUDIO_I2SDELAYED_MODE; // mode of the MSP - hdmi_audio_input_cmd.i2s_input_nb = 1; // 0, 1 2 3 4 - hdmi_audio_input_cmd.sample_audio_freq = AV8100_AUDIO_FREQ_48KHZ; - hdmi_audio_input_cmd.audio_word_lg = AV8100_AUDIO_16BITS; - hdmi_audio_input_cmd.audio_format = AV8100_AUDIO_LPCM_MODE; - hdmi_audio_input_cmd.audio_if_mode = AV8100_AUDIO_MASTER; - hdmi_audio_input_cmd.audio_mute = AV8100_AUDIO_MUTE_DISABLE; + default: + return AV8100_FAIL; + break; + } -#endif /* if..else CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */ - // HDMI mode - hdmi_cmd.hdmi_mode = AV8100_HDMI_ON; - hdmi_cmd.hdmi_format = AV8100_HDMI; - return; + return 0; } - -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV -static mcde_video_mode av8100_get_mcde_video_mode(av8100_output_CEA_VESA format) +int av8100_configuration_write(enum av8100_command_type command_type, + u8 *return_buffer_length, + u8 *return_buffer, enum interface_type if_type) { - mcde_video_mode retval = VMODE_1280_720_60_P; + int retval = 0; + u8 cmd_buffer[AV8100_COMMAND_MAX_LENGTH]; + u32 cmd_length = 0; + struct i2c_client *i2c; -#define PRNK_MODE(_m, _n) \ - printk(KERN_DEBUG "AV8100 mapped mode: " #_m " on " #_n "\n"); + if (return_buffer_length) + *return_buffer_length = 0; - switch(format) { - case AV8100_CEA1_640X480P_59_94HZ: - PRNK_MODE(AV8100_CEA1_640X480P_59_94HZ, VMODE_640_480_60_P); - retval = VMODE_640_480_60_P; + if (!av8100_config) + return AV8100_FAIL; + + i2c = av8100_config->client; + + memset(&cmd_buffer, 0x00, AV8100_COMMAND_MAX_LENGTH); + +#ifdef AV8100_DEBUG_EXTRA +#define PRNK_MODE(_m) printk(KERN_DEBUG "cmd: " #_m "\n"); +#else +#define PRNK_MODE(_m) +#endif + + /* Fill the command buffer with configuration data */ + switch (command_type) { + case AV8100_COMMAND_VIDEO_INPUT_FORMAT: + PRNK_MODE(AV8100_COMMAND_VIDEO_INPUT_FORMAT); + configuration_video_input_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA2_3_720X480P_59_94HZ: - PRNK_MODE(AV8100_CEA2_3_720X480P_59_94HZ, VMODE_720_480_60_P); - retval = VMODE_720_480_60_P; + + case AV8100_COMMAND_AUDIO_INPUT_FORMAT: + PRNK_MODE(AV8100_COMMAND_AUDIO_INPUT_FORMAT); + configuration_audio_input_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA5_1920X1080I_60HZ: - PRNK_MODE(AV8100_CEA5_1920X1080I_60HZ, VMODE_1920_1080_60_I); - retval = VMODE_1920_1080_60_I; + + case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT: + PRNK_MODE(AV8100_COMMAND_VIDEO_OUTPUT_FORMAT); + configuration_video_output_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA6_7_NTSC_60HZ: - PRNK_MODE(AV8100_CEA6_7_NTSC_60HZ, VMODE_720_480_60_I); - retval = VMODE_720_480_60_I; + + case AV8100_COMMAND_VIDEO_SCALING_FORMAT: + PRNK_MODE(AV8100_COMMAND_VIDEO_SCALING_FORMAT); + configuration_video_scaling_get(cmd_buffer, + &cmd_length); break; - case AV8100_CEA4_1280X720P_60HZ: - PRNK_MODE(AV8100_CEA4_1280X720P_60HZ, VMODE_1280_720_60_P); - retval = VMODE_1280_720_60_P; + + case AV8100_COMMAND_COLORSPACECONVERSION: + PRNK_MODE(AV8100_COMMAND_COLORSPACECONVERSION); + configuration_colorspace_conversion_get(cmd_buffer, + &cmd_length); break; - case AV8100_CEA17_18_720X576P_50HZ: - PRNK_MODE(AV8100_CEA17_18_720X576P_50HZ, VMODE_720_576_50_P); - retval = VMODE_720_576_50_P; + + case AV8100_COMMAND_CEC_MESSAGE_WRITE: + PRNK_MODE(AV8100_COMMAND_CEC_MESSAGE_WRITE); + configuration_cec_message_write_get(cmd_buffer, + &cmd_length); break; - case AV8100_CEA19_1280X720P_50HZ: - PRNK_MODE(AV8100_CEA19_1280X720P_50HZ, VMODE_1280_720_50_P); - retval = VMODE_1280_720_50_P; + + case AV8100_COMMAND_CEC_MESSAGE_READ_BACK: + PRNK_MODE(AV8100_COMMAND_CEC_MESSAGE_READ_BACK); + configuration_cec_message_read_get(cmd_buffer, + &cmd_length); break; - case AV8100_CEA20_1920X1080I_50HZ: - PRNK_MODE(AV8100_CEA20_1920X1080I_50HZ, VMODE_1920_1080_50_I); - retval = VMODE_1920_1080_50_I; + + case AV8100_COMMAND_DENC: + PRNK_MODE(AV8100_COMMAND_DENC); + configuration_denc_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA21_22_576I_PAL_50HZ: - PRNK_MODE(AV8100_CEA21_22_576I_PAL_50HZ, VMODE_720_576_50_I); - retval = VMODE_720_576_50_I; + + case AV8100_COMMAND_HDMI: + PRNK_MODE(AV8100_COMMAND_HDMI); + configuration_hdmi_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA32_1920X1080P_24HZ: - PRNK_MODE(AV8100_CEA32_1920X1080P_24HZ, VMODE_1920_1080_24_P); - retval = VMODE_1920_1080_24_P; + + case AV8100_COMMAND_HDCP_SENDKEY: + PRNK_MODE(AV8100_COMMAND_HDCP_SENDKEY); + configuration_hdcp_sendkey_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA33_1920X1080P_25HZ: - PRNK_MODE(AV8100_CEA33_1920X1080P_25HZ, VMODE_1920_1080_25_P); - retval = VMODE_1920_1080_25_P; + + case AV8100_COMMAND_HDCP_MANAGEMENT: + PRNK_MODE(AV8100_COMMAND_HDCP_MANAGEMENT); + configuration_hdcp_management_get(cmd_buffer, + &cmd_length); break; - case AV8100_CEA34_1920X1080P_30HZ: - PRNK_MODE(AV8100_CEA34_1920X1080P_30HZ, VMODE_1920_1080_30_P); - retval = VMODE_1920_1080_30_P; + + case AV8100_COMMAND_INFOFRAMES: + PRNK_MODE(AV8100_COMMAND_INFOFRAMES); + configuration_infoframe_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA60_1280X720P_24HZ: - PRNK_MODE(AV8100_CEA60_1280X720P_24HZ, VMODE_1280_720_24_P); - retval = VMODE_1280_720_24_P; + + case AV8100_COMMAND_EDID_SECTION_READBACK: + PRNK_MODE(AV8100_COMMAND_EDID_SECTION_READBACK); + av8100_edid_section_readback_get(cmd_buffer, &cmd_length); break; - case AV8100_CEA62_1280X720P_30HZ: - PRNK_MODE(AV8100_CEA62_1280X720P_30HZ, VMODE_1280_720_30_P); - retval = VMODE_1280_720_30_P; + + case AV8100_COMMAND_PATTERNGENERATOR: + PRNK_MODE(AV8100_COMMAND_PATTERNGENERATOR); + configuration_pattern_generator_get(cmd_buffer, + &cmd_length); + break; + + case AV8100_COMMAND_FUSE_AES_KEY: + PRNK_MODE(AV8100_COMMAND_FUSE_AES_KEY); + configuration_fuse_aes_key_get(cmd_buffer, &cmd_length); break; - case AV8100_VESA9_800X600P_60_32HZ: - case AV8100_CEA14_15_480p_60HZ: - case AV8100_CEA16_1920X1080P_60HZ: - case AV8100_CEA29_30_576P_50HZ: - case AV8100_CEA31_1920x1080P_50Hz: - case AV8100_CEA61_1280X720P_25HZ: - case AV8100_VESA14_848X480P_60HZ: - case AV8100_VESA16_1024X768P_60HZ: - case AV8100_VESA22_1280X768P_59_99HZ: - case AV8100_VESA23_1280X768P_59_87HZ: - case AV8100_VESA27_1280X800P_59_91HZ: - case AV8100_VESA28_1280X800P_59_81HZ: - case AV8100_VESA39_1360X768P_60_02HZ: - case AV8100_VESA81_1366X768P_59_79HZ: default: - /* TODO */ - PRNK_MODE(AV8100_UNKNOWN_OR_TODO_MODE, VMODE_1280_720_60_P); - retval = VMODE_1280_720_60_P; + printk(KERN_INFO "Invalid command type\n"); + retval = AV8100_INVALID_COMMAND; break; } - return retval; -} + LOCK_AV8100_HW; + + if (if_type == I2C_INTERFACE) { +#ifdef AV8100_DEBUG_EXTRA + { + int cnt = 0; + printk(KERN_DEBUG "av8100_configuration_write cmd_type:%02x length:%02x ", + command_type, cmd_length); + printk(KERN_DEBUG "buffer: "); + while (cnt < cmd_length) { + printk(KERN_DEBUG "%02x ", cmd_buffer[cnt]); + cnt++; + } + printk(KERN_DEBUG "\n"); + } #endif -static void av8100_set_state(av8100_operating_mode state) -{ - g_av8100_state = state; -} + /* Write the command buffer */ + retval = write_multi_byte(i2c, + AV8100_COMMAND_OFFSET + 1, cmd_buffer, cmd_length); + if (retval) { + UNLOCK_AV8100_HW; + return retval; + } -static av8100_operating_mode av8100_get_state(void) -{ - return g_av8100_state; -} + /* Write the command */ + retval = write_single_byte(i2c, AV8100_COMMAND_OFFSET, + command_type); + if (retval) { + UNLOCK_AV8100_HW; + return retval; + } + /* TODO */ + mdelay(100); -#ifdef AV8100_USE_KERNEL_THREAD -/** - * av8100_thread() - This function will be used to send the data from 8500(MCDE/VTG) to hdmi chip. - * - **/ -static int av8100_thread(void) + retval = get_command_return_data(i2c, command_type, cmd_buffer, + return_buffer_length, return_buffer); + } else if (if_type == DSI_INTERFACE) { + /* TODO */ + } else { + retval = AV8100_INVALID_INTERFACE; + printk(KERN_INFO "Invalid command type\n"); + } + + if (command_type == AV8100_COMMAND_HDMI) { + g_av8100_status.hdmi_on = ((av8100_config->hdmi_cmd. + hdmi_mode == AV8100_HDMI_ON) && + (av8100_config->hdmi_cmd.hdmi_format == AV8100_HDMI)); + } + + UNLOCK_AV8100_HW; + return retval; +} + +int av8100_configuration_write_raw(enum av8100_command_type command_type, + u8 buffer_length, + u8 *buffer, + u8 *return_buffer_length, + u8 *return_buffer) { - int retval = AV8100_OK; - char val = 0x0; + int retval = 0; + struct i2c_client *i2c; - daemonize("hdmi_feeding_thread"); - allow_signal(SIGKILL); + LOCK_AV8100_HW; - while (1) - { - wait_event_interruptible(av8100_event, (av8100_flag == 1) ); - av8100_flag = 0; + if (return_buffer_length) + *return_buffer_length = 0; - /* STANDBY interrupts */ - retval = av8100_read_single_byte(av8100Data->client, STANDBY_PENDING_INTERRUPT_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the STANDBY_PENDING_INTERRUPT_REG\n"); - return -EFAULT; - } + if (!av8100_config) { + retval = AV8100_FAIL; + goto av8100_configuration_write_raw_out; + } - if (val && HDMI_HOTPLUG_INTERRUPT) { - //printk("HDMI_HOTPLUG_INTERRUPT\n"); + i2c = av8100_config->client; - /* TODO */ - } + /* Write the command buffer */ + retval = write_multi_byte(i2c, + AV8100_COMMAND_OFFSET + 1, buffer, buffer_length); + if (retval) + goto av8100_configuration_write_raw_out; - if (val && CVBS_PLUG_INTERRUPT) { - //printk("CVBS_PLUG_INTERRUPT\n"); + /* Write the command */ + retval = write_single_byte(i2c, AV8100_COMMAND_OFFSET, + command_type); + if (retval) + goto av8100_configuration_write_raw_out; - /* TODO */ - } + /* TODO */ + mdelay(100); - /* Clear interrupts */ - av8100_write_single_byte(av8100Data->client, STANDBY_PENDING_INTERRUPT_REG, STANDBY_INTERRUPT_MASK_ALL); + retval = get_command_return_data(i2c, command_type, buffer, + return_buffer_length, return_buffer); - /* General interrupts */ - retval = av8100_read_single_byte(av8100Data->client, GENERAL_INTERRUPT_REG, &val); - if(retval != AV8100_OK) - { - printk("Failed to read the GENERAL_INTERRUPT_REG\n"); - return -EFAULT; - } +av8100_configuration_write_raw_out: + UNLOCK_AV8100_HW; + return retval; +} - if(val & TE_INTERRUPT) - { - u8500_mcde_tasklet_4(0); +struct av8100_status av8100_status_get(void) +{ + return g_av8100_status; +} + +enum av8100_output_CEA_VESA av8100_video_output_format_get(int xres, + int yres, + int htot, + int vtot, + bool interlaced) +{ + enum av8100_output_CEA_VESA index = 1; + int yres_div = (interlaced == false ? 1 : 2); + + while (index < sizeof(av8100_all_cea)/sizeof(struct av8100_cea)) { + if ((xres == av8100_all_cea[index].hactive) && + (yres == av8100_all_cea[index].vactive * yres_div) && + (htot == av8100_all_cea[index].htotale) && + (vtot == av8100_all_cea[index].vtotale)) { + goto av8100_video_output_format_get_out; } + index++; + } - if(val & UNDER_OVER_FLOW_INTERRUPT) - { - //printk("Received the underflow/overflow interrupt\n"); +av8100_video_output_format_get_out: + /* TODO remove */ + printk(KERN_DEBUG "av8100_video_output_format_get %d %d %d %d %d\n", + xres, yres, htot, vtot, index); + return index; +} - /* TODO */ - } +static int av8100_open(struct inode *inode, struct file *filp) +{ + printk(KERN_DEBUG "av8100_open is called\n"); + return 0; +} - /* Clear interrupts */ - retval = av8100_write_single_byte(av8100Data->client, GENERAL_INTERRUPT_REG, GENERAL_INTERRUPT_MASK_ALL); - } +static int av8100_release(struct inode *inode, struct file *filp) +{ + printk(KERN_DEBUG "av8100_release is called\n"); return 0; } -#endif -/** - * av8100_probe() - This function will be used to powerup and initialize the av8100. - * @i2c: i2c client device - * @id: device id - * - **/ -static int av8100_probe(struct i2c_client *i2cClient, - const struct i2c_device_id *id) +static int av8100_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) { - int ret= 0; -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - mcde_video_mode mcde_mode; -#endif + return 0; +} -#ifndef TEST_PATTERN_TEST +static int __devinit av8100_probe(struct i2c_client *i2cClient, + const struct i2c_device_id *id) +{ + int ret = 0; struct av8100_platform_data *pdata = i2cClient->dev.platform_data; -#endif - //printk(KERN_INFO "av8100 probe\n"); - //printk("av8100 probe\n"); + printk(KERN_DEBUG "%s\n", __func__); - PRNK_COL(PRNK_COL_GREEN); - printk(KERN_DEBUG "av8100_probe\n"); - PRNK_COL(PRNK_COL_WHITE); + g_av8100_status.av8100_state = AV8100_OPMODE_SHUTDOWN; + g_av8100_status.av8100_plugin_status = AV8100_PLUGIN_NONE; + g_av8100_status.hdmi_on = false; - av8100_init_config_params(); - -#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT -#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\ - defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV - mcde_mode = av8100_get_mcde_video_mode(hdmi_video_output_cmd.video_output_cea_vesa); - PRNK_COL(PRNK_COL_GREEN); - printk(KERN_DEBUG "av8100_probe: mcde_hdmi_display_init_command_mode\n"); - PRNK_COL(PRNK_COL_WHITE); - mcde_hdmi_display_init_command_mode(mcde_mode); -#endif -#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ - - /** Register av8100 driver */ - ret = misc_register(&av8100_miscdev); + ret = av8100_config_init(); if (ret) { - printk("registering av8100 driver as misc device fails\n"); - goto av8100_misc_fail; - } - if (!i2c_check_functionality(i2cClient->adapter, I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_READ_WORD_DATA)) { - ret = -ENODEV; - goto err; + pr_info("av8100_config_init failed\n"); + goto err; } - av8100Data = kcalloc(1, sizeof(*av8100Data), GFP_KERNEL); - if(!av8100Data) { - ret = -ENOMEM; + if (!i2c_check_functionality(i2cClient->adapter, + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_READ_WORD_DATA)) { + ret = -ENODEV; + pr_info("av8100 i2c_check_functionality failed\n"); goto err; } - init_waitqueue_head(&av8100_event); - //INIT_WORK(&av8100Data->work, u8500_av8100_wq); - av8100Data->client = i2cClient; - i2c_set_clientdata(i2cClient,av8100Data); - /* Test pattern is local to AV8100 driver so if set no MCDE probe as no interaction with it */ - if(mcde_get_hdmi_flag()) - { - printk("HDMI is included in the menuconfig\n"); - - /** powerup the av8100IC */ - ret = av8100_powerup(i2cClient, id); - if(ret != AV8100_OK){ - printk("error in init the hdmi client\n"); - goto err; - } - g_av8100_state = AV8100_OPMODE_INIT; - - ret = av8100_download_firmware(i2cClient, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE); - if(ret != AV8100_OK){ - printk("error in av8100 firmware download: failed\n"); - goto err; - } - - av8100_configure_hdmi(i2cClient); + init_waitqueue_head(&av8100_event); -#ifndef TEST_PATTERN_TEST -#ifdef AV8100_USE_KERNEL_THREAD - kernel_thread((void*)av8100_thread, NULL, CLONE_FS | CLONE_SIGHAND); -#endif + av8100_config->client = i2cClient; + av8100_config->id = (struct i2c_device_id *) id; + i2c_set_clientdata(i2cClient, av8100_config); - ret = request_irq(pdata->irq, av8100_intr_handler, - IRQF_TRIGGER_RISING, "av8100", av8100Data); - if (ret) { - printk(KERN_ERR "unable to request for the irq %d\n", GPIO_TO_IRQ(192)); - gpio_free(pdata->irq); - goto err; - } - ret = av8100_enable_interrupt(i2cClient); - if(ret != AV8100_OK){ - printk("error in enabling the interrupts\n"); - goto err; - } + kthread_run(av8100_thread, NULL, "hdmi_thread"); - av8100_hdmi_on(av8100Data); -#endif /* TEST_PATTERN_TEST */ + ret = request_irq(pdata->irq, av8100_intr_handler, + IRQF_TRIGGER_RISING, "av8100", av8100_config); + if (ret) { + printk(KERN_ERR "av8100_hw request_irq %d failed %d\n", + pdata->irq, ret); + gpio_free(pdata->irq); + goto err; } + return ret; err: - kfree(i2cClient); -av8100_misc_fail: return ret; } - -/** - * av8100_remove() - This function will be used to unload the av8100 driver. - * @i2c: i2c client device - * - **/ -static int __exit av8100_remove(struct i2c_client *i2cClient) +static int __devexit av8100_remove(struct i2c_client *i2cClient) { - i2c_set_clientdata(i2cClient,NULL); + printk(KERN_DEBUG "%s\n", __func__); + + av8100_config_exit(); + return 0; } -static const struct i2c_device_id av8100_id[] = { - { "av8100", 0 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, av8100); +int av8100_init(void) +{ + int ret; -static struct i2c_driver av8100_driver = { - .driver = { - .name = "av8100", - .owner = THIS_MODULE, - }, - .probe = av8100_probe, - .remove = __exit_p(av8100_remove), - .id_table = av8100_id, -}; + printk(KERN_DEBUG "%s\n", __func__); -static int __init av8100_init(void) -{ - return i2c_add_driver(&av8100_driver); -} + ret = i2c_add_driver(&av8100_driver); + if (ret) { + printk(KERN_DEBUG "av8100 i2c_add_driver failed\n"); + goto av8100_init_err; + } + ret = misc_register(&av8100_miscdev); + if (ret) { + printk(KERN_DEBUG "av8100 misc_register failed\n"); + goto av8100_init_err; + } + + hdmi_init(); + + return ret; + +av8100_init_err: + return ret; +} module_init(av8100_init); -static void __exit av8100_exit(void) + +void av8100_exit(void) { + printk(KERN_DEBUG "%s\n", __func__); + + hdmi_exit(); + + misc_deregister(&av8100_miscdev); i2c_del_driver(&av8100_driver); } - module_exit(av8100_exit); + +MODULE_AUTHOR("Per Persson <per.xb.persson@stericsson.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ST-Ericsson hdmi display driver"); diff --git a/drivers/video/av8100/av8100_fw.h b/drivers/video/av8100/av8100_fw.h new file mode 100755 index 00000000000..5c668476077 --- /dev/null +++ b/drivers/video/av8100/av8100_fw.h @@ -0,0 +1,2065 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +/* AV8100 Firmware version : V4.0 HDCP 1.0 + 3D supported */ +#define AV8100_FW_SIZE 16384 +char av8100_receivetab[AV8100_FW_SIZE]; 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0x10, 0x72, +0x15, 0x20, 0x11, 0x72, 0x10, 0x1e, 0xa8, 0xc2, +0xcc, 0x8b, 0xff, 0xa6, 0x04, 0xae, 0x81, 0x85, +0x01, 0x7b, 0x9a, 0x58, 0x01, 0xc7, 0x0f, 0xa4, +0x58, 0x01, 0xc6, 0x5a, 0x01, 0x4f, 0x72, 0x58, +0x01, 0x5c, 0x72, 0x01, 0x6b, 0x5a, 0x01, 0xd6, +0x58, 0x01, 0xce, 0x18, 0x27, 0x58, 0x01, 0xc1, +0x59, 0x01, 0xc6, 0x9b, 0x01, 0x6b, 0x4f, 0x88, +0x81, 0x84, 0x9a, 0x59, 0x01, 0xc7, 0x0f, 0xa4, +0x59, 0x01, 0xc6, 0x5a, 0x01, 0xd7, 0x59, 0x01, +0x5c, 0x72, 0x59, 0x01, 0xce, 0x01, 0x7b, 0x14, +0x27, 0x01, 0xe1, 0x72, 0x5a, 0x01, 0xd6, 0x97, +0x0f, 0xa4, 0x4a, 0x59, 0x01, 0xc6, 0x9b, 0x88, +}; + diff --git a/drivers/video/av8100/av8100_regs.h b/drivers/video/av8100/av8100_regs.h new file mode 100755 index 00000000000..3660051d9ea --- /dev/null +++ b/drivers/video/av8100/av8100_regs.h @@ -0,0 +1,334 @@ + +#define AV8100_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define AV8100_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define AV8100_STANDBY 0x00000000 +#define AV8100_STANDBY_CPD_SHIFT 0 +#define AV8100_STANDBY_CPD_MASK 0x00000001 +#define AV8100_STANDBY_CPD_HIGH 1 +#define AV8100_STANDBY_CPD_LOW 0 +#define AV8100_STANDBY_CPD(__x) \ + AV8100_VAL2REG(AV8100_STANDBY, CPD, __x) +#define AV8100_STANDBY_CPD_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY, CPD, __x) +#define AV8100_STANDBY_STBY_SHIFT 1 +#define AV8100_STANDBY_STBY_MASK 0x00000002 +#define AV8100_STANDBY_STBY_HIGH 1 +#define AV8100_STANDBY_STBY_LOW 0 +#define AV8100_STANDBY_STBY(__x) \ + AV8100_VAL2REG(AV8100_STANDBY, STBY, __x) +#define AV8100_STANDBY_STBY_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY, STBY, __x) +#define AV8100_STANDBY_HPDS_SHIFT 2 +#define AV8100_STANDBY_HPDS_MASK 0x00000004 +#define AV8100_STANDBY_HPDS(__x) \ + AV8100_VAL2REG(AV8100_STANDBY, HPDS, __x) +#define AV8100_STANDBY_HPDS_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY, HPDS, __x) +#define AV8100_STANDBY_CPDS_SHIFT 3 +#define AV8100_STANDBY_CPDS_MASK 0x00000008 +#define AV8100_STANDBY_CPDS(__x) \ + AV8100_VAL2REG(AV8100_STANDBY, CPDS, __x) +#define AV8100_STANDBY_CPDS_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY, CPDS, __x) +#define AV8100_STANDBY_MCLKRNG_SHIFT 4 +#define AV8100_STANDBY_MCLKRNG_MASK 0x000000F0 +#define AV8100_STANDBY_MCLKRNG(__x) \ + AV8100_VAL2REG(AV8100_STANDBY, MCLKRNG, __x) +#define AV8100_STANDBY_MCLKRNG_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY, MCLKRNG, __x) +#define AV8100_HDMI_5_VOLT_TIME 0x00000001 +#define AV8100_HDMI_5_VOLT_TIME_OFF_TIME_SHIFT 0 +#define AV8100_HDMI_5_VOLT_TIME_OFF_TIME_MASK 0x0000001F +#define AV8100_HDMI_5_VOLT_TIME_OFF_TIME(__x) \ + AV8100_VAL2REG(AV8100_HDMI_5_VOLT_TIME, OFF_TIME, __x) +#define AV8100_HDMI_5_VOLT_TIME_OFF_TIME_GET(__x) \ + AV8100_REG2VAL(AV8100_HDMI_5_VOLT_TIME, OFF_TIME, __x) +#define AV8100_HDMI_5_VOLT_TIME_ON_TIME_SHIFT 5 +#define AV8100_HDMI_5_VOLT_TIME_ON_TIME_MASK 0x000000E0 +#define AV8100_HDMI_5_VOLT_TIME_ON_TIME(__x) \ + AV8100_VAL2REG(AV8100_HDMI_5_VOLT_TIME, ON_TIME, __x) +#define AV8100_HDMI_5_VOLT_TIME_ON_TIME_GET(__x) \ + AV8100_REG2VAL(AV8100_HDMI_5_VOLT_TIME, ON_TIME, __x) +#define AV8100_STANDBY_INTERRUPT_MASK 0x00000002 +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM_SHIFT 0 +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM_MASK 0x00000001 +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM_HIGH 1 +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM_LOW 0 +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_INTERRUPT_MASK, HPDM, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_HPDM_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_INTERRUPT_MASK, HPDM, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM_SHIFT 1 +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM_MASK 0x00000002 +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM_HIGH 1 +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM_LOW 0 +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_INTERRUPT_MASK, CPDM, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_CPDM_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_INTERRUPT_MASK, CPDM, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_SHIFT 2 +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_MASK 0x0000000C +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_INPUT 0x00 +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_ALT 0x01 +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_OUTPUT0 0x02 +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_OUTPUT1 0x03 +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_INTERRUPT_MASK, STBYGPIOCFG, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_INTERRUPT_MASK, STBYGPIOCFG, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL_SHIFT 7 +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL_MASK 0x00000080 +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL_HIGH 1 +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL_LOW 0 +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_INTERRUPT_MASK, IPOL, __x) +#define AV8100_STANDBY_INTERRUPT_MASK_IPOL_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_INTERRUPT_MASK, IPOL, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT 0x00000003 +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI_SHIFT 0 +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI_MASK 0x00000001 +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI_HIGH 1 +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI_LOW 0 +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_PENDING_INTERRUPT, HPDI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_HPDI_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_PENDING_INTERRUPT, HPDI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI_SHIFT 1 +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI_MASK 0x00000002 +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI_HIGH 1 +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI_LOW 0 +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_PENDING_INTERRUPT, CPDI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_CPDI_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_PENDING_INTERRUPT, CPDI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI_SHIFT 2 +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI_MASK 0x00000004 +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI_HIGH 1 +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI_LOW 0 +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_PENDING_INTERRUPT, ONI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_ONI_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_PENDING_INTERRUPT, ONI, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_SID_SHIFT 4 +#define AV8100_STANDBY_PENDING_INTERRUPT_SID_MASK 0x000000F0 +#define AV8100_STANDBY_PENDING_INTERRUPT_SID(__x) \ + AV8100_VAL2REG(AV8100_STANDBY_PENDING_INTERRUPT, SID, __x) +#define AV8100_STANDBY_PENDING_INTERRUPT_SID_GET(__x) \ + AV8100_REG2VAL(AV8100_STANDBY_PENDING_INTERRUPT, SID, __x) +#define AV8100_GENERAL_INTERRUPT_MASK 0x00000004 +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM_SHIFT 0 +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM_MASK 0x00000001 +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, EOCM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_EOCM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, EOCM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM_SHIFT 1 +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM_MASK 0x00000002 +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, VSIM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_VSIM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, VSIM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM_SHIFT 2 +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM_MASK 0x00000004 +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, VSOM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_VSOM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, VSOM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_CECM_SHIFT 3 +#define AV8100_GENERAL_INTERRUPT_MASK_CECM_MASK 0x00000008 +#define AV8100_GENERAL_INTERRUPT_MASK_CECM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_CECM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_CECM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, CECM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_CECM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, CECM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM_SHIFT 4 +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM_MASK 0x00000010 +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, HDCPM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_HDCPM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, HDCPM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM_SHIFT 5 +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM_MASK 0x00000020 +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, UOVBM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_UOVBM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, UOVBM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_TEM_SHIFT 6 +#define AV8100_GENERAL_INTERRUPT_MASK_TEM_MASK 0x00000040 +#define AV8100_GENERAL_INTERRUPT_MASK_TEM_HIGH 1 +#define AV8100_GENERAL_INTERRUPT_MASK_TEM_LOW 0 +#define AV8100_GENERAL_INTERRUPT_MASK_TEM(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT_MASK, TEM, __x) +#define AV8100_GENERAL_INTERRUPT_MASK_TEM_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT_MASK, TEM, __x) +#define AV8100_GENERAL_INTERRUPT 0x00000005 +#define AV8100_GENERAL_INTERRUPT_EOCI_SHIFT 0 +#define AV8100_GENERAL_INTERRUPT_EOCI_MASK 0x00000001 +#define AV8100_GENERAL_INTERRUPT_EOCI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, EOCI, __x) +#define AV8100_GENERAL_INTERRUPT_EOCI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, EOCI, __x) +#define AV8100_GENERAL_INTERRUPT_VSII_SHIFT 1 +#define AV8100_GENERAL_INTERRUPT_VSII_MASK 0x00000002 +#define AV8100_GENERAL_INTERRUPT_VSII(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, VSII, __x) +#define AV8100_GENERAL_INTERRUPT_VSII_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, VSII, __x) +#define AV8100_GENERAL_INTERRUPT_VSOI_SHIFT 2 +#define AV8100_GENERAL_INTERRUPT_VSOI_MASK 0x00000004 +#define AV8100_GENERAL_INTERRUPT_VSOI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, VSOI, __x) +#define AV8100_GENERAL_INTERRUPT_VSOI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, VSOI, __x) +#define AV8100_GENERAL_INTERRUPT_CECI_SHIFT 3 +#define AV8100_GENERAL_INTERRUPT_CECI_MASK 0x00000008 +#define AV8100_GENERAL_INTERRUPT_CECI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, CECI, __x) +#define AV8100_GENERAL_INTERRUPT_CECI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, CECI, __x) +#define AV8100_GENERAL_INTERRUPT_HDCPI_SHIFT 4 +#define AV8100_GENERAL_INTERRUPT_HDCPI_MASK 0x00000010 +#define AV8100_GENERAL_INTERRUPT_HDCPI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, HDCPI, __x) +#define AV8100_GENERAL_INTERRUPT_HDCPI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, HDCPI, __x) +#define AV8100_GENERAL_INTERRUPT_UOVBI_SHIFT 5 +#define AV8100_GENERAL_INTERRUPT_UOVBI_MASK 0x00000020 +#define AV8100_GENERAL_INTERRUPT_UOVBI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, UOVBI, __x) +#define AV8100_GENERAL_INTERRUPT_UOVBI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, UOVBI, __x) +#define AV8100_GENERAL_INTERRUPT_TEI_SHIFT 6 +#define AV8100_GENERAL_INTERRUPT_TEI_MASK 0x00000040 +#define AV8100_GENERAL_INTERRUPT_TEI(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_INTERRUPT, TEI, __x) +#define AV8100_GENERAL_INTERRUPT_TEI_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_INTERRUPT, TEI, __x) +#define AV8100_GENERAL_STATUS 0x00000006 +#define AV8100_GENERAL_STATUS_CECREC_SHIFT 1 +#define AV8100_GENERAL_STATUS_CECREC_MASK 0x00000002 +#define AV8100_GENERAL_STATUS_CECREC(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_STATUS, CECREC, __x) +#define AV8100_GENERAL_STATUS_CECREC_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_STATUS, CECREC, __x) +#define AV8100_GENERAL_STATUS_CECTRX_SHIFT 2 +#define AV8100_GENERAL_STATUS_CECTRX_MASK 0x00000004 +#define AV8100_GENERAL_STATUS_CECTRX(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_STATUS, CECTRX, __x) +#define AV8100_GENERAL_STATUS_CECTRX_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_STATUS, CECTRX, __x) +#define AV8100_GENERAL_STATUS_UC_SHIFT 3 +#define AV8100_GENERAL_STATUS_UC_MASK 0x00000008 +#define AV8100_GENERAL_STATUS_UC(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_STATUS, UC, __x) +#define AV8100_GENERAL_STATUS_UC_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_STATUS, UC, __x) +#define AV8100_GENERAL_STATUS_ONUVB_SHIFT 4 +#define AV8100_GENERAL_STATUS_ONUVB_MASK 0x00000010 +#define AV8100_GENERAL_STATUS_ONUVB(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_STATUS, ONUVB, __x) +#define AV8100_GENERAL_STATUS_ONUVB_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_STATUS, ONUVB, __x) +#define AV8100_GENERAL_STATUS_HDCPS_SHIFT 5 +#define AV8100_GENERAL_STATUS_HDCPS_MASK 0x000000E0 +#define AV8100_GENERAL_STATUS_HDCPS(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_STATUS, HDCPS, __x) +#define AV8100_GENERAL_STATUS_HDCPS_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_STATUS, HDCPS, __x) +#define AV8100_GPIO_CONFIGURATION 0x00000007 +#define AV8100_GPIO_CONFIGURATION_DAT3DIR_SHIFT 0 +#define AV8100_GPIO_CONFIGURATION_DAT3DIR_MASK 0x00000001 +#define AV8100_GPIO_CONFIGURATION_DAT3DIR(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT3DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT3DIR_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT3DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT3VAL_SHIFT 1 +#define AV8100_GPIO_CONFIGURATION_DAT3VAL_MASK 0x00000002 +#define AV8100_GPIO_CONFIGURATION_DAT3VAL(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT3VAL, __x) +#define AV8100_GPIO_CONFIGURATION_DAT3VAL_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT3VAL, __x) +#define AV8100_GPIO_CONFIGURATION_DAT2DIR_SHIFT 2 +#define AV8100_GPIO_CONFIGURATION_DAT2DIR_MASK 0x00000004 +#define AV8100_GPIO_CONFIGURATION_DAT2DIR(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT2DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT2DIR_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT2DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT2VAL_SHIFT 3 +#define AV8100_GPIO_CONFIGURATION_DAT2VAL_MASK 0x00000008 +#define AV8100_GPIO_CONFIGURATION_DAT2VAL(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT2VAL, __x) +#define AV8100_GPIO_CONFIGURATION_DAT2VAL_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT2VAL, __x) +#define AV8100_GPIO_CONFIGURATION_DAT1DIR_SHIFT 4 +#define AV8100_GPIO_CONFIGURATION_DAT1DIR_MASK 0x00000010 +#define AV8100_GPIO_CONFIGURATION_DAT1DIR(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT1DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT1DIR_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT1DIR, __x) +#define AV8100_GPIO_CONFIGURATION_DAT1VAL_SHIFT 5 +#define AV8100_GPIO_CONFIGURATION_DAT1VAL_MASK 0x00000020 +#define AV8100_GPIO_CONFIGURATION_DAT1VAL(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, DAT1VAL, __x) +#define AV8100_GPIO_CONFIGURATION_DAT1VAL_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, DAT1VAL, __x) +#define AV8100_GPIO_CONFIGURATION_UCDBG_SHIFT 6 +#define AV8100_GPIO_CONFIGURATION_UCDBG_MASK 0x00000040 +#define AV8100_GPIO_CONFIGURATION_UCDBG(__x) \ + AV8100_VAL2REG(AV8100_GPIO_CONFIGURATION, UCDBG, __x) +#define AV8100_GPIO_CONFIGURATION_UCDBG_GET(__x) \ + AV8100_REG2VAL(AV8100_GPIO_CONFIGURATION, UCDBG, __x) +#define AV8100_GENERAL_CONTROL 0x00000008 +#define AV8100_GENERAL_CONTROL_FDL_SHIFT 4 +#define AV8100_GENERAL_CONTROL_FDL_MASK 0x00000010 +#define AV8100_GENERAL_CONTROL_FDL_HIGH 1 +#define AV8100_GENERAL_CONTROL_FDL_LOW 0 +#define AV8100_GENERAL_CONTROL_FDL(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_CONTROL, FDL, __x) +#define AV8100_GENERAL_CONTROL_FDL_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_CONTROL, FDL, __x) +#define AV8100_GENERAL_CONTROL_HLD_SHIFT 5 +#define AV8100_GENERAL_CONTROL_HLD_MASK 0x00000020 +#define AV8100_GENERAL_CONTROL_HLD_HIGH 1 +#define AV8100_GENERAL_CONTROL_HLD_LOW 0 +#define AV8100_GENERAL_CONTROL_HLD(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_CONTROL, HLD, __x) +#define AV8100_GENERAL_CONTROL_HLD_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_CONTROL, HLD, __x) +#define AV8100_GENERAL_CONTROL_WA_SHIFT 6 +#define AV8100_GENERAL_CONTROL_WA_MASK 0x00000040 +#define AV8100_GENERAL_CONTROL_WA_HIGH 1 +#define AV8100_GENERAL_CONTROL_WA_LOW 0 +#define AV8100_GENERAL_CONTROL_WA(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_CONTROL, WA, __x) +#define AV8100_GENERAL_CONTROL_WA_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_CONTROL, WA, __x) +#define AV8100_GENERAL_CONTROL_RA_SHIFT 7 +#define AV8100_GENERAL_CONTROL_RA_MASK 0x00000080 +#define AV8100_GENERAL_CONTROL_RA_HIGH 1 +#define AV8100_GENERAL_CONTROL_RA_LOW 0 +#define AV8100_GENERAL_CONTROL_RA(__x) \ + AV8100_VAL2REG(AV8100_GENERAL_CONTROL, RA, __x) +#define AV8100_GENERAL_CONTROL_RA_GET(__x) \ + AV8100_REG2VAL(AV8100_GENERAL_CONTROL, RA, __x) +#define AV8100_FIRMWARE_DOWNLOAD_ENTRY 0x0000000F +#define AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY_SHIFT 0 +#define AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY_MASK 0x000000FF +#define AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY(__x) \ + AV8100_VAL2REG(AV8100_FIRMWARE_DOWNLOAD_ENTRY, MBYTE_CODE_ENTRY, __x) +#define AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY_GET(__x) \ + AV8100_REG2VAL(AV8100_FIRMWARE_DOWNLOAD_ENTRY, MBYTE_CODE_ENTRY, __x) diff --git a/drivers/video/av8100/hdmi.c b/drivers/video/av8100/hdmi.c new file mode 100644 index 00000000000..cb6d1077876 --- /dev/null +++ b/drivers/video/av8100/hdmi.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson HDMI driver + * + * Author: Per Persson <per.xb.persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/miscdevice.h> +#include <linux/fs.h> +#include <linux/ioctl.h> +#include <linux/uaccess.h> +#include <video/hdmi.h> +#include <video/av8100.h> + +static int hdmi_open(struct inode *inode, struct file *filp) +{ + int retval = 0; + return retval; +} + +static int hdmi_release(struct inode *inode, struct file *filp) +{ + int retval = 0; + return retval; +} + +static int hdmi_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + int retval = 0; + int value = 0; + union av8100_configuration config; + struct hdmi_register reg; + struct hdmi_command_register command_reg; + struct av8100_status status; + + switch (cmd) { + case IOC_HDMI_POWER: + /* Get desired power state on or off */ + if (copy_from_user(&value, (void *)arg, sizeof(int))) + return -EINVAL; + + if (value == 0) { + if (av8100_powerdown() != AV8100_OK) { + printk(KERN_ERR "av8100_powerdown FAIL\n"); + return -EINVAL; + } + } else { + if (av8100_powerup() != AV8100_OK) { + printk(KERN_ERR "av8100_powerup FAIL\n"); + return -EINVAL; + } + } + break; + + case IOC_HDMI_ENABLE_INTERRUPTS: + if (av8100_enable_interrupt() != AV8100_OK) { + printk(KERN_ERR "av8100_configuration_get FAIL\n"); + return -EINVAL; + } + break; + + case IOC_HDMI_DOWNLOAD_FW: + if (av8100_download_firmware(NULL, 0, I2C_INTERFACE) != + AV8100_OK) { + printk(KERN_ERR "av8100_configuration_get FAIL\n"); + return -EINVAL; + } + break; + + case IOC_HDMI_ONOFF: + /* Get desired HDMI mode on or off */ + if (copy_from_user(&value, (void *)arg, sizeof(int))) + return -EFAULT; + + if (av8100_configuration_get(AV8100_COMMAND_HDMI, &config) != + AV8100_OK) { + printk(KERN_ERR "av8100_configuration_get FAIL\n"); + return -EINVAL; + } + if (value == 0) + config.hdmi_format.hdmi_mode = AV8100_HDMI_OFF; + else + config.hdmi_format.hdmi_mode = AV8100_HDMI_ON; + + if (av8100_configuration_prepare(AV8100_COMMAND_HDMI, &config) + != AV8100_OK) { + printk(KERN_ERR "av8100_configuration_prepare FAIL\n"); + return -EINVAL; + } + if (av8100_configuration_write(AV8100_COMMAND_HDMI, NULL, NULL, + I2C_INTERFACE) != AV8100_OK) { + printk(KERN_ERR "av8100_configuration_write FAIL\n"); + return -EINVAL; + } + break; + + case IOC_HDMI_REGISTER_WRITE: + if (copy_from_user(®, (void *)arg, + sizeof(struct hdmi_register))) { + return -EINVAL; + } + + if (av8100_register_write(reg.offset, reg.value) != + AV8100_OK) { + printk(KERN_ERR "hdmi_register_write FAIL\n"); + return -EINVAL; + } + break; + + case IOC_HDMI_REGISTER_READ: + if (copy_from_user(®, (void *)arg, + sizeof(struct hdmi_register))) { + return -EINVAL; + } + + if (av8100_register_read(reg.offset, ®.value) != + AV8100_OK) { + printk(KERN_ERR "hdmi_register_write FAIL\n"); + return -EINVAL; + } + + if (copy_to_user((void *)arg, (void *)®, + sizeof(struct hdmi_register))) { + return -EINVAL; + } + break; + + case IOC_HDMI_STATUS_GET: + status = av8100_status_get(); + + if (copy_to_user((void *)arg, (void *)&status, + sizeof(struct av8100_status))) { + return -EINVAL; + } + break; + + case IOC_HDMI_CONFIGURATION_WRITE: + if (copy_from_user(&command_reg, (void *)arg, + sizeof(struct hdmi_command_register)) != 0) { + printk(KERN_ERR "IOC_HDMI_CONFIGURATION_WRITE fail 1\n"); + command_reg.return_status = + HDMI_COMMAND_RETURN_STATUS_FAIL; + } else { + if (av8100_configuration_write_raw(command_reg.cmd_id, + command_reg.buf_len, + command_reg.buf, + &(command_reg.buf_len), + command_reg.buf) != AV8100_OK) { + printk(KERN_ERR "IOC_HDMI_CONFIGURATION_WRITE fail 1\n"); + command_reg.return_status = + HDMI_COMMAND_RETURN_STATUS_FAIL; + } + } + + if (copy_to_user((void *)arg, (void *)&command_reg, + sizeof(struct hdmi_command_register)) != 0) { + return -EINVAL; + } + break; + + default: + break; + } + + return retval; +} + +static const struct file_operations hdmi_fops = { + .owner = THIS_MODULE, + .open = hdmi_open, + .release = hdmi_release, + .ioctl = hdmi_ioctl +}; + +static struct miscdevice hdmi_miscdev = { + HDMI_DRIVER_MINOR_NUMBER, + "hdmi", + &hdmi_fops +}; + +int __init hdmi_init(void) +{ + return misc_register(&hdmi_miscdev); +} + +void hdmi_exit(void) +{ + misc_deregister(&hdmi_miscdev); +} diff --git a/drivers/video/mcde/Kconfig b/drivers/video/mcde/Kconfig index 794411dd1fe..7e04bef7f27 100644 --- a/drivers/video/mcde/Kconfig +++ b/drivers/video/mcde/Kconfig @@ -1,18 +1,37 @@ config FB_MCDE - tristate "MCDE display engine support" + tristate "MCDE support" depends on FB - default y - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help - MCDE display engine offers multiple channel,multiple input, multiple - overlay support for rendering on various types of display panels. + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + ---help--- + This enables support for MCDE based frame buffer driver. -config FB_MCDE_MULTIBUFFER - bool "MCDE multibuffer support" - depends on FB && FB_MCDE - default y - help - Please disable this feature if multibuffer not required. + Please read the file <file:Documentation/fb/mcde.txt> +config MCDE_DISPLAY_GENERIC_DSI + tristate "Generic display driver" + depends on FB_MCDE + +config MCDE_DISPLAY_AV8100 + tristate "AV8100 HDMI/CVBS display driver" + depends on FB_MCDE + select AV8100 + +config MCDE_DISPLAY_AB8500_DENC + tristate "AB8500 CVBS display driver" + depends on FB_MCDE + select AB8500_DENC + +config FB_MCDE_DEBUG + bool "MCDE debug messages" + depends on FB_MCDE + ---help--- + Say Y here if you want the MCDE driver to output debug messages + +config FB_MCDE_VDEBUG + bool "MCDE verbose debug messages" + depends on FB_MCDE_DEBUG + ---help--- + Say Y here if you want the MCDE driver to output more debug messages diff --git a/drivers/video/mcde/Makefile b/drivers/video/mcde/Makefile index 8045876a40a..48566c995d3 100644 --- a/drivers/video/mcde/Makefile +++ b/drivers/video/mcde/Makefile @@ -1,16 +1,14 @@ -# Make file for compiling and loadable module MCDE -obj- := mcde.o # Dummy rule to force built-in.o to be made +mcde-objs := mcde_mod.o mcde_hw.o mcde_dss.o mcde_display.o mcde_bus.o mcde_fb.o +obj-$(CONFIG_FB_MCDE) += mcde.o -obj-$(CONFIG_FB_MCDE) += mcde_hwaccess.o - -obj-$(CONFIG_FB_MCDE) += dsi_hwaccess.o - -obj-$(CONFIG_FB_MCDE) += dsi_link_utils.o - -obj-$(CONFIG_FB_MCDE) += mcde_utils.o - -obj-$(CONFIG_FB_MCDE) += mcde.o - -clean-files := mcde_hwaccess.o dsi_hwaccess.o dsi_link_utils.o mcde_utils.o mcde.o modules.order built-in.o +obj-$(CONFIG_MCDE_DISPLAY_GENERIC_DSI) += display-generic_dsi.o +obj-$(CONFIG_MCDE_DISPLAY_AB8500_DENC) += display-ab8500.o +obj-$(CONFIG_MCDE_DISPLAY_AV8100) += display-av8100.o +ifdef CONFIG_FB_MCDE_DEBUG +EXTRA_CFLAGS += -DDEBUG +endif +ifdef CONFIG_FB_MCDE_VDEBUG +EXTRA_CFLAGS += -DVERBOSE_DEBUG +endif diff --git a/drivers/video/mcde/display-ab8500.c b/drivers/video/mcde/display-ab8500.c new file mode 100644 index 00000000000..c062c0313f0 --- /dev/null +++ b/drivers/video/mcde/display-ab8500.c @@ -0,0 +1,407 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * AB8500 display driver + * + * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/regulator/consumer.h> +#include <video/mcde_display.h> +#include <video/mcde_display-ab8500.h> +#include <mach/ab8500_denc.h> + +#define AB8500_DISP_TRACE dev_dbg(&ddev->dev, "%s\n", __func__) + +static int try_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +static int set_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode); +static int set_power_mode(struct mcde_display_device *ddev, + enum mcde_display_power_mode power_mode); +static int on_first_update(struct mcde_display_device *ddev); +static int display_update(struct mcde_display_device *ddev); + +static int __devinit ab8500_probe(struct mcde_display_device *ddev) +{ + int ret = 0; + struct ab8500_display_platform_data *pdata = ddev->dev.platform_data; + struct ab8500_denc_conf *driver_data; + AB8500_DISP_TRACE; + + if (pdata == NULL) { + dev_err(&ddev->dev, "%s:Platform data missing\n", __func__); + ret = -EINVAL; + goto no_pdata; + } + if (ddev->port->type != MCDE_PORTTYPE_DPI) { + dev_err(&ddev->dev, "%s:Invalid port type %d\n", __func__, + ddev->port->type); + ret = -EINVAL; + goto invalid_port_type; + } + ddev->dev.driver_data = kmalloc(sizeof(struct ab8500_denc_conf), + GFP_KERNEL); + if (!ddev->dev.driver_data) { + dev_err(&ddev->dev, "Failed to allocate driver data\n"); + ret = -ENOMEM; + goto no_driver_data; + } + driver_data = (struct ab8500_denc_conf *) ddev->dev.driver_data; + memset(driver_data, 0, sizeof(struct ab8500_denc_conf)); + + /* initialise the device */ + if (pdata->regulator_id) { + pdata->regulator = regulator_get(&ddev->dev, + pdata->regulator_id); + if (IS_ERR(pdata->regulator)) { + ret = PTR_ERR(pdata->regulator); + dev_warn(&ddev->dev, + "%s:Failed to get regulator '%s'\n", + __func__, pdata->regulator_id); + pdata->regulator = NULL; + goto regulator_get_failed; + } + ret = regulator_enable(pdata->regulator); + if (ret < 0) { + dev_err(&ddev->dev, "%s:Failed to enable regulator\n", + __func__); + goto regu_failed; + } + } else { + /* TODO remove as soon as we use a kernel with support + * for ab8500 supports regulators */ + /* enable tv voltage, no lp mode */ + ab8500_denc_regu_setup(true, false); + } + + ddev->try_video_mode = try_video_mode; + ddev->set_video_mode = set_video_mode; + ddev->set_power_mode = set_power_mode; + ddev->on_first_update = on_first_update; + ddev->update = display_update; + ddev->prepare_for_update = NULL; + +out: + return ret; +regu_failed: +regulator_get_failed: + kfree(ddev->dev.driver_data); +no_driver_data: +invalid_port_type: +no_pdata: + goto out; +} + +static int __devexit ab8500_remove(struct mcde_display_device *ddev) +{ + struct ab8500_display_platform_data *pdata = ddev->dev.platform_data; + AB8500_DISP_TRACE; + + if (pdata->regulator) + regulator_put(pdata->regulator); + + kfree(ddev->dev.driver_data); + ddev->dev.driver_data = NULL; + return 0; +} + +static int ab8500_resume(struct mcde_display_device *ddev) +{ + int res = 0; + struct ab8500_display_platform_data *pdata = ddev->dev.platform_data; + AB8500_DISP_TRACE; + + if (pdata->regulator) { + res = regulator_enable(pdata->regulator); + if (res < 0) { + dev_err(&ddev->dev, "%s:Failed to enable regulator\n", + __func__); + goto regu_failed; + } + } else { + /* TODO remove as soon as we use a kernel with support + * for ab8500 supports regulators */ + /* enable tv voltage, no lp mode */ + ab8500_denc_regu_setup(true, false); + } + + ab8500_denc_power_up(); + ab8500_denc_reset(/* hard = */ true); + + return res; +regu_failed: + return 0; +} + +static int ab8500_suspend(struct mcde_display_device *ddev, pm_message_t state) +{ + int res = 0; + struct ab8500_display_platform_data *pdata = ddev->dev.platform_data; + AB8500_DISP_TRACE; + + if (pdata->regulator) { + res = regulator_disable(pdata->regulator); + if (res != 0) { + dev_err(&ddev->dev, "%s:Failed to disable regulator\n", + __func__); + goto regu_failed; + } + } + ab8500_denc_power_down(); + return res; +regu_failed: + return res; +} + + +static struct mcde_display_driver ab8500_driver = { + .probe = ab8500_probe, + .remove = ab8500_remove, + .suspend = ab8500_suspend, + .resume = ab8500_resume, + .driver = { + .name = "mcde_tv_ab8500", + }, +}; + +static void print_vmode(struct mcde_video_mode *vmode) +{ + pr_debug("resolution: %dx%d\n", vmode->xres, vmode->yres); + pr_debug(" pixclock: %d\n", vmode->pixclock); + pr_debug(" hbp: %d\n", vmode->hbp); + pr_debug(" hfp: %d\n", vmode->hfp); + pr_debug(" vbp1: %d\n", vmode->vbp1); + pr_debug(" vfp1: %d\n", vmode->vfp1); + pr_debug(" vbp2: %d\n", vmode->vbp2); + pr_debug(" vfp2: %d\n", vmode->vfp2); + pr_debug("interlaced: %s\n", vmode->interlaced ? "true" : "false"); +} + +static int try_video_mode( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode) +{ + int res = -EINVAL; + AB8500_DISP_TRACE; + + if (ddev == NULL || video_mode == NULL) { + dev_warn(&ddev->dev, "%s:ddev = NULL or video_mode = NULL\n", + __func__); + return res; + } + + /* TODO: move this part to MCDE: mcde_dss_try_video_mode? */ + if (video_mode->xres == 720) { + /* check for PAL */ + if (video_mode->yres == 576) { + /* set including SAV/EAV: */ + video_mode->hbp = 132; + video_mode->hfp = 12; + /* + * Total nr of active lines: 576 + * Total nr of blanking lines: 49 + */ + video_mode->vbp1 = 22; + video_mode->vfp1 = 2; + video_mode->vbp2 = 23; + video_mode->vfp2 = 2; + /* currently only support interlaced */ + video_mode->interlaced = true; + video_mode->pixclock = 37037; + res = 0; + } else if (video_mode->yres == 480) { + /* set including SAV/EAV */ + video_mode->hbp = 122; + video_mode->hfp = 16; + /* + * Total nr of active lines: 486. + * Total nr of blanking lines: 39. + */ + /* Why does the following work? As far as I know the + * total nr of vertical blanking lines between the + * fields equals to 19 or 20, of which 3 are vfp. + */ + video_mode->vbp1 = 19; + video_mode->vfp1 = 3; + video_mode->vbp2 = 20; + video_mode->vfp2 = 3; + /* currently only support interlaced */ + video_mode->interlaced = true; + video_mode->pixclock = 37037; + res = 0; + } + } + + if (res == 0) + print_vmode(video_mode); + else + dev_warn(&ddev->dev, + "%s:Failed to find video mode x=%d, y=%d\n", + __func__, video_mode->xres, video_mode->yres); + + return res; + +} + +static int set_video_mode( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode) +{ + int res = -EINVAL; + struct ab8500_denc_conf *driver_data = (struct ab8500_denc_conf *) + ddev->dev.driver_data; + AB8500_DISP_TRACE; + + if (ddev == NULL || video_mode == NULL) { + dev_warn(&ddev->dev, "%s:ddev = NULL or video_mode = NULL\n", + __func__); + goto out; + } + ddev->video_mode = *video_mode; + if (video_mode->xres == 720) { + /* check for PAL BDGHI and N */ + if (video_mode->yres == 576) { + driver_data->TV_std = TV_STD_PAL_BDGHI; + /* TODO: how to choose LOW DEF FILTER */ + driver_data->cr_filter = TV_CR_PAL_HIGH_DEF_FILTER; + /* TODO: PAL N (e.g. uses a setup of 7.5 IRE) */ + driver_data->black_level_setup = false; + res = 0; + } else if (video_mode->yres == 480) { /* NTSC, PAL M */ + /* TODO: PAL M */ + driver_data->TV_std = TV_STD_NTSC_M; + /* TODO: how to choose LOW DEF FILTER */ + driver_data->cr_filter = TV_CR_NTSC_HIGH_DEF_FILTER; + driver_data->black_level_setup = true; + res = 0; + } + } + if (res < 0) { + dev_warn(&ddev->dev, "%s:Failed to set video mode x=%d, y=%d\n", + __func__, video_mode->xres, video_mode->yres); + goto error; + } + + driver_data->progressive = !video_mode->interlaced; + driver_data->act_output = true; + driver_data->test_pattern = false; + driver_data->partial_blanking = true; + driver_data->blank_all = false; + driver_data->suppress_col = false; + driver_data->phase_reset_mode = TV_PHASE_RST_MOD_DISABLE; + driver_data->dac_enable = false; + driver_data->act_dc_output = true; + + set_power_mode(ddev, MCDE_DISPLAY_PM_STANDBY); + res = mcde_chnl_set_video_mode(ddev->chnl_state, &ddev->video_mode); + if (res < 0) { + dev_warn(&ddev->dev, "%s:Failed to set video mode on channel\n", + __func__); + + goto error; + } + ddev->update_flags |= UPDATE_FLAG_VIDEO_MODE; + return res; +out: +error: + return res; +} + +static int set_power_mode(struct mcde_display_device *ddev, + enum mcde_display_power_mode power_mode) +{ + int ret = 0; + AB8500_DISP_TRACE; + + /* OFF -> STANDBY */ + if (ddev->power_mode == MCDE_DISPLAY_PM_OFF && + power_mode >= MCDE_DISPLAY_PM_OFF) { + dev_vdbg(&ddev->dev, "/* OFF -> STANDBY */\n"); + if (ddev->platform_enable) + ret = ddev->platform_enable(ddev); + ab8500_denc_power_up(); + if (!ret) { + ab8500_denc_reset(/* hard = */ true); + ddev->power_mode = MCDE_DISPLAY_PM_STANDBY; + } + } + /* STANDBY -> ON */ + if (ddev->power_mode == MCDE_DISPLAY_PM_STANDBY && + power_mode == MCDE_DISPLAY_PM_ON) { + dev_vdbg(&ddev->dev, "/* STANDBY -> ON */\n"); + ddev->power_mode = MCDE_DISPLAY_PM_ON; + } + /* ON -> STANDBY */ + if (!ret && ddev->power_mode == MCDE_DISPLAY_PM_ON && + power_mode <= MCDE_DISPLAY_PM_STANDBY) { + dev_vdbg(&ddev->dev, "/* ON -> STANDBY */\n"); + ab8500_denc_reset(/* hard = */ false); + ddev->power_mode = MCDE_DISPLAY_PM_STANDBY; + } + /* STANDBY -> OFF */ + if (!ret && ddev->power_mode == MCDE_DISPLAY_PM_STANDBY && + power_mode == MCDE_DISPLAY_PM_OFF) { + dev_vdbg(&ddev->dev, "/* STANDBY -> OFF */\n"); + if (ddev->platform_disable) + ret = ddev->platform_disable(ddev); + ab8500_denc_power_down(); + if (!ret) + ddev->power_mode = MCDE_DISPLAY_PM_OFF; + } + + return ret; +} + +static int on_first_update(struct mcde_display_device *ddev) +{ + ab8500_denc_conf((struct ab8500_denc_conf *) ddev->dev.driver_data); + ab8500_denc_conf_plug_detect(true, false, TV_PLUG_TIME_2S); + ab8500_denc_mask_int_plug_det(false, false); + ddev->first_update = false; + return 0; +} + +static int display_update(struct mcde_display_device *ddev) +{ + int ret; + if (ddev->first_update) + on_first_update(ddev); + if (ddev->power_mode != MCDE_DISPLAY_PM_ON && ddev->set_power_mode) { + ret = set_power_mode(ddev, MCDE_DISPLAY_PM_ON); + if (ret < 0) + goto error; + } + ret = mcde_chnl_update(ddev->chnl_state, &ddev->update_area); + if (ret < 0) + goto error; +out: + return ret; +error: + dev_warn(&ddev->dev, "%s:Failed to set power mode to on\n", __func__); + goto out; +} + +/* Module init */ +static int __init mcde_display_tvout_ab8500_init(void) +{ + pr_debug("%s\n", __func__); + + return mcde_display_driver_register(&ab8500_driver); +} +late_initcall(mcde_display_tvout_ab8500_init); + +static void __exit mcde_display_tvout_ab8500_exit(void) +{ + pr_debug("%s\n", __func__); + + mcde_display_driver_unregister(&ab8500_driver); +} +module_exit(mcde_display_tvout_ab8500_exit); + +MODULE_AUTHOR("Marcel Tunnissen <marcel.tuennissen@stericsson.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ST-Ericsson MCDE TVout through AB8500 display driver"); diff --git a/drivers/video/mcde/display-av8100.c b/drivers/video/mcde/display-av8100.c new file mode 100755 index 00000000000..1baa0ff7fb6 --- /dev/null +++ b/drivers/video/mcde/display-av8100.c @@ -0,0 +1,593 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson HDMI display driver + * + * Author: Per Persson <per-xb-persson@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <video/mcde_display.h> +#include <video/mcde_display-av8100.h> +#include <video/hdmi.h> +#include <video/av8100.h> + +static int hdmi_try_video_mode( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode); +static int hdmi_set_video_mode( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode); + +struct mcde_video_mode video_modes_supp[] = +{ +/* xres, yres, pixclk, hbp, hfp, vbp, vfp, interlaced */ +#ifndef CONFIG_AV8100_SDTV + /* 640_480_60_P */ + {640, 480, 39682, 112, 48, 33, 12, 0, 0, 0}, + /* 720_480_60_P */ + {720, 480, 37000, 104, 34, 30, 15, 0, 0, 0}, + /* 720_576_50_P */ + {720, 576, 37037, 132, 12, 44, 5, 0, 0, 0}, + /* 1280_720_50_P */ + {1280, 720, 13468, 260, 440, 25, 5, 0, 0, 0}, + /* 1280_720_60_P */ + {1280, 720, 13468, 256, 114, 20, 10, 0, 0, 0}, + /* 1920_1080_24_P */ + {1920, 1080, 13468, 170, 660, 36, 9, 0, 0, 0}, + /* 1920_1080_25_P */ + {1920, 1080, 13468, 192, 528, 36, 9, 0, 0, 0}, + /* 1920_1080_30_P */ + {1920, 1080, 13468, 189, 91, 36, 9, 0, 0, 0}, +#endif /* CONFIG_AV8100_SDTV */ + /* 720_480_60_I) */ + {720, 480, 74000, 126, 12, 44, 1, 0, 0, 1}, + /* 720_576_50_I) */ + {720, 576, 74074, 132, 12, 44, 5, 0, 0, 1}, +#ifndef CONFIG_AV8100_SDTV + /* 1920_1080_50_I) */ + {1920, 1080, 13468, 192, 528, 20, 25, 0, 0, 1}, + /* 1920_1080_60_I) */ + {1920, 1080, 13468, 192, 88, 20, 25, 0, 0, 1}, +#endif /* CONFIG_AV8100_SDTV */ +}; + +static int hdmi_try_video_mode( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode) +{ + int res = -EINVAL; + int index = 0; + int index_crit1 = -1; + int index_crit2 = -1; + int index_crit3 = -1; + int index_crit4 = -1; + + dev_vdbg(&ddev->dev, "%s:\n", __func__); + + if (ddev == NULL || video_mode == NULL) { + dev_warn(&ddev->dev, "%s:ddev = NULL or video_mode = NULL\n", + __func__); + goto hdmi_try_video_mode_out; + } + +#ifdef CONFIG_AV8100_SDTV + video_mode->interlaced = true; +#endif /* CONFIG_AV8100_SDTV */ + + while (index < sizeof(video_modes_supp)/ + sizeof(struct mcde_video_mode)) { + /* 1. Check if all parameters match */ + if (memcmp(video_mode, &video_modes_supp[index], + sizeof(struct mcde_video_mode)) == 0) { + index_crit1 = index; + break; + } + + /* 2. Check if xres,yres,htot,vtot,interlaced match */ + if ((video_mode->xres == video_modes_supp[index].xres) && + (video_mode->yres == video_modes_supp[index].yres) && + ((video_mode->xres + video_mode->hbp + + video_mode->hfp) == + (video_modes_supp[index].xres + + video_modes_supp[index].hbp + + video_modes_supp[index].hfp)) && + ((video_mode->yres + video_mode->vbp1 + + video_mode->vfp1) == + (video_modes_supp[index].yres + + video_modes_supp[index].vbp1 + + video_modes_supp[index].vfp1)) && + (video_mode->interlaced == + video_modes_supp[index].interlaced)) { + video_mode->hbp = video_modes_supp[index].hbp; + video_mode->hfp = video_modes_supp[index].hfp; + video_mode->vbp1 = video_modes_supp[index].vbp1; + video_mode->vfp1 = video_modes_supp[index].vfp1; + video_mode->pixclock = + video_modes_supp[index].pixclock; + + index_crit2 = index; + } + + /* 3. Check if xres,yres,interlaced match,pixelclock */ + if ((video_mode->xres == video_modes_supp[index].xres) && + (video_mode->yres == video_modes_supp[index].yres) && + (video_mode->interlaced == + video_modes_supp[index].interlaced) && + (video_mode->pixclock == + video_modes_supp[index].pixclock)) { + video_mode->hbp = video_modes_supp[index].hbp; + video_mode->hfp = video_modes_supp[index].hfp; + video_mode->vbp1 = video_modes_supp[index].vbp1; + video_mode->vfp1 = video_modes_supp[index].vfp1; + index_crit3 = index; + } + + + /* 4. Check if xres,yres,interlaced match */ + if ((video_mode->xres == video_modes_supp[index].xres) && + (video_mode->yres == video_modes_supp[index].yres) && + (video_mode->interlaced == + video_modes_supp[index].interlaced)) { + video_mode->hbp = video_modes_supp[index].hbp; + video_mode->hfp = video_modes_supp[index].hfp; + video_mode->vbp1 = video_modes_supp[index].vbp1; + video_mode->vfp1 = video_modes_supp[index].vfp1; + video_mode->pixclock = + video_modes_supp[index].pixclock; + index_crit4 = index; + } + + index++; + } + + index = -1; + + if (index_crit1 != -1) + index = index_crit1; + else if (index_crit2 != -1) + index = index_crit2; + else if (index_crit3 != -1) + index = index_crit3; + else if (index_crit4 != -1) + index = index_crit4; + + if (index != -1) { + res = 0; + memset(video_mode, 0, sizeof(struct mcde_video_mode)); + memcpy(video_mode, &video_modes_supp[index], + sizeof(struct mcde_video_mode)); + + dev_dbg(&ddev->dev, "%s:HDMI video_mode %d chosen\n", __func__, + index); + } else { + dev_dbg(&ddev->dev, "video_mode not accepted\n"); + dev_dbg(&ddev->dev, "xres:%d yres:%d pixclock:%d hbp:%d hfp:%d " + "vfp1:%d vfp2:%d vbp1:%d vbp2:%d intlcd:%d\n", + video_mode->xres, video_mode->yres, + video_mode->pixclock, video_mode->hbp, + video_mode->hfp, video_mode->vfp1, video_mode->vfp2, + video_mode->vbp1, video_mode->vbp2, + video_mode->interlaced); + } + +hdmi_try_video_mode_out: + return res; +} + +static int hdmi_set_video_mode( + struct mcde_display_device *dev, struct mcde_video_mode *video_mode) +{ + int ret = -EINVAL; + bool update = 0; + union av8100_configuration av8100_config; + + /* TODO check video_mode_params */ + if (dev == NULL || video_mode == NULL) { + dev_warn(&dev->dev, "%s:ddev = NULL or video_mode = NULL\n", + __func__); + goto out; + } + + dev_vdbg(&dev->dev, "%s:\n", __func__); + dev_vdbg(&dev->dev, "%s:xres:%d yres:%d hbp:%d hfp:%d vbp1:%d vfp1:%d " + "vbp2:%d vfp2:%d interlaced:%d\n", __func__, + video_mode->xres, + video_mode->yres, + video_mode->hbp, + video_mode->hfp, + video_mode->vbp1, + video_mode->vfp1, + video_mode->vbp2, + video_mode->vfp2, + video_mode->interlaced); + + memset(&(dev->video_mode), 0, sizeof(struct mcde_video_mode)); + memcpy(&(dev->video_mode), video_mode, sizeof(struct mcde_video_mode)); + + /* Disable interrupts */ + ret = av8100_disable_interrupt(); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_disable_interrupt failed\n", + __func__); + goto out; + } + + /* TODO: We shouldn't need to shutdown */ + ret = av8100_powerdown(); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "av8100_powerdown failed\n"); + goto out; + } + + ret = av8100_powerup(); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "av8100_powerup failed\n"); + goto out; + } + + ret = av8100_download_firmware(NULL, 0, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "av8100_download_firmware failed\n"); + goto out; + } + + ret = mcde_chnl_set_video_mode(dev->chnl_state, &dev->video_mode); + if (ret < 0) { + dev_warn(&dev->dev, "Failed to set video mode\n"); + goto out; + } + + /* Get current av8100 video output format */ + ret = av8100_configuration_get(AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_get " + "AV8100_COMMAND_VIDEO_OUTPUT_FORMAT failed\n", + __func__); + goto out; + } + + av8100_config.video_output_format.video_output_cea_vesa = +#ifdef CONFIG_AV8100_SDTV + dev->native_y_res == 576 ? AV8100_CEA21_22_576I_PAL_50HZ + : AV8100_CEA6_7_NTSC_60HZ; + /* TODO: check vmode and return error instead? */ +#else + av8100_video_output_format_get( + dev->video_mode.xres, + dev->video_mode.yres, + dev->video_mode.xres + + dev->video_mode.hbp + dev->video_mode.hfp, + dev->video_mode.yres + + dev->video_mode.vbp1 + dev->video_mode.vfp1 + + dev->video_mode.vbp2 + dev->video_mode.vfp2, + dev->video_mode.interlaced); +#endif + if (AV8100_VIDEO_OUTPUT_CEA_VESA_MAX == + av8100_config.video_output_format.video_output_cea_vesa) { + dev_err(&dev->dev, "%s:video output format not found " + "\n", __func__); + goto out; + } + + ret = av8100_configuration_prepare(AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, + "%s:av8100_configuration_prepare " + "AV8100_COMMAND_VIDEO_OUTPUT_FORMAT failed\n", + __func__); + goto out; + } + + /* Get current av8100 video input format */ + ret = av8100_configuration_get(AV8100_COMMAND_VIDEO_INPUT_FORMAT, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_get " + "AV8100_COMMAND_VIDEO_INPUT_FORMAT failed\n", + __func__); + goto out; + } + + /* Set correct av8100 video input pixel format */ + switch (dev->port_pixel_format) { + case MCDE_PORTPIXFMT_DSI_16BPP: + default: + av8100_config.video_input_format.input_pixel_format = + AV8100_INPUT_PIX_RGB565; + break; + case MCDE_PORTPIXFMT_DSI_18BPP: + av8100_config.video_input_format.input_pixel_format = + AV8100_INPUT_PIX_RGB666; + break; + case MCDE_PORTPIXFMT_DSI_18BPP_PACKED: + av8100_config.video_input_format.input_pixel_format = + AV8100_INPUT_PIX_RGB666P; + break; + case MCDE_PORTPIXFMT_DSI_24BPP: + av8100_config.video_input_format.input_pixel_format = + AV8100_INPUT_PIX_RGB888; + break; + case MCDE_PORTPIXFMT_DSI_YCBCR422: + av8100_config.video_input_format.input_pixel_format = + AV8100_INPUT_PIX_YCBCR422; + break; + } + + /* Set ui_x4 */ + av8100_config.video_input_format.ui_x4 = dev->port->phy.dsi.ui; + + ret = av8100_configuration_prepare(AV8100_COMMAND_VIDEO_INPUT_FORMAT, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_prepare " + "AV8100_COMMAND_VIDEO_INPUT_FORMAT failed\n", + __func__); + goto out; + } + + ret = av8100_configuration_write(AV8100_COMMAND_VIDEO_INPUT_FORMAT, + NULL, NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_write " + "AV8100_COMMAND_VIDEO_INPUT_FORMAT failed\n", + __func__); + goto out; + } + +#ifdef CONFIG_AV8100_SDTV + ret = av8100_configuration_write(AV8100_COMMAND_COLORSPACECONVERSION, + NULL, NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_write " + "AV8100_COMMAND_COLORSPACECONVERSION failed\n", + __func__); + goto out; + } +#endif + + /* Set video output format */ + ret = av8100_configuration_write(AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, + NULL, NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "av8100_configuration_write failed\n"); + goto out; + } + + /* Set audio input format */ + ret = av8100_configuration_write(AV8100_COMMAND_AUDIO_INPUT_FORMAT, + NULL, NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_write " + "AV8100_COMMAND_AUDIO_INPUT_FORMAT failed\n", + __func__); + goto out; + } + + /* Get current av8100 video denc settings format */ + ret = av8100_configuration_get(AV8100_COMMAND_DENC, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_get " + "AV8100_COMMAND_DENC failed\n", __func__); + goto out; + } +#ifdef CONFIG_AV8100_SDTV + update = true; + if (dev->video_mode.yres == 576) { + av8100_config.denc_format.standard_selection = AV8100_PAL_BDGHI; + av8100_config.denc_format.cvbs_video_format = AV8100_CVBS_625; + } else { + av8100_config.denc_format.standard_selection = AV8100_NTSC_M; + av8100_config.denc_format.cvbs_video_format = AV8100_CVBS_525; + } +#else + update = (av8100_config.denc_format.on_off != 0); +#endif + + if (update) { +#ifdef CONFIG_AV8100_SDTV + av8100_config.denc_format.on_off = 1; +#else + av8100_config.denc_format.on_off = 0; +#endif + ret = av8100_configuration_prepare(AV8100_COMMAND_DENC, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_prepare " + "AV8100_COMMAND_DENC failed\n", __func__); + goto out; + } + + /* TODO: prepare depending on OUT fmt */ + ret = av8100_configuration_write(AV8100_COMMAND_DENC, + NULL, NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_write " + "AV8100_COMMAND_DENC failed\n", __func__); + goto out; + } + } + + ret = mcde_chnl_set_video_mode(dev->chnl_state, &dev->video_mode); + if (ret < 0) { + dev_warn(&dev->dev, "%s:Failed to set video mode on " + "channel\n", __func__); + goto out; + } + dev->update_flags |= UPDATE_FLAG_VIDEO_MODE; + + return ret; +out: + return ret; +} + +static int hdmi_on_first_update(struct mcde_display_device *dev) +{ + int ret = 0; + union av8100_configuration av8100_config; + + dev->first_update = false; + + /* HDMI on*/ + av8100_config.hdmi_format.hdmi_mode = AV8100_HDMI_ON; + av8100_config.hdmi_format.hdmi_format = AV8100_HDMI; + av8100_config.hdmi_format.dvi_format = AV8100_DVI_CTRL_CTL0; + + ret = av8100_configuration_prepare(AV8100_COMMAND_HDMI, + &av8100_config); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_prepare " + "AV8100_COMMAND_HDMI failed\n", __func__); + goto out; + } + + /* Enable interrupts */ + ret = av8100_enable_interrupt(); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_enable_interrupt failed\n", + __func__); + goto out; + } + + ret = av8100_configuration_write(AV8100_COMMAND_HDMI, NULL, + NULL, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "%s:av8100_configuration_write " + "AV8100_COMMAND_HDMI failed\n", __func__); + goto out; + } + + return ret; +out: + return ret; +} + +static int __devinit hdmi_probe(struct mcde_display_device *dev) +{ + int ret = EINVAL; + struct mcde_display_hdmi_platform_data *pdata = + dev->dev.platform_data; + + if (pdata == NULL) { + dev_err(&dev->dev, "%s:Platform data missing\n", __func__); + goto no_pdata; + } + + if (dev->port->type != MCDE_PORTTYPE_DSI) { + dev_err(&dev->dev, "%s:Invalid port type %d\n", + __func__, dev->port->type); + goto invalid_port_type; + } + + dev->prepare_for_update = NULL; + dev->on_first_update = hdmi_on_first_update; + dev->try_video_mode = hdmi_try_video_mode; + dev->set_video_mode = hdmi_set_video_mode; + + ret = av8100_powerup(); + if (ret != AV8100_OK) { + dev_err(&dev->dev, "av8100_powerup failed\n"); + goto out; + } + + dev_info(&dev->dev, "HDMI display probed\n"); + + goto out; +invalid_port_type: +no_pdata: +out: + return ret; +} + +static int __devexit hdmi_remove(struct mcde_display_device *dev) +{ + struct mcde_display_hdmi_platform_data *pdata = + dev->dev.platform_data; + + dev->set_power_mode(dev, MCDE_DISPLAY_PM_OFF); + + if (pdata->hdmi_platform_enable) { + if (pdata->regulator) + regulator_put(pdata->regulator); + if (pdata->reset_gpio) { + gpio_direction_input(pdata->reset_gpio); + gpio_free(pdata->reset_gpio); + } + } + + return 0; +} + +static int hdmi_resume(struct mcde_display_device *ddev) +{ + int ret; + ret = av8100_powerup(); + if (ret != AV8100_OK) { + dev_err(&ddev->dev, "%s:av8100_powerup failed\n", __func__); + goto out; + } + + ret = av8100_download_firmware(NULL, 0, I2C_INTERFACE); + if (ret != AV8100_OK) { + dev_err(&ddev->dev, "%s:av8100_download_firmware failed\n", + __func__); + goto out; + } + +out: + return ret; +} + +static int hdmi_suspend(struct mcde_display_device *ddev, pm_message_t state) +{ + int ret; + ret = av8100_powerdown(); + if (ret != AV8100_OK) { + dev_err(&ddev->dev, "%s:av8100_powerdown failed\n", __func__); + goto out; + } +out: + return ret; +} + +static struct mcde_display_driver hdmi_driver = { + .probe = hdmi_probe, + .remove = hdmi_remove, + .suspend = hdmi_suspend, + .resume = hdmi_resume, + .driver = { + .name = "av8100_hdmi", + }, +}; + +/* Module init */ +static int __init mcde_display_hdmi_init(void) +{ + int retval; + pr_info("%s\n", __func__); + + retval = mcde_display_driver_register(&hdmi_driver); + + return retval; +} +late_initcall(mcde_display_hdmi_init); + +static void __exit mcde_display_hdmi_exit(void) +{ + pr_info("%s\n", __func__); + + mcde_display_driver_unregister(&hdmi_driver); +} +module_exit(mcde_display_hdmi_exit); + +MODULE_AUTHOR("Per Persson <per.xb.persson@stericsson.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ST-Ericsson hdmi display driver"); diff --git a/drivers/video/mcde/display-generic_dsi.c b/drivers/video/mcde/display-generic_dsi.c new file mode 100644 index 00000000000..1f28497569a --- /dev/null +++ b/drivers/video/mcde/display-generic_dsi.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE generic DCS display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <video/mcde_display.h> +#include <video/mcde_display-generic_dsi.h> + +static int generic_platform_enable(struct mcde_display_device *dev) +{ + int ret = 0; + struct mcde_display_generic_platform_data *pdata = + dev->dev.platform_data; + + dev_dbg(&dev->dev, "%s: Reset & power on generic display\n", __func__); + + if (pdata->regulator) { + ret = regulator_enable(pdata->regulator); + if (ret < 0) { + dev_err(&dev->dev, "%s:Failed to enable regulator\n" + , __func__); + goto out; + } + } + if (pdata->reset_gpio) + gpio_set_value(pdata->reset_gpio, pdata->reset_high); + mdelay(pdata->reset_delay); + if (pdata->reset_gpio) + gpio_set_value(pdata->reset_gpio, !pdata->reset_high); +out: + return ret; +} + +static int generic_platform_disable(struct mcde_display_device *dev) +{ + int ret = 0; + struct mcde_display_generic_platform_data *pdata = + dev->dev.platform_data; + + dev_dbg(&dev->dev, "%s:Reset & power off generic display\n", __func__); + + if (pdata->regulator) { + ret = regulator_disable(pdata->regulator); + if (ret < 0) + dev_err(&dev->dev, "%s:Failed to disable regulator\n" + , __func__); + } + return ret; +} + +static int __devinit generic_probe(struct mcde_display_device *dev) +{ + int ret = 0; + struct mcde_display_generic_platform_data *pdata = + dev->dev.platform_data; + + if (pdata == NULL) { + dev_err(&dev->dev, "%s:Platform data missing\n", __func__); + ret = -EINVAL; + goto no_pdata; + } + + if (dev->port->type != MCDE_PORTTYPE_DSI) { + dev_err(&dev->dev, + "%s:Invalid port type %d\n", + __func__, dev->port->type); + ret = -EINVAL; + goto invalid_port_type; + } + + if (!dev->platform_enable && !dev->platform_disable) { + pdata->generic_platform_enable = true; + if (pdata->reset_gpio) { + ret = gpio_request(pdata->reset_gpio, NULL); + if (ret) { + dev_warn(&dev->dev, + "%s:Failed to request gpio %d\n", + __func__, pdata->reset_gpio); + goto gpio_request_failed; + } + gpio_direction_output(pdata->reset_gpio, + !pdata->reset_high); + } + if (pdata->regulator_id) { + pdata->regulator = regulator_get(NULL, + pdata->regulator_id); + if (IS_ERR(pdata->regulator)) { + ret = PTR_ERR(pdata->regulator); + dev_warn(&dev->dev, + "%s:Failed to get regulator '%s'\n", + __func__, pdata->regulator_id); + pdata->regulator = NULL; + goto regulator_get_failed; + } + } + dev->platform_enable = generic_platform_enable; + dev->platform_disable = generic_platform_disable; + } + + if (dev->video_mode.xres == 0 || dev->video_mode.yres == 0) { + dev->video_mode.xres = dev->native_x_res; + dev->video_mode.yres = dev->native_y_res; + } + + /* TODO: Remove when DSI send command uses interrupts */ + dev->prepare_for_update = NULL; + dev->platform_enable = generic_platform_enable, + dev->platform_disable = generic_platform_disable, + + dev_info(&dev->dev, "Generic display probed\n"); + + goto out; + +regulator_get_failed: + if (pdata->generic_platform_enable && pdata->reset_gpio) + gpio_free(pdata->reset_gpio); +gpio_request_failed: +invalid_port_type: +no_pdata: +out: + return ret; +} + +static int __devexit generic_remove(struct mcde_display_device *dev) +{ + struct mcde_display_generic_platform_data *pdata = + dev->dev.platform_data; + + dev->set_power_mode(dev, MCDE_DISPLAY_PM_OFF); + + if (pdata->generic_platform_enable) { + if (pdata->regulator) + regulator_put(pdata->regulator); + if (pdata->reset_gpio) { + gpio_direction_input(pdata->reset_gpio); + gpio_free(pdata->reset_gpio); + } + } + + return 0; +} + +static int generic_resume(struct mcde_display_device *ddev) +{ + int ret; + /* set_power_mode will handle call platform_enable */ + ret = ddev->set_power_mode(ddev, MCDE_DISPLAY_PM_STANDBY); + if (ret < 0) + dev_warn(&ddev->dev, "%s:Failed to resume display\n" + , __func__); + return ret; +} + +static int generic_suspend(struct mcde_display_device *ddev, pm_message_t state) +{ + int ret; + /* set_power_mode will handle call platform_disable */ + ret = ddev->set_power_mode(ddev, MCDE_DISPLAY_PM_OFF); + if (ret < 0) + dev_warn(&ddev->dev, "%s:Failed to suspend display\n" + , __func__); + return ret; +} + +static struct mcde_display_driver generic_driver = { + .probe = generic_probe, + .remove = generic_remove, + .suspend = generic_suspend, + .resume = generic_resume, + .driver = { + .name = "mcde_disp_generic", + }, +}; + +/* Module init */ +static int __init mcde_display_generic_init(void) +{ + pr_info("%s\n", __func__); + + return mcde_display_driver_register(&generic_driver); +} +module_init(mcde_display_generic_init); + +static void __exit mcde_display_generic_exit(void) +{ + pr_info("%s\n", __func__); + + mcde_display_driver_unregister(&generic_driver); +} +module_exit(mcde_display_generic_exit); + +MODULE_AUTHOR("Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ST-Ericsson MCDE generic DCS display driver"); diff --git a/drivers/video/mcde/dsi_hwaccess.c b/drivers/video/mcde/dsi_hwaccess.c deleted file mode 100644 index bea2c32fb97..00000000000 --- a/drivers/video/mcde/dsi_hwaccess.c +++ /dev/null @@ -1,1461 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -/** Linux include files:charachter driver and memory functions */ - - -#include <linux/module.h> -#include <linux/kernel.h> -#include <mach/mcde_common.h> - -extern struct mcdefb_info *gpar[]; -dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl & ~DSI_MCTL_LINKEN_MASK) |((u32) linkState & DSI_MCTL_LINKEN_MASK)); - gpar[chid]->dsi_lnk_context.dsi_link_state = linkState; - - return(dsi_error); -} - -dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_INTERFACE1_MODE_MASK) |(((u32) mode << DSI_MCTL_INTERFACE1_MODE_SHIFT) & DSI_MCTL_INTERFACE1_MODE_MASK) ); - - gpar[chid]->dsi_lnk_context.dsi_if_mode = mode; - - return(dsi_error); - -} - -dsi_error dsisetVSG(dsi_link link, dsi_vsg_ctrl state, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_VID_EN_MASK) |(((u32) state << DSI_MCTL_VID_EN_SHIFT ) & DSI_MCTL_VID_EN_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetTVG(dsi_link link, dsi_tvg_ctrl state, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - if ((gpar[chid]->dsi_lnk_context.dsi_if_mode == 1) || (gpar[chid]->dsi_lnk_context.dsi_if1_state == 1)) - { - return(DSI_REQUEST_NOT_APPLICABLE); - } - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_TVG_SEL_MASK) |(((u32) state << DSI_MCTL_TVG_SEL_SHIFT ) & DSI_MCTL_TVG_SEL_MASK) ); - - return(dsi_error); -} -dsi_error dsisetTBG(dsi_link link, dsi_tbg_ctrl state, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_TBG_SEL_MASK) |(((u32) state << DSI_MCTL_TBG_SEL_SHIFT ) & DSI_MCTL_TBG_SEL_MASK) ); - - return(dsi_error); -} - -dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_READEN_MASK) |(((u32) state << DSI_MCTL_READEN_SHIFT ) & DSI_MCTL_READEN_MASK) ); - - - return(dsi_error); -} - -dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_BTAEN_MASK) |(((u32) mode << DSI_MCTL_BTAEN_SHIFT ) & DSI_MCTL_BTAEN_MASK) ); - - return(dsi_error); -} -dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - - switch(tearing.te_sel) - { - case DSI_REG_TE: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_REG_TE_MASK) |(((u32) state << DSI_REG_TE_SHIFT ) & DSI_REG_TE_MASK) ); - break; - - case DSI_IF_TE: - if(tearing.interface == DSI_INTERFACE_1) - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_IF1_TE_MASK) |(((u32) state << DSI_IF1_TE_SHIFT ) & DSI_IF1_TE_MASK) ); - else if(tearing.interface == DSI_INTERFACE_2) - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_IF2_TE_MASK) |(((u32) state << DSI_IF2_TE_SHIFT ) & DSI_IF2_TE_MASK) ); - else - dsi_error = DSI_INVALID_PARAMETER ; - break; - - default: - dsi_error = DSI_INVALID_PARAMETER ; - } - - - return(dsi_error); -} - -dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_DISPECCGEN_MASK) |(((u32) mode << DSI_MCTL_DISPECCGEN_SHIFT ) & DSI_MCTL_DISPECCGEN_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_DISPCHECKSUMGEN_MASK) |(((u32) mode << DSI_MCTL_DISPCHECKSUMGEN_SHIFT ) & DSI_MCTL_DISPCHECKSUMGEN_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_DISPEOTGEN_MASK) |(((u32) mode << DSI_MCTL_DISPEOTGEN_SHIFT ) & DSI_MCTL_DISPEOTGEN_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_data_ctl &~DSI_MCTL_HOSTEOTGEN_MASK) |(((u32) mode << DSI_MCTL_HOSTEOTGEN_SHIFT ) & DSI_MCTL_HOSTEOTGEN_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl &~DSI_PLL_OUT_SEL_MASK) |(((u32) pll_ctl.pll_out_sel << DSI_PLL_OUT_SEL_SHIFT ) & DSI_PLL_OUT_SEL_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl &~DSI_PLL_DIV_MASK) |(((u32) pll_ctl.division_ratio << DSI_PLL_DIV_SHIFT ) & DSI_PLL_DIV_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl &~DSI_PLL_IN_SEL_MASK) |(((u32) pll_ctl.pll_in_sel << DSI_PLL_IN_SEL_SHIFT ) & DSI_PLL_IN_SEL_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl &~DSI_PLL_MASTER_MASK) |(((u32) pll_ctl.pll_master << DSI_PLL_MASTER_SHIFT ) & DSI_PLL_MASTER_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_pll_ctl &~DSI_PLL_MULT_MASK) |((u32) pll_ctl.multiplier & DSI_PLL_MASTER_MASK) ); - - return(dsi_error); -} -dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface) -{ - dsi_error dsi_error = DSI_OK; - - switch(interface) - { - case DSI_INTERFACE_1: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_IF1_EN_MASK) |(((u32) state << DSI_IF1_EN_SHIFT)& DSI_IF1_EN_MASK) ); - break; - - case DSI_INTERFACE_2: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_IF2_EN_MASK) |(((u32) state << DSI_IF2_EN_SHIFT)& DSI_IF2_EN_MASK) ); - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - } - - return(dsi_error); -} -dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface) -{ - dsi_error dsi_error = DSI_OK; - dsi_if_state ifState; - - if ( modType == DSI_CLK_LANE_LPM) - ifState = DSI_IF_ENABLE; - else - ifState = DSI_IF_DISABLE; - - switch(interface) - { - case DSI_INTERFACE_1: - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_IF1_LPM_EN_MASK) |(((u32) ifState << DSI_IF1_LPM_EN_MASK_SHIFT)& DSI_IF1_LPM_EN_MASK) ); - break; - - case DSI_INTERFACE_2: - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_IF2_LPM_EN_MASK) |(((u32) ifState << DSI_IF2_LPM_EN_MASK_SHIFT)& DSI_IF2_LPM_EN_MASK) ); - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - } - - return(dsi_error); -} -dsi_error dsisetstallsignal(dsi_link link, mcde_ch_id chid, dsi_stall_signal_state state, dsi_interface_mode mode) -{ - dsi_error dsi_error = DSI_OK; - - if(gpar[chid]->dsi_lnk_context.dsi_int_mode != DSI_INT_MODE_ENABLE) - return(DSI_REQUEST_NOT_APPLICABLE); - switch(mode) - { - case DSI_VIDEO_MODE: - gpar[chid]->dsi_lnk_registers[link]->int_vid_gnt = ((gpar[chid]->dsi_lnk_registers[link]->int_vid_gnt &~DSI_IF_STALL_MASK) |((u32) state & DSI_IF_STALL_MASK) ); - - break; - - case DSI_COMMAND_MODE: - gpar[chid]->dsi_lnk_registers[link]->int_cmd_gnt = ((gpar[chid]->dsi_lnk_registers[link]->int_cmd_gnt &~DSI_IF_STALL_MASK) |((u32) state & DSI_IF_STALL_MASK) ); - - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - - } - - return(dsi_error); - - -} -dsi_error dsisetdirectcmdsettings(dsi_link link, mcde_ch_id chid, dsi_cmd_main_setting cmd_settings) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_NAT_MASK) |((u32) cmd_settings.cmd_nature & DSI_CMD_NAT_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_LONGNOTSHORT_MASK) |(((u32) cmd_settings.packet_type << DSI_CMD_LONGNOTSHORT_SHIFT)& DSI_CMD_LONGNOTSHORT_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_HEAD_MASK) |(((u32) cmd_settings.cmd_header << DSI_CMD_HEAD_SHIFT)& DSI_CMD_HEAD_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_ID_MASK) |(((u32) cmd_settings.cmd_id << DSI_CMD_ID_SHIFT)& DSI_CMD_ID_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_SIZE_MASK) |(((u32) cmd_settings.cmd_size << DSI_CMD_SIZE_SHIFT)& DSI_CMD_SIZE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_CMD_LP_EN_MASK) |(((u32) cmd_settings.cmd_lp_enable << DSI_CMD_LP_EN_SHIFT)& DSI_CMD_LP_EN_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings &~DSI_TRIGGER_VAL_MASK) |(((u32) cmd_settings.cmd_trigger_val << DSI_TRIGGER_VAL_SHIFT)& DSI_TRIGGER_VAL_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout) -{ - dsi_error dsi_error = DSI_OK; - u8 te_lowerbits ; - dsi_te_timeout te_upperbits; - - if(te_timeout/256 == 1) - { - te_lowerbits = te_timeout % 256; - te_upperbits = DSI_TE_256; - } - else if(te_timeout/512 == 1) - { - te_lowerbits = te_timeout % 512; - te_upperbits = DSI_TE_512; - } - else if (te_timeout/1024 == 1) - { - te_lowerbits = te_timeout % 1024; - te_upperbits = DSI_TE_1024; - } - else - { - te_lowerbits = te_timeout % 2048; - te_upperbits = DSI_TE_2048; - } - - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_TE_LOWERBIT_MASK) |(((u32) te_lowerbits << DSI_TE_LOWERBIT_SHIFT)& DSI_TE_LOWERBIT_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_TE_UPPERBIT_MASK) |(((u32) te_upperbits << DSI_TE_UPPERBIT_SHIFT)& DSI_TE_UPPERBIT_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode) -{ - dsi_error dsi_error = DSI_OK; - - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_PLL_START_MASK) |((u32) mode & DSI_PLL_START_MASK) ); - - return(dsi_error); -} -dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane) -{ - dsi_error dsi_error = DSI_OK; - - if ( (lane > DSI_DATA_LANE2)) - { - return(DSI_INVALID_PARAMETER); - } - - switch(lane) - { - case DSI_CLK_LANE: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_CKLANE_EN_MASK) |(((u32) mode << DSI_CKLANE_EN_SHIFT)& DSI_CKLANE_EN_MASK) ); - break; - - case DSI_DATA_LANE1: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_DAT1_EN_MASK) |(((u32) mode << DSI_DAT1_EN_SHIFT)& DSI_DAT1_EN_MASK) ); - break; - - case DSI_DATA_LANE2: - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_LANE2_EN_MASK) |((u32) mode & DSI_LANE2_EN_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_DAT2_EN_MASK) |(((u32) mode << DSI_DAT2_EN_SHIFT)& DSI_DAT2_EN_MASK) ); - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - } - - return(dsi_error); - -} - -dsi_error dsisetlanetoULPM(dsi_link link, mcde_ch_id chid, dsi_lane_mode mode, dsi_lane lane) -{ - dsi_error dsi_error = DSI_OK; - - if ( (lane > DSI_DATA_LANE2)) - { - return(DSI_INVALID_PARAMETER); - } - - switch(lane) - { - case DSI_CLK_LANE: - /** enable the ULPM mode for clock lane*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_CLK_ULPM_EN_MASK) |(((u32) mode << DSI_CLK_ULPM_EN_SHIFT ) & DSI_CLK_ULPM_EN_MASK) ); - /** start the clock lane in ULPM mode*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_CLK_ULPM_MASK) |(((u32) mode << DSI_CLK_ULPM_SHIFT)& DSI_CLK_ULPM_MASK) ); - break; - - case DSI_DATA_LANE1: - /** enable the ULPM mode for data1 lane*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_DAT1_ULPM_EN_MASK) |(((u32) mode << DSI_DAT1_ULPM_EN_SHIFT ) & DSI_DAT1_ULPM_EN_MASK) ); - /** start the data1 lane in ULPM mode*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_DAT1_ULPM_MASK) |(((u32) mode << DSI_DAT1_ULPM_SHIFT)& DSI_DAT1_ULPM_MASK) ); - break; - - case DSI_DATA_LANE2: - /** enable the ULPM mode for data2 lane*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_DAT2_ULPM_EN_MASK) |(((u32) mode << DSI_DAT2_ULPM_EN_SHIFT ) & DSI_DAT2_ULPM_EN_MASK) ); - /** start the data2 lane in ULPM mode*/ - gpar[chid]->dsi_lnk_registers[link]->mctl_main_en = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_en &~DSI_DAT2_ULPM_MASK) |(((u32) mode << DSI_DAT2_ULPM_SHIFT)& DSI_DAT2_ULPM_MASK) ); - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - } - return dsi_error; -} - -dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_CLK_CONTINUOUS_MASK) |(((u32) mode << DSI_CLK_CONTINUOUS_SHIFT ) & DSI_CLK_CONTINUOUS_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetwaitbursttime(dsi_link link, u8 delay, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl = ((gpar[chid]->dsi_lnk_registers[link]->mctl_main_phy_ctl &~DSI_WAIT_BURST_MASK) |(((u32) delay << DSI_WAIT_BURST_SHIFT ) & DSI_WAIT_BURST_MASK) ); - - return(dsi_error); -} - -dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status) -{ - dsi_error dsi_error = DSI_OK; - - *p_status = (u8)(gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts & DSI_MAIN_STS_MASK); - - return(dsi_error); -} - - -dsi_error dsisetvideomodectrl(dsi_link link, mcde_ch_id chid, dsi_vid_main_ctl vid_ctl) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_STOP_MODE_MASK) |(((u32) vid_ctl.vid_stop_mode << DSI_STOP_MODE_SHIFT)& DSI_STOP_MODE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_VID_ID_MASK) |(((u32) vid_ctl.vid_id << DSI_VID_ID_SHIFT)& DSI_VID_ID_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_HEADER_MASK) |(((u32) vid_ctl.header << DSI_HEADER_SHIFT)& DSI_HEADER_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_PIXEL_MODE_MASK) |(((u32) vid_ctl.vid_pixel_mode << DSI_PIXEL_MODE_SHIFT)& DSI_PIXEL_MODE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_BURST_MODE_MASK) |(((u32) vid_ctl.vid_burst_mode << DSI_BURST_MODE_SHIFT)& DSI_VID_ID_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_SYNC_PULSE_ACTIVE_MASK) |(((u32) vid_ctl.sync_pulse_active << DSI_SYNC_PULSE_ACTIVE_SHIFT)& DSI_VID_ID_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_SYNC_PULSE_HORIZONTAL_MASK) |(((u32) vid_ctl.sync_pulse_horizontal << DSI_SYNC_PULSE_HORIZONTAL_SHIFT)& DSI_SYNC_PULSE_HORIZONTAL_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_BLKLINE_MASK) |(((u32) vid_ctl.blkline_mode << DSI_BLKLINE_SHIFT)& DSI_BLKLINE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_BLKEOL_MASK) |(((u32) vid_ctl.blkeol_mode << DSI_BLKEOL_SHIFT)& DSI_BLKEOL_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_RECOVERY_MODE_MASK) |(((u32) vid_ctl.recovery_mode << DSI_RECOVERY_MODE_SHIFT)& DSI_RECOVERY_MODE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl = ((gpar[chid]->dsi_lnk_registers[link]->vid_main_ctl &~DSI_START_MODE_MASK) |((u32) vid_ctl.vid_start_mode & DSI_START_MODE_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetvideoXYsize(dsi_link link, mcde_ch_id chid, dsi_img_horizontal_size vid_hsize, dsi_img_vertical_size vid_vsize) -{ - dsi_error dsi_error = DSI_OK; - - // X size settings - gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 &~DSI_HBP_LENGTH_MASK) |(((u32) vid_hsize.hbp_length << DSI_HBP_LENGTH_SHIFT)& DSI_HBP_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 &~DSI_HFP_LENGTH_MASK) |(((u32) vid_hsize.hfp_length << DSI_HFP_LENGTH_SHIFT)& DSI_HFP_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_hsize1 &~DSI_HSA_LENGTH_MASK) |((u32) vid_hsize.hsa_length & DSI_HSA_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_hsize2 = ((gpar[chid]->dsi_lnk_registers[link]->vid_hsize2 &~DSI_RGB_SIZE_MASK) |((u32) vid_hsize.rgb_size & DSI_RGB_SIZE_MASK) ); - - //Y size settings - gpar[chid]->dsi_lnk_registers[link]->vid_vsize = ((gpar[chid]->dsi_lnk_registers[link]->vid_vsize &~DSI_VACT_LENGTH_MASK) |(((u32) vid_vsize.vact_length << DSI_VACT_LENGTH_SHIFT)& DSI_VACT_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vsize = ((gpar[chid]->dsi_lnk_registers[link]->vid_vsize &~DSI_VFP_LENGTH_MASK) |(((u32) vid_vsize.vfp_length << DSI_VFP_LENGTH_SHIFT)& DSI_VFP_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vsize = ((gpar[chid]->dsi_lnk_registers[link]->vid_vsize &~DSI_VBP_LENGTH_MASK) |(((u32) vid_vsize.vbp_length << DSI_VBP_LENGTH_SHIFT)& DSI_VBP_LENGTH_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vsize = ((gpar[chid]->dsi_lnk_registers[link]->vid_vsize &~DSI_VSA_LENGTH_MASK) |((u32) vid_vsize.vact_length & DSI_VSA_LENGTH_MASK) ); - - return(dsi_error); -} - - -dsi_error dsisetvideopos(dsi_link link, mcde_ch_id chid, dsi_img_position vid_pos) -{ - dsi_error dsi_error = DSI_OK; - - - gpar[chid]->dsi_lnk_registers[link]->vid_vpos = ((gpar[chid]->dsi_lnk_registers[link]->vid_vpos &~DSI_LINE_POS_MASK) |( (u32) vid_pos.line_pos & DSI_LINE_POS_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_vpos = ((gpar[chid]->dsi_lnk_registers[link]->vid_vpos &~DSI_LINE_VAL_MASK) |(((u32) vid_pos.line_val << DSI_LINE_VAL_SHIFT)& DSI_LINE_VAL_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_hpos = ((gpar[chid]->dsi_lnk_registers[link]->vid_hpos &~DSI_HORI_POS_MASK) |((u32) vid_pos.horizontal_pos & DSI_HORI_POS_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->vid_hpos = ((gpar[chid]->dsi_lnk_registers[link]->vid_hpos &~DSI_HORI_VAL_MASK) |(((u32) vid_pos.horizontal_val << DSI_HORI_VAL_SHIFT)& DSI_HORI_VAL_MASK) ); - - return(dsi_error); -} - -dsi_error dsigetvideomodestatus(dsi_link link, mcde_ch_id chid, u16 *p_vid_mode_sts) -{ - dsi_error dsi_error = DSI_OK; - - *p_vid_mode_sts = (u16)(gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts & DSI_VID_MODE_STS_MASK); - - return(dsi_error); -} - -dsi_error dsisetblankingctrl(dsi_link link, mcde_ch_id chid, dsi_vid_blanking blksize) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->vid_blksize1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_blksize1 &~DSI_BLKEOL_PCK_MASK) |(((u32) blksize.blkeol_pck << DSI_BLKEOL_PCK_SHIFT)& DSI_BLKEOL_PCK_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_blksize1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_blksize1 &~DSI_BLKLINE_EVENT_MASK) |((u32) blksize.blkline_event_pck & DSI_BLKLINE_EVENT_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_blksize2 = ((gpar[chid]->dsi_lnk_registers[link]->vid_blksize2 &~DSI_BLKLINE_PULSE_PCK_MASK) |((u32) blksize.blkline_pulse_pck & DSI_BLKLINE_PULSE_PCK_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_pck_time = ((gpar[chid]->dsi_lnk_registers[link]->vid_pck_time &~DSI_VERT_BLANK_DURATION_MASK) |(((u32) blksize.vert_balnking_duration << DSI_VERT_BLANK_DURATION_SHIFT)& DSI_VERT_BLANK_DURATION_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_pck_time = ((gpar[chid]->dsi_lnk_registers[link]->vid_pck_time &~DSI_BLKEOL_DURATION_MASK) |((u32) blksize.blkeol_duration & DSI_BLKEOL_DURATION_MASK) ); - - return(dsi_error); -} - - -dsi_error dsisetviderrorcolor(dsi_link link, mcde_ch_id chid, dsi_vid_err_color err_color) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->vid_err_color = ((gpar[chid]->dsi_lnk_registers[link]->vid_err_color &~DSI_COL_GREEN_MASK) |(((u32) err_color.col_green << DSI_COL_GREEN_SHIFT)& DSI_COL_GREEN_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_err_color = ((gpar[chid]->dsi_lnk_registers[link]->vid_err_color &~DSI_COL_BLUE_MASK) |(((u32) err_color.col_blue << DSI_COL_BLUE_SHIFT)& DSI_COL_BLUE_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_err_color = ((gpar[chid]->dsi_lnk_registers[link]->vid_err_color &~DSI_PAD_VAL_MASK) |(((u32) err_color.pad_val << DSI_PAD_VAL_SHIFT)& DSI_PAD_VAL_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_err_color = ((gpar[chid]->dsi_lnk_registers[link]->vid_err_color &~DSI_COL_RED_MASK) |((u32)err_color.col_red & DSI_COL_RED_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetVCActrl(dsi_link link, mcde_ch_id chid, dsi_vca_setting vca_setting) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting1 &~DSI_BURST_LP_MASK) |(((u32) vca_setting.burst_lp << DSI_BURST_LP_SHIFT)& DSI_BURST_LP_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting2 = ((gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting1 &~DSI_MAX_BURST_LIMIT_MASK) |((u32) vca_setting.max_burst_limit & DSI_MAX_BURST_LIMIT_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting1 = ((gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting2 &~DSI_MAX_LINE_LIMIT_MASK) |(((u32) vca_setting.max_line_limit << DSI_MAX_LINE_LIMIT_SHIFT)& DSI_MAX_LINE_LIMIT_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting2 = ((gpar[chid]->dsi_lnk_registers[link]->vid_vca_setting2 &~DSI_EXACT_BURST_LIMIT_MASK) |((u32) vca_setting.exact_burst_limit & DSI_EXACT_BURST_LIMIT_MASK) ); - - return(dsi_error); - -} -dsi_error dsisetTVGctrl(dsi_link link, mcde_ch_id chid, dsi_tvg_control tvg_control) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->tvg_ctl = ((gpar[chid]->dsi_lnk_registers[link]->tvg_ctl &~DSI_TVG_STRIPE_MASK) |(((u32) tvg_control.tvg_stripe_size << DSI_TVG_STRIPE_SHIFT)& DSI_TVG_STRIPE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_ctl = ((gpar[chid]->dsi_lnk_registers[link]->tvg_ctl &~DSI_TVG_MODE_MASK) |(((u32) tvg_control.tvg_mode << DSI_TVG_MODE_SHIFT)& DSI_TVG_MODE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_ctl = ((gpar[chid]->dsi_lnk_registers[link]->tvg_ctl &~DSI_TVG_STOPMODE_MASK) |(((u32) tvg_control.stop_mode << DSI_TVG_STOPMODE_SHIFT)& DSI_TVG_STOPMODE_MASK) ); - - return(dsi_error); -} - -dsi_error dsiTVGsetstate(dsi_link link, mcde_ch_id chid, dsi_tvg_ctrl_state state) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->tvg_ctl = ((gpar[chid]->dsi_lnk_registers[link]->tvg_ctl &~DSI_TVG_RUN_MASK) |((u32) state & DSI_TVG_RUN_MASK) ); - - return(dsi_error); -} - - - -dsi_error dsisetTVGimagesize(dsi_link link, mcde_ch_id chid, dsi_tvg_img_size img_size) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->tvg_img_size = ((gpar[chid]->dsi_lnk_registers[link]->tvg_img_size &~DSI_TVG_NBLINE_MASK) |(((u32) img_size.tvg_nbline << DSI_TVG_NBLINE_SHIFT)& DSI_TVG_NBLINE_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_img_size = ((gpar[chid]->dsi_lnk_registers[link]->tvg_img_size &~DSI_TVG_LINE_SIZE_MASK) |((u32) img_size.tvg_line_size & DSI_TVG_LINE_SIZE_MASK) ); - - return(dsi_error); -} - -dsi_error dsisetTVGcolor(dsi_link link, mcde_ch_id chid, dsi_color_type color_type,dsi_frame_color color) -{ - dsi_error dsi_error = DSI_OK; - - if(color_type == DSI_TVG_COLOR1) - { - gpar[chid]->dsi_lnk_registers[link]->tvg_color1 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color1 &~DSI_COL_RED_MASK) |((u32) color.col_red & DSI_COL_RED_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_color1 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color1 &~DSI_COL_GREEN_MASK) |(((u32) color.col_green << DSI_COL_GREEN_SHIFT)& DSI_COL_GREEN_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_color1 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color1 &~DSI_COL_BLUE_MASK) |(((u32) color.col_blue << DSI_COL_BLUE_SHIFT)& DSI_COL_BLUE_MASK) ); - } - else if (color_type == DSI_TVG_COLOR2) - { - gpar[chid]->dsi_lnk_registers[link]->tvg_color2 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color2 &~DSI_COL_RED_MASK) |((u32) color.col_red & DSI_COL_RED_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_color2 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color2 &~DSI_COL_GREEN_MASK) |(((u32) color.col_green << DSI_COL_GREEN_SHIFT)& DSI_COL_GREEN_MASK) ); - - gpar[chid]->dsi_lnk_registers[link]->tvg_color2 = ((gpar[chid]->dsi_lnk_registers[link]->tvg_color2 &~DSI_COL_BLUE_MASK) |(((u32) color.col_blue << DSI_COL_BLUE_SHIFT)& DSI_COL_BLUE_MASK) ); - - } - else - dsi_error = DSI_INVALID_PARAMETER; - - return(dsi_error); -} - -dsi_error dsisetARBctrl( dsi_link link, mcde_ch_id chid, dsi_arb_ctl arb_ctl) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_ARB_MODE_MASK) |(((u32) arb_ctl.arb_mode << DSI_ARB_MODE_SHIFT)& DSI_ARB_MODE_MASK) ); - - if(arb_ctl.arb_mode == DSI_ARB_MODE_FIXED) - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_ARB_PRI_MASK) |(((u32) arb_ctl.arb_mode << DSI_ARB_PRI_SHIFT)& DSI_ARB_PRI_MASK) ); - - return(dsi_error); - -} -dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl = ((gpar[chid]->dsi_lnk_registers[link]->cmd_mode_ctl &~DSI_FIL_VAL_MASK) |(((u32) padding << DSI_FIL_VAL_SHIFT)& DSI_FIL_VAL_MASK) ); - - return(dsi_error); - -} -dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout) -{ - dsi_error dsi_error = DSI_OK; - - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout &~DSI_HSTX_TO_MASK) |(((u32) timeout.hs_tx_timeout << DSI_HSTX_TO_SHIFT ) & DSI_HSTX_TO_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout &~DSI_LPRX_TO_MASK) |(((u32) timeout.lp_rx_timeout << DSI_LPRX_TO_SHIFT ) & DSI_LPRX_TO_MASK) ); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_timeout &~DSI_CLK_DIV_MASK) |((u32) timeout.clk_div & DSI_CLK_DIV_MASK) ); - - return(dsi_error); -} -dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout) -{ - dsi_error dsi_error = DSI_OK; - - if ( (lane > DSI_DATA_LANE2) || (link > DSI_LINK2) ) - { - return(DSI_INVALID_PARAMETER); - } - - switch(lane) - { - case DSI_CLK_LANE: - gpar[chid]->dsi_lnk_registers[link]->mctl_ulpout_time = ((gpar[chid]->dsi_lnk_registers[link]->mctl_ulpout_time &~DSI_CLK_ULPOUT_MASK) |((u32) timeout & DSI_DATA_ULPOUT_MASK) ); - break; - - case DSI_DATA_LANE1: - case DSI_DATA_LANE2: - gpar[chid]->dsi_lnk_registers[link]->mctl_ulpout_time = ((gpar[chid]->dsi_lnk_registers[link]->mctl_ulpout_time &~DSI_DATA_ULPOUT_MASK) |(((u32) timeout << DSI_DATA_ULPOUT_SHIFT ) & DSI_DATA_ULPOUT_MASK) ); - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - } - return dsi_error; -} -dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_HS_INVERT_CLK) |((u32) dphyStaticConf.clocklanehsinvermode << DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK) |((u32) dphyStaticConf.clocklaneswappinmode << DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1) |((u32) dphyStaticConf.datalane1hsinvermode << DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1) |((u32) dphyStaticConf.datalane1swappinmode << DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2) |((u32) dphyStaticConf.datalane2hsinvermode << DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2) |((u32) dphyStaticConf.datalane2swappinmode << DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT)); - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static = ((gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_static & ~DSIMCTL_DPHY_STATIC_UI_X4) |((u32) dphyStaticConf.ui_x4 << DSIMCTL_DPHY_STATIC_UI_X4_SHIFT)); - - return(dsi_error); -} -u32 dsiclearallstatus(mcde_ch_id chid, dsi_link link) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rd_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->tg_sts_clr = DSI_SET_ALL_BIT; - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_err_clr = DSI_SET_ALL_BIT; - return(dsi_error); -} -u32 dsienableirqsrc(mcde_ch_id chid, dsi_link link, dsi_irq_type irq_type,u32 irq_src) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - switch(irq_type) - { - case DSI_IRQ_TYPE_MCTL_MAIN : - gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts_ctl |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_sts_ctl |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_ctl |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rd_sts_ctl |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_VID_MODE : - gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts_ctl |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_TG : - gpar[chid]->dsi_lnk_registers[link]->tg_sts_ctl |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_ERROR : - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_err_ctl |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD : - gpar[chid]->dsi_lnk_registers[link]->dphy_clk_trim_rd_ctl |=(u8)irq_src; - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - break; - - } - return(dsi_error); -} -u32 dsidisableirqsrc(mcde_ch_id chid, dsi_link link, dsi_irq_type irq_type,u32 irq_src) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - switch(irq_type) - { - case DSI_IRQ_TYPE_MCTL_MAIN : - gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts_ctl |= (u8)~irq_src; - break; - - case DSI_IRQ_TYPE_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_sts_ctl |= (u8)~irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_ctl |= (u16)~irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rd_sts_ctl |= (u16)~irq_src; - break; - - case DSI_IRQ_TYPE_VID_MODE : - gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts_ctl |= (u16)~irq_src; - break; - - case DSI_IRQ_TYPE_TG : - gpar[chid]->dsi_lnk_registers[link]->tg_sts_ctl |= (u8)~irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_ERROR : - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_err_ctl |= (u16)~irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD : - gpar[chid]->dsi_lnk_registers[link]->dphy_clk_trim_rd_ctl |=(u8)~irq_src; - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - break; - - } - return(dsi_error); - -} -u32 dsiclearirqsrc(mcde_ch_id chid, dsi_link link, dsi_irq_type irq_type, u32 irq_src) -{ - dsi_error dsi_error = DSI_OK; - - if (link > DSI_LINK2) - { - return(DSI_INVALID_PARAMETER); - } - switch(irq_type) - { - case DSI_IRQ_TYPE_MCTL_MAIN : - gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts_flag |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->cmd_mode_sts_flag |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_flag |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE : - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rd_sts_flag |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_VID_MODE : - gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts_flag |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_TG : - gpar[chid]->dsi_lnk_registers[link]->tg_sts_flag |= (u8)irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_ERROR : - gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_err_flag |= (u16)irq_src; - break; - - case DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD : - gpar[chid]->dsi_lnk_registers[link]->dphy_clk_trim_rd_flag |=(u8)irq_src; - break; - - default: - dsi_error = DSI_INVALID_PARAMETER; - break; - - } - return(dsi_error); -} -u32 dsigetirqsrc(mcde_ch_id chid, dsi_link link, dsi_irq_type irq_type) -{ - u32 irq_src = DSI_NO_INTERRUPT; - - switch(irq_type) - { - case DSI_IRQ_TYPE_MCTL_MAIN : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->mctl_main_sts_flag ; - break; - - case DSI_IRQ_TYPE_CMD_MODE : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->cmd_mode_sts_flag; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_MODE : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_flag; - break; - - case DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rd_sts_flag; - break; - - case DSI_IRQ_TYPE_VID_MODE : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->vid_mode_sts_flag; - break; - - case DSI_IRQ_TYPE_TG : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->tg_sts_flag; - break; - - case DSI_IRQ_TYPE_DPHY_ERROR : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->mctl_dphy_err_flag; - break; - - case DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD : - irq_src = (u32)gpar[chid]->dsi_lnk_registers[link]->dphy_clk_trim_rd_flag; - break; - - default: - break; - - } - return(irq_src); - -} - -u32 dsiconfdphy(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link) -{ - mcde_dsi_clk_config clk_config; - dsi_pll_ctl pll_ctl; - u8 link_sts; - u32 time_out= 1000; - - clk_config.pllout_divsel2 = MCDE_PLL_OUT_1; - clk_config.pllout_divsel1 = MCDE_PLL_OUT_1; - clk_config.pllout_divsel0 = MCDE_PLL_OUT_1; - clk_config.txescdiv_sel = MCDE_DSI_MCDECLK; - clk_config.txescdiv = 0x8; - - pll_ctl.division_ratio = 0x0; - pll_ctl.pll_master = 0x0; - pll_ctl.pll_in_sel = 0x0; - pll_ctl.pll_out_sel = 0x1; - - switch(pll_sel) - { - case MCDE_CLK27: - clk_config.pll4in_sel = MCDE_CLK27; - pll_ctl.multiplier = 0x53; - break; - - case MCDE_TV1CLK: - clk_config.pll4in_sel = MCDE_TV1CLK; - pll_ctl.division_ratio = 0xD3; - break; - - case MCDE_TV2CLK: - clk_config.pll4in_sel = MCDE_TV2CLK; - pll_ctl.division_ratio = 0xD3; - break; - - case MCDE_HDMICLK: - clk_config.pll4in_sel = MCDE_HDMICLK; - pll_ctl.division_ratio = 0x9E; - break; - - case MCDE_MXTALI: - clk_config.pll4in_sel = MCDE_CLK27; - pll_ctl.division_ratio = 0xBA; - break; - - default: - return(1); - } - - mcdesetdsiclk(link, chid, clk_config); - - /*MCTL_MAIN_DATA_CTL*/ - dsisetlinkstate(link, DSI_ENABLE, chid); - - /*Main enable-start enable*/ - - dsisetlanestate(link, chid, DSI_PLL_START, DSI_CLK_LANE); - dsisetlanestate(link, chid, DSI_PLL_START, DSI_DATA_LANE1); - - dsisetPLLcontrol(link, chid, pll_ctl); - dsisetPLLmode(link, chid, DSI_PLL_START); - - - while(time_out > 0) - time_out--; - - /*Wait for PLL Ready*/ - dsigetlinkstatus(link, chid, &link_sts); - - if(!(link_sts & 0x6)) - return(1);/*PLL programming failed*/ - - return(0); - -} - -dsi_error dsigetdirectcommandstatus(dsi_link link,mcde_ch_id chid, u32 * p_status) -{ - dsi_error dsi_error = DSI_OK; - - *p_status = (u32)(gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts & 0xFFFFFFFF); - - return(dsi_error); -} -u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid) -{ - u32 err=0; - switch(cmd_head) - { - /********************************************************************/ - case 0x39: - /** Direct command main register */ - if (mode_type == DSI_CLK_LANE_HSM) - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00003908 | cmd_size << 16; - else /** LPM */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00203908 | cmd_size << 16; - - break; - /********************************************************************/ - case 0x15: - /** Direct command main register */ - if (mode_type == DSI_CLK_LANE_HSM) - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00001500 | cmd_size << 16; - else /** LPM */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00201500 | cmd_size << 16; - break; - - /********************************************************************/ - case 0x05: - /** Direct command main register */ - if (mode_type == DSI_CLK_LANE_HSM) - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00000500 | cmd_size << 16; - else /** LPM */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00200500 | cmd_size << 16; - break; - - case 0x09: - /** Direct command main register */ - if (mode_type == DSI_CLK_LANE_HSM) - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00000908 | cmd_size << 16; - else /** LPM */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x00200908 | cmd_size << 16; - break; - - /********************************************************************/ - default: - printk("Command ID not supported\n"); - err=1; - return err; - - } - - /** Data registers */ - if (cmd1 != 0) - { - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = cmd1; - } - if (cmd2 != 0) - { - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1 = cmd2; - } - if (cmd3 != 0) - { - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2 = cmd3; - - } - if (cmd4 != 0) - { - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= cmd4; - - } - - /** Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - return err; -} -EXPORT_SYMBOL(dsisenddirectcommand); -/** - * dsiLPdcslongwrite - This Api is used to send the data(Max 16 bytes) with dcs long packet command using dsi interface in low power mode. - * - */ -u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3, - u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11, - u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link) -{ - int uTimeout = 0xFFFFFFFF; - u32 retVal =0; - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - cmd_settings.cmd_header = 0x39; - cmd_settings.cmd_lp_enable = DSI_ENABLE; - cmd_settings.cmd_size = NoOfParam; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x1; /** long packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT1) | - (Param1 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT2) | - (Param2 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT3) | - (Param3 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT4) | - (Param4 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT5) | - (Param5 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT6) | - (Param6 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT7) | - (Param7<< Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT8) | - (Param8 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT9) | - (Param9 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT10) | - (Param10 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT11) | - (Param11 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11)); - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT12) | - (Param12 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT13) | - (Param13 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT14) | - (Param14 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT15) | - (Param15 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15)); - - /** Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - - uTimeout = 0xFFF; - - while(uTimeout > 0) - uTimeout--; - - - - /** Wait for PLL Ready */ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_LP_DCS_Long_Write\n"); - return(1);/** PLL programming failed */ - } - - return retVal; -} -EXPORT_SYMBOL(dsiLPdcslongwrite); -/** - * dsiLPdcsshortwrite1parm - This Api is used to send dcs short packet(1 byte max) command using dsi interface in low power mode. - * - */ -u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link) -{ - u32 retVal =0; - - u32 uTimeout = 0xFFFFFFFF; - - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - - cmd_settings.cmd_header = 0x15; - cmd_settings.cmd_lp_enable = DSI_ENABLE; - cmd_settings.cmd_size = 0x2; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x0; /** short packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT1) | - (Param1 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1)); - - - /* Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - while(uTimeout > 0) - uTimeout--; - - - - /*Wait for PLL Ready*/ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_LP_DCS_Long_Write\n"); - return(1);/** PLL programming failed*/ - } - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - return retVal; -} -EXPORT_SYMBOL(dsiLPdcsshortwrite1parm); -/** - * dsiLPdcsshortwritenoparam - This Api is used to send dcs short packet command using dsi interface with out any data in low power mode. - * - */ -u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link) -{ - - u32 retVal =0; - u32 uTimeout = 0xFFFFFFFF; - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - - cmd_settings.cmd_header = 0x05; - cmd_settings.cmd_lp_enable = DSI_ENABLE; - cmd_settings.cmd_size = 0x1; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x0; /** short packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - /** Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - - while(uTimeout > 0) - uTimeout--; - - - - /** Wait for PLL Ready */ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_LP_DCS_Long_Write\n"); - return(1);/** PLL programming failed */ - } - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - return retVal; -} -EXPORT_SYMBOL(dsiLPdcsshortwritenoparam); -/** - * dsiHSdcslongwrite - This Api is used to send the data(Max 16 bytes) with dcs long packet command using dsi interface in high speed mode. - * - */ -u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3, - u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11, - u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link) -{ - int uTimeout = 0xFFFFFFFF; - u32 retVal =0; - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - cmd_settings.cmd_header = 0x39; - cmd_settings.cmd_lp_enable = DSI_DISABLE; - cmd_settings.cmd_size = NoOfParam; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x1; /** long packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT1) | - (Param1 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT2) | - (Param2 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT3) | - (Param3 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT4) | - (Param4 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT5) | - (Param5 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT6) | - (Param6 << Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat1= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT1_WRDAT7) | - (Param7<< Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT8) | - (Param8 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT9) | - (Param9 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT10) | - (Param10 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat2= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT2_WRDAT11) | - (Param11 << Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11)); - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT12) | - (Param12 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT13) | - (Param13 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT14) | - (Param14 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat3= ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT3_WRDAT15) | - (Param15 << Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15)); - - /** Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - - uTimeout = 0xFFF; - - while(uTimeout > 0) - uTimeout--; - - /** Wait for PLL Ready */ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_HS_DCS_Long_Write\n"); - return(1);/** PLL programming failed */ - } - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - return retVal; -} -EXPORT_SYMBOL(dsiHSdcslongwrite); -/** - * dsiHSdcsshortwrite1parm - This Api is used to send dcs short packet(1 byte max) command using dsi interface in high speed mode. - * - */ -u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link) -{ - u32 retVal =0; - - u32 uTimeout = 0xFFFFFFFF; - - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - - cmd_settings.cmd_header = 0x15; - cmd_settings.cmd_lp_enable = DSI_DISABLE; - cmd_settings.cmd_size = 0x2; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x0; /** short packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT1) | - (Param1 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1)); - - - /* Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - while(uTimeout > 0) - uTimeout--; - - - - /*Wait for PLL Ready*/ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_LP_DCS_Long_Write\n"); - return(1);/** PLL programming failed*/ - } - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - return retVal; -} -EXPORT_SYMBOL(dsiHSdcsshortwrite1parm); -/** - * dsiHSdcsshortwritenoparam - This Api is used to send dcs short packet command using dsi interface with out any data in high speed mode. - * - */ -u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link) -{ - - u32 retVal =0; - u32 uTimeout = 0xFFFFFFFF; - dsi_cmd_main_setting cmd_settings; - u32 command_sts; - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - - cmd_settings.cmd_header = 0x05; - cmd_settings.cmd_lp_enable = DSI_DISABLE; - cmd_settings.cmd_size = 0x1; - cmd_settings.cmd_id = VC_ID; - cmd_settings.packet_type = 0x0; /** short packet */ - cmd_settings.cmd_nature = 0x0; /** command nature is write */ - cmd_settings.cmd_trigger_val = 0x0; - - dsisetdirectcmdsettings(link, chid, cmd_settings); - - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_wrdat0 & ~DSIDIRECT_CMD_WRDAT0_WRDAT0) | - (Param0 << Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0)); - - /** Send command */ - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_send = 0x00000001; - - - while(uTimeout > 0) - uTimeout--; - - - - /** Wait for PLL Ready */ - dsigetdirectcommandstatus(link, chid, &command_sts); - - if(!(command_sts & 0x2)) - { - dbgprintk(MCDE_ERROR_INFO, "ERROR in sending DSI_LP_DCS_Long_Write\n"); - return(1);/** PLL programming failed */ - } - gpar[chid]->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x2; /** write completed flag */ - - return retVal; -} -EXPORT_SYMBOL(dsiHSdcsshortwritenoparam); -/** - * dsireaddata - This Api is used to read the data from dsi interface command fifo(max of 4 bytes). - * - */ -u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link) -{ - u32 retVal =0; - - *byte0 = (gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rddat & DSIDIRECT_CMD_RDAT0); - *byte1 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rddat & DSIDIRECT_CMD_RDAT1)) >> Shift_DSIDIRECT_CMD_RDAT1; - *byte2 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rddat & DSIDIRECT_CMD_RDAT2)) >> Shift_DSIDIRECT_CMD_RDAT2; - *byte3 = ((gpar[chid]->dsi_lnk_registers[link]->direct_cmd_rddat & DSIDIRECT_CMD_RDAT3)) >> Shift_DSIDIRECT_CMD_RDAT3; - - return retVal; -} -EXPORT_SYMBOL(dsireaddata); - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - - - - - - - diff --git a/drivers/video/mcde/dsi_link_utils.c b/drivers/video/mcde/dsi_link_utils.c deleted file mode 100644 index 6b15a7ba9cc..00000000000 --- a/drivers/video/mcde/dsi_link_utils.c +++ /dev/null @@ -1,1794 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT -/* HW V1 */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <mach/mcde_common.h> - -extern struct mcdefb_info *gpar[]; -#ifdef TESTING -char * pbitmapData; /** to be removed */ -#endif - -#define DSI_TAAL_DISPLAY - -dsi_error dsiPllConf(dsi_pll_ctl pll_ctl, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - u32 waitTimeout = 0xFFFFFFFF; - u8 pll_sts; - - /** Clock Selection and enabling */ - dsisetPLLcontrol(link, chid, pll_ctl); - dsisetPLLmode(link, chid, DSI_PLL_START); - - /** Wait Till pll LOCKS */ - waitTimeout = 0xFFFF; - dsigetlinkstatus(link, chid, &pll_sts); - while ( !(pll_sts & DSI_PLL_LOCK) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &pll_sts); - } - if (waitTimeout == 0) - { - dbgprintk(MCDE_ERROR_INFO, "dsiPLLconf:PLL lOCK FAILED!!!!\n"); - retVal = DSI_PLL_PROGRAM_ERROR; - } - return retVal; -} -dsi_error dsiLinkConf (struct dsi_link_conf *pdsiLinkConf, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - dsi_interface dsiInterface; - dsi_if_state dsiInterfaceState; /** interface enable/disable */ - dsi_te_en tearing; - switch (pdsiLinkConf->dsiInterfaceMode) - { - case DSI_VIDEO_MODE: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_VIDEO_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->videoModeType, dsiInterface); - break; - case DSI_COMMAND_MODE: - if (pdsiLinkConf->dsiInterface == DSI_INTERFACE_1) - { - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_COMMAND_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - }else - { - dsiInterface = DSI_INTERFACE_2; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - } - break; - case DSI_INTERFACE_BOTH: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_VIDEO_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->videoModeType, dsiInterface); - - dsiInterface = DSI_INTERFACE_2; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - break; - case DSI_INTERFACE_NONE: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_DISABLE; - /** disable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - dsiInterface = DSI_INTERFACE_2; - /** disable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - - break; - default: - retVal = DSI_INVALID_PARAMETER; - break; - } - - /** configuring the TE values for If1 */ - tearing.te_sel = DSI_IF_TE; - tearing.interface = DSI_INTERFACE_1; - dsisetTE(link, tearing, pdsiLinkConf->if1TeCtrl, chid); - - /** configuring the TE values for If2 */ - tearing.te_sel = DSI_IF_TE; - tearing.interface = DSI_INTERFACE_2; - dsisetTE(link, tearing, pdsiLinkConf->if2TeCtrl, chid); - - /** configuring the TE values for reg type */ - tearing.te_sel = DSI_REG_TE; - dsisetTE(link, tearing, pdsiLinkConf->regTeCtrl, chid); - - /** configuring read,BTA,EOTGen,HostEOTGen,CheckSumGen,Continious clock and padding values */ - dsireadset(link, pdsiLinkConf->rdCtrl, chid); - dsisetBTAmode(link, pdsiLinkConf->btaMode, chid); - dsisetdispEOTGenmode(link, pdsiLinkConf->displayEotGenMode, chid); - dsisetdispHOSTEOTGenmode(link, pdsiLinkConf->hostEotGenMode, chid); - dsisetdispCHKSUMGenmode(link, pdsiLinkConf->dispChecksumGenMode, chid); - dsisetdispECCGenmode(link, pdsiLinkConf->dispEccGenMode, chid); - dsisetCLKHSsendingmode(link, pdsiLinkConf->clockContiniousMode, chid); - dsisetpaddingval(link, chid, pdsiLinkConf->paddingValue); - - return retVal; -} -dsi_error dsiLinkEnable (struct dsi_link_conf *pdsiLinkConf, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - u32 waitTimeout = 0xFFFFFFFF; - u8 link_sts; - - /** Enable the DSI link, Link Clock and the Data Lane */ - dsisetlinkstate(link, pdsiLinkConf->dsiLinkState, chid); - dsisetlanestate(link, chid, pdsiLinkConf->clockLaneMode, DSI_CLK_LANE); - dsisetlanestate(link, chid, pdsiLinkConf->dataLane1Mode, DSI_DATA_LANE1); - - if (pdsiLinkConf->clockLaneMode == DSI_LANE_ENABLE) - { - /** Wait Till clock lane are ready */ - waitTimeout = 0xFFFFFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_CLKLANE_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_CLOCK_LANE_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Clock Lane not ready :...... FAILED!!!!\n"); - } - } - /** Wait Till data1 lane are ready */ - if (pdsiLinkConf->clockLaneMode == DSI_LANE_ENABLE) - { - waitTimeout = 0xFFFFFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_DAT1_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_DATA_LANE1_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Data Lane1 not ready :...... FAILED!!!!\n"); - } - } - if(pdsiLinkConf->dataLane2Mode == DSI_LANE_ENABLE) - { - dsisetlanestate(link, chid, pdsiLinkConf->dataLane2Mode, DSI_DATA_LANE2); - /*************** Wait Till DATA1 lane are ready ********/ - //waitTimeout = 0xFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_DAT2_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_DATA_LANE2_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Data Lane2 not ready :...... FAILED!!!!\n"); - } - } - return retVal; -} - -u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link) -{ - dsi_pll_ctl pll_ctl; - - pll_ctl.multiplier = 0x0; - pll_ctl.division_ratio = 0x0; - - pll_ctl.pll_in_sel = DSI_PLL_IN_CLK_27; - - if (pdsiLinkConf->commandModeType == DSI_CLK_LANE_HSM || pdsiLinkConf->videoModeType == DSI_CLK_LANE_HSM) - { - pll_ctl.pll_master = DSI_PLL_SLAVE; - pll_ctl.pll_out_sel = DSI_INTERNAL_PLL; - } - else - { - pll_ctl.pll_master = DSI_PLL_MASTER; - pll_ctl.pll_out_sel = DSI_SYSTEM_PLL; - } - - /*Main enable-start enable*/ - dsiLinkConf (pdsiLinkConf,chid, link); - dsiLinkEnable (pdsiLinkConf, chid, link); - - dsiset_hs_clock(link, dphyStaticConf, chid); - dsiPllConf(pll_ctl, chid, link); - - return(0); - -} - -/** - Initialization of TPO Display using LP mode and DSI direct command registor & dispaly of two alternating color - */ -int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key) -{ - struct dsi_dphy_static_conf dphyStaticConf; - struct dsi_link_conf dsiLinkConf; - struct mcdefb_info *currentpar = info->par; - unsigned int retVal= 0; - unsigned int Field = 1; - int num, temp; - int No_Loop; - unsigned char PixelRed; - unsigned char PixelGreen; - unsigned char PixelBlue; - int pixel_nb ; - - - dsiLinkConf.dsiInterfaceMode = DSI_INTERFACE_NONE; - dsiLinkConf.clockContiniousMode = DSI_CLK_CONTINIOUS_HS_DISABLE; - dsiLinkConf.dsiLinkState = DSI_ENABLE; - dsiLinkConf.clockLaneMode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane1Mode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane2Mode = DSI_LANE_DISABLE; - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dsiLinkConf.commandModeType = DSI_CLK_LANE_HSM; - dphyStaticConf.ui_x4 = 0; - /*** To configure the dsi clock and enable the clock lane and data1 lane */ - dsiLinkInit(&dsiLinkConf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - -#ifdef DSI_TPO_DISPLAY - mcde_dsi_tpodisplay_init(info); -#endif -#ifdef DSI_TAAL_DISPLAY - mcde_dsi_taaldisplay_init(info); -#endif - - num=0; - No_Loop=10; - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - pixel_nb = info->var.xres*info->var.yres; - /** The Screen is filled with one color by LP commands, in the next loop the color changes */ - - while(num < No_Loop)//Color Changess in each loop - { - - retVal = dsiHSdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR, PixelRed,PixelGreen, PixelBlue,0,0,0,0,0,0,0,0,0,0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - retVal = dsiHSdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - for (temp=4; temp< (pixel_nb);temp= temp +4) - { - retVal = dsiHSdcslongwrite(VC_ID0, 13, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - } - for (temp=0;temp<1000;temp++);//delay - - if(Field == 1) /** odd field */ - { - Field=0; /** set even field */ - PixelRed = 0xFF; - PixelGreen =0x00; - PixelBlue =0x00; - } - else if(Field == 0) /** even field */ - { - Field=1; /** set odd field */ - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - } - - - num++; - } -return retVal; -} - -#ifdef TESTING -static int mcde_dsi_testbitmap_LP_directcommand_mode(struct fb_info *info,u32 key) -{ - struct dsi_dphy_static_conf dphyStaticConf; - struct dsi_link_conf dsiLinkConf; - struct mcdefb_info *currentpar = info->par; - unsigned int retVal= 0; - int size; - - dsiLinkConf.dsiInterfaceMode = DSI_INTERFACE_NONE; - dsiLinkConf.clockContiniousMode = DSI_CLK_CONTINIOUS_HS_DISABLE; - dsiLinkConf.dsiLinkState = DSI_ENABLE; - dsiLinkConf.clockLaneMode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane1Mode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane2Mode = DSI_LANE_DISABLE; - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dphyStaticConf.clocklaneswappinmode = HS_SWAP_PIN_DISABLE; - dsiLinkConf.commandModeType = DSI_CLK_LANE_LPM; - /*** To configure the dsi clock and enable the clock lane and data1 lane */ - dsiLinkInit(&dsiLinkConf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - - /** INITIALISE DSI(TPO) DISPLAY to run in direct command mode */ -// mcde_dsi_tpodisplay_init(info); -#ifdef DSI_TPO_DISPLAY - mcde_dsi_tpodisplay_init(info); -#endif -#ifdef DSI_TAAL_DISPLAY - mcde_dsi_taaldisplay_init(info); -#endif - retVal = dsiLPdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR, *(pbitmapData + 56),*(pbitmapData+55), *(pbitmapData+54),0,0,0,0,0,0,0,0,0,0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - - for (size=57; size< (230454);size= size +12) - { - retVal = dsiLPdcslongwrite(VC_ID0, 13, TPO_CMD_RAMWR_CONTINUE, - *(pbitmapData + (size+2)),*(pbitmapData +(size + 1)), *(pbitmapData+ (size)), - *(pbitmapData+( size + 5)),*(pbitmapData+(size + 4)),*(pbitmapData+ (size + 3)), - *(pbitmapData+ (size + 8)),*(pbitmapData+ (size+7)),*(pbitmapData+ (size+6)), - *(pbitmapData+ (size+11)),*(pbitmapData+ (size+10)),*(pbitmapData+ (size+9)), - 0,0, 0, currentpar->chid, currentpar->dsi_lnk_no); - } - return retVal; -} -#endif - -int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key) -{ - struct dsi_dphy_static_conf dphyStaticConf; - struct dsi_link_conf dsiLinkConf; - struct mcdefb_info *currentpar = info->par; - //unsigned long flags; - unsigned int retVal= 0; - unsigned int Field = 1; - //int uTimeout = 0xFFFFFFFF; - int num, temp; - int No_Loop; - unsigned char PixelRed; - unsigned char PixelGreen; - unsigned char PixelBlue; - int pixel_nb ; - - dsiLinkConf.dsiInterfaceMode = DSI_INTERFACE_NONE; - dsiLinkConf.clockContiniousMode = DSI_CLK_CONTINIOUS_HS_DISABLE; - dsiLinkConf.dsiLinkState = DSI_ENABLE; - dsiLinkConf.clockLaneMode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane1Mode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane2Mode = DSI_LANE_DISABLE; - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dphyStaticConf.clocklaneswappinmode = HS_SWAP_PIN_DISABLE; - dsiLinkConf.commandModeType = DSI_CLK_LANE_LPM; - dphyStaticConf.ui_x4 = 0; - /*** To configure the dsi clock and enable the clock lane and data1 lane */ - dsiLinkInit(&dsiLinkConf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - - /** INITIALISE DSI(TPO) DISPLAY to run in direct command mode */ - // dsidisplayinitLPcmdmode(currentpar->chid, currentpar->dsi_lnk_no); -// mcde_dsi_tpodisplay_init(info); - -#ifdef DSI_TPO_DISPLAY - mcde_dsi_tpodisplay_init(info); -#endif -#ifdef DSI_TAAL_DISPLAY - mcde_dsi_taaldisplay_init(info); -#endif - dbgprintk(MCDE_DEBUG_INFO, "Writing Pixel For Display to the Display Buffer in LP Command Mode\n"); - - num=0; - No_Loop=10; - - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - pixel_nb = info->var.xres*info->var.yres; - /** The Screen is filled with one color by LP commands, in the next loop the color changes */ - - while(num < No_Loop)//Color Changess in each loop - { - retVal= dsiLPdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR, PixelRed,PixelGreen, PixelBlue,0,0,0,0,0,0,0,0,0,0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - retVal = dsiLPdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - for (temp=4; temp< (pixel_nb);temp= temp +4) - { - retVal = dsiLPdcslongwrite(VC_ID0, 13, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - } - for (temp=0;temp<1000;temp++);//delay - - if(Field == 1) /** odd field */ - { - Field=0; /** set even field */ - PixelRed = 0xFF; - PixelGreen =0x00; - PixelBlue =0x00; - } - else if(Field == 0) /** even field */ - { - Field=1; /** set odd field */ - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - } - num++; - } - return retVal; -} - -void mcde_dsi_taaldisplay_init(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - int timeout; - - if(currentpar->chid==MCDE_CH_C0) { - //currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl|=0x380; - - /* Link enable */ - printk(KERN_ERR "mctl_main_data_ctl\n"); - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_phy_ctl=0x5; - - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl|=0x380; - - /* PLL start */ - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_en=0x438; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_pll_ctl=0x00000001;//0x10000; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_en=0x439; - - /* wait for lanes ready */ - timeout=0xFFFF; - while(!((currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_sts) & 0xE) && (timeout > 0)) - { - timeout--; - } - if(timeout == 0) { - printk(KERN_INFO "DSI CLK LANE DAT1 DAT2 NOT READY\n"); - } - else { - printk(KERN_INFO "DSI CLK LANE DAT1 DAT2 READY %x\n", timeout); - } - - currentpar->dsi_lnk_registers[DSI_LINK0]->cmd_mode_ctl=0x3FF0040; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_dphy_static=0x300;//0x3c0; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_dphy_timeout=0xffffffff; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_ulpout_time=0x201; - - mdelay(100); - - - /** send DSI commands to make display up */ - - /** Reset display (SW reset) */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x01; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - mdelay(200); - - /** make the display up ~ send commands */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x11; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(150); /** sleep for 150 ms */ - - /** send teaing command with low power mode */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x35; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); - - /** send color mode */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0xf73a; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); - - /** send power on command */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0xF729; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); /** check for display to up ok ~ primary display */ - - dbgprintk(MCDE_ERROR_INFO, "\n>> TAAL Display Initialisation done DSI_LINK0\n\n\n"); - } - - if(currentpar->chid==MCDE_CH_C1) { -#if 0 - if(currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en!=0x9) { - mcde_dsi_clk=(u32 *) ioremap(0xA0350EF0, (0xA0350EF0+3)-0xA0350EF0 + 1); - *mcde_dsi_clk =0xA1010C; - iounmap(mcde_dsi_clk); - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_data_ctl |=0x1; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_phy_ctl|=0x1; -#ifndef CONFIG_FB_MCDE_MULTIBUFFER - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl |=0x104A0;//0x104A2; -#else - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl |=0x1049E;//0x104A2; -#endif - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en |=0x9; - } - - mdelay(100); -#endif - - /* Link enable */ - printk(KERN_ERR "mctl_main_data_ctl\n"); - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_phy_ctl=0x5; - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl|=0x380; - - /* PLL start */ - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x438; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_pll_ctl=0x00000001;//0x10000; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x439; - - /* wait for lanes ready */ - timeout=0xFFFF; - while(!((currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_sts) & 0xE) && (timeout > 0)) - { - timeout--; - } - if(timeout == 0) { - printk(KERN_INFO "DSI CLK LANE DAT1 DAT2 NOT READY\n"); - } - else { - printk(KERN_INFO "DSI CLK LANE DAT1 DAT2 READY %x\n", timeout); - } - - currentpar->dsi_lnk_registers[DSI_LINK1]->cmd_mode_ctl=0x3FF0040; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_static=0x300;//0x3c0; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_timeout=0xffffffff; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_ulpout_time=0x201; - - mdelay(100); - - - /** send DSI commands to make display up */ - - /** Reset display (SW reset) */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x01; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - mdelay(200); - - /** make the display up ~ send commands */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x11; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(150); /** sleep for 150 ms */ - - /** send teaing command with low power mode */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x35; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - /** send color mode */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xf73a; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - /** send power on command */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xF729; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); /** check for display to up ok ~ secondary display */ - -#if 0 -/* old code begin */ - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl|=0x380; - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_phy_ctl=0x5; - - //currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl|=0x380;//0x380; - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x438; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_pll_ctl=0x10000; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x439; - - mdelay(100); /** check for pll lock */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->cmd_mode_ctl=0x3FF0040; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_static=0x3c0; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_timeout=0xffffffff; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_ulpout_time=0x201; - - mdelay(100); - - /** make the display up ~ send commands */ - - /** sleep on */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x11; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(150); /** sleep for 150 ms */ - - /** send teaing command with low power mode */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x35; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - /** send color mode */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xf73a; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xF729; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); /** check for display to up ok ~ secondary display */ -#endif -/* old code end */ - - dbgprintk(MCDE_ERROR_INFO, "\n>> TAAL Display Initialisation done DSI_LINK1\n\n\n"); - } -} - - -void mcde_dsi_tpodisplay_init(struct fb_info *info) -{ - u32 ret_val; - int i; - struct mcdefb_info *currentpar = info->par; - - dbgprintk(MCDE_ERROR_INFO, "\n\n\n////////////////////////////////////////////////////////////\n") ; - dbgprintk(MCDE_ERROR_INFO, "// TPO screen startup procedure //\n") ; - dbgprintk(MCDE_ERROR_INFO, "////////////////////////////////////////////////////////////\n") ; - - /* - *! Settings for Gamma corrections and seletions - */ - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E0,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E1,0x110F092B,0x035030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E2,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E3,0x110F092B,0x35030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E4,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E5,0x110F092B,0x035030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000001EA,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* - *! Display Settings for initialization - */ - - /* sending the direct command -- This is Key packet */ - dbgprintk(MCDE_ERROR_INFO, "\n## Key packet\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x04,0x6455AAF6,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display Interface Mode\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000000B0,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## LTPS Function 3\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x00004CBC,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display function setting\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000008B7,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Color Mode\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x0000F73A,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Memory data access control\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x0000C036,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display Inversion ON\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000021,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Sleep Out\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000011,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - dbgprintk(MCDE_ERROR_INFO, "\n## Delay loop\n") ; - for (i=0; i<100000; i++); - - - /* sending the direct command DISPON*/ - dbgprintk(MCDE_ERROR_INFO, "\n## Display ON\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000029,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - - dbgprintk(MCDE_ERROR_INFO, "\n>> TPO Dispaly Initialisation done\n\n\n"); - -} - - -int mcde_dsi_start(struct fb_info *info) -{ - - unsigned int retVal= 0; - -#ifdef PEPS_PLATFORM - struct dsi_dphy_static_conf dphyStaticConf; - struct mcdefb_info *currentpar = info->par; - dsi_dphy_timeout timeout; - u16 clkulptimeout = 0; - u16 dataulptimeout = 0; -#endif - -#ifdef PEPS_PLATFORM - if (currentpar->dsi_lnk_context.if_mode_type == DSI_CLK_LANE_HSM) - { - timeout.lp_rx_timeout = 0xFFFF; - timeout.hs_tx_timeout = 0xFFFF; - timeout.clk_div = 0xF; - dphyStaticConf.ui_x4 = 12; - clkulptimeout = 0xff; - dataulptimeout = 0xff; - } else if (currentpar->dsi_lnk_context.if_mode_type == DSI_CLK_LANE_LPM) - { - timeout.lp_rx_timeout = 0xFFF1; - timeout.hs_tx_timeout = 0x3FFF; - timeout.clk_div = 0xF; - dphyStaticConf.ui_x4 = 0; - clkulptimeout = 0; - dataulptimeout = 0; - } - - dsisetDPHYtimeout(currentpar->dsi_lnk_no, currentpar->chid, timeout); - dsisetlaneULPwaittime(currentpar->dsi_lnk_no, currentpar->chid, DSI_CLK_LANE, clkulptimeout); - dsisetlaneULPwaittime(currentpar->dsi_lnk_no, currentpar->chid, DSI_DATA_LANE1, clkulptimeout); - - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dphyStaticConf.clocklaneswappinmode = HS_SWAP_PIN_DISABLE; - - // To configure the dsi clock and enable the clock lane and data1 lane - dsiLinkInit(¤tpar->dsi_lnk_conf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - // configure link 3 - if (currentpar->dsi_lnk_context.if_mode_type == DSI_CLK_LANE_HSM) - { - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_data_ctl = 0x1 ; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl = 0x104a0; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en = 0x9; - } else if (currentpar->dsi_lnk_context.if_mode_type == DSI_CLK_LANE_LPM) - { - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_data_ctl = 0x1; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl = 0x800; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en = 0x1; - } -#endif - -#ifdef PEPS_PLATFORM - address = (u32 *)currentpar->dsi_lnk_registers[0]; - *(address + 0x280) = 0x14080C00; - *(address + 0x281) = 0xA8800240; - *(address + 0x282) = 0x041000AA; - *(address + 0x283) = 0x00000024; - *(address + 0x28A) = 0x00000700; - *(address + 0x291) = 0x0000E002; - *(address + 0x294) = 0x1; -#endif - -/** INITIALISE DSI(TPO/TAAL) DISPLAY to run in command mode */ -#ifdef DSI_TPO_DISPLAY - mcde_dsi_tpodisplay_init(info); -#endif -#ifdef DSI_TAAL_DISPLAY - mcde_dsi_taaldisplay_init(info); -#endif - - return retVal; -} - -int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value) -{ - struct mcdefb_info *currentpar = info->par; - int ret = -EINVAL; - int wait = 10; - int link; - - *value = 0xFFFFFFFF; - - if (currentpar->chid == CHANNEL_C0) - link = DSI_LINK0; - else if (currentpar->chid == CHANNEL_C1) - link = DSI_LINK1; - else - return -EINVAL; - - /* Enable BTA */ - currentpar->dsi_lnk_registers[link]->mctl_main_data_ctl |= 0x380; - - /* Send register to read */ - currentpar->dsi_lnk_registers[link]->direct_cmd_main_settings = 0x10601; - currentpar->dsi_lnk_registers[link]->direct_cmd_wrdat0 = (u8) reg; - currentpar->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x7FF; - currentpar->dsi_lnk_registers[link]->direct_cmd_send = 0x1; - - /* Wait for read to complete */ - wait = 10; - while (wait-- && (currentpar->dsi_lnk_registers[link]->direct_cmd_sts & 0x408) == 0) - mdelay(10); - - if ((currentpar->dsi_lnk_registers[link]->direct_cmd_sts & 0x408) != 8) { - printk(KERN_INFO "%s: Failed to read reg %X, " - "cmd_sts = %X, cmd_rd_sts = %X, rddat=%X\n", - __func__, - reg, - currentpar->dsi_lnk_registers[link]->direct_cmd_sts, - currentpar->dsi_lnk_registers[link]->direct_cmd_rd_sts, - currentpar->dsi_lnk_registers[link]->direct_cmd_rddat); - } - else { - *value = currentpar->dsi_lnk_registers[link]->direct_cmd_rddat; - ret = 0; - } - - /* Disable BTA */ - currentpar->dsi_lnk_registers[link]->mctl_main_data_ctl &= ~0x380; - currentpar->dsi_lnk_registers[link]->direct_cmd_sts_clr = 0x7FF; - - return ret; -} - -int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value) -{ - struct mcdefb_info *currentpar = info->par; - int wait = 10; - int ret = 0; - int link; - - if (currentpar->chid == CHANNEL_C0) - link = DSI_LINK0; - else if (currentpar->chid == CHANNEL_C1) - link = DSI_LINK1; - else - return -EINVAL; - - currentpar->dsi_lnk_registers[link]-> - direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_wrdat0= (((u8) value) << 8) | (u8) reg; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts_clr = 0x7FF; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_send=0x1; - - /* Wait for write to complete */ - while (wait-- && (currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts & 0x2) == 0) - mdelay(10); - if ((currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts & 0x2) != 0x2) { - printk(KERN_INFO "%s: Failed to write reg %X, " - "cmd_sts = %X, value = %X\n", - __func__, - reg, - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts, - value); - ret = -EINVAL; - } - - return ret; -} - - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ -/* HW ED */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <mach/mcde_common.h> - -extern struct mcdefb_info *gpar[]; -#ifdef TESTING -char * pbitmapData; /** to be removed */ -#endif - - -dsi_error dsiPllConf(dsi_pll_ctl pll_ctl, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - u32 waitTimeout = 0xFFFFFFFF; - u8 pll_sts; - - /** Clock Selection and enabling */ - dsisetPLLcontrol(link, chid, pll_ctl); - dsisetPLLmode(link, chid, DSI_PLL_START); - - /** Wait Till pll LOCKS */ - waitTimeout = 0xFFFF; - dsigetlinkstatus(link, chid, &pll_sts); - while ( !(pll_sts & DSI_PLL_LOCK) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &pll_sts); - } - if (waitTimeout == 0) - { - dbgprintk(MCDE_ERROR_INFO, "dsiPLLconf:PLL lOCK FAILED!!!!\n"); - retVal = DSI_PLL_PROGRAM_ERROR; - } - return retVal; -} -dsi_error dsiLinkConf (struct dsi_link_conf *pdsiLinkConf, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - dsi_interface dsiInterface; - dsi_if_state dsiInterfaceState; /** interface enable/disable */ - dsi_te_en tearing; - switch (pdsiLinkConf->dsiInterfaceMode) - { - case DSI_VIDEO_MODE: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_VIDEO_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->videoModeType, dsiInterface); - break; - case DSI_COMMAND_MODE: - if (pdsiLinkConf->dsiInterface == DSI_INTERFACE_1) - { - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_COMMAND_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - }else - { - dsiInterface = DSI_INTERFACE_2; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - } - break; - case DSI_INTERFACE_BOTH: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_ENABLE; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface1 mode (VideoMode/Command mode */ - retVal = dsisetInterface1mode(link, DSI_VIDEO_MODE, chid); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->videoModeType, dsiInterface); - - dsiInterface = DSI_INTERFACE_2; - /** enable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - /** set the interface in LP/HS mode */ - dsisetInterfaceInLpm(link, chid, pdsiLinkConf->commandModeType, dsiInterface); - break; - case DSI_INTERFACE_NONE: - dsiInterface = DSI_INTERFACE_1; - dsiInterfaceState = DSI_IF_DISABLE; - /** disable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - dsiInterface = DSI_INTERFACE_2; - /** disable the interface */ - retVal = dsisetInterface(link, chid, dsiInterfaceState, dsiInterface); - - break; - default: - retVal = DSI_INVALID_PARAMETER; - break; - } - - /** configuring the TE values for If1 */ - tearing.te_sel = DSI_IF_TE; - tearing.interface = DSI_INTERFACE_1; - dsisetTE(link, tearing, pdsiLinkConf->if1TeCtrl, chid); - - /** configuring the TE values for If2 */ - tearing.te_sel = DSI_IF_TE; - tearing.interface = DSI_INTERFACE_2; - dsisetTE(link, tearing, pdsiLinkConf->if2TeCtrl, chid); - - /** configuring the TE values for reg type */ - tearing.te_sel = DSI_REG_TE; - dsisetTE(link, tearing, pdsiLinkConf->regTeCtrl, chid); - - /** configuring read,BTA,EOTGen,HostEOTGen,CheckSumGen,Continious clock and padding values */ - dsireadset(link, pdsiLinkConf->rdCtrl, chid); - dsisetBTAmode(link, pdsiLinkConf->btaMode, chid); - dsisetdispEOTGenmode(link, pdsiLinkConf->displayEotGenMode, chid); - dsisetdispHOSTEOTGenmode(link, pdsiLinkConf->hostEotGenMode, chid); - dsisetdispCHKSUMGenmode(link, pdsiLinkConf->dispChecksumGenMode, chid); - dsisetdispECCGenmode(link, pdsiLinkConf->dispEccGenMode, chid); - dsisetCLKHSsendingmode(link, pdsiLinkConf->clockContiniousMode, chid); - dsisetpaddingval(link, chid, pdsiLinkConf->paddingValue); - - return retVal; -} -dsi_error dsiLinkEnable (struct dsi_link_conf *pdsiLinkConf, mcde_ch_id chid, dsi_link link) -{ - dsi_error retVal = DSI_OK; - u32 waitTimeout = 0xFFFFFFFF; - u8 link_sts; - - /** Enable the DSI link, Link Clock and the Data Lane */ - dsisetlinkstate(link, pdsiLinkConf->dsiLinkState, chid); - dsisetlanestate(link, chid, pdsiLinkConf->clockLaneMode, DSI_CLK_LANE); - dsisetlanestate(link, chid, pdsiLinkConf->dataLane1Mode, DSI_DATA_LANE1); - - if (pdsiLinkConf->clockLaneMode == DSI_LANE_ENABLE) - { - /** Wait Till clock lane are ready */ - waitTimeout = 0xFFFFFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_CLKLANE_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_CLOCK_LANE_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Clock Lane not ready :...... FAILED!!!!\n"); - } - } - /** Wait Till data1 lane are ready */ - if (pdsiLinkConf->clockLaneMode == DSI_LANE_ENABLE) - { - waitTimeout = 0xFFFFFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_DAT1_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_DATA_LANE1_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Data Lane1 not ready :...... FAILED!!!!\n"); - } - } - if(pdsiLinkConf->dataLane2Mode == DSI_LANE_ENABLE) - { - dsisetlanestate(link, chid, pdsiLinkConf->dataLane2Mode, DSI_DATA_LANE2); - /*************** Wait Till DATA1 lane are ready ********/ - //waitTimeout = 0xFFFF; - dsigetlinkstatus(link, chid, &link_sts); - while ( !(link_sts & DSI_DAT2_READY) && (waitTimeout > 0) ) - { - waitTimeout-- ; - dsigetlinkstatus(link, chid, &link_sts); - } - if (waitTimeout == 0) - { - retVal = DSI_DATA_LANE2_NOT_READY; - dbgprintk(MCDE_ERROR_INFO, "dsiLinkConf:DSI Data Lane2 not ready :...... FAILED!!!!\n"); - } - } - return retVal; -} - -u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link) -{ - dsi_pll_ctl pll_ctl; - - pll_ctl.multiplier = 0x0; - pll_ctl.division_ratio = 0x0; - - pll_ctl.pll_in_sel = DSI_PLL_IN_CLK_27; - - if (pdsiLinkConf->commandModeType == DSI_CLK_LANE_HSM || pdsiLinkConf->videoModeType == DSI_CLK_LANE_HSM) - { - pll_ctl.pll_master = DSI_PLL_SLAVE; - pll_ctl.pll_out_sel = DSI_INTERNAL_PLL; - } - else - { - pll_ctl.pll_master = DSI_PLL_MASTER; - pll_ctl.pll_out_sel = DSI_SYSTEM_PLL; - } - - /*Main enable-start enable*/ - dsiLinkConf (pdsiLinkConf,chid, link); - dsiLinkEnable (pdsiLinkConf, chid, link); - - dsiset_hs_clock(link, dphyStaticConf, chid); - dsiPllConf(pll_ctl, chid, link); - - return(0); - -} - -/** - Initialization of TPO Display using LP mode and DSI direct command registor & dispaly of two alternating color - */ -int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key) -{ - struct dsi_dphy_static_conf dphyStaticConf; - struct dsi_link_conf dsiLinkConf; - struct mcdefb_info *currentpar = info->par; - unsigned int retVal= 0; - unsigned int Field = 1; - int num, temp; - int No_Loop; - unsigned char PixelRed; - unsigned char PixelGreen; - unsigned char PixelBlue; - int pixel_nb ; - - - dsiLinkConf.dsiInterfaceMode = DSI_INTERFACE_NONE; - dsiLinkConf.clockContiniousMode = DSI_CLK_CONTINIOUS_HS_DISABLE; - dsiLinkConf.dsiLinkState = DSI_ENABLE; - dsiLinkConf.clockLaneMode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane1Mode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane2Mode = DSI_LANE_DISABLE; - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dsiLinkConf.commandModeType = DSI_CLK_LANE_HSM; - dphyStaticConf.ui_x4 = 0; - /*** To configure the dsi clock and enable the clock lane and data1 lane */ - dsiLinkInit(&dsiLinkConf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - - mcde_dsi_taaldisplay_init(info); - - num=0; - No_Loop=10; - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - pixel_nb = info->var.xres*info->var.yres; - /** The Screen is filled with one color by LP commands, in the next loop the color changes */ - - while(num < No_Loop)//Color Changess in each loop - { - - retVal = dsiHSdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR, PixelRed,PixelGreen, PixelBlue,0,0,0,0,0,0,0,0,0,0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - retVal = dsiHSdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - for (temp=4; temp< (pixel_nb);temp= temp +4) - { - retVal = dsiHSdcslongwrite(VC_ID0, 13, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - } - for (temp=0;temp<1000;temp++);//delay - - if(Field == 1) /** odd field */ - { - Field=0; /** set even field */ - PixelRed = 0xFF; - PixelGreen =0x00; - PixelBlue =0x00; - } - else if(Field == 0) /** even field */ - { - Field=1; /** set odd field */ - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - } - - - num++; - } -return retVal; -} - -int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key) -{ - struct dsi_dphy_static_conf dphyStaticConf; - struct dsi_link_conf dsiLinkConf; - struct mcdefb_info *currentpar = info->par; - //unsigned long flags; - unsigned int retVal= 0; - unsigned int Field = 1; - //int uTimeout = 0xFFFFFFFF; - int num, temp; - int No_Loop; - unsigned char PixelRed; - unsigned char PixelGreen; - unsigned char PixelBlue; - int pixel_nb ; - - dsiLinkConf.dsiInterfaceMode = DSI_INTERFACE_NONE; - dsiLinkConf.clockContiniousMode = DSI_CLK_CONTINIOUS_HS_DISABLE; - dsiLinkConf.dsiLinkState = DSI_ENABLE; - dsiLinkConf.clockLaneMode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane1Mode = DSI_LANE_ENABLE; - dsiLinkConf.dataLane2Mode = DSI_LANE_DISABLE; - dphyStaticConf.datalane1swappinmode = HS_SWAP_PIN_DISABLE; - dphyStaticConf.clocklaneswappinmode = HS_SWAP_PIN_DISABLE; - dsiLinkConf.commandModeType = DSI_CLK_LANE_LPM; - dphyStaticConf.ui_x4 = 0; - /*** To configure the dsi clock and enable the clock lane and data1 lane */ - dsiLinkInit(&dsiLinkConf, dphyStaticConf, currentpar->chid, currentpar->dsi_lnk_no); - - /** INITIALISE DSI(TPO) DISPLAY to run in direct command mode */ - // dsidisplayinitLPcmdmode(currentpar->chid, currentpar->dsi_lnk_no); -// mcde_dsi_tpodisplay_init(info); - - mcde_dsi_taaldisplay_init(info); - dbgprintk(MCDE_DEBUG_INFO, "Writing Pixel For Display to the Display Buffer in LP Command Mode\n"); - - num=0; - No_Loop=10; - - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - pixel_nb = info->var.xres*info->var.yres; - /** The Screen is filled with one color by LP commands, in the next loop the color changes */ - - while(num < No_Loop)//Color Changess in each loop - { - retVal= dsiLPdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR, PixelRed,PixelGreen, PixelBlue,0,0,0,0,0,0,0,0,0,0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - retVal = dsiLPdcslongwrite(VC_ID0, 4, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - for (temp=4; temp< (pixel_nb);temp= temp +4) - { - retVal = dsiLPdcslongwrite(VC_ID0, 13, TPO_CMD_RAMWR_CONTINUE, PixelRed,PixelGreen, PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed, PixelGreen,PixelBlue, - PixelRed,PixelGreen,PixelBlue, - 0,0,0, currentpar->chid, currentpar->dsi_lnk_no); - } - for (temp=0;temp<1000;temp++);//delay - - if(Field == 1) /** odd field */ - { - Field=0; /** set even field */ - PixelRed = 0xFF; - PixelGreen =0x00; - PixelBlue =0x00; - } - else if(Field == 0) /** even field */ - { - Field=1; /** set odd field */ - PixelRed=0x00; - PixelGreen=0xFF; - PixelBlue=0x00; - } - num++; - } - return retVal; -} - -void mcde_dsi_taaldisplay_init(struct fb_info *info) -{ - //u32 ret_val; - struct mcdefb_info *currentpar = info->par; - - volatile u32 __iomem *mcde_dsi_clk; - - if(currentpar->chid==MCDE_CH_C0) - - { - - //currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl|=0x380; - - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_phy_ctl=0x5; - - //currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_data_ctl|=0x380; - - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_en=0x438; - - mdelay(100); - - - /** mcde dsi clock */ - mcde_dsi_clk=(u32 *) ioremap(0xA0350EF0, (0xA0350EF0+3)-0xA0350EF0 + 1); - *mcde_dsi_clk=0xA1010C; - iounmap(mcde_dsi_clk); - - mdelay(100); - - - /** configure DSI link2 which is having plls */ - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_phy_ctl=0x1; - -#ifndef CONFIG_FB_MCDE_MULTIBUFFER - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl=0x104A0;//0x104A2; -#else - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl=0x1049E;//0x104A2; - -#endif - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en=0x9; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_pll_ctl=0x10000; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_main_en=0x439; - - mdelay(100); /** check for pll lock */ - - currentpar->dsi_lnk_registers[DSI_LINK0]->cmd_mode_ctl=0x3FF0040; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_dphy_static=0x3c0; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_dphy_timeout=0xffffffff; - currentpar->dsi_lnk_registers[DSI_LINK0]->mctl_ulpout_time=0x201; - - mdelay(100); - - - /** send DSI commands to make display up */ - - /** Reset display (SW reset) */ - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x01; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - mdelay(200); - - /** make the display up ~ send commands */ - - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x11; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(150); /** sleep for 150 ms */ - - - /** send teaing command with low power mode */ - - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0x35; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); - - /** send color mode */ - - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0xf73a; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); - - /** send power on command */ - - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_wrdat0=0xF729; - currentpar->dsi_lnk_registers[DSI_LINK0]->direct_cmd_send=0x1; - - mdelay(100); /** check for display to up ok ~ primary display */ - - } - - - if(currentpar->chid==MCDE_CH_C1) - { - - - if(currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en!=0x9) - { - mcde_dsi_clk=(u32 *) ioremap(0xA0350EF0, (0xA0350EF0+3)-0xA0350EF0 + 1); - *mcde_dsi_clk =0xA1010C; - iounmap(mcde_dsi_clk); - - mdelay(100); - - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_data_ctl |=0x1; - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_phy_ctl|=0x1; -#ifndef CONFIG_FB_MCDE_MULTIBUFFER - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl |=0x104A0;//0x104A2; -#else - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_pll_ctl |=0x1049E;//0x104A2; -#endif - - currentpar->dsi_lnk_registers[DSI_LINK2]->mctl_main_en |=0x9; - } - - mdelay(100); - - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl|=0x380; - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl=0x1; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_phy_ctl=0x5; - - //currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_data_ctl|=0x380;//0x380; - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x438; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_pll_ctl=0x10000; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_main_en=0x439; - - mdelay(100); /** check for pll lock */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->cmd_mode_ctl=0x3FF0040; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_static=0x3c0; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_dphy_timeout=0xffffffff; - currentpar->dsi_lnk_registers[DSI_LINK1]->mctl_ulpout_time=0x201; - - mdelay(100); - - /** make the display up ~ send commands */ - - /** sleep on */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x11; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(150); /** sleep for 150 ms */ - - /** send teaing command with low power mode */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x35; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - -#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT - - /* LP, size=2 */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - /* Rotate 270 degrees */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xA036; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - /* LP, size=5 */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x253908; - /* Column Address Set 0-0x1DF (0-479) */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x0100002A; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat1=0x000000DF; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - mdelay(100); - - /* LP, size=5 */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x253908; - /* Page Address Set 0-0x35F (0-863) */ - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0x0300002B; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat1=0x0000005F; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - mdelay(100); -#endif - - /** send color mode */ - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xf73a; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); - - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_main_settings=0x210500; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_wrdat0=0xF729; - currentpar->dsi_lnk_registers[DSI_LINK1]->direct_cmd_send=0x1; - - mdelay(100); /** check for display to up ok ~ secondary display */ - - } - - - dbgprintk(MCDE_ERROR_INFO, "\n>> TAAL Dispaly Initialisation done\n\n\n"); - -} -void mcde_dsi_tpodisplay_init(struct fb_info *info) -{ - u32 ret_val; - int i; - struct mcdefb_info *currentpar = info->par; - - dbgprintk(MCDE_ERROR_INFO, "\n\n\n////////////////////////////////////////////////////////////\n") ; - dbgprintk(MCDE_ERROR_INFO, "// TPO screen startup procedure //\n") ; - dbgprintk(MCDE_ERROR_INFO, "////////////////////////////////////////////////////////////\n") ; - - /* - *! Settings for Gamma corrections and seletions - */ - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E0,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E1,0x110F092B,0x035030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E2,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E3,0x110F092B,0x35030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x010002E4,0x130D0601,0x1B090C0A,0x1426200E,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x10,0x282221E5,0x110F092B,0x035030624,0x3E29220C,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Gamma correction\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000001EA,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* - *! Display Settings for initialization - */ - - /* sending the direct command -- This is Key packet */ - dbgprintk(MCDE_ERROR_INFO, "\n## Key packet\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x39,0x04,0x6455AAF6,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display Interface Mode\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000000B0,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## LTPS Function 3\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x00004CBC,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display function setting\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x000008B7,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Color Mode\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x0000F73A,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Memory data access control\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x15,0x02,0x0000C036,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Display Inversion ON\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000021,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - /* sending the direct command */ - dbgprintk(MCDE_ERROR_INFO, "\n## Sleep Out\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000011,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - dbgprintk(MCDE_ERROR_INFO, "\n## Delay loop\n") ; - for (i=0; i<100000; i++); - - - /* sending the direct command DISPON*/ - dbgprintk(MCDE_ERROR_INFO, "\n## Display ON\n"); - ret_val = dsisenddirectcommand(DSI_CLK_LANE_LPM,0x05,0x01,0x00000029,0x00000000,0x00000000,0x00000000,currentpar->dsi_lnk_no,currentpar->chid); - - - dbgprintk(MCDE_ERROR_INFO, "\n>> TPO Dispaly Initialisation done\n\n\n"); - -} - - -int mcde_dsi_start(struct fb_info *info) -{ - - unsigned int retVal= 0; - - mcde_dsi_taaldisplay_init(info); - - return retVal; -} - -int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value) -{ - struct mcdefb_info *currentpar = info->par; - int ret = -EINVAL; - int wait = 10; - int link; - - *value = 0xFFFFFFFF; - - if (currentpar->chid == CHANNEL_C0) - link = DSI_LINK0; - else if (currentpar->chid == CHANNEL_C1) - link = DSI_LINK1; - else - return -EINVAL; - - /* Enable BTA */ - currentpar->dsi_lnk_registers[link]-> - mctl_main_data_ctl|=0x380; - - /* Send register to read */ - currentpar->dsi_lnk_registers[link]-> - direct_cmd_main_settings=0x10601; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_wrdat0= (u8) reg; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts_clr = 0x7FF; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_send=0x1; - - - /* Wait for read to complete */ - wait = 10; - while (wait-- && (currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts & 0x408) == 0) - mdelay(10); - - if ((currentpar->dsi_lnk_registers[link]->direct_cmd_sts & - 0x408) != 8) { - printk(KERN_INFO "%s: Failed to read reg %X, " - "cmd_sts = %X, cmd_rd_sts = %X, rddat=%X\n", - __func__, - reg, - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts, - currentpar->dsi_lnk_registers[link]-> - direct_cmd_rd_sts, - currentpar->dsi_lnk_registers[link]-> - direct_cmd_rddat); - } - else { - *value = currentpar->dsi_lnk_registers[link]-> - direct_cmd_rddat; - ret = 0; - } - - /* Disable BTA */ - currentpar->dsi_lnk_registers[link]-> - mctl_main_data_ctl&=~0x380; - - return ret; -} - -int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value) -{ - struct mcdefb_info *currentpar = info->par; - int wait = 10; - int ret = 0; - int link; - - if (currentpar->chid == CHANNEL_C0) - link = DSI_LINK0; - else if (currentpar->chid == CHANNEL_C1) - link = DSI_LINK1; - else - return -EINVAL; - - currentpar->dsi_lnk_registers[link]-> - direct_cmd_main_settings=0x221500; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_wrdat0= (((u8) value) << 8) | (u8) reg; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts_clr = 0x7FF; - currentpar->dsi_lnk_registers[link]-> - direct_cmd_send=0x1; - - /* Wait for write to complete */ - while (wait-- && (currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts & 0x2) == 0) - mdelay(10); - if ((currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts & 0x2) != 0x2) { - printk(KERN_INFO "%s: Failed to write reg %X, " - "cmd_sts = %X, value = %X\n", - __func__, - reg, - currentpar->dsi_lnk_registers[link]-> - direct_cmd_sts, - value); - ret = -EINVAL; - } - - return ret; -} - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ diff --git a/drivers/video/mcde/dsilink_regs.h b/drivers/video/mcde/dsilink_regs.h new file mode 100644 index 00000000000..b5d5bd952eb --- /dev/null +++ b/drivers/video/mcde/dsilink_regs.h @@ -0,0 +1,2024 @@ + +#define DSI_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define DSI_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define DSI_MCTL_INTEGRATION_MODE 0x00000000 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_SHIFT 0 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN_MASK 0x00000001 +#define DSI_MCTL_INTEGRATION_MODE_INT_MODE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_INTEGRATION_MODE, INT_MODE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL 0x00000004 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_SHIFT 0 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_DATA_CTL_LINK_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, LINK_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_SHIFT 1 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_MASK 0x00000002 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_CMD 0 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_VID 1 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, \ + DSI_MCTL_MAIN_DATA_CTL_IF1_MODE_##__x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_MODE, __x) +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_SHIFT 2 +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN_MASK 0x00000004 +#define DSI_MCTL_MAIN_DATA_CTL_VID_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, VID_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_SHIFT 3 +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL_MASK 0x00000008 +#define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TVG_SEL, __x) +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_SHIFT 4 +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL_MASK 0x00000010 +#define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, TBG_SEL, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_SHIFT 5 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF1_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_SHIFT 6 +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN_MASK 0x00000040 +#define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, IF2_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_SHIFT 7 +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN_MASK 0x00000080 +#define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_SHIFT 8 +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN_MASK 0x00000100 +#define DSI_MCTL_MAIN_DATA_CTL_READ_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, READ_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_SHIFT 9 +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN_MASK 0x00000200 +#define DSI_MCTL_MAIN_DATA_CTL_BTA_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, BTA_EN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_SHIFT 10 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC_MASK 0x00000400 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_ECC, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_SHIFT 11 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM_MASK 0x00000800 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_GEN_CHECKSUM, __x) +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_SHIFT 12 +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN_MASK 0x00001000 +#define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, HOST_EOT_GEN, __x) +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_SHIFT 13 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN_MASK 0x00002000 +#define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_DATA_CTL, DISP_EOT_GEN, __x) +#define DSI_MCTL_MAIN_PHY_CTL 0x00000008 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_SHIFT 0 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, LANE2_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_SHIFT 1 +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE_MASK 0x00000002 +#define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, FORCE_STOP_MODE, __x) +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_SHIFT 2 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS_MASK 0x00000004 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_CONTINUOUS, __x) +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_SHIFT 3 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, CLK_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_SHIFT 4 +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT1_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_SHIFT 5 +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, DAT2_ULPM_EN, __x) +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT 6 +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0 +#define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_PHY_CTL, WAIT_BURST_TIME, __x) +#define DSI_MCTL_PLL_CTL 0x0000000C +#define DSI_MCTL_PLL_CTL_PLL_MULT_SHIFT 0 +#define DSI_MCTL_PLL_CTL_PLL_MULT_MASK 0x000000FF +#define DSI_MCTL_PLL_CTL_PLL_MULT(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MULT, __x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_SHIFT 8 +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV_MASK 0x00003F00 +#define DSI_MCTL_PLL_CTL_PLL_OUT_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_DIV, __x) +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_SHIFT 14 +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV_MASK 0x0001C000 +#define DSI_MCTL_PLL_CTL_PLL_IN_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_IN_DIV, __x) +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_SHIFT 17 +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2_MASK 0x00020000 +#define DSI_MCTL_PLL_CTL_PLL_SEL_DIV2(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_SEL_DIV2, __x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SHIFT 18 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_MASK 0x00040000 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_INT_PLL 0 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_SYS_PLL 1 +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, \ + DSI_MCTL_PLL_CTL_PLL_OUT_SEL_##__x) +#define DSI_MCTL_PLL_CTL_PLL_OUT_SEL(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_OUT_SEL, __x) +#define DSI_MCTL_PLL_CTL_PLL_MASTER_SHIFT 31 +#define DSI_MCTL_PLL_CTL_PLL_MASTER_MASK 0x80000000 +#define DSI_MCTL_PLL_CTL_PLL_MASTER(__x) \ + DSI_VAL2REG(DSI_MCTL_PLL_CTL, PLL_MASTER, __x) +#define DSI_MCTL_LANE_STS 0x00000010 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_SHIFT 0 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_MASK 0x00000003 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_START 0 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_HS 2 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_CLKLANE_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, \ + DSI_MCTL_LANE_STS_CLKLANE_STATE_##__x) +#define DSI_MCTL_LANE_STS_CLKLANE_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, CLKLANE_STATE, __x) +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_SHIFT 2 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_MASK 0x0000001C +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_START 0 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_WRITE 2 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_READ 4 +#define DSI_MCTL_LANE_STS_DATLANE1_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, \ + DSI_MCTL_LANE_STS_DATLANE1_STATE_##__x) +#define DSI_MCTL_LANE_STS_DATLANE1_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE1_STATE, __x) +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_SHIFT 5 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_MASK 0x00000060 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_START 0 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_IDLE 1 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_WRITE 2 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ULPM 3 +#define DSI_MCTL_LANE_STS_DATLANE2_STATE_ENUM(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, \ + DSI_MCTL_LANE_STS_DATLANE2_STATE_##__x) +#define DSI_MCTL_LANE_STS_DATLANE2_STATE(__x) \ + DSI_VAL2REG(DSI_MCTL_LANE_STS, DATLANE2_STATE, __x) +#define DSI_MCTL_DPHY_TIMEOUT 0x00000014 +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0 +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK 0x0000000F +#define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, CLK_DIV, __x) +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT 4 +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK 0x0003FFF0 +#define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, HSTX_TO_VAL, __x) +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT 18 +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK 0xFFFC0000 +#define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_TIMEOUT, LPRX_TO_VAL, __x) +#define DSI_MCTL_ULPOUT_TIME 0x00000018 +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT 0 +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK 0x000001FF +#define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, CKLANE_ULPOUT_TIME, __x) +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT 9 +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK 0x0003FE00 +#define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(__x) \ + DSI_VAL2REG(DSI_MCTL_ULPOUT_TIME, DATA_ULPOUT_TIME, __x) +#define DSI_MCTL_DPHY_STATIC 0x0000001C +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK_MASK 0x00000001 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_CLK, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK_MASK 0x00000002 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_CLK, __x) +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1_MASK 0x00000004 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT1, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1_MASK 0x00000008 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT1, __x) +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2_MASK 0x00000010 +#define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, SWAP_PINS_DAT2, __x) +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2_MASK 0x00000020 +#define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, HS_INVERT_DAT2, __x) +#define DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT 6 +#define DSI_MCTL_DPHY_STATIC_UI_X4_MASK 0x00000FC0 +#define DSI_MCTL_DPHY_STATIC_UI_X4(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_STATIC, UI_X4, __x) +#define DSI_MCTL_MAIN_EN 0x00000020 +#define DSI_MCTL_MAIN_EN_PLL_START_SHIFT 0 +#define DSI_MCTL_MAIN_EN_PLL_START_MASK 0x00000001 +#define DSI_MCTL_MAIN_EN_PLL_START(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, PLL_START, __x) +#define DSI_MCTL_MAIN_EN_CKLANE_EN_SHIFT 3 +#define DSI_MCTL_MAIN_EN_CKLANE_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_EN_CKLANE_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, CKLANE_EN, __x) +#define DSI_MCTL_MAIN_EN_DAT1_EN_SHIFT 4 +#define DSI_MCTL_MAIN_EN_DAT1_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_EN_DAT1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_EN, __x) +#define DSI_MCTL_MAIN_EN_DAT2_EN_SHIFT 5 +#define DSI_MCTL_MAIN_EN_DAT2_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_EN_DAT2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_EN, __x) +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_SHIFT 6 +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ_MASK 0x00000040 +#define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, CLKLANE_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_SHIFT 7 +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ_MASK 0x00000080 +#define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT1_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_SHIFT 8 +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ_MASK 0x00000100 +#define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, DAT2_ULPM_REQ, __x) +#define DSI_MCTL_MAIN_EN_IF1_EN_SHIFT 9 +#define DSI_MCTL_MAIN_EN_IF1_EN_MASK 0x00000200 +#define DSI_MCTL_MAIN_EN_IF1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF1_EN, __x) +#define DSI_MCTL_MAIN_EN_IF2_EN_SHIFT 10 +#define DSI_MCTL_MAIN_EN_IF2_EN_MASK 0x00000400 +#define DSI_MCTL_MAIN_EN_IF2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_EN, IF2_EN, __x) +#define DSI_MCTL_MAIN_STS 0x00000024 +#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0 +#define DSI_MCTL_MAIN_STS_PLL_LOCK_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_PLL_LOCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, PLL_LOCK, __x) +#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CLKLANE_READY_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CLKLANE_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, CLKLANE_READY, __x) +#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2 +#define DSI_MCTL_MAIN_STS_DAT1_READY_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_DAT1_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT1_READY, __x) +#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3 +#define DSI_MCTL_MAIN_STS_DAT2_READY_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_DAT2_READY(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, DAT2_READY, __x) +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4 +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, HSTX_TO_ERR, __x) +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5 +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, LPRX_TO_ERR, __x) +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, CRS_UNTERM_PCK, __x) +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7 +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS, VRS_UNTERM_PCK, __x) +#define DSI_MCTL_DPHY_ERR 0x00000028 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_ERR_ESC_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_ESC_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_ERR_SYNCESC_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_SYNCESC_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_ERR_CONTROL_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONTROL_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP0_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP0_2, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_1(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_1, __x) +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_ERR_CONT_LP1_2(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR, ERR_CONT_LP1_2, __x) +#define DSI_INT_VID_RDDATA 0x00000030 +#define DSI_INT_VID_RDDATA_IF_DATA_SHIFT 0 +#define DSI_INT_VID_RDDATA_IF_DATA_MASK 0x0000FFFF +#define DSI_INT_VID_RDDATA_IF_DATA(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_DATA, __x) +#define DSI_INT_VID_RDDATA_IF_VALID_SHIFT 16 +#define DSI_INT_VID_RDDATA_IF_VALID_MASK 0x00010000 +#define DSI_INT_VID_RDDATA_IF_VALID(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_VALID, __x) +#define DSI_INT_VID_RDDATA_IF_START_SHIFT 17 +#define DSI_INT_VID_RDDATA_IF_START_MASK 0x00020000 +#define DSI_INT_VID_RDDATA_IF_START(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_START, __x) +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_SHIFT 18 +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC_MASK 0x00040000 +#define DSI_INT_VID_RDDATA_IF_FRAME_SYNC(__x) \ + DSI_VAL2REG(DSI_INT_VID_RDDATA, IF_FRAME_SYNC, __x) +#define DSI_INT_VID_GNT 0x00000034 +#define DSI_INT_VID_GNT_IF_STALL_SHIFT 0 +#define DSI_INT_VID_GNT_IF_STALL_MASK 0x00000001 +#define DSI_INT_VID_GNT_IF_STALL(__x) \ + DSI_VAL2REG(DSI_INT_VID_GNT, IF_STALL, __x) +#define DSI_INT_CMD_RDDATA 0x00000038 +#define DSI_INT_CMD_RDDATA_IF_DATA_SHIFT 0 +#define DSI_INT_CMD_RDDATA_IF_DATA_MASK 0x0000FFFF +#define DSI_INT_CMD_RDDATA_IF_DATA(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_DATA, __x) +#define DSI_INT_CMD_RDDATA_IF_VALID_SHIFT 16 +#define DSI_INT_CMD_RDDATA_IF_VALID_MASK 0x00010000 +#define DSI_INT_CMD_RDDATA_IF_VALID(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_VALID, __x) +#define DSI_INT_CMD_RDDATA_IF_START_SHIFT 17 +#define DSI_INT_CMD_RDDATA_IF_START_MASK 0x00020000 +#define DSI_INT_CMD_RDDATA_IF_START(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_START, __x) +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_SHIFT 18 +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC_MASK 0x00040000 +#define DSI_INT_CMD_RDDATA_IF_FRAME_SYNC(__x) \ + DSI_VAL2REG(DSI_INT_CMD_RDDATA, IF_FRAME_SYNC, __x) +#define DSI_INT_CMD_GNT 0x0000003C +#define DSI_INT_CMD_GNT_IF_STALL_SHIFT 0 +#define DSI_INT_CMD_GNT_IF_STALL_MASK 0x00000001 +#define DSI_INT_CMD_GNT_IF_STALL(__x) \ + DSI_VAL2REG(DSI_INT_CMD_GNT, IF_STALL, __x) +#define DSI_INT_INTERRUPT_CTL 0x00000040 +#define DSI_INT_INTERRUPT_CTL_INT_VAL_SHIFT 0 +#define DSI_INT_INTERRUPT_CTL_INT_VAL_MASK 0x00000001 +#define DSI_INT_INTERRUPT_CTL_INT_VAL(__x) \ + DSI_VAL2REG(DSI_INT_INTERRUPT_CTL, INT_VAL, __x) +#define DSI_CMD_MODE_CTL 0x00000050 +#define DSI_CMD_MODE_CTL_IF1_ID_SHIFT 0 +#define DSI_CMD_MODE_CTL_IF1_ID_MASK 0x00000003 +#define DSI_CMD_MODE_CTL_IF1_ID(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_ID, __x) +#define DSI_CMD_MODE_CTL_IF2_ID_SHIFT 2 +#define DSI_CMD_MODE_CTL_IF2_ID_MASK 0x0000000C +#define DSI_CMD_MODE_CTL_IF2_ID(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_ID, __x) +#define DSI_CMD_MODE_CTL_IF1_LP_EN_SHIFT 4 +#define DSI_CMD_MODE_CTL_IF1_LP_EN_MASK 0x00000010 +#define DSI_CMD_MODE_CTL_IF1_LP_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF1_LP_EN, __x) +#define DSI_CMD_MODE_CTL_IF2_LP_EN_SHIFT 5 +#define DSI_CMD_MODE_CTL_IF2_LP_EN_MASK 0x00000020 +#define DSI_CMD_MODE_CTL_IF2_LP_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, IF2_LP_EN, __x) +#define DSI_CMD_MODE_CTL_ARB_MODE_SHIFT 6 +#define DSI_CMD_MODE_CTL_ARB_MODE_MASK 0x00000040 +#define DSI_CMD_MODE_CTL_ARB_MODE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_MODE, __x) +#define DSI_CMD_MODE_CTL_ARB_PRI_SHIFT 7 +#define DSI_CMD_MODE_CTL_ARB_PRI_MASK 0x00000080 +#define DSI_CMD_MODE_CTL_ARB_PRI(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, ARB_PRI, __x) +#define DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT 8 +#define DSI_CMD_MODE_CTL_FIL_VALUE_MASK 0x0000FF00 +#define DSI_CMD_MODE_CTL_FIL_VALUE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, FIL_VALUE, __x) +#define DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT 16 +#define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK 0x03FF0000 +#define DSI_CMD_MODE_CTL_TE_TIMEOUT(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_CTL, TE_TIMEOUT, __x) +#define DSI_CMD_MODE_STS 0x00000054 +#define DSI_CMD_MODE_STS_ERR_NO_TE_SHIFT 0 +#define DSI_CMD_MODE_STS_ERR_NO_TE_MASK 0x00000001 +#define DSI_CMD_MODE_STS_ERR_NO_TE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_NO_TE, __x) +#define DSI_CMD_MODE_STS_ERR_TE_MISS_SHIFT 1 +#define DSI_CMD_MODE_STS_ERR_TE_MISS_MASK 0x00000002 +#define DSI_CMD_MODE_STS_ERR_TE_MISS(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_TE_MISS, __x) +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_SHIFT 2 +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN_MASK 0x00000004 +#define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI1_UNDERRUN, __x) +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_SHIFT 3 +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN_MASK 0x00000008 +#define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_SDI2_UNDERRUN, __x) +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_SHIFT 4 +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD_MASK 0x00000010 +#define DSI_CMD_MODE_STS_ERR_UNWANTED_RD(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, ERR_UNWANTED_RD, __x) +#define DSI_CMD_MODE_STS_CSM_RUNNING_SHIFT 5 +#define DSI_CMD_MODE_STS_CSM_RUNNING_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CSM_RUNNING(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS, CSM_RUNNING, __x) +#define DSI_DIRECT_CMD_SEND 0x00000060 +#define DSI_DIRECT_CMD_SEND_START_SHIFT 0 +#define DSI_DIRECT_CMD_SEND_START_MASK 0xFFFFFFFF +#define DSI_DIRECT_CMD_SEND_START(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_SEND, START, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS 0x00000064 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT 0 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK 0x00000007 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE 0 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ 1 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ 4 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ 5 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ 6 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, \ + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_##__x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_SHIFT 3 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT_MASK 0x00000008 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LONGNOTSHORT, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT 8 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK 0x00003F00 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_0 5 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_SHORT_WRITE_1 21 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_LONG_WRITE 57 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_DCS_READ 6 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, \ + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_##__x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT 14 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_MASK 0x0000C000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_ID, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT 16 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_MASK 0x001F0000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_SIZE, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_SHIFT 21 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN_MASK 0x00200000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, CMD_LP_EN, __x) +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT 24 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK 0x0F000000 +#define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_MAIN_SETTINGS, TRIGGER_VAL, __x) +#define DSI_DIRECT_CMD_STS 0x00000068 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, CMD_TRANSMISSION, __x) +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_SHIFT 1 +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_WRITE_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, WRITE_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_SHIFT 2 +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_SHIFT 3 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT 4 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_SHIFT 5 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACKNOWLEDGE_WITH_ERR_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_SHIFT 6 +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_TE_RECEIVED_SHIFT 7 +#define DSI_DIRECT_CMD_STS_TE_RECEIVED_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_TE_RECEIVED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TE_RECEIVED, __x) +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_SHIFT 8 +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_BTA_COMPLETED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_COMPLETED, __x) +#define DSI_DIRECT_CMD_STS_BTA_FINISHED_SHIFT 9 +#define DSI_DIRECT_CMD_STS_BTA_FINISHED_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_BTA_FINISHED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, BTA_FINISHED, __x) +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_SHIFT 10 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, READ_COMPLETED_WITH_ERR, __x) +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT 11 +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK 0x00007800 +#define DSI_DIRECT_CMD_STS_TRIGGER_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, TRIGGER_VAL, __x) +#define DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT 16 +#define DSI_DIRECT_CMD_STS_ACK_VAL_MASK 0xFFFF0000 +#define DSI_DIRECT_CMD_STS_ACK_VAL(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS, ACK_VAL, __x) +#define DSI_DIRECT_CMD_RD_INIT 0x0000006C +#define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT 0 +#define DSI_DIRECT_CMD_RD_INIT_RESET_MASK 0xFFFFFFFF +#define DSI_DIRECT_CMD_RD_INIT_RESET(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_INIT, RESET, __x) +#define DSI_DIRECT_CMD_WRDAT0 0x00000070 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT0_WRDAT0(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT0, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT1(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT1, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT2(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT2, __x) +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT0_WRDAT3(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT0, WRDAT3, __x) +#define DSI_DIRECT_CMD_WRDAT1 0x00000074 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT1_WRDAT4(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT4, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT5(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT5, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT6(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT6, __x) +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT1_WRDAT7(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT1, WRDAT7, __x) +#define DSI_DIRECT_CMD_WRDAT2 0x00000078 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT2_WRDAT8(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT8, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT9(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT9, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT10(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT10, __x) +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT2_WRDAT11(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT2, WRDAT11, __x) +#define DSI_DIRECT_CMD_WRDAT3 0x0000007C +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_SHIFT 0 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12_MASK 0x000000FF +#define DSI_DIRECT_CMD_WRDAT3_WRDAT12(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT12, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_SHIFT 8 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT13(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT13, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_SHIFT 16 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT14(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT14, __x) +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_SHIFT 24 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15_MASK 0xFF000000 +#define DSI_DIRECT_CMD_WRDAT3_WRDAT15(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_WRDAT3, WRDAT15, __x) +#define DSI_DIRECT_CMD_RDDAT 0x00000080 +#define DSI_DIRECT_CMD_RDDAT_RDDAT0_SHIFT 0 +#define DSI_DIRECT_CMD_RDDAT_RDDAT0_MASK 0x000000FF +#define DSI_DIRECT_CMD_RDDAT_RDDAT0(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT0, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT1_SHIFT 8 +#define DSI_DIRECT_CMD_RDDAT_RDDAT1_MASK 0x0000FF00 +#define DSI_DIRECT_CMD_RDDAT_RDDAT1(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT1, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT2_SHIFT 16 +#define DSI_DIRECT_CMD_RDDAT_RDDAT2_MASK 0x00FF0000 +#define DSI_DIRECT_CMD_RDDAT_RDDAT2(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT2, __x) +#define DSI_DIRECT_CMD_RDDAT_RDDAT3_SHIFT 24 +#define DSI_DIRECT_CMD_RDDAT_RDDAT3_MASK 0xFF000000 +#define DSI_DIRECT_CMD_RDDAT_RDDAT3(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RDDAT, RDDAT3, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY 0x00000084 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT 0 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK 0x0000FFFF +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_SIZE, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT 16 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK 0x00030000 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_ID, __x) +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT 18 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK 0x00040000 +#define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_PROPERTY, RD_DCSNOTGENERIC, __x) +#define DSI_DIRECT_CMD_RD_STS 0x00000088 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_ERR_FIXED(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_FIXED, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNCORRECTABLE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNCORRECTABLE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_ERR_CHECKSUM(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_CHECKSUM, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_ERR_UNDECODABLE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_UNDECODABLE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_ERR_RECEIVE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_RECEIVE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_ERR_OVERSIZE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_OVERSIZE, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_ERR_WRONG_LENGTH(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_WRONG_LENGTH, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_ERR_MISSING_EOT(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_MISSING_EOT, __x) +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_ERR_EOT_WITH_ERR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS, ERR_EOT_WITH_ERR, __x) +#define DSI_VID_MAIN_CTL 0x00000090 +#define DSI_VID_MAIN_CTL_START_MODE_SHIFT 0 +#define DSI_VID_MAIN_CTL_START_MODE_MASK 0x00000003 +#define DSI_VID_MAIN_CTL_START_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, START_MODE, __x) +#define DSI_VID_MAIN_CTL_STOP_MODE_SHIFT 2 +#define DSI_VID_MAIN_CTL_STOP_MODE_MASK 0x0000000C +#define DSI_VID_MAIN_CTL_STOP_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, STOP_MODE, __x) +#define DSI_VID_MAIN_CTL_VID_ID_SHIFT 4 +#define DSI_VID_MAIN_CTL_VID_ID_MASK 0x00000030 +#define DSI_VID_MAIN_CTL_VID_ID(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_ID, __x) +#define DSI_VID_MAIN_CTL_HEADER_SHIFT 6 +#define DSI_VID_MAIN_CTL_HEADER_MASK 0x00000FC0 +#define DSI_VID_MAIN_CTL_HEADER(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, HEADER, __x) +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_SHIFT 12 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_MASK 0x00003000 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS 0 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS 1 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE 2 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS 3 +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, \ + DSI_VID_MAIN_CTL_VID_PIXEL_MODE_##__x) +#define DSI_VID_MAIN_CTL_VID_PIXEL_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, VID_PIXEL_MODE, __x) +#define DSI_VID_MAIN_CTL_BURST_MODE_SHIFT 14 +#define DSI_VID_MAIN_CTL_BURST_MODE_MASK 0x00004000 +#define DSI_VID_MAIN_CTL_BURST_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, BURST_MODE, __x) +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_SHIFT 15 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE_MASK 0x00008000 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_ACTIVE, __x) +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_SHIFT 16 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL_MASK 0x00010000 +#define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, SYNC_PULSE_HORIZONTAL, __x) +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_SHIFT 17 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_MASK 0x00060000 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL 0 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING 1 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 2 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 3 +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, \ + DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_##__x) +#define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKLINE_MODE, __x) +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_SHIFT 19 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_MASK 0x00180000 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL 0 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING 1 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 2 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 3 +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, \ + DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_##__x) +#define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, REG_BLKEOL_MODE, __x) +#define DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT 21 +#define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK 0x00600000 +#define DSI_VID_MAIN_CTL_RECOVERY_MODE(__x) \ + DSI_VAL2REG(DSI_VID_MAIN_CTL, RECOVERY_MODE, __x) +#define DSI_VID_VSIZE 0x00000094 +#define DSI_VID_VSIZE_VSA_LENGTH_SHIFT 0 +#define DSI_VID_VSIZE_VSA_LENGTH_MASK 0x0000003F +#define DSI_VID_VSIZE_VSA_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VSA_LENGTH, __x) +#define DSI_VID_VSIZE_VBP_LENGTH_SHIFT 6 +#define DSI_VID_VSIZE_VBP_LENGTH_MASK 0x00000FC0 +#define DSI_VID_VSIZE_VBP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VBP_LENGTH, __x) +#define DSI_VID_VSIZE_VFP_LENGTH_SHIFT 12 +#define DSI_VID_VSIZE_VFP_LENGTH_MASK 0x000FF000 +#define DSI_VID_VSIZE_VFP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VFP_LENGTH, __x) +#define DSI_VID_VSIZE_VACT_LENGTH_SHIFT 20 +#define DSI_VID_VSIZE_VACT_LENGTH_MASK 0x7FF00000 +#define DSI_VID_VSIZE_VACT_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_VSIZE, VACT_LENGTH, __x) +#define DSI_VID_HSIZE1 0x00000098 +#define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT 0 +#define DSI_VID_HSIZE1_HSA_LENGTH_MASK 0x000003FF +#define DSI_VID_HSIZE1_HSA_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HSA_LENGTH, __x) +#define DSI_VID_HSIZE1_HBP_LENGTH_SHIFT 10 +#define DSI_VID_HSIZE1_HBP_LENGTH_MASK 0x000FFC00 +#define DSI_VID_HSIZE1_HBP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HBP_LENGTH, __x) +#define DSI_VID_HSIZE1_HFP_LENGTH_SHIFT 20 +#define DSI_VID_HSIZE1_HFP_LENGTH_MASK 0x7FF00000 +#define DSI_VID_HSIZE1_HFP_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE1, HFP_LENGTH, __x) +#define DSI_VID_HSIZE2 0x0000009C +#define DSI_VID_HSIZE2_RGB_SIZE_SHIFT 0 +#define DSI_VID_HSIZE2_RGB_SIZE_MASK 0x00001FFF +#define DSI_VID_HSIZE2_RGB_SIZE(__x) \ + DSI_VAL2REG(DSI_VID_HSIZE2, RGB_SIZE, __x) +#define DSI_VID_BLKSIZE1 0x000000A0 +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT 0 +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK 0x00001FFF +#define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKLINE_EVENT_PCK, __x) +#define DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT 13 +#define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK 0x03FFE000 +#define DSI_VID_BLKSIZE1_BLKEOL_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE1, BLKEOL_PCK, __x) +#define DSI_VID_BLKSIZE2 0x000000A4 +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT 0 +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK 0x00001FFF +#define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK(__x) \ + DSI_VAL2REG(DSI_VID_BLKSIZE2, BLKLINE_PULSE_PCK, __x) +#define DSI_VID_PCK_TIME 0x000000A8 +#define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT 0 +#define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK 0x00001FFF +#define DSI_VID_PCK_TIME_BLKEOL_DURATION(__x) \ + DSI_VAL2REG(DSI_VID_PCK_TIME, BLKEOL_DURATION, __x) +#define DSI_VID_DPHY_TIME 0x000000AC +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT 0 +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK 0x00001FFF +#define DSI_VID_DPHY_TIME_REG_LINE_DURATION(__x) \ + DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_LINE_DURATION, __x) +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT 13 +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK 0x00FFE000 +#define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME(__x) \ + DSI_VAL2REG(DSI_VID_DPHY_TIME, REG_WAKEUP_TIME, __x) +#define DSI_VID_ERR_COLOR 0x000000B0 +#define DSI_VID_ERR_COLOR_COL_RED_SHIFT 0 +#define DSI_VID_ERR_COLOR_COL_RED_MASK 0x000000FF +#define DSI_VID_ERR_COLOR_COL_RED(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_RED, __x) +#define DSI_VID_ERR_COLOR_COL_GREEN_SHIFT 8 +#define DSI_VID_ERR_COLOR_COL_GREEN_MASK 0x0000FF00 +#define DSI_VID_ERR_COLOR_COL_GREEN(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_GREEN, __x) +#define DSI_VID_ERR_COLOR_COL_BLUE_SHIFT 16 +#define DSI_VID_ERR_COLOR_COL_BLUE_MASK 0x00FF0000 +#define DSI_VID_ERR_COLOR_COL_BLUE(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, COL_BLUE, __x) +#define DSI_VID_ERR_COLOR_PAD_VAL_SHIFT 24 +#define DSI_VID_ERR_COLOR_PAD_VAL_MASK 0xFF000000 +#define DSI_VID_ERR_COLOR_PAD_VAL(__x) \ + DSI_VAL2REG(DSI_VID_ERR_COLOR, PAD_VAL, __x) +#define DSI_VID_VPOS 0x000000B4 +#define DSI_VID_VPOS_LINE_POS_SHIFT 0 +#define DSI_VID_VPOS_LINE_POS_MASK 0x00000003 +#define DSI_VID_VPOS_LINE_POS(__x) \ + DSI_VAL2REG(DSI_VID_VPOS, LINE_POS, __x) +#define DSI_VID_VPOS_LINE_VAL_SHIFT 2 +#define DSI_VID_VPOS_LINE_VAL_MASK 0x00001FFC +#define DSI_VID_VPOS_LINE_VAL(__x) \ + DSI_VAL2REG(DSI_VID_VPOS, LINE_VAL, __x) +#define DSI_VID_HPOS 0x000000B8 +#define DSI_VID_HPOS_HORIZONTAL_POS_SHIFT 0 +#define DSI_VID_HPOS_HORIZONTAL_POS_MASK 0x00000007 +#define DSI_VID_HPOS_HORIZONTAL_POS(__x) \ + DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_POS, __x) +#define DSI_VID_HPOS_HORIZONTAL_VAL_SHIFT 3 +#define DSI_VID_HPOS_HORIZONTAL_VAL_MASK 0x0000FFF8 +#define DSI_VID_HPOS_HORIZONTAL_VAL(__x) \ + DSI_VAL2REG(DSI_VID_HPOS, HORIZONTAL_VAL, __x) +#define DSI_VID_MODE_STS 0x000000BC +#define DSI_VID_MODE_STS_VSG_RUNNING_SHIFT 0 +#define DSI_VID_MODE_STS_VSG_RUNNING_MASK 0x00000001 +#define DSI_VID_MODE_STS_VSG_RUNNING(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RUNNING, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_DATA_SHIFT 1 +#define DSI_VID_MODE_STS_ERR_MISSING_DATA_MASK 0x00000002 +#define DSI_VID_MODE_STS_ERR_MISSING_DATA(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_DATA, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_SHIFT 2 +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC_MASK 0x00000004 +#define DSI_VID_MODE_STS_ERR_MISSING_HSYNC(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_HSYNC, __x) +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_SHIFT 3 +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC_MASK 0x00000008 +#define DSI_VID_MODE_STS_ERR_MISSING_VSYNC(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_MISSING_VSYNC, __x) +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_SHIFT 4 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH_MASK 0x00000010 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_LENGTH, __x) +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_SHIFT 5 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT_MASK 0x00000020 +#define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, REG_ERR_SMALL_HEIGHT, __x) +#define DSI_VID_MODE_STS_ERR_BURSTWRITE_SHIFT 6 +#define DSI_VID_MODE_STS_ERR_BURSTWRITE_MASK 0x00000040 +#define DSI_VID_MODE_STS_ERR_BURSTWRITE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_BURSTWRITE, __x) +#define DSI_VID_MODE_STS_ERR_LONGWRITE_SHIFT 7 +#define DSI_VID_MODE_STS_ERR_LONGWRITE_MASK 0x00000080 +#define DSI_VID_MODE_STS_ERR_LONGWRITE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGWRITE, __x) +#define DSI_VID_MODE_STS_ERR_LONGREAD_SHIFT 8 +#define DSI_VID_MODE_STS_ERR_LONGREAD_MASK 0x00000100 +#define DSI_VID_MODE_STS_ERR_LONGREAD(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_LONGREAD, __x) +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_SHIFT 9 +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH_MASK 0x00000200 +#define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, ERR_VRS_WRONG_LENGTH, __x) +#define DSI_VID_MODE_STS_VSG_RECOVERY_SHIFT 10 +#define DSI_VID_MODE_STS_VSG_RECOVERY_MASK 0x00000400 +#define DSI_VID_MODE_STS_VSG_RECOVERY(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS, VSG_RECOVERY, __x) +#define DSI_VID_VCA_SETTING1 0x000000C0 +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT 0 +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK 0x0000FFFF +#define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING1, MAX_BURST_LIMIT, __x) +#define DSI_VID_VCA_SETTING1_BURST_LP_SHIFT 16 +#define DSI_VID_VCA_SETTING1_BURST_LP_MASK 0x00010000 +#define DSI_VID_VCA_SETTING1_BURST_LP(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING1, BURST_LP, __x) +#define DSI_VID_VCA_SETTING2 0x000000C4 +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT 0 +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK 0x0000FFFF +#define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING2, EXACT_BURST_LIMIT, __x) +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT 16 +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK 0xFFFF0000 +#define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT(__x) \ + DSI_VAL2REG(DSI_VID_VCA_SETTING2, MAX_LINE_LIMIT, __x) +#define DSI_TVG_CTL 0x000000C8 +#define DSI_TVG_CTL_TVG_RUN_SHIFT 0 +#define DSI_TVG_CTL_TVG_RUN_MASK 0x00000001 +#define DSI_TVG_CTL_TVG_RUN(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_RUN, __x) +#define DSI_TVG_CTL_TVG_STOPMODE_SHIFT 1 +#define DSI_TVG_CTL_TVG_STOPMODE_MASK 0x00000006 +#define DSI_TVG_CTL_TVG_STOPMODE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_STOPMODE, __x) +#define DSI_TVG_CTL_TVG_MODE_SHIFT 3 +#define DSI_TVG_CTL_TVG_MODE_MASK 0x00000018 +#define DSI_TVG_CTL_TVG_MODE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_MODE, __x) +#define DSI_TVG_CTL_TVG_STRIPE_SIZE_SHIFT 5 +#define DSI_TVG_CTL_TVG_STRIPE_SIZE_MASK 0x000000E0 +#define DSI_TVG_CTL_TVG_STRIPE_SIZE(__x) \ + DSI_VAL2REG(DSI_TVG_CTL, TVG_STRIPE_SIZE, __x) +#define DSI_TVG_IMG_SIZE 0x000000CC +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_SHIFT 0 +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE_MASK 0x00001FFF +#define DSI_TVG_IMG_SIZE_TVG_LINE_SIZE(__x) \ + DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_LINE_SIZE, __x) +#define DSI_TVG_IMG_SIZE_TVG_NBLINE_SHIFT 16 +#define DSI_TVG_IMG_SIZE_TVG_NBLINE_MASK 0x07FF0000 +#define DSI_TVG_IMG_SIZE_TVG_NBLINE(__x) \ + DSI_VAL2REG(DSI_TVG_IMG_SIZE, TVG_NBLINE, __x) +#define DSI_TVG_COLOR1 0x000000D0 +#define DSI_TVG_COLOR1_COL1_RED_SHIFT 0 +#define DSI_TVG_COLOR1_COL1_RED_MASK 0x000000FF +#define DSI_TVG_COLOR1_COL1_RED(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_RED, __x) +#define DSI_TVG_COLOR1_COL1_GREEN_SHIFT 8 +#define DSI_TVG_COLOR1_COL1_GREEN_MASK 0x0000FF00 +#define DSI_TVG_COLOR1_COL1_GREEN(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_GREEN, __x) +#define DSI_TVG_COLOR1_COL1_BLUE_SHIFT 16 +#define DSI_TVG_COLOR1_COL1_BLUE_MASK 0x00FF0000 +#define DSI_TVG_COLOR1_COL1_BLUE(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR1, COL1_BLUE, __x) +#define DSI_TVG_COLOR2 0x000000D4 +#define DSI_TVG_COLOR2_COL2_RED_SHIFT 0 +#define DSI_TVG_COLOR2_COL2_RED_MASK 0x000000FF +#define DSI_TVG_COLOR2_COL2_RED(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_RED, __x) +#define DSI_TVG_COLOR2_COL2_GREEN_SHIFT 8 +#define DSI_TVG_COLOR2_COL2_GREEN_MASK 0x0000FF00 +#define DSI_TVG_COLOR2_COL2_GREEN(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_GREEN, __x) +#define DSI_TVG_COLOR2_COL2_BLUE_SHIFT 16 +#define DSI_TVG_COLOR2_COL2_BLUE_MASK 0x00FF0000 +#define DSI_TVG_COLOR2_COL2_BLUE(__x) \ + DSI_VAL2REG(DSI_TVG_COLOR2, COL2_BLUE, __x) +#define DSI_TVG_STS 0x000000D8 +#define DSI_TVG_STS_TVG_RUNNING_SHIFT 0 +#define DSI_TVG_STS_TVG_RUNNING_MASK 0x00000001 +#define DSI_TVG_STS_TVG_RUNNING(__x) \ + DSI_VAL2REG(DSI_TVG_STS, TVG_RUNNING, __x) +#define DSI_TBG_CTL 0x000000E0 +#define DSI_TBG_CTL_TBG_START_SHIFT 0 +#define DSI_TBG_CTL_TBG_START_MASK 0x00000001 +#define DSI_TBG_CTL_TBG_START(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_START, __x) +#define DSI_TBG_CTL_TBG_HS_REQ_SHIFT 1 +#define DSI_TBG_CTL_TBG_HS_REQ_MASK 0x00000002 +#define DSI_TBG_CTL_TBG_HS_REQ(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_HS_REQ, __x) +#define DSI_TBG_CTL_TBG_DATA_SEL_SHIFT 2 +#define DSI_TBG_CTL_TBG_DATA_SEL_MASK 0x00000004 +#define DSI_TBG_CTL_TBG_DATA_SEL(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_DATA_SEL, __x) +#define DSI_TBG_CTL_TBG_MODE_SHIFT 3 +#define DSI_TBG_CTL_TBG_MODE_MASK 0x00000018 +#define DSI_TBG_CTL_TBG_MODE_1BYTE 0 +#define DSI_TBG_CTL_TBG_MODE_2BYTE 1 +#define DSI_TBG_CTL_TBG_MODE_BURST_COUNTER 2 +#define DSI_TBG_CTL_TBG_MODE_BURST 3 +#define DSI_TBG_CTL_TBG_MODE_ENUM(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, DSI_TBG_CTL_TBG_MODE_##__x) +#define DSI_TBG_CTL_TBG_MODE(__x) \ + DSI_VAL2REG(DSI_TBG_CTL, TBG_MODE, __x) +#define DSI_TBG_SETTING 0x000000E4 +#define DSI_TBG_SETTING_TBG_DATA_SHIFT 0 +#define DSI_TBG_SETTING_TBG_DATA_MASK 0x0000FFFF +#define DSI_TBG_SETTING_TBG_DATA(__x) \ + DSI_VAL2REG(DSI_TBG_SETTING, TBG_DATA, __x) +#define DSI_TBG_SETTING_TBG_CPT_SHIFT 16 +#define DSI_TBG_SETTING_TBG_CPT_MASK 0x0FFF0000 +#define DSI_TBG_SETTING_TBG_CPT(__x) \ + DSI_VAL2REG(DSI_TBG_SETTING, TBG_CPT, __x) +#define DSI_TBG_STS 0x000000E8 +#define DSI_TBG_STS_TBG_STATUS_SHIFT 0 +#define DSI_TBG_STS_TBG_STATUS_MASK 0x00000001 +#define DSI_TBG_STS_TBG_STATUS(__x) \ + DSI_VAL2REG(DSI_TBG_STS, TBG_STATUS, __x) +#define DSI_MCTL_MAIN_STS_CTL 0x000000F0 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_SHIFT 0 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_SHIFT 2 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_SHIFT 3 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_SHIFT 4 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_SHIFT 5 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_SHIFT 7 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EN, __x) +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_SHIFT 16 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE_MASK 0x00010000 +#define DSI_MCTL_MAIN_STS_CTL_PLL_LOCK_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, PLL_LOCK_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_SHIFT 17 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE_MASK 0x00020000 +#define DSI_MCTL_MAIN_STS_CTL_CLKLANE_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CLKLANE_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_SHIFT 18 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE_MASK 0x00040000 +#define DSI_MCTL_MAIN_STS_CTL_DAT1_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT1_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_SHIFT 19 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE_MASK 0x00080000 +#define DSI_MCTL_MAIN_STS_CTL_DAT2_READY_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, DAT2_READY_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_SHIFT 20 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE_MASK 0x00100000 +#define DSI_MCTL_MAIN_STS_CTL_HSTX_TO_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, HSTX_TO_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_SHIFT 21 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE_MASK 0x00200000 +#define DSI_MCTL_MAIN_STS_CTL_LPRX_TO_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, LPRX_TO_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_SHIFT 22 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE_MASK 0x00400000 +#define DSI_MCTL_MAIN_STS_CTL_CRS_UNTERM_PCK_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, CRS_UNTERM_PCK_ERR_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_SHIFT 23 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE_MASK 0x00800000 +#define DSI_MCTL_MAIN_STS_CTL_VRS_UNTERM_PCK_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CTL, VRS_UNTERM_PCK_ERR_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL 0x000000F4 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_SHIFT 0 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN_MASK 0x00000001 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_SHIFT 1 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN_MASK 0x00000002 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_SHIFT 2 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN_MASK 0x00000004 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_SHIFT 3 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN_MASK 0x00000008 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_SHIFT 4 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN_MASK 0x00000010 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EN, __x) +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_SHIFT 5 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EN, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_SHIFT 16 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE_MASK 0x00010000 +#define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_SHIFT 17 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE_MASK 0x00020000 +#define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_TE_MISS_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_SHIFT 18 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE_MASK 0x00040000 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI1_UNDERRUN_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_SHIFT 19 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE_MASK 0x00080000 +#define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_SDI2_UNDERRUN_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_SHIFT 20 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE_MASK 0x00100000 +#define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, ERR_UNWANTED_RD_EDGE, __x) +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_SHIFT 21 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE_MASK 0x00200000 +#define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CTL, CSM_RUNNING_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL 0x000000F8 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_SHIFT 1 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_SHIFT 2 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_SHIFT 3 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_SHIFT 4 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_SHIFT 5 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_SHIFT 6 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_SHIFT 7 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_SHIFT 8 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_SHIFT 9 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_SHIFT 10 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_SHIFT 16 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE_MASK 0x00010000 +#define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, CMD_TRANSMISSION_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_SHIFT 17 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE_MASK 0x00020000 +#define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, WRITE_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_SHIFT 18 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE_MASK 0x00040000 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_SHIFT 19 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE_MASK 0x00080000 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_SHIFT 20 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE_MASK 0x00100000 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_SHIFT 21 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE_MASK 0x00200000 +#define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, ACKNOWLEDGE_WITH_ERR_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_SHIFT 22 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE_MASK 0x00400000 +#define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TRIGGER_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_SHIFT 23 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE_MASK 0x00800000 +#define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_SHIFT 24 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE_MASK 0x01000000 +#define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_COMPLETED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_SHIFT 25 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE_MASK 0x02000000 +#define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, BTA_FINISHED_EDGE, __x) +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_SHIFT 26 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE_MASK 0x04000000 +#define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CTL, READ_COMPLETED_WITH_ERR_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL 0x000000FC +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EN(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EN, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_SHIFT 16 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE_MASK 0x00010000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_FIXED_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_FIXED_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_SHIFT 17 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE_MASK 0x00020000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNCORRECTABLE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNCORRECTABLE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_SHIFT 18 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE_MASK 0x00040000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_CHECKSUM_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_CHECKSUM_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_SHIFT 19 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE_MASK 0x00080000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_UNDECODABLE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_UNDECODABLE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_SHIFT 20 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE_MASK 0x00100000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_RECEIVE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_RECEIVE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_SHIFT 21 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE_MASK 0x00200000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_OVERSIZE_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_OVERSIZE_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_SHIFT 22 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE_MASK 0x00400000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_WRONG_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_WRONG_LENGTH_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_SHIFT 23 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE_MASK 0x00800000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_MISSING_EOT_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_MISSING_EOT_EDGE, __x) +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_SHIFT 24 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE_MASK 0x01000000 +#define DSI_DIRECT_CMD_RD_STS_CTL_ERR_EOT_WITH_ERR_EDGE(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CTL, ERR_EOT_WITH_ERR_EDGE, __x) +#define DSI_VID_MODE_STS_CTL 0x00000100 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_SHIFT 0 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN_MASK 0x00000001 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_SHIFT 1 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN_MASK 0x00000002 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_SHIFT 2 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN_MASK 0x00000004 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_SHIFT 3 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN_MASK 0x00000008 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EN, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_SHIFT 4 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN_MASK 0x00000010 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EN, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_SHIFT 5 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN_MASK 0x00000020 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_SHIFT 6 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN_MASK 0x00000040 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_SHIFT 7 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN_MASK 0x00000080 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_SHIFT 8 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN_MASK 0x00000100 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EN, __x) +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_SHIFT 9 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN_MASK 0x00000200 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EN(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EN, __x) +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_SHIFT 16 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE_MASK 0x00010000 +#define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RUNNING_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_SHIFT 17 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE_MASK 0x00020000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_DATA_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_SHIFT 18 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE_MASK 0x00040000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_HSYNC_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_SHIFT 19 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE_MASK 0x00080000 +#define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_MISSING_VSYNC_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_SHIFT 20 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE_MASK 0x00100000 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_LENGTH_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_SHIFT 21 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE_MASK 0x00200000 +#define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, REG_ERR_SMALL_HEIGHT_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_SHIFT 22 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE_MASK 0x00400000 +#define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_BURSTWRITE_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_SHIFT 23 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE_MASK 0x00800000 +#define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGWRITE_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_SHIFT 24 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE_MASK 0x01000000 +#define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_LONGREAD_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_SHIFT 25 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE_MASK 0x02000000 +#define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, ERR_VRS_WRONG_LENGTH_EDGE, __x) +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_SHIFT 26 +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE_MASK 0x04000000 +#define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CTL, VSG_RECOVERY_EDGE, __x) +#define DSI_TG_STS_CTL 0x00000104 +#define DSI_TG_STS_CTL_TVG_STS_EN_SHIFT 0 +#define DSI_TG_STS_CTL_TVG_STS_EN_MASK 0x00000001 +#define DSI_TG_STS_CTL_TVG_STS_EN(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EN, __x) +#define DSI_TG_STS_CTL_TBG_STS_EN_SHIFT 1 +#define DSI_TG_STS_CTL_TBG_STS_EN_MASK 0x00000002 +#define DSI_TG_STS_CTL_TBG_STS_EN(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EN, __x) +#define DSI_TG_STS_CTL_TVG_STS_EDGE_SHIFT 16 +#define DSI_TG_STS_CTL_TVG_STS_EDGE_MASK 0x00010000 +#define DSI_TG_STS_CTL_TVG_STS_EDGE(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TVG_STS_EDGE, __x) +#define DSI_TG_STS_CTL_TBG_STS_EDGE_SHIFT 17 +#define DSI_TG_STS_CTL_TBG_STS_EDGE_MASK 0x00020000 +#define DSI_TG_STS_CTL_TBG_STS_EDGE(__x) \ + DSI_VAL2REG(DSI_TG_STS_CTL, TBG_STS_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL 0x00000108 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_SHIFT 6 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN_MASK 0x00000040 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_SHIFT 7 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN_MASK 0x00000080 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_SHIFT 8 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN_MASK 0x00000100 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_SHIFT 9 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN_MASK 0x00000200 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_SHIFT 10 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN_MASK 0x00000400 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_SHIFT 11 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN_MASK 0x00000800 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_SHIFT 12 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN_MASK 0x00001000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_SHIFT 13 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN_MASK 0x00002000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_SHIFT 14 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN_MASK 0x00004000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_SHIFT 15 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN_MASK 0x00008000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EN(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EN, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_SHIFT 22 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE_MASK 0x00400000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_SHIFT 23 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE_MASK 0x00800000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_ESC_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_ESC_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_SHIFT 24 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE_MASK 0x01000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_SHIFT 25 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE_MASK 0x02000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_SYNCESC_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_SYNCESC_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_SHIFT 26 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE_MASK 0x04000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_SHIFT 27 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE_MASK 0x08000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONTROL_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONTROL_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_SHIFT 28 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE_MASK 0x10000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_SHIFT 29 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE_MASK 0x20000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP0_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP0_2_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_SHIFT 30 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE_MASK 0x40000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_1_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_1_EDGE, __x) +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_SHIFT 31 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE_MASK 0x80000000 +#define DSI_MCTL_DHPY_ERR_CTL_ERR_CONT_LP1_2_EDGE(__x) \ + DSI_VAL2REG(DSI_MCTL_DHPY_ERR_CTL, ERR_CONT_LP1_2_EDGE, __x) +#define DSI_MCTL_MAIN_STS_CLR 0x00000110 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_SHIFT 0 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_CLR_PLL_LOCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, PLL_LOCK_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_SHIFT 1 +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_CLR_CLKLANE_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CLKLANE_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_SHIFT 2 +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_CLR_DAT1_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT1_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_SHIFT 3 +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_CLR_DAT2_READY_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, DAT2_READY_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_SHIFT 4 +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_CLR_HSTX_TO_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, HSTX_TO_ERR_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_SHIFT 5 +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_CLR_LPRX_TO_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, LPRX_TO_ERR_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_SHIFT 6 +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_CLR_CRS_UNTERM_PCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, CRS_UNTERM_PCK_CLR, __x) +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_SHIFT 7 +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_CLR_VRS_UNTERM_PCK_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_CLR, VRS_UNTERM_PCK_CLR, __x) +#define DSI_CMD_MODE_STS_CLR 0x00000114 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_SHIFT 0 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR_MASK 0x00000001 +#define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_NO_TE_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_SHIFT 1 +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR_MASK 0x00000002 +#define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_TE_MISS_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_SHIFT 2 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR_MASK 0x00000004 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI1_UNDERRUN_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_SHIFT 3 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR_MASK 0x00000008 +#define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_SDI2_UNDERRUN_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_SHIFT 4 +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR_MASK 0x00000010 +#define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, ERR_UNWANTED_RD_CLR, __x) +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_SHIFT 5 +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR_MASK 0x00000020 +#define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_CLR, CSM_RUNNING_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR 0x00000118 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_SHIFT 0 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, CMD_TRANSMISSION_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_SHIFT 1 +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, WRITE_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_SHIFT 2 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_SHIFT 3 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_SHIFT 4 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_SHIFT 5 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_SHIFT 6 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TRIGGER_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_SHIFT 7 +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, TE_RECEIVED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_SHIFT 8 +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_COMPLETED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_SHIFT 9 +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, BTA_FINISHED_CLR, __x) +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_SHIFT 10 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_CLR, READ_COMPLETED_WITH_ERR_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR 0x0000011C +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_FIXED_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_FIXED_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNCORRECTABLE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNCORRECTABLE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_CHECKSUM_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_CHECKSUM_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_UNDECODABLE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_UNDECODABLE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_RECEIVE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_RECEIVE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_OVERSIZE_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_OVERSIZE_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_WRONG_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_WRONG_LENGTH_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_MISSING_EOT_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_MISSING_EOT_CLR, __x) +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_CLR_ERR_EOT_WITH_ERR_CLR(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_CLR, ERR_EOT_WITH_ERR_CLR, __x) +#define DSI_VID_MODE_STS_CLR 0x00000120 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_SHIFT 0 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR_MASK 0x00000001 +#define DSI_VID_MODE_STS_CLR_VSG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_STS_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_SHIFT 1 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR_MASK 0x00000002 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_DATA_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_DATA_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_SHIFT 2 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR_MASK 0x00000004 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_HSYNC_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_HSYNC_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_SHIFT 3 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR_MASK 0x00000008 +#define DSI_VID_MODE_STS_CLR_ERR_MISSING_VSYNC_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_MISSING_VSYNC_CLR, __x) +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_SHIFT 4 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR_MASK 0x00000010 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_LENGTH_CLR, __x) +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_SHIFT 5 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR_MASK 0x00000020 +#define DSI_VID_MODE_STS_CLR_REG_ERR_SMALL_HEIGHT_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, REG_ERR_SMALL_HEIGHT_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_SHIFT 6 +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR_MASK 0x00000040 +#define DSI_VID_MODE_STS_CLR_ERR_BURSTWRITE_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_BURSTWRITE_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_SHIFT 7 +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR_MASK 0x00000080 +#define DSI_VID_MODE_STS_CLR_ERR_LONGWRITE_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGWRITE_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_SHIFT 8 +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR_MASK 0x00000100 +#define DSI_VID_MODE_STS_CLR_ERR_LONGREAD_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_LONGREAD_CLR, __x) +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_SHIFT 9 +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR_MASK 0x00000200 +#define DSI_VID_MODE_STS_CLR_ERR_VRS_WRONG_LENGTH_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, ERR_VRS_WRONG_LENGTH_CLR, __x) +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_SHIFT 10 +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR_MASK 0x00000400 +#define DSI_VID_MODE_STS_CLR_VSG_RECOVERY_CLR(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_CLR, VSG_RECOVERY_CLR, __x) +#define DSI_TG_STS_CLR 0x00000124 +#define DSI_TG_STS_CLR_TVG_STS_CLR_SHIFT 0 +#define DSI_TG_STS_CLR_TVG_STS_CLR_MASK 0x00000001 +#define DSI_TG_STS_CLR_TVG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_TG_STS_CLR, TVG_STS_CLR, __x) +#define DSI_TG_STS_CLR_TBG_STS_CLR_SHIFT 1 +#define DSI_TG_STS_CLR_TBG_STS_CLR_MASK 0x00000002 +#define DSI_TG_STS_CLR_TBG_STS_CLR(__x) \ + DSI_VAL2REG(DSI_TG_STS_CLR, TBG_STS_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR 0x00000128 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_ESC_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_ESC_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_SYNCESC_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_SYNCESC_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONTROL_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONTROL_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP0_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP0_2_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_1_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_1_CLR, __x) +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_CLR_ERR_CONT_LP1_2_CLR(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_CLR, ERR_CONT_LP1_2_CLR, __x) +#define DSI_MCTL_MAIN_STS_FLAG 0x00000130 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_SHIFT 0 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG_MASK 0x00000001 +#define DSI_MCTL_MAIN_STS_FLAG_PLL_LOCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, PLL_LOCK_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_SHIFT 1 +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG_MASK 0x00000002 +#define DSI_MCTL_MAIN_STS_FLAG_CLKLANE_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CLKLANE_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_SHIFT 2 +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG_MASK 0x00000004 +#define DSI_MCTL_MAIN_STS_FLAG_DAT1_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT1_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_SHIFT 3 +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG_MASK 0x00000008 +#define DSI_MCTL_MAIN_STS_FLAG_DAT2_READY_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, DAT2_READY_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_SHIFT 4 +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG_MASK 0x00000010 +#define DSI_MCTL_MAIN_STS_FLAG_HSTX_TO_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, HSTX_TO_ERR_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_SHIFT 5 +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG_MASK 0x00000020 +#define DSI_MCTL_MAIN_STS_FLAG_LPRX_TO_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, LPRX_TO_ERR_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_SHIFT 6 +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG_MASK 0x00000040 +#define DSI_MCTL_MAIN_STS_FLAG_CRS_UNTERM_PCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, CRS_UNTERM_PCK_FLAG, __x) +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_SHIFT 7 +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG_MASK 0x00000080 +#define DSI_MCTL_MAIN_STS_FLAG_VRS_UNTERM_PCK_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_MAIN_STS_FLAG, VRS_UNTERM_PCK_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG 0x00000134 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_SHIFT 0 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG_MASK 0x00000001 +#define DSI_CMD_MODE_STS_FLAG_ERR_NO_TE_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_NO_TE_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_SHIFT 1 +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG_MASK 0x00000002 +#define DSI_CMD_MODE_STS_FLAG_ERR_TE_MISS_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_TE_MISS_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_SHIFT 2 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG_MASK 0x00000004 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI1_UNDERRUN_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI1_UNDERRUN_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_SHIFT 3 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG_MASK 0x00000008 +#define DSI_CMD_MODE_STS_FLAG_ERR_SDI2_UNDERRUN_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_SDI2_UNDERRUN_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_SHIFT 4 +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG_MASK 0x00000010 +#define DSI_CMD_MODE_STS_FLAG_ERR_UNWANTED_RD_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, ERR_UNWANTED_RD_FLAG, __x) +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_SHIFT 5 +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG_MASK 0x00000020 +#define DSI_CMD_MODE_STS_FLAG_CSM_RUNNING_FLAG(__x) \ + DSI_VAL2REG(DSI_CMD_MODE_STS_FLAG, CSM_RUNNING_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG 0x00000138 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_SHIFT 0 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG_MASK 0x00000001 +#define DSI_DIRECT_CMD_STS_FLAG_CMD_TRANSMISSION_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, CMD_TRANSMISSION_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_SHIFT 1 +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG_MASK 0x00000002 +#define DSI_DIRECT_CMD_STS_FLAG_WRITE_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, WRITE_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_SHIFT 2 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG_MASK 0x00000004 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_SHIFT 3 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG_MASK 0x00000008 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_SHIFT 4 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG_MASK 0x00000010 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_SHIFT 5 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG_MASK 0x00000020 +#define DSI_DIRECT_CMD_STS_FLAG_ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, ACKNOWLEDGE_WITH_ERR_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_SHIFT 6 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG_MASK 0x00000040 +#define DSI_DIRECT_CMD_STS_FLAG_TRIGGER_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TRIGGER_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_SHIFT 7 +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG_MASK 0x00000080 +#define DSI_DIRECT_CMD_STS_FLAG_TE_RECEIVED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, TE_RECEIVED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_SHIFT 8 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG_MASK 0x00000100 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_COMPLETED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_COMPLETED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_SHIFT 9 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG_MASK 0x00000200 +#define DSI_DIRECT_CMD_STS_FLAG_BTA_FINISHED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, BTA_FINISHED_FLAG, __x) +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_SHIFT 10 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG_MASK 0x00000400 +#define DSI_DIRECT_CMD_STS_FLAG_READ_COMPLETED_WITH_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_STS_FLAG, READ_COMPLETED_WITH_ERR_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG 0x0000013C +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_SHIFT 0 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG_MASK 0x00000001 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_FIXED_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_FIXED_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_SHIFT 1 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG_MASK 0x00000002 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNCORRECTABLE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNCORRECTABLE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_SHIFT 2 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG_MASK 0x00000004 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_CHECKSUM_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_CHECKSUM_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_SHIFT 3 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG_MASK 0x00000008 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_UNDECODABLE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_UNDECODABLE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_SHIFT 4 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG_MASK 0x00000010 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_RECEIVE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_RECEIVE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_SHIFT 5 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG_MASK 0x00000020 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_OVERSIZE_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_OVERSIZE_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_SHIFT 6 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG_MASK 0x00000040 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_WRONG_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_WRONG_LENGTH_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_SHIFT 7 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG_MASK 0x00000080 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_MISSING_EOT_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_MISSING_EOT_FLAG, __x) +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_SHIFT 8 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG_MASK 0x00000100 +#define DSI_DIRECT_CMD_RD_STS_FLAG_ERR_EOT_WITH_ERR_FLAG(__x) \ + DSI_VAL2REG(DSI_DIRECT_CMD_RD_STS_FLAG, ERR_EOT_WITH_ERR_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG 0x00000140 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_SHIFT 0 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG_MASK 0x00000001 +#define DSI_VID_MODE_STS_FLAG_VSG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_STS_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_SHIFT 1 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG_MASK 0x00000002 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_DATA_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_DATA_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_SHIFT 2 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG_MASK 0x00000004 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_HSYNC_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_HSYNC_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_SHIFT 3 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG_MASK 0x00000008 +#define DSI_VID_MODE_STS_FLAG_ERR_MISSING_VSYNC_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_MISSING_VSYNC_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_SHIFT 4 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG_MASK 0x00000010 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_LENGTH_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_SHIFT 5 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG_MASK 0x00000020 +#define DSI_VID_MODE_STS_FLAG_REG_ERR_SMALL_HEIGHT_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, REG_ERR_SMALL_HEIGHT_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_SHIFT 6 +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG_MASK 0x00000040 +#define DSI_VID_MODE_STS_FLAG_ERR_BURSTWRITE_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_BURSTWRITE_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_SHIFT 7 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG_MASK 0x00000080 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGWRITE_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGWRITE_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_SHIFT 8 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG_MASK 0x00000100 +#define DSI_VID_MODE_STS_FLAG_ERR_LONGREAD_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_LONGREAD_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_SHIFT 9 +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG_MASK 0x00000200 +#define DSI_VID_MODE_STS_FLAG_ERR_VRS_WRONG_LENGTH_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, ERR_VRS_WRONG_LENGTH_FLAG, __x) +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_SHIFT 10 +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG_MASK 0x00000400 +#define DSI_VID_MODE_STS_FLAG_VSG_RECOVERY_FLAG(__x) \ + DSI_VAL2REG(DSI_VID_MODE_STS_FLAG, VSG_RECOVERY_FLAG, __x) +#define DSI_TG_STS_FLAG 0x00000144 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG_SHIFT 0 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG_MASK 0x00000001 +#define DSI_TG_STS_FLAG_TVG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_TG_STS_FLAG, TVG_STS_FLAG, __x) +#define DSI_TG_STS_FLAG_TBG_STS_FLAG_SHIFT 1 +#define DSI_TG_STS_FLAG_TBG_STS_FLAG_MASK 0x00000002 +#define DSI_TG_STS_FLAG_TBG_STS_FLAG(__x) \ + DSI_VAL2REG(DSI_TG_STS_FLAG, TBG_STS_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG 0x00000148 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_SHIFT 6 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG_MASK 0x00000040 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_SHIFT 7 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG_MASK 0x00000080 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_ESC_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_ESC_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_SHIFT 8 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG_MASK 0x00000100 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_SHIFT 9 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG_MASK 0x00000200 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_SYNCESC_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_SYNCESC_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_SHIFT 10 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG_MASK 0x00000400 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_SHIFT 11 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG_MASK 0x00000800 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONTROL_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONTROL_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_SHIFT 12 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG_MASK 0x00001000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_SHIFT 13 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG_MASK 0x00002000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP0_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP0_2_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_SHIFT 14 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG_MASK 0x00004000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_1_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_1_FLAG, __x) +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_SHIFT 15 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG_MASK 0x00008000 +#define DSI_MCTL_DPHY_ERR_FLAG_ERR_CONT_LP1_2_FLAG(__x) \ + DSI_VAL2REG(DSI_MCTL_DPHY_ERR_FLAG, ERR_CONT_LP1_2_FLAG, __x) +#define DSI_DPHY_LANES_TRIM 0x00000150 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT 0 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK 0x00000003 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_SHIFT 2 +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1_MASK 0x00000004 +#define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_CD_OFF_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_SHIFT 3 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1_MASK 0x00000008 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_SHIFT 4 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1_MASK 0x00000010 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_SHIFT 5 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1_MASK 0x00000020 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT1, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT 6 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK 0x000000C0 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT 8 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK 0x00000300 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_RX_VIL_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT 10 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK 0x00000C00 +#define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_LP_TX_SLEWRATE_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_SHIFT 12 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_MASK 0x00001000 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 0 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 1 +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_ENUM(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, \ + DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_##__x) +#define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SPECS_90_81B, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_SHIFT 13 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK_MASK 0x00002000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_SHIFT 14 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK_MASK 0x00004000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_SHIFT 15 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK_MASK 0x00008000 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_CLK, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_SHIFT 16 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2_MASK 0x00030000 +#define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_SKEW_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_SHIFT 18 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2_MASK 0x00040000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_UP_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_SHIFT 19 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2_MASK 0x00080000 +#define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_HSTX_SLEWRATE_DOWN_DAT2, __x) +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_SHIFT 20 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2_MASK 0x00100000 +#define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2(__x) \ + DSI_VAL2REG(DSI_DPHY_LANES_TRIM, DPHY_TEST_RESERVED_1_DAT2, __x) +#define DSI_ID_REG 0x00000FF0 +#define DSI_ID_REG_Y_SHIFT 0 +#define DSI_ID_REG_Y_MASK 0x0000000F +#define DSI_ID_REG_Y(__x) \ + DSI_VAL2REG(DSI_ID_REG, Y, __x) +#define DSI_ID_REG_X_SHIFT 4 +#define DSI_ID_REG_X_MASK 0x000000F0 +#define DSI_ID_REG_X(__x) \ + DSI_VAL2REG(DSI_ID_REG, X, __x) +#define DSI_ID_REG_H_SHIFT 8 +#define DSI_ID_REG_H_MASK 0x00000300 +#define DSI_ID_REG_H(__x) \ + DSI_VAL2REG(DSI_ID_REG, H, __x) +#define DSI_ID_REG_PRODUCT_ID_SHIFT 10 +#define DSI_ID_REG_PRODUCT_ID_MASK 0x0003FC00 +#define DSI_ID_REG_PRODUCT_ID(__x) \ + DSI_VAL2REG(DSI_ID_REG, PRODUCT_ID, __x) +#define DSI_ID_REG_VENDOR_ID_SHIFT 18 +#define DSI_ID_REG_VENDOR_ID_MASK 0xFFFC0000 +#define DSI_ID_REG_VENDOR_ID(__x) \ + DSI_VAL2REG(DSI_ID_REG, VENDOR_ID, __x) +#define DSI_IP_CONF 0x00000FF4 +#define DSI_IP_CONF_FIFO_SIZE_SHIFT 0 +#define DSI_IP_CONF_FIFO_SIZE_MASK 0x0000003F +#define DSI_IP_CONF_FIFO_SIZE(__x) \ + DSI_VAL2REG(DSI_IP_CONF, FIFO_SIZE, __x) diff --git a/drivers/video/mcde/mcde_bus.c b/drivers/video/mcde/mcde_bus.c new file mode 100644 index 00000000000..63c6079a879 --- /dev/null +++ b/drivers/video/mcde/mcde_bus.c @@ -0,0 +1,261 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display bus driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/notifier.h> + +#include <video/mcde_display.h> +#include <video/mcde_dss.h> + +#define to_mcde_display_driver(__drv) \ + container_of((__drv), struct mcde_display_driver, driver) + +static BLOCKING_NOTIFIER_HEAD(bus_notifier_list); + +static int mcde_drv_suspend(struct device *_dev, pm_message_t state); +static int mcde_drv_resume(struct device *_dev); +struct bus_type mcde_bus_type; + +static int mcde_suspend_device(struct device *dev, void *data) +{ + pm_message_t* state = (pm_message_t *) data; + if (dev->driver->suspend) + return dev->driver->suspend(dev, *state); + return 0; +} + +static int mcde_resume_device(struct device *dev, void *data) +{ + if (dev->driver->resume) + return dev->driver->resume(dev); + return 0; +} + +/* Bus driver */ + +static int mcde_bus_match(struct device *_dev, struct device_driver *driver) +{ + pr_debug("Matching device %s with driver %s\n", + dev_name(_dev), driver->name); + + return strncmp(dev_name(_dev), driver->name, strlen(driver->name)) == 0; +} + +static int mcde_bus_suspend(struct device *_dev, pm_message_t state) +{ + int ret; + ret = bus_for_each_dev(&mcde_bus_type, NULL, &state, + mcde_suspend_device); + if (ret) { + /* TODO Resume all suspended devices */ + /* mcde_bus_resume(dev); */ + return ret; + } + return 0; +} + +static int mcde_bus_resume(struct device *_dev) +{ + return bus_for_each_dev(&mcde_bus_type, NULL, NULL, mcde_resume_device); +} + +struct bus_type mcde_bus_type = { + .name = "mcde_bus", + .match = mcde_bus_match, + .suspend = mcde_bus_suspend, + .resume = mcde_bus_resume, +}; + +static int mcde_drv_probe(struct device *_dev) +{ + struct mcde_display_driver *drv = to_mcde_display_driver(_dev->driver); + struct mcde_display_device *dev = to_mcde_display_device(_dev); + + return drv->probe(dev); +} + +static int mcde_drv_remove(struct device *_dev) +{ + struct mcde_display_driver *drv = to_mcde_display_driver(_dev->driver); + struct mcde_display_device *dev = to_mcde_display_device(_dev); + + return drv->remove(dev); +} + +static void mcde_drv_shutdown(struct device *_dev) +{ + struct mcde_display_driver *drv = to_mcde_display_driver(_dev->driver); + struct mcde_display_device *dev = to_mcde_display_device(_dev); + + drv->shutdown(dev); +} + +static int mcde_drv_suspend(struct device *_dev, pm_message_t state) +{ + struct mcde_display_driver *drv = to_mcde_display_driver(_dev->driver); + struct mcde_display_device *dev = to_mcde_display_device(_dev); + + return drv->suspend(dev, state); +} + +static int mcde_drv_resume(struct device *_dev) +{ + struct mcde_display_driver *drv = to_mcde_display_driver(_dev->driver); + struct mcde_display_device *dev = to_mcde_display_device(_dev); + + return drv->resume(dev); +} + +/* Bus device */ + +static void mcde_bus_release(struct device *dev) +{ +} + +struct device mcde_bus = { + .init_name = "mcde_bus", + .release = mcde_bus_release +}; + +/* Public bus API */ + +int mcde_display_driver_register(struct mcde_display_driver *drv) +{ + drv->driver.bus = &mcde_bus_type; + if (drv->probe) + drv->driver.probe = mcde_drv_probe; + if (drv->remove) + drv->driver.remove = mcde_drv_remove; + if (drv->shutdown) + drv->driver.shutdown = mcde_drv_shutdown; + if (drv->suspend) + drv->driver.suspend = mcde_drv_suspend; + if (drv->resume) + drv->driver.resume = mcde_drv_resume; + + return driver_register(&drv->driver); +} +EXPORT_SYMBOL(mcde_display_driver_register); + +void mcde_display_driver_unregister(struct mcde_display_driver *drv) +{ + driver_unregister(&drv->driver); +} +EXPORT_SYMBOL(mcde_display_driver_unregister); + +static void mcde_display_dev_release(struct device *dev) +{ + /* Do nothing */ +} + +int mcde_display_device_register(struct mcde_display_device *dev) +{ + /* Setup device */ + if (!dev) + return -EINVAL; + dev->dev.coherent_dma_mask = DMA_32BIT_MASK; + dev->dev.bus = &mcde_bus_type; + if (dev->dev.parent != NULL) + dev->dev.parent = &mcde_bus; + dev->dev.release = mcde_display_dev_release; + if (dev->id != -1) + dev_set_name(&dev->dev, "%s.%d", dev->name, dev->id); + else + dev_set_name(&dev->dev, dev->name); + + mcde_display_init_device(dev); + + return device_register(&dev->dev); +} +EXPORT_SYMBOL(mcde_display_device_register); + +void mcde_display_device_unregister(struct mcde_display_device *dev) +{ + device_unregister(&dev->dev); +} +EXPORT_SYMBOL(mcde_display_device_unregister); + +/* Notifications */ +int mcde_dss_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&bus_notifier_list, nb); +} +EXPORT_SYMBOL(mcde_dss_register_notifier); + +int mcde_dss_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&bus_notifier_list, nb); +} +EXPORT_SYMBOL(mcde_dss_unregister_notifier); + +static int bus_notify_callback(struct notifier_block *nb, + unsigned long event, void *dev) +{ + struct mcde_display_device *ddev = to_mcde_display_device(dev); + + if (event == BUS_NOTIFY_BOUND_DRIVER) { + ddev->initialized = true; + blocking_notifier_call_chain(&bus_notifier_list, + MCDE_DSS_EVENT_DISPLAY_REGISTERED, ddev); + } else if (event == BUS_NOTIFY_UNBIND_DRIVER) { + ddev->initialized = false; + blocking_notifier_call_chain(&bus_notifier_list, + MCDE_DSS_EVENT_DISPLAY_UNREGISTERED, ddev); + } + return 0; +} + +struct notifier_block bus_nb = { + .notifier_call = bus_notify_callback, +}; + +/* Driver init/exit */ + +int __init mcde_display_init(void) +{ + int ret; + + ret = bus_register(&mcde_bus_type); + if (ret) { + pr_warning("Unable to register bus type\n"); + goto no_bus_registration; + } + ret = device_register(&mcde_bus); + if (ret) { + pr_warning("Unable to register bus device\n"); + goto no_device_registration; + } + ret = bus_register_notifier(&mcde_bus_type, &bus_nb); + if (ret) { + pr_warning("Unable to register bus notifier\n"); + goto no_bus_notifier; + } + + goto out; + +no_bus_notifier: + device_unregister(&mcde_bus); +no_device_registration: + bus_unregister(&mcde_bus_type); +no_bus_registration: +out: + return ret; +} + +void mcde_display_exit(void) +{ + bus_unregister_notifier(&mcde_bus_type, &bus_nb); + device_unregister(&mcde_bus); + bus_unregister(&mcde_bus_type); +} diff --git a/drivers/video/mcde/mcde_display.c b/drivers/video/mcde/mcde_display.c new file mode 100644 index 00000000000..1673e77c2dc --- /dev/null +++ b/drivers/video/mcde/mcde_display.c @@ -0,0 +1,424 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * ST-Ericsson MCDE display driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> + +#include <video/mcde_display.h> + +/*temp*/ +#include <linux/delay.h> + +static void mcde_display_get_native_resolution_default( + struct mcde_display_device *ddev, u16 *x_res, u16 *y_res) +{ + if (x_res) + *x_res = ddev->native_x_res; + if (y_res) + *y_res = ddev->native_y_res; +} + +static enum mcde_ovly_pix_fmt mcde_display_get_default_pixel_format_default( + struct mcde_display_device *ddev) +{ + return ddev->default_pixel_format; +} + +static void mcde_display_get_physical_size_default( + struct mcde_display_device *ddev, u16 *width, u16 *height) +{ + if (width) + *width = ddev->physical_width; + if (height) + *height = ddev->physical_height; +} + +static int mcde_display_set_power_mode_default(struct mcde_display_device *ddev, + enum mcde_display_power_mode power_mode) +{ + int ret = 0; + + /* OFF -> STANDBY */ + if (ddev->power_mode == MCDE_DISPLAY_PM_OFF && + power_mode >= MCDE_DISPLAY_PM_OFF) { + if (ddev->platform_enable) + ret = ddev->platform_enable(ddev); + if (!ret) + ddev->power_mode = MCDE_DISPLAY_PM_STANDBY; + } + + if (!ret && ddev->port->type == MCDE_PORTTYPE_DSI) { + /* STANDBY -> ON */ + if (ddev->power_mode == MCDE_DISPLAY_PM_STANDBY && + power_mode == MCDE_DISPLAY_PM_ON) { + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_EXIT_SLEEP_MODE, NULL, 0); + if (!ret) + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_SET_DISPLAY_ON, NULL, 0); + if (!ret) + ddev->power_mode = MCDE_DISPLAY_PM_ON; + } + /* ON -> STANDBY */ + else if (ddev->power_mode == MCDE_DISPLAY_PM_ON && + power_mode <= MCDE_DISPLAY_PM_STANDBY) { + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_SET_DISPLAY_OFF, NULL, 0); + if (!ret) + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_ENTER_SLEEP_MODE, NULL, 0); + if (!ret) + ddev->power_mode = MCDE_DISPLAY_PM_STANDBY; + } + } else if (!ret && ddev->port->type == MCDE_PORTTYPE_DPI) + ddev->power_mode = power_mode; + else if (ddev->power_mode != power_mode) + return -EINVAL; + + /* SLEEP -> OFF */ + if (!ret && ddev->power_mode == MCDE_DISPLAY_PM_STANDBY && + power_mode == MCDE_DISPLAY_PM_OFF) { + if (ddev->platform_disable) + ret = ddev->platform_disable(ddev); + if (!ret) + ddev->power_mode = MCDE_DISPLAY_PM_OFF; + } + + return ret; +} + +static enum mcde_display_power_mode mcde_display_get_power_mode_default( + struct mcde_display_device *ddev) +{ + return ddev->power_mode; +} + +static int mcde_display_try_video_mode_default(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode) +{ + return (video_mode && video_mode->xres == ddev->video_mode.xres && + video_mode->yres == ddev->video_mode.yres) ? 0 : -EINVAL; +} + +static int mcde_display_set_video_mode_default(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode) +{ + int ret = 0; + + if (!video_mode) + return -EINVAL; + + ddev->video_mode = *video_mode; + ret = mcde_chnl_set_video_mode(ddev->chnl_state, &ddev->video_mode); + if (ret < 0) { + dev_warn(&ddev->dev, "%s:Failed to set video mode\n", __func__); + goto out; + } + ddev->update_flags |= UPDATE_FLAG_VIDEO_MODE; + +out: + return ret; +} + +static void mcde_display_get_video_mode_default( + struct mcde_display_device *ddev, struct mcde_video_mode *video_mode) +{ + if (video_mode) + *video_mode = ddev->video_mode; +} + +static int mcde_display_set_pixel_format_default( + struct mcde_display_device *ddev, enum mcde_ovly_pix_fmt format) +{ + int ret = 0; + ddev->pixel_format = format; + ret = mcde_chnl_set_pixel_format(ddev->chnl_state, + ddev->port_pixel_format); + if (ret < 0) { + dev_warn(&ddev->dev, "%s:Failed to set pixel format = %d\n", + __func__, format); + goto out; + } + + ddev->update_flags |= UPDATE_FLAG_PIXEL_FORMAT; +out: + return ret; +} + +static enum mcde_ovly_pix_fmt mcde_display_get_pixel_format_default( + struct mcde_display_device *ddev) +{ + return ddev->pixel_format; +} + +static enum mcde_port_pix_fmt mcde_display_get_port_pixel_format_default( + struct mcde_display_device *ddev) +{ + return ddev->port_pixel_format; +} + +static int mcde_display_set_rotation_default(struct mcde_display_device *ddev, + enum mcde_display_rotation rotation) +{ + int ret = 0; + + ret = mcde_chnl_set_rotation(ddev->chnl_state, rotation, + ddev->rotbuf1, ddev->rotbuf2); + if (ret < 0) { + dev_warn(&ddev->dev, "%s:Failed to set rotation = %d\n", + __func__, rotation); + goto out; + } + + if (!ret) { + bool was90 = ddev->rotation == MCDE_DISPLAY_ROT_90_CCW || + ddev->rotation == MCDE_DISPLAY_ROT_90_CW; + bool new90 = rotation == MCDE_DISPLAY_ROT_90_CCW || + rotation == MCDE_DISPLAY_ROT_90_CW; + if (was90 != new90) { + u16 tmp = ddev->update_area.w; + ddev->update_area.w = ddev->update_area.h; + ddev->update_area.h = tmp; + } + + ddev->rotation = rotation; + ddev->update_flags |= UPDATE_FLAG_ROTATION; + } +out: + return ret; +} + +static enum mcde_display_rotation mcde_display_get_rotation_default( + struct mcde_display_device *ddev) +{ + return ddev->rotation; +} + +static int mcde_display_set_synchronized_update_default( + struct mcde_display_device *ddev, bool enable) +{ + int ret = 0; + if (ddev->port->type == MCDE_PORTTYPE_DSI) { + if (ddev->port->sync_src == MCDE_SYNCSRC_TE0 || + ddev->port->sync_src == MCDE_SYNCSRC_TE1) { + u8 m = 0; + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_SET_TEAR_ON, &m, 1); + } else if (ddev->port->sync_src != MCDE_SYNCSRC_BTA) { + ret = -EINVAL; + } + } else { + ret = -EINVAL; + } + + if (ret < 0) { + dev_warn(&ddev->dev, + "%s:Failed to set synchornized update = %d\n", + __func__, enable); + goto out; + } + + ddev->synchronized_update = enable; + + return ret; +out: + return ret; +} + +static bool mcde_display_get_synchronized_update_default( + struct mcde_display_device *ddev) +{ + return ddev->synchronized_update; +} + +static int mcde_display_apply_config_default(struct mcde_display_device *ddev) +{ + int ret = 0; + ret = mcde_chnl_enable_synchronized_update(ddev->chnl_state, + ddev->synchronized_update); + + if (ret < 0) { + dev_warn(&ddev->dev, + "%s:Failed to enable synchronized update\n", + __func__); + goto out; + } + + if (ddev->update_flags) { + ret = mcde_chnl_apply(ddev->chnl_state); + if (ret < 0) { + dev_warn(&ddev->dev, "%s:Failed to apply to channel\n", + __func__); + goto out; + } + ddev->update_flags = 0; + ddev->first_update = true; + } +out: + return ret; +} + +static int mcde_display_invalidate_area_default( + struct mcde_display_device *ddev, + struct mcde_rectangle *area) +{ + dev_vdbg(&ddev->dev, "%s\n", __func__); + if (area) { + /* take union of rects */ + u16 t; + t = min(ddev->update_area.x, area->x); + /* note should be > 0 */ + ddev->update_area.w = max(ddev->update_area.x + + ddev->update_area.w, + area->x + area->w) - t; + ddev->update_area.x = t; + t = min(ddev->update_area.y, area->y); + ddev->update_area.h = max(ddev->update_area.y + + ddev->update_area.h, + area->y + area->h) - t; + ddev->update_area.y = t; + /* TODO: Implement real clipping when partial refresh is + activated.*/ + ddev->update_area.w = min((u16) ddev->video_mode.xres, + (u16) ddev->update_area.w); + ddev->update_area.h = min((u16) ddev->video_mode.yres, + (u16) ddev->update_area.h); + } else { + ddev->update_area.x = 0; + ddev->update_area.y = 0; + ddev->update_area.w = ddev->video_mode.xres; + ddev->update_area.h = ddev->video_mode.yres; + /* Invalidate_area(ddev, NULL) means reset area to empty + * rectangle really. After that the rectangle should grow by + * taking an union (above). This means that the code should + * really look like below, however the code above is a temp fix + * for rotation. + * TODO: fix + * ddev->update_area.x = ddev->video_mode.xres; + * ddev->update_area.y = ddev->video_mode.yres; + * ddev->update_area.w = 0; + * ddev->update_area.h = 0; + */ + } + + return 0; +} + +static int mcde_display_update_default(struct mcde_display_device *ddev) +{ + int ret; + /* TODO: Dirty */ + if (ddev->prepare_for_update) { + /* TODO: Send dirty rectangle */ + ret = ddev->prepare_for_update(ddev, 0, 0, + ddev->native_x_res, ddev->native_y_res); + if (ret < 0) { + dev_warn(&ddev->dev, + "%s:Failed to prepare for update\n", __func__); + goto out; + } + } + /* TODO: Calculate & set update rect */ + ret = mcde_chnl_update(ddev->chnl_state, &ddev->update_area); + if (ret < 0) { + dev_warn(&ddev->dev, "%s:Failed to update channel\n",__func__); + goto out; + } + if (ddev->first_update && ddev->on_first_update) + ddev->on_first_update(ddev); + + if (ddev->power_mode != MCDE_DISPLAY_PM_ON && ddev->set_power_mode) { + ret = ddev->set_power_mode(ddev, MCDE_DISPLAY_PM_ON); + if (ret < 0) { + dev_warn(&ddev->dev, + "%s:Failed to set power mode to on\n", + __func__); + goto out; + } + } + + dev_vdbg(&ddev->dev, "Overlay updated, chnl=%d\n", ddev->chnl_id); +out: + return ret; +} + +static int mcde_display_prepare_for_update_default( + struct mcde_display_device *ddev, + u16 x, u16 y, u16 w, u16 h) +{ + int ret = 0; + if (ddev->port->type == MCDE_PORTTYPE_DSI) { + u8 params[8] = { x >> 8, x & 0xff, + (x + w - 1) >> 8, (x + w - 1) & 0xff, + y >> 8, y & 0xff, + (y + h - 1) >> 8, (y + h - 1) & 0xff }; + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_SET_COLUMN_ADDRESS, ¶ms[0], 4); + if (ret) + return ret; + ret = mcde_display_dsi_dcs_write(ddev, + DCS_CMD_SET_PAGE_ADDRESS, ¶ms[4], 4); + } else + ret = -EINVAL; + return ret; +} + +static int mcde_display_on_first_update_default( + struct mcde_display_device *ddev) +{ + ddev->first_update = false; + return 0; +} + +void mcde_display_init_device(struct mcde_display_device *ddev) +{ + /* Setup default callbacks */ + ddev->get_native_resolution = + mcde_display_get_native_resolution_default; + ddev->get_default_pixel_format = + mcde_display_get_default_pixel_format_default; + ddev->get_physical_size = mcde_display_get_physical_size_default; + ddev->set_power_mode = mcde_display_set_power_mode_default; + ddev->get_power_mode = mcde_display_get_power_mode_default; + ddev->try_video_mode = mcde_display_try_video_mode_default; + ddev->set_video_mode = mcde_display_set_video_mode_default; + ddev->get_video_mode = mcde_display_get_video_mode_default; + ddev->set_pixel_format = mcde_display_set_pixel_format_default; + ddev->get_pixel_format = mcde_display_get_pixel_format_default; + ddev->get_port_pixel_format = + mcde_display_get_port_pixel_format_default; + ddev->set_rotation = mcde_display_set_rotation_default; + ddev->get_rotation = mcde_display_get_rotation_default; + ddev->set_synchronized_update = + mcde_display_set_synchronized_update_default; + ddev->get_synchronized_update = + mcde_display_get_synchronized_update_default; + ddev->apply_config = mcde_display_apply_config_default; + ddev->invalidate_area = mcde_display_invalidate_area_default; + ddev->update = mcde_display_update_default; + ddev->prepare_for_update = mcde_display_prepare_for_update_default; + ddev->on_first_update = mcde_display_on_first_update_default; +} + +int mcde_display_dsi_dcs_write(struct mcde_display_device *ddev, + u8 cmd, u8 *data, int len) +{ + return mcde_dsi_dcs_write(ddev->chnl_state, cmd, data, len); +} +EXPORT_SYMBOL(mcde_display_dsi_dcs_write); + +int mcde_display_dsi_dcs_read(struct mcde_display_device *ddev, + u8 cmd, u8 *data, int *len) +{ + return mcde_dsi_dcs_read(ddev->chnl_state, cmd, data, len); +} +EXPORT_SYMBOL(mcde_display_dsi_dcs_read); + diff --git a/drivers/video/mcde/mcde_dss.c b/drivers/video/mcde/mcde_dss.c new file mode 100644 index 00000000000..4058a673aae --- /dev/null +++ b/drivers/video/mcde/mcde_dss.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE display sub system driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/err.h> + +#include <video/mcde_dss.h> + +#define to_overlay(x) container_of(x, struct mcde_overlay, kobj) + +void overlay_release(struct kobject *kobj) +{ + struct mcde_overlay *ovly = to_overlay(kobj); + + kfree(ovly); +} + +struct kobj_type ovly_type = { + .release = overlay_release, +}; + +static int apply_overlay(struct mcde_overlay *ovly, + struct mcde_overlay_info *info, bool force) +{ + int ret = 0; + if (ovly->ddev->invalidate_area) { + /* TODO: transform ovly coord to screen coords (vmode): + * add offset + */ + struct mcde_rectangle dirty = info->dirty; + ret = ovly->ddev->invalidate_area(ovly->ddev, &dirty); + } + + if (ovly->info.paddr != info->paddr || force) + mcde_ovly_set_source_buf(ovly->state, info->paddr); + + if (ovly->info.stride != info->stride || ovly->info.fmt != info->fmt || + force) + mcde_ovly_set_source_info(ovly->state, info->stride, info->fmt); + if (ovly->info.src_x != info->src_x || + ovly->info.src_y != info->src_y || + ovly->info.w != info->w || + ovly->info.h != info->h || force) + mcde_ovly_set_source_area(ovly->state, + info->src_x, info->src_y, info->w, info->h); + if (ovly->info.dst_x != info->dst_x || ovly->info.dst_y != info->dst_y + || ovly->info.dst_z != info->dst_z || + force) + mcde_ovly_set_dest_pos(ovly->state, + info->dst_x, info->dst_y, info->dst_z); + + mcde_ovly_apply(ovly->state); + ovly->info = *info; + + return ret; +} + +/* MCDE DSS operations */ + +int mcde_dss_enable_display(struct mcde_display_device *ddev, + bool display_initialized) +{ + int ret; + struct mcde_chnl_state *chnl; + + if (ddev->enabled) + return 0; + + /* Acquire MCDE resources */ + chnl = mcde_chnl_get(ddev->chnl_id, ddev->fifo, ddev->port); + if (IS_ERR(chnl)) { + ret = PTR_ERR(chnl); + dev_warn(&ddev->dev, "Failed to acquire MCDE channel\n"); + goto get_chnl_failed; + } + ddev->chnl_state = chnl; + if (!display_initialized) { + /* Initiate display communication */ + ret = ddev->set_power_mode(ddev, MCDE_DISPLAY_PM_STANDBY); + if (ret < 0) { + dev_warn(&ddev->dev, "Failed to initialize display\n"); + goto display_failed; + } + + dev_dbg(&ddev->dev, "Display enabled, chnl=%d\n", + ddev->chnl_id); + } else { + printk(KERN_INFO "Display already enabled, chnl=%d\n", + ddev->chnl_id); + ddev->power_mode = MCDE_DISPLAY_PM_ON; + ret = 0; + } + ddev->enabled = true; +out: + return ret; + +display_failed: + mcde_chnl_put(ddev->chnl_state); + ddev->chnl_state = NULL; +get_chnl_failed: + goto out; +} + +void mcde_dss_disable_display(struct mcde_display_device *ddev) +{ + if (!ddev->enabled) + return; + + /* TODO: Disable overlays */ + + (void)ddev->set_power_mode(ddev, MCDE_DISPLAY_PM_OFF); + mcde_chnl_put(ddev->chnl_state); + ddev->chnl_state = NULL; + + ddev->enabled = false; + + dev_dbg(&ddev->dev, "Display disabled, chnl=%d\n", ddev->chnl_id); +} + +int mcde_dss_apply_channel(struct mcde_display_device *ddev) +{ + if (ddev->apply_config) + return ddev->apply_config(ddev); + else + return -EINVAL; +} + +struct mcde_overlay *mcde_dss_create_overlay(struct mcde_display_device *ddev, + struct mcde_overlay_info *info) +{ + struct mcde_overlay *ovly; + + ovly = kzalloc(sizeof(struct mcde_overlay), GFP_KERNEL); + if (!ovly) + return NULL; + + kobject_init(&ovly->kobj, &ovly_type); /* Local ref */ + kobject_get(&ovly->kobj); /* Creator ref */ + INIT_LIST_HEAD(&ovly->list); + list_add(&ddev->ovlys, &ovly->list); + ovly->info = *info; + ovly->ddev = ddev; + + return ovly; +} + +void mcde_dss_destroy_overlay(struct mcde_overlay *ovly) +{ + list_del(&ovly->list); + if (ovly->state) + mcde_dss_disable_overlay(ovly); + kobject_put(&ovly->kobj); +} + +int mcde_dss_enable_overlay(struct mcde_overlay *ovly) +{ + int ret = 0; + + if (!ovly->ddev->chnl_state) + return -EINVAL; + + if (!ovly->state) { + struct mcde_ovly_state *state; + state = mcde_ovly_get(ovly->ddev->chnl_state); + if (IS_ERR(state)) { + ret = PTR_ERR(state); + dev_warn(&ovly->ddev->dev, + "Failed to acquire overlay\n"); + goto get_ovly_failed; + } + ovly->state = state; + } + + apply_overlay(ovly, &ovly->info, true); + + dev_vdbg(&ovly->ddev->dev, "Overlay enabled, chnl=%d\n", + ovly->ddev->chnl_id); + + goto out; +get_ovly_failed: +out: + return ret; +} + +int mcde_dss_apply_overlay(struct mcde_overlay *ovly, + struct mcde_overlay_info *info) +{ + if (info == NULL) + info = &ovly->info; + return apply_overlay(ovly, info, false); +} + +void mcde_dss_disable_overlay(struct mcde_overlay *ovly) +{ + if (!ovly->state) + return; + + mcde_ovly_put(ovly->state); + + dev_dbg(&ovly->ddev->dev, "Overlay disabled, chnl=%d\n", + ovly->ddev->chnl_id); + + ovly->state = NULL; +} + +int mcde_dss_update_overlay(struct mcde_overlay *ovly) +{ + int ret = 0; + + dev_vdbg(&ovly->ddev->dev, "Overlay update, chnl=%d\n", + ovly->ddev->chnl_id); + + if (!ovly->state || !ovly->ddev->update || !ovly->ddev->invalidate_area) + return -EINVAL; + + ret = ovly->ddev->update(ovly->ddev); + if (ret) + goto out; + ret = ovly->ddev->invalidate_area(ovly->ddev, NULL); + +out: + return ret; +} + +void mcde_dss_get_native_resolution(struct mcde_display_device *ddev, + u16 *x_res, u16 *y_res) +{ + ddev->get_native_resolution(ddev, x_res, y_res); +} + +enum mcde_ovly_pix_fmt mcde_dss_get_default_pixel_format( + struct mcde_display_device *ddev) +{ + return ddev->get_default_pixel_format(ddev); +} + +void mcde_dss_get_physical_size(struct mcde_display_device *ddev, + u16 *physical_width, u16 *physical_height) +{ + ddev->get_physical_size(ddev, physical_width, physical_height); +} + +int mcde_dss_try_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode) +{ + return ddev->try_video_mode(ddev, video_mode); +} + +int mcde_dss_set_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *vmode) +{ + int ret; + struct mcde_video_mode old_vmode; + + ddev->get_video_mode(ddev, &old_vmode); + if (memcmp(vmode, &old_vmode, sizeof(old_vmode)) == 0) + return 0; + + ret = ddev->set_video_mode(ddev, vmode); + if (ret) + return ret; + + return ddev->invalidate_area(ddev, NULL); +} + +void mcde_dss_get_video_mode(struct mcde_display_device *ddev, + struct mcde_video_mode *video_mode) +{ + ddev->get_video_mode(ddev, video_mode); +} + +int mcde_dss_set_pixel_format(struct mcde_display_device *ddev, + enum mcde_ovly_pix_fmt pix_fmt) +{ + enum mcde_ovly_pix_fmt old_pix_fmt; + + old_pix_fmt = ddev->get_pixel_format(ddev); + if (old_pix_fmt == pix_fmt) + return 0; + + return ddev->set_pixel_format(ddev, pix_fmt); +} + +int mcde_dss_get_pixel_format(struct mcde_display_device *ddev) +{ + return ddev->get_pixel_format(ddev); +} + +int mcde_dss_set_rotation(struct mcde_display_device *ddev, + enum mcde_display_rotation rotation) +{ + enum mcde_display_rotation old_rotation; + + old_rotation = ddev->get_rotation(ddev); + if (old_rotation == rotation) + return 0; + + return ddev->set_rotation(ddev, rotation); +} + +enum mcde_display_rotation mcde_dss_get_rotation( + struct mcde_display_device *ddev) +{ + return ddev->get_rotation(ddev); +} + +int mcde_dss_set_synchronized_update(struct mcde_display_device *ddev, + bool enable) +{ + int ret; + ret = ddev->set_synchronized_update(ddev, enable); + if (ret) + return ret; + if (ddev->chnl_state) + mcde_chnl_enable_synchronized_update(ddev->chnl_state, enable); + return 0; +} + +bool mcde_dss_get_synchronized_update(struct mcde_display_device *ddev) +{ + return ddev->get_synchronized_update(ddev); +} + +int __init mcde_dss_init(void) +{ + return 0; +} + +void mcde_dss_exit(void) +{ +} + diff --git a/drivers/video/mcde/mcde_fb.c b/drivers/video/mcde/mcde_fb.c new file mode 100644 index 00000000000..cbf493d4f4e --- /dev/null +++ b/drivers/video/mcde/mcde_fb.c @@ -0,0 +1,666 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE frame buffer driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/fb.h> +#include <linux/mm.h> +#include <linux/dma-mapping.h> + +#include <video/mcde_fb.h> + +/* When this define is enabled, a max size frame buffer is allocated and used + * for all resolutions. + * Without this define, the frame buffer is reallocated when resolution is + * changed */ +/*#define MCDE_FB_AVOID_REALLOC*/ + +#define MCDE_FB_BPP_MAX 16 +#define MCDE_FB_VXRES_MAX 1920 +#define MCDE_FB_VYRES_MAX 2160 + +static struct fb_ops fb_ops; + +struct pix_fmt_info { + enum mcde_ovly_pix_fmt pix_fmt; + + __u32 bpp; + struct fb_bitfield r; + struct fb_bitfield g; + struct fb_bitfield b; + struct fb_bitfield a; + __u32 nonstd; +}; + +struct pix_fmt_info pix_fmt_map[] = { + { + .pix_fmt = MCDE_OVLYPIXFMT_RGB565, + .bpp = 16, + .r = { .offset = 11, .length = 5 }, + .g = { .offset = 5, .length = 6 }, + .b = { .offset = 0, .length = 5 }, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_RGBA5551, + .bpp = 16, + .r = { .offset = 11, .length = 5 }, + .g = { .offset = 6, .length = 5 }, + .b = { .offset = 1, .length = 5 }, + .a = { .offset = 0, .length = 1 }, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_RGBA4444, + .bpp = 16, + .r = { .offset = 12, .length = 4 }, + .g = { .offset = 8, .length = 4 }, + .b = { .offset = 4, .length = 4 }, + .a = { .offset = 0, .length = 4 }, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_YCbCr422, + .bpp = 16, + .nonstd = MCDE_OVLYPIXFMT_YCbCr422, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_RGB888, + .bpp = 24, + .r = { .offset = 0, .length = 8 }, + .g = { .offset = 8, .length = 8 }, + .b = { .offset = 16, .length = 8 }, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_RGBX8888, + .bpp = 32, + .r = { .offset = 0, .length = 8 }, + .g = { .offset = 8, .length = 8 }, + .b = { .offset = 16, .length = 8 }, + }, { + .pix_fmt = MCDE_OVLYPIXFMT_RGBA8888, + .bpp = 32, + .r = { .offset = 0, .length = 8 }, + .g = { .offset = 8, .length = 8 }, + .b = { .offset = 16, .length = 8 }, + .a = { .offset = 24, .length = 8 }, + } +}; + +/* Helpers */ + +static struct pix_fmt_info *find_pix_fmt_info(enum mcde_ovly_pix_fmt pix_fmt) +{ + int i; + for (i = 0; i < ARRAY_SIZE(pix_fmt_map); i++) { + if (pix_fmt_map[i].pix_fmt == pix_fmt) + return &pix_fmt_map[i]; + } + return NULL; +} + +static bool bitfield_cmp(struct fb_bitfield *bf1, struct fb_bitfield *bf2) +{ + return bf1->offset == bf2->offset && + bf1->length == bf2->length && + bf1->msb_right == bf2->msb_right; +} + +static struct pix_fmt_info *var_to_pix_fmt_info(struct fb_var_screeninfo *var) +{ + int i; + struct pix_fmt_info *info; + + if (var->nonstd) + return find_pix_fmt_info(var->nonstd); + + for (i = 0; i < ARRAY_SIZE(pix_fmt_map); i++) { + info = &pix_fmt_map[i]; + if (info->bpp == var->bits_per_pixel && + bitfield_cmp(&info->r, &var->red) && + bitfield_cmp(&info->g, &var->green) && + bitfield_cmp(&info->b, &var->blue) && + bitfield_cmp(&info->a, &var->transp)) + return info; + } + + for (i = 0; i < ARRAY_SIZE(pix_fmt_map); i++) { + info = &pix_fmt_map[i]; + if (var->bits_per_pixel == info->bpp) + return info; + } + + return NULL; +} + +static void pix_fmt_info_to_var(struct pix_fmt_info *pix_fmt_info, + struct fb_var_screeninfo *var) +{ + var->bits_per_pixel = pix_fmt_info->bpp; + var->nonstd = pix_fmt_info->nonstd; + var->red = pix_fmt_info->r; + var->green = pix_fmt_info->g; + var->blue = pix_fmt_info->b; + var->transp = pix_fmt_info->a; +} + +static int init_var_fmt(struct fb_var_screeninfo *var, + u16 w, u16 h, u16 vw, u16 vh, enum mcde_ovly_pix_fmt pix_fmt, + u32 rotate) +{ + struct pix_fmt_info *info; + + info = find_pix_fmt_info(pix_fmt); + if (!info) + return -EINVAL; + + var->bits_per_pixel = info->bpp; + var->nonstd = info->nonstd; + var->red = info->r; + var->green = info->g; + var->blue = info->b; + var->transp = info->a; + var->grayscale = false; + + var->xres = w; + var->yres = h; + var->xres_virtual = vw; + var->yres_virtual = vh; + var->xoffset = 0; + var->yoffset = 0; + var->activate = FB_ACTIVATE_NOW; + var->rotate = rotate; + return 0; +}; + +static int reallocate_fb_mem(struct fb_info *fbi, u32 size) +{ + dma_addr_t paddr; + void __iomem *vaddr; +#ifdef MCDE_FB_AVOID_REALLOC + u32 size_max; +#endif + + size = PAGE_ALIGN(size); + + if (size == fbi->screen_size) + return 0; + + /* TODO: hwmem */ +#ifdef MCDE_FB_AVOID_REALLOC + if (!fbi->screen_base) { + size_max = MCDE_FB_BPP_MAX / 8 * MCDE_FB_VXRES_MAX * + MCDE_FB_VYRES_MAX; + vaddr = dma_alloc_coherent(fbi->dev, size_max, &paddr, + GFP_KERNEL|GFP_DMA); + if (!vaddr) + return -ENOMEM; + + fbi->screen_base = vaddr; + fbi->fix.smem_start = paddr; + } +#else + vaddr = dma_alloc_coherent(fbi->dev, size, &paddr, GFP_KERNEL|GFP_DMA); + if (!vaddr) + return -ENOMEM; +#endif + +#ifndef MCDE_FB_AVOID_REALLOC + if (fbi->screen_base) + dma_free_coherent(fbi->dev, fbi->screen_size, + fbi->screen_base, fbi->fix.smem_start); +#endif + +#ifndef MCDE_FB_AVOID_REALLOC + fbi->screen_base = vaddr; + fbi->fix.smem_start = paddr; +#endif + fbi->screen_size = size; + fbi->fix.smem_len = size; + + return 0; +} + +static void free_fb_mem(struct fb_info *fbi) +{ + if (fbi->fix.smem_start) { + dma_free_coherent(fbi->dev, fbi->screen_size, + fbi->screen_base, fbi->fix.smem_start); + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + fbi->screen_base = 0; + fbi->screen_size = 0; + } +} + +static void init_fb(struct fb_info *fbi) +{ + struct mcde_fb *mfb = to_mcde_fb(fbi); + + strlcpy(fbi->fix.id, "mcde_fb", sizeof(fbi->fix.id)); + fbi->fix.type = FB_TYPE_PACKED_PIXELS; + fbi->fix.visual = FB_VISUAL_TRUECOLOR; + fbi->fix.xpanstep = 1; + fbi->fix.ypanstep = 1; + fbi->flags = FBINFO_HWACCEL_DISABLED; + fbi->fbops = &fb_ops; + fbi->pseudo_palette = &mfb->pseudo_palette[0]; +} + +static void get_ovly_info(struct fb_info *fbi, struct mcde_overlay *ovly, + struct mcde_overlay_info *info) +{ + struct mcde_fb *mfb = to_mcde_fb(fbi); + memset(info, 0, sizeof(*info)); + info->paddr = fbi->fix.smem_start + + fbi->fix.line_length * fbi->var.yoffset; + /* TODO: move mem check to check_var/pan_display */ + if (info->paddr + fbi->fix.line_length * fbi->var.yres > + fbi->fix.smem_start + fbi->fix.smem_len) + info->paddr = fbi->fix.smem_start; + info->fmt = mfb->pix_fmt; + info->stride = fbi->fix.line_length; + if (ovly) { + info->src_x = ovly->info.src_x; + info->src_y = ovly->info.src_y; + info->dst_x = ovly->info.dst_x; + info->dst_y = ovly->info.dst_y; + info->dst_z = ovly->info.dst_z; + } else { + info->src_x = 0; + info->src_y = 0; + info->dst_x = 0; + info->dst_y = 0; + info->dst_z = 0; + } + info->w = fbi->var.xres; + info->h = fbi->var.yres; + info->dirty.x = 0; + info->dirty.y = 0; + info->dirty.w = fbi->var.xres; + info->dirty.h = fbi->var.yres; +} + +void vmode_to_var(struct mcde_video_mode *video_mode, + struct fb_var_screeninfo *var) +{ + /* TODO: use only 1 vbp and 1 vfp */ + var->xres = video_mode->xres; + var->yres = video_mode->yres; + var->pixclock = video_mode->pixclock; + var->upper_margin = video_mode->vbp1 + video_mode->vbp2; + var->lower_margin = video_mode->vfp1 + video_mode->vfp2; + var->left_margin = video_mode->hbp; + var->right_margin = video_mode->hfp; + var->vmode |= video_mode->interlaced ? + FB_VMODE_INTERLACED : FB_VMODE_NONINTERLACED; +} + +void var_to_vmode(struct fb_var_screeninfo *var, + struct mcde_video_mode *video_mode) +{ + video_mode->xres = var->xres; + video_mode->yres = var->yres; + video_mode->pixclock = var->pixclock; + video_mode->vbp1 = var->upper_margin / 2; + video_mode->vfp1 = var->lower_margin / 2; + video_mode->vbp2 = video_mode->vbp1 + var->upper_margin % 2; + video_mode->vfp2 = video_mode->vfp1 + var->lower_margin % 2; + video_mode->hbp = var->left_margin; + video_mode->hfp = var->right_margin; + video_mode->interlaced = (var->vmode & FB_VMODE_INTERLACED) == + FB_VMODE_INTERLACED; +} + +enum mcde_display_rotation var_to_rotation(struct fb_var_screeninfo *var) +{ + switch (var->rotate) { + case FB_ROTATE_UR: + return MCDE_DISPLAY_ROT_0; + case FB_ROTATE_CW: + return MCDE_DISPLAY_ROT_90_CW; + case FB_ROTATE_UD: + return MCDE_DISPLAY_ROT_180_CW; + case FB_ROTATE_CCW: + return MCDE_DISPLAY_ROT_90_CCW; + default: + return MCDE_DISPLAY_ROT_0; + } +} + +static struct mcde_display_device *fb_to_display(struct fb_info *fbi) +{ + int i; + struct mcde_fb *mfb = to_mcde_fb(fbi); + + for (i = 0; i < mfb->num_ovlys; i++) { + if (mfb->ovlys[i]) + return mfb->ovlys[i]->ddev; + } + return NULL; +} + +static int check_var(struct fb_var_screeninfo *var, struct fb_info *fbi, + struct mcde_display_device *ddev) +{ + int ret; + u16 w = -1, h = -1; + struct mcde_video_mode vmode; + struct pix_fmt_info *fmtinfo; + + /* TODO: check sizes/offsets/memory validity */ + + /* Device physical size */ + mcde_dss_get_physical_size(ddev, &w, &h); + var->width = w; + var->height = h; + + /* Video mode */ + var_to_vmode(var, &vmode); + ret = mcde_dss_try_video_mode(ddev, &vmode); + if (ret < 0) { + dev_vdbg(&(ddev->dev), "check_var failed " + "mcde_dss_try_video_mode with size = %x \n", ret); + return ret; + } + vmode_to_var(&vmode, var); + + /* Pixel format */ + fmtinfo = var_to_pix_fmt_info(var); + if (!fmtinfo) { + dev_vdbg(&(ddev->dev), "check_var failed fmtinfo\n"); + return -EINVAL; + } + pix_fmt_info_to_var(fmtinfo, var); + + /* Rotation */ + if (var->rotate > 3) { + dev_vdbg(&(ddev->dev), "check_var failed var->rotate\n"); + return -EINVAL; + } + + /* Not used */ + var->grayscale = 0; + var->sync = 0; + + return 0; +} + +static int apply_var(struct fb_info *fbi, struct mcde_display_device *ddev) +{ + int ret, i; + struct mcde_fb *mfb = to_mcde_fb(fbi); + struct fb_var_screeninfo *var; + struct mcde_video_mode vmode; + struct pix_fmt_info *fmt; + u32 line_len, size; + + dev_vdbg(&(ddev->dev), "%s\n", __func__); + + var = &fbi->var; + + /* Reallocate memory */ + line_len = (fbi->var.bits_per_pixel * var->xres_virtual) / 8; + size = line_len * var->yres_virtual; + ret = reallocate_fb_mem(fbi, size); + if (ret) { + dev_vdbg(&(ddev->dev), "apply_var failed with" + "reallocate mem with size = %d \n", size); + return ret; + } + fbi->fix.line_length = line_len; + + if (ddev) { + /* Apply pixel format */ + fmt = var_to_pix_fmt_info(var); + mfb->pix_fmt = fmt->pix_fmt; + mcde_dss_set_pixel_format(ddev, mfb->pix_fmt); + + /* Apply video mode */ + memset(&vmode, 0, sizeof(struct mcde_video_mode)); + var_to_vmode(var, &vmode); + mcde_dss_set_video_mode(ddev, &vmode); + + /* Apply rotation */ + mcde_dss_set_rotation(ddev, var_to_rotation(var)); + + mcde_dss_apply_channel(ddev); + } + + /* Apply overlay info */ + for (i = 0; i < mfb->num_ovlys; i++) { + struct mcde_overlay *ovly = mfb->ovlys[i]; + struct mcde_overlay_info info; + + get_ovly_info(fbi, ovly, &info); + (void) mcde_dss_apply_overlay(ovly, &info); + ret = mcde_dss_update_overlay(ovly); + } + + return 0; +} + +/* FB ops */ + +static int mcde_fb_open(struct fb_info *fbi, int user) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); + return 0; +} + +static int mcde_fb_release(struct fb_info *fbi, int user) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); + return 0; +} + +static int mcde_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) +{ + struct mcde_display_device *ddev = fb_to_display(fbi); + + dev_vdbg(fbi->dev, "%s\n", __func__); + + if (!ddev) { + printk(KERN_ERR "mcde_fb_check_var failed !ddev\n"); + return -ENODEV; + } + + return check_var(var, fbi, ddev); +} + +static int mcde_fb_set_par(struct fb_info *fbi) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); + + return apply_var(fbi, fb_to_display(fbi)); +} + +static int mcde_fb_blank(int blank, struct fb_info *fbi) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); + /* REVIEW: is this supposed to be empty? */ + return 0; +} + +static int mcde_fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *fbi) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); + + if (var->xoffset == fbi->var.xoffset && + var->yoffset == fbi->var.yoffset) + return 0; + + fbi->var.xoffset = var->xoffset; + fbi->var.yoffset = var->yoffset; + return apply_var(fbi, fb_to_display(fbi)); +} + +static void mcde_fb_rotate(struct fb_info *fbi, int rotate) +{ + dev_vdbg(fbi->dev, "%s\n", __func__); +} + +static struct fb_ops fb_ops = { + /* creg, cmap */ + .owner = THIS_MODULE, + .fb_open = mcde_fb_open, + .fb_release = mcde_fb_release, + .fb_read = fb_sys_read, + .fb_write = fb_sys_write, + .fb_fillrect = sys_fillrect, + .fb_copyarea = sys_copyarea, + .fb_imageblit = sys_imageblit, + .fb_check_var = mcde_fb_check_var, + .fb_set_par = mcde_fb_set_par, + .fb_blank = mcde_fb_blank, + .fb_pan_display = mcde_fb_pan_display, + .fb_rotate = mcde_fb_rotate, +}; + +/* FB driver */ + +static struct platform_device mcde_fb_device = { + .name = "mcde_fb", + .id = -1, +}; + +struct fb_info *mcde_fb_create(struct mcde_display_device *ddev, + u16 w, u16 h, u16 vw, u16 vh, enum mcde_ovly_pix_fmt pix_fmt, + u32 rotate, bool display_initialized) +{ + int ret = 0; + struct fb_info *fbi; + struct mcde_fb *mfb; + struct mcde_overlay *ovly = NULL; + struct mcde_overlay_info ovly_info; + + dev_vdbg(&ddev->dev, "%s\n", __func__); + if (!ddev->initialized) { + dev_warn(&ddev->dev, "%s: Device not initialized\n", __func__); + return ERR_PTR(-EINVAL); + } + + /* Init fb */ + fbi = framebuffer_alloc(sizeof(struct mcde_fb), &mcde_fb_device.dev); + if (fbi == NULL) { + ret = -ENOMEM; + goto fb_alloc_failed; + } + init_fb(fbi); + mfb = to_mcde_fb(fbi); + + ret = mcde_dss_enable_display(ddev, display_initialized); + if (ret) + goto display_enable_failed; + + /* Prepare var and allocate frame buffer memory */ + init_var_fmt(&fbi->var, w, h, vw, vh, pix_fmt, rotate); + check_var(&fbi->var, fbi, ddev); + ret = apply_var(fbi, ddev); + if (ret) + goto apply_var_failed; + + /* Setup overlay */ + get_ovly_info(fbi, NULL, &ovly_info); + ovly = mcde_dss_create_overlay(ddev, &ovly_info); + if (!ovly) { + ret = PTR_ERR(ovly); + goto ovly_alloc_failed; + } + mfb->ovlys[0] = ovly; + mfb->num_ovlys = 1; + + ret = mcde_dss_enable_overlay(ovly); + if (ret) + goto ovly_enable_failed; + + /* Register framebuffer */ + ret = register_framebuffer(fbi); + if (ret) + goto fb_register_failed; + + if (!display_initialized) { + ret = mcde_dss_update_overlay(ovly); + if (ret) + goto ovly_update_failed; + } + + goto out; +ovly_update_failed: + unregister_framebuffer(fbi); +fb_register_failed: + mcde_dss_disable_overlay(ovly); +ovly_enable_failed: + mcde_dss_destroy_overlay(ovly); +ovly_alloc_failed: + free_fb_mem(fbi); +apply_var_failed: + mcde_dss_disable_display(ddev); +display_enable_failed: + framebuffer_release(fbi); +fb_alloc_failed: +out: + return ret ? ERR_PTR(ret) : fbi; +} +EXPORT_SYMBOL(mcde_fb_create); + +int mcde_fb_attach_overlay(struct fb_info *fb_info, struct mcde_overlay *ovl) +{ + /* TODO: Attach extra overlay targets */ + return -EINVAL; +} + +void mcde_fb_destroy(struct fb_info *fb_info) +{ + /* TODO: clean up */ +} + +/* Overlay fbs' platform device */ +static int mcde_fb_probe(struct platform_device *pdev) +{ + return 0; +} + +static int mcde_fb_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver mcde_fb_driver = { + .probe = mcde_fb_probe, + .remove = mcde_fb_remove, + .driver = { + .name = "mcde_fb", + .owner = THIS_MODULE, + }, +}; + +/* MCDE fb init */ + +int __init mcde_fb_init(void) +{ + int ret; + + ret = platform_driver_register(&mcde_fb_driver); + if (ret) + goto fb_driver_failed; + ret = platform_device_register(&mcde_fb_device); + if (ret) + goto fb_device_failed; + + goto out; +fb_device_failed: + platform_driver_unregister(&mcde_fb_driver); +fb_driver_failed: +out: + return ret; +} + +void mcde_fb_exit(void) +{ + platform_device_unregister(&mcde_fb_device); + platform_driver_unregister(&mcde_fb_driver); +} + diff --git a/drivers/video/mcde/mcde_hw.c b/drivers/video/mcde/mcde_hw.c new file mode 100644 index 00000000000..e8e67047adf --- /dev/null +++ b/drivers/video/mcde/mcde_hw.c @@ -0,0 +1,2170 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE base driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/err.h> +#include <linux/wait.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/regulator/consumer.h> +#include <linux/clk.h> + +#include "dsilink_regs.h" +#include "mcde_regs.h" +#include <video/mcde.h> + +#include <mach/ab8500.h> /* TODO: Remove */ +static void disable_channel(struct mcde_chnl_state *chnl); +static void update_prmcu_registers(void); + +#define MSEC_TO_JIFFIES(__x) (((__x) * HZ + HZ - 1) / 1000) + +#define OVLY_TIMEOUT MSEC_TO_JIFFIES(500) +#define CHNL_TIMEOUT MSEC_TO_JIFFIES(500) + +u8 *mcdeio, **dsiio; +DEFINE_SPINLOCK(mcde_lock); /* REVIEW: Remove or use */ +struct platform_device *mcde_dev; +u8 num_dsilinks; + +#ifdef CONFIG_REGULATOR +static struct regulator *regulator; +static struct clk *clock_dsi; +static struct clk *clock_mcde; +static struct clk *clock_dsi_lp; +#endif +static inline u32 dsi_rreg(int __i, u32 __reg) +{ + return readl(dsiio[__i] + __reg); +} +static inline void dsi_wreg(int __i, u32 __reg, u32 __val) +{ + writel(__val, dsiio[__i] + __reg); +} +#define dsi_rfld(__i, __reg, __fld) \ + ((dsi_rreg(__i, __reg) & __reg##_##__fld##_MASK) >> \ + __reg##_##__fld##_SHIFT) +#define dsi_wfld(__i, __reg, __fld, __val) \ + dsi_wreg(__i, __reg, (dsi_rreg(__i, __reg) & \ + ~__reg##_##__fld##_MASK) | (((__val) << __reg##_##__fld##_SHIFT) & \ + __reg##_##__fld##_MASK)) + +static inline u32 mcde_rreg(u32 __reg) +{ + return readl(mcdeio + __reg); +} +static inline void mcde_wreg(u32 __reg, u32 __val) +{ + writel(__val, mcdeio + __reg); +} +#define mcde_rfld(__reg, __fld) \ + ((mcde_rreg(__reg) & __reg##_##__fld##_MASK) >> \ + __reg##_##__fld##_SHIFT) +#define mcde_wfld(__reg, __fld, __val) \ + mcde_wreg(__reg, (mcde_rreg(__reg) & \ + ~__reg##_##__fld##_MASK) | (((__val) << __reg##_##__fld##_SHIFT) & \ + __reg##_##__fld##_MASK)) + +struct ovly_regs { + u8 ch_id; + bool enabled; + u32 baseaddress0; + u32 baseaddress1; + bool reset_buf_id; + u8 bits_per_pixel; + u8 bpp; + bool bgr; + bool bebo; + bool opq; + u8 col_conv; + u8 pixoff; + u16 ppl; + u16 lpf; + u16 cropx; + u16 cropy; + u16 xpos; + u16 ypos; + u8 z; +}; + +struct mcde_ovly_state { + bool inuse; + u8 idx; /* MCDE overlay index */ + struct mcde_chnl_state *chnl; /* Owner channel */ + u32 transactionid; /* Apply time stamp */ + u32 transactionid_regs; /* Register update time stamp */ + u32 transactionid_hw; /* HW completed time stamp */ + wait_queue_head_t waitq_hw; /* Waitq for transactionid_hw */ + + /* Staged settings */ + u32 paddr; + u16 stride; + enum mcde_ovly_pix_fmt pix_fmt; + + u16 src_x; + u16 src_y; + u16 dst_x; + u16 dst_y; + u16 dst_z; + u16 w; + u16 h; + + /* Applied settings */ + struct ovly_regs regs; +}; +static struct mcde_ovly_state overlays[] = { + { .idx = 0 }, + { .idx = 1 }, + { .idx = 2 }, + { .idx = 3 }, + { .idx = 4 }, + { .idx = 5 }, +}; + +struct chnl_regs { + bool floen; + u16 x; + u16 y; + u16 ppl; + u16 lpf; + u8 bpp; + bool synchronized_update; + bool roten; + u8 rotdir; + u32 rotbuf1; /* TODO: Replace with eSRAM alloc */ + u32 rotbuf2; /* TODO: Replace with eSRAM alloc */ + + /* DSI */ + u8 dsipacking; +}; + +enum mcde_hw_tv_mode {/* REVIEW: What's wrong with regs defines? */ + MCDE_HW_SDTV_MODE = 0, + MCDE_HW_HDTV_MODE_480P = 1, + MCDE_HW_HDTV_MODE_720P = 2, + MCDE_HW_SDTV_MODE_DDR_LSB_1ST = 3, + MCDE_HW_SDTV_MODE_DDR_MSB_1ST = 4, + MCDE_HW_TV_MODE_LEN = 5, +}; + +struct col_regs { + u16 yr_red; + u16 yr_green; + u16 yr_blue; + u16 cr_red; + u16 cr_green; + u16 cr_blue; + u16 cb_red; + u16 cb_green; + u16 cb_blue; + u16 off_red; + u16 off_green; + u16 off_blue; +}; + +struct tv_regs { + u16 hbw; /* horizontal blanking width */ + /* field 1 */ + u16 bel1; /* field total vertical blanking lines */ + u16 fsl1; /* field vbp */ + /* field 1 *//* REVIEW: Field 2? */ + u16 bel2; + u16 fsl2; + bool interlaced_en; + enum mcde_hw_tv_mode tv_mode; +}; + +struct mcde_chnl_state { + bool inuse; + enum mcde_chnl id; + struct mcde_port port; + struct mcde_ovly_state *ovly0; + struct mcde_ovly_state *ovly1; + const struct chnl_config *cfg; + u32 transactionid; + u32 transactionid_regs; + u32 transactionid_hw; + wait_queue_head_t waitq_hw; /* Waitq for transactionid_hw */ + + /* Staged settings */ + bool synchronized_update; + enum mcde_port_pix_fmt pix_fmt; + u16 update_x; + u16 update_y; + u16 update_w; + u16 update_h; + struct mcde_video_mode vmode; + enum mcde_display_rotation rotation; + u32 rotbuf1; + u32 rotbuf2; + + /* Applied settings */ + struct chnl_regs regs; + struct col_regs col_regs; + struct tv_regs tv_regs; + + bool continous_running; +}; + +/* TODO: give these a place? *//* REVIEW: Remove, move to top move to use? */ +#define MCDE_CONFIG_TVOUT_HBORDER 2 +#define MCDE_CONFIG_TVOUT_VBORDER 2 + +int mcde_chnl_set_video_mode(struct mcde_chnl_state *chnl, + struct mcde_video_mode *vmode) +{ + if (chnl == NULL || vmode == NULL) + return -EINVAL; + + disable_channel(chnl); + chnl->vmode = *vmode; + + return 0; +} +EXPORT_SYMBOL(mcde_chnl_set_video_mode); + +static void tv_video_mode_apply(struct mcde_chnl_state *chnl) +{ + /* assume xres == 720 */ + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + /* -4 since MCDE doesn't include SAV/EAV, 2 bytes each, to blanking */ + chnl->tv_regs.hbw = chnl->vmode.hbp + chnl->vmode.hfp - 4; + chnl->tv_regs.bel1 = chnl->vmode.vbp1 + chnl->vmode.vfp1; + chnl->tv_regs.fsl1 = chnl->vmode.vbp1; + chnl->tv_regs.bel2 = chnl->vmode.vbp2 + chnl->vmode.vfp2; + chnl->tv_regs.fsl2 = chnl->vmode.vbp2; + chnl->tv_regs.interlaced_en = chnl->vmode.interlaced; + + if (chnl->port.phy.dpi.num_data_lanes == 4) + chnl->tv_regs.tv_mode = MCDE_TVCRA_TVMODE_SDTV_656P_BE; + else + chnl->tv_regs.tv_mode = MCDE_TVCRA_TVMODE_SDTV_656P; +} + +static void update_tv_registers(enum mcde_chnl chnl_id, struct tv_regs *regs) +{ + u8 idx = chnl_id; + u8 maj_version; + + dev_dbg(&mcde_dev->dev, "%s\n", __func__); + mcde_wreg(MCDE_TVCRA + idx * MCDE_TVCRA_GROUPOFFSET, + MCDE_TVCRA_SEL_MOD(MCDE_TVCRA_SEL_MOD_TV) | + MCDE_TVCRA_INTEREN(regs->interlaced_en) | + MCDE_TVCRA_IFIELD(1) | + MCDE_TVCRA_TVMODE(regs->tv_mode) | + MCDE_TVCRA_SDTVMODE(MCDE_TVCRA_SDTVMODE_Y0CBY1CR) | + MCDE_TVCRA_AVRGEN(0)); + /* REVIEW: Magic values */ + mcde_wreg(MCDE_TVBLUA + idx * MCDE_TVBLUA_GROUPOFFSET, + MCDE_TVBLUA_TVBLU(0x83) | + MCDE_TVBLUA_TVBCB(0x9c) | + MCDE_TVBLUA_TVBCR(0x2c)); + + /* Vertical timing registers */ + mcde_wreg(MCDE_TVDVOA + idx * MCDE_TVDVOA_GROUPOFFSET, + MCDE_TVDVOA_DVO1(MCDE_CONFIG_TVOUT_VBORDER) | + MCDE_TVDVOA_DVO2(MCDE_CONFIG_TVOUT_VBORDER)); + mcde_wreg(MCDE_TVBL1A + idx * MCDE_TVBL1A_GROUPOFFSET, + MCDE_TVBL1A_BEL1(regs->bel1) | + MCDE_TVBL1A_BSL1(MCDE_CONFIG_TVOUT_VBORDER)); + mcde_wreg(MCDE_TVBL2A + idx * MCDE_TVBL1A_GROUPOFFSET, + MCDE_TVBL2A_BEL2(regs->bel2) | + MCDE_TVBL2A_BSL2(MCDE_CONFIG_TVOUT_VBORDER)); + mcde_wreg(MCDE_TVISLA + idx * MCDE_TVISLA_GROUPOFFSET, + MCDE_TVISLA_FSL1(regs->fsl1) | + MCDE_TVISLA_FSL2(regs->fsl2)); + /* Horizontal timing registers */ + maj_version = MCDE_REG2VAL(/* REVIEW: Make global and do on init? */ + MCDE_PID, MAJOR_VERSION, mcde_rreg(MCDE_PID)); + + if (maj_version > 3) { + mcde_wreg(MCDE_TVLBALWA + idx * MCDE_TVLBALWA_GROUPOFFSET, + MCDE_TVLBALWA_LBW(regs->hbw) | + MCDE_TVLBALWA_ALW(MCDE_CONFIG_TVOUT_HBORDER)); + mcde_wreg(MCDE_TVTIM1A + idx * MCDE_TVTIM1A_GROUPOFFSET, + MCDE_TVTIM1A_DHO(MCDE_CONFIG_TVOUT_HBORDER)); + } else { + /* in earlier versions the LBW and DHO fields are swapped */ + mcde_wreg(MCDE_TVLBALWA + idx * MCDE_TVLBALWA_GROUPOFFSET, + MCDE_TVLBALWA_LBW(MCDE_CONFIG_TVOUT_HBORDER) | + MCDE_TVLBALWA_ALW(MCDE_CONFIG_TVOUT_HBORDER)); + mcde_wreg(MCDE_TVTIM1A + idx * MCDE_TVTIM1A_GROUPOFFSET, + MCDE_TVTIM1A_DHO(regs->hbw)); + } +} + +static void tv_col_convert_apply(struct mcde_chnl_state *chnl) +{ +/* REVIEW: What is this? Magic matrix? */ +/* Why not supplied by mcde_chnl_set_col_convert? */ + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + chnl->col_regs.yr_red = 66; + chnl->col_regs.yr_green = 129; + chnl->col_regs.yr_blue = 25; + chnl->col_regs.cr_red = 112; + chnl->col_regs.cr_green = -94; + chnl->col_regs.cr_blue = -18; + chnl->col_regs.cb_red = -38; + chnl->col_regs.cb_green = -74; + chnl->col_regs.cb_blue = 112; + chnl->col_regs.off_red = 128; + chnl->col_regs.off_green = 16; + chnl->col_regs.off_blue = 128; +} + +static void update_col_registers(enum mcde_chnl chnl_id, struct col_regs *regs) +{ + u8 idx = chnl_id; + + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + mcde_wreg(MCDE_RGBCONV1A + idx * MCDE_RGBCONV1A_GROUPOFFSET, + MCDE_RGBCONV1A_YR_RED(regs->yr_red) | + MCDE_RGBCONV1A_YR_GREEN(regs->yr_green)); + mcde_wreg(MCDE_RGBCONV2A + idx * MCDE_RGBCONV2A_GROUPOFFSET, + MCDE_RGBCONV2A_YR_BLUE(regs->yr_blue) | + MCDE_RGBCONV2A_CR_RED(regs->cr_red)); + mcde_wreg(MCDE_RGBCONV3A + idx * MCDE_RGBCONV3A_GROUPOFFSET, + MCDE_RGBCONV3A_CR_GREEN(regs->cr_green) | + MCDE_RGBCONV3A_CR_BLUE(regs->cr_blue)); + mcde_wreg(MCDE_RGBCONV4A + idx * MCDE_RGBCONV4A_GROUPOFFSET, + MCDE_RGBCONV4A_CB_RED(regs->cb_red) | + MCDE_RGBCONV4A_CB_GREEN(regs->cb_green)); + mcde_wreg(MCDE_RGBCONV5A + idx * MCDE_RGBCONV5A_GROUPOFFSET, + MCDE_RGBCONV5A_CB_BLUE(regs->cb_blue) | + MCDE_RGBCONV5A_OFF_RED(regs->off_red)); + mcde_wreg(MCDE_RGBCONV6A + idx * MCDE_RGBCONV6A_GROUPOFFSET, + MCDE_RGBCONV6A_OFF_GREEN(regs->off_green) | + MCDE_RGBCONV6A_OFF_BLUE(regs->off_blue)); +} +/* REVIEW: Move all structs etc to top, don't mix code and declarations */ +static struct mcde_chnl_state channels[] = { + { + .id = MCDE_CHNL_A, + .ovly0 = &overlays[0], + .ovly1 = &overlays[1], + }, + { + .id = MCDE_CHNL_B, + .ovly0 = &overlays[2], + .ovly1 = &overlays[3], + }, + { + .id = MCDE_CHNL_C0, + .ovly0 = &overlays[4], + .ovly1 = NULL, + }, + { + .id = MCDE_CHNL_C1, + .ovly0 = &overlays[5], + .ovly1 = NULL, + } +}; + +struct chnl_config { + /* Key */ + enum mcde_chnl_path path; + + /* Value */ + bool swap_a_c0; + bool swap_a_c0_set; + bool swap_b_c1; + bool swap_b_c1_set; + bool fabmux; + bool fabmux_set; + bool f01mux; + bool f01mux_set; +}; +static /* TODO: const, compiler bug? */ struct chnl_config chnl_configs[] = { + /* Channel A */ + { .path = MCDE_CHNLPATH_CHNLA_FIFOA_DPI_0, + .swap_a_c0 = false, .swap_a_c0_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_0, + .swap_a_c0 = false, .swap_a_c0_set = true, + .fabmux = false, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC0_1, + .swap_a_c0 = false, .swap_a_c0_set = true, + .fabmux = true, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC0_2, + .swap_a_c0 = true, .swap_a_c0_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_0, + .swap_a_c0 = true, .swap_a_c0_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOC0_DSI_IFC1_1, + .swap_a_c0 = true, .swap_a_c0_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLA_FIFOA_DSI_IFC1_2, + .swap_a_c0 = false, .swap_a_c0_set = true, + .fabmux = false, .fabmux_set = true }, + /* Channel B */ + { .path = MCDE_CHNLPATH_CHNLB_FIFOB_DPI_1, + .swap_b_c1 = false, .swap_b_c1_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_0, + .swap_b_c1 = false, .swap_b_c1_set = true, + .fabmux = true, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC0_1, + .swap_b_c1 = false, .swap_b_c1_set = true, + .fabmux = false, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC0_2, + .swap_b_c1 = true, .swap_b_c1_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_0, + .swap_b_c1 = true, .swap_b_c1_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOC1_DSI_IFC1_1, + .swap_b_c1 = true, .swap_b_c1_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLB_FIFOB_DSI_IFC1_2, + .swap_b_c1 = false, .swap_b_c1_set = true, + .fabmux = true, .fabmux_set = true }, + /* Channel C0 */ + { .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_0, + .swap_a_c0 = true, .swap_a_c0_set = true, + .fabmux = false, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC0_1, + .swap_a_c0 = true, .swap_a_c0_set = true, + .fabmux = true, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC0_2, + .swap_a_c0 = false, .swap_a_c0_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_0, + .swap_a_c0 = false, .swap_a_c0_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC0_FIFOC0_DSI_IFC1_1, + .swap_a_c0 = false, .swap_a_c0_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC0_FIFOA_DSI_IFC1_2, + .swap_a_c0 = true, .swap_a_c0_set = true, + .fabmux = false, .fabmux_set = true }, + /* Channel C1 */ + { .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_0, + .swap_b_c1 = true, .swap_b_c1_set = true, + .fabmux = true, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC0_1, + .swap_b_c1 = true, .swap_b_c1_set = true, + .fabmux = false, .fabmux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC0_2, + .swap_b_c1 = false, .swap_b_c1_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_0, + .swap_b_c1 = false, .swap_b_c1_set = true, + .f01mux = true, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC1_FIFOC1_DSI_IFC1_1, + .swap_b_c1 = false, .swap_b_c1_set = true, + .f01mux = false, .f01mux_set = true }, + { .path = MCDE_CHNLPATH_CHNLC1_FIFOB_DSI_IFC1_2, + .swap_b_c1 = true, .swap_b_c1_set = true, + .fabmux = true, .fabmux_set = true }, +}; + +/* MCDE internal helpers */ + +static u8 portfmt2dsipacking(enum mcde_port_pix_fmt pix_fmt) +{ + switch (pix_fmt) { + case MCDE_PORTPIXFMT_DSI_16BPP: + return MCDE_DSIVID0CONF0_PACKING_RGB565; + case MCDE_PORTPIXFMT_DSI_18BPP_PACKED: + return MCDE_DSIVID0CONF0_PACKING_RGB666; + case MCDE_PORTPIXFMT_DSI_18BPP: + case MCDE_PORTPIXFMT_DSI_24BPP: + default: + return MCDE_DSIVID0CONF0_PACKING_RGB888; + case MCDE_PORTPIXFMT_DSI_YCBCR422: + return MCDE_DSIVID0CONF0_PACKING_HDTV; + } +} + +static u8 portfmt2bpp(enum mcde_port_pix_fmt pix_fmt) +{ + /* TODO: Check DPI spec *//* REVIEW: Remove or check */ + switch (pix_fmt) { + case MCDE_PORTPIXFMT_DPI_16BPP_C1: + case MCDE_PORTPIXFMT_DPI_16BPP_C2: + case MCDE_PORTPIXFMT_DPI_16BPP_C3: + case MCDE_PORTPIXFMT_DSI_16BPP: + case MCDE_PORTPIXFMT_DSI_YCBCR422: + return 16; + case MCDE_PORTPIXFMT_DPI_18BPP_C1: + case MCDE_PORTPIXFMT_DPI_18BPP_C2: + case MCDE_PORTPIXFMT_DSI_18BPP_PACKED: + return 18; + case MCDE_PORTPIXFMT_DSI_18BPP: + case MCDE_PORTPIXFMT_DPI_24BPP: + case MCDE_PORTPIXFMT_DSI_24BPP: + return 24; + default: + return 0;/* REVIEW: 1, to reduce ris of div by zero */ + } +} + +static struct mcde_chnl_state *find_channel_by_dsilink(int link) +{ + struct mcde_chnl_state *chnl = &channels[0]; + for (; chnl < &channels[ARRAY_SIZE(channels)]; chnl++) + if (chnl->inuse && chnl->port.link == link && + chnl->port.type == MCDE_PORTTYPE_DSI) + return chnl; + return NULL; +} + +static irqreturn_t mcde_irq_handler(int irq, void *dev) +{ + int i; + u32 irq_status; + + dev_vdbg(&mcde_dev->dev, "IRQ enter\n"); + + /* Handle overlay irqs */ + irq_status = mcde_rfld(MCDE_RISOVL, OVLFDRIS); + for (i = 0; i < ARRAY_SIZE(overlays); i++) { + if (irq_status & (1 << i)) { + struct mcde_ovly_state *ovly = &overlays[i]; + ovly->transactionid_hw = ovly->transactionid_regs; + wake_up(&ovly->waitq_hw); + } + } + mcde_wfld(MCDE_RISOVL, OVLFDRIS, irq_status); + + /* Handle channel irqs */ + irq_status = mcde_rreg(MCDE_RISPP); + if (irq_status & MCDE_RISPP_VCMPARIS_MASK) { + struct mcde_chnl_state *chnl = &channels[MCDE_CHNL_A]; + chnl->transactionid_hw = chnl->transactionid_regs; + wake_up(&chnl->waitq_hw); + mcde_wfld(MCDE_RISPP, VCMPARIS, 1); + } + if (irq_status & MCDE_RISPP_VCMPBRIS_MASK) { + struct mcde_chnl_state *chnl = &channels[MCDE_CHNL_B]; + chnl->transactionid_hw = chnl->transactionid_regs; + wake_up(&chnl->waitq_hw); + mcde_wfld(MCDE_RISPP, VCMPBRIS, 1); + } + if (irq_status & MCDE_RISPP_VCMPC0RIS_MASK) { + struct mcde_chnl_state *chnl = &channels[MCDE_CHNL_C0]; + chnl->transactionid_hw = chnl->transactionid_regs; + wake_up(&chnl->waitq_hw); + mcde_wfld(MCDE_RISPP, VCMPC0RIS, 1); + } + if (irq_status & MCDE_RISPP_VCMPC1RIS_MASK) { + struct mcde_chnl_state *chnl = &channels[MCDE_CHNL_C1]; + chnl->transactionid_hw = chnl->transactionid_regs; + wake_up(&chnl->waitq_hw); + mcde_wfld(MCDE_RISPP, VCMPC1RIS, 1); + } + for (i = 0; i < num_dsilinks; i++) { + bool trig = false; + struct mcde_chnl_state *chnl; + irq_status = dsi_rfld(i, DSI_DIRECT_CMD_STS_FLAG, + TE_RECEIVED_FLAG); + if (irq_status) { + trig = true; + dsi_wreg(i, DSI_DIRECT_CMD_STS_CLR, + DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR(true)); + dev_vdbg(&mcde_dev->dev, "BTA TE DSI%d\n", i); + } + irq_status = dsi_rfld(i, DSI_CMD_MODE_STS_FLAG, ERR_NO_TE_FLAG); + if (irq_status) { + trig = true; + dsi_wreg(i, DSI_CMD_MODE_STS_CLR, + DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR(true)); + dev_vdbg(&mcde_dev->dev, "NO_TE DSI%d\n", i); + } + if (!trig) + continue; + chnl = find_channel_by_dsilink(i); + if (chnl) { + mcde_wreg(MCDE_CHNL0SYNCHSW + + chnl->id * MCDE_CHNL0SYNCHSW_GROUPOFFSET, + MCDE_CHNL0SYNCHSW_SW_TRIG(true)); + dev_vdbg(&mcde_dev->dev, "SW TRIG DSI%d, chnl=%d\n", i, + chnl->id); + } + } + + dev_vdbg(&mcde_dev->dev, "IRQ exit\n"); + + return IRQ_HANDLED; +} + +void wait_for_overlay(struct mcde_ovly_state *ovly) +{ + int ret; + + ret = wait_event_timeout(ovly->waitq_hw, + ovly->transactionid_hw == ovly->transactionid_regs, + OVLY_TIMEOUT); + if (!ret) + dev_warn(&mcde_dev->dev, + "Wait for overlay timeout (ovly=%d,%d<%d)!\n", + ovly->idx, ovly->transactionid_hw, + ovly->transactionid_regs); +} + +void wait_for_channel(struct mcde_chnl_state *chnl) +{ + int ret; + + ret = wait_event_timeout(chnl->waitq_hw, + chnl->transactionid_hw == chnl->transactionid_regs, + CHNL_TIMEOUT); + if (!ret) + dev_warn(&mcde_dev->dev, + "Wait for channel timeout (chnl=%d,%d<%d)!\n", + chnl->id, chnl->transactionid_hw, + chnl->transactionid_regs); +} + +void update_channel_static_registers(struct mcde_chnl_state *chnl) +{ + const struct chnl_config *cfg = chnl->cfg; + const struct mcde_port *port = &chnl->port; + + /* Fifo & muxing */ + if (cfg->swap_a_c0_set) + mcde_wfld(MCDE_CONF0, SWAP_A_C0, cfg->swap_a_c0); + if (cfg->swap_b_c1_set) + mcde_wfld(MCDE_CONF0, SWAP_B_C1, cfg->swap_b_c1); + if (cfg->fabmux_set) + mcde_wfld(MCDE_CR, FABMUX, cfg->fabmux); + if (cfg->f01mux_set) + mcde_wfld(MCDE_CR, F01MUX, cfg->f01mux); + + /* Formatter */ + if (port->type == MCDE_PORTTYPE_DSI) { + int i = 0; + u8 idx = 2 * port->link + port->ifc; + u8 lnk = port->link; + + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, LINK_EN, true); + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, BTA_EN, true); + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, READ_EN, true); + dsi_wfld(lnk, DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, true); + dsi_wreg(lnk, DSI_MCTL_DPHY_STATIC, + DSI_MCTL_DPHY_STATIC_UI_X4(port->phy.dsi.ui)); + dsi_wreg(lnk, DSI_DPHY_LANES_TRIM, + DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_ENUM(0_90)); + dsi_wreg(lnk, DSI_MCTL_DPHY_TIMEOUT, + DSI_MCTL_DPHY_TIMEOUT_CLK_DIV(0xf) | + DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL(0x3fff) | + DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL(0x3fff)); + dsi_wreg(lnk, DSI_MCTL_MAIN_PHY_CTL, + DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME(0xf) | + DSI_MCTL_MAIN_PHY_CTL_LANE2_EN(true) | + DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS(false)); + dsi_wreg(lnk, DSI_MCTL_ULPOUT_TIME, + DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME(1) | + DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME(1)); + /* TODO: make enum */ + dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_MODE, false); + /* TODO: make enum */ + dsi_wfld(lnk, DSI_CMD_MODE_CTL, ARB_PRI, port->ifc == 1); + dsi_wreg(lnk, DSI_MCTL_MAIN_EN, + DSI_MCTL_MAIN_EN_PLL_START(true) | + DSI_MCTL_MAIN_EN_CKLANE_EN(true) | + DSI_MCTL_MAIN_EN_DAT1_EN(true) | + DSI_MCTL_MAIN_EN_DAT2_EN(port->phy.dsi.num_data_lanes + == 2) | + DSI_MCTL_MAIN_EN_IF1_EN(port->ifc == 0) | + DSI_MCTL_MAIN_EN_IF2_EN(port->ifc == 1)); + while (dsi_rfld(lnk, DSI_MCTL_MAIN_STS, CLKLANE_READY) == 0 || + dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT1_READY) == 0 || + dsi_rfld(lnk, DSI_MCTL_MAIN_STS, DAT2_READY) == 0) { + mdelay(1); + if (i++ == 10) + dev_warn(&mcde_dev->dev, + "DSI lane not ready (link=%d)!\n", lnk); + } + + if (port->ifc == 0 && port->link == 0) + mcde_wfld(MCDE_CR, DSIVID0_EN, true); + else if (port->ifc == 0 && port->link == 1) + mcde_wfld(MCDE_CR, DSIVID1_EN, true); + else if (port->ifc == 0 && port->link == 2) + mcde_wfld(MCDE_CR, DSIVID2_EN, true); + else if (port->ifc == 1 && port->link == 0) + mcde_wfld(MCDE_CR, DSICMD0_EN, true); + else if (port->ifc == 1 && port->link == 1) + mcde_wfld(MCDE_CR, DSICMD1_EN, true); + else if (port->ifc == 1 && port->link == 2) + mcde_wfld(MCDE_CR, DSICMD2_EN, true); + mcde_wreg(MCDE_DSIVID0CONF0 + + idx * MCDE_DSIVID0CONF0_GROUPOFFSET, + MCDE_DSIVID0CONF0_BLANKING(0) | + MCDE_DSIVID0CONF0_VID_MODE( + port->mode == MCDE_PORTMODE_VID) | + MCDE_DSIVID0CONF0_CMD8(true) | + MCDE_DSIVID0CONF0_BIT_SWAP(false) | + MCDE_DSIVID0CONF0_BYTE_SWAP(false) | + MCDE_DSIVID0CONF0_DCSVID_NOTGEN(true)); + + if (port->mode == MCDE_PORTMODE_CMD) { + if (port->ifc == 0) + dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF1_ID, + port->phy.dsi.virt_id); + else if (port->ifc == 1) + dsi_wfld(port->link, DSI_CMD_MODE_CTL, IF2_ID, + port->phy.dsi.virt_id); + } + } else if (port->type == MCDE_PORTTYPE_DPI) { + if (port->link == 0) + mcde_wfld(MCDE_CR, DPIA_EN, true); + else if (port->link == 1) + mcde_wfld(MCDE_CR, DPIB_EN, true); + } +/* REVIEW: Magic numbers, define! Calculate? */ + if (chnl->id == MCDE_CHNL_C0) + mcde_wreg(MCDE_CTRLC0, MCDE_CTRLC0_FIFOWTRMRK(0xa0)); + else if (chnl->id == MCDE_CHNL_C1) + mcde_wreg(MCDE_CTRLC1, MCDE_CTRLC1_FIFOWTRMRK(0xa0)); + else if (port->update_auto_trig && (port->sync_src == MCDE_SYNCSRC_TE0)) + mcde_wreg(MCDE_CTRLC0, MCDE_CTRLC0_FIFOWTRMRK(0xa0)); + else if (port->update_auto_trig && (port->sync_src == MCDE_SYNCSRC_TE1)) + mcde_wreg(MCDE_CTRLC1, MCDE_CTRLC1_FIFOWTRMRK(0xa0)); + + mcde_wfld(MCDE_CR, MCDEEN, true); + + dev_vdbg(&mcde_dev->dev, "Static registers setup, chnl=%d\n", chnl->id); +} + +/* REVIEW: Make update_* an mcde_rectangle? */ +static void update_overlay_registers(u8 idx, struct ovly_regs *regs, + struct mcde_port *port, u16 update_x, u16 update_y, u16 update_w, + u16 update_h, u16 stride, bool interlaced) +{ + /* TODO: fix clipping for small overlay */ + u32 lmrgn = (regs->cropx + update_x) * regs->bits_per_pixel; + u32 tmrgn = (regs->cropy + update_y) * stride; + u32 ppl = regs->ppl - update_x; + u32 lpf = regs->lpf - update_y; + u32 ljinc = stride; + u32 pixelfetchwtrmrklevel = 32;/* REVIEW: Magic number */ + u8 nr_of_bufs = 1; + + /* TODO: disable if everything clipped */ + if (!regs->enabled) { + u32 temp; + temp = mcde_rreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET); + mcde_wreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET, + (temp & ~MCDE_OVL0CR_OVLEN_MASK) | + MCDE_OVL0CR_OVLEN(false)); + return; + } + + /* TODO: Preferably most of this is done in some apply function instead + * of every update. Problem is however that at overlay apply + * there is no port type info available (and the question is + * whether it is appropriate to add a port type there). + * Note that lpf has a dependency on update_y. + */ + if (port->type == MCDE_PORTTYPE_DPI) + /* REVIEW: Why not for DSI? enable in regs? */ + regs->col_conv = MCDE_OVL0CR_COLCCTRL_ENABLED_NO_SAT; + else if (port->type == MCDE_PORTTYPE_DSI) + if (interlaced) { + nr_of_bufs = 2; + lpf = lpf / 2; + ljinc *= 2; + } + + /* REVIEW: Magic numbers */ +#ifdef CONFIG_AV8100_SDTV + /* TODO: check if these watermark levels work for HDMI as well. */ + pixelfetchwtrmrklevel = 16; +#else + if (regs->ppl >= 1280) + pixelfetchwtrmrklevel = 64; + else + pixelfetchwtrmrklevel = 32; +#endif /* CONFIG_AV8100_SDTV */ + + mcde_wreg(MCDE_EXTSRC0A0 + idx * MCDE_EXTSRC0A0_GROUPOFFSET, + regs->baseaddress0); + mcde_wreg(MCDE_EXTSRC0A1 + idx * MCDE_EXTSRC0A1_GROUPOFFSET, + regs->baseaddress1); + if (regs->reset_buf_id) { + regs->reset_buf_id = false; + mcde_wreg(MCDE_EXTSRC0CONF + idx * MCDE_EXTSRC0CONF_GROUPOFFSET, + MCDE_EXTSRC0CONF_BUF_ID(0) | + MCDE_EXTSRC0CONF_BUF_NB(nr_of_bufs) | + MCDE_EXTSRC0CONF_PRI_OVLID(idx) | + MCDE_EXTSRC0CONF_BPP(regs->bpp) | + MCDE_EXTSRC0CONF_BGR(regs->bgr) | + MCDE_EXTSRC0CONF_BEBO(regs->bebo) | + MCDE_EXTSRC0CONF_BEPO(false)); + mcde_wreg(MCDE_EXTSRC0CR + idx * MCDE_EXTSRC0CR_GROUPOFFSET, + MCDE_EXTSRC0CR_SEL_MOD(port->update_auto_trig ? + MCDE_EXTSRC0CR_SEL_MOD_AUTO_TOGGLE : + MCDE_EXTSRC0CR_SEL_MOD_SOFTWARE_SEL) | + MCDE_EXTSRC0CR_MULTIOVL_CTRL_ENUM(PRIMARY) | + MCDE_EXTSRC0CR_FS_DIV_DISABLE(false) | + MCDE_EXTSRC0CR_FORCE_FS_DIV(false)); + mcde_wreg(MCDE_OVL0CR + idx * MCDE_OVL0CR_GROUPOFFSET, + MCDE_OVL0CR_OVLEN(true) | + MCDE_OVL0CR_COLCCTRL(regs->col_conv) | + MCDE_OVL0CR_CKEYGEN(false) | + MCDE_OVL0CR_ALPHAPMEN(true) | + MCDE_OVL0CR_OVLF(false) | + MCDE_OVL0CR_OVLR(false) | + MCDE_OVL0CR_OVLB(false) | + MCDE_OVL0CR_FETCH_ROPC(0) | + MCDE_OVL0CR_STBPRIO(0) | + MCDE_OVL0CR_BURSTSIZE(11) | /* TODO: _HW_8W */ + /* TODO: enum, get from ovly */ + MCDE_OVL0CR_MAXOUTSTANDING(2) | + /* TODO: _HW_8W, calculate? */ + MCDE_OVL0CR_ROTBURSTSIZE(11)); + mcde_wreg(MCDE_OVL0CONF + idx * MCDE_OVL0CONF_GROUPOFFSET, + MCDE_OVL0CONF_PPL(ppl) | + MCDE_OVL0CONF_EXTSRC_ID(idx) | + MCDE_OVL0CONF_LPF(lpf)); + mcde_wreg(MCDE_OVL0CONF2 + idx * MCDE_OVL0CONF2_GROUPOFFSET, + MCDE_OVL0CONF2_BP_ENUM(PER_PIXEL_ALPHA) | + /* TODO: Allow setting? */ + MCDE_OVL0CONF2_ALPHAVALUE(0xff) | + MCDE_OVL0CONF2_OPQ(regs->opq) | + MCDE_OVL0CONF2_PIXOFF(lmrgn & 63) | + MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL( + pixelfetchwtrmrklevel)); + mcde_wreg(MCDE_OVL0LJINC + idx * MCDE_OVL0LJINC_GROUPOFFSET, + ljinc); + mcde_wreg(MCDE_OVL0CROP + idx * MCDE_OVL0CROP_GROUPOFFSET, + MCDE_OVL0CROP_TMRGN(tmrgn) | + MCDE_OVL0CROP_LMRGN(lmrgn >> 6)); + mcde_wreg(MCDE_OVL0COMP + idx * MCDE_OVL0COMP_GROUPOFFSET, + MCDE_OVL0COMP_XPOS(regs->xpos) | + MCDE_OVL0COMP_CH_ID(regs->ch_id) | + MCDE_OVL0COMP_YPOS(regs->ypos) | + MCDE_OVL0COMP_Z(regs->z)); + } + + dev_vdbg(&mcde_dev->dev, "Overlay registers setup, idx=%d\n", idx); +} + +static void disable_channel(struct mcde_chnl_state *chnl) +{ + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + switch (chnl->id) { + case MCDE_CHNL_A: + mcde_wfld(MCDE_CRA0, FLOEN, false); + break; + case MCDE_CHNL_B: + mcde_wfld(MCDE_CRB0, FLOEN, false); + break; + case MCDE_CHNL_C0: + mcde_wfld(MCDE_CRC, C1EN, false); + if (!mcde_rfld(MCDE_CRC, C2EN)) + mcde_wfld(MCDE_CRC, FLOEN, false); + break; + case MCDE_CHNL_C1: + mcde_wfld(MCDE_CRC, C2EN, false); + if (!mcde_rfld(MCDE_CRC, C1EN)) + mcde_wfld(MCDE_CRC, FLOEN, false); + break; + } + wait_for_channel(chnl); + /* TODO poll for channel enable bit */ + chnl->continous_running = false; +} + +static void enable_channel(enum mcde_chnl chnl_id) +{ + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + switch (chnl_id) { + case MCDE_CHNL_A: + mcde_wfld(MCDE_CRA0, FLOEN, true); + break; + case MCDE_CHNL_B: + mcde_wfld(MCDE_CRB0, FLOEN, true); + break; + case MCDE_CHNL_C0: + mcde_wfld(MCDE_CRC, POWEREN, true); + mcde_wfld(MCDE_CRC, FLOEN, true); + mcde_wfld(MCDE_CRC, C1EN, true); + break; + case MCDE_CHNL_C1: + mcde_wfld(MCDE_CRC, POWEREN, true); + mcde_wfld(MCDE_CRC, FLOEN, true); + mcde_wfld(MCDE_CRC, C2EN, true); + break; + } +} + +/* TODO get from register */ +#define MCDE_CLK_FREQ_MHZ 160 + +void update_channel_registers(enum mcde_chnl chnl_id, struct chnl_regs *regs, + struct mcde_port *port, struct mcde_video_mode *video_mode) +{ + u8 idx = chnl_id; + u32 out_synch_src = MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_FORMATTER; + + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + /* Channel */ + if (port->update_auto_trig && port->type != MCDE_PORTTYPE_DPI) { + out_synch_src = port->sync_src == MCDE_SYNCSRC_TE0 ? + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 : + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC1; + } + mcde_wreg(MCDE_CHNL0CONF + idx * MCDE_CHNL0CONF_GROUPOFFSET, + MCDE_CHNL0CONF_PPL(regs->ppl-1) | + MCDE_CHNL0CONF_LPF(regs->lpf-1)); + mcde_wreg(MCDE_CHNL0STAT + idx * MCDE_CHNL0STAT_GROUPOFFSET, + MCDE_CHNL0STAT_CHNLBLBCKGND_EN(false) | + MCDE_CHNL0STAT_CHNLRD(true)); + mcde_wreg(MCDE_CHNL0SYNCHMOD + + idx * MCDE_CHNL0SYNCHMOD_GROUPOFFSET, + MCDE_CHNL0SYNCHMOD_SRC_SYNCH(port->update_auto_trig ? + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT : + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE) | + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC(out_synch_src)); + mcde_wreg(MCDE_CHNL0BCKGNDCOL + idx * MCDE_CHNL0BCKGNDCOL_GROUPOFFSET, + MCDE_CHNL0BCKGNDCOL_B(255) | /* TODO: Temp */ + MCDE_CHNL0BCKGNDCOL_G(0) | + MCDE_CHNL0BCKGNDCOL_R(0)); + mcde_wreg(MCDE_CHNL0PRIO + idx * MCDE_CHNL0PRIO_GROUPOFFSET, + MCDE_CHNL0PRIO_CHNLPRIO(0)); + switch (chnl_id) { + case MCDE_CHNL_A: + if (port->type == MCDE_PORTTYPE_DPI) { + mcde_wreg(MCDE_CRA1, + MCDE_CRA1_CLKSEL_ENUM(EXT_TV1) | + MCDE_CRA1_OUTBPP_ENUM(24BPP) | + MCDE_CRA1_BCD(1) + ); + } else { + mcde_wreg(MCDE_CRA1, MCDE_CRA1_CLKSEL_ENUM(166MHZ)); + } + break; + case MCDE_CHNL_B: + if (port->type == MCDE_PORTTYPE_DPI) { + mcde_wreg(MCDE_CRB1, + MCDE_CRB1_CLKSEL_ENUM(EXT_TV2) | + MCDE_CRB1_OUTBPP_ENUM(24BPP) | + MCDE_CRB1_BCD(1) + ); + } else { + mcde_wreg(MCDE_CRB1, MCDE_CRB1_CLKSEL_ENUM(166MHZ)); + } + break; + default: + break; + } + + /* Formatter */ + if (port->type == MCDE_PORTTYPE_DSI) { + u8 fidx = 2 * port->link + port->ifc; + u32 temp, packet; + /* pkt_div is used to avoid underflow in output fifo for + * large packets */ + u32 pkt_div = 1; + u32 dsi_delay0 = 0; + u32 screen_ppl, screen_lpf; + + /* REVIEW: Calc? */ + if (regs->ppl >= 1280) + pkt_div = 2; + else + pkt_div = 1; + + if (regs->roten) { + screen_ppl = regs->lpf; + screen_lpf = regs->ppl; + } else { + screen_ppl = regs->ppl; + screen_lpf = regs->lpf; + } + + /* pkt_delay_progressive = pixelclock * htot / + * (1E12 / 160E6) / pkt_div */ + dsi_delay0 = (video_mode->pixclock + 1) * + (video_mode->xres + video_mode->hbp + + video_mode->hfp) / + (1000000 / MCDE_CLK_FREQ_MHZ) / pkt_div; + temp = mcde_rreg(MCDE_DSIVID0CONF0 + + fidx * MCDE_DSIVID0CONF0_GROUPOFFSET); + mcde_wreg(MCDE_DSIVID0CONF0 + + fidx * MCDE_DSIVID0CONF0_GROUPOFFSET, + (temp & ~MCDE_DSIVID0CONF0_PACKING_MASK) | + MCDE_DSIVID0CONF0_PACKING(regs->dsipacking)); + /* 1==CMD8 */ + packet = ((screen_ppl / pkt_div * regs->bpp) >> 3) + 1; + mcde_wreg(MCDE_DSIVID0FRAME + + fidx * MCDE_DSIVID0FRAME_GROUPOFFSET, + MCDE_DSIVID0FRAME_FRAME(packet * screen_lpf)); + mcde_wreg(MCDE_DSIVID0PKT + fidx * MCDE_DSIVID0PKT_GROUPOFFSET, + MCDE_DSIVID0PKT_PACKET(packet)); + mcde_wreg(MCDE_DSIVID0SYNC + + fidx * MCDE_DSIVID0SYNC_GROUPOFFSET, + MCDE_DSIVID0SYNC_SW(0) | + MCDE_DSIVID0SYNC_DMA(0)); + mcde_wreg(MCDE_DSIVID0CMDW + + fidx * MCDE_DSIVID0CMDW_GROUPOFFSET, + MCDE_DSIVID0CMDW_CMDW_START(DCS_CMD_WRITE_START) | + MCDE_DSIVID0CMDW_CMDW_CONTINUE(DCS_CMD_WRITE_CONTINUE)); + mcde_wreg(MCDE_DSIVID0DELAY0 + + fidx * MCDE_DSIVID0DELAY0_GROUPOFFSET, + MCDE_DSIVID0DELAY0_INTPKTDEL(dsi_delay0)); + mcde_wreg(MCDE_DSIVID0DELAY1 + + fidx * MCDE_DSIVID0DELAY1_GROUPOFFSET, + MCDE_DSIVID0DELAY1_TEREQDEL(0) | + MCDE_DSIVID0DELAY1_FRAMESTARTDEL(0)); +/* TODO remove *//* REVIEW: Remove */ +/* +dev_dbg(&mcde_dev->dev, "video_mode->pixclock %d\n", video_mode->pixclock); +dev_dbg(&mcde_dev->dev, "video_mode->xres %d\n", video_mode->xres); +dev_dbg(&mcde_dev->dev, "video_mode->hbp %d\n", video_mode->hbp); +dev_dbg(&mcde_dev->dev, "video_mode->hfp %d\n", video_mode->hfp); +dev_dbg(&mcde_dev->dev, "dsi_delay0 %d %x\n", dsi_delay0, dsi_delay0); +dev_dbg(&mcde_dev->dev, "interlaced:%d\n", (video_mode->interlaced)); +*/ + } + + /* Rotation */ + if (regs->roten) { + /* TODO: Allocate memory in ESRAM instead of + static allocations. */ + mcde_wreg(MCDE_ROTADD0A + chnl_id * MCDE_ROTADD0A_GROUPOFFSET, + MCDE_ROTADD0A_ROTADD0(regs->rotbuf1)); + mcde_wreg(MCDE_ROTADD1A + chnl_id * MCDE_ROTADD1A_GROUPOFFSET, + MCDE_ROTADD1A_ROTADD1(regs->rotbuf2)); + + mcde_wreg(MCDE_ROTACONF + chnl_id * MCDE_ROTACONF_GROUPOFFSET, + MCDE_ROTACONF_ROTBURSTSIZE( + MCDE_ROTACONF_ROTBURSTSIZE_8W) | + MCDE_ROTACONF_ROTBURSTSIZE_HW(1) | + MCDE_ROTACONF_ROTDIR(regs->rotdir) | + MCDE_ROTACONF_STRIP_WIDTH_ENUM(16PIX) | + /* TODO: MAXOUT_ENUM */ + MCDE_ROTACONF_RD_MAXOUT(2) | + MCDE_ROTACONF_WR_MAXOUT(3)); + + if (chnl_id == MCDE_CHNL_A) { + mcde_wfld(MCDE_CRA0, ROTEN, true); + mcde_wfld(MCDE_CRA0, ROTBURSTSIZE, + MCDE_CRA0_ROTBURSTSIZE_8W); + mcde_wfld(MCDE_CRA0, ROTBURSTSIZE_HW, true); + mcde_wfld(MCDE_CRA1, CLKSEL, MCDE_CRA1_CLKSEL_166MHZ); + /* TODO: Fetch port output bpp */ + mcde_wfld(MCDE_CRA1, OUTBPP, MCDE_CRA1_OUTBPP_24BPP); + mcde_wfld(MCDE_CRA1, BCD, true); + } else if (chnl_id == MCDE_CHNL_B) { + mcde_wfld(MCDE_CRB0, ROTEN, true); + mcde_wfld(MCDE_CRB0, ROTBURSTSIZE, + MCDE_CRB0_ROTBURSTSIZE_8W); + mcde_wfld(MCDE_CRB0, ROTBURSTSIZE_HW, true); + mcde_wfld(MCDE_CRB1, CLKSEL, MCDE_CRB1_CLKSEL_166MHZ); + /* TODO: Fetch port output bpp */ + mcde_wfld(MCDE_CRB1, OUTBPP, MCDE_CRB1_OUTBPP_24BPP); + mcde_wfld(MCDE_CRB1, BCD, true); + } + } else { + if (chnl_id == MCDE_CHNL_A) + mcde_wfld(MCDE_CRA0, ROTEN, false); + else if (chnl_id == MCDE_CHNL_B) + mcde_wfld(MCDE_CRB0, ROTEN, false); + } + + dev_vdbg(&mcde_dev->dev, "Channel registers setup, chnl=%d\n", chnl_id); +} + +/* DSI */ + +int mcde_dsi_dcs_write(struct mcde_chnl_state *chnl, u8 cmd, u8* data, int len) +{ + int i; + u32 wrdat[4] = { 0, 0, 0, 0 }; + u32 settings; + u8 link = chnl->port.link; + u8 virt_id = chnl->port.phy.dsi.virt_id; + + /* REVIEW: One command at a time */ + /* REVIEW: Allow read/write on unreserved ports */ + if (len > MCDE_MAX_DCS_WRITE || chnl->port.type != MCDE_PORTTYPE_DSI) + return -EINVAL; + + wrdat[0] = cmd; + for (i = 1; i <= len; i++) + wrdat[i>>2] |= ((u32)data[i-1] << ((i & 3) * 8)); + + settings = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(WRITE) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(len > 1) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(virt_id) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(len+1) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(true); + if (len == 0) + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_SHORT_WRITE_0); + else if (len == 1) + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_SHORT_WRITE_1); + else + settings |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM( + DCS_LONG_WRITE); + + dsi_wreg(link, DSI_DIRECT_CMD_MAIN_SETTINGS, settings); + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT0, wrdat[0]); + if (len > 3) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT1, wrdat[1]); + if (len > 7) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT2, wrdat[2]); + if (len > 11) + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT3, wrdat[3]); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_SEND, true); + + /* TODO: irq wait and error check */ + mdelay(10); + dsi_wreg(link, DSI_CMD_MODE_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, ~0); + + return 0; +} + +int mcde_dsi_dcs_read(struct mcde_chnl_state *chnl, u8 cmd, u8* data, int *len) +{ + int ret = 0; + u8 link = chnl->port.link; + u8 virt_id = chnl->port.phy.dsi.virt_id; + u32 settings; + int wait = 100; + bool error, ok; + + if (*len > MCDE_MAX_DCS_READ || chnl->port.type != MCDE_PORTTYPE_DSI) + return -EINVAL; + + dsi_wfld(link, DSI_MCTL_MAIN_DATA_CTL, BTA_EN, true); + dsi_wfld(link, DSI_MCTL_MAIN_DATA_CTL, READ_EN, true); + settings = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(READ) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(false) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(virt_id) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(1) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(true) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM(DCS_READ); + dsi_wreg(link, DSI_DIRECT_CMD_MAIN_SETTINGS, settings); + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT0, cmd); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_RD_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_SEND, true); + + /* TODO */ + while (wait-- && !(error = dsi_rfld(link, DSI_DIRECT_CMD_STS, + READ_COMPLETED_WITH_ERR)) && !(ok = dsi_rfld(link, + DSI_DIRECT_CMD_STS, READ_COMPLETED))) + mdelay(10); + + if (ok) { + int rdsize; + u32 rddat; + + rdsize = dsi_rfld(link, DSI_DIRECT_CMD_RD_PROPERTY, RD_SIZE); + rddat = dsi_rreg(link, DSI_DIRECT_CMD_RDDAT); + if (rdsize < *len) + pr_debug("DCS incomplete read %d<%d (%.8X)\n", + rdsize, *len, rddat);/* REVIEW: dev_dbg */ + *len = min(*len, rdsize); + memcpy(data, &rddat, *len); + } else { + pr_err("DCS read failed, err=%d, sts=%X\n", + error, dsi_rreg(link, DSI_DIRECT_CMD_STS)); + ret = -EIO; + } + + dsi_wreg(link, DSI_CMD_MODE_STS_CLR, ~0); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, ~0); + + return ret; +} + +static void dsi_te_request(struct mcde_chnl_state *chnl) +{ + u8 link = chnl->port.link; + u8 virt_id = chnl->port.phy.dsi.virt_id; + u32 settings; + + dev_vdbg(&mcde_dev->dev, "Request BTA TE, chnl=%d\n", + chnl->id); + + dsi_wfld(link, DSI_MCTL_MAIN_DATA_CTL, BTA_EN, true); + dsi_wfld(link, DSI_MCTL_MAIN_DATA_CTL, REG_TE_EN, true); + dsi_wfld(link, DSI_CMD_MODE_CTL, TE_TIMEOUT, 0x3FF); + settings = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_ENUM(TE_REQ) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT(false) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID(virt_id) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE(2) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN(true) | + DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_ENUM(DCS_SHORT_WRITE_1); + dsi_wreg(link, DSI_DIRECT_CMD_MAIN_SETTINGS, settings); + dsi_wreg(link, DSI_DIRECT_CMD_WRDAT0, DCS_CMD_SET_TEAR_ON); + dsi_wreg(link, DSI_DIRECT_CMD_STS_CLR, + DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR(true)); + dsi_wfld(link, DSI_DIRECT_CMD_STS_CTL, TE_RECEIVED_EN, true); + dsi_wreg(link, DSI_CMD_MODE_STS_CLR, + DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR(true)); + dsi_wfld(link, DSI_CMD_MODE_STS_CTL, ERR_NO_TE_EN, true); + dsi_wreg(link, DSI_DIRECT_CMD_SEND, true); +} + +/* MCDE channels */ +struct mcde_chnl_state *mcde_chnl_get(enum mcde_chnl chnl_id, + enum mcde_fifo fifo, const struct mcde_port *port) +{ + int i; + struct mcde_chnl_state *chnl = NULL; + enum mcde_chnl_path path; + const struct chnl_config *cfg = NULL; + + /* Allocate channel */ + for (i = 0; i < ARRAY_SIZE(channels); i++) { + if (chnl_id == channels[i].id) + chnl = &channels[i]; + } + if (!chnl) { + dev_dbg(&mcde_dev->dev, "Invalid channel, chnl=%d\n", chnl_id); + return ERR_PTR(-EINVAL); + } + if (chnl->inuse) { + dev_dbg(&mcde_dev->dev, "Channel in use, chnl=%d\n", chnl_id); + return ERR_PTR(-EBUSY); + } + + path = MCDE_CHNLPATH(chnl->id, fifo, port->type, port->ifc, port->link); + for (i = 0; i < ARRAY_SIZE(chnl_configs); i++) + if (chnl_configs[i].path == path) { + cfg = &chnl_configs[i]; + break; + } + if (cfg == NULL) { + dev_dbg(&mcde_dev->dev, "Invalid config, chnl=%d," + " path=0x%.8X\n", chnl_id, path); + chnl = ERR_PTR(-EINVAL); + goto find_config_failed; + } else + dev_info(&mcde_dev->dev, "Config, chnl=%d," + " path=0x%.8X\n", chnl_id, path); + + /* TODO: verify that cfg is ok to activate (check other chnl cfgs) */ + + chnl->cfg = cfg; + chnl->port = *port; + + chnl->synchronized_update = true; + if (port->type == MCDE_PORTTYPE_DSI) + chnl->pix_fmt = MCDE_PORTPIXFMT_DSI_16BPP; + else if (port->type == MCDE_PORTTYPE_DPI) + chnl->pix_fmt = MCDE_PORTPIXFMT_DPI_16BPP_C1; + mcde_chnl_apply(chnl); + + chnl->inuse = true; + update_channel_static_registers(chnl); + + goto out; + +find_config_failed: +out: + return chnl; +} + +int mcde_chnl_set_pixel_format(struct mcde_chnl_state *chnl, + enum mcde_port_pix_fmt pix_fmt) +{ + if (!chnl->inuse) + return -EINVAL; + chnl->pix_fmt = pix_fmt; + return 0; +} + +int mcde_chnl_set_rotation(struct mcde_chnl_state *chnl, + enum mcde_display_rotation rotation, u32 rotbuf1, u32 rotbuf2) +{ + if (!chnl->inuse) + return -EINVAL; + + /* TODO: Fix 180 degrees rotation */ + if (rotation == MCDE_DISPLAY_ROT_180_CCW || + (chnl->id != MCDE_CHNL_A && chnl->id != MCDE_CHNL_B)) + return -EINVAL; + + chnl->rotation = rotation; + chnl->rotbuf1 = rotbuf1; + chnl->rotbuf2 = rotbuf2; + + return 0; +} + +int mcde_chnl_enable_synchronized_update(struct mcde_chnl_state *chnl, + bool enable) +{ + if (!chnl->inuse) + return -EINVAL; + chnl->synchronized_update = enable; + return 0; +} + +int mcde_chnl_apply(struct mcde_chnl_state *chnl) +{ + /* TODO: lock *//* REVIEW: MCDE locking! */ + bool roten = false; + u8 rotdir = 0; + + if (!chnl->inuse) + return -EINVAL; + + if (chnl->rotation == MCDE_DISPLAY_ROT_90_CCW) { + roten = true; + rotdir = MCDE_ROTACONF_ROTDIR_CCW; + } else if (chnl->rotation == MCDE_DISPLAY_ROT_90_CW) { + roten = true; + rotdir = MCDE_ROTACONF_ROTDIR_CW; + } + /* REVIEW: 180 deg? */ + + chnl->regs.bpp = portfmt2bpp(chnl->pix_fmt); + chnl->regs.synchronized_update = chnl->synchronized_update; + chnl->regs.roten = roten; + chnl->regs.rotdir = rotdir; + chnl->regs.rotbuf1 = chnl->rotbuf1; + chnl->regs.rotbuf2 = chnl->rotbuf2; + if (chnl->port.type == MCDE_PORTTYPE_DSI) + chnl->regs.dsipacking = portfmt2dsipacking(chnl->pix_fmt); + else if (chnl->port.type == MCDE_PORTTYPE_DPI) { + tv_col_convert_apply(chnl); + tv_video_mode_apply(chnl); + } + chnl->transactionid++; + + dev_vdbg(&mcde_dev->dev, "Channel applied, chnl=%d\n", chnl->id); + return 0; +} + +static void chnl_update_registers(struct mcde_chnl_state *chnl) +{ + /* REVIEW: Move content to update_channel_register */ + /* and remove this one */ + if (chnl->port.type == MCDE_PORTTYPE_DPI) { + /* REVIEW: DSI? */ + update_col_registers(chnl->id, &chnl->col_regs); + update_tv_registers(chnl->id, &chnl->tv_regs); + } + update_channel_registers(chnl->id, &chnl->regs, &chnl->port, + &chnl->vmode); + + chnl->transactionid_regs = chnl->transactionid; +} + +static void chnl_update_continous(struct mcde_chnl_state *chnl) +{ + if (!chnl->continous_running) { + if (chnl->transactionid_regs < chnl->transactionid) + chnl_update_registers(chnl); + + if (chnl->port.sync_src == MCDE_SYNCSRC_TE0) + mcde_wfld(MCDE_CRC, SYCEN0, true); + else if (chnl->port.sync_src == MCDE_SYNCSRC_TE1) + mcde_wfld(MCDE_CRC, SYCEN1, true); + + chnl->continous_running = true; + } +} + +static void chnl_update_non_continous(struct mcde_chnl_state *chnl) +{ + /* Commit settings to registers */ + wait_for_channel(chnl); + if (chnl->transactionid_regs < chnl->transactionid) + chnl_update_registers(chnl); + + /* TODO: look at port sync source and synched_update */ + if (chnl->regs.synchronized_update) { + if (chnl->port.type == MCDE_PORTTYPE_DSI && + chnl->port.sync_src == MCDE_SYNCSRC_BTA) { + while (dsi_rfld(chnl->port.link, DSI_CMD_MODE_STS, + CSM_RUNNING)) + udelay(100); + dsi_te_request(chnl); + } + /* TODO: TE sync */ + } else { + mcde_wreg(MCDE_CHNL0SYNCHSW + + chnl->id * MCDE_CHNL0SYNCHSW_GROUPOFFSET, + MCDE_CHNL0SYNCHSW_SW_TRIG(true)); + dev_vdbg(&mcde_dev->dev, "Channel update (no sync), chnl=%d\n", + chnl->id); + } +} + +static void chnl_update_overlay(struct mcde_chnl_state *chnl, + struct mcde_ovly_state *ovly) +{ + if (ovly && (ovly->transactionid_regs < ovly->transactionid || + chnl->transactionid_regs < chnl->transactionid)) { + wait_for_overlay(ovly); + + update_overlay_registers(ovly->idx, &ovly->regs, &chnl->port, + chnl->regs.x, chnl->regs.y, + chnl->regs.ppl, chnl->regs.lpf, ovly->stride, + chnl->vmode.interlaced); + ovly->transactionid_regs = ovly->transactionid; + } +} + +int mcde_chnl_update(struct mcde_chnl_state *chnl, + struct mcde_rectangle *update_area) +{ + dev_vdbg(&mcde_dev->dev, "%s\n", __func__); + + /* TODO: lock & make wait->trig async */ + if (!chnl->inuse || !update_area + || (update_area->w == 0 && update_area->h == 0)) { + return -EINVAL; + } + + chnl->regs.x = update_area->x; + chnl->regs.y = update_area->y; + chnl->regs.ppl = update_area->w; + chnl->regs.lpf = update_area->h; + if (chnl->port.type == MCDE_PORTTYPE_DPI) {/* REVIEW: Comment */ + chnl->regs.ppl -= 2 * MCDE_CONFIG_TVOUT_HBORDER; + /* subtract double borders, ie. per field */ + chnl->regs.lpf -= 4 * MCDE_CONFIG_TVOUT_VBORDER; + } else if (chnl->port.type == MCDE_PORTTYPE_DSI && + chnl->vmode.interlaced) + chnl->regs.lpf /= 2; + + /*if (chnl->rotation == MCDE_DISPLAY_ROT_90_CCW) { + chnl->regs.ppl = update_area->h; + chnl->regs.lpf = update_area->w; + } else if (chnl->rotation == MCDE_DISPLAY_ROT_90_CW) { + chnl->regs.ppl = update_area->h; + chnl->regs.lpf = update_area->w; + }*/ + + chnl_update_overlay(chnl, chnl->ovly0); + chnl_update_overlay(chnl, chnl->ovly1); + + if (chnl->port.update_auto_trig) + chnl_update_continous(chnl); + else + chnl_update_non_continous(chnl); + + enable_channel(chnl->id); + + dev_vdbg(&mcde_dev->dev, "Channel updated, chnl=%d\n", chnl->id); + return 0; +} + +void mcde_chnl_put(struct mcde_chnl_state *chnl) +{ + /* TODO: If last channel, shutdown MCDE */ + /* TODO: Release formatter MCDE_CR.DPI/DSI_EN */ + if (!chnl->inuse) + return; + + mcde_chnl_apply(chnl); + chnl->inuse = false; + update_channel_static_registers(chnl); +} + +/* MCDE overlays */ +struct mcde_ovly_state *mcde_ovly_get(struct mcde_chnl_state *chnl) +{ + struct mcde_ovly_state *ovly; + + if (!chnl->inuse) + return ERR_PTR(-EINVAL); + + if (!chnl->ovly0->inuse) + ovly = chnl->ovly0; + else if (chnl->ovly1 && !chnl->ovly1->inuse) + ovly = chnl->ovly1; + else + ovly = ERR_PTR(-EBUSY); + + if (!IS_ERR(ovly)) { + ovly->inuse = true; + ovly->paddr = 0; + ovly->stride = 0; + ovly->pix_fmt = MCDE_OVLYPIXFMT_RGB565; + ovly->src_x = 0; + ovly->src_y = 0; + ovly->dst_x = 0; + ovly->dst_y = 0; + ovly->dst_z = 0; + ovly->w = 0; + ovly->h = 0; + mcde_ovly_apply(ovly); + } + + return ovly; +} + +void mcde_ovly_put(struct mcde_ovly_state *ovly) +{ + if (!ovly->inuse) + return; + if (ovly->regs.enabled) { + ovly->paddr = 0; + mcde_ovly_apply(ovly);/* REVIEW: API call calling API call! */ + } + ovly->inuse = false; +} + +void mcde_ovly_set_source_buf(struct mcde_ovly_state *ovly, u32 paddr) +{ + if (!ovly->inuse) + return; + + ovly->paddr = paddr; +} + +void mcde_ovly_set_source_info(struct mcde_ovly_state *ovly, + u32 stride, enum mcde_ovly_pix_fmt pix_fmt) +{ + if (!ovly->inuse) + return; + + ovly->stride = stride; + ovly->pix_fmt = pix_fmt; +} + +void mcde_ovly_set_source_area(struct mcde_ovly_state *ovly, + u16 x, u16 y, u16 w, u16 h) +{ + if (!ovly->inuse) + return; + + ovly->src_x = x; + ovly->src_y = y; + ovly->w = w; + ovly->h = h; +} + +void mcde_ovly_set_dest_pos(struct mcde_ovly_state *ovly, u16 x, u16 y, u8 z) +{ + if (!ovly->inuse) + return; + + ovly->dst_x = x; + ovly->dst_y = y; + ovly->dst_z = z; +} + +void mcde_ovly_apply(struct mcde_ovly_state *ovly) +{ + if (!ovly->inuse) + return; + + /* TODO: lock */ + + ovly->regs.ch_id = ovly->chnl->id; + ovly->regs.enabled = ovly->paddr != 0; + ovly->regs.baseaddress0 = ovly->paddr; + ovly->regs.baseaddress1 = ovly->paddr + ovly->stride; +/*TODO set to true if interlaced *//* REVIEW: Video mode interlaced? */ + ovly->regs.reset_buf_id = !ovly->chnl->continous_running; + switch (ovly->pix_fmt) {/* REVIEW: Extract to table */ + case MCDE_OVLYPIXFMT_RGB565: + ovly->regs.bits_per_pixel = 16; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_RGB565; + ovly->regs.bgr = false; + ovly->regs.bebo = false; + ovly->regs.opq = true; + break; + case MCDE_OVLYPIXFMT_RGBA5551: + ovly->regs.bits_per_pixel = 16; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_IRGB1555; + ovly->regs.bgr = false; + ovly->regs.bebo = false; + ovly->regs.opq = false; + break; + case MCDE_OVLYPIXFMT_RGBA4444: + ovly->regs.bits_per_pixel = 16; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_ARGB4444; + ovly->regs.bgr = false; + ovly->regs.bebo = false; + ovly->regs.opq = false; + break; + case MCDE_OVLYPIXFMT_RGB888: + ovly->regs.bits_per_pixel = 24; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_RGB888; + ovly->regs.bgr = true; + ovly->regs.bebo = false; + ovly->regs.opq = true; + break; + case MCDE_OVLYPIXFMT_RGBX8888: + ovly->regs.bits_per_pixel = 32; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_XRGB8888; + ovly->regs.bgr = true; + ovly->regs.bebo = true; + ovly->regs.opq = true; + break; + case MCDE_OVLYPIXFMT_RGBA8888: + ovly->regs.bits_per_pixel = 32; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_ARGB8888; + ovly->regs.bgr = true; + ovly->regs.bebo = true; + ovly->regs.opq = false; + break; + case MCDE_OVLYPIXFMT_YCbCr422: + ovly->regs.bits_per_pixel = 16; + ovly->regs.bpp = MCDE_EXTSRC0CONF_BPP_YCBCR422; + ovly->regs.bgr = false; + ovly->regs.bebo = false; + ovly->regs.opq = true; + break; + default: + break; + } + + ovly->regs.ppl = ovly->w; + ovly->regs.lpf = ovly->h; + ovly->regs.cropx = ovly->src_x; + ovly->regs.cropy = ovly->src_y; + ovly->regs.xpos = ovly->dst_x; + ovly->regs.ypos = ovly->dst_y; + ovly->regs.z = ovly->dst_z > 0; /* 0 or 1 */ + ovly->regs.col_conv = MCDE_OVL0CR_COLCCTRL_DISABLED; + + ovly->transactionid = ++ovly->chnl->transactionid; + + dev_vdbg(&mcde_dev->dev, "Overlay applied, chnl=%d\n", ovly->chnl->id); +} + +#ifdef CONFIG_REGULATOR +static int init_clocks_and_power(struct platform_device *pdev) +{ + int ret = 0; + struct mcde_platform_data *pdata = pdev->dev.platform_data; + if (pdata->regulator_id) { + regulator = regulator_get(&pdev->dev, + pdata->regulator_id); + if (IS_ERR(regulator)) { + ret = PTR_ERR(regulator); + dev_warn(&pdev->dev, + "%s: Failed to get regulator '%s'\n", + __func__, pdata->regulator_id); + goto regulator_err; + } + } else { + ret = -EINVAL; + dev_warn(&pdev->dev, "%s: No regulator id supplied\n" + , __func__); + goto regulator_err; + } + clock_dsi = clk_get(&pdev->dev, pdata->clock_dsi_id); + if (IS_ERR(clock_dsi)) { + ret = PTR_ERR(clock_dsi); + dev_warn(&pdev->dev, "%s: Failed to get clock '%s'\n", + __func__, pdata->clock_dsi_id); + goto clk_dsi_err; + } + + clock_dsi_lp = clk_get(&pdev->dev, pdata->clock_dsi_lp_id); + if (IS_ERR(clock_dsi_lp)) { + ret = PTR_ERR(clock_dsi_lp); + dev_warn(&pdev->dev, "%s: Failed to get clock '%s'\n", + __func__, pdata->clock_dsi_lp_id); + goto clk_dsi_lp_err; + } + + clock_mcde = clk_get(&pdev->dev, pdata->clock_mcde_id); + if (IS_ERR(clock_mcde)) { + ret = PTR_ERR(clock_mcde); + dev_warn(&pdev->dev, "%s: Failed to get clock '%s'\n", + __func__, pdata->clock_mcde_id); + goto clk_mcde_err; + } + + return ret; + +clk_mcde_err: + clk_put(clock_dsi_lp); +clk_dsi_lp_err: + clk_put(clock_dsi); +clk_dsi_err: + regulator_put(regulator); +regulator_err: + return ret; +} + +static void remove_clocks_and_power(struct platform_device *pdev) +{ + /* REVIEW: Release only if exist */ + /* REVIEW: Remove make sure MCDE is done */ + clk_put(clock_dsi); + clk_put(clock_dsi_lp); + clk_put(clock_mcde); + regulator_put(regulator); +} + +static int enable_clocks_and_power(struct platform_device *pdev) +{ + int ret = 0; + u32 ctrlreg; + if (regulator) { + ret = regulator_enable(regulator); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: regulator_enable failed\n", + __func__); + goto regulator_err; + } + } else { + ret = -EINVAL; + dev_warn(&pdev->dev, "%s: No regulator\n", __func__); + goto regulator_err; + } + /* REVIEW: Is this really needed? Move to meminit? */ + /* These reads make the secondary display to be turned on */ + ctrlreg = ab8500_read(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG); + ctrlreg = ab8500_read(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG); + ctrlreg = ab8500_read(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG); + ctrlreg = ab8500_read(AB8500_MISC, AB8500_PWM_OUT_CTRL3_REG); + ctrlreg = ab8500_read(AB8500_MISC, AB8500_PWM_OUT_CTRL4_REG); + + /* Enable the PWM control for the backlight */ + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, 0x7); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG, 0xFF); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG, 0x03); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL3_REG, 0xFF); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL4_REG, 0x03); + + ret = prcmu_set_hwacc(HW_ACC_ESRAM4, HW_ON); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: prcmu_set_hwacc ESRAM 4 failed" + " ret = %d\n", __func__, ret); + goto prcmu_set_err; + } + ret = prcmu_set_hwacc(HW_ACC_MCDE, HW_ON); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: " + "prcmu_set_hwacc MCDE failed ret = %d\n", + __func__, ret); + goto prcmu_set_err; + } + + ret = clk_enable(clock_dsi); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: " + "clk_enable dsi failed ret = %d\n", __func__, ret); + goto clk_dsi_err; + } + ret = clk_enable(clock_dsi_lp); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: " + "clk_enable dsi_lp failed ret = %d\n", __func__, ret); + goto clk_dsi_lp_err; + } + ret = clk_enable(clock_mcde); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: " + "clk_enable mcde failed ret = %d\n", __func__, ret); + goto clk_mcde_err; + } + + update_prmcu_registers(); + + return ret; + +clk_mcde_err: + clk_disable(clock_dsi_lp); +clk_dsi_lp_err: + clk_disable(clock_dsi); +clk_dsi_err: + if (regulator) + regulator_disable(regulator); +regulator_err: + (void)prcmu_set_hwacc(HW_ACC_MCDE, HW_OFF); +prcmu_set_err: + + return ret; +} + +static int disable_clocks_and_power(struct platform_device *pdev) +{ + int ret = 0; + + clk_disable(clock_dsi_lp); + clk_disable(clock_mcde); + clk_disable(clock_dsi); + if (regulator) { + ret = regulator_disable(regulator); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: regulator_disable failed\n" + , __func__); + goto regulator_err; + } + } else { + ret = -EINVAL; + dev_warn(&pdev->dev, "%s: No regulator\n", __func__); + goto regulator_err; + } + + (void)prcmu_set_hwacc(HW_ACC_MCDE, HW_OFF); + + /* Disable the PWM control for the backlight */ + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL7_REG, 0x0); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL1_REG, 0x0); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL2_REG, 0x0); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL3_REG, 0x0); + ab8500_write(AB8500_MISC, AB8500_PWM_OUT_CTRL4_REG, 0x0); + + return ret; +regulator_err: + clk_enable(clock_dsi_lp); + clk_enable(clock_mcde); + clk_enable(clock_dsi); + return ret; +} + +static int enable_dss(struct platform_device *pdev) +{ + int ret; + ret = init_clocks_and_power(pdev); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: init_clocks_and_power" + " failed\n", __func__); + goto init_clock_err; + } + ret = enable_clocks_and_power(pdev); + if (ret < 0) { + dev_warn(&pdev->dev, "%s: enable_clocks_and_power" + " failed\n", __func__); + goto enable_clock_err; + } + return ret; + +init_clock_err: +enable_clock_err: + return ret; +} +#endif + +static void update_prmcu_registers(void) +{ + /* TODO: PRCMU stuff, move to regulator/clock framework */ + + /* Setup clocks */ + #define MCDE_PRCM_MMIP_LS_CLAMP_SET 0x420 + #define MCDE_PRCM_APE_RESETN_CLR 0x1E8 + #define MCDE_PRCM_EPOD_C_SET 0x410 + #define MCDE_PRCM_SRAM_LS_SLEEP 0x304 + #define MCDE_PRCM_MMIP_LS_CLAMP_CLR 0x424 + #define MCDE_PRCM_POWER_STATE_SET 0x254 + #define MCDE_PRCM_LCDCLK_MGT 0x044 + #define MCDE_PRCM_MCDECLK_MGT 0x064 + #define MCDE_PRCM_HDMICLK_MGT 0x058 + #define MCDE_PRCM_TVCLK_MGT 0x07c + #define MCDE_PRCM_PLLDSI_FREQ 0x500 + #define MCDE_PRCM_PLLDSI_ENABLE 0x504 + #define MCDE_PRCM_APE_RESETN_SET 0x1E4 + #define MCDE_PRCM_DSI_PLLOUT_SEL 0x530 + #define MCDE_PRCM_DSITVCLK_DIV 0x52C + #define MCDE_PRCM_DSI_SW_RESET 0x324 + + /* Clamp DSS out, DSIPLL in/out, (why not DSS input?) */ +#ifndef CONFIG_REGULATOR + u32 temp; +#endif + u8 *prcmu = ioremap(0x80157000, 0x1000); + printk(KERN_INFO "ioremap prcmu %.8X\n", (u32)prcmu); + writel(0x00600C00, &prcmu[MCDE_PRCM_MMIP_LS_CLAMP_SET]); + mdelay(10); + /* Enable DSS_M_INITN, DSS_L_RESETN, DSIPLL_RESETN resets */ + writel(0x0000000C, &prcmu[MCDE_PRCM_APE_RESETN_CLR]); + mdelay(10); +#ifndef CONFIG_REGULATOR + /* Power on DSS mem */ + writel(0x00200000, &prcmu[MCDE_PRCM_EPOD_C_SET]); + mdelay(10); + /* Power on DSS logic */ + writel(0x00100000, &prcmu[MCDE_PRCM_EPOD_C_SET]); + mdelay(10); + /* Release DSS_SLEEP */ + temp = readl(&prcmu[MCDE_PRCM_SRAM_LS_SLEEP]); + writel(temp & ~0x400, &prcmu[MCDE_PRCM_SRAM_LS_SLEEP]); + mdelay(10); +#endif + /* Unclamp DSS out, DSIPLL in/out, (why not DSS input?) */ + writel(0x00600C00, &prcmu[MCDE_PRCM_MMIP_LS_CLAMP_CLR]); + mdelay(10); +#ifndef CONFIG_REGULATOR + /* Power on CSI_DSI */ + writel(0x00008000, &prcmu[MCDE_PRCM_POWER_STATE_SET]); + mdelay(10); + /* PLLDIV=8, PLLSW=2, CLKEN=1 */ + writel(0x00000148, &prcmu[MCDE_PRCM_LCDCLK_MGT]); + mdelay(10); + /* PLLDIV=5, PLLSW=1, CLKEN=1 */ + writel(0x00000125, &prcmu[MCDE_PRCM_MCDECLK_MGT]); + mdelay(10); +#endif + /* HDMI and TVCLK Should be handled somewhere else */ + /* PLLDIV=5, PLLSW=2, CLKEN=1 */ + writel(0x00000145, &prcmu[MCDE_PRCM_HDMICLK_MGT]); + mdelay(10); + /* PLLDIV=14, PLLSW=2, CLKEN=1 */ + writel(0x00000141, &prcmu[MCDE_PRCM_TVCLK_MGT]); /*148*/ + mdelay(10); + + /* D=43, N=1, R=4, SELDIV2=0 */ + writel(0x0004012B, &prcmu[MCDE_PRCM_PLLDSI_FREQ]); + mdelay(10); + /* Start DSI PLL */ + writel(0x00000001, &prcmu[MCDE_PRCM_PLLDSI_ENABLE]); + mdelay(10); + /* Release DSS_M_INITN, DSS_L_RESETN, DSIPLL_RESETN */ + writel(0x0000400C, &prcmu[MCDE_PRCM_APE_RESETN_SET]); + mdelay(10); + /* DSI0=phi/2, DSI1=phi/2 */ + writel(0x00000202, &prcmu[MCDE_PRCM_DSI_PLLOUT_SEL]); + mdelay(10); + /* Enable ESC clk 0/1/2, div0=3, div1=3, div2=3 */ + writel(0x07031717, &prcmu[MCDE_PRCM_DSITVCLK_DIV]); + mdelay(10); + /* Release DSI reset 0/1/2 */ + writel(0x00000007, &prcmu[MCDE_PRCM_DSI_SW_RESET]); + mdelay(10); + + printk(KERN_INFO "PRCMU setup done!\n"); + mdelay(100); +} + +static void update_mcde_registers(void) +{ + struct mcde_platform_data *pdata = mcde_dev->dev.platform_data; + + /* Setup output muxing */ + mcde_wreg(MCDE_CONF0, + MCDE_CONF0_IFIFOCTRLWTRMRKLVL(7) | + MCDE_CONF0_OUTMUX0(pdata->outmux[0]) | + MCDE_CONF0_OUTMUX1(pdata->outmux[1]) | + MCDE_CONF0_OUTMUX2(pdata->outmux[2]) | + MCDE_CONF0_OUTMUX3(pdata->outmux[3]) | + MCDE_CONF0_OUTMUX4(pdata->outmux[4]) | + pdata->syncmux); + + /* Enable channel VCMP interrupts */ + mcde_wreg(MCDE_IMSCPP, + MCDE_IMSCPP_VCMPAIM(true) | + MCDE_IMSCPP_VCMPBIM(true) | + MCDE_IMSCPP_VCMPC0IM(true) | + MCDE_IMSCPP_VCMPC1IM(true)); + + /* Enable overlay fetch done interrupts */ + mcde_wfld(MCDE_IMSCOVL, OVLFDIM, 0x3f); + + /* Setup sync pulse length */ + mcde_wreg(MCDE_VSCRC0, + MCDE_VSCRC0_VSPMIN(1) | + MCDE_VSCRC0_VSPMAX(0xff)); + mcde_wreg(MCDE_VSCRC1, + MCDE_VSCRC1_VSPMIN(1) | + MCDE_VSCRC1_VSPMAX(0xff)); +} + +static int __devinit mcde_probe(struct platform_device *pdev) +{ + int ret = 0; + int i, irq; + struct resource *res; + struct mcde_platform_data *pdata = pdev->dev.platform_data; + + if (!pdata) { + dev_dbg(&pdev->dev, "No platform data\n"); + return -EINVAL; + } + + num_dsilinks = pdata->num_dsilinks; + mcde_dev = pdev; + + dsiio = kzalloc(num_dsilinks * sizeof(*dsiio), GFP_KERNEL); + if (!dsiio) { + ret = -ENOMEM; + goto failed_dsi_alloc; + } + + /* Hook up irq */ + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_dbg(&pdev->dev, "No irq defined\n"); + ret = -EINVAL; + goto failed_irq_get; + } + ret = request_irq(irq, mcde_irq_handler, 0, "mcde", &pdev->dev); + if (ret) { + dev_dbg(&pdev->dev, "Failed to request irq (irq=%d)\n", irq); + goto failed_request_irq; + } + + /* Map I/O */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_dbg(&pdev->dev, "No MCDE io defined\n"); + ret = -EINVAL; + goto failed_get_mcde_io; + } + mcdeio = ioremap(res->start, res->end - res->start + 1); + if (!mcdeio) { + dev_dbg(&pdev->dev, "MCDE iomap failed\n"); + ret = -EINVAL; + goto failed_map_mcde_io; + } + dev_info(&pdev->dev, "MCDE iomap: 0x%.8X->0x%.8X\n", + (u32)res->start, (u32)mcdeio); + for (i = 0; i < num_dsilinks; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1+i); + if (!res) { + dev_dbg(&pdev->dev, "No DSI%d io defined\n", i); + ret = -EINVAL; + goto failed_get_dsi_io; + } + dsiio[i] = ioremap(res->start, res->end - res->start + 1); + if (!dsiio[i]) { + dev_dbg(&pdev->dev, "MCDE DSI%d iomap failed\n", i); + ret = -EINVAL; + goto failed_map_dsi_io; + } + dev_info(&pdev->dev, "MCDE DSI%d iomap: 0x%.8X->0x%.8X\n", + i, (u32)res->start, (u32)dsiio[i]); + } + + /* REVIEW: Move clocks and regulator to probe */ + /* TODO: temp, replace with regulator_ and clk_ calls */ +#ifdef CONFIG_REGULATOR + enable_dss(pdev); +#else + update_prmcu_registers(); +#endif + + update_mcde_registers(); + + dev_info(&mcde_dev->dev, "Probe done (v%d.%d.%d.%d)\n", + mcde_rfld(MCDE_PID, MAJOR_VERSION), + mcde_rfld(MCDE_PID, MINOR_VERSION), + mcde_rfld(MCDE_PID, DEVELOPMENT_VERSION), + mcde_rfld(MCDE_PID, METALFIX_VERSION)); + goto out; +failed_map_dsi_io: +failed_get_dsi_io: + for (i = 0; i < num_dsilinks; i++) { + if (dsiio[i]) + iounmap(dsiio[i]); + } + iounmap(mcdeio); +failed_map_mcde_io: +failed_get_mcde_io: + free_irq(irq, &pdev->dev); +failed_request_irq: +failed_irq_get: + kfree(dsiio); + dsiio = NULL; +failed_dsi_alloc: +out: + return ret; +} + +static int __devexit mcde_remove(struct platform_device *pdev) +{ +#ifdef CONFIG_REGULATOR + remove_clocks_and_power(pdev); +#endif + return 0; +} + +#ifdef CONFIG_REGULATOR +static int mcde_resume(struct platform_device *pdev) +{ + int ret; + struct mcde_chnl_state *chnl = &channels[0]; + dev_info(&pdev->dev, "Resume is called\n"); + ret = enable_clocks_and_power(pdev); + if (ret < 0) { + dev_dbg(&pdev->dev, "Enable clocks and power " + "failed in resume\n"); + goto clock_err; + } + update_mcde_registers(); + + for (; chnl < &channels[ARRAY_SIZE(channels)]; chnl++) { + if (chnl->inuse) { + update_channel_static_registers(chnl); + update_channel_registers(chnl->id, &chnl->regs, + &chnl->port, &chnl->vmode); + if (chnl->ovly0) + update_overlay_registers(chnl->ovly0->idx, + &chnl->ovly0->regs, &chnl->port, + chnl->regs.x, chnl->regs.y, + chnl->regs.ppl, chnl->regs.lpf, + chnl->ovly0->stride, + chnl->vmode.interlaced); + if (chnl->ovly1) + update_overlay_registers(chnl->ovly1->idx, + &chnl->ovly1->regs, &chnl->port, + chnl->regs.x, chnl->regs.y, + chnl->regs.ppl, chnl->regs.lpf, + chnl->ovly1->stride, + chnl->vmode.interlaced); + } + } + return ret; +clock_err: + return ret; +} + +static int mcde_suspend(struct platform_device *pdev, pm_message_t state) +{ + dev_info(&pdev->dev, "Suspend is called\n"); + return disable_clocks_and_power(pdev); +} +#endif + +static struct platform_driver mcde_driver = { + .probe = mcde_probe, + .remove = mcde_remove, +#ifdef CONFIG_REGULATOR + .suspend = mcde_suspend, + .resume = mcde_resume, +#else + .suspend = NULL, + .resume = NULL, +#endif + .driver = { + .name = "mcde", + }, +}; + +/* REVIEW: __init? */ +int mcde_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(channels); i++) { + channels[i].ovly0->chnl = &channels[i]; + if (channels[i].ovly1) + channels[i].ovly1->chnl = &channels[i]; + init_waitqueue_head(&channels[i].waitq_hw); + } + for (i = 0; i < ARRAY_SIZE(overlays); i++) + init_waitqueue_head(&overlays[i].waitq_hw); + + return platform_driver_register(&mcde_driver); +} + +void mcde_exit(void) +{ + /* REVIEW: shutdown MCDE? */ + platform_driver_unregister(&mcde_driver); +} diff --git a/drivers/video/mcde/mcde_hwaccess.c b/drivers/video/mcde/mcde_hwaccess.c deleted file mode 100644 index bef9103eb2c..00000000000 --- a/drivers/video/mcde/mcde_hwaccess.c +++ /dev/null @@ -1,6577 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT -/* HW V1 */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -/** Linux include files:charachter driver and memory functions */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <mach/mcde_common.h> -#include <mach/mcde_a0.h> - -extern struct mcdefb_info *gpar[]; - -#define PLATFORM_8500 1 - - -mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config) -{ - mcde_error error = MCDE_OK; - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLLOUT_DIVSEL1_MASK) | - (((u32) clk_config.pllout_divsel1 << MCDE_PLLOUT_DIVSEL1_SHIFT) & MCDE_PLLOUT_DIVSEL1_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLLOUT_DIVSEL0_MASK) | - (((u32) clk_config.pllout_divsel0 << MCDE_PLLOUT_DIVSEL0_SHIFT) & MCDE_PLLOUT_DIVSEL0_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLL4IN_SEL_MASK) | - (((u32) clk_config.pll4in_sel << MCDE_PLL4IN_SEL_SHIFT) & MCDE_PLL4IN_SEL_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_TXESCDIV_SEL_MASK) | - (((u32) clk_config.pll4in_sel << MCDE_TXESCDIV_SEL_SHIFT) & MCDE_TXESCDIV_SEL_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_TXESCDIV_MASK) | - ((u32) clk_config.pll4in_sel & MCDE_TXESCDIV_MASK) - ); - - return(error); -} - - -mcde_error mcdesetdsicommandword -( - dsi_link link, - mcde_ch_id chid, - mcde_dsi_channel dsichannel, - u8 cmdbyte_lsb, - u8 cmdbyte_msb -) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - /* Importante: Register definition changed! */ - dsi_reg->mcde_dsi_cmdw = - ( - (dsi_reg->mcde_dsi_cmdw &~MCDE_CMDBYTE_LSB_MASK) | - ((u32) cmdbyte_lsb & MCDE_CMDBYTE_LSB_MASK) - ); - - dsi_reg->mcde_dsi_cmdw = - ( - (dsi_reg->mcde_dsi_cmdw &~MCDE_CMDBYTE_MSB_MASK) | - (((u32) cmdbyte_msb << MCDE_CMDBYTE_MSB_SHIFT) & MCDE_CMDBYTE_MSB_MASK) - ); - - return(error); -} - -mcde_error mcdesetdsisyncpulse(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, u16 sync_dma, u16 sync_sw) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - dsi_reg->mcde_dsi_sync = ((dsi_reg->mcde_dsi_sync &~MCDE_DSI_DMA_MASK) | ((u32) sync_dma & MCDE_DSI_DMA_MASK)); - - dsi_reg->mcde_dsi_sync = - ( - (dsi_reg->mcde_dsi_sync &~MCDE_DSI_SW_MASK) | - (((u32) sync_dma << MCDE_DSI_SW_SHIFT) & MCDE_DSI_SW_MASK) - ); - - - return(error); -} - -mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_PACK_MASK) | - (((u32) dsi_conf.packing << MCDE_DSI_PACK_SHIFT) & MCDE_DSI_PACK_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_DCSVID_MASK) | - (((u32) dsi_conf.synchro << MCDE_DSI_DCSVID_SHIFT) & MCDE_DSI_DCSVID_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_BYTE_SWAP_MASK) | - (((u32) dsi_conf.byte_swap << MCDE_DSI_BYTE_SWAP_SHIFT) & MCDE_DSI_BYTE_SWAP_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_BIT_SWAP_MASK) | - (((u32) dsi_conf.bit_swap << MCDE_DSI_BIT_SWAP_SHIFT) & MCDE_DSI_BIT_SWAP_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_CMD8_MASK) | - (((u32) dsi_conf.cmd8 << MCDE_DSI_CMD8_SHIFT) & MCDE_DSI_CMD8_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_VID_MODE_MASK) | - (((u32) dsi_conf.vid_mode << MCDE_DSI_VID_MODE_SHIFT) & MCDE_DSI_VID_MODE_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_BLANKING_MASK) | - ((u32) dsi_conf.blanking & MCDE_BLANKING_MASK) - ); - - dsi_reg->mcde_dsi_frame = - ( - (dsi_reg->mcde_dsi_frame &~MCDE_DSI_FRAME_MASK) | - ((u32) dsi_conf.words_per_frame & MCDE_DSI_FRAME_MASK) - ); - - dsi_reg->mcde_dsi_pkt = - ( - (dsi_reg->mcde_dsi_pkt &~MCDE_DSI_PACKET_MASK) | - ((u32) dsi_conf.words_per_packet & MCDE_DSI_PACKET_MASK) - ); - return(error); -} - - - -/****************************************************************************/ -/** NAME : mcdesetfifoctrl() */ -/*--------------------------------------------------------------------------*/ -/* DESCRIPTION : This routine sets the formatter selection for output FIFOs*/ -/* */ -/* */ -/* PARAMETERS : */ -/* IN :mcde_fifo_ctrl : FIFO selection control structure */ -/* InOut :None */ -/* OUT :None */ -/* */ -/* RETURN :mcde_error : MCDE error code */ -/* MCDE_OK */ -/* MCDE_INVALID_PARAMETER :if input argument is invalid */ -/*--------------------------------------------------------------------------*/ -/* Type : PUBLIC */ -/* REENTRANCY : Non Re-entrant */ -/* REENTRANCY ISSUES : */ - -/****************************************************************************/ -mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl) -{ - mcde_error error = MCDE_OK; - - /*FIFO A Output Selection*/ - switch (chid) - { - case MCDE_CH_A: - switch (fifo_ctrl.out_fifoa) - { - case MCDE_DPI_A: - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - break; - - case MCDE_DSI_VID0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID0] = MCDE_CH_A; - - break; - - case MCDE_DSI_VID1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID1] = MCDE_CH_A; - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD2_EN_MASK) | - ((u32) MCDE_SET_BIT & MCDE_DSICMD2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_A; - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_B: - /*FIFO B Output Selection*/ - switch (fifo_ctrl.out_fifob) - { - case MCDE_DPI_B: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - break; - - case MCDE_DSI_VID0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID0] = MCDE_CH_B; - break; - - case MCDE_DSI_VID1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID1] = MCDE_CH_B; - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD2_EN_MASK) | - ((u32) MCDE_SET_BIT & MCDE_DSICMD2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_B; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_C0: - /*FIFO 0 Output Selection*/ - switch (fifo_ctrl.out_fifo0) - { - case MCDE_DBI_C0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - break; - - case MCDE_DSI_CMD0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD0] = MCDE_CH_C0; - - break; - - case MCDE_DSI_CMD1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD1] = MCDE_CH_C0; - break; - - case MCDE_DSI_VID2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID2_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID2_EN_SHIFT) & MCDE_DSIVID2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID2] = MCDE_CH_C0; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_C1: - /*FIFO 1 Output Selection*/ - switch (fifo_ctrl.out_fifo1) - { - case MCDE_DBI_C1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - break; - - case MCDE_DSI_CMD0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD0] = MCDE_CH_C1; - - break; - - case MCDE_DSI_CMD1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD1] = MCDE_CH_C1; - - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID2_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID2_EN_SHIFT) & MCDE_DSIVID2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_C1; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - default: - error = MCDE_INVALID_PARAMETER; - } - return(error); -} -#ifdef PLATFORM_8500 -mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf) -{ - mcde_error error = MCDE_OK; - - // if (chid == CHANNEL_C0) - // gpar[chid]->regbase->mcde_conf0 = 0x5e145001; /** has to be removed, Added for testing */ - - switch (output_conf) - { - case MCDE_CONF_TVA_DPIC0_LCDB: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_TVA_DPIC0_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_TVB_DPIC1_LCDA: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_TVB_DPIC1_LCDA_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_DPIC1_LCDA: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DPIC1_LCDA_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_DPIC0_LCDB: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DPIC0_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_LCDA_LCDB: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_LCDA_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - case MCDE_CONF_DSI: - gpar[chid]->regbase->mcde_conf0 = - ( - (gpar[chid]->regbase->mcde_conf0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DSI_MASK & MCDE_SYNCMUX_MASK) - ); - break; - default: - error = MCDE_INVALID_PARAMETER; - } - - return(error); -} -#endif -/****************************************************************************/ -/* NAME : mcdesetbufferaddr() */ -/*--------------------------------------------------------------------------*/ -/* DESCRIPTION : This API is used to set the base address of the buffer. */ -/* */ -/* */ -/* PARAMETERS : */ -/* IN :mcde_ext_src src_id: External source id number to be */ -/* configured */ -/* mcde_buffer_id buffer_id : Buffer id whose address is */ -/* to be configured */ -/* uint32 address : Address of the buffer */ -/* InOut :None */ -/* OUT :None */ -/* */ -/* RETURN :mcde_error : MCDE error code */ -/* MCDE_OK */ -/* MCDE_INVALID_PARAMETER :if input argument is invalid */ -/*--------------------------------------------------------------------------*/ -/* Type : PUBLIC */ -/* REENTRANCY : Non Re-entrant */ -/* REENTRANCY ISSUES : */ - -/****************************************************************************/ -mcde_error mcdesetbufferaddr -( - mcde_ch_id chid, - mcde_ext_src src_id, - mcde_buffer_id buffer_id, - u32 address -) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - switch (buffer_id) - { - case MCDE_BUFFER_ID_0: - ext_src->mcde_extsrc_a0 = - ( - (ext_src->mcde_extsrc_a0 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - case MCDE_BUFFER_ID_1: - ext_src->mcde_extsrc_a1 = - ( - (ext_src->mcde_extsrc_a1 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - case MCDE_BUFFER_ID_2: - ext_src->mcde_extsrc_a2 = - ( - (ext_src->mcde_extsrc_a2 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) buffer_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - return(error); -} - -mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BEPO_MASK) | - (((u32) config.ovr_pxlorder << MCDE_EXT_BEPO_SHIFT) & MCDE_EXT_BEPO_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BEBO_MASK) | - (((u32) config.endianity << MCDE_EXT_BEBO_SHIFT) & MCDE_EXT_BEBO_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BGR_MASK) | - (((u32) config.rgb_format << MCDE_EXT_BGR_SHIFT) & MCDE_EXT_BGR_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BPP_MASK) | - (((u32) config.bpp << MCDE_EXT_BPP_SHIFT) & MCDE_EXT_BPP_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_PRI_OVR_MASK) | - (((u32) config.provr_id << MCDE_EXT_PRI_OVR_SHIFT) & MCDE_EXT_PRI_OVR_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_NUM_MASK) | - (((u32) config.buf_num << MCDE_EXT_BUFFER_NUM_SHIFT) & MCDE_EXT_BUFFER_NUM_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) config.buf_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - return(error); -} - -mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_FORCEFSDIV_MASK) | - (((u32) control.fs_div << MCDE_EXT_FORCEFSDIV_SHIFT) & MCDE_EXT_FORCEFSDIV_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_FSDISABLE_MASK) | - (((u32) control.fs_ctrl << MCDE_EXT_FSDISABLE_SHIFT) & MCDE_EXT_FSDISABLE_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_OVR_CTRL_MASK) | - (((u32) control.ovr_ctrl << MCDE_EXT_OVR_CTRL_SHIFT) & MCDE_EXT_OVR_CTRL_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_BUF_MODE_MASK) | - ((u32) control.sel_mode & MCDE_EXT_BUF_MODE_MASK) - ); - - return(error); -} -mcde_error mcdesetbufid(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, mcde_num_buffer_used buffer_num) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - if ((int) buffer_id > 2) - { - return(MCDE_INVALID_PARAMETER); - } - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) buffer_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_NUM_MASK) | - (((u32) buffer_num << MCDE_EXT_BUFFER_NUM_SHIFT) & MCDE_EXT_BUFFER_NUM_MASK) - ); - - - return(error); -} -mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_COLCTRL_MASK) | - (((u32) col_ctrl << MCDE_OVR_COLCTRL_SHIFT) & MCDE_OVR_COLCTRL_MASK) - ); - return error; -} -mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr) -{ -#if 0 /* this is old ED func, register has been updated */ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_OVLEN_MASK) | - ((u32) ovr_cr.ovr_state & MCDE_OVR_OVLEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_COLCTRL_MASK) | - (((u32) ovr_cr.col_ctrl << MCDE_OVR_COLCTRL_SHIFT) & MCDE_OVR_COLCTRL_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_PALCTRL_MASK) | - (((u32) ovr_cr.pal_control << MCDE_OVR_PALCTRL_SHIFT) & MCDE_OVR_PALCTRL_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_CKEYEN_MASK) | - (((u32) ovr_cr.color_key << MCDE_OVR_CKEYEN_SHIFT) & MCDE_OVR_CKEYEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_STBPRIO_MASK) | - (((u32) ovr_cr.priority << MCDE_OVR_STBPRIO_SHIFT) & MCDE_OVR_STBPRIO_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_BURSTSZ_MASK) | - (((u32) ovr_cr.burst_req << MCDE_OVR_BURSTSZ_SHIFT) & MCDE_OVR_BURSTSZ_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_MAXREQ_MASK) | - (((u32) ovr_cr.outstnd_req << MCDE_OVR_MAXREQ_SHIFT) & MCDE_OVR_MAXREQ_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_ROTBURSTSIZE_MASK) | - (((u32) ovr_cr.rot_burst_req << MCDE_OVR_ROTBURSTSIZE_SHIFT) & MCDE_OVR_ROTBURSTSIZE_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_ALPHAPMEN_MASK) | - (((u32) ovr_cr.alpha << MCDE_OVR_ALPHAPMEN_SHIFT) & MCDE_OVR_ALPHAPMEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_CLIPEN_MASK) | - (((u32) ovr_cr.clip << MCDE_OVR_CLIPEN_SHIFT) & MCDE_OVR_CLIPEN_MASK) - ); - - return(error); -#endif - return MCDE_UNSUPPORTED_FEATURE; -} - -mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_LPF_MASK) | - (((u32) ovr_conf.line_per_frame << MCDE_OVR_LPF_SHIFT) & MCDE_OVR_LPF_MASK) - ); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_EXT_SRCID_MASK) | - (((u32) ovr_conf.src_id << MCDE_EXT_SRCID_SHIFT) & MCDE_EXT_SRCID_MASK) - ); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_PPL_MASK) | - ((u32) ovr_conf.ovr_ppl & MCDE_OVR_PPL_MASK) - ); - - return(error); -} - -mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_WATERMARK_MASK) | - (((u32) ovr_conf2.watermark_level << MCDE_WATERMARK_SHIFT) & MCDE_WATERMARK_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_OVR_OPQ_MASK) | - (((u32) ovr_conf2.ovr_opaq << MCDE_OVR_OPQ_SHIFT) & MCDE_OVR_OPQ_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_ALPHAVALUE_MASK) | - (((u32) ovr_conf2.alpha_value << MCDE_ALPHAVALUE_SHIFT) & MCDE_ALPHAVALUE_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_PIXOFF_MASK) | - (((u32) ovr_conf2.pixoff << MCDE_PIXOFF_SHIFT) & MCDE_PIXOFF_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_OVR_BLEND_MASK) | - ((u32) ovr_conf2.ovr_blend & MCDE_OVR_BLEND_MASK) - ); - - return(error); -} -mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_ljinc = ((ovr_ljinc << MCDE_LINEINCREMENT_SHIFT) & MCDE_LINEINCREMENT_MASK); - - return(error); -} -#ifdef PLATFORM_8500 -mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin) -{ -#if 0 /* this is old ED func, register has been updated */ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - - ovr_config->mcde_ovl_crop = - ( - (ovr_config->mcde_ovl_crop &~MCDE_YCLIP_MASK) | - ((ovr_topmargin << MCDE_YCLIP_SHIFT) & MCDE_YCLIP_MASK) - ); - - - ovr_config->mcde_ovl_crop = - ( - (ovr_config->mcde_ovl_crop &~MCDE_XCLIP_MASK) | - (((u32) ovr_leftmargin << MCDE_XCLIP_SHIFT) & MCDE_XCLIP_MASK) - ); - - - return(error); -#endif - return MCDE_UNSUPPORTED_FEATURE; -} -#endif -mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_ZLEVEL_MASK) | - (((u32) ovr_comp.ovr_zlevel << MCDE_OVR_ZLEVEL_SHIFT) & MCDE_OVR_ZLEVEL_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_YPOS_MASK) | - (((u32) ovr_comp.ovr_ypos << MCDE_OVR_YPOS_SHIFT) & MCDE_OVR_YPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_CHID_MASK) | - (((u32) ovr_comp.ch_id << MCDE_OVR_CHID_SHIFT) & MCDE_OVR_CHID_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_XPOS_MASK) | - ((u32) ovr_comp.ovr_xpos & MCDE_OVR_XPOS_MASK) - ); - - return(error); -} - -#ifdef PLATFORM_8500 -mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - /* TODO: Not implemented - ovr_config->mcde_ovl_bot_rht_clip= - ( - (ovr_config->mcde_ovl_bot_rht_clip&~MCDE_YBRCOOR_MASK) | - (((u32) ovr_clip.ybrcoor << MCDE_YBRCOOR_SHIFT) & MCDE_YBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_top_left_clip= - ( - (ovr_config->mcde_ovl_top_left_clip &~MCDE_YBRCOOR_MASK) | - (((u32) ovr_clip.ytlcoor << MCDE_YBRCOOR_SHIFT) & MCDE_YBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_bot_rht_clip = - ( - (ovr_config->mcde_ovl_bot_rht_clip &~MCDE_XBRCOOR_MASK) | - ((u32) ovr_clip.xbrcoor & MCDE_XBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_top_left_clip = - ( - (ovr_config->mcde_ovl_top_left_clip &~MCDE_XBRCOOR_MASK) | - ((u32) ovr_clip.xtlcoor & MCDE_XBRCOOR_MASK) - ); - */ - return(error); -} -#endif - -mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_cr = ((ovr_config->mcde_ovl_cr &~MCDE_OVR_OVLEN_MASK) | (state & MCDE_OVR_OVLEN_MASK)); - - return(error); -} - -mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_PPL_MASK) | - ((u32) ppl & MCDE_OVR_PPL_MASK) - ); - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_LPF_MASK) | - (((u32) lpf << MCDE_OVR_LPF_SHIFT) & MCDE_OVR_LPF_MASK) - ); - - - return(error); -} - -mcde_error mcdeovraassociatechnl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ch_id ch_id) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_CHID_MASK) | - (((u32) ch_id << MCDE_OVR_CHID_SHIFT) & MCDE_OVR_CHID_MASK) - ); - - return(error); -} - - -mcde_error mcdesetovrXYZpos(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ovr_xy xy_pos, u8 z_pos) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_YPOS_MASK) | - (((u32) xy_pos.ovr_ypos << MCDE_OVR_YPOS_SHIFT) & MCDE_OVR_YPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_XPOS_MASK) | - ((u32) xy_pos.ovr_xpos & MCDE_OVR_XPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_ZLEVEL_MASK) | - (((u32) z_pos << MCDE_OVR_ZLEVEL_SHIFT) & MCDE_OVR_ZLEVEL_MASK) - ); - - return(error); -} - -mcde_error mcdeovrassociateextsrc(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ext_src ext_src) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_EXT_SRCID_MASK) | - (((u32) ext_src << MCDE_EXT_SRCID_SHIFT) & MCDE_EXT_SRCID_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config) -{ - mcde_error mcde_error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_conf = ((config.lpf & MCDE_CHNLCONF_LPF_MASK) << MCDE_CHNLCONF_LPF_SHIFT) | - ((config.ppl & MCDE_CHNLCONF_PPL_MASK) << MCDE_CHNLCONF_PPL_SHIFT); - - return(mcde_error); -} - -mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod) -{ - mcde_error mcde_error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_synchmod = ((sync_mod.out_synch_interface & MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK) << MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT) | - ((sync_mod.ch_synch_src & MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK) << MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT); - - return(mcde_error); -} - -mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config) -{ - mcde_error mcde_error = MCDE_OK; -#ifdef PLATFORM_8500 - struct mcde_chAB_reg *ch_x_reg; -#else - struct mcde_chnl_conf_reg *ch_x_reg; -#endif - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { -#ifdef PLATFORM_8500 - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); -#else - ch_x_reg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[gpar[chid]->mcde_cur_ovl_bmp]); -#endif - - } - - ch_x_reg->mcde_synchconf = ((ch_x_reg->mcde_synchconf & ~MCDE_SWINTVCNT_MASK) | (((u32)ch_config.swint_vcnt << MCDE_SWINTVCNT_SHIFT) & MCDE_SWINTVCNT_MASK)); - /** set to active video if you want to receive VSYNC interrupts*/ - ch_x_reg->mcde_synchconf = ((ch_x_reg->mcde_synchconf & ~MCDE_SWINTVEVENT_MASK) | (((u32)ch_config.swint_vevent << MCDE_SWINTVEVENT_SHIFT) & MCDE_SWINTVEVENT_MASK)); - ch_x_reg->mcde_synchconf = ((ch_x_reg->mcde_synchconf & ~MCDE_HWREQVCNT_MASK) | (((u32)ch_config.hwreq_vcnt << MCDE_HWREQVCNT_SHIFT) & MCDE_HWREQVCNT_MASK)); - ch_x_reg->mcde_synchconf = ((ch_x_reg->mcde_synchconf & ~MCDE_HWREQVEVENT_MASK) | ((u32)ch_config.hwreq_vevent & MCDE_HWREQVEVENT_MASK)); - - return(mcde_error); -} - -mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig) -{ - mcde_error error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_synchsw = - (ch_syncreg->mcde_chnl_synchsw &~MCDE_CHNLSYNCHSW_SW_TRIG) | - (sw_trig != 0 ? MCDE_CHNLSYNCHSW_SW_TRIG : 0); - - return(error); -} - -mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color) -{ - mcde_error error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_bckgndcol = - ( - (ch_syncreg->mcde_chnl_bckgndcol &~MCDE_REDCOLOR_MASK) | - ((color.red << MCDE_REDCOLOR_SHIFT) & MCDE_REDCOLOR_MASK) - ); - - ch_syncreg->mcde_chnl_bckgndcol = - ( - (ch_syncreg->mcde_chnl_bckgndcol &~MCDE_GREENCOLOR_MASK) | - ((color.green << MCDE_GREENCOLOR_SHIFT) & MCDE_GREENCOLOR_MASK) - ); - - ch_syncreg->mcde_chnl_bckgndcol = - ( - (ch_syncreg->mcde_chnl_bckgndcol &~MCDE_BLUECOLOR_MASK) | - (color.blue & MCDE_BLUECOLOR_MASK) - ); - - - return(error); -} - -mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority) -{ - mcde_error error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_prio = - ( - (ch_syncreg->mcde_chnl_prio &~MCDE_CHPRIORITY_MASK) | - (priority & MCDE_CHPRIORITY_MASK) - ); - - return(error); -} - -mcde_error mcdesetoutdevicelpfandppl(mcde_ch_id chid, u16 channelnum, u16 lpf, u16 ppl) -{ - mcde_error error = MCDE_OK; - struct mcde_chnl_conf_reg *ch_syncreg; - - ch_syncreg = (struct mcde_chnl_conf_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chnl_conf = ((lpf & MCDE_CHNLCONF_LPF_MASK) << MCDE_CHNLCONF_LPF_SHIFT) | - ((ppl & MCDE_CHNLCONF_PPL_MASK) << MCDE_CHNLCONF_PPL_SHIFT); - - return(error); -} - -mcde_error mcdesetchnlCconf(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_chc_config config) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_RES1_MASK) | - (((u32) config.res_pol << MCDE_RES1_SHIFT) & MCDE_RES1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_RD1_MASK) | - (((u32) config.rd_pol << MCDE_RD1_SHIFT) & MCDE_RD1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_WR1_MASK) | - (((u32) config.wr_pol << MCDE_WR1_SHIFT) & MCDE_WR1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CD1_MASK) | - (((u32) config.cd_pol << MCDE_CD1_SHIFT) & MCDE_CD1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CS1_MASK) | - (((u32) config.cs_pol << MCDE_CS1_SHIFT) & MCDE_CS1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CS1EN_MASK) | - (((u32) config.csen << MCDE_CS1EN_SHIFT) & MCDE_CS1EN_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_INBAND1_MASK) | - (((u32) config.inband_mode << MCDE_INBAND1_SHIFT) & MCDE_INBAND1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_BUSSIZE1_MASK) | - (((u32) config.bus_size << MCDE_BUSSIZE1_SHIFT) & MCDE_BUSSIZE1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCEN1_MASK) | - (((u32) config.syncen << MCDE_SYNCEN1_SHIFT) & MCDE_SYNCEN1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_WMLVL1_MASK) | - (((u32) config.fifo_watermark << MCDE_WMLVL1_SHIFT) & MCDE_WMLVL1_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_C1EN_MASK) | - (((u32) config.chcen << MCDE_C1EN_SHIFT) & MCDE_C1EN_MASK) - ); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_RES2_MASK) | - (((u32) config.res_pol << MCDE_RES2_SHIFT) & MCDE_RES2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_RD2_MASK) | - (((u32) config.rd_pol << MCDE_RD2_SHIFT) & MCDE_RD2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_WR2_MASK) | - (((u32) config.wr_pol << MCDE_WR2_SHIFT) & MCDE_WR2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CD2_MASK) | - (((u32) config.cd_pol << MCDE_CD2_SHIFT) & MCDE_CD2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CS2_MASK) | - (((u32) config.cs_pol << MCDE_CS2_SHIFT) & MCDE_CS2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CS2EN_MASK) | - (((u32) config.csen << MCDE_CS2EN_SHIFT) & MCDE_CS2EN_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_INBAND2_MASK) | - (((u32) config.inband_mode << MCDE_INBAND2_SHIFT) & MCDE_INBAND2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_BUSSIZE2_MASK) | - (((u32) config.bus_size << MCDE_BUSSIZE2_SHIFT) & MCDE_BUSSIZE2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCEN2_MASK) | - (((u32) config.syncen << MCDE_SYNCEN2_SHIFT) & MCDE_SYNCEN2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_WMLVL2_MASK) | - (((u32) config.fifo_watermark << MCDE_WMLVL2_SHIFT) & MCDE_WMLVL2_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_C2EN_MASK) | - (((u32) config.chcen << MCDE_C2EN_SHIFT) & MCDE_C2EN_MASK) - ); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetchnlCctrl(mcde_ch_id chid, struct mcde_chc_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCCTRL_MASK) | - (((u32) control.sync << MCDE_SYNCCTRL_SHIFT) & MCDE_SYNCCTRL_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_RESEN_MASK) | - (((u32) control.resen << MCDE_RESEN_SHIFT) & MCDE_RESEN_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CLKSEL_MASK) | - (((u32) control.clksel << MCDE_CLKSEL_SHIFT) & MCDE_CLKSEL_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCSEL_MASK) | - (((u32) control.synsel << MCDE_SYNCSEL_SHIFT) & MCDE_SYNCSEL_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power) -{ - mcde_error error = MCDE_OK; - - if (chid <= MCDE_CH_B) - { /* Channel A or B */ - struct mcde_chAB_reg *ch_x_reg = (struct mcde_chAB_reg *) gpar[chid]->ch_regbase2[chid]; - ch_x_reg->mcde_cr0 = (ch_x_reg->mcde_cr0 & ~MCDE_CR0_POWEREN) | - (power != 0 ? MCDE_CR0_POWEREN : 0); - } else - { /* Channel C0 or C1 */ - struct mcde_chC0C1_reg *ch_c_reg = (struct mcde_chC0C1_reg *) gpar[chid]->ch_c_reg; - ch_c_reg->mcde_crc = (ch_c_reg->mcde_crc & ~MCDE_CRC_POWEREN) | - (power != 0 ? MCDE_CRC_POWEREN : 0); - } - - return(error); -} - -mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow) -{ - mcde_error error = MCDE_OK; - - if (chid <= MCDE_CH_B) - { /* Channel A or B */ - struct mcde_chAB_reg *ch_x_reg = (struct mcde_chAB_reg *) gpar[chid]->ch_regbase2[chid]; - ch_x_reg->mcde_cr0 = (ch_x_reg->mcde_cr0 & ~MCDE_CR0_FLOEN) | (flow != 0 ? MCDE_CR0_FLOEN : 0); - } else - { /* Channel C0 or C1 */ - struct mcde_chC0C1_reg *ch_c_reg = (struct mcde_chC0C1_reg *) gpar[chid]->ch_c_reg; - ch_c_reg->mcde_crc = (ch_c_reg->mcde_crc & ~MCDE_CRC_FLOEN) | (flow != 0 ? MCDE_CRC_FLOEN : 0); - } - - return(error); -} - -mcde_error mcdeconfPBCunit(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_config config) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_pbccrc[0] = - ( - (ch_c_reg->mcde_pbccrc[0] &~MCDE_PBCCRC_PDCTRL) | - (config.duplex_mode != 0 ? MCDE_PBCCRC_PDCTRL : 0) - ); - - ch_c_reg->mcde_pbccrc[0] = - ( - (ch_c_reg->mcde_pbccrc[0] &~(MCDE_PBCCRC_PDM_MASK << MCDE_PBCCRC_PDM_SHIFT)) | - ((config.duplex_mode & MCDE_PBCCRC_PDM_MASK) << MCDE_PBCCRC_PDM_SHIFT) - ); - - ch_c_reg->mcde_pbccrc[0] = - ( - (ch_c_reg->mcde_pbccrc[0] &~(MCDE_PBCCRC_BSDM_MASK << MCDE_PBCCRC_BSDM_SHIFT)) | - ((config.data_segment & MCDE_PBCCRC_BSDM_MASK) << MCDE_PBCCRC_BSDM_SHIFT) - ); - - ch_c_reg->mcde_pbccrc[0] = - ( - (ch_c_reg->mcde_pbccrc[0] &~(MCDE_PBCCRC_BSCM_MASK << MCDE_PBCCRC_BSCM_SHIFT)) | - ((config.cmd_segment & MCDE_PBCCRC_BSCM_MASK) << MCDE_PBCCRC_BSCM_SHIFT) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_pbccrc[1] = - ( - (ch_c_reg->mcde_pbccrc[1] &~MCDE_PBCCRC_PDCTRL) | - (config.duplex_mode != 0 ? MCDE_PBCCRC_PDCTRL : 0) - ); - - ch_c_reg->mcde_pbccrc[1] = - ( - (ch_c_reg->mcde_pbccrc[1] &~(MCDE_PBCCRC_PDM_MASK << MCDE_PBCCRC_PDM_SHIFT)) | - ((config.duplex_mode & MCDE_PBCCRC_PDM_MASK) << MCDE_PBCCRC_PDM_SHIFT) - ); - - ch_c_reg->mcde_pbccrc[1] = - ( - (ch_c_reg->mcde_pbccrc[1] &~(MCDE_PBCCRC_BSDM_MASK << MCDE_PBCCRC_BSDM_SHIFT)) | - ((config.data_segment & MCDE_PBCCRC_BSDM_MASK) << MCDE_PBCCRC_BSDM_SHIFT) - ); - - ch_c_reg->mcde_pbccrc[1] = - ( - (ch_c_reg->mcde_pbccrc[1] &~(MCDE_PBCCRC_BSCM_MASK << MCDE_PBCCRC_BSCM_SHIFT)) | - ((config.cmd_segment & MCDE_PBCCRC_BSCM_MASK) << MCDE_PBCCRC_BSCM_SHIFT) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetPBCmux(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_mux mux) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_pbcbmrc0[0] = mux.imux0; - - ch_c_reg->mcde_pbcbmrc0[1] = mux.imux1; - - ch_c_reg->mcde_pbcbmrc0[2] = mux.imux2; - - ch_c_reg->mcde_pbcbmrc0[3] = mux.imux3; - - ch_c_reg->mcde_pbcbmrc0[4] = mux.imux4; - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_pbcbmrc1[0] = mux.imux0; - - ch_c_reg->mcde_pbcbmrc1[1] = mux.imux1; - - ch_c_reg->mcde_pbcbmrc1[2] = mux.imux2; - - ch_c_reg->mcde_pbcbmrc1[3] = mux.imux3; - - ch_c_reg->mcde_pbcbmrc1[4] = mux.imux4; - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetchnlCvsyndelay(mcde_ch_id chid, mcde_chc_panel panel_id, u8 delay) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_sctrc = ((ch_c_reg->mcde_sctrc &~MCDE_SYNCDELC0_MASK) | (delay & MCDE_SYNCDELC0_MASK)); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_sctrc = - ( - (ch_c_reg->mcde_sctrc &~MCDE_SYNCDELC1_MASK) | - ((delay << MCDE_SYNCDELC1_SHIFT) & MCDE_SYNCDELC1_MASK) - ); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchnlCsynctrigdelay(mcde_ch_id chid, u8 delay) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_sctrc = - ( - (ch_c_reg->mcde_sctrc &~MCDE_TRDELC_MASK) | - ((delay << MCDE_TRDELC_SHIFT) & MCDE_TRDELC_MASK) - ); - - - return(error); -} -mcde_error mcdesetPBCbitctrl(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_bitctrl bit_control) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_pbcbcrc0[0] = bit_control.bit_ctrl0; - - ch_c_reg->mcde_pbcbcrc0[1] = bit_control.bit_ctrl1; - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_pbcbcrc1[0] = bit_control.bit_ctrl0; - - ch_c_reg->mcde_pbcbcrc1[1] = bit_control.bit_ctrl1; - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchnlCsynccapconf(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_sync_conf config) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSDBL_MASK) | - ((config.debounce_length << MCDE_VSDBL_SHIFT) & MCDE_VSDBL_MASK) - ); - - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSSEL_MASK) | - (((u32) config.sync_sel << MCDE_VSSEL_SHIFT) & MCDE_VSSEL_MASK) - ); - - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSPOL_MASK) | - (((u32) config.sync_pol << MCDE_VSPOL_SHIFT) & MCDE_VSPOL_MASK) - ); - - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSPDIV_MASK) | - (((u32) config.clk_div << MCDE_VSPDIV_SHIFT) & MCDE_VSPDIV_MASK) - ); - - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSPMAX_MASK) | - (((u32) config.vsp_max << MCDE_VSPMAX_SHIFT) & MCDE_VSPMAX_MASK) - ); - - ch_c_reg->mcde_vscrc[0] = - ( - (ch_c_reg->mcde_vscrc[0] &~MCDE_VSPMIN_MASK) | - ((u32) config.vsp_min & MCDE_VSPMIN_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSDBL_MASK) | - ((config.debounce_length << MCDE_VSDBL_SHIFT) & MCDE_VSDBL_MASK) - ); - - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSSEL_MASK) | - (((u32) config.sync_sel << MCDE_VSSEL_SHIFT) & MCDE_VSSEL_MASK) - ); - - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSPOL_MASK) | - (((u32) config.sync_pol << MCDE_VSPOL_SHIFT) & MCDE_VSPOL_MASK) - ); - - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSPDIV_MASK) | - (((u32) config.clk_div << MCDE_VSPDIV_SHIFT) & MCDE_VSPDIV_MASK) - ); - - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSPMAX_MASK) | - (((u32) config.vsp_max << MCDE_VSPMAX_SHIFT) & MCDE_VSPMAX_MASK) - ); - - ch_c_reg->mcde_vscrc[1] = - ( - (ch_c_reg->mcde_vscrc[1] &~MCDE_VSPMIN_MASK) | - ((u32) config.vsp_min & MCDE_VSPMIN_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdechnlCclkandsyncsel(mcde_ch_id chid, mcde_clk_sel clk_sel, mcde_synchro_select sync_select) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_CLKSEL_MASK) | - (((u32) clk_sel << MCDE_CLKSEL_SHIFT) & MCDE_CLKSEL_MASK) - ); - - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCSEL_MASK) | - (((u32) sync_select << MCDE_SYNCSEL_SHIFT) & MCDE_SYNCSEL_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlCmode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_chc_enable state) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_C1EN_MASK) | - ((state << MCDE_C1EN_SHIFT) & MCDE_C1EN_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_C2EN_MASK) | - ((state << MCDE_C2EN_SHIFT) & MCDE_C2EN_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - - return(error); -} - -mcde_error mcdesetsynchromode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_synchro_capture sync_enable) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCEN1_MASK) | - (((u32) sync_enable << MCDE_SYNCEN1_SHIFT) & MCDE_SYNCEN1_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_crc = - ( - (ch_c_reg->mcde_crc &~MCDE_SYNCEN2_MASK) | - (((u32) sync_enable << MCDE_SYNCEN2_SHIFT) & MCDE_SYNCEN2_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchipseltiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_cd_timing_activate active) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_cscdtr[0] = - ( - (ch_c_reg->mcde_cscdtr[0] &~MCDE_CSCDDEACT_MASK) | - ((active.cs_cd_deactivate << MCDE_CSCDDEACT_SHIFT) & MCDE_CSCDDEACT_MASK) - ); - - ch_c_reg->mcde_cscdtr[0] = - ( - (ch_c_reg->mcde_cscdtr[0] &~MCDE_CSCDACT_MASK) | - (active.cs_cd_activate & MCDE_CSCDACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_cscdtr[1] = - ( - (ch_c_reg->mcde_cscdtr[1] &~MCDE_CSCDDEACT_MASK) | - ((active.cs_cd_deactivate << MCDE_CSCDDEACT_SHIFT) & MCDE_CSCDDEACT_MASK) - ); - - ch_c_reg->mcde_cscdtr[1] = - ( - (ch_c_reg->mcde_cscdtr[1] &~MCDE_CSCDACT_MASK) | - (active.cs_cd_activate & MCDE_CSCDACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetbusaccessnum(mcde_ch_id chid, mcde_chc_panel panel_id, u8 bcn) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_bcnr[0] = ((ch_c_reg->mcde_bcnr[0] &~MCDE_BCN_MASK) | (bcn & MCDE_BCN_MASK)); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_bcnr[1] = ((ch_c_reg->mcde_bcnr[1] &~MCDE_BCN_MASK) | (bcn & MCDE_BCN_MASK)); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetrdwrtiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_rw_timing rw_time) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_rdwrtr[0] = - ( - (ch_c_reg->mcde_rdwrtr[0] &~MCDE_MOTINT_MASK) | - (((u32) rw_time.panel_type << MCDE_MOTINT_SHIFT) & MCDE_MOTINT_MASK) - ); - - ch_c_reg->mcde_rdwrtr[0] = - ( - (ch_c_reg->mcde_rdwrtr[0] &~MCDE_RWDEACT_MASK) | - ((rw_time.readwrite_deactivate << MCDE_RWDEACT_SHIFT) & MCDE_RWDEACT_MASK) - ); - - ch_c_reg->mcde_rdwrtr[0] = - ( - (ch_c_reg->mcde_rdwrtr[0] &~MCDE_RWACT_MASK) | - (rw_time.readwrite_activate & MCDE_RWACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_rdwrtr[1] = - ( - (ch_c_reg->mcde_rdwrtr[1] &~MCDE_MOTINT_MASK) | - (((u32) rw_time.panel_type << MCDE_MOTINT_SHIFT) & MCDE_MOTINT_MASK) - ); - - ch_c_reg->mcde_rdwrtr[1] = - ( - (ch_c_reg->mcde_rdwrtr[1] &~MCDE_RWDEACT_MASK) | - ((rw_time.readwrite_deactivate << MCDE_RWDEACT_SHIFT) & MCDE_RWDEACT_MASK) - ); - - ch_c_reg->mcde_rdwrtr[1] = - ( - (ch_c_reg->mcde_rdwrtr[1] &~MCDE_RWACT_MASK) | - (rw_time.readwrite_activate & MCDE_RWACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetdataouttiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_data_out_timing data_time) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_dotr[0] = - ( - (ch_c_reg->mcde_dotr[0] &~MCDE_DODEACT_MASK) | - ((data_time.data_out_deactivate << MCDE_DODEACT_SHIFT) & MCDE_DODEACT_MASK) - ); - - ch_c_reg->mcde_dotr[0] = - ( - (ch_c_reg->mcde_dotr[0] &~MCDE_DOACT_MASK) | - (data_time.data_out_activate & MCDE_DOACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_dotr[1] = - ( - (ch_c_reg->mcde_dotr[1] &~MCDE_DODEACT_MASK) | - ((data_time.data_out_deactivate << MCDE_DODEACT_SHIFT) & MCDE_DODEACT_MASK) - ); - - ch_c_reg->mcde_dotr[1] = - ( - (ch_c_reg->mcde_dotr[1] &~MCDE_DOACT_MASK) | - (data_time.data_out_activate & MCDE_DOACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdewrcmd(mcde_ch_id chid, mcde_chc_panel panel_id, u32 command) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_wcmdc[0] = (command & MCDE_DATACOMMANDMASK); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_wcmdc[1] = (command & MCDE_DATACOMMANDMASK); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdewrdata(mcde_ch_id chid, mcde_chc_panel panel_id, u32 data) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_wdatadc[0] = (data & MCDE_DATACOMMANDMASK); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_wdatadc[1] = (data & MCDE_DATACOMMANDMASK); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdewrtxfifo(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_txfifo_request_type type, u32 data) -{ - mcde_error error = MCDE_OK; - struct mcde_chC0C1_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chC0C1_reg *) (gpar[chid]->ch_c_reg); - switch (type) - { - case MCDE_TXFIFO_WRITE_DATA: - ch_c_reg->mcde_wdatadc[panel_id] = (data & MCDE_DATACOMMANDMASK); - - break; - - case MCDE_TXFIFO_WRITE_COMMAND: - ch_c_reg->mcde_wcmdc[panel_id] = (data & MCDE_DATACOMMANDMASK); - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - - return(error); -} - -mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_cr0 = - (ch_x_reg->mcde_cr0 &~(MCDE_CR0_KEYCTRL_MASK << MCDE_CR0_KEYCTRL_SHIFT)) | - ((key_ctrl & MCDE_CR0_KEYCTRL_MASK) << MCDE_CR0_KEYCTRL_SHIFT); - - return(error); -} - -mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - /* TODO: Fix me! Strange that alpha_blend and blend trigger the same bit */ - ch_x_reg->mcde_cr0 = - (ch_x_reg->mcde_cr0 &~MCDE_CR0_BLENDEN) | - (blend_ctrl.alpha_blend != 0 ? MCDE_CR0_BLENDEN : 0); - - ch_x_reg->mcde_cr0 = - (ch_x_reg->mcde_cr0 &~MCDE_CR0_BLENDCTRL) | - (blend_ctrl.blend_ctrl != 0 ? MCDE_CR0_BLENDCTRL : 0); - - ch_x_reg->mcde_cr0 = - (ch_x_reg->mcde_cr0 &~MCDE_CR0_BLENDEN) | - (blend_ctrl.blenden != 0 ? MCDE_CR0_BLENDEN : 0); - - return(error); -} - -mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - if (rot_ctrl == MCDE_ROTATION_ENABLE) - { - ch_x_reg->mcde_rot_conf = - (ch_x_reg->mcde_rot_conf &~MCDE_ROTCONF_ROTDIR) | - (rot_dir != 0 ? MCDE_ROTCONF_ROTDIR : 0);//(((u32) rot_dir << MCDE_CHX_ROTDIR_SHIFT) & MCDE_CHX_ROTDIR_MASK) - } - ch_x_reg->mcde_cr0 = - (ch_x_reg->mcde_cr0 &~MCDE_CR0_ROTEN) | - (rot_ctrl != 0 ? MCDE_CR0_ROTEN : 0);//(((u32) rot_ctrl << MCDE_ROTEN_SHIFT) & MCDE_ROTEN_MASK) - - return error; -} -mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_cr0 = - ( - (ch_x_reg->mcde_cr0 &~MCDE_CR0_DITHEN) | - (dithering_control != 0 ? MCDE_CR0_DITHEN : 0)//(((u32) dithering_control << MCDE_DITHEN_SHIFT) & MCDE_DITHEN_MASK) - ); - return (error); -} -mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_cr0 &= ~((MCDE_CR0_ROTBURSTSIZE_MASK << MCDE_CR0_ROTBURSTSIZE_SHIFT) | - (MCDE_CR0_ALPHABLEND_MASK << MCDE_CR0_ALPHABLEND_SHIFT) | - (MCDE_CR0_GAMEN) | (MCDE_CR0_FLICKFORMAT) | (MCDE_CR0_FLICKMODE_MASK << MCDE_CR0_FLICKMODE_SHIFT) | - (MCDE_CR0_BLENDCTRL) | (MCDE_CR0_KEYCTRL_MASK << MCDE_CR0_KEYCTRL_SHIFT) | - (MCDE_CR0_ROTEN) | (MCDE_CR0_DITHEN) | (MCDE_CR0_AFLICKEN) | (MCDE_CR0_BLENDEN)); - - ch_x_reg->mcde_cr0 |= (control.chx_read_request & MCDE_CR0_ROTBURSTSIZE_MASK) << MCDE_CR0_ROTBURSTSIZE_SHIFT; - /*(ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_BURSTSIZE_MASK) | - ((u32) control.chx_read_request << MCDE_CHX_BURSTSIZE_SHIFT) & MCDE_CHX_BURSTSIZE_MASK);*/ - - ch_x_reg->mcde_cr0 |= (control.alpha_blend & MCDE_CR0_ALPHABLEND_MASK) << MCDE_CR0_ALPHABLEND_SHIFT; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_ALPHA_MASK) | - (((u32) control.alpha_blend << MCDE_CHX_ALPHA_SHIFT) & MCDE_CHX_ALPHA_MASK) - );*/ - - - ch_x_reg->mcde_rot_conf = (ch_x_reg->mcde_rot_conf & ~MCDE_ROTCONF_ROTDIR) | - (control.rot_dir != 0 ? MCDE_ROTCONF_ROTDIR : 0); - - ch_x_reg->mcde_cr0 |= control.gamma_ctrl ? MCDE_CR0_GAMEN : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_GAMAEN_MASK) | - (((u32) control.gamma_ctrl << MCDE_CHX_GAMAEN_SHIFT) & MCDE_CHX_GAMAEN_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.flicker_format ? MCDE_CR0_FLICKFORMAT : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_FLICKFORMAT_MASK) | - (((u32) control.flicker_format << MCDE_FLICKFORMAT_SHIFT) & MCDE_FLICKFORMAT_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= (control.filter_mode & MCDE_CR0_FLICKMODE_MASK) << MCDE_CR0_FLICKMODE_SHIFT; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_FLICKMODE_MASK) | - (((u32) control.filter_mode << MCDE_FLICKMODE_SHIFT) & MCDE_FLICKMODE_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.blend ? MCDE_CR0_BLENDCTRL : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDCONTROL_MASK) | - (((u32) control.blend << MCDE_BLENDCONTROL_SHIFT) & MCDE_BLENDCONTROL_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= (control.key_ctrl & MCDE_CR0_KEYCTRL_MASK) << MCDE_CR0_KEYCTRL_SHIFT; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_KEYCTRL_MASK) | - (((u32) control.key_ctrl << MCDE_KEYCTRL_SHIFT) & MCDE_KEYCTRL_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.rot_enable != 0 ? MCDE_CR0_ROTEN : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_ROTEN_MASK) | - (((u32) control.rot_enable << MCDE_ROTEN_SHIFT) & MCDE_ROTEN_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.dither_ctrl != 0 ? MCDE_CR0_DITHEN : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_DITHEN_MASK) | - (((u32) control.dither_ctrl << MCDE_DITHEN_SHIFT) & MCDE_DITHEN_MASK) - );*/ - - // TODO: Not implemented yet CEAEN Color Enhancement Algorithm enable - /*ch_x_reg->mcde_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CEAEN_MASK) | - (((u32) control.color_enhance << MCDE_CEAEN_SHIFT) & MCDE_CEAEN_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.anti_flicker != 0 ? MCDE_CR0_AFLICKEN : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_AFLICKEN_MASK) | - (((u32) control.anti_flicker << MCDE_AFLICKEN_SHIFT) & MCDE_AFLICKEN_MASK) - );*/ - - ch_x_reg->mcde_cr0 |= control.blend_ctrl != 0 ? MCDE_CR0_BLENDEN : 0; - /*( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDEN_MASK) | - (((u32) control.blend_ctrl << MCDE_BLENDEN_SHIFT) & MCDE_BLENDEN_MASK) - );*/ - - - return(error); -} - -mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_cr1 = - ( - (ch_x_reg->mcde_cr1 &~MCDE_CLK_MASK) | - (((u32) control.tv_clk << MCDE_CLK_SHIFT) & MCDE_CLK_MASK) - ); - - ch_x_reg->mcde_cr1 = - ( - (ch_x_reg->mcde_cr1 &~MCDE_BCD_MASK) | - (((u32) control.bcd_ctrl << MCDE_BCD_SHIFT) & MCDE_BCD_MASK) - ); - - ch_x_reg->mcde_cr1 = - ( - (ch_x_reg->mcde_cr1 &~MCDE_OUTBPP_MASK) | - (((u32) control.out_bpp << MCDE_OUTBPP_SHIFT) & MCDE_OUTBPP_MASK) - ); -/* Only applicable to older version of chip - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_CLP_MASK) | - (((u32) control.clk_per_line << MCDE_CLP_SHIFT) & MCDE_CLP_MASK) - ); -*/ - - ch_x_reg->mcde_cr1 = - ( - (ch_x_reg->mcde_cr1 &~MCDE_CDWIN_MASK) | - (((u32) control.lcd_bus << MCDE_CDWIN_SHIFT) & MCDE_CDWIN_MASK) - ); - - ch_x_reg->mcde_cr1 = - ( - (ch_x_reg->mcde_cr1 &~MCDE_CLOCKSEL_MASK) | - (((u32) control.dpi2_clk << MCDE_CLOCKSEL_SHIFT) & MCDE_CLOCKSEL_MASK) - ); - - ch_x_reg->mcde_cr1 = ((ch_x_reg->mcde_cr1 &~MCDE_PCD_MASK) | ((u32) control.pcd & MCDE_PCD_MASK)); - - return(error); -} - -mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - if (type == MCDE_COLORKEY_NORMAL) - { - ch_x_reg->mcde_colkey = - ( - (ch_x_reg->mcde_colkey &~MCDE_KEYA_MASK) | - ((key.alpha << MCDE_KEYA_SHIFT) & MCDE_KEYA_MASK) - ); - - ch_x_reg->mcde_colkey = - ( - (ch_x_reg->mcde_colkey &~MCDE_KEYR_MASK) | - ((key.red << MCDE_KEYR_SHIFT) & MCDE_KEYR_MASK) - ); - - ch_x_reg->mcde_colkey = - ( - (ch_x_reg->mcde_colkey &~MCDE_KEYG_MASK) | - ((key.green << MCDE_KEYG_SHIFT) & MCDE_KEYG_MASK) - ); - - ch_x_reg->mcde_colkey = ((ch_x_reg->mcde_colkey &~MCDE_KEYB_MASK) | (key.blue & MCDE_KEYB_MASK)); - } - else - if (type == MCDE_COLORKEY_FORCE) - { - ch_x_reg->mcde_fcolkey = - ( - (ch_x_reg->mcde_fcolkey &~MCDE_KEYA_MASK) | - ((key.alpha << MCDE_KEYA_SHIFT) & MCDE_KEYA_MASK) - ); - - ch_x_reg->mcde_fcolkey = - ( - (ch_x_reg->mcde_fcolkey &~MCDE_KEYR_MASK) | - ((key.red << MCDE_KEYR_SHIFT) & MCDE_KEYR_MASK) - ); - - ch_x_reg->mcde_fcolkey = - ( - (ch_x_reg->mcde_fcolkey &~MCDE_KEYG_MASK) | - ((key.green << MCDE_KEYG_SHIFT) & MCDE_KEYG_MASK) - ); - - ch_x_reg->mcde_fcolkey = ((ch_x_reg->mcde_fcolkey &~MCDE_KEYB_MASK) | (key.blue & MCDE_KEYB_MASK)); - } - - - return(error); -} -mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_rgbconv1 = ((coef.Yr_red & MCDE_RGBCONV1_YR_RED_MASK) << MCDE_RGBCONV1_YR_RED_SHIFT) | - ((coef.Yr_green & MCDE_RGBCONV1_YR_GREEN_MASK) << MCDE_RGBCONV1_YR_GREEN_SHIFT); - - ch_x_reg->mcde_rgbconv2 = ((coef.Yr_blue & MCDE_RGBCONV2_YR_BLUE_MASK) << MCDE_RGBCONV2_YR_BLUE_SHIFT) | - ((coef.Cr_red & MCDE_RGBCONV2_CR_RED_MASK) << MCDE_RGBCONV2_CR_RED_SHIFT); - - ch_x_reg->mcde_rgbconv3 = ((coef.Cr_green & MCDE_RGBCONV3_CR_GREEN_MASK) << MCDE_RGBCONV3_CR_GREEN_SHIFT) | - ((coef.Cr_blue & MCDE_RGBCONV3_CR_BLUE_MASK) << MCDE_RGBCONV3_CR_BLUE_SHIFT); - - ch_x_reg->mcde_rgbconv4 = ((coef.Cb_red & MCDE_RGBCONV4_CB_RED_MASK) << MCDE_RGBCONV4_CB_RED_SHIFT) | - ((coef.Cb_green & MCDE_RGBCONV4_CB_GREEN_MASK) << MCDE_RGBCONV4_CB_GREEN_SHIFT); - - ch_x_reg->mcde_rgbconv5 = ((coef.Cb_blue & MCDE_RGBCONV5_CB_BLUE_MASK) << MCDE_RGBCONV5_CB_BLUE_SHIFT) | - ((coef.Off_red & MCDE_RGBCONV5_OFF_RED_MASK) << MCDE_RGBCONV5_OFF_RED_SHIFT); - - ch_x_reg->mcde_rgbconv6 = ((coef.Off_green & MCDE_RGBCONV6_OFF_GREEN_MASK) << MCDE_RGBCONV6_OFF_GREEN_SHIFT) | - ((coef.Off_blue & MCDE_RGBCONV6_OFF_BLUE_MASK) << MCDE_RGBCONV6_OFF_BLUE_SHIFT); - - return(error); -} -mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ffcoef0 = - ( - (ch_x_reg->mcde_ffcoef0 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl0 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ffcoef0 = - ( - (ch_x_reg->mcde_ffcoef0 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff0_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ffcoef0 = - ( - (ch_x_reg->mcde_ffcoef0 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff0_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ffcoef0 = - ( - (ch_x_reg->mcde_ffcoef0 &~MCDE_COEFFN1_MASK) | - (coef.Coeff0_N1 & MCDE_COEFFN1_MASK) - ); - - ch_x_reg->mcde_ffcoef1 = - ( - (ch_x_reg->mcde_ffcoef1 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl1 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ffcoef1 = - ( - (ch_x_reg->mcde_ffcoef1 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff1_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ffcoef1 = - ( - (ch_x_reg->mcde_ffcoef1 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff1_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ffcoef1 = - ( - (ch_x_reg->mcde_ffcoef1 &~MCDE_COEFFN1_MASK) | - (coef.Coeff1_N1 & MCDE_COEFFN1_MASK) - ); - - ch_x_reg->mcde_ffcoef2 = - ( - (ch_x_reg->mcde_ffcoef2 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl2 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ffcoef2 = - ( - (ch_x_reg->mcde_ffcoef2 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff2_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ffcoef2 = - ( - (ch_x_reg->mcde_ffcoef2 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff2_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ffcoef2 = - ( - (ch_x_reg->mcde_ffcoef2 &~MCDE_COEFFN1_MASK) | - (coef.Coeff2_N1 & MCDE_COEFFN1_MASK) - ); - - return(error); -} - -mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_REVVAEN_MASK) | - (((u32) control.rev_va_enable << MCDE_REVVAEN_SHIFT) & MCDE_REVVAEN_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_REVTGEN_MASK) | - (((u32) control.rev_toggle_enable << MCDE_REVTGEN_SHIFT) & MCDE_REVTGEN_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_REVLOADSEL_MASK) | - (((u32) control.rev_sync_sel << MCDE_REVLOADSEL_SHIFT) & MCDE_REVLOADSEL_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_REVDEL1_MASK) | - (((u32) control.rev_delay1 << MCDE_REVDEL1_SHIFT) & MCDE_REVDEL1_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_REVDEL0_MASK) | - (((u32) control.rev_delay0 << MCDE_REVDEL0_SHIFT) & MCDE_REVDEL0_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_PSVAEN_MASK) | - (((u32) control.ps_va_enable << MCDE_PSVAEN_SHIFT) & MCDE_PSVAEN_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_PSTGEN_MASK) | - (((u32) control.ps_toggle_enable << MCDE_PSTGEN_SHIFT) & MCDE_PSTGEN_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_PSLOADSEL_MASK) | - (((u32) control.ps_sync_sel << MCDE_PSLOADSEL_SHIFT) & MCDE_PSLOADSEL_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_PSDEL1_MASK) | - (((u32) control.ps_delay1 << MCDE_PSDEL1_SHIFT) & MCDE_PSDEL1_MASK) - ); - - ch_x_reg->mcde_lcdtim0 = - ( - (ch_x_reg->mcde_lcdtim0 &~MCDE_PSDEL0_MASK) | - ((u32) control.ps_delay0 & MCDE_PSDEL0_MASK) - ); - - return(error); -} - -mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing1 control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_IOE_MASK) | - (((u32) control.io_enable << MCDE_IOE_SHIFT) & MCDE_IOE_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_IPC_MASK) | - (((u32) control.ipc << MCDE_IPC_SHIFT) & MCDE_IPC_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_IHS_MASK) | - (((u32) control.ihs << MCDE_IHS_SHIFT) & MCDE_IHS_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_IVS_MASK) | - (((u32) control.ivs << MCDE_IVS_SHIFT) & MCDE_IVS_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_IVP_MASK) | - (((u32) control.ivp << MCDE_IVP_SHIFT) & MCDE_IPC_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_ICLSPL_MASK) | - (((u32) control.iclspl << MCDE_ICLSPL_SHIFT) & MCDE_ICLSPL_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_ICLREV_MASK) | - (((u32) control.iclrev << MCDE_ICLREV_SHIFT) & MCDE_ICLREV_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_ICLSP_MASK) | - (((u32) control.iclsp << MCDE_ICLSP_SHIFT) & MCDE_ICLSP_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_SPLVAEN_MASK) | - (((u32) control.mcde_spl << MCDE_SPLVAEN_SHIFT) & MCDE_SPLVAEN_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_SPLTGEN_MASK) | - (((u32) control.spltgen << MCDE_SPLTGEN_SHIFT) & MCDE_SPLTGEN_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_SPLLOADSEL_MASK) | - (((u32) control.spl_sync_sel << MCDE_SPLLOADSEL_SHIFT) & MCDE_SPLLOADSEL_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_SPLDEL1_MASK) | - (((u32) control.spl_delay1 << MCDE_SPLDEL1_SHIFT) & MCDE_SPLDEL1_MASK) - ); - - ch_x_reg->mcde_lcdtim1 = - ( - (ch_x_reg->mcde_lcdtim1 &~MCDE_SPLDEL0_MASK) | - ((u32) control.spl_delay0 & MCDE_SPLDEL0_MASK) - ); - - return(error); -} -mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - if (0x0 == address) - { - return(MCDE_INVALID_PARAMETER); - } - if(rotnum == MCDE_ROTATE0) - ch_x_reg->mcde_rotadd0 = address; - else if(rotnum == MCDE_ROTATE1) - ch_x_reg->mcde_rotadd1 = address; - - return(error); -} - -/****************************************************************************/ -mcde_state mcdegetchannelstate(mcde_ch_id chid) -{ - mcde_state retval = MCDE_DISABLE; - - switch(chid) { - case MCDE_CH_A: - case MCDE_CH_B: - if ((gpar[chid]->ch_regbase2[chid]->mcde_cr0 & (MCDE_CR0_POWEREN | MCDE_CR0_FLOEN)) == - (MCDE_CR0_POWEREN | MCDE_CR0_FLOEN)) { - retval = MCDE_ENABLE; - } - else { - retval = MCDE_DISABLE; - } - break; - - case MCDE_CH_C0: - case MCDE_CH_C1: - if ((gpar[chid]->ch_c_reg->mcde_crc & (MCDE_CRC_POWEREN | MCDE_CRC_FLOEN)) == - (MCDE_CRC_POWEREN | MCDE_CRC_FLOEN)) { - retval = MCDE_ENABLE; - } - else { - retval = MCDE_DISABLE; - } - break; - } - - return retval; -} - -mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state) -{ - mcde_error error = MCDE_OK; - -#ifdef PLATFORM_8500 - if (state == 0) { - switch(chid) { - case MCDE_CH_A: - break; - case MCDE_CH_B: - gpar[chid]->regbase->mcde_imscpp &= ~MCDE_IMSCPP_VCMPBIM; - break; - case MCDE_CH_C0: - gpar[chid]->regbase->mcde_imscpp &= ~MCDE_IMSCPP_VCMPC0IM; - while(gpar[chid]->dsi_lnk_registers[DSI_LINK0]->cmd_mode_sts & 0x20); - break; - case MCDE_CH_C1: - gpar[chid]->regbase->mcde_imscpp &= ~MCDE_IMSCPP_VCMPC1IM; - while(gpar[chid]->dsi_lnk_registers[DSI_LINK1]->cmd_mode_sts & 0x20); - break; - default: - break; - } - - } - else { - switch(chid) { - case MCDE_CH_A: - break; - - case MCDE_CH_B: - /* Int */ - gpar[chid]->regbase->mcde_imscpp |= MCDE_IMSCPP_VCMPBIM; - break; - - case MCDE_CH_C0: - gpar[chid]->dsi_lnk_registers[DSI_LINK0]->cmd_mode_sts_clr = 0x20; - - /* SW synch */ - gpar[chid]->ch_regbase1[MCDE_CH_C0]->mcde_chnl_synchsw = MCDE_CHNLSYNCHSW_SW_TRIG; - - /* Int */ - gpar[chid]->regbase->mcde_imscpp |= MCDE_IMSCPP_VCMPC0IM; - break; - - case MCDE_CH_C1: - gpar[chid]->dsi_lnk_registers[DSI_LINK1]->cmd_mode_sts_clr = 0x20; - - gpar[chid]->regbase->mcde_imscpp |= MCDE_IMSCPP_VCMPC1IM; - /* SW synch */ - gpar[chid]->ch_regbase1[chid]->mcde_chnl_synchsw = MCDE_CHNLSYNCHSW_SW_TRIG; - - /* Int */ - gpar[chid]->regbase->mcde_imscpp |= MCDE_IMSCPP_VCMPC0IM; - break; - - default: - break; - } - } - -#endif -#ifdef PLATFORM_8820 - - gpar[chid]->regbase->mcde_cr |= state; -#endif - - return(error); -} - -mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_pal1 = (palette.alphared & MCDE_PAL1_RED_MASK) << MCDE_PAL1_RED_SHIFT; - ch_x_reg->mcde_pal0 = ((palette.green & MCDE_PAL0_GREEN_MASK) << MCDE_PAL0_GREEN_SHIFT) | - ((palette.blue & MCDE_PAL0_BLUE_MASK) << MCDE_PAL0_BLUE_SHIFT); - - return(error); -} - - -mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_FOFFY_MASK) | - ((control.y_offset << MCDE_FOFFY_SHIFT) & MCDE_FOFFY_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_FOFFX_MASK) | - ((control.x_offset << MCDE_FOFFX_SHIFT) & MCDE_FOFFX_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_MASK_BITCTRL_MASK) | - (((u32) control.masking_ctrl << MCDE_MASK_BITCTRL_SHIFT) & MCDE_MASK_BITCTRL_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_MODE_MASK) | - ((control.mode << MCDE_MODE_SHIFT) & MCDE_MODE_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_COMP_MASK) | - (((u32) control.comp_dithering << MCDE_COMP_SHIFT) & MCDE_COMP_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_TEMP_MASK) | - ((u32) control.temp_dithering & MCDE_TEMP_MASK) - ); - return(error); -} - -mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_YB_MASK) | - ((offset.y_offset_rb << MCDE_YB_SHIFT) & MCDE_YB_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_XB_MASK) | - ((offset.x_offset_rb << MCDE_XB_SHIFT) & MCDE_XB_MASK) - ); - - ch_x_reg->mcde_ditctrl = - ( - (ch_x_reg->mcde_ditctrl &~MCDE_YG_MASK) | - ((offset.y_offset_rg << MCDE_YG_SHIFT) & MCDE_YG_MASK) - ); - - ch_x_reg->mcde_ditctrl = ((ch_x_reg->mcde_ditctrl &~MCDE_XG_MASK) | (offset.x_offset_rg & MCDE_XG_MASK)); - - return(error); -} - -mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_gam2 = gamma.red; //(ch_x_reg->mcde_ch_gam &~MCDE_RED_MASK) | - //((gamma.red << MCDE_ARED_SHIFT) & MCDE_RED_MASK); - ch_x_reg->mcde_gam1 = gamma.green; //(ch_x_reg->mcde_ch_gam &~MCDE_GREEN_MASK) | - //((gamma.green << MCDE_GREEN_SHIFT) & MCDE_GREEN_MASK); - ch_x_reg->mcde_gam0 = gamma.blue; //(ch_x_reg->mcde_ch_gam &~MCDE_BLUE_MASK) | (gamma.blue & MCDE_BLUE_MASK); - - return(error); -} -mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_INTEREN_MASK) |(((u32) scan_mode << MCDE_INTEREN_SHIFT) & MCDE_INTEREN_MASK)); - - return error; -} -mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_TV_LINES_MASK) |((lcd_ctrl_reg.num_lines << MCDE_TV_LINES_SHIFT) & MCDE_TV_LINES_MASK)); - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_TVMODE_MASK) |(((u32) lcd_ctrl_reg.tv_mode << MCDE_TVMODE_SHIFT) & MCDE_TVMODE_MASK)); - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_IFIELD_MASK) |(((u32) lcd_ctrl_reg.ifield << MCDE_IFIELD_SHIFT) & MCDE_IFIELD_MASK)); - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_INTEREN_MASK) |(((u32) 0x0 << MCDE_INTEREN_SHIFT) & MCDE_INTEREN_MASK)); - ch_x_reg->mcde_tvcr = ((ch_x_reg->mcde_tvcr &~MCDE_SELMODE_MASK) |((u32) lcd_ctrl_reg.sel_mode & MCDE_SELMODE_MASK)); - ch_x_reg->mcde_tvtim1 = ((ch_x_reg->mcde_tvtim1 & ~MCDE_SWW_MASK) | ((lcd_ctrl_reg.ppl << MCDE_SWW_SHIFT) & MCDE_SWW_MASK)); - - return(error); -} -mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_tvtim1 = ((ch_x_reg->mcde_tvtim1 & ~MCDE_DHO_MASK) | (lcd_horizontal_timing.hbp & MCDE_DHO_MASK)); - ch_x_reg->mcde_tvlbalw = ((ch_x_reg->mcde_tvlbalw & ~MCDE_ALW_MASK) | ((lcd_horizontal_timing.hfp << MCDE_ALW_SHIFT) & MCDE_ALW_MASK)); - ch_x_reg->mcde_tvlbalw = ((ch_x_reg->mcde_tvlbalw & ~MCDE_LBW_MASK) | (lcd_horizontal_timing.hsw & MCDE_LBW_MASK)); - - return(error); -} -mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing) -{ - mcde_error error = MCDE_OK; - struct mcde_chAB_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_chAB_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_tvbl1 = ((ch_x_reg->mcde_tvbl1 & ~MCDE_BSL_MASK) | ((lcd_vertical_timing.vfp << MCDE_BSL_SHIFT) & MCDE_BSL_MASK)); - ch_x_reg->mcde_tvbl1 = ((ch_x_reg->mcde_tvbl1 & ~MCDE_BEL_MASK) | (lcd_vertical_timing.vsw & MCDE_BEL_MASK)); - ch_x_reg->mcde_tvdvo = ((ch_x_reg->mcde_tvdvo & ~MCDE_DVO1_MASK) | (lcd_vertical_timing.vbp & MCDE_DVO1_MASK)); - - return(error); -} -#ifdef PLATFORM_8820 - -mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp) -{ - mcde_error error = MCDE_OK; - - switch (chid) - { - case CHANNEL_A: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_A_MSB << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - } - break; - case CHANNEL_B: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX3_MASK) | (((u32)MCDE_CH_B_MSB << MCDE_CFG_OUTMUX3_SHIFT)& MCDE_CFG_OUTMUX3_MASK)); - } - break; - default: - ; - } - return(error); -} -#else -mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp) -{ - mcde_error error = MCDE_OK; - - switch (chid) - { - case CHANNEL_A: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_A_MSB << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - } - break; - case CHANNEL_B: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - gpar[chid]->regbase->mcde_conf0 = ((gpar[chid]->regbase->mcde_conf0 & ~MCDE_CFG_OUTMUX3_MASK) | (((u32)MCDE_CH_B_MSB << MCDE_CFG_OUTMUX3_SHIFT)& MCDE_CFG_OUTMUX3_MASK)); - } - break; - case CHANNEL_C0: - gpar[chid]->regbase->mcde_conf0 |= 0x5000;//0x5e145000; /** This code needs to be modified */ - break; - case CHANNEL_C1: - gpar[chid]->regbase->mcde_conf0 |= 0x5e145000; /** This code needs to be modified */ - break; - default: - ; - } - return(error); -} -#endif -mcde_error mcderesetextsrcovrlay(mcde_ch_id chid) -{ - struct mcde_ext_src_reg *ext_src; - struct mcde_ovl_reg *ovr_config; - mcde_error retVal = MCDE_OK; - - /** point to the correct ext src register */ - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[gpar[chid]->mcde_cur_ovl_bmp]); - - /** reset ext src address registers, src conf register and src ctrl register to default value */ - ext_src->mcde_extsrc_a0 = 0x0; - ext_src->mcde_extsrc_a1 = 0x0; - ext_src->mcde_extsrc_a2 = 0x0; - ext_src->mcde_extsrc_conf = 0xA04; - ext_src->mcde_extsrc_cr = 0x0; - - /** point to the correct overlay register */ - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[gpar[chid]->mcde_cur_ovl_bmp]); - - /** reset overlay conf and overlay control register to default values...this also disables overlay */ - ovr_config->mcde_ovl_conf = 0x0; - ovr_config->mcde_ovl_conf2 = 0x00200001; - ovr_config->mcde_ovl_ljinc = 0x0; - ovr_config->mcde_ovl_cr = 0x22B00000; - - return retVal; -} - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ -/* HW ED */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -/** Linux include files:charachter driver and memory functions */ - - -#include <linux/module.h> -#include <linux/kernel.h> -#include <mach/mcde_common.h> - -extern struct mcdefb_info *gpar[]; - -#define PLATFORM_8500 1 - -mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config) -{ - mcde_error error = MCDE_OK; - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLLOUT_DIVSEL1_MASK) | - (((u32) clk_config.pllout_divsel1 << MCDE_PLLOUT_DIVSEL1_SHIFT) & MCDE_PLLOUT_DIVSEL1_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLLOUT_DIVSEL0_MASK) | - (((u32) clk_config.pllout_divsel0 << MCDE_PLLOUT_DIVSEL0_SHIFT) & MCDE_PLLOUT_DIVSEL0_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_PLL4IN_SEL_MASK) | - (((u32) clk_config.pll4in_sel << MCDE_PLL4IN_SEL_SHIFT) & MCDE_PLL4IN_SEL_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_TXESCDIV_SEL_MASK) | - (((u32) clk_config.pll4in_sel << MCDE_TXESCDIV_SEL_SHIFT) & MCDE_TXESCDIV_SEL_MASK) - ); - - *gpar[chid]->mcde_clkdsi = - ( - (*gpar[chid]->mcde_clkdsi &~MCDE_TXESCDIV_MASK) | - ((u32) clk_config.pll4in_sel & MCDE_TXESCDIV_MASK) - ); - - return(error); -} - - -mcde_error mcdesetdsicommandword -( - dsi_link link, - mcde_ch_id chid, - mcde_dsi_channel dsichannel, - u8 cmdbyte_lsb, - u8 cmdbyte_msb -) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - dsi_reg->mcde_dsi_cmd = - ( - (dsi_reg->mcde_dsi_cmd &~MCDE_CMDBYTE_LSB_MASK) | - ((u32) cmdbyte_lsb & MCDE_CMDBYTE_LSB_MASK) - ); - - dsi_reg->mcde_dsi_cmd = - ( - (dsi_reg->mcde_dsi_cmd &~MCDE_CMDBYTE_MSB_MASK) | - (((u32) cmdbyte_msb << MCDE_CMDBYTE_MSB_SHIFT) & MCDE_CMDBYTE_MSB_MASK) - ); - - return(error); -} - -mcde_error mcdesetdsisyncpulse(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, u16 sync_dma, u16 sync_sw) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - dsi_reg->mcde_dsi_sync = ((dsi_reg->mcde_dsi_sync &~MCDE_DSI_DMA_MASK) | ((u32) sync_dma & MCDE_DSI_DMA_MASK)); - - dsi_reg->mcde_dsi_sync = - ( - (dsi_reg->mcde_dsi_sync &~MCDE_DSI_SW_MASK) | - (((u32) sync_dma << MCDE_DSI_SW_SHIFT) & MCDE_DSI_SW_MASK) - ); - - - return(error); -} - -mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf) -{ - mcde_error error = MCDE_OK; - struct mcde_dsi_reg *dsi_reg; - - - if (MCDE_DSI_CH_CMD2 < (u32) dsichannel) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - dsi_reg = (struct mcde_dsi_reg *) (gpar[chid]->mcde_dsi_channel_reg[dsichannel]); - } - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_PACK_MASK) | - (((u32) dsi_conf.packing << MCDE_DSI_PACK_SHIFT) & MCDE_DSI_PACK_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_DCSVID_MASK) | - (((u32) dsi_conf.synchro << MCDE_DSI_DCSVID_SHIFT) & MCDE_DSI_DCSVID_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_BYTE_SWAP_MASK) | - (((u32) dsi_conf.byte_swap << MCDE_DSI_BYTE_SWAP_SHIFT) & MCDE_DSI_BYTE_SWAP_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_BIT_SWAP_MASK) | - (((u32) dsi_conf.bit_swap << MCDE_DSI_BIT_SWAP_SHIFT) & MCDE_DSI_BIT_SWAP_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_CMD8_MASK) | - (((u32) dsi_conf.cmd8 << MCDE_DSI_CMD8_SHIFT) & MCDE_DSI_CMD8_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_DSI_VID_MODE_MASK) | - (((u32) dsi_conf.vid_mode << MCDE_DSI_VID_MODE_SHIFT) & MCDE_DSI_VID_MODE_MASK) - ); - - dsi_reg->mcde_dsi_conf0 = - ( - (dsi_reg->mcde_dsi_conf0 &~MCDE_BLANKING_MASK) | - ((u32) dsi_conf.blanking & MCDE_BLANKING_MASK) - ); - - dsi_reg->mcde_dsi_frame = - ( - (dsi_reg->mcde_dsi_frame &~MCDE_DSI_FRAME_MASK) | - ((u32) dsi_conf.words_per_frame & MCDE_DSI_FRAME_MASK) - ); - - dsi_reg->mcde_dsi_pkt = - ( - (dsi_reg->mcde_dsi_pkt &~MCDE_DSI_PACKET_MASK) | - ((u32) dsi_conf.words_per_packet & MCDE_DSI_PACKET_MASK) - ); - return(error); -} - - - -/****************************************************************************/ -/** NAME : mcdesetfifoctrl() */ -/*--------------------------------------------------------------------------*/ -/* DESCRIPTION : This routine sets the formatter selection for output FIFOs*/ -/* */ -/* */ -/* PARAMETERS : */ -/* IN :mcde_fifo_ctrl : FIFO selection control structure */ -/* InOut :None */ -/* OUT :None */ -/* */ -/* RETURN :mcde_error : MCDE error code */ -/* MCDE_OK */ -/* MCDE_INVALID_PARAMETER :if input argument is invalid */ -/*--------------------------------------------------------------------------*/ -/* Type : PUBLIC */ -/* REENTRANCY : Non Re-entrant */ -/* REENTRANCY ISSUES : */ - -/****************************************************************************/ -mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl) -{ - mcde_error error = MCDE_OK; - - /*FIFO A Output Selection*/ - switch (chid) - { - case MCDE_CH_A: - switch (fifo_ctrl.out_fifoa) - { - case MCDE_DPI_A: - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - break; - - case MCDE_DSI_VID0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID0] = MCDE_CH_A; - - break; - - case MCDE_DSI_VID1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID1] = MCDE_CH_A; - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIA_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIA_EN_SHIFT) & MCDE_CTRL_DPIA_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD2_EN_MASK) | - ((u32) MCDE_SET_BIT & MCDE_DSICMD2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_A; - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_B: - /*FIFO B Output Selection*/ - switch (fifo_ctrl.out_fifob) - { - case MCDE_DPI_B: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - break; - - case MCDE_DSI_VID0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID0] = MCDE_CH_B; - break; - - case MCDE_DSI_VID1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID1] = MCDE_CH_B; - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DPIB_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DPIB_EN_SHIFT) & MCDE_CTRL_DPIB_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_FABMUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_FABMUX_SHIFT) & MCDE_CTRL_FABMUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID0_EN_SHIFT) & MCDE_DSIVID0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSIVID1_EN_SHIFT) & MCDE_DSIVID1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD2_EN_MASK) | - ((u32) MCDE_SET_BIT & MCDE_DSICMD2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_B; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_C0: - /*FIFO 0 Output Selection*/ - switch (fifo_ctrl.out_fifo0) - { - case MCDE_DBI_C0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - break; - - case MCDE_DSI_CMD0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD0] = MCDE_CH_C0; - - break; - - case MCDE_DSI_CMD1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD1] = MCDE_CH_C0; - break; - - case MCDE_DSI_VID2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC0_EN_SHIFT) & MCDE_CTRL_DBIC0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID2_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID2_EN_SHIFT) & MCDE_DSIVID2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_VID2] = MCDE_CH_C0; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - case MCDE_CH_C1: - /*FIFO 1 Output Selection*/ - switch (fifo_ctrl.out_fifo1) - { - case MCDE_DBI_C1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - break; - - case MCDE_DSI_CMD0: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD0] = MCDE_CH_C1; - - break; - - case MCDE_DSI_CMD1: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD1] = MCDE_CH_C1; - - break; - - case MCDE_DSI_CMD2: - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_DBIC1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_CTRL_DBIC1_EN_SHIFT) & MCDE_CTRL_DBIC1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_F01MUX_MASK) | - (((u32) MCDE_SET_BIT << MCDE_CTRL_F01MUX_SHIFT) & MCDE_CTRL_F01MUX_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD0_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD0_EN_SHIFT) & MCDE_DSICMD0_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSICMD1_EN_MASK) | - (((u32) MCDE_CLEAR_BIT << MCDE_DSICMD1_EN_SHIFT) & MCDE_DSICMD1_EN_MASK) - ); - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_DSIVID2_EN_MASK) | - (((u32) MCDE_SET_BIT << MCDE_DSIVID2_EN_SHIFT) & MCDE_DSIVID2_EN_MASK) - ); - - gpar[chid]->dsi_formatter_plugged_channel[MCDE_DSI_CH_CMD2] = MCDE_CH_C1; - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - break; - default: - error = MCDE_INVALID_PARAMETER; - } - return(error); -} -#ifdef PLATFORM_8500 -mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf) -{ - mcde_error error = MCDE_OK; - - // if (chid == CHANNEL_C0) - // gpar[chid]->regbase->mcde_cfg0 = 0x5e145001; /** has to be removed, Added for testing */ - - switch (output_conf) - { - case MCDE_CONF_TVA_DPIC0_LCDB: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_TVA_DPIC0_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_TVB_DPIC1_LCDA: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_TVB_DPIC1_LCDA_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_DPIC1_LCDA: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DPIC1_LCDA_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_DPIC0_LCDB: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DPIC0_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - - case MCDE_CONF_LCDA_LCDB: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_LCDA_LCDB_MASK & MCDE_SYNCMUX_MASK) - ); - break; - case MCDE_CONF_DSI: - gpar[chid]->regbase->mcde_cfg0 = - ( - (gpar[chid]->regbase->mcde_cfg0 &~MCDE_SYNCMUX_MASK) | - ((u32) MCDE_DSI_MASK & MCDE_SYNCMUX_MASK) - ); - break; - default: - error = MCDE_INVALID_PARAMETER; - } - - return(error); -} -#endif -/****************************************************************************/ -/* NAME : mcdesetbufferaddr() */ -/*--------------------------------------------------------------------------*/ -/* DESCRIPTION : This API is used to set the base address of the buffer. */ -/* */ -/* */ -/* PARAMETERS : */ -/* IN :mcde_ext_src src_id: External source id number to be */ -/* configured */ -/* mcde_buffer_id buffer_id : Buffer id whose address is */ -/* to be configured */ -/* uint32 address : Address of the buffer */ -/* InOut :None */ -/* OUT :None */ -/* */ -/* RETURN :mcde_error : MCDE error code */ -/* MCDE_OK */ -/* MCDE_INVALID_PARAMETER :if input argument is invalid */ -/*--------------------------------------------------------------------------*/ -/* Type : PUBLIC */ -/* REENTRANCY : Non Re-entrant */ -/* REENTRANCY ISSUES : */ - -/****************************************************************************/ -mcde_error mcdesetbufferaddr -( - mcde_ch_id chid, - mcde_ext_src src_id, - mcde_buffer_id buffer_id, - u32 address -) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - switch (buffer_id) - { - case MCDE_BUFFER_ID_0: - ext_src->mcde_extsrc_a0 = - ( - (ext_src->mcde_extsrc_a0 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - case MCDE_BUFFER_ID_1: - ext_src->mcde_extsrc_a1 = - ( - (ext_src->mcde_extsrc_a1 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - case MCDE_BUFFER_ID_2: - ext_src->mcde_extsrc_a2 = - ( - (ext_src->mcde_extsrc_a2 &~MCDE_EXT_BUFFER_MASK) | - ((address << MCDE_EXT_BUFFER_SHIFT) & MCDE_EXT_BUFFER_MASK) - ); - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) buffer_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - return(error); -} - -mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BEPO_MASK) | - (((u32) config.ovr_pxlorder << MCDE_EXT_BEPO_SHIFT) & MCDE_EXT_BEPO_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BEBO_MASK) | - (((u32) config.endianity << MCDE_EXT_BEBO_SHIFT) & MCDE_EXT_BEBO_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BGR_MASK) | - (((u32) config.rgb_format << MCDE_EXT_BGR_SHIFT) & MCDE_EXT_BGR_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BPP_MASK) | - (((u32) config.bpp << MCDE_EXT_BPP_SHIFT) & MCDE_EXT_BPP_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_PRI_OVR_MASK) | - (((u32) config.provr_id << MCDE_EXT_PRI_OVR_SHIFT) & MCDE_EXT_PRI_OVR_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_NUM_MASK) | - (((u32) config.buf_num << MCDE_EXT_BUFFER_NUM_SHIFT) & MCDE_EXT_BUFFER_NUM_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) config.buf_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - return(error); -} - -mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_FORCEFSDIV_MASK) | - (((u32) control.fs_div << MCDE_EXT_FORCEFSDIV_SHIFT) & MCDE_EXT_FORCEFSDIV_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_FSDISABLE_MASK) | - (((u32) control.fs_ctrl << MCDE_EXT_FSDISABLE_SHIFT) & MCDE_EXT_FSDISABLE_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_OVR_CTRL_MASK) | - (((u32) control.ovr_ctrl << MCDE_EXT_OVR_CTRL_SHIFT) & MCDE_EXT_OVR_CTRL_MASK) - ); - - ext_src->mcde_extsrc_cr = - ( - (ext_src->mcde_extsrc_cr &~MCDE_EXT_BUF_MODE_MASK) | - ((u32) control.sel_mode & MCDE_EXT_BUF_MODE_MASK) - ); - - return(error); -} -mcde_error mcdesetbufid(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, mcde_num_buffer_used buffer_num) -{ - mcde_error error = MCDE_OK; - struct mcde_ext_src_reg *ext_src; - - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[src_id]); - - if ((int) buffer_id > 2) - { - return(MCDE_INVALID_PARAMETER); - } - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_ID_MASK) | - ((u32) buffer_id & MCDE_EXT_BUFFER_ID_MASK) - ); - - ext_src->mcde_extsrc_conf = - ( - (ext_src->mcde_extsrc_conf &~MCDE_EXT_BUFFER_NUM_MASK) | - (((u32) buffer_num << MCDE_EXT_BUFFER_NUM_SHIFT) & MCDE_EXT_BUFFER_NUM_MASK) - ); - - - return(error); -} -mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_COLCTRL_MASK) | - (((u32) col_ctrl << MCDE_OVR_COLCTRL_SHIFT) & MCDE_OVR_COLCTRL_MASK) - ); - return error; -} -mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_OVLEN_MASK) | - ((u32) ovr_cr.ovr_state & MCDE_OVR_OVLEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_COLCTRL_MASK) | - (((u32) ovr_cr.col_ctrl << MCDE_OVR_COLCTRL_SHIFT) & MCDE_OVR_COLCTRL_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_PALCTRL_MASK) | - (((u32) ovr_cr.pal_control << MCDE_OVR_PALCTRL_SHIFT) & MCDE_OVR_PALCTRL_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_CKEYEN_MASK) | - (((u32) ovr_cr.color_key << MCDE_OVR_CKEYEN_SHIFT) & MCDE_OVR_CKEYEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_STBPRIO_MASK) | - (((u32) ovr_cr.priority << MCDE_OVR_STBPRIO_SHIFT) & MCDE_OVR_STBPRIO_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_BURSTSZ_MASK) | - (((u32) ovr_cr.burst_req << MCDE_OVR_BURSTSZ_SHIFT) & MCDE_OVR_BURSTSZ_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_MAXREQ_MASK) | - (((u32) ovr_cr.outstnd_req << MCDE_OVR_MAXREQ_SHIFT) & MCDE_OVR_MAXREQ_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_ROTBURSTSIZE_MASK) | - (((u32) ovr_cr.rot_burst_req << MCDE_OVR_ROTBURSTSIZE_SHIFT) & MCDE_OVR_ROTBURSTSIZE_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_ALPHAPMEN_MASK) | - (((u32) ovr_cr.alpha << MCDE_OVR_ALPHAPMEN_SHIFT) & MCDE_OVR_ALPHAPMEN_MASK) - ); - - ovr_config->mcde_ovl_cr = - ( - (ovr_config->mcde_ovl_cr &~MCDE_OVR_CLIPEN_MASK) | - (((u32) ovr_cr.clip << MCDE_OVR_CLIPEN_SHIFT) & MCDE_OVR_CLIPEN_MASK) - ); - - - return(error); -} - -mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_LPF_MASK) | - (((u32) ovr_conf.line_per_frame << MCDE_OVR_LPF_SHIFT) & MCDE_OVR_LPF_MASK) - ); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_EXT_SRCID_MASK) | - (((u32) ovr_conf.src_id << MCDE_EXT_SRCID_SHIFT) & MCDE_EXT_SRCID_MASK) - ); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_PPL_MASK) | - ((u32) ovr_conf.ovr_ppl & MCDE_OVR_PPL_MASK) - ); - - return(error); -} - -mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_WATERMARK_MASK) | - (((u32) ovr_conf2.watermark_level << MCDE_WATERMARK_SHIFT) & MCDE_WATERMARK_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_OVR_OPQ_MASK) | - (((u32) ovr_conf2.ovr_opaq << MCDE_OVR_OPQ_SHIFT) & MCDE_OVR_OPQ_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_ALPHAVALUE_MASK) | - (((u32) ovr_conf2.alpha_value << MCDE_ALPHAVALUE_SHIFT) & MCDE_ALPHAVALUE_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_PIXOFF_MASK) | - (((u32) ovr_conf2.pixoff << MCDE_PIXOFF_SHIFT) & MCDE_PIXOFF_MASK) - ); - - ovr_config->mcde_ovl_conf2 = - ( - (ovr_config->mcde_ovl_conf2 &~MCDE_OVR_BLEND_MASK) | - ((u32) ovr_conf2.ovr_blend & MCDE_OVR_BLEND_MASK) - ); - - return(error); -} -mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_ljinc = ((ovr_ljinc << MCDE_LINEINCREMENT_SHIFT) & MCDE_LINEINCREMENT_MASK); - - return(error); -} -#ifdef PLATFORM_8500 -mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - - ovr_config->mcde_ovl_crop = - ( - (ovr_config->mcde_ovl_crop &~MCDE_YCLIP_MASK) | - ((ovr_topmargin << MCDE_YCLIP_SHIFT) & MCDE_YCLIP_MASK) - ); - - - ovr_config->mcde_ovl_crop = - ( - (ovr_config->mcde_ovl_crop &~MCDE_XCLIP_MASK) | - (((u32) ovr_leftmargin << MCDE_XCLIP_SHIFT) & MCDE_XCLIP_MASK) - ); - - - return(error); -} -#endif -mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_ZLEVEL_MASK) | - (((u32) ovr_comp.ovr_zlevel << MCDE_OVR_ZLEVEL_SHIFT) & MCDE_OVR_ZLEVEL_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_YPOS_MASK) | - (((u32) ovr_comp.ovr_ypos << MCDE_OVR_YPOS_SHIFT) & MCDE_OVR_YPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_CHID_MASK) | - (((u32) ovr_comp.ch_id << MCDE_OVR_CHID_SHIFT) & MCDE_OVR_CHID_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_XPOS_MASK) | - ((u32) ovr_comp.ovr_xpos & MCDE_OVR_XPOS_MASK) - ); - - return(error); -} -#ifdef PLATFORM_8500 -mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_bot_rht_clip= - ( - (ovr_config->mcde_ovl_bot_rht_clip&~MCDE_YBRCOOR_MASK) | - (((u32) ovr_clip.ybrcoor << MCDE_YBRCOOR_SHIFT) & MCDE_YBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_top_left_clip= - ( - (ovr_config->mcde_ovl_top_left_clip &~MCDE_YBRCOOR_MASK) | - (((u32) ovr_clip.ytlcoor << MCDE_YBRCOOR_SHIFT) & MCDE_YBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_bot_rht_clip = - ( - (ovr_config->mcde_ovl_bot_rht_clip &~MCDE_XBRCOOR_MASK) | - ((u32) ovr_clip.xbrcoor & MCDE_XBRCOOR_MASK) - ); - - ovr_config->mcde_ovl_top_left_clip = - ( - (ovr_config->mcde_ovl_top_left_clip &~MCDE_XBRCOOR_MASK) | - ((u32) ovr_clip.xtlcoor & MCDE_XBRCOOR_MASK) - ); - - return(error); -} -#endif -mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_cr = ((ovr_config->mcde_ovl_cr &~MCDE_OVR_OVLEN_MASK) | (state & MCDE_OVR_OVLEN_MASK)); - - return(error); -} - -mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_PPL_MASK) | - ((u32) ppl & MCDE_OVR_PPL_MASK) - ); - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_OVR_LPF_MASK) | - (((u32) lpf << MCDE_OVR_LPF_SHIFT) & MCDE_OVR_LPF_MASK) - ); - - - return(error); -} - -mcde_error mcdeovraassociatechnl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ch_id ch_id) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_CHID_MASK) | - (((u32) ch_id << MCDE_OVR_CHID_SHIFT) & MCDE_OVR_CHID_MASK) - ); - - return(error); -} - - -mcde_error mcdesetovrXYZpos(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ovr_xy xy_pos, u8 z_pos) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_YPOS_MASK) | - (((u32) xy_pos.ovr_ypos << MCDE_OVR_YPOS_SHIFT) & MCDE_OVR_YPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_XPOS_MASK) | - ((u32) xy_pos.ovr_xpos & MCDE_OVR_XPOS_MASK) - ); - - ovr_config->mcde_ovl_comp = - ( - (ovr_config->mcde_ovl_comp &~MCDE_OVR_ZLEVEL_MASK) | - (((u32) z_pos << MCDE_OVR_ZLEVEL_SHIFT) & MCDE_OVR_ZLEVEL_MASK) - ); - - return(error); -} - -mcde_error mcdeovrassociateextsrc(mcde_ch_id chid, mcde_overlay_id overlay, mcde_ext_src ext_src) -{ - mcde_error error = MCDE_OK; - struct mcde_ovl_reg *ovr_config; - - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[overlay]); - - ovr_config->mcde_ovl_conf = - ( - (ovr_config->mcde_ovl_conf &~MCDE_EXT_SRCID_MASK) | - (((u32) ext_src << MCDE_EXT_SRCID_SHIFT) & MCDE_EXT_SRCID_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config) -{ - mcde_error mcde_error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_ch_conf = - ( - (ch_syncreg->mcde_ch_conf &~MCDE_CHXLPF_MASK) | - (((u32) config.lpf << MCDE_CHXLPF_SHIFT) & MCDE_CHXLPF_MASK) - ); - - ch_syncreg->mcde_ch_conf = - ( - (ch_syncreg->mcde_ch_conf &~MCDE_CHXPPL_MASK) | - ((u32) config.ppl & MCDE_CHXPPL_MASK) - ); - - - return(mcde_error); -} - -mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod) -{ - mcde_error mcde_error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chsyn_mod = - ( - (ch_syncreg->mcde_chsyn_mod &~MCDE_OUTINTERFACE_MASK) | - (((u32) sync_mod.out_synch_interface << MCDE_OUTINTERFACE_SHIFT) & MCDE_OUTINTERFACE_MASK) - ); - - ch_syncreg->mcde_chsyn_mod = - ( - (ch_syncreg->mcde_chsyn_mod &~MCDE_SRCSYNCH_MASK) | - ((u32) sync_mod.ch_synch_src & MCDE_SRCSYNCH_MASK) - ); - - - return(mcde_error); -} -mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config) -{ - mcde_error mcde_error = MCDE_OK; -#ifdef PLATFORM_8500 - struct mcde_ch_reg *ch_x_reg; -#else - struct mcde_ch_synch_reg *ch_x_reg; -#endif - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { -#ifdef PLATFORM_8500 - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); -#else - ch_x_reg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[gpar[chid]->mcde_cur_ovl_bmp]); -#endif - - } - - ch_x_reg->mcde_chsyn_con = ((ch_x_reg->mcde_chsyn_con & ~MCDE_SWINTVCNT_MASK) | (((u32)ch_config.swint_vcnt << MCDE_SWINTVCNT_SHIFT) & MCDE_SWINTVCNT_MASK)); - /**set to active video if you want to receive VSYNC interrupts*/ - ch_x_reg->mcde_chsyn_con = ((ch_x_reg->mcde_chsyn_con & ~MCDE_SWINTVEVENT_MASK) | (((u32)ch_config.swint_vevent << MCDE_SWINTVEVENT_SHIFT) & MCDE_SWINTVEVENT_MASK)); - ch_x_reg->mcde_chsyn_con = ((ch_x_reg->mcde_chsyn_con & ~MCDE_HWREQVCNT_MASK) | (((u32)ch_config.hwreq_vcnt << MCDE_HWREQVCNT_SHIFT) & MCDE_HWREQVCNT_MASK)); - ch_x_reg->mcde_chsyn_con = ((ch_x_reg->mcde_chsyn_con & ~MCDE_HWREQVEVENT_MASK) | ((u32)ch_config.hwreq_vevent & MCDE_HWREQVEVENT_MASK)); - - return(mcde_error); -} -mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chsyn_sw = - ( - (ch_syncreg->mcde_chsyn_sw &~MCDE_SW_TRIG_MASK) | - ((u32) sw_trig & MCDE_SW_TRIG_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chsyn_bck = - ( - (ch_syncreg->mcde_chsyn_bck &~MCDE_REDCOLOR_MASK) | - ((color.red << MCDE_REDCOLOR_SHIFT) & MCDE_REDCOLOR_MASK) - ); - - ch_syncreg->mcde_chsyn_bck = - ( - (ch_syncreg->mcde_chsyn_bck &~MCDE_GREENCOLOR_MASK) | - ((color.green << MCDE_GREENCOLOR_SHIFT) & MCDE_GREENCOLOR_MASK) - ); - - ch_syncreg->mcde_chsyn_bck = - ( - (ch_syncreg->mcde_chsyn_bck &~MCDE_BLUECOLOR_MASK) | - (color.blue & MCDE_BLUECOLOR_MASK) - ); - - - return(error); -} - -mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_chsyn_prio = - ( - (ch_syncreg->mcde_chsyn_prio &~MCDE_CHPRIORITY_MASK) | - (priority & MCDE_CHPRIORITY_MASK) - ); - - return(error); -} - -mcde_error mcdesetoutdevicelpfandppl(mcde_ch_id chid, u16 channelnum, u16 lpf, u16 ppl) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_synch_reg *ch_syncreg; - - ch_syncreg = (struct mcde_ch_synch_reg *) (gpar[chid]->ch_regbase1[channelnum]); - - ch_syncreg->mcde_ch_conf = - ( - (ch_syncreg->mcde_ch_conf &~MCDE_CHXLPF_MASK) | - ((lpf << MCDE_CHXLPF_SHIFT) & MCDE_CHXLPF_MASK) - ); - - ch_syncreg->mcde_ch_conf = ((ch_syncreg->mcde_ch_conf &~MCDE_CHXPPL_MASK) | (ppl & MCDE_CHXLPF_MASK)); - - - return(error); -} - -mcde_error mcdesetchnlCconf(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_chc_config config) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_RES1_MASK) | - (((u32) config.res_pol << MCDE_RES1_SHIFT) & MCDE_RES1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_RD1_MASK) | - (((u32) config.rd_pol << MCDE_RD1_SHIFT) & MCDE_RD1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_WR1_MASK) | - (((u32) config.wr_pol << MCDE_WR1_SHIFT) & MCDE_WR1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CD1_MASK) | - (((u32) config.cd_pol << MCDE_CD1_SHIFT) & MCDE_CD1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CS1_MASK) | - (((u32) config.cs_pol << MCDE_CS1_SHIFT) & MCDE_CS1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CS1EN_MASK) | - (((u32) config.csen << MCDE_CS1EN_SHIFT) & MCDE_CS1EN_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_INBAND1_MASK) | - (((u32) config.inband_mode << MCDE_INBAND1_SHIFT) & MCDE_INBAND1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_BUSSIZE1_MASK) | - (((u32) config.bus_size << MCDE_BUSSIZE1_SHIFT) & MCDE_BUSSIZE1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCEN1_MASK) | - (((u32) config.syncen << MCDE_SYNCEN1_SHIFT) & MCDE_SYNCEN1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_WMLVL1_MASK) | - (((u32) config.fifo_watermark << MCDE_WMLVL1_SHIFT) & MCDE_WMLVL1_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_C1EN_MASK) | - (((u32) config.chcen << MCDE_C1EN_SHIFT) & MCDE_C1EN_MASK) - ); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_RES2_MASK) | - (((u32) config.res_pol << MCDE_RES2_SHIFT) & MCDE_RES2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_RD2_MASK) | - (((u32) config.rd_pol << MCDE_RD2_SHIFT) & MCDE_RD2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_WR2_MASK) | - (((u32) config.wr_pol << MCDE_WR2_SHIFT) & MCDE_WR2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CD2_MASK) | - (((u32) config.cd_pol << MCDE_CD2_SHIFT) & MCDE_CD2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CS2_MASK) | - (((u32) config.cs_pol << MCDE_CS2_SHIFT) & MCDE_CS2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CS2EN_MASK) | - (((u32) config.csen << MCDE_CS2EN_SHIFT) & MCDE_CS2EN_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_INBAND2_MASK) | - (((u32) config.inband_mode << MCDE_INBAND2_SHIFT) & MCDE_INBAND2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_BUSSIZE2_MASK) | - (((u32) config.bus_size << MCDE_BUSSIZE2_SHIFT) & MCDE_BUSSIZE2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCEN2_MASK) | - (((u32) config.syncen << MCDE_SYNCEN2_SHIFT) & MCDE_SYNCEN2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_WMLVL2_MASK) | - (((u32) config.fifo_watermark << MCDE_WMLVL2_SHIFT) & MCDE_WMLVL2_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_C2EN_MASK) | - (((u32) config.chcen << MCDE_C2EN_SHIFT) & MCDE_C2EN_MASK) - ); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetchnlCctrl(mcde_ch_id chid, struct mcde_chc_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCCTRL_MASK) | - (((u32) control.sync << MCDE_SYNCCTRL_SHIFT) & MCDE_SYNCCTRL_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_RESEN_MASK) | - (((u32) control.resen << MCDE_RESEN_SHIFT) & MCDE_RESEN_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CLKSEL_MASK) | - (((u32) control.clksel << MCDE_CLKSEL_SHIFT) & MCDE_CLKSEL_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCSEL_MASK) | - (((u32) control.synsel << MCDE_SYNCSEL_SHIFT) & MCDE_SYNCSEL_MASK) - ); - - return(error); -} -mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - struct mcde_ch_reg *ch_x_reg; - - if (chid <= MCDE_CH_B) - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_POWEREN_MASK) | - ((power << MCDE_POWEREN_SHIFT) & MCDE_POWEREN_MASK) - ); - - }else - { - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_POWEREN_MASK) | - (((u32) power << MCDE_POWEREN_SHIFT) & MCDE_POWEREN_MASK) - ); - - } - - - return(error); -} - -mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - struct mcde_ch_reg *ch_x_reg; - - if (chid <= MCDE_CH_B) - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - ch_x_reg->mcde_ch_cr0 = ((ch_x_reg->mcde_ch_cr0 &~MCDE_FLOEN_MASK) | (flow & MCDE_FLOEN_MASK)); - - } else - { - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_chc_crc = ((ch_c_reg->mcde_chc_crc &~MCDE_FLOEN_MASK) | ((u32) flow & MCDE_FLOEN_MASK)); - } - - return(error); -} - -mcde_error mcdeconfPBCunit(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_config config) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_pbcrc0 = - ( - (ch_c_reg->mcde_chc_pbcrc0 &~MCDE_PDCTRL_SHIFT) | - (((u32) config.duplex_mode << MCDE_PDCTRL_SHIFT) & MCDE_PDCTRL_SHIFT) - ); - - ch_c_reg->mcde_chc_pbcrc0 = - ( - (ch_c_reg->mcde_chc_pbcrc0 &~MCDE_DUPLEXER_MASK) | - (((u32) config.duplex_mode << MCDE_DUPLEXER_SHIFT) & MCDE_DUPLEXER_MASK) - ); - - ch_c_reg->mcde_chc_pbcrc0 = - ( - (ch_c_reg->mcde_chc_pbcrc0 &~MCDE_BSDM_MASK) | - (((u32) config.data_segment << MCDE_BSDM_SHIFT) & MCDE_BSDM_MASK) - ); - - ch_c_reg->mcde_chc_pbcrc0 = - ( - (ch_c_reg->mcde_chc_pbcrc0 &~MCDE_BSCM_MASK) | - ((u32) config.cmd_segment & MCDE_BSCM_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_pbcrc1 = - ( - (ch_c_reg->mcde_chc_pbcrc1 &~MCDE_PDCTRL_SHIFT) | - (((u32) config.duplex_mode << MCDE_PDCTRL_SHIFT) & MCDE_PDCTRL_SHIFT) - ); - - ch_c_reg->mcde_chc_pbcrc1 = - ( - (ch_c_reg->mcde_chc_pbcrc1 &~MCDE_DUPLEXER_MASK) | - (((u32) config.duplex_mode << MCDE_DUPLEXER_SHIFT) & MCDE_DUPLEXER_MASK) - ); - - ch_c_reg->mcde_chc_pbcrc1 = - ( - (ch_c_reg->mcde_chc_pbcrc1 &~MCDE_BSDM_MASK) | - (((u32) config.data_segment << MCDE_BSDM_SHIFT) & MCDE_BSDM_MASK) - ); - - ch_c_reg->mcde_chc_pbcrc1 = - ( - (ch_c_reg->mcde_chc_pbcrc1 &~MCDE_BSCM_MASK) | - ((u32) config.cmd_segment & MCDE_BSCM_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetPBCmux(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_mux mux) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_pbcbmrc0[0] = mux.imux0; - - ch_c_reg->mcde_chc_pbcbmrc0[1] = mux.imux1; - - ch_c_reg->mcde_chc_pbcbmrc0[2] = mux.imux2; - - ch_c_reg->mcde_chc_pbcbmrc0[3] = mux.imux3; - - ch_c_reg->mcde_chc_pbcbmrc0[4] = mux.imux4; - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_pbcbmrc1[0] = mux.imux0; - - ch_c_reg->mcde_chc_pbcbmrc1[1] = mux.imux1; - - ch_c_reg->mcde_chc_pbcbmrc1[2] = mux.imux2; - - ch_c_reg->mcde_chc_pbcbmrc1[3] = mux.imux3; - - ch_c_reg->mcde_chc_pbcbmrc1[4] = mux.imux4; - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetchnlCvsyndelay(mcde_ch_id chid, mcde_chc_panel panel_id, u8 delay) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_sctrc = ((ch_c_reg->mcde_chc_sctrc &~MCDE_SYNCDELC0_MASK) | (delay & MCDE_SYNCDELC0_MASK)); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_sctrc = - ( - (ch_c_reg->mcde_chc_sctrc &~MCDE_SYNCDELC1_MASK) | - ((delay << MCDE_SYNCDELC1_SHIFT) & MCDE_SYNCDELC1_MASK) - ); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchnlCsynctrigdelay(mcde_ch_id chid, u8 delay) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_chc_sctrc = - ( - (ch_c_reg->mcde_chc_sctrc &~MCDE_TRDELC_MASK) | - ((delay << MCDE_TRDELC_SHIFT) & MCDE_TRDELC_MASK) - ); - - - return(error); -} -mcde_error mcdesetPBCbitctrl(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_pbc_bitctrl bit_control) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_pbcbcrc0[0] = bit_control.bit_ctrl0; - - ch_c_reg->mcde_chc_pbcbcrc0[1] = bit_control.bit_ctrl1; - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_pbcbcrc1[0] = bit_control.bit_ctrl0; - - ch_c_reg->mcde_chc_pbcbcrc1[1] = bit_control.bit_ctrl1; - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchnlCsynccapconf(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_sync_conf config) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSDBL_MASK) | - ((config.debounce_length << MCDE_VSDBL_SHIFT) & MCDE_VSDBL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSSEL_MASK) | - (((u32) config.sync_sel << MCDE_VSSEL_SHIFT) & MCDE_VSSEL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSPOL_MASK) | - (((u32) config.sync_pol << MCDE_VSPOL_SHIFT) & MCDE_VSPOL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSPDIV_MASK) | - (((u32) config.clk_div << MCDE_VSPDIV_SHIFT) & MCDE_VSPDIV_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSPMAX_MASK) | - (((u32) config.vsp_max << MCDE_VSPMAX_SHIFT) & MCDE_VSPMAX_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[0] = - ( - (ch_c_reg->mcde_chc_vscrc[0] &~MCDE_VSPMIN_MASK) | - ((u32) config.vsp_min & MCDE_VSPMIN_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSDBL_MASK) | - ((config.debounce_length << MCDE_VSDBL_SHIFT) & MCDE_VSDBL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSSEL_MASK) | - (((u32) config.sync_sel << MCDE_VSSEL_SHIFT) & MCDE_VSSEL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSPOL_MASK) | - (((u32) config.sync_pol << MCDE_VSPOL_SHIFT) & MCDE_VSPOL_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSPDIV_MASK) | - (((u32) config.clk_div << MCDE_VSPDIV_SHIFT) & MCDE_VSPDIV_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSPMAX_MASK) | - (((u32) config.vsp_max << MCDE_VSPMAX_SHIFT) & MCDE_VSPMAX_MASK) - ); - - ch_c_reg->mcde_chc_vscrc[1] = - ( - (ch_c_reg->mcde_chc_vscrc[1] &~MCDE_VSPMIN_MASK) | - ((u32) config.vsp_min & MCDE_VSPMIN_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdechnlCclkandsyncsel(mcde_ch_id chid, mcde_clk_sel clk_sel, mcde_synchro_select sync_select) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_CLKSEL_MASK) | - (((u32) clk_sel << MCDE_CLKSEL_SHIFT) & MCDE_CLKSEL_MASK) - ); - - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCSEL_MASK) | - (((u32) sync_select << MCDE_SYNCSEL_SHIFT) & MCDE_SYNCSEL_MASK) - ); - - return(error); -} - -mcde_error mcdesetchnlCmode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_chc_enable state) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_C1EN_MASK) | - ((state << MCDE_C1EN_SHIFT) & MCDE_C1EN_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_C2EN_MASK) | - ((state << MCDE_C2EN_SHIFT) & MCDE_C2EN_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - - return(error); -} - -mcde_error mcdesetsynchromode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_synchro_capture sync_enable) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCEN1_MASK) | - (((u32) sync_enable << MCDE_SYNCEN1_SHIFT) & MCDE_SYNCEN1_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_crc = - ( - (ch_c_reg->mcde_chc_crc &~MCDE_SYNCEN2_MASK) | - (((u32) sync_enable << MCDE_SYNCEN2_SHIFT) & MCDE_SYNCEN2_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetchipseltiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_cd_timing_activate active) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_cscdtr[0] = - ( - (ch_c_reg->mcde_chc_cscdtr[0] &~MCDE_CSCDDEACT_MASK) | - ((active.cs_cd_deactivate << MCDE_CSCDDEACT_SHIFT) & MCDE_CSCDDEACT_MASK) - ); - - ch_c_reg->mcde_chc_cscdtr[0] = - ( - (ch_c_reg->mcde_chc_cscdtr[0] &~MCDE_CSCDACT_MASK) | - (active.cs_cd_activate & MCDE_CSCDACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_cscdtr[1] = - ( - (ch_c_reg->mcde_chc_cscdtr[1] &~MCDE_CSCDDEACT_MASK) | - ((active.cs_cd_deactivate << MCDE_CSCDDEACT_SHIFT) & MCDE_CSCDDEACT_MASK) - ); - - ch_c_reg->mcde_chc_cscdtr[1] = - ( - (ch_c_reg->mcde_chc_cscdtr[1] &~MCDE_CSCDACT_MASK) | - (active.cs_cd_activate & MCDE_CSCDACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetbusaccessnum(mcde_ch_id chid, mcde_chc_panel panel_id, u8 bcn) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_bcnr[0] = ((ch_c_reg->mcde_chc_bcnr[0] &~MCDE_BCN_MASK) | (bcn & MCDE_BCN_MASK)); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_bcnr[1] = ((ch_c_reg->mcde_chc_bcnr[1] &~MCDE_BCN_MASK) | (bcn & MCDE_BCN_MASK)); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdesetrdwrtiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_rw_timing rw_time) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_rdwrtr[0] = - ( - (ch_c_reg->mcde_chc_rdwrtr[0] &~MCDE_MOTINT_MASK) | - (((u32) rw_time.panel_type << MCDE_MOTINT_SHIFT) & MCDE_MOTINT_MASK) - ); - - ch_c_reg->mcde_chc_rdwrtr[0] = - ( - (ch_c_reg->mcde_chc_rdwrtr[0] &~MCDE_RWDEACT_MASK) | - ((rw_time.readwrite_deactivate << MCDE_RWDEACT_SHIFT) & MCDE_RWDEACT_MASK) - ); - - ch_c_reg->mcde_chc_rdwrtr[0] = - ( - (ch_c_reg->mcde_chc_rdwrtr[0] &~MCDE_RWACT_MASK) | - (rw_time.readwrite_activate & MCDE_RWACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_rdwrtr[1] = - ( - (ch_c_reg->mcde_chc_rdwrtr[1] &~MCDE_MOTINT_MASK) | - (((u32) rw_time.panel_type << MCDE_MOTINT_SHIFT) & MCDE_MOTINT_MASK) - ); - - ch_c_reg->mcde_chc_rdwrtr[1] = - ( - (ch_c_reg->mcde_chc_rdwrtr[1] &~MCDE_RWDEACT_MASK) | - ((rw_time.readwrite_deactivate << MCDE_RWDEACT_SHIFT) & MCDE_RWDEACT_MASK) - ); - - ch_c_reg->mcde_chc_rdwrtr[1] = - ( - (ch_c_reg->mcde_chc_rdwrtr[1] &~MCDE_RWACT_MASK) | - (rw_time.readwrite_activate & MCDE_RWACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdesetdataouttiming(mcde_ch_id chid, mcde_chc_panel panel_id, struct mcde_data_out_timing data_time) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_dotr[0] = - ( - (ch_c_reg->mcde_chc_dotr[0] &~MCDE_DODEACT_MASK) | - ((data_time.data_out_deactivate << MCDE_DODEACT_SHIFT) & MCDE_DODEACT_MASK) - ); - - ch_c_reg->mcde_chc_dotr[0] = - ( - (ch_c_reg->mcde_chc_dotr[0] &~MCDE_DOACT_MASK) | - (data_time.data_out_activate & MCDE_DOACT_MASK) - ); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_dotr[1] = - ( - (ch_c_reg->mcde_chc_dotr[1] &~MCDE_DODEACT_MASK) | - ((data_time.data_out_deactivate << MCDE_DODEACT_SHIFT) & MCDE_DODEACT_MASK) - ); - - ch_c_reg->mcde_chc_dotr[1] = - ( - (ch_c_reg->mcde_chc_dotr[1] &~MCDE_DOACT_MASK) | - (data_time.data_out_activate & MCDE_DOACT_MASK) - ); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} - -mcde_error mcdewrcmd(mcde_ch_id chid, mcde_chc_panel panel_id, u32 command) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_wcmd[0] = (command & MCDE_DATACOMMANDMASK); - - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_wcmd[1] = (command & MCDE_DATACOMMANDMASK); - - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdewrdata(mcde_ch_id chid, mcde_chc_panel panel_id, u32 data) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - - switch (panel_id) - { - case MCDE_PANEL_C0: - ch_c_reg->mcde_chc_wd[0] = (data & MCDE_DATACOMMANDMASK); - break; - - case MCDE_PANEL_C1: - ch_c_reg->mcde_chc_wd[1] = (data & MCDE_DATACOMMANDMASK); - break; - - default: - return(MCDE_INVALID_PARAMETER); - } - - return(error); -} -mcde_error mcdewrtxfifo(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_txfifo_request_type type, u32 data) -{ - mcde_error error = MCDE_OK; - struct mcde_chc_reg *ch_c_reg; - - ch_c_reg = (struct mcde_chc_reg *) (gpar[chid]->ch_c_reg); - switch (type) - { - case MCDE_TXFIFO_WRITE_DATA: - ch_c_reg->mcde_chc_wd[panel_id] = (data & MCDE_DATACOMMANDMASK); - - break; - - case MCDE_TXFIFO_WRITE_COMMAND: - ch_c_reg->mcde_chc_wcmd[panel_id] = (data & MCDE_DATACOMMANDMASK); - - break; - - default: - error = MCDE_INVALID_PARAMETER; - } - - return(error); -} - -mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_KEYCTRL_MASK) | - (((u32) key_ctrl << MCDE_KEYCTRL_SHIFT) & MCDE_KEYCTRL_MASK) - ); - return(error); -} -mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_ALPHA_MASK) | - (((u32) blend_ctrl.alpha_blend << MCDE_CHX_ALPHA_SHIFT) & MCDE_CHX_ALPHA_MASK) - ); - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDCONTROL_MASK) | - (((u32) blend_ctrl.blend_ctrl << MCDE_BLENDCONTROL_SHIFT) & MCDE_BLENDCONTROL_MASK) - ); - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDEN_MASK) | - (((u32) blend_ctrl.blenden << MCDE_BLENDEN_SHIFT) & MCDE_BLENDEN_MASK) - ); - return(error); -} -mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - if (rot_ctrl == MCDE_ROTATION_ENABLE) - { - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_ROTDIR_MASK) | - (((u32) rot_dir << MCDE_CHX_ROTDIR_SHIFT) & MCDE_CHX_ROTDIR_MASK) - ); - } - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_ROTEN_MASK) | - (((u32) rot_ctrl << MCDE_ROTEN_SHIFT) & MCDE_ROTEN_MASK) - ); - return error; -} -mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_DITHEN_MASK) | - (((u32) dithering_control << MCDE_DITHEN_SHIFT) & MCDE_DITHEN_MASK) - ); - return (error); -} -mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_BURSTSIZE_MASK) | - (((u32) control.chx_read_request << MCDE_CHX_BURSTSIZE_SHIFT) & MCDE_CHX_BURSTSIZE_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_ALPHA_MASK) | - (((u32) control.alpha_blend << MCDE_CHX_ALPHA_SHIFT) & MCDE_CHX_ALPHA_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_ROTDIR_MASK) | - (((u32) control.rot_dir << MCDE_CHX_ROTDIR_SHIFT) & MCDE_CHX_ROTDIR_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CHX_GAMAEN_MASK) | - (((u32) control.gamma_ctrl << MCDE_CHX_GAMAEN_SHIFT) & MCDE_CHX_GAMAEN_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_FLICKFORMAT_MASK) | - (((u32) control.flicker_format << MCDE_FLICKFORMAT_SHIFT) & MCDE_FLICKFORMAT_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_FLICKMODE_MASK) | - (((u32) control.filter_mode << MCDE_FLICKMODE_SHIFT) & MCDE_FLICKMODE_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDCONTROL_MASK) | - (((u32) control.blend << MCDE_BLENDCONTROL_SHIFT) & MCDE_BLENDCONTROL_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_KEYCTRL_MASK) | - (((u32) control.key_ctrl << MCDE_KEYCTRL_SHIFT) & MCDE_KEYCTRL_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_ROTEN_MASK) | - (((u32) control.rot_enable << MCDE_ROTEN_SHIFT) & MCDE_ROTEN_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_DITHEN_MASK) | - (((u32) control.dither_ctrl << MCDE_DITHEN_SHIFT) & MCDE_DITHEN_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_CEAEN_MASK) | - (((u32) control.color_enhance << MCDE_CEAEN_SHIFT) & MCDE_CEAEN_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_AFLICKEN_MASK) | - (((u32) control.anti_flicker << MCDE_AFLICKEN_SHIFT) & MCDE_AFLICKEN_MASK) - ); - - ch_x_reg->mcde_ch_cr0 = - ( - (ch_x_reg->mcde_ch_cr0 &~MCDE_BLENDEN_MASK) | - (((u32) control.blend_ctrl << MCDE_BLENDEN_SHIFT) & MCDE_BLENDEN_MASK) - ); - - - return(error); -} - -mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_CLK_MASK) | - (((u32) control.tv_clk << MCDE_CLK_SHIFT) & MCDE_CLK_MASK) - ); - - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_BCD_MASK) | - (((u32) control.bcd_ctrl << MCDE_BCD_SHIFT) & MCDE_BCD_MASK) - ); - - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_OUTBPP_MASK) | - (((u32) control.out_bpp << MCDE_OUTBPP_SHIFT) & MCDE_OUTBPP_MASK) - ); -/* Only applicable to older version of chip - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_CLP_MASK) | - (((u32) control.clk_per_line << MCDE_CLP_SHIFT) & MCDE_CLP_MASK) - ); -*/ - - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_CDWIN_MASK) | - (((u32) control.lcd_bus << MCDE_CDWIN_SHIFT) & MCDE_CDWIN_MASK) - ); - - ch_x_reg->mcde_ch_cr1 = - ( - (ch_x_reg->mcde_ch_cr1 &~MCDE_CLOCKSEL_MASK) | - (((u32) control.dpi2_clk << MCDE_CLOCKSEL_SHIFT) & MCDE_CLOCKSEL_MASK) - ); - - ch_x_reg->mcde_ch_cr1 = ((ch_x_reg->mcde_ch_cr1 &~MCDE_PCD_MASK) | ((u32) control.pcd & MCDE_PCD_MASK)); - - return(error); -} - -mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - if (type == MCDE_COLORKEY_NORMAL) - { - ch_x_reg->mcde_ch_colkey = - ( - (ch_x_reg->mcde_ch_colkey &~MCDE_KEYA_MASK) | - ((key.alpha << MCDE_KEYA_SHIFT) & MCDE_KEYA_MASK) - ); - - ch_x_reg->mcde_ch_colkey = - ( - (ch_x_reg->mcde_ch_colkey &~MCDE_KEYR_MASK) | - ((key.red << MCDE_KEYR_SHIFT) & MCDE_KEYR_MASK) - ); - - ch_x_reg->mcde_ch_colkey = - ( - (ch_x_reg->mcde_ch_colkey &~MCDE_KEYG_MASK) | - ((key.green << MCDE_KEYG_SHIFT) & MCDE_KEYG_MASK) - ); - - ch_x_reg->mcde_ch_colkey = ((ch_x_reg->mcde_ch_colkey &~MCDE_KEYB_MASK) | (key.blue & MCDE_KEYB_MASK)); - } - else - if (type == MCDE_COLORKEY_FORCE) - { - ch_x_reg->mcde_ch_fcolkey = - ( - (ch_x_reg->mcde_ch_fcolkey &~MCDE_KEYA_MASK) | - ((key.alpha << MCDE_KEYA_SHIFT) & MCDE_KEYA_MASK) - ); - - ch_x_reg->mcde_ch_fcolkey = - ( - (ch_x_reg->mcde_ch_fcolkey &~MCDE_KEYR_MASK) | - ((key.red << MCDE_KEYR_SHIFT) & MCDE_KEYR_MASK) - ); - - ch_x_reg->mcde_ch_fcolkey = - ( - (ch_x_reg->mcde_ch_fcolkey &~MCDE_KEYG_MASK) | - ((key.green << MCDE_KEYG_SHIFT) & MCDE_KEYG_MASK) - ); - - ch_x_reg->mcde_ch_fcolkey = ((ch_x_reg->mcde_ch_fcolkey &~MCDE_KEYB_MASK) | (key.blue & MCDE_KEYB_MASK)); - } - - - return(error); -} -mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_rgbconv1 = - ( - (ch_x_reg->mcde_ch_rgbconv1 &~MCDE_RGB_MASK1) | - ((coef.Yr_red << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv1 = ((ch_x_reg->mcde_ch_rgbconv1 &~MCDE_RGB_MASK2) | (coef.Yr_green & MCDE_RGB_MASK2)); - - ch_x_reg->mcde_ch_rgbconv2 = - ( - (ch_x_reg->mcde_ch_rgbconv2 &~MCDE_RGB_MASK1) | - ((coef.Yr_blue << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv2 = ((ch_x_reg->mcde_ch_rgbconv2 &~MCDE_RGB_MASK2) | (coef.Cr_red & MCDE_RGB_MASK2)); - - ch_x_reg->mcde_ch_rgbconv3 = - ( - (ch_x_reg->mcde_ch_rgbconv3 &~MCDE_RGB_MASK1) | - ((coef.Cr_green << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv3 = ((ch_x_reg->mcde_ch_rgbconv3 &~MCDE_RGB_MASK2) | (coef.Cr_blue & MCDE_RGB_MASK2)); - - ch_x_reg->mcde_ch_rgbconv4 = - ( - (ch_x_reg->mcde_ch_rgbconv4 &~MCDE_RGB_MASK1) | - ((coef.Cb_red << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv4 = ((ch_x_reg->mcde_ch_rgbconv4 &~MCDE_RGB_MASK2) | (coef.Cb_green & MCDE_RGB_MASK2)); - - ch_x_reg->mcde_ch_rgbconv5 = - ( - (ch_x_reg->mcde_ch_rgbconv5 &~MCDE_RGB_MASK1) | - ((coef.Cb_blue << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv5 = ((ch_x_reg->mcde_ch_rgbconv5 &~MCDE_RGB_MASK2) | (coef.Off_red & MCDE_RGB_MASK2)); - - ch_x_reg->mcde_ch_rgbconv6 = - ( - (ch_x_reg->mcde_ch_rgbconv6 &~MCDE_RGB_MASK1) | - ((coef.Off_green << MCDE_RGB_SHIFT) & MCDE_RGB_MASK1) - ); - - ch_x_reg->mcde_ch_rgbconv6 = ((ch_x_reg->mcde_ch_rgbconv6 &~MCDE_RGB_MASK2) | (coef.Off_blue & MCDE_RGB_MASK2)); - - return(error); -} -mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ch_ffcoef0 = - ( - (ch_x_reg->mcde_ch_ffcoef0 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl0 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef0 = - ( - (ch_x_reg->mcde_ch_ffcoef0 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff0_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef0 = - ( - (ch_x_reg->mcde_ch_ffcoef0 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff0_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef0 = - ( - (ch_x_reg->mcde_ch_ffcoef0 &~MCDE_COEFFN1_MASK) | - (coef.Coeff0_N1 & MCDE_COEFFN1_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef1 = - ( - (ch_x_reg->mcde_ch_ffcoef1 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl1 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef1 = - ( - (ch_x_reg->mcde_ch_ffcoef1 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff1_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef1 = - ( - (ch_x_reg->mcde_ch_ffcoef1 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff1_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef1 = - ( - (ch_x_reg->mcde_ch_ffcoef1 &~MCDE_COEFFN1_MASK) | - (coef.Coeff1_N1 & MCDE_COEFFN1_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef2 = - ( - (ch_x_reg->mcde_ch_ffcoef2 &~MCDE_THRESHOLD_MASK) | - ((coef.threshold_ctrl2 << MCDE_THRESHOLD_SHIFT) & MCDE_THRESHOLD_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef2 = - ( - (ch_x_reg->mcde_ch_ffcoef2 &~MCDE_COEFFN3_MASK) | - ((coef.Coeff2_N3 << MCDE_COEFFN3_SHIFT) & MCDE_COEFFN3_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef2 = - ( - (ch_x_reg->mcde_ch_ffcoef2 &~MCDE_COEFFN2_MASK) | - ((coef.Coeff2_N2 << MCDE_COEFFN2_SHIFT) & MCDE_COEFFN2_MASK) - ); - - ch_x_reg->mcde_ch_ffcoef2 = - ( - (ch_x_reg->mcde_ch_ffcoef2 &~MCDE_COEFFN1_MASK) | - (coef.Coeff2_N1 & MCDE_COEFFN1_MASK) - ); - - return(error); -} - -mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_REVVAEN_MASK) | - (((u32) control.rev_va_enable << MCDE_REVVAEN_SHIFT) & MCDE_REVVAEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_REVTGEN_MASK) | - (((u32) control.rev_toggle_enable << MCDE_REVTGEN_SHIFT) & MCDE_REVTGEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_REVLOADSEL_MASK) | - (((u32) control.rev_sync_sel << MCDE_REVLOADSEL_SHIFT) & MCDE_REVLOADSEL_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_REVDEL1_MASK) | - (((u32) control.rev_delay1 << MCDE_REVDEL1_SHIFT) & MCDE_REVDEL1_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_REVDEL0_MASK) | - (((u32) control.rev_delay0 << MCDE_REVDEL0_SHIFT) & MCDE_REVDEL0_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_PSVAEN_MASK) | - (((u32) control.ps_va_enable << MCDE_PSVAEN_SHIFT) & MCDE_PSVAEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_PSTGEN_MASK) | - (((u32) control.ps_toggle_enable << MCDE_PSTGEN_SHIFT) & MCDE_PSTGEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_PSLOADSEL_MASK) | - (((u32) control.ps_sync_sel << MCDE_PSLOADSEL_SHIFT) & MCDE_PSLOADSEL_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_PSDEL1_MASK) | - (((u32) control.ps_delay1 << MCDE_PSDEL1_SHIFT) & MCDE_PSDEL1_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim0 = - ( - (ch_x_reg->mcde_ch_lcdtim0 &~MCDE_PSDEL0_MASK) | - ((u32) control.ps_delay0 & MCDE_PSDEL0_MASK) - ); - - return(error); -} - -mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing1 control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_IOE_MASK) | - (((u32) control.io_enable << MCDE_IOE_SHIFT) & MCDE_IOE_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_IPC_MASK) | - (((u32) control.ipc << MCDE_IPC_SHIFT) & MCDE_IPC_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_IHS_MASK) | - (((u32) control.ihs << MCDE_IHS_SHIFT) & MCDE_IHS_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_IVS_MASK) | - (((u32) control.ivs << MCDE_IVS_SHIFT) & MCDE_IVS_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_IVP_MASK) | - (((u32) control.ivp << MCDE_IVP_SHIFT) & MCDE_IPC_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_ICLSPL_MASK) | - (((u32) control.iclspl << MCDE_ICLSPL_SHIFT) & MCDE_ICLSPL_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_ICLREV_MASK) | - (((u32) control.iclrev << MCDE_ICLREV_SHIFT) & MCDE_ICLREV_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_ICLSP_MASK) | - (((u32) control.iclsp << MCDE_ICLSP_SHIFT) & MCDE_ICLSP_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_SPLVAEN_MASK) | - (((u32) control.mcde_spl << MCDE_SPLVAEN_SHIFT) & MCDE_SPLVAEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_SPLTGEN_MASK) | - (((u32) control.spltgen << MCDE_SPLTGEN_SHIFT) & MCDE_SPLTGEN_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_SPLLOADSEL_MASK) | - (((u32) control.spl_sync_sel << MCDE_SPLLOADSEL_SHIFT) & MCDE_SPLLOADSEL_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_SPLDEL1_MASK) | - (((u32) control.spl_delay1 << MCDE_SPLDEL1_SHIFT) & MCDE_SPLDEL1_MASK) - ); - - ch_x_reg->mcde_ch_lcdtim1 = - ( - (ch_x_reg->mcde_ch_lcdtim1 &~MCDE_SPLDEL0_MASK) | - ((u32) control.spl_delay0 & MCDE_SPLDEL0_MASK) - ); - - return(error); -} -mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - if (0x0 == address) - { - return(MCDE_INVALID_PARAMETER); - } - if(rotnum == MCDE_ROTATE0) - ch_x_reg->mcde_rotadd0 = address; - else if(rotnum == MCDE_ROTATE1) - ch_x_reg->mcde_rotadd1 = address; - - return(error); -} - -/****************************************************************************/ -mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state) -{ - mcde_error error = MCDE_OK; - -#ifdef PLATFORM_8500 - - gpar[chid]->regbase->mcde_cr = - ( - (gpar[chid]->regbase->mcde_cr &~MCDE_CTRL_MCDEEN_MASK) | - (((u32) state << MCDE_CTRL_MCDEEN_SHIFT) & MCDE_CTRL_MCDEEN_MASK) - ); -#endif -#ifdef PLATFORM_8820 - - gpar[chid]->regbase->mcde_cr |= state; -#endif - - return(error); -} - -mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ch_pal = - ( - (ch_x_reg->mcde_ch_pal &~MCDE_ARED_MASK) | - ((palette.alphared << MCDE_ARED_SHIFT) & MCDE_ARED_MASK) - ); - - ch_x_reg->mcde_ch_pal = - ( - (ch_x_reg->mcde_ch_pal &~MCDE_GREEN_MASK) | - ((palette.green << MCDE_GREEN_SHIFT) & MCDE_GREEN_MASK) - ); - - ch_x_reg->mcde_ch_pal = ((ch_x_reg->mcde_ch_pal &~MCDE_BLUE_MASK) | (palette.blue & MCDE_BLUE_MASK)); - - return(error); -} - - -mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_FOFFY_MASK) | - ((control.y_offset << MCDE_FOFFY_SHIFT) & MCDE_FOFFY_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_FOFFX_MASK) | - ((control.x_offset << MCDE_FOFFX_SHIFT) & MCDE_FOFFX_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_MASK_BITCTRL_MASK) | - (((u32) control.masking_ctrl << MCDE_MASK_BITCTRL_SHIFT) & MCDE_MASK_BITCTRL_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_MODE_MASK) | - ((control.mode << MCDE_MODE_SHIFT) & MCDE_MODE_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_COMP_MASK) | - (((u32) control.comp_dithering << MCDE_COMP_SHIFT) & MCDE_COMP_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_TEMP_MASK) | - ((u32) control.temp_dithering & MCDE_TEMP_MASK) - ); - return(error); -} - -mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_YB_MASK) | - ((offset.y_offset_rb << MCDE_YB_SHIFT) & MCDE_YB_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_XB_MASK) | - ((offset.x_offset_rb << MCDE_XB_SHIFT) & MCDE_XB_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = - ( - (ch_x_reg->mcde_ch_ditctrl &~MCDE_YG_MASK) | - ((offset.y_offset_rg << MCDE_YG_SHIFT) & MCDE_YG_MASK) - ); - - ch_x_reg->mcde_ch_ditctrl = ((ch_x_reg->mcde_ch_ditctrl &~MCDE_XG_MASK) | (offset.x_offset_rg & MCDE_XG_MASK)); - - return(error); -} - -mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_gam = - ( - (ch_x_reg->mcde_ch_gam &~MCDE_RED_MASK) | - ((gamma.red << MCDE_ARED_SHIFT) & MCDE_RED_MASK) - ); - - ch_x_reg->mcde_ch_gam = - ( - (ch_x_reg->mcde_ch_gam &~MCDE_GREEN_MASK) | - ((gamma.green << MCDE_GREEN_SHIFT) & MCDE_GREEN_MASK) - ); - - ch_x_reg->mcde_ch_gam = ((ch_x_reg->mcde_ch_gam &~MCDE_BLUE_MASK) | (gamma.blue & MCDE_BLUE_MASK)); - - return(error); -} -mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_INTEREN_MASK) |(((u32) scan_mode << MCDE_INTEREN_SHIFT) & MCDE_INTEREN_MASK)); - - return error; -} -mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_TV_LINES_MASK) |((lcd_ctrl_reg.num_lines << MCDE_TV_LINES_SHIFT) & MCDE_TV_LINES_MASK)); - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_TVMODE_MASK) |(((u32) lcd_ctrl_reg.tv_mode << MCDE_TVMODE_SHIFT) & MCDE_TVMODE_MASK)); - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_IFIELD_MASK) |(((u32) lcd_ctrl_reg.ifield << MCDE_IFIELD_SHIFT) & MCDE_IFIELD_MASK)); - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_INTEREN_MASK) |(((u32) 0x0 << MCDE_INTEREN_SHIFT) & MCDE_INTEREN_MASK)); - ch_x_reg->mcde_ch_tvcr = ((ch_x_reg->mcde_ch_tvcr &~MCDE_SELMODE_MASK) |((u32) lcd_ctrl_reg.sel_mode & MCDE_SELMODE_MASK)); - ch_x_reg->mcde_ch_tvtim1 = ((ch_x_reg->mcde_ch_tvtim1 & ~MCDE_SWW_MASK) | ((lcd_ctrl_reg.ppl << MCDE_SWW_SHIFT) & MCDE_SWW_MASK)); - - return(error); -} -mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_tvtim1 = ((ch_x_reg->mcde_ch_tvtim1 & ~MCDE_DHO_MASK) | (lcd_horizontal_timing.hbp & MCDE_DHO_MASK)); - ch_x_reg->mcde_ch_tvbalw = ((ch_x_reg->mcde_ch_tvbalw & ~MCDE_ALW_MASK) | ((lcd_horizontal_timing.hfp << MCDE_ALW_SHIFT) & MCDE_ALW_MASK)); - ch_x_reg->mcde_ch_tvbalw = ((ch_x_reg->mcde_ch_tvbalw & ~MCDE_LBW_MASK) | (lcd_horizontal_timing.hsw & MCDE_LBW_MASK)); - - return(error); -} -mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing) -{ - mcde_error error = MCDE_OK; - struct mcde_ch_reg *ch_x_reg; - - if (MCDE_CH_B < (u32) chid) - { - return(MCDE_INVALID_PARAMETER); - } - else - { - ch_x_reg = (struct mcde_ch_reg *) (gpar[chid]->ch_regbase2[chid]); - } - - ch_x_reg->mcde_ch_tvbl1 = ((ch_x_reg->mcde_ch_tvbl1 & ~MCDE_BSL_MASK) | ((lcd_vertical_timing.vfp << MCDE_BSL_SHIFT) & MCDE_BSL_MASK)); - ch_x_reg->mcde_ch_tvbl1 = ((ch_x_reg->mcde_ch_tvbl1 & ~MCDE_BEL_MASK) | (lcd_vertical_timing.vsw & MCDE_BEL_MASK)); - ch_x_reg->mcde_ch_tvdvo = ((ch_x_reg->mcde_ch_tvdvo & ~MCDE_DVO1_MASK) | (lcd_vertical_timing.vbp & MCDE_DVO1_MASK)); - - return(error); -} -#ifdef PLATFORM_8820 - -mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp) -{ - mcde_error error = MCDE_OK; - - switch (chid) - { - case CHANNEL_A: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_A_MSB << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - } - break; - case CHANNEL_B: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - gpar[chid]->regbase->mcde_cr = ((gpar[chid]->regbase->mcde_cr & ~MCDE_CFG_OUTMUX3_MASK) | (((u32)MCDE_CH_B_MSB << MCDE_CFG_OUTMUX3_SHIFT)& MCDE_CFG_OUTMUX3_MASK)); - } - break; - default: - ; - } - return(error); -} -#else -mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp) -{ - mcde_error error = MCDE_OK; - - switch (chid) - { - case CHANNEL_A: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_A_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_A_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_A_MSB << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - } - break; - case CHANNEL_B: - if (outbpp == MCDE_BPP_1_TO_8) - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - - else if (outbpp == MCDE_BPP_16) - { - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX1_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX1_SHIFT)& MCDE_CFG_OUTMUX1_MASK)); - } - else if (outbpp == MCDE_BPP_24) - { - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX0_MASK) | (((u32)MCDE_CH_B_LSB << MCDE_CFG_OUTMUX0_SHIFT)& MCDE_CFG_OUTMUX0_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX2_MASK) | (((u32)MCDE_CH_B_MID << MCDE_CFG_OUTMUX2_SHIFT)& MCDE_CFG_OUTMUX2_MASK)); - gpar[chid]->regbase->mcde_cfg0 = ((gpar[chid]->regbase->mcde_cfg0 & ~MCDE_CFG_OUTMUX3_MASK) | (((u32)MCDE_CH_B_MSB << MCDE_CFG_OUTMUX3_SHIFT)& MCDE_CFG_OUTMUX3_MASK)); - } - break; - case CHANNEL_C0: - gpar[chid]->regbase->mcde_cfg0 |= 0x5000;//0x5e145000; /** This code needs to be modified */ - break; - case CHANNEL_C1: - gpar[chid]->regbase->mcde_cfg0 |= 0x5e145000; /** This code needs to be modified */ - break; - default: - ; - } - return(error); -} -#endif -mcde_error mcderesetextsrcovrlay(mcde_ch_id chid) -{ - struct mcde_ext_src_reg *ext_src; - struct mcde_ovl_reg *ovr_config; - mcde_error retVal = MCDE_OK; - - /** point to the correct ext src register */ - ext_src = (struct mcde_ext_src_reg *) (gpar[chid]->extsrc_regbase[gpar[chid]->mcde_cur_ovl_bmp]); - - /** reset ext src address registers, src conf register and src ctrl register to default value */ - ext_src->mcde_extsrc_a0 = 0x0; - ext_src->mcde_extsrc_a1 = 0x0; - ext_src->mcde_extsrc_a2 = 0x0; - ext_src->mcde_extsrc_conf = 0xA04; - ext_src->mcde_extsrc_cr = 0x0; - - /** point to the correct overlay register */ - ovr_config = (struct mcde_ovl_reg *) (gpar[chid]->ovl_regbase[gpar[chid]->mcde_cur_ovl_bmp]); - - /** reset overlay conf and overlay control register to default values...this also disables overlay */ - ovr_config->mcde_ovl_conf = 0x0; - ovr_config->mcde_ovl_conf2 = 0x00200001; - ovr_config->mcde_ovl_ljinc = 0x0; - ovr_config->mcde_ovl_cr = 0x22B00000; - - return retVal; -} - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ diff --git a/drivers/video/mcde/mcde_mod.c b/drivers/video/mcde/mcde_mod.c new file mode 100644 index 00000000000..ed5d1d3e958 --- /dev/null +++ b/drivers/video/mcde/mcde_mod.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) ST-Ericsson AB 2010 + * + * ST-Ericsson MCDE driver + * + * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com> + * for ST-Ericsson. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/init.h> +#include <linux/module.h> + +#include <video/mcde.h> +#include <video/mcde_fb.h> +#include <video/mcde_dss.h> +#include <video/mcde_display.h> + +/* Module init */ + +static int __init mcde_subsystem_init(void) +{ + int ret; + pr_debug("MCDE subsystem init begin\n"); + + /* MCDE module init sequence */ + ret = mcde_init(); + if (ret) + goto mcde_failed; + ret = mcde_display_init(); + if (ret) + goto mcde_display_failed; + ret = mcde_dss_init(); + if (ret) + goto mcde_dss_failed; + ret = mcde_fb_init(); + if (ret) + goto mcde_fb_failed; + pr_info("MCDE subsystem init done\n"); + + goto done; +mcde_fb_failed: + mcde_dss_exit(); +mcde_dss_failed: + mcde_display_exit(); +mcde_display_failed: + mcde_exit(); +mcde_failed: +done: + return ret; +} +#ifdef MODULE +module_init(mcde_subsystem_init); +#else +fs_initcall(mcde_subsystem_init); +#endif + +static void __exit mcde_module_exit(void) +{ + mcde_exit(); + mcde_display_exit(); + mcde_dss_exit(); +} +module_exit(mcde_module_exit); + +MODULE_AUTHOR("Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ST-Ericsson MCDE driver"); + diff --git a/drivers/video/mcde/mcde_regs.h b/drivers/video/mcde/mcde_regs.h new file mode 100644 index 00000000000..25e024b3806 --- /dev/null +++ b/drivers/video/mcde/mcde_regs.h @@ -0,0 +1,5085 @@ + +#define MCDE_VAL2REG(__reg, __fld, __val) \ + (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK) +#define MCDE_REG2VAL(__reg, __fld, __val) \ + (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT) + +#define MCDE_CR 0x00000000 +#define MCDE_CR_DSICMD2_EN_SHIFT 0 +#define MCDE_CR_DSICMD2_EN_MASK 0x00000001 +#define MCDE_CR_DSICMD2_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD2_EN, __x) +#define MCDE_CR_DSICMD1_EN_SHIFT 1 +#define MCDE_CR_DSICMD1_EN_MASK 0x00000002 +#define MCDE_CR_DSICMD1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD1_EN, __x) +#define MCDE_CR_DSICMD0_EN_SHIFT 2 +#define MCDE_CR_DSICMD0_EN_MASK 0x00000004 +#define MCDE_CR_DSICMD0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSICMD0_EN, __x) +#define MCDE_CR_DSIVID2_EN_SHIFT 3 +#define MCDE_CR_DSIVID2_EN_MASK 0x00000008 +#define MCDE_CR_DSIVID2_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID2_EN, __x) +#define MCDE_CR_DSIVID1_EN_SHIFT 4 +#define MCDE_CR_DSIVID1_EN_MASK 0x00000010 +#define MCDE_CR_DSIVID1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID1_EN, __x) +#define MCDE_CR_DSIVID0_EN_SHIFT 5 +#define MCDE_CR_DSIVID0_EN_MASK 0x00000020 +#define MCDE_CR_DSIVID0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DSIVID0_EN, __x) +#define MCDE_CR_DBIC1_EN_SHIFT 6 +#define MCDE_CR_DBIC1_EN_MASK 0x00000040 +#define MCDE_CR_DBIC1_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DBIC1_EN, __x) +#define MCDE_CR_DBIC0_EN_SHIFT 7 +#define MCDE_CR_DBIC0_EN_MASK 0x00000080 +#define MCDE_CR_DBIC0_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DBIC0_EN, __x) +#define MCDE_CR_DPIB_EN_SHIFT 8 +#define MCDE_CR_DPIB_EN_MASK 0x00000100 +#define MCDE_CR_DPIB_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DPIB_EN, __x) +#define MCDE_CR_DPIA_EN_SHIFT 9 +#define MCDE_CR_DPIA_EN_MASK 0x00000200 +#define MCDE_CR_DPIA_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, DPIA_EN, __x) +#define MCDE_CR_IFIFOCTRLEN_SHIFT 15 +#define MCDE_CR_IFIFOCTRLEN_MASK 0x00008000 +#define MCDE_CR_IFIFOCTRLEN(__x) \ + MCDE_VAL2REG(MCDE_CR, IFIFOCTRLEN, __x) +#define MCDE_CR_F01MUX_SHIFT 16 +#define MCDE_CR_F01MUX_MASK 0x00010000 +#define MCDE_CR_F01MUX(__x) \ + MCDE_VAL2REG(MCDE_CR, F01MUX, __x) +#define MCDE_CR_FABMUX_SHIFT 17 +#define MCDE_CR_FABMUX_MASK 0x00020000 +#define MCDE_CR_FABMUX(__x) \ + MCDE_VAL2REG(MCDE_CR, FABMUX, __x) +#define MCDE_CR_AUTOCLKG_EN_SHIFT 30 +#define MCDE_CR_AUTOCLKG_EN_MASK 0x40000000 +#define MCDE_CR_AUTOCLKG_EN(__x) \ + MCDE_VAL2REG(MCDE_CR, AUTOCLKG_EN, __x) +#define MCDE_CR_MCDEEN_SHIFT 31 +#define MCDE_CR_MCDEEN_MASK 0x80000000 +#define MCDE_CR_MCDEEN(__x) \ + MCDE_VAL2REG(MCDE_CR, MCDEEN, __x) +#define MCDE_CONF0 0x00000004 +#define MCDE_CONF0_SYNCMUX0_SHIFT 0 +#define MCDE_CONF0_SYNCMUX0_MASK 0x00000001 +#define MCDE_CONF0_SYNCMUX0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX0, __x) +#define MCDE_CONF0_SYNCMUX1_SHIFT 1 +#define MCDE_CONF0_SYNCMUX1_MASK 0x00000002 +#define MCDE_CONF0_SYNCMUX1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX1, __x) +#define MCDE_CONF0_SYNCMUX2_SHIFT 2 +#define MCDE_CONF0_SYNCMUX2_MASK 0x00000004 +#define MCDE_CONF0_SYNCMUX2(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX2, __x) +#define MCDE_CONF0_SYNCMUX3_SHIFT 3 +#define MCDE_CONF0_SYNCMUX3_MASK 0x00000008 +#define MCDE_CONF0_SYNCMUX3(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX3, __x) +#define MCDE_CONF0_SYNCMUX4_SHIFT 4 +#define MCDE_CONF0_SYNCMUX4_MASK 0x00000010 +#define MCDE_CONF0_SYNCMUX4(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX4, __x) +#define MCDE_CONF0_SYNCMUX5_SHIFT 5 +#define MCDE_CONF0_SYNCMUX5_MASK 0x00000020 +#define MCDE_CONF0_SYNCMUX5(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX5, __x) +#define MCDE_CONF0_SYNCMUX6_SHIFT 6 +#define MCDE_CONF0_SYNCMUX6_MASK 0x00000040 +#define MCDE_CONF0_SYNCMUX6(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX6, __x) +#define MCDE_CONF0_SYNCMUX7_SHIFT 7 +#define MCDE_CONF0_SYNCMUX7_MASK 0x00000080 +#define MCDE_CONF0_SYNCMUX7(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SYNCMUX7, __x) +#define MCDE_CONF0_SWAP_A_C0_SHIFT 8 +#define MCDE_CONF0_SWAP_A_C0_MASK 0x00000100 +#define MCDE_CONF0_SWAP_A_C0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SWAP_A_C0, __x) +#define MCDE_CONF0_SWAP_B_C1_SHIFT 9 +#define MCDE_CONF0_SWAP_B_C1_MASK 0x00000200 +#define MCDE_CONF0_SWAP_B_C1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, SWAP_B_C1, __x) +#define MCDE_CONF0_FSYNCTRLA_SHIFT 10 +#define MCDE_CONF0_FSYNCTRLA_MASK 0x00000400 +#define MCDE_CONF0_FSYNCTRLA(__x) \ + MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLA, __x) +#define MCDE_CONF0_FSYNCTRLB_SHIFT 11 +#define MCDE_CONF0_FSYNCTRLB_MASK 0x00000800 +#define MCDE_CONF0_FSYNCTRLB(__x) \ + MCDE_VAL2REG(MCDE_CONF0, FSYNCTRLB, __x) +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000 +#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL(__x) \ + MCDE_VAL2REG(MCDE_CONF0, IFIFOCTRLWTRMRKLVL, __x) +#define MCDE_CONF0_OUTMUX0_SHIFT 16 +#define MCDE_CONF0_OUTMUX0_MASK 0x00070000 +#define MCDE_CONF0_OUTMUX0(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX0, __x) +#define MCDE_CONF0_OUTMUX1_SHIFT 19 +#define MCDE_CONF0_OUTMUX1_MASK 0x00380000 +#define MCDE_CONF0_OUTMUX1(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX1, __x) +#define MCDE_CONF0_OUTMUX2_SHIFT 22 +#define MCDE_CONF0_OUTMUX2_MASK 0x01C00000 +#define MCDE_CONF0_OUTMUX2(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX2, __x) +#define MCDE_CONF0_OUTMUX3_SHIFT 25 +#define MCDE_CONF0_OUTMUX3_MASK 0x0E000000 +#define MCDE_CONF0_OUTMUX3(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX3, __x) +#define MCDE_CONF0_OUTMUX4_SHIFT 28 +#define MCDE_CONF0_OUTMUX4_MASK 0x70000000 +#define MCDE_CONF0_OUTMUX4(__x) \ + MCDE_VAL2REG(MCDE_CONF0, OUTMUX4, __x) +#define MCDE_SSP 0x00000008 +#define MCDE_SSP_SSPDATA_SHIFT 0 +#define MCDE_SSP_SSPDATA_MASK 0x000000FF +#define MCDE_SSP_SSPDATA(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPDATA, __x) +#define MCDE_SSP_SSPCMD_SHIFT 8 +#define MCDE_SSP_SSPCMD_MASK 0x00000100 +#define MCDE_SSP_SSPCMD_DATA 0 +#define MCDE_SSP_SSPCMD_COMMAND 1 +#define MCDE_SSP_SSPCMD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPCMD, MCDE_SSP_SSPCMD_##__x) +#define MCDE_SSP_SSPCMD(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPCMD, __x) +#define MCDE_SSP_SSPEN_SHIFT 16 +#define MCDE_SSP_SSPEN_MASK 0x00010000 +#define MCDE_SSP_SSPEN(__x) \ + MCDE_VAL2REG(MCDE_SSP, SSPEN, __x) +#define MCDE_AIS 0x00000100 +#define MCDE_AIS_MCDEPPI_SHIFT 0 +#define MCDE_AIS_MCDEPPI_MASK 0x00000001 +#define MCDE_AIS_MCDEPPI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEPPI, __x) +#define MCDE_AIS_MCDEOVLI_SHIFT 1 +#define MCDE_AIS_MCDEOVLI_MASK 0x00000002 +#define MCDE_AIS_MCDEOVLI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEOVLI, __x) +#define MCDE_AIS_MCDECHNLI_SHIFT 2 +#define MCDE_AIS_MCDECHNLI_MASK 0x00000004 +#define MCDE_AIS_MCDECHNLI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDECHNLI, __x) +#define MCDE_AIS_MCDEERRI_SHIFT 3 +#define MCDE_AIS_MCDEERRI_MASK 0x00000008 +#define MCDE_AIS_MCDEERRI(__x) \ + MCDE_VAL2REG(MCDE_AIS, MCDEERRI, __x) +#define MCDE_AIS_DSI0AI_SHIFT 4 +#define MCDE_AIS_DSI0AI_MASK 0x00000010 +#define MCDE_AIS_DSI0AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI0AI, __x) +#define MCDE_AIS_DSI1AI_SHIFT 5 +#define MCDE_AIS_DSI1AI_MASK 0x00000020 +#define MCDE_AIS_DSI1AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI1AI, __x) +#define MCDE_AIS_DSI2AI_SHIFT 6 +#define MCDE_AIS_DSI2AI_MASK 0x00000040 +#define MCDE_AIS_DSI2AI(__x) \ + MCDE_VAL2REG(MCDE_AIS, DSI2AI, __x) +#define MCDE_IMSCPP 0x00000104 +#define MCDE_IMSCPP_VCMPAIM_SHIFT 0 +#define MCDE_IMSCPP_VCMPAIM_MASK 0x00000001 +#define MCDE_IMSCPP_VCMPAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPAIM, __x) +#define MCDE_IMSCPP_VCMPBIM_SHIFT 1 +#define MCDE_IMSCPP_VCMPBIM_MASK 0x00000002 +#define MCDE_IMSCPP_VCMPBIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPBIM, __x) +#define MCDE_IMSCPP_VSCC0IM_SHIFT 2 +#define MCDE_IMSCPP_VSCC0IM_MASK 0x00000004 +#define MCDE_IMSCPP_VSCC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VSCC0IM, __x) +#define MCDE_IMSCPP_VSCC1IM_SHIFT 3 +#define MCDE_IMSCPP_VSCC1IM_MASK 0x00000008 +#define MCDE_IMSCPP_VSCC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VSCC1IM, __x) +#define MCDE_IMSCPP_VCMPC0IM_SHIFT 4 +#define MCDE_IMSCPP_VCMPC0IM_MASK 0x00000010 +#define MCDE_IMSCPP_VCMPC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPC0IM, __x) +#define MCDE_IMSCPP_VCMPC1IM_SHIFT 5 +#define MCDE_IMSCPP_VCMPC1IM_MASK 0x00000020 +#define MCDE_IMSCPP_VCMPC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, VCMPC1IM, __x) +#define MCDE_IMSCPP_ROTFDIM_B_SHIFT 6 +#define MCDE_IMSCPP_ROTFDIM_B_MASK 0x00000040 +#define MCDE_IMSCPP_ROTFDIM_B(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, ROTFDIM_B, __x) +#define MCDE_IMSCPP_ROTFDIM_A_SHIFT 7 +#define MCDE_IMSCPP_ROTFDIM_A_MASK 0x00000080 +#define MCDE_IMSCPP_ROTFDIM_A(__x) \ + MCDE_VAL2REG(MCDE_IMSCPP, ROTFDIM_A, __x) +#define MCDE_IMSCOVL 0x00000108 +#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0 +#define MCDE_IMSCOVL_OVLRDIM_MASK 0x0000FFFF +#define MCDE_IMSCOVL_OVLRDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCOVL, OVLRDIM, __x) +#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16 +#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF0000 +#define MCDE_IMSCOVL_OVLFDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCOVL, OVLFDIM, __x) +#define MCDE_IMSCCHNL 0x0000010C +#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0 +#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0x0000FFFF +#define MCDE_IMSCCHNL_CHNLRDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCCHNL, CHNLRDIM, __x) +#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16 +#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF0000 +#define MCDE_IMSCCHNL_CHNLAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCCHNL, CHNLAIM, __x) +#define MCDE_IMSCERR 0x00000110 +#define MCDE_IMSCERR_FUAIM_SHIFT 0 +#define MCDE_IMSCERR_FUAIM_MASK 0x00000001 +#define MCDE_IMSCERR_FUAIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUAIM, __x) +#define MCDE_IMSCERR_FUBIM_SHIFT 1 +#define MCDE_IMSCERR_FUBIM_MASK 0x00000002 +#define MCDE_IMSCERR_FUBIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUBIM, __x) +#define MCDE_IMSCERR_SCHBLCKDIM_SHIFT 2 +#define MCDE_IMSCERR_SCHBLCKDIM_MASK 0x00000004 +#define MCDE_IMSCERR_SCHBLCKDIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, SCHBLCKDIM, __x) +#define MCDE_IMSCERR_ROTAFEIM_WRITE_SHIFT 3 +#define MCDE_IMSCERR_ROTAFEIM_WRITE_MASK 0x00000008 +#define MCDE_IMSCERR_ROTAFEIM_WRITE(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTAFEIM_WRITE, __x) +#define MCDE_IMSCERR_ROTAFEIM_READ_SHIFT 4 +#define MCDE_IMSCERR_ROTAFEIM_READ_MASK 0x00000010 +#define MCDE_IMSCERR_ROTAFEIM_READ(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTAFEIM_READ, __x) +#define MCDE_IMSCERR_ROTBFEIM_WRITE_SHIFT 5 +#define MCDE_IMSCERR_ROTBFEIM_WRITE_MASK 0x00000020 +#define MCDE_IMSCERR_ROTBFEIM_WRITE(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTBFEIM_WRITE, __x) +#define MCDE_IMSCERR_ROTBFEIM_READ_SHIFT 6 +#define MCDE_IMSCERR_ROTBFEIM_READ_MASK 0x00000040 +#define MCDE_IMSCERR_ROTBFEIM_READ(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, ROTBFEIM_READ, __x) +#define MCDE_IMSCERR_FUC0IM_SHIFT 7 +#define MCDE_IMSCERR_FUC0IM_MASK 0x00000080 +#define MCDE_IMSCERR_FUC0IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUC0IM, __x) +#define MCDE_IMSCERR_FUC1IM_SHIFT 8 +#define MCDE_IMSCERR_FUC1IM_MASK 0x00000100 +#define MCDE_IMSCERR_FUC1IM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, FUC1IM, __x) +#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16 +#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF0000 +#define MCDE_IMSCERR_OVLFERRIM(__x) \ + MCDE_VAL2REG(MCDE_IMSCERR, OVLFERRIM, __x) +#define MCDE_RISPP 0x00000114 +#define MCDE_RISPP_VCMPARIS_SHIFT 0 +#define MCDE_RISPP_VCMPARIS_MASK 0x00000001 +#define MCDE_RISPP_VCMPARIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPARIS, __x) +#define MCDE_RISPP_VCMPBRIS_SHIFT 1 +#define MCDE_RISPP_VCMPBRIS_MASK 0x00000002 +#define MCDE_RISPP_VCMPBRIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPBRIS, __x) +#define MCDE_RISPP_VSCC0RIS_SHIFT 2 +#define MCDE_RISPP_VSCC0RIS_MASK 0x00000004 +#define MCDE_RISPP_VSCC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VSCC0RIS, __x) +#define MCDE_RISPP_VSCC1RIS_SHIFT 3 +#define MCDE_RISPP_VSCC1RIS_MASK 0x00000008 +#define MCDE_RISPP_VSCC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VSCC1RIS, __x) +#define MCDE_RISPP_VCMPC0RIS_SHIFT 4 +#define MCDE_RISPP_VCMPC0RIS_MASK 0x00000010 +#define MCDE_RISPP_VCMPC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPC0RIS, __x) +#define MCDE_RISPP_VCMPC1RIS_SHIFT 5 +#define MCDE_RISPP_VCMPC1RIS_MASK 0x00000020 +#define MCDE_RISPP_VCMPC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISPP, VCMPC1RIS, __x) +#define MCDE_RISPP_ROTFDRIS_B_SHIFT 6 +#define MCDE_RISPP_ROTFDRIS_B_MASK 0x00000040 +#define MCDE_RISPP_ROTFDRIS_B(__x) \ + MCDE_VAL2REG(MCDE_RISPP, ROTFDRIS_B, __x) +#define MCDE_RISPP_ROTFDRIS_A_SHIFT 7 +#define MCDE_RISPP_ROTFDRIS_A_MASK 0x00000080 +#define MCDE_RISPP_ROTFDRIS_A(__x) \ + MCDE_VAL2REG(MCDE_RISPP, ROTFDRIS_A, __x) +#define MCDE_RISOVL 0x00000118 +#define MCDE_RISOVL_OVLRDRIS_SHIFT 0 +#define MCDE_RISOVL_OVLRDRIS_MASK 0x0000FFFF +#define MCDE_RISOVL_OVLRDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISOVL, OVLRDRIS, __x) +#define MCDE_RISOVL_OVLFDRIS_SHIFT 16 +#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF0000 +#define MCDE_RISOVL_OVLFDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISOVL, OVLFDRIS, __x) +#define MCDE_RISCHNL 0x0000011C +#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0 +#define MCDE_RISCHNL_CHNLRDRIS_MASK 0x0000FFFF +#define MCDE_RISCHNL_CHNLRDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISCHNL, CHNLRDRIS, __x) +#define MCDE_RISCHNL_CHNLARIS_SHIFT 16 +#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF0000 +#define MCDE_RISCHNL_CHNLARIS(__x) \ + MCDE_VAL2REG(MCDE_RISCHNL, CHNLARIS, __x) +#define MCDE_RISERR 0x00000120 +#define MCDE_RISERR_FUARIS_SHIFT 0 +#define MCDE_RISERR_FUARIS_MASK 0x00000001 +#define MCDE_RISERR_FUARIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUARIS, __x) +#define MCDE_RISERR_FUBRIS_SHIFT 1 +#define MCDE_RISERR_FUBRIS_MASK 0x00000002 +#define MCDE_RISERR_FUBRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUBRIS, __x) +#define MCDE_RISERR_SCHBLCKDRIS_SHIFT 2 +#define MCDE_RISERR_SCHBLCKDRIS_MASK 0x00000004 +#define MCDE_RISERR_SCHBLCKDRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, SCHBLCKDRIS, __x) +#define MCDE_RISERR_ROTAFERIS_WRITE_SHIFT 3 +#define MCDE_RISERR_ROTAFERIS_WRITE_MASK 0x00000008 +#define MCDE_RISERR_ROTAFERIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTAFERIS_WRITE, __x) +#define MCDE_RISERR_ROTAFERIS_READ_SHIFT 4 +#define MCDE_RISERR_ROTAFERIS_READ_MASK 0x00000010 +#define MCDE_RISERR_ROTAFERIS_READ(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTAFERIS_READ, __x) +#define MCDE_RISERR_ROTBFERIS_WRITE_SHIFT 5 +#define MCDE_RISERR_ROTBFERIS_WRITE_MASK 0x00000020 +#define MCDE_RISERR_ROTBFERIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTBFERIS_WRITE, __x) +#define MCDE_RISERR_ROTBFERIS_READ_SHIFT 6 +#define MCDE_RISERR_ROTBFERIS_READ_MASK 0x00000040 +#define MCDE_RISERR_ROTBFERIS_READ(__x) \ + MCDE_VAL2REG(MCDE_RISERR, ROTBFERIS_READ, __x) +#define MCDE_RISERR_FUC0RIS_SHIFT 7 +#define MCDE_RISERR_FUC0RIS_MASK 0x00000080 +#define MCDE_RISERR_FUC0RIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUC0RIS, __x) +#define MCDE_RISERR_FUC1RIS_SHIFT 8 +#define MCDE_RISERR_FUC1RIS_MASK 0x00000100 +#define MCDE_RISERR_FUC1RIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, FUC1RIS, __x) +#define MCDE_RISERR_OVLFERRRIS_SHIFT 16 +#define MCDE_RISERR_OVLFERRRIS_MASK 0xFFFF0000 +#define MCDE_RISERR_OVLFERRRIS(__x) \ + MCDE_VAL2REG(MCDE_RISERR, OVLFERRRIS, __x) +#define MCDE_MISPP 0x00000124 +#define MCDE_MISPP_VCMPAMIS_SHIFT 0 +#define MCDE_MISPP_VCMPAMIS_MASK 0x00000001 +#define MCDE_MISPP_VCMPAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPAMIS, __x) +#define MCDE_MISPP_VCMPBMIS_SHIFT 1 +#define MCDE_MISPP_VCMPBMIS_MASK 0x00000002 +#define MCDE_MISPP_VCMPBMIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPBMIS, __x) +#define MCDE_MISPP_VSCC0MIS_SHIFT 2 +#define MCDE_MISPP_VSCC0MIS_MASK 0x00000004 +#define MCDE_MISPP_VSCC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VSCC0MIS, __x) +#define MCDE_MISPP_VSCC1MIS_SHIFT 3 +#define MCDE_MISPP_VSCC1MIS_MASK 0x00000008 +#define MCDE_MISPP_VSCC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VSCC1MIS, __x) +#define MCDE_MISPP_VCMPC0MIS_SHIFT 4 +#define MCDE_MISPP_VCMPC0MIS_MASK 0x00000010 +#define MCDE_MISPP_VCMPC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPC0MIS, __x) +#define MCDE_MISPP_VCMPC1MIS_SHIFT 5 +#define MCDE_MISPP_VCMPC1MIS_MASK 0x00000020 +#define MCDE_MISPP_VCMPC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISPP, VCMPC1MIS, __x) +#define MCDE_MISPP_ROTFDMIS_A_SHIFT 6 +#define MCDE_MISPP_ROTFDMIS_A_MASK 0x00000040 +#define MCDE_MISPP_ROTFDMIS_A(__x) \ + MCDE_VAL2REG(MCDE_MISPP, ROTFDMIS_A, __x) +#define MCDE_MISPP_ROTFDMIS_B_SHIFT 7 +#define MCDE_MISPP_ROTFDMIS_B_MASK 0x00000080 +#define MCDE_MISPP_ROTFDMIS_B(__x) \ + MCDE_VAL2REG(MCDE_MISPP, ROTFDMIS_B, __x) +#define MCDE_MISOVL 0x00000128 +#define MCDE_MISOVL_OVLRDMIS_SHIFT 0 +#define MCDE_MISOVL_OVLRDMIS_MASK 0x0000FFFF +#define MCDE_MISOVL_OVLRDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISOVL, OVLRDMIS, __x) +#define MCDE_MISOVL_OVLFDMIS_SHIFT 16 +#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF0000 +#define MCDE_MISOVL_OVLFDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISOVL, OVLFDMIS, __x) +#define MCDE_MISCHNL 0x0000012C +#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0 +#define MCDE_MISCHNL_CHNLRDMIS_MASK 0x0000FFFF +#define MCDE_MISCHNL_CHNLRDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISCHNL, CHNLRDMIS, __x) +#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16 +#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF0000 +#define MCDE_MISCHNL_CHNLAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISCHNL, CHNLAMIS, __x) +#define MCDE_MISERR 0x00000130 +#define MCDE_MISERR_FUAMIS_SHIFT 0 +#define MCDE_MISERR_FUAMIS_MASK 0x00000001 +#define MCDE_MISERR_FUAMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUAMIS, __x) +#define MCDE_MISERR_FUBMIS_SHIFT 1 +#define MCDE_MISERR_FUBMIS_MASK 0x00000002 +#define MCDE_MISERR_FUBMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUBMIS, __x) +#define MCDE_MISERR_SCHBLCKDMIS_SHIFT 2 +#define MCDE_MISERR_SCHBLCKDMIS_MASK 0x00000004 +#define MCDE_MISERR_SCHBLCKDMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, SCHBLCKDMIS, __x) +#define MCDE_MISERR_ROTAFEMIS_WRITE_SHIFT 3 +#define MCDE_MISERR_ROTAFEMIS_WRITE_MASK 0x00000008 +#define MCDE_MISERR_ROTAFEMIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTAFEMIS_WRITE, __x) +#define MCDE_MISERR_ROTAFEMIS_READ_SHIFT 4 +#define MCDE_MISERR_ROTAFEMIS_READ_MASK 0x00000010 +#define MCDE_MISERR_ROTAFEMIS_READ(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTAFEMIS_READ, __x) +#define MCDE_MISERR_ROTBFEMIS_WRITE_SHIFT 5 +#define MCDE_MISERR_ROTBFEMIS_WRITE_MASK 0x00000020 +#define MCDE_MISERR_ROTBFEMIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTBFEMIS_WRITE, __x) +#define MCDE_MISERR_ROTBFEMIS_READ_SHIFT 6 +#define MCDE_MISERR_ROTBFEMIS_READ_MASK 0x00000040 +#define MCDE_MISERR_ROTBFEMIS_READ(__x) \ + MCDE_VAL2REG(MCDE_MISERR, ROTBFEMIS_READ, __x) +#define MCDE_MISERR_FUC0MIS_SHIFT 7 +#define MCDE_MISERR_FUC0MIS_MASK 0x00000080 +#define MCDE_MISERR_FUC0MIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUC0MIS, __x) +#define MCDE_MISERR_FUC1MIS_SHIFT 8 +#define MCDE_MISERR_FUC1MIS_MASK 0x00000100 +#define MCDE_MISERR_FUC1MIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, FUC1MIS, __x) +#define MCDE_MISERR_OVLFERMIS_SHIFT 16 +#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF0000 +#define MCDE_MISERR_OVLFERMIS(__x) \ + MCDE_VAL2REG(MCDE_MISERR, OVLFERMIS, __x) +#define MCDE_SISPP 0x00000134 +#define MCDE_SISPP_VCMPASIS_SHIFT 0 +#define MCDE_SISPP_VCMPASIS_MASK 0x00000001 +#define MCDE_SISPP_VCMPASIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPASIS, __x) +#define MCDE_SISPP_VCMPBSIS_SHIFT 1 +#define MCDE_SISPP_VCMPBSIS_MASK 0x00000002 +#define MCDE_SISPP_VCMPBSIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPBSIS, __x) +#define MCDE_SISPP_VSCC0SIS_SHIFT 2 +#define MCDE_SISPP_VSCC0SIS_MASK 0x00000004 +#define MCDE_SISPP_VSCC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VSCC0SIS, __x) +#define MCDE_SISPP_VSCC1SIS_SHIFT 3 +#define MCDE_SISPP_VSCC1SIS_MASK 0x00000008 +#define MCDE_SISPP_VSCC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VSCC1SIS, __x) +#define MCDE_SISPP_VCMPC0SIS_SHIFT 4 +#define MCDE_SISPP_VCMPC0SIS_MASK 0x00000010 +#define MCDE_SISPP_VCMPC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPC0SIS, __x) +#define MCDE_SISPP_VCMPC1SIS_SHIFT 5 +#define MCDE_SISPP_VCMPC1SIS_MASK 0x00000020 +#define MCDE_SISPP_VCMPC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISPP, VCMPC1SIS, __x) +#define MCDE_SISPP_ROTFDSIS_A_SHIFT 6 +#define MCDE_SISPP_ROTFDSIS_A_MASK 0x00000040 +#define MCDE_SISPP_ROTFDSIS_A(__x) \ + MCDE_VAL2REG(MCDE_SISPP, ROTFDSIS_A, __x) +#define MCDE_SISPP_ROTFDSIS_B_SHIFT 7 +#define MCDE_SISPP_ROTFDSIS_B_MASK 0x00000080 +#define MCDE_SISPP_ROTFDSIS_B(__x) \ + MCDE_VAL2REG(MCDE_SISPP, ROTFDSIS_B, __x) +#define MCDE_SISOVL 0x00000138 +#define MCDE_SISOVL_OVLRDSIS_SHIFT 0 +#define MCDE_SISOVL_OVLRDSIS_MASK 0x0000FFFF +#define MCDE_SISOVL_OVLRDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISOVL, OVLRDSIS, __x) +#define MCDE_SISOVL_OVLFDSIS_SHIFT 16 +#define MCDE_SISOVL_OVLFDSIS_MASK 0xFFFF0000 +#define MCDE_SISOVL_OVLFDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISOVL, OVLFDSIS, __x) +#define MCDE_SISCHNL 0x0000013C +#define MCDE_SISCHNL_CHNLRDSIS_SHIFT 0 +#define MCDE_SISCHNL_CHNLRDSIS_MASK 0x0000FFFF +#define MCDE_SISCHNL_CHNLRDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISCHNL, CHNLRDSIS, __x) +#define MCDE_SISCHNL_CHNLASIS_SHIFT 16 +#define MCDE_SISCHNL_CHNLASIS_MASK 0xFFFF0000 +#define MCDE_SISCHNL_CHNLASIS(__x) \ + MCDE_VAL2REG(MCDE_SISCHNL, CHNLASIS, __x) +#define MCDE_SISERR 0x00000140 +#define MCDE_SISERR_FUASIS_SHIFT 0 +#define MCDE_SISERR_FUASIS_MASK 0x00000001 +#define MCDE_SISERR_FUASIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUASIS, __x) +#define MCDE_SISERR_FUBSIS_SHIFT 1 +#define MCDE_SISERR_FUBSIS_MASK 0x00000002 +#define MCDE_SISERR_FUBSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUBSIS, __x) +#define MCDE_SISERR_SCHBLCKDSIS_SHIFT 2 +#define MCDE_SISERR_SCHBLCKDSIS_MASK 0x00000004 +#define MCDE_SISERR_SCHBLCKDSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, SCHBLCKDSIS, __x) +#define MCDE_SISERR_ROTAFESIS_WRITE_SHIFT 3 +#define MCDE_SISERR_ROTAFESIS_WRITE_MASK 0x00000008 +#define MCDE_SISERR_ROTAFESIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTAFESIS_WRITE, __x) +#define MCDE_SISERR_ROTAFESIS_READ_SHIFT 4 +#define MCDE_SISERR_ROTAFESIS_READ_MASK 0x00000010 +#define MCDE_SISERR_ROTAFESIS_READ(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTAFESIS_READ, __x) +#define MCDE_SISERR_ROTBFESIS_WRITE_SHIFT 5 +#define MCDE_SISERR_ROTBFESIS_WRITE_MASK 0x00000020 +#define MCDE_SISERR_ROTBFESIS_WRITE(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTBFESIS_WRITE, __x) +#define MCDE_SISERR_ROTBFESIS_READ_SHIFT 6 +#define MCDE_SISERR_ROTBFESIS_READ_MASK 0x00000040 +#define MCDE_SISERR_ROTBFESIS_READ(__x) \ + MCDE_VAL2REG(MCDE_SISERR, ROTBFESIS_READ, __x) +#define MCDE_SISERR_FUC0SIS_SHIFT 7 +#define MCDE_SISERR_FUC0SIS_MASK 0x00000080 +#define MCDE_SISERR_FUC0SIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUC0SIS, __x) +#define MCDE_SISERR_FUC1SIS_SHIFT 8 +#define MCDE_SISERR_FUC1SIS_MASK 0x00000100 +#define MCDE_SISERR_FUC1SIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, FUC1SIS, __x) +#define MCDE_SISERR_OVLFERSIS_SHIFT 16 +#define MCDE_SISERR_OVLFERSIS_MASK 0xFFFF0000 +#define MCDE_SISERR_OVLFERSIS(__x) \ + MCDE_VAL2REG(MCDE_SISERR, OVLFERSIS, __x) +#define MCDE_PID 0x000001FC +#define MCDE_PID_METALFIX_VERSION_SHIFT 0 +#define MCDE_PID_METALFIX_VERSION_MASK 0x000000FF +#define MCDE_PID_METALFIX_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, METALFIX_VERSION, __x) +#define MCDE_PID_DEVELOPMENT_VERSION_SHIFT 8 +#define MCDE_PID_DEVELOPMENT_VERSION_MASK 0x0000FF00 +#define MCDE_PID_DEVELOPMENT_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, DEVELOPMENT_VERSION, __x) +#define MCDE_PID_MINOR_VERSION_SHIFT 16 +#define MCDE_PID_MINOR_VERSION_MASK 0x00FF0000 +#define MCDE_PID_MINOR_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, MINOR_VERSION, __x) +#define MCDE_PID_MAJOR_VERSION_SHIFT 24 +#define MCDE_PID_MAJOR_VERSION_MASK 0xFF000000 +#define MCDE_PID_MAJOR_VERSION(__x) \ + MCDE_VAL2REG(MCDE_PID, MAJOR_VERSION, __x) +#define MCDE_EXTSRC0A0 0x00000200 +#define MCDE_EXTSRC0A0_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC0A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC0A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC1A0 0x00000220 +#define MCDE_EXTSRC1A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC1A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC1A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC2A0 0x00000240 +#define MCDE_EXTSRC2A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC2A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC2A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC3A0 0x00000260 +#define MCDE_EXTSRC3A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC3A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC3A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC4A0 0x00000280 +#define MCDE_EXTSRC4A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC4A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC4A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC5A0 0x000002A0 +#define MCDE_EXTSRC5A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC5A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC5A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC6A0 0x000002C0 +#define MCDE_EXTSRC6A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC6A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC7A0 0x000002E0 +#define MCDE_EXTSRC7A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC7A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC7A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC8A0 0x00000300 +#define MCDE_EXTSRC8A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC8A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC8A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC9A0 0x00000320 +#define MCDE_EXTSRC9A0_BASEADDRESS0_SHIFT 0 +#define MCDE_EXTSRC9A0_BASEADDRESS0_MASK 0xFFFFFFFF +#define MCDE_EXTSRC9A0_BASEADDRESS0(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9A0, BASEADDRESS0, __x) +#define MCDE_EXTSRC0A1 0x00000204 +#define MCDE_EXTSRC0A1_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC0A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC0A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC1A1 0x00000224 +#define MCDE_EXTSRC1A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC1A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC1A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC2A1 0x00000244 +#define MCDE_EXTSRC2A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC2A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC2A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC3A1 0x00000264 +#define MCDE_EXTSRC3A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC3A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC3A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC4A1 0x00000284 +#define MCDE_EXTSRC4A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC4A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC4A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC5A1 0x000002A4 +#define MCDE_EXTSRC5A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC5A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC5A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC6A1 0x000002C4 +#define MCDE_EXTSRC6A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC6A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC7A1 0x000002E4 +#define MCDE_EXTSRC7A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC7A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC7A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC8A1 0x00000304 +#define MCDE_EXTSRC8A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC8A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC8A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC9A1 0x00000324 +#define MCDE_EXTSRC9A1_BASEADDRESS1_SHIFT 0 +#define MCDE_EXTSRC9A1_BASEADDRESS1_MASK 0xFFFFFFFF +#define MCDE_EXTSRC9A1_BASEADDRESS1(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9A1, BASEADDRESS1, __x) +#define MCDE_EXTSRC6A2 0x000002C8 +#define MCDE_EXTSRC6A2_BASEADDRESS2_SHIFT 0 +#define MCDE_EXTSRC6A2_BASEADDRESS2_MASK 0xFFFFFFFF +#define MCDE_EXTSRC6A2_BASEADDRESS2(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6A2, BASEADDRESS2, __x) +#define MCDE_EXTSRC0CONF 0x0000020C +#define MCDE_EXTSRC0CONF_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC0CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC0CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BUF_ID, __x) +#define MCDE_EXTSRC0CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC0CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC0CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BUF_NB, __x) +#define MCDE_EXTSRC0CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC0CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC0CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC0CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC0CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC0CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC0CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC0CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC0CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC0CONF_BPP_RGB444 4 +#define MCDE_EXTSRC0CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC0CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC0CONF_BPP_RGB565 7 +#define MCDE_EXTSRC0CONF_BPP_RGB888 1 +#define MCDE_EXTSRC0CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC0CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC0CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC0CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BPP, MCDE_EXTSRC0CONF_BPP_##__x) +#define MCDE_EXTSRC0CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BPP, __x) +#define MCDE_EXTSRC0CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC0CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC0CONF_BGR_RGB 0 +#define MCDE_EXTSRC0CONF_BGR_BGR 1 +#define MCDE_EXTSRC0CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BGR, MCDE_EXTSRC0CONF_BGR_##__x) +#define MCDE_EXTSRC0CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BGR, __x) +#define MCDE_EXTSRC0CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC0CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC0CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC0CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC0CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEBO, MCDE_EXTSRC0CONF_BEBO_##__x) +#define MCDE_EXTSRC0CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEBO, __x) +#define MCDE_EXTSRC0CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC0CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC0CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC0CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC0CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEPO, MCDE_EXTSRC0CONF_BEPO_##__x) +#define MCDE_EXTSRC0CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CONF, BEPO, __x) +#define MCDE_EXTSRC1CONF 0x0000022C +#define MCDE_EXTSRC1CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC1CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC1CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BUF_ID, __x) +#define MCDE_EXTSRC1CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC1CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC1CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BUF_NB, __x) +#define MCDE_EXTSRC1CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC1CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC1CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC1CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC1CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC1CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC1CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC1CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC1CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC1CONF_BPP_RGB444 4 +#define MCDE_EXTSRC1CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC1CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC1CONF_BPP_RGB565 7 +#define MCDE_EXTSRC1CONF_BPP_RGB888 1 +#define MCDE_EXTSRC1CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC1CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC1CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC1CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BPP, MCDE_EXTSRC1CONF_BPP_##__x) +#define MCDE_EXTSRC1CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BPP, __x) +#define MCDE_EXTSRC1CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC1CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC1CONF_BGR_RGB 0 +#define MCDE_EXTSRC1CONF_BGR_BGR 1 +#define MCDE_EXTSRC1CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BGR, MCDE_EXTSRC1CONF_BGR_##__x) +#define MCDE_EXTSRC1CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BGR, __x) +#define MCDE_EXTSRC1CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC1CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC1CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC1CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC1CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEBO, MCDE_EXTSRC1CONF_BEBO_##__x) +#define MCDE_EXTSRC1CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEBO, __x) +#define MCDE_EXTSRC1CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC1CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC1CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC1CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC1CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEPO, MCDE_EXTSRC1CONF_BEPO_##__x) +#define MCDE_EXTSRC1CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CONF, BEPO, __x) +#define MCDE_EXTSRC2CONF 0x0000024C +#define MCDE_EXTSRC2CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC2CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC2CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BUF_ID, __x) +#define MCDE_EXTSRC2CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC2CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC2CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BUF_NB, __x) +#define MCDE_EXTSRC2CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC2CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC2CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC2CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC2CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC2CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC2CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC2CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC2CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC2CONF_BPP_RGB444 4 +#define MCDE_EXTSRC2CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC2CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC2CONF_BPP_RGB565 7 +#define MCDE_EXTSRC2CONF_BPP_RGB888 1 +#define MCDE_EXTSRC2CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC2CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC2CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC2CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BPP, MCDE_EXTSRC2CONF_BPP_##__x) +#define MCDE_EXTSRC2CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BPP, __x) +#define MCDE_EXTSRC2CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC2CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC2CONF_BGR_RGB 0 +#define MCDE_EXTSRC2CONF_BGR_BGR 1 +#define MCDE_EXTSRC2CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BGR, MCDE_EXTSRC2CONF_BGR_##__x) +#define MCDE_EXTSRC2CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BGR, __x) +#define MCDE_EXTSRC2CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC2CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC2CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC2CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC2CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEBO, MCDE_EXTSRC2CONF_BEBO_##__x) +#define MCDE_EXTSRC2CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEBO, __x) +#define MCDE_EXTSRC2CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC2CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC2CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC2CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC2CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEPO, MCDE_EXTSRC2CONF_BEPO_##__x) +#define MCDE_EXTSRC2CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CONF, BEPO, __x) +#define MCDE_EXTSRC3CONF 0x0000026C +#define MCDE_EXTSRC3CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC3CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC3CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BUF_ID, __x) +#define MCDE_EXTSRC3CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC3CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC3CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BUF_NB, __x) +#define MCDE_EXTSRC3CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC3CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC3CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC3CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC3CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC3CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC3CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC3CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC3CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC3CONF_BPP_RGB444 4 +#define MCDE_EXTSRC3CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC3CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC3CONF_BPP_RGB565 7 +#define MCDE_EXTSRC3CONF_BPP_RGB888 1 +#define MCDE_EXTSRC3CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC3CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC3CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC3CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BPP, MCDE_EXTSRC3CONF_BPP_##__x) +#define MCDE_EXTSRC3CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BPP, __x) +#define MCDE_EXTSRC3CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC3CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC3CONF_BGR_RGB 0 +#define MCDE_EXTSRC3CONF_BGR_BGR 1 +#define MCDE_EXTSRC3CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BGR, MCDE_EXTSRC3CONF_BGR_##__x) +#define MCDE_EXTSRC3CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BGR, __x) +#define MCDE_EXTSRC3CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC3CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC3CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC3CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC3CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEBO, MCDE_EXTSRC3CONF_BEBO_##__x) +#define MCDE_EXTSRC3CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEBO, __x) +#define MCDE_EXTSRC3CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC3CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC3CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC3CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC3CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEPO, MCDE_EXTSRC3CONF_BEPO_##__x) +#define MCDE_EXTSRC3CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CONF, BEPO, __x) +#define MCDE_EXTSRC4CONF 0x0000028C +#define MCDE_EXTSRC4CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC4CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC4CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BUF_ID, __x) +#define MCDE_EXTSRC4CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC4CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC4CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BUF_NB, __x) +#define MCDE_EXTSRC4CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC4CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC4CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC4CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC4CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC4CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC4CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC4CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC4CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC4CONF_BPP_RGB444 4 +#define MCDE_EXTSRC4CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC4CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC4CONF_BPP_RGB565 7 +#define MCDE_EXTSRC4CONF_BPP_RGB888 1 +#define MCDE_EXTSRC4CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC4CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC4CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC4CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BPP, MCDE_EXTSRC4CONF_BPP_##__x) +#define MCDE_EXTSRC4CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BPP, __x) +#define MCDE_EXTSRC4CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC4CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC4CONF_BGR_RGB 0 +#define MCDE_EXTSRC4CONF_BGR_BGR 1 +#define MCDE_EXTSRC4CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BGR, MCDE_EXTSRC4CONF_BGR_##__x) +#define MCDE_EXTSRC4CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BGR, __x) +#define MCDE_EXTSRC4CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC4CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC4CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC4CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC4CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEBO, MCDE_EXTSRC4CONF_BEBO_##__x) +#define MCDE_EXTSRC4CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEBO, __x) +#define MCDE_EXTSRC4CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC4CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC4CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC4CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC4CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEPO, MCDE_EXTSRC4CONF_BEPO_##__x) +#define MCDE_EXTSRC4CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CONF, BEPO, __x) +#define MCDE_EXTSRC5CONF 0x000002AC +#define MCDE_EXTSRC5CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC5CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC5CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BUF_ID, __x) +#define MCDE_EXTSRC5CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC5CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC5CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BUF_NB, __x) +#define MCDE_EXTSRC5CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC5CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC5CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC5CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC5CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC5CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC5CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC5CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC5CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC5CONF_BPP_RGB444 4 +#define MCDE_EXTSRC5CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC5CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC5CONF_BPP_RGB565 7 +#define MCDE_EXTSRC5CONF_BPP_RGB888 1 +#define MCDE_EXTSRC5CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC5CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC5CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC5CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BPP, MCDE_EXTSRC5CONF_BPP_##__x) +#define MCDE_EXTSRC5CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BPP, __x) +#define MCDE_EXTSRC5CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC5CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC5CONF_BGR_RGB 0 +#define MCDE_EXTSRC5CONF_BGR_BGR 1 +#define MCDE_EXTSRC5CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BGR, MCDE_EXTSRC5CONF_BGR_##__x) +#define MCDE_EXTSRC5CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BGR, __x) +#define MCDE_EXTSRC5CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC5CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC5CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC5CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC5CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEBO, MCDE_EXTSRC5CONF_BEBO_##__x) +#define MCDE_EXTSRC5CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEBO, __x) +#define MCDE_EXTSRC5CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC5CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC5CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC5CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC5CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEPO, MCDE_EXTSRC5CONF_BEPO_##__x) +#define MCDE_EXTSRC5CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CONF, BEPO, __x) +#define MCDE_EXTSRC6CONF 0x000002CC +#define MCDE_EXTSRC6CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC6CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC6CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BUF_ID, __x) +#define MCDE_EXTSRC6CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC6CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC6CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BUF_NB, __x) +#define MCDE_EXTSRC6CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC6CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC6CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC6CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC6CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC6CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC6CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC6CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC6CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC6CONF_BPP_RGB444 4 +#define MCDE_EXTSRC6CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC6CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC6CONF_BPP_RGB565 7 +#define MCDE_EXTSRC6CONF_BPP_RGB888 1 +#define MCDE_EXTSRC6CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC6CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC6CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC6CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BPP, MCDE_EXTSRC6CONF_BPP_##__x) +#define MCDE_EXTSRC6CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BPP, __x) +#define MCDE_EXTSRC6CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC6CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC6CONF_BGR_RGB 0 +#define MCDE_EXTSRC6CONF_BGR_BGR 1 +#define MCDE_EXTSRC6CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BGR, MCDE_EXTSRC6CONF_BGR_##__x) +#define MCDE_EXTSRC6CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BGR, __x) +#define MCDE_EXTSRC6CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC6CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC6CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC6CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC6CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEBO, MCDE_EXTSRC6CONF_BEBO_##__x) +#define MCDE_EXTSRC6CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEBO, __x) +#define MCDE_EXTSRC6CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC6CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC6CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC6CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC6CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEPO, MCDE_EXTSRC6CONF_BEPO_##__x) +#define MCDE_EXTSRC6CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CONF, BEPO, __x) +#define MCDE_EXTSRC7CONF 0x000002EC +#define MCDE_EXTSRC7CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC7CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC7CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BUF_ID, __x) +#define MCDE_EXTSRC7CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC7CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC7CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BUF_NB, __x) +#define MCDE_EXTSRC7CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC7CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC7CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC7CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC7CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC7CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC7CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC7CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC7CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC7CONF_BPP_RGB444 4 +#define MCDE_EXTSRC7CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC7CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC7CONF_BPP_RGB565 7 +#define MCDE_EXTSRC7CONF_BPP_RGB888 1 +#define MCDE_EXTSRC7CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC7CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC7CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC7CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BPP, MCDE_EXTSRC7CONF_BPP_##__x) +#define MCDE_EXTSRC7CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BPP, __x) +#define MCDE_EXTSRC7CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC7CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC7CONF_BGR_RGB 0 +#define MCDE_EXTSRC7CONF_BGR_BGR 1 +#define MCDE_EXTSRC7CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BGR, MCDE_EXTSRC7CONF_BGR_##__x) +#define MCDE_EXTSRC7CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BGR, __x) +#define MCDE_EXTSRC7CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC7CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC7CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC7CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC7CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEBO, MCDE_EXTSRC7CONF_BEBO_##__x) +#define MCDE_EXTSRC7CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEBO, __x) +#define MCDE_EXTSRC7CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC7CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC7CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC7CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC7CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEPO, MCDE_EXTSRC7CONF_BEPO_##__x) +#define MCDE_EXTSRC7CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CONF, BEPO, __x) +#define MCDE_EXTSRC8CONF 0x0000030C +#define MCDE_EXTSRC8CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC8CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC8CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BUF_ID, __x) +#define MCDE_EXTSRC8CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC8CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC8CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BUF_NB, __x) +#define MCDE_EXTSRC8CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC8CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC8CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC8CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC8CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC8CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC8CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC8CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC8CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC8CONF_BPP_RGB444 4 +#define MCDE_EXTSRC8CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC8CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC8CONF_BPP_RGB565 7 +#define MCDE_EXTSRC8CONF_BPP_RGB888 1 +#define MCDE_EXTSRC8CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC8CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC8CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC8CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BPP, MCDE_EXTSRC8CONF_BPP_##__x) +#define MCDE_EXTSRC8CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BPP, __x) +#define MCDE_EXTSRC8CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC8CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC8CONF_BGR_RGB 0 +#define MCDE_EXTSRC8CONF_BGR_BGR 1 +#define MCDE_EXTSRC8CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BGR, MCDE_EXTSRC8CONF_BGR_##__x) +#define MCDE_EXTSRC8CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BGR, __x) +#define MCDE_EXTSRC8CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC8CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC8CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC8CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC8CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEBO, MCDE_EXTSRC8CONF_BEBO_##__x) +#define MCDE_EXTSRC8CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEBO, __x) +#define MCDE_EXTSRC8CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC8CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC8CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC8CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC8CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEPO, MCDE_EXTSRC8CONF_BEPO_##__x) +#define MCDE_EXTSRC8CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CONF, BEPO, __x) +#define MCDE_EXTSRC9CONF 0x0000032C +#define MCDE_EXTSRC9CONF_BUF_ID_SHIFT 0 +#define MCDE_EXTSRC9CONF_BUF_ID_MASK 0x00000003 +#define MCDE_EXTSRC9CONF_BUF_ID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BUF_ID, __x) +#define MCDE_EXTSRC9CONF_BUF_NB_SHIFT 2 +#define MCDE_EXTSRC9CONF_BUF_NB_MASK 0x0000000C +#define MCDE_EXTSRC9CONF_BUF_NB(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BUF_NB, __x) +#define MCDE_EXTSRC9CONF_PRI_OVLID_SHIFT 4 +#define MCDE_EXTSRC9CONF_PRI_OVLID_MASK 0x000000F0 +#define MCDE_EXTSRC9CONF_PRI_OVLID(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, PRI_OVLID, __x) +#define MCDE_EXTSRC9CONF_BPP_SHIFT 8 +#define MCDE_EXTSRC9CONF_BPP_MASK 0x00000F00 +#define MCDE_EXTSRC9CONF_BPP_1BPP_PAL 0 +#define MCDE_EXTSRC9CONF_BPP_2BPP_PAL 1 +#define MCDE_EXTSRC9CONF_BPP_4BPP_PAL 2 +#define MCDE_EXTSRC9CONF_BPP_8BPP_PAL 3 +#define MCDE_EXTSRC9CONF_BPP_RGB444 4 +#define MCDE_EXTSRC9CONF_BPP_ARGB4444 5 +#define MCDE_EXTSRC9CONF_BPP_IRGB1555 6 +#define MCDE_EXTSRC9CONF_BPP_RGB565 7 +#define MCDE_EXTSRC9CONF_BPP_RGB888 1 +#define MCDE_EXTSRC9CONF_BPP_XRGB8888 9 +#define MCDE_EXTSRC9CONF_BPP_ARGB8888 10 +#define MCDE_EXTSRC9CONF_BPP_YCBCR422 11 +#define MCDE_EXTSRC9CONF_BPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BPP, MCDE_EXTSRC9CONF_BPP_##__x) +#define MCDE_EXTSRC9CONF_BPP(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BPP, __x) +#define MCDE_EXTSRC9CONF_BGR_SHIFT 12 +#define MCDE_EXTSRC9CONF_BGR_MASK 0x00001000 +#define MCDE_EXTSRC9CONF_BGR_RGB 0 +#define MCDE_EXTSRC9CONF_BGR_BGR 1 +#define MCDE_EXTSRC9CONF_BGR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BGR, MCDE_EXTSRC9CONF_BGR_##__x) +#define MCDE_EXTSRC9CONF_BGR(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BGR, __x) +#define MCDE_EXTSRC9CONF_BEBO_SHIFT 13 +#define MCDE_EXTSRC9CONF_BEBO_MASK 0x00002000 +#define MCDE_EXTSRC9CONF_BEBO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC9CONF_BEBO_BIG_ENDIAN 1 +#define MCDE_EXTSRC9CONF_BEBO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEBO, MCDE_EXTSRC9CONF_BEBO_##__x) +#define MCDE_EXTSRC9CONF_BEBO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEBO, __x) +#define MCDE_EXTSRC9CONF_BEPO_SHIFT 14 +#define MCDE_EXTSRC9CONF_BEPO_MASK 0x00004000 +#define MCDE_EXTSRC9CONF_BEPO_LITTLE_ENDIAN 0 +#define MCDE_EXTSRC9CONF_BEPO_BIG_ENDIAN 1 +#define MCDE_EXTSRC9CONF_BEPO_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEPO, MCDE_EXTSRC9CONF_BEPO_##__x) +#define MCDE_EXTSRC9CONF_BEPO(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CONF, BEPO, __x) +#define MCDE_EXTSRC0CR 0x00000210 +#define MCDE_EXTSRC0CR_GROUPOFFSET 0x20 +#define MCDE_EXTSRC0CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC0CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC0CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC0CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC0CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC0CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, SEL_MOD, MCDE_EXTSRC0CR_SEL_MOD_##__x) +#define MCDE_EXTSRC0CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, SEL_MOD, __x) +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC0CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC0CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC0CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC0CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC0CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC0CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC0CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC1CR 0x00000230 +#define MCDE_EXTSRC1CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC1CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC1CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC1CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC1CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC1CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, SEL_MOD, MCDE_EXTSRC1CR_SEL_MOD_##__x) +#define MCDE_EXTSRC1CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, SEL_MOD, __x) +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC1CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC1CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC1CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC1CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC1CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC1CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC1CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC2CR 0x00000250 +#define MCDE_EXTSRC2CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC2CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC2CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC2CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC2CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC2CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, SEL_MOD, MCDE_EXTSRC2CR_SEL_MOD_##__x) +#define MCDE_EXTSRC2CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, SEL_MOD, __x) +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC2CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC2CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC2CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC2CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC2CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC2CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC2CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC3CR 0x00000270 +#define MCDE_EXTSRC3CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC3CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC3CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC3CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC3CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC3CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, SEL_MOD, MCDE_EXTSRC3CR_SEL_MOD_##__x) +#define MCDE_EXTSRC3CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, SEL_MOD, __x) +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC3CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC3CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC3CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC3CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC3CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC3CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC3CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC4CR 0x00000290 +#define MCDE_EXTSRC4CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC4CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC4CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC4CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC4CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC4CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, SEL_MOD, MCDE_EXTSRC4CR_SEL_MOD_##__x) +#define MCDE_EXTSRC4CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, SEL_MOD, __x) +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC4CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC4CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC4CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC4CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC4CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC4CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC4CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC5CR 0x000002B0 +#define MCDE_EXTSRC5CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC5CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC5CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC5CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC5CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC5CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, SEL_MOD, MCDE_EXTSRC5CR_SEL_MOD_##__x) +#define MCDE_EXTSRC5CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, SEL_MOD, __x) +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC5CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC5CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC5CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC5CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC5CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC5CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC5CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC6CR 0x000002D0 +#define MCDE_EXTSRC6CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC6CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC6CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC6CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC6CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC6CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, SEL_MOD, MCDE_EXTSRC6CR_SEL_MOD_##__x) +#define MCDE_EXTSRC6CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, SEL_MOD, __x) +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC6CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC6CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC6CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC6CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC6CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC6CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC6CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC7CR 0x000002F0 +#define MCDE_EXTSRC7CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC7CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC7CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC7CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC7CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC7CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, SEL_MOD, MCDE_EXTSRC7CR_SEL_MOD_##__x) +#define MCDE_EXTSRC7CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, SEL_MOD, __x) +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC7CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC7CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC7CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC7CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC7CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC7CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC7CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC8CR 0x00000310 +#define MCDE_EXTSRC8CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC8CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC8CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC8CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC8CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC8CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, SEL_MOD, MCDE_EXTSRC8CR_SEL_MOD_##__x) +#define MCDE_EXTSRC8CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, SEL_MOD, __x) +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC8CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC8CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC8CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC8CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC8CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC8CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC8CR, FORCE_FS_DIV, __x) +#define MCDE_EXTSRC9CR 0x00000330 +#define MCDE_EXTSRC9CR_SEL_MOD_SHIFT 0 +#define MCDE_EXTSRC9CR_SEL_MOD_MASK 0x00000003 +#define MCDE_EXTSRC9CR_SEL_MOD_EXTERNAL_SEL 0 +#define MCDE_EXTSRC9CR_SEL_MOD_AUTO_TOGGLE 1 +#define MCDE_EXTSRC9CR_SEL_MOD_SOFTWARE_SEL 2 +#define MCDE_EXTSRC9CR_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, SEL_MOD, MCDE_EXTSRC9CR_SEL_MOD_##__x) +#define MCDE_EXTSRC9CR_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, SEL_MOD, __x) +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_SHIFT 2 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_MASK 0x00000004 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_ALL 0 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_PRIMARY 1 +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, MULTIOVL_CTRL, \ + MCDE_EXTSRC9CR_MULTIOVL_CTRL_##__x) +#define MCDE_EXTSRC9CR_MULTIOVL_CTRL(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, MULTIOVL_CTRL, __x) +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE_SHIFT 3 +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE_MASK 0x00000008 +#define MCDE_EXTSRC9CR_FS_DIV_DISABLE(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, FS_DIV_DISABLE, __x) +#define MCDE_EXTSRC9CR_FORCE_FS_DIV_SHIFT 4 +#define MCDE_EXTSRC9CR_FORCE_FS_DIV_MASK 0x00000010 +#define MCDE_EXTSRC9CR_FORCE_FS_DIV(__x) \ + MCDE_VAL2REG(MCDE_EXTSRC9CR, FORCE_FS_DIV, __x) +#define MCDE_OVL0CR 0x00000400 +#define MCDE_OVL0CR_GROUPOFFSET 0x20 +#define MCDE_OVL0CR_OVLEN_SHIFT 0 +#define MCDE_OVL0CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL0CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLEN, __x) +#define MCDE_OVL0CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL0CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL0CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL0CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL0CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL0CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, COLCCTRL, MCDE_OVL0CR_COLCCTRL_##__x) +#define MCDE_OVL0CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, COLCCTRL, __x) +#define MCDE_OVL0CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL0CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL0CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, CKEYGEN, __x) +#define MCDE_OVL0CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL0CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL0CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, ALPHAPMEN, __x) +#define MCDE_OVL0CR_OVLF_SHIFT 5 +#define MCDE_OVL0CR_OVLF_MASK 0x00000020 +#define MCDE_OVL0CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLF, __x) +#define MCDE_OVL0CR_OVLR_SHIFT 6 +#define MCDE_OVL0CR_OVLR_MASK 0x00000040 +#define MCDE_OVL0CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLR, __x) +#define MCDE_OVL0CR_OVLB_SHIFT 7 +#define MCDE_OVL0CR_OVLB_MASK 0x00000080 +#define MCDE_OVL0CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, OVLB, __x) +#define MCDE_OVL0CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL0CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL0CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, FETCH_ROPC, __x) +#define MCDE_OVL0CR_STBPRIO_SHIFT 16 +#define MCDE_OVL0CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL0CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, STBPRIO, __x) +#define MCDE_OVL0CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL0CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL0CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, BURSTSIZE, __x) +#define MCDE_OVL0CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL0CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL0CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, MAXOUTSTANDING, __x) +#define MCDE_OVL0CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL0CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL0CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CR, ROTBURSTSIZE, __x) +#define MCDE_OVL1CR 0x00000420 +#define MCDE_OVL1CR_OVLEN_SHIFT 0 +#define MCDE_OVL1CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL1CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLEN, __x) +#define MCDE_OVL1CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL1CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL1CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL1CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL1CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL1CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, COLCCTRL, MCDE_OVL1CR_COLCCTRL_##__x) +#define MCDE_OVL1CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, COLCCTRL, __x) +#define MCDE_OVL1CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL1CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL1CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, CKEYGEN, __x) +#define MCDE_OVL1CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL1CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL1CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, ALPHAPMEN, __x) +#define MCDE_OVL1CR_OVLF_SHIFT 5 +#define MCDE_OVL1CR_OVLF_MASK 0x00000020 +#define MCDE_OVL1CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLF, __x) +#define MCDE_OVL1CR_OVLR_SHIFT 6 +#define MCDE_OVL1CR_OVLR_MASK 0x00000040 +#define MCDE_OVL1CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLR, __x) +#define MCDE_OVL1CR_OVLB_SHIFT 7 +#define MCDE_OVL1CR_OVLB_MASK 0x00000080 +#define MCDE_OVL1CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, OVLB, __x) +#define MCDE_OVL1CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL1CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL1CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, FETCH_ROPC, __x) +#define MCDE_OVL1CR_STBPRIO_SHIFT 16 +#define MCDE_OVL1CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL1CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, STBPRIO, __x) +#define MCDE_OVL1CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL1CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL1CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, BURSTSIZE, __x) +#define MCDE_OVL1CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL1CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL1CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, MAXOUTSTANDING, __x) +#define MCDE_OVL1CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL1CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL1CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CR, ROTBURSTSIZE, __x) +#define MCDE_OVL2CR 0x00000440 +#define MCDE_OVL2CR_OVLEN_SHIFT 0 +#define MCDE_OVL2CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL2CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLEN, __x) +#define MCDE_OVL2CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL2CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL2CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL2CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL2CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL2CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, COLCCTRL, MCDE_OVL2CR_COLCCTRL_##__x) +#define MCDE_OVL2CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, COLCCTRL, __x) +#define MCDE_OVL2CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL2CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL2CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, CKEYGEN, __x) +#define MCDE_OVL2CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL2CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL2CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, ALPHAPMEN, __x) +#define MCDE_OVL2CR_OVLF_SHIFT 5 +#define MCDE_OVL2CR_OVLF_MASK 0x00000020 +#define MCDE_OVL2CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLF, __x) +#define MCDE_OVL2CR_OVLR_SHIFT 6 +#define MCDE_OVL2CR_OVLR_MASK 0x00000040 +#define MCDE_OVL2CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLR, __x) +#define MCDE_OVL2CR_OVLB_SHIFT 7 +#define MCDE_OVL2CR_OVLB_MASK 0x00000080 +#define MCDE_OVL2CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, OVLB, __x) +#define MCDE_OVL2CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL2CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL2CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, FETCH_ROPC, __x) +#define MCDE_OVL2CR_STBPRIO_SHIFT 16 +#define MCDE_OVL2CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL2CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, STBPRIO, __x) +#define MCDE_OVL2CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL2CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL2CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, BURSTSIZE, __x) +#define MCDE_OVL2CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL2CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL2CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, MAXOUTSTANDING, __x) +#define MCDE_OVL2CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL2CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL2CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CR, ROTBURSTSIZE, __x) +#define MCDE_OVL3CR 0x00000460 +#define MCDE_OVL3CR_OVLEN_SHIFT 0 +#define MCDE_OVL3CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL3CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLEN, __x) +#define MCDE_OVL3CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL3CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL3CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL3CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL3CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL3CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, COLCCTRL, MCDE_OVL3CR_COLCCTRL_##__x) +#define MCDE_OVL3CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, COLCCTRL, __x) +#define MCDE_OVL3CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL3CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL3CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, CKEYGEN, __x) +#define MCDE_OVL3CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL3CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL3CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, ALPHAPMEN, __x) +#define MCDE_OVL3CR_OVLF_SHIFT 5 +#define MCDE_OVL3CR_OVLF_MASK 0x00000020 +#define MCDE_OVL3CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLF, __x) +#define MCDE_OVL3CR_OVLR_SHIFT 6 +#define MCDE_OVL3CR_OVLR_MASK 0x00000040 +#define MCDE_OVL3CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLR, __x) +#define MCDE_OVL3CR_OVLB_SHIFT 7 +#define MCDE_OVL3CR_OVLB_MASK 0x00000080 +#define MCDE_OVL3CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, OVLB, __x) +#define MCDE_OVL3CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL3CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL3CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, FETCH_ROPC, __x) +#define MCDE_OVL3CR_STBPRIO_SHIFT 16 +#define MCDE_OVL3CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL3CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, STBPRIO, __x) +#define MCDE_OVL3CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL3CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL3CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, BURSTSIZE, __x) +#define MCDE_OVL3CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL3CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL3CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, MAXOUTSTANDING, __x) +#define MCDE_OVL3CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL3CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL3CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CR, ROTBURSTSIZE, __x) +#define MCDE_OVL4CR 0x00000480 +#define MCDE_OVL4CR_OVLEN_SHIFT 0 +#define MCDE_OVL4CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL4CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLEN, __x) +#define MCDE_OVL4CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL4CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL4CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL4CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL4CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL4CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, COLCCTRL, MCDE_OVL4CR_COLCCTRL_##__x) +#define MCDE_OVL4CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, COLCCTRL, __x) +#define MCDE_OVL4CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL4CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL4CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, CKEYGEN, __x) +#define MCDE_OVL4CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL4CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL4CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, ALPHAPMEN, __x) +#define MCDE_OVL4CR_OVLF_SHIFT 5 +#define MCDE_OVL4CR_OVLF_MASK 0x00000020 +#define MCDE_OVL4CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLF, __x) +#define MCDE_OVL4CR_OVLR_SHIFT 6 +#define MCDE_OVL4CR_OVLR_MASK 0x00000040 +#define MCDE_OVL4CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLR, __x) +#define MCDE_OVL4CR_OVLB_SHIFT 7 +#define MCDE_OVL4CR_OVLB_MASK 0x00000080 +#define MCDE_OVL4CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, OVLB, __x) +#define MCDE_OVL4CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL4CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL4CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, FETCH_ROPC, __x) +#define MCDE_OVL4CR_STBPRIO_SHIFT 16 +#define MCDE_OVL4CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL4CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, STBPRIO, __x) +#define MCDE_OVL4CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL4CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL4CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, BURSTSIZE, __x) +#define MCDE_OVL4CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL4CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL4CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, MAXOUTSTANDING, __x) +#define MCDE_OVL4CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL4CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL4CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CR, ROTBURSTSIZE, __x) +#define MCDE_OVL5CR 0x000004A0 +#define MCDE_OVL5CR_OVLEN_SHIFT 0 +#define MCDE_OVL5CR_OVLEN_MASK 0x00000001 +#define MCDE_OVL5CR_OVLEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLEN, __x) +#define MCDE_OVL5CR_COLCCTRL_SHIFT 1 +#define MCDE_OVL5CR_COLCCTRL_MASK 0x00000006 +#define MCDE_OVL5CR_COLCCTRL_DISABLED 0 +#define MCDE_OVL5CR_COLCCTRL_ENABLED_NO_SAT 1 +#define MCDE_OVL5CR_COLCCTRL_ENABLED_SAT 2 +#define MCDE_OVL5CR_COLCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, COLCCTRL, MCDE_OVL5CR_COLCCTRL_##__x) +#define MCDE_OVL5CR_COLCCTRL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, COLCCTRL, __x) +#define MCDE_OVL5CR_CKEYGEN_SHIFT 3 +#define MCDE_OVL5CR_CKEYGEN_MASK 0x00000008 +#define MCDE_OVL5CR_CKEYGEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, CKEYGEN, __x) +#define MCDE_OVL5CR_ALPHAPMEN_SHIFT 4 +#define MCDE_OVL5CR_ALPHAPMEN_MASK 0x00000010 +#define MCDE_OVL5CR_ALPHAPMEN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, ALPHAPMEN, __x) +#define MCDE_OVL5CR_OVLF_SHIFT 5 +#define MCDE_OVL5CR_OVLF_MASK 0x00000020 +#define MCDE_OVL5CR_OVLF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLF, __x) +#define MCDE_OVL5CR_OVLR_SHIFT 6 +#define MCDE_OVL5CR_OVLR_MASK 0x00000040 +#define MCDE_OVL5CR_OVLR(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLR, __x) +#define MCDE_OVL5CR_OVLB_SHIFT 7 +#define MCDE_OVL5CR_OVLB_MASK 0x00000080 +#define MCDE_OVL5CR_OVLB(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, OVLB, __x) +#define MCDE_OVL5CR_FETCH_ROPC_SHIFT 8 +#define MCDE_OVL5CR_FETCH_ROPC_MASK 0x0000FF00 +#define MCDE_OVL5CR_FETCH_ROPC(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, FETCH_ROPC, __x) +#define MCDE_OVL5CR_STBPRIO_SHIFT 16 +#define MCDE_OVL5CR_STBPRIO_MASK 0x000F0000 +#define MCDE_OVL5CR_STBPRIO(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, STBPRIO, __x) +#define MCDE_OVL5CR_BURSTSIZE_SHIFT 20 +#define MCDE_OVL5CR_BURSTSIZE_MASK 0x00F00000 +#define MCDE_OVL5CR_BURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, BURSTSIZE, __x) +#define MCDE_OVL5CR_MAXOUTSTANDING_SHIFT 24 +#define MCDE_OVL5CR_MAXOUTSTANDING_MASK 0x0F000000 +#define MCDE_OVL5CR_MAXOUTSTANDING(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, MAXOUTSTANDING, __x) +#define MCDE_OVL5CR_ROTBURSTSIZE_SHIFT 28 +#define MCDE_OVL5CR_ROTBURSTSIZE_MASK 0xF0000000 +#define MCDE_OVL5CR_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CR, ROTBURSTSIZE, __x) +#define MCDE_OVL0CONF 0x00000404 +#define MCDE_OVL0CONF_GROUPOFFSET 0x20 +#define MCDE_OVL0CONF_PPL_SHIFT 0 +#define MCDE_OVL0CONF_PPL_MASK 0x000007FF +#define MCDE_OVL0CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, PPL, __x) +#define MCDE_OVL0CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL0CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL0CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, EXTSRC_ID, __x) +#define MCDE_OVL0CONF_LPF_SHIFT 16 +#define MCDE_OVL0CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL0CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF, LPF, __x) +#define MCDE_OVL1CONF 0x00000424 +#define MCDE_OVL1CONF_PPL_SHIFT 0 +#define MCDE_OVL1CONF_PPL_MASK 0x000007FF +#define MCDE_OVL1CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, PPL, __x) +#define MCDE_OVL1CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL1CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL1CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, EXTSRC_ID, __x) +#define MCDE_OVL1CONF_LPF_SHIFT 16 +#define MCDE_OVL1CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL1CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF, LPF, __x) +#define MCDE_OVL2CONF 0x00000444 +#define MCDE_OVL2CONF_PPL_SHIFT 0 +#define MCDE_OVL2CONF_PPL_MASK 0x000007FF +#define MCDE_OVL2CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, PPL, __x) +#define MCDE_OVL2CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL2CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL2CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, EXTSRC_ID, __x) +#define MCDE_OVL2CONF_LPF_SHIFT 16 +#define MCDE_OVL2CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL2CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF, LPF, __x) +#define MCDE_OVL3CONF 0x00000464 +#define MCDE_OVL3CONF_PPL_SHIFT 0 +#define MCDE_OVL3CONF_PPL_MASK 0x000007FF +#define MCDE_OVL3CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, PPL, __x) +#define MCDE_OVL3CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL3CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL3CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, EXTSRC_ID, __x) +#define MCDE_OVL3CONF_LPF_SHIFT 16 +#define MCDE_OVL3CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL3CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF, LPF, __x) +#define MCDE_OVL4CONF 0x00000484 +#define MCDE_OVL4CONF_PPL_SHIFT 0 +#define MCDE_OVL4CONF_PPL_MASK 0x000007FF +#define MCDE_OVL4CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, PPL, __x) +#define MCDE_OVL4CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL4CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL4CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, EXTSRC_ID, __x) +#define MCDE_OVL4CONF_LPF_SHIFT 16 +#define MCDE_OVL4CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL4CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF, LPF, __x) +#define MCDE_OVL5CONF 0x000004A4 +#define MCDE_OVL5CONF_PPL_SHIFT 0 +#define MCDE_OVL5CONF_PPL_MASK 0x000007FF +#define MCDE_OVL5CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, PPL, __x) +#define MCDE_OVL5CONF_EXTSRC_ID_SHIFT 11 +#define MCDE_OVL5CONF_EXTSRC_ID_MASK 0x00007800 +#define MCDE_OVL5CONF_EXTSRC_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, EXTSRC_ID, __x) +#define MCDE_OVL5CONF_LPF_SHIFT 16 +#define MCDE_OVL5CONF_LPF_MASK 0x07FF0000 +#define MCDE_OVL5CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF, LPF, __x) +#define MCDE_OVL0CONF2 0x00000408 +#define MCDE_OVL0CONF2_GROUPOFFSET 0x20 +#define MCDE_OVL0CONF2_BP_SHIFT 0 +#define MCDE_OVL0CONF2_BP_MASK 0x00000001 +#define MCDE_OVL0CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL0CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL0CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, BP, MCDE_OVL0CONF2_BP_##__x) +#define MCDE_OVL0CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, BP, __x) +#define MCDE_OVL0CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL0CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL0CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, ALPHAVALUE, __x) +#define MCDE_OVL0CONF2_OPQ_SHIFT 9 +#define MCDE_OVL0CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL0CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, OPQ, __x) +#define MCDE_OVL0CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL0CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL0CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, PIXOFF, __x) +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL0CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL0CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL1CONF2 0x00000428 +#define MCDE_OVL1CONF2_BP_SHIFT 0 +#define MCDE_OVL1CONF2_BP_MASK 0x00000001 +#define MCDE_OVL1CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL1CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL1CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, BP, MCDE_OVL1CONF2_BP_##__x) +#define MCDE_OVL1CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, BP, __x) +#define MCDE_OVL1CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL1CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL1CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, ALPHAVALUE, __x) +#define MCDE_OVL1CONF2_OPQ_SHIFT 9 +#define MCDE_OVL1CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL1CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, OPQ, __x) +#define MCDE_OVL1CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL1CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL1CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, PIXOFF, __x) +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL1CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL1CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL2CONF2 0x00000448 +#define MCDE_OVL2CONF2_BP_SHIFT 0 +#define MCDE_OVL2CONF2_BP_MASK 0x00000001 +#define MCDE_OVL2CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL2CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL2CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, BP, MCDE_OVL2CONF2_BP_##__x) +#define MCDE_OVL2CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, BP, __x) +#define MCDE_OVL2CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL2CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL2CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, ALPHAVALUE, __x) +#define MCDE_OVL2CONF2_OPQ_SHIFT 9 +#define MCDE_OVL2CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL2CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, OPQ, __x) +#define MCDE_OVL2CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL2CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL2CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, PIXOFF, __x) +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL2CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL2CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL3CONF2 0x00000468 +#define MCDE_OVL3CONF2_BP_SHIFT 0 +#define MCDE_OVL3CONF2_BP_MASK 0x00000001 +#define MCDE_OVL3CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL3CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL3CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, BP, MCDE_OVL3CONF2_BP_##__x) +#define MCDE_OVL3CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, BP, __x) +#define MCDE_OVL3CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL3CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL3CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, ALPHAVALUE, __x) +#define MCDE_OVL3CONF2_OPQ_SHIFT 9 +#define MCDE_OVL3CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL3CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, OPQ, __x) +#define MCDE_OVL3CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL3CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL3CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, PIXOFF, __x) +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL3CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL3CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL4CONF2 0x00000488 +#define MCDE_OVL4CONF2_BP_SHIFT 0 +#define MCDE_OVL4CONF2_BP_MASK 0x00000001 +#define MCDE_OVL4CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL4CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL4CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, BP, MCDE_OVL4CONF2_BP_##__x) +#define MCDE_OVL4CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, BP, __x) +#define MCDE_OVL4CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL4CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL4CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, ALPHAVALUE, __x) +#define MCDE_OVL4CONF2_OPQ_SHIFT 9 +#define MCDE_OVL4CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL4CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, OPQ, __x) +#define MCDE_OVL4CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL4CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL4CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, PIXOFF, __x) +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL4CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL4CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL5CONF2 0x000004A8 +#define MCDE_OVL5CONF2_BP_SHIFT 0 +#define MCDE_OVL5CONF2_BP_MASK 0x00000001 +#define MCDE_OVL5CONF2_BP_PER_PIXEL_ALPHA 0 +#define MCDE_OVL5CONF2_BP_CONSTANT_ALPHA 1 +#define MCDE_OVL5CONF2_BP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, BP, MCDE_OVL5CONF2_BP_##__x) +#define MCDE_OVL5CONF2_BP(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, BP, __x) +#define MCDE_OVL5CONF2_ALPHAVALUE_SHIFT 1 +#define MCDE_OVL5CONF2_ALPHAVALUE_MASK 0x000001FE +#define MCDE_OVL5CONF2_ALPHAVALUE(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, ALPHAVALUE, __x) +#define MCDE_OVL5CONF2_OPQ_SHIFT 9 +#define MCDE_OVL5CONF2_OPQ_MASK 0x00000200 +#define MCDE_OVL5CONF2_OPQ(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, OPQ, __x) +#define MCDE_OVL5CONF2_PIXOFF_SHIFT 10 +#define MCDE_OVL5CONF2_PIXOFF_MASK 0x0000FC00 +#define MCDE_OVL5CONF2_PIXOFF(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, PIXOFF, __x) +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT 16 +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL_MASK 0x1FFF0000 +#define MCDE_OVL5CONF2_PIXELFETCHERWATERMARKLEVEL(__x) \ + MCDE_VAL2REG(MCDE_OVL5CONF2, PIXELFETCHERWATERMARKLEVEL, __x) +#define MCDE_OVL0LJINC 0x0000040C +#define MCDE_OVL0LJINC_GROUPOFFSET 0x20 +#define MCDE_OVL0LJINC_LJINC_SHIFT 0 +#define MCDE_OVL0LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL0LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL0LJINC, LJINC, __x) +#define MCDE_OVL1LJINC 0x0000042C +#define MCDE_OVL1LJINC_LJINC_SHIFT 0 +#define MCDE_OVL1LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL1LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL1LJINC, LJINC, __x) +#define MCDE_OVL2LJINC 0x0000044C +#define MCDE_OVL2LJINC_LJINC_SHIFT 0 +#define MCDE_OVL2LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL2LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL2LJINC, LJINC, __x) +#define MCDE_OVL3LJINC 0x0000046C +#define MCDE_OVL3LJINC_LJINC_SHIFT 0 +#define MCDE_OVL3LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL3LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL3LJINC, LJINC, __x) +#define MCDE_OVL4LJINC 0x0000048C +#define MCDE_OVL4LJINC_LJINC_SHIFT 0 +#define MCDE_OVL4LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL4LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL4LJINC, LJINC, __x) +#define MCDE_OVL5LJINC 0x000004AC +#define MCDE_OVL5LJINC_LJINC_SHIFT 0 +#define MCDE_OVL5LJINC_LJINC_MASK 0xFFFFFFFF +#define MCDE_OVL5LJINC_LJINC(__x) \ + MCDE_VAL2REG(MCDE_OVL5LJINC, LJINC, __x) +#define MCDE_OVL0CROP 0x00000410 +#define MCDE_OVL0CROP_GROUPOFFSET 0x20 +#define MCDE_OVL0CROP_TMRGN_SHIFT 0 +#define MCDE_OVL0CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL0CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CROP, TMRGN, __x) +#define MCDE_OVL0CROP_LMRGN_SHIFT 22 +#define MCDE_OVL0CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL0CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL0CROP, LMRGN, __x) +#define MCDE_OVL1CROP 0x00000430 +#define MCDE_OVL1CROP_TMRGN_SHIFT 0 +#define MCDE_OVL1CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL1CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CROP, TMRGN, __x) +#define MCDE_OVL1CROP_LMRGN_SHIFT 22 +#define MCDE_OVL1CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL1CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL1CROP, LMRGN, __x) +#define MCDE_OVL2CROP 0x00000450 +#define MCDE_OVL2CROP_TMRGN_SHIFT 0 +#define MCDE_OVL2CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL2CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CROP, TMRGN, __x) +#define MCDE_OVL2CROP_LMRGN_SHIFT 22 +#define MCDE_OVL2CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL2CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL2CROP, LMRGN, __x) +#define MCDE_OVL3CROP 0x00000470 +#define MCDE_OVL3CROP_TMRGN_SHIFT 0 +#define MCDE_OVL3CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL3CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CROP, TMRGN, __x) +#define MCDE_OVL3CROP_LMRGN_SHIFT 22 +#define MCDE_OVL3CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL3CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL3CROP, LMRGN, __x) +#define MCDE_OVL4CROP 0x00000490 +#define MCDE_OVL4CROP_TMRGN_SHIFT 0 +#define MCDE_OVL4CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL4CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CROP, TMRGN, __x) +#define MCDE_OVL4CROP_LMRGN_SHIFT 22 +#define MCDE_OVL4CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL4CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL4CROP, LMRGN, __x) +#define MCDE_OVL5CROP 0x000004B0 +#define MCDE_OVL5CROP_TMRGN_SHIFT 0 +#define MCDE_OVL5CROP_TMRGN_MASK 0x003FFFFF +#define MCDE_OVL5CROP_TMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CROP, TMRGN, __x) +#define MCDE_OVL5CROP_LMRGN_SHIFT 22 +#define MCDE_OVL5CROP_LMRGN_MASK 0xFFC00000 +#define MCDE_OVL5CROP_LMRGN(__x) \ + MCDE_VAL2REG(MCDE_OVL5CROP, LMRGN, __x) +#define MCDE_OVL0COMP 0x00000414 +#define MCDE_OVL0COMP_GROUPOFFSET 0x20 +#define MCDE_OVL0COMP_XPOS_SHIFT 0 +#define MCDE_OVL0COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL0COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, XPOS, __x) +#define MCDE_OVL0COMP_CH_ID_SHIFT 11 +#define MCDE_OVL0COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL0COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, CH_ID, __x) +#define MCDE_OVL0COMP_YPOS_SHIFT 16 +#define MCDE_OVL0COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL0COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, YPOS, __x) +#define MCDE_OVL0COMP_Z_SHIFT 27 +#define MCDE_OVL0COMP_Z_MASK 0x78000000 +#define MCDE_OVL0COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL0COMP, Z, __x) +#define MCDE_OVL1COMP 0x00000434 +#define MCDE_OVL1COMP_XPOS_SHIFT 0 +#define MCDE_OVL1COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL1COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, XPOS, __x) +#define MCDE_OVL1COMP_CH_ID_SHIFT 11 +#define MCDE_OVL1COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL1COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, CH_ID, __x) +#define MCDE_OVL1COMP_YPOS_SHIFT 16 +#define MCDE_OVL1COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL1COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, YPOS, __x) +#define MCDE_OVL1COMP_Z_SHIFT 27 +#define MCDE_OVL1COMP_Z_MASK 0x78000000 +#define MCDE_OVL1COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL1COMP, Z, __x) +#define MCDE_OVL2COMP 0x00000454 +#define MCDE_OVL2COMP_XPOS_SHIFT 0 +#define MCDE_OVL2COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL2COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, XPOS, __x) +#define MCDE_OVL2COMP_CH_ID_SHIFT 11 +#define MCDE_OVL2COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL2COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, CH_ID, __x) +#define MCDE_OVL2COMP_YPOS_SHIFT 16 +#define MCDE_OVL2COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL2COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, YPOS, __x) +#define MCDE_OVL2COMP_Z_SHIFT 27 +#define MCDE_OVL2COMP_Z_MASK 0x78000000 +#define MCDE_OVL2COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL2COMP, Z, __x) +#define MCDE_OVL3COMP 0x00000474 +#define MCDE_OVL3COMP_XPOS_SHIFT 0 +#define MCDE_OVL3COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL3COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, XPOS, __x) +#define MCDE_OVL3COMP_CH_ID_SHIFT 11 +#define MCDE_OVL3COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL3COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, CH_ID, __x) +#define MCDE_OVL3COMP_YPOS_SHIFT 16 +#define MCDE_OVL3COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL3COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, YPOS, __x) +#define MCDE_OVL3COMP_Z_SHIFT 27 +#define MCDE_OVL3COMP_Z_MASK 0x78000000 +#define MCDE_OVL3COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL3COMP, Z, __x) +#define MCDE_OVL4COMP 0x00000494 +#define MCDE_OVL4COMP_XPOS_SHIFT 0 +#define MCDE_OVL4COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL4COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, XPOS, __x) +#define MCDE_OVL4COMP_CH_ID_SHIFT 11 +#define MCDE_OVL4COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL4COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, CH_ID, __x) +#define MCDE_OVL4COMP_YPOS_SHIFT 16 +#define MCDE_OVL4COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL4COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, YPOS, __x) +#define MCDE_OVL4COMP_Z_SHIFT 27 +#define MCDE_OVL4COMP_Z_MASK 0x78000000 +#define MCDE_OVL4COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL4COMP, Z, __x) +#define MCDE_OVL5COMP 0x000004B4 +#define MCDE_OVL5COMP_XPOS_SHIFT 0 +#define MCDE_OVL5COMP_XPOS_MASK 0x000007FF +#define MCDE_OVL5COMP_XPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, XPOS, __x) +#define MCDE_OVL5COMP_CH_ID_SHIFT 11 +#define MCDE_OVL5COMP_CH_ID_MASK 0x00007800 +#define MCDE_OVL5COMP_CH_ID(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, CH_ID, __x) +#define MCDE_OVL5COMP_YPOS_SHIFT 16 +#define MCDE_OVL5COMP_YPOS_MASK 0x07FF0000 +#define MCDE_OVL5COMP_YPOS(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, YPOS, __x) +#define MCDE_OVL5COMP_Z_SHIFT 27 +#define MCDE_OVL5COMP_Z_MASK 0x78000000 +#define MCDE_OVL5COMP_Z(__x) \ + MCDE_VAL2REG(MCDE_OVL5COMP, Z, __x) +#define MCDE_CHNL0CONF 0x00000600 +#define MCDE_CHNL0CONF_GROUPOFFSET 0x20 +#define MCDE_CHNL0CONF_PPL_SHIFT 0 +#define MCDE_CHNL0CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL0CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL0CONF, PPL, __x) +#define MCDE_CHNL0CONF_LPF_SHIFT 16 +#define MCDE_CHNL0CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL0CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL0CONF, LPF, __x) +#define MCDE_CHNL1CONF 0x00000620 +#define MCDE_CHNL1CONF_PPL_SHIFT 0 +#define MCDE_CHNL1CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL1CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL1CONF, PPL, __x) +#define MCDE_CHNL1CONF_LPF_SHIFT 16 +#define MCDE_CHNL1CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL1CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL1CONF, LPF, __x) +#define MCDE_CHNL2CONF 0x00000640 +#define MCDE_CHNL2CONF_PPL_SHIFT 0 +#define MCDE_CHNL2CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL2CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL2CONF, PPL, __x) +#define MCDE_CHNL2CONF_LPF_SHIFT 16 +#define MCDE_CHNL2CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL2CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL2CONF, LPF, __x) +#define MCDE_CHNL3CONF 0x00000660 +#define MCDE_CHNL3CONF_PPL_SHIFT 0 +#define MCDE_CHNL3CONF_PPL_MASK 0x000007FF +#define MCDE_CHNL3CONF_PPL(__x) \ + MCDE_VAL2REG(MCDE_CHNL3CONF, PPL, __x) +#define MCDE_CHNL3CONF_LPF_SHIFT 16 +#define MCDE_CHNL3CONF_LPF_MASK 0x07FF0000 +#define MCDE_CHNL3CONF_LPF(__x) \ + MCDE_VAL2REG(MCDE_CHNL3CONF, LPF, __x) +#define MCDE_CHNL0STAT 0x00000604 +#define MCDE_CHNL0STAT_GROUPOFFSET 0x20 +#define MCDE_CHNL0STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL0STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL0STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLRD, __x) +#define MCDE_CHNL0STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL0STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL0STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLA, __x) +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL0STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL0STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL1STAT 0x00000624 +#define MCDE_CHNL1STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL1STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL1STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLRD, __x) +#define MCDE_CHNL1STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL1STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL1STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLA, __x) +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL1STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL1STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL2STAT 0x00000644 +#define MCDE_CHNL2STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL2STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL2STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLRD, __x) +#define MCDE_CHNL2STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL2STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL2STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLA, __x) +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL2STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL2STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL3STAT 0x00000664 +#define MCDE_CHNL3STAT_CHNLRD_SHIFT 0 +#define MCDE_CHNL3STAT_CHNLRD_MASK 0x00000001 +#define MCDE_CHNL3STAT_CHNLRD(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLRD, __x) +#define MCDE_CHNL3STAT_CHNLA_SHIFT 1 +#define MCDE_CHNL3STAT_CHNLA_MASK 0x00000002 +#define MCDE_CHNL3STAT_CHNLA(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLA, __x) +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN_SHIFT 16 +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN_MASK 0x00010000 +#define MCDE_CHNL3STAT_CHNLBLBCKGND_EN(__x) \ + MCDE_VAL2REG(MCDE_CHNL3STAT, CHNLBLBCKGND_EN, __x) +#define MCDE_CHNL0SYNCHMOD 0x00000608 +#define MCDE_CHNL0SYNCHMOD_GROUPOFFSET 0x20 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL0SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL1SYNCHMOD 0x00000628 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL1SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL1SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL1SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL2SYNCHMOD 0x00000648 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL2SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL2SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL2SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL3SYNCHMOD 0x00000668 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SHIFT 0 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_MASK 0x00000003 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_OUTPUT 0 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_AUTO 1 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_SOFTWARE 2 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_EXTERNAL 3 +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, SRC_SYNCH, \ + MCDE_CHNL3SYNCHMOD_SRC_SYNCH_##__x) +#define MCDE_CHNL3SYNCHMOD_SRC_SYNCH(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, SRC_SYNCH, __x) +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_MASK 0x0000001C +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_FORMATTER 0 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC0 1 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_VSYNC1 2 +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, OUT_SYNCH_SRC, \ + MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC_##__x) +#define MCDE_CHNL3SYNCHMOD_OUT_SYNCH_SRC(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHMOD, OUT_SYNCH_SRC, __x) +#define MCDE_CHNL0SYNCHSW 0x0000060C +#define MCDE_CHNL0SYNCHSW_GROUPOFFSET 0x20 +#define MCDE_CHNL0SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL0SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL0SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL0SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL1SYNCHSW 0x0000062C +#define MCDE_CHNL1SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL1SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL1SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL1SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL2SYNCHSW 0x0000064C +#define MCDE_CHNL2SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL2SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL2SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL2SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL3SYNCHSW 0x0000066C +#define MCDE_CHNL3SYNCHSW_SW_TRIG_SHIFT 0 +#define MCDE_CHNL3SYNCHSW_SW_TRIG_MASK 0x00000001 +#define MCDE_CHNL3SYNCHSW_SW_TRIG(__x) \ + MCDE_VAL2REG(MCDE_CHNL3SYNCHSW, SW_TRIG, __x) +#define MCDE_CHNL0BCKGNDCOL 0x00000610 +#define MCDE_CHNL0BCKGNDCOL_GROUPOFFSET 0x20 +#define MCDE_CHNL0BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL0BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL0BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, B, __x) +#define MCDE_CHNL0BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL0BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL0BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, G, __x) +#define MCDE_CHNL0BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL0BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL0BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL0BCKGNDCOL, R, __x) +#define MCDE_CHNL1BCKGNDCOL 0x00000630 +#define MCDE_CHNL1BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL1BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL1BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, B, __x) +#define MCDE_CHNL1BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL1BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL1BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, G, __x) +#define MCDE_CHNL1BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL1BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL1BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL1BCKGNDCOL, R, __x) +#define MCDE_CHNL2BCKGNDCOL 0x00000650 +#define MCDE_CHNL2BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL2BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL2BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, B, __x) +#define MCDE_CHNL2BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL2BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL2BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, G, __x) +#define MCDE_CHNL2BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL2BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL2BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL2BCKGNDCOL, R, __x) +#define MCDE_CHNL3BCKGNDCOL 0x00000670 +#define MCDE_CHNL3BCKGNDCOL_B_SHIFT 0 +#define MCDE_CHNL3BCKGNDCOL_B_MASK 0x000000FF +#define MCDE_CHNL3BCKGNDCOL_B(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, B, __x) +#define MCDE_CHNL3BCKGNDCOL_G_SHIFT 8 +#define MCDE_CHNL3BCKGNDCOL_G_MASK 0x0000FF00 +#define MCDE_CHNL3BCKGNDCOL_G(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, G, __x) +#define MCDE_CHNL3BCKGNDCOL_R_SHIFT 16 +#define MCDE_CHNL3BCKGNDCOL_R_MASK 0x00FF0000 +#define MCDE_CHNL3BCKGNDCOL_R(__x) \ + MCDE_VAL2REG(MCDE_CHNL3BCKGNDCOL, R, __x) +#define MCDE_CHNL0PRIO 0x00000614 +#define MCDE_CHNL0PRIO_GROUPOFFSET 0x20 +#define MCDE_CHNL0PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL0PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL0PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL0PRIO, CHNLPRIO, __x) +#define MCDE_CHNL1PRIO 0x00000634 +#define MCDE_CHNL1PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL1PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL1PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL1PRIO, CHNLPRIO, __x) +#define MCDE_CHNL2PRIO 0x00000654 +#define MCDE_CHNL2PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL2PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL2PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL2PRIO, CHNLPRIO, __x) +#define MCDE_CHNL3PRIO 0x00000674 +#define MCDE_CHNL3PRIO_CHNLPRIO_SHIFT 0 +#define MCDE_CHNL3PRIO_CHNLPRIO_MASK 0x0000000F +#define MCDE_CHNL3PRIO_CHNLPRIO(__x) \ + MCDE_VAL2REG(MCDE_CHNL3PRIO, CHNLPRIO, __x) +#define MCDE_CRA0 0x00000800 +#define MCDE_CRA0_GROUPOFFSET 0x200 +#define MCDE_CRA0_FLOEN_SHIFT 0 +#define MCDE_CRA0_FLOEN_MASK 0x00000001 +#define MCDE_CRA0_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOEN, __x) +#define MCDE_CRA0_POWEREN_SHIFT 1 +#define MCDE_CRA0_POWEREN_MASK 0x00000002 +#define MCDE_CRA0_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, POWEREN, __x) +#define MCDE_CRA0_BLENDEN_SHIFT 2 +#define MCDE_CRA0_BLENDEN_MASK 0x00000004 +#define MCDE_CRA0_BLENDEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDEN, __x) +#define MCDE_CRA0_AFLICKEN_SHIFT 3 +#define MCDE_CRA0_AFLICKEN_MASK 0x00000008 +#define MCDE_CRA0_AFLICKEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, AFLICKEN, __x) +#define MCDE_CRA0_PALEN_SHIFT 4 +#define MCDE_CRA0_PALEN_MASK 0x00000010 +#define MCDE_CRA0_PALEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, PALEN, __x) +#define MCDE_CRA0_DITHEN_SHIFT 5 +#define MCDE_CRA0_DITHEN_MASK 0x00000020 +#define MCDE_CRA0_DITHEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, DITHEN, __x) +#define MCDE_CRA0_GAMEN_SHIFT 6 +#define MCDE_CRA0_GAMEN_MASK 0x00000040 +#define MCDE_CRA0_GAMEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, GAMEN, __x) +#define MCDE_CRA0_KEYCTRL_SHIFT 7 +#define MCDE_CRA0_KEYCTRL_MASK 0x00000380 +#define MCDE_CRA0_KEYCTRL_OFF 0 +#define MCDE_CRA0_KEYCTRL_ALPHA_RGB 1 +#define MCDE_CRA0_KEYCTRL_RGB 2 +#define MCDE_CRA0_KEYCTRL_FALPHA_FRGB 4 +#define MCDE_CRA0_KEYCTRL_FRGB 5 +#define MCDE_CRA0_KEYCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, KEYCTRL, MCDE_CRA0_KEYCTRL_##__x) +#define MCDE_CRA0_KEYCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRA0, KEYCTRL, __x) +#define MCDE_CRA0_BLENDCTRL_SHIFT 10 +#define MCDE_CRA0_BLENDCTRL_MASK 0x00000400 +#define MCDE_CRA0_BLENDCTRL_SOURCE 0 +#define MCDE_CRA0_BLENDCTRL_CONSTANT 1 +#define MCDE_CRA0_BLENDCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDCTRL, MCDE_CRA0_BLENDCTRL_##__x) +#define MCDE_CRA0_BLENDCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRA0, BLENDCTRL, __x) +#define MCDE_CRA0_FLICKMODE_SHIFT 11 +#define MCDE_CRA0_FLICKMODE_MASK 0x00001800 +#define MCDE_CRA0_FLICKMODE_FORCE_FILTER_0 0 +#define MCDE_CRA0_FLICKMODE_ADAPTIVE 1 +#define MCDE_CRA0_FLICKMODE_TEST_MODE 2 +#define MCDE_CRA0_FLICKMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLICKMODE, MCDE_CRA0_FLICKMODE_##__x) +#define MCDE_CRA0_FLICKMODE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLICKMODE, __x) +#define MCDE_CRA0_FLOCKFORMAT_SHIFT 13 +#define MCDE_CRA0_FLOCKFORMAT_MASK 0x00002000 +#define MCDE_CRA0_FLOCKFORMAT_YCBCR 0 +#define MCDE_CRA0_FLOCKFORMAT_RGB 1 +#define MCDE_CRA0_FLOCKFORMAT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOCKFORMAT, MCDE_CRA0_FLOCKFORMAT_##__x) +#define MCDE_CRA0_FLOCKFORMAT(__x) \ + MCDE_VAL2REG(MCDE_CRA0, FLOCKFORMAT, __x) +#define MCDE_CRA0_PALMODE_SHIFT 14 +#define MCDE_CRA0_PALMODE_MASK 0x00004000 +#define MCDE_CRA0_PALMODE_PALETTE 0 +#define MCDE_CRA0_PALMODE_GAMMA 1 +#define MCDE_CRA0_PALMODE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, PALMODE, __x) +#define MCDE_CRA0_OLEDEN_SHIFT 15 +#define MCDE_CRA0_OLEDEN_MASK 0x00008000 +#define MCDE_CRA0_OLEDEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, OLEDEN, __x) +#define MCDE_CRA0_ALPHABLEND_SHIFT 16 +#define MCDE_CRA0_ALPHABLEND_MASK 0x00FF0000 +#define MCDE_CRA0_ALPHABLEND(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ALPHABLEND, __x) +#define MCDE_CRA0_ROTEN_SHIFT 24 +#define MCDE_CRA0_ROTEN_MASK 0x01000000 +#define MCDE_CRA0_ROTEN(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTEN, __x) +#define MCDE_CRA0_ROTBURSTSIZE_SHIFT 25 +#define MCDE_CRA0_ROTBURSTSIZE_MASK 0x0E000000 +#define MCDE_CRA0_ROTBURSTSIZE_1W 0 +#define MCDE_CRA0_ROTBURSTSIZE_2W 1 +#define MCDE_CRA0_ROTBURSTSIZE_4W 2 +#define MCDE_CRA0_ROTBURSTSIZE_8W 3 +#define MCDE_CRA0_ROTBURSTSIZE_16W 4 +#define MCDE_CRA0_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, MCDE_CRA0_ROTBURSTSIZE_##__x) +#define MCDE_CRA0_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE, __x) +#define MCDE_CRA0_ROTBURSTSIZE_HW_SHIFT 28 +#define MCDE_CRA0_ROTBURSTSIZE_HW_MASK 0x10000000 +#define MCDE_CRA0_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_CRA0, ROTBURSTSIZE_HW, __x) +#define MCDE_CRB0 0x00000A00 +#define MCDE_CRB0_FLOEN_SHIFT 0 +#define MCDE_CRB0_FLOEN_MASK 0x00000001 +#define MCDE_CRB0_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOEN, __x) +#define MCDE_CRB0_POWEREN_SHIFT 1 +#define MCDE_CRB0_POWEREN_MASK 0x00000002 +#define MCDE_CRB0_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, POWEREN, __x) +#define MCDE_CRB0_BLENDEN_SHIFT 2 +#define MCDE_CRB0_BLENDEN_MASK 0x00000004 +#define MCDE_CRB0_BLENDEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDEN, __x) +#define MCDE_CRB0_AFLICKEN_SHIFT 3 +#define MCDE_CRB0_AFLICKEN_MASK 0x00000008 +#define MCDE_CRB0_AFLICKEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, AFLICKEN, __x) +#define MCDE_CRB0_PALEN_SHIFT 4 +#define MCDE_CRB0_PALEN_MASK 0x00000010 +#define MCDE_CRB0_PALEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, PALEN, __x) +#define MCDE_CRB0_DITHEN_SHIFT 5 +#define MCDE_CRB0_DITHEN_MASK 0x00000020 +#define MCDE_CRB0_DITHEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, DITHEN, __x) +#define MCDE_CRB0_GAMEN_SHIFT 6 +#define MCDE_CRB0_GAMEN_MASK 0x00000040 +#define MCDE_CRB0_GAMEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, GAMEN, __x) +#define MCDE_CRB0_KEYCTRL_SHIFT 7 +#define MCDE_CRB0_KEYCTRL_MASK 0x00000380 +#define MCDE_CRB0_KEYCTRL_OFF 0 +#define MCDE_CRB0_KEYCTRL_ALPHA_RGB 1 +#define MCDE_CRB0_KEYCTRL_RGB 2 +#define MCDE_CRB0_KEYCTRL_FALPHA_FRGB 4 +#define MCDE_CRB0_KEYCTRL_FRGB 5 +#define MCDE_CRB0_KEYCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, KEYCTRL, MCDE_CRB0_KEYCTRL_##__x) +#define MCDE_CRB0_KEYCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRB0, KEYCTRL, __x) +#define MCDE_CRB0_BLENDCTRL_SHIFT 10 +#define MCDE_CRB0_BLENDCTRL_MASK 0x00000400 +#define MCDE_CRB0_BLENDCTRL_SOURCE 0 +#define MCDE_CRB0_BLENDCTRL_CONSTANT 1 +#define MCDE_CRB0_BLENDCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDCTRL, MCDE_CRB0_BLENDCTRL_##__x) +#define MCDE_CRB0_BLENDCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRB0, BLENDCTRL, __x) +#define MCDE_CRB0_FLICKMODE_SHIFT 11 +#define MCDE_CRB0_FLICKMODE_MASK 0x00001800 +#define MCDE_CRB0_FLICKMODE_FORCE_FILTER_0 0 +#define MCDE_CRB0_FLICKMODE_ADAPTIVE 1 +#define MCDE_CRB0_FLICKMODE_TEST_MODE 2 +#define MCDE_CRB0_FLICKMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLICKMODE, MCDE_CRB0_FLICKMODE_##__x) +#define MCDE_CRB0_FLICKMODE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLICKMODE, __x) +#define MCDE_CRB0_FLOCKFORMAT_SHIFT 13 +#define MCDE_CRB0_FLOCKFORMAT_MASK 0x00002000 +#define MCDE_CRB0_FLOCKFORMAT_YCBCR 0 +#define MCDE_CRB0_FLOCKFORMAT_RGB 1 +#define MCDE_CRB0_FLOCKFORMAT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOCKFORMAT, MCDE_CRB0_FLOCKFORMAT_##__x) +#define MCDE_CRB0_FLOCKFORMAT(__x) \ + MCDE_VAL2REG(MCDE_CRB0, FLOCKFORMAT, __x) +#define MCDE_CRB0_PALMODE_SHIFT 14 +#define MCDE_CRB0_PALMODE_MASK 0x00004000 +#define MCDE_CRB0_PALMODE_PALETTE 0 +#define MCDE_CRB0_PALMODE_GAMMA 1 +#define MCDE_CRB0_PALMODE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, PALMODE, __x) +#define MCDE_CRB0_OLEDEN_SHIFT 15 +#define MCDE_CRB0_OLEDEN_MASK 0x00008000 +#define MCDE_CRB0_OLEDEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, OLEDEN, __x) +#define MCDE_CRB0_ALPHABLEND_SHIFT 16 +#define MCDE_CRB0_ALPHABLEND_MASK 0x00FF0000 +#define MCDE_CRB0_ALPHABLEND(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ALPHABLEND, __x) +#define MCDE_CRB0_ROTEN_SHIFT 24 +#define MCDE_CRB0_ROTEN_MASK 0x01000000 +#define MCDE_CRB0_ROTEN(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTEN, __x) +#define MCDE_CRB0_ROTBURSTSIZE_SHIFT 25 +#define MCDE_CRB0_ROTBURSTSIZE_MASK 0x0E000000 +#define MCDE_CRB0_ROTBURSTSIZE_1W 0 +#define MCDE_CRB0_ROTBURSTSIZE_2W 1 +#define MCDE_CRB0_ROTBURSTSIZE_4W 2 +#define MCDE_CRB0_ROTBURSTSIZE_8W 3 +#define MCDE_CRB0_ROTBURSTSIZE_16W 4 +#define MCDE_CRB0_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, MCDE_CRB0_ROTBURSTSIZE_##__x) +#define MCDE_CRB0_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE, __x) +#define MCDE_CRB0_ROTBURSTSIZE_HW_SHIFT 28 +#define MCDE_CRB0_ROTBURSTSIZE_HW_MASK 0x10000000 +#define MCDE_CRB0_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_CRB0, ROTBURSTSIZE_HW, __x) +#define MCDE_CRA1 0x00000804 +#define MCDE_CRA1_GROUPOFFSET 0x200 +#define MCDE_CRA1_PCD_SHIFT 0 +#define MCDE_CRA1_PCD_MASK 0x000003FF +#define MCDE_CRA1_PCD(__x) \ + MCDE_VAL2REG(MCDE_CRA1, PCD, __x) +#define MCDE_CRA1_CLKSEL_SHIFT 10 +#define MCDE_CRA1_CLKSEL_MASK 0x00001C00 +#define MCDE_CRA1_CLKSEL_LCD 0 +#define MCDE_CRA1_CLKSEL_HDMI 1 +#define MCDE_CRA1_CLKSEL_TV 2 +#define MCDE_CRA1_CLKSEL_EXT_TV1 3 +#define MCDE_CRA1_CLKSEL_EXT_TV2 4 +#define MCDE_CRA1_CLKSEL_166MHZ 5 +#define MCDE_CRA1_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKSEL, MCDE_CRA1_CLKSEL_##__x) +#define MCDE_CRA1_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKSEL, __x) +#define MCDE_CRA1_CDWIN_SHIFT 13 +#define MCDE_CRA1_CDWIN_MASK 0x0001E000 +#define MCDE_CRA1_CDWIN_8BBP_C1 0 +#define MCDE_CRA1_CDWIN_12BBP_C1 1 +#define MCDE_CRA1_CDWIN_12BBP_C2 2 +#define MCDE_CRA1_CDWIN_16BBP_C1 3 +#define MCDE_CRA1_CDWIN_16BBP_C2 4 +#define MCDE_CRA1_CDWIN_18BBP_C1 5 +#define MCDE_CRA1_CDWIN_18BBP_C2 6 +#define MCDE_CRA1_CDWIN_24BBP 7 +#define MCDE_CRA1_CDWIN_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CDWIN, MCDE_CRA1_CDWIN_##__x) +#define MCDE_CRA1_CDWIN(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CDWIN, __x) +#define MCDE_CRA1_OUTBPP_SHIFT 25 +#define MCDE_CRA1_OUTBPP_MASK 0x1E000000 +#define MCDE_CRA1_OUTBPP_MONO1 0 +#define MCDE_CRA1_OUTBPP_MONO2 1 +#define MCDE_CRA1_OUTBPP_MONO4 2 +#define MCDE_CRA1_OUTBPP_MONO8 3 +#define MCDE_CRA1_OUTBPP_8BPP 4 +#define MCDE_CRA1_OUTBPP_12BPP 5 +#define MCDE_CRA1_OUTBPP_15BPP 6 +#define MCDE_CRA1_OUTBPP_16BPP 7 +#define MCDE_CRA1_OUTBPP_18BPP 8 +#define MCDE_CRA1_OUTBPP_24BPP 9 +#define MCDE_CRA1_OUTBPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, OUTBPP, MCDE_CRA1_OUTBPP_##__x) +#define MCDE_CRA1_OUTBPP(__x) \ + MCDE_VAL2REG(MCDE_CRA1, OUTBPP, __x) +#define MCDE_CRA1_BCD_SHIFT 29 +#define MCDE_CRA1_BCD_MASK 0x20000000 +#define MCDE_CRA1_BCD(__x) \ + MCDE_VAL2REG(MCDE_CRA1, BCD, __x) +#define MCDE_CRA1_CLKTYPE_SHIFT 30 +#define MCDE_CRA1_CLKTYPE_MASK 0x40000000 +#define MCDE_CRA1_CLKTYPE_EXTERNAL 0 +#define MCDE_CRA1_CLKTYPE_INTERNAL 1 +#define MCDE_CRA1_CLKTYPE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, MCDE_CRA1_CLKTYPE_##__x) +#define MCDE_CRA1_CLKTYPE(__x) \ + MCDE_VAL2REG(MCDE_CRA1, CLKTYPE, __x) +#define MCDE_CRA1_TEFFECTEN_SHIFT 31 +#define MCDE_CRA1_TEFFECTEN_MASK 0x80000000 +#define MCDE_CRA1_TEFFECTEN(__x) \ + MCDE_VAL2REG(MCDE_CRA1, TEFFECTEN, __x) +#define MCDE_CRB1 0x00000A04 +#define MCDE_CRB1_PCD_SHIFT 0 +#define MCDE_CRB1_PCD_MASK 0x000003FF +#define MCDE_CRB1_PCD(__x) \ + MCDE_VAL2REG(MCDE_CRB1, PCD, __x) +#define MCDE_CRB1_CLKSEL_SHIFT 10 +#define MCDE_CRB1_CLKSEL_MASK 0x00001C00 +#define MCDE_CRB1_CLKSEL_LCD 0 +#define MCDE_CRB1_CLKSEL_HDMI 1 +#define MCDE_CRB1_CLKSEL_TV 2 +#define MCDE_CRB1_CLKSEL_EXT_TV1 3 +#define MCDE_CRB1_CLKSEL_EXT_TV2 4 +#define MCDE_CRB1_CLKSEL_166MHZ 5 +#define MCDE_CRB1_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKSEL, MCDE_CRB1_CLKSEL_##__x) +#define MCDE_CRB1_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKSEL, __x) +#define MCDE_CRB1_CDWIN_SHIFT 13 +#define MCDE_CRB1_CDWIN_MASK 0x0001E000 +#define MCDE_CRB1_CDWIN_8BBP_C1 0 +#define MCDE_CRB1_CDWIN_12BBP_C1 1 +#define MCDE_CRB1_CDWIN_12BBP_C2 2 +#define MCDE_CRB1_CDWIN_16BBP_C1 3 +#define MCDE_CRB1_CDWIN_16BBP_C2 4 +#define MCDE_CRB1_CDWIN_18BBP_C1 5 +#define MCDE_CRB1_CDWIN_18BBP_C2 6 +#define MCDE_CRB1_CDWIN_24BBP 7 +#define MCDE_CRB1_CDWIN_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CDWIN, MCDE_CRB1_CDWIN_##__x) +#define MCDE_CRB1_CDWIN(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CDWIN, __x) +#define MCDE_CRB1_OUTBPP_SHIFT 25 +#define MCDE_CRB1_OUTBPP_MASK 0x1E000000 +#define MCDE_CRB1_OUTBPP_MONO1 0 +#define MCDE_CRB1_OUTBPP_MONO2 1 +#define MCDE_CRB1_OUTBPP_MONO4 2 +#define MCDE_CRB1_OUTBPP_MONO8 3 +#define MCDE_CRB1_OUTBPP_8BPP 4 +#define MCDE_CRB1_OUTBPP_12BPP 5 +#define MCDE_CRB1_OUTBPP_15BPP 6 +#define MCDE_CRB1_OUTBPP_16BPP 7 +#define MCDE_CRB1_OUTBPP_18BPP 8 +#define MCDE_CRB1_OUTBPP_24BPP 9 +#define MCDE_CRB1_OUTBPP_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, OUTBPP, MCDE_CRB1_OUTBPP_##__x) +#define MCDE_CRB1_OUTBPP(__x) \ + MCDE_VAL2REG(MCDE_CRB1, OUTBPP, __x) +#define MCDE_CRB1_BCD_SHIFT 29 +#define MCDE_CRB1_BCD_MASK 0x20000000 +#define MCDE_CRB1_BCD(__x) \ + MCDE_VAL2REG(MCDE_CRB1, BCD, __x) +#define MCDE_CRB1_CLKTYPE_SHIFT 30 +#define MCDE_CRB1_CLKTYPE_MASK 0x40000000 +#define MCDE_CRB1_CLKTYPE_EXTERNAL 0 +#define MCDE_CRB1_CLKTYPE_INTERNAL 1 +#define MCDE_CRB1_CLKTYPE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, MCDE_CRB1_CLKTYPE_##__x) +#define MCDE_CRB1_CLKTYPE(__x) \ + MCDE_VAL2REG(MCDE_CRB1, CLKTYPE, __x) +#define MCDE_CRB1_TEFFECTEN_SHIFT 31 +#define MCDE_CRB1_TEFFECTEN_MASK 0x80000000 +#define MCDE_CRB1_TEFFECTEN(__x) \ + MCDE_VAL2REG(MCDE_CRB1, TEFFECTEN, __x) +#define MCDE_COLKEYA 0x00000808 +#define MCDE_COLKEYA_GROUPOFFSET 0x200 +#define MCDE_COLKEYA_KEYB_SHIFT 0 +#define MCDE_COLKEYA_KEYB_MASK 0x000000FF +#define MCDE_COLKEYA_KEYB(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYB, __x) +#define MCDE_COLKEYA_KEYG_SHIFT 8 +#define MCDE_COLKEYA_KEYG_MASK 0x0000FF00 +#define MCDE_COLKEYA_KEYG(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYG, __x) +#define MCDE_COLKEYA_KEYR_SHIFT 16 +#define MCDE_COLKEYA_KEYR_MASK 0x00FF0000 +#define MCDE_COLKEYA_KEYR(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYR, __x) +#define MCDE_COLKEYA_KEYA_SHIFT 24 +#define MCDE_COLKEYA_KEYA_MASK 0xFF000000 +#define MCDE_COLKEYA_KEYA(__x) \ + MCDE_VAL2REG(MCDE_COLKEYA, KEYA, __x) +#define MCDE_COLKEYB 0x00000A08 +#define MCDE_COLKEYB_KEYB_SHIFT 0 +#define MCDE_COLKEYB_KEYB_MASK 0x000000FF +#define MCDE_COLKEYB_KEYB(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYB, __x) +#define MCDE_COLKEYB_KEYG_SHIFT 8 +#define MCDE_COLKEYB_KEYG_MASK 0x0000FF00 +#define MCDE_COLKEYB_KEYG(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYG, __x) +#define MCDE_COLKEYB_KEYR_SHIFT 16 +#define MCDE_COLKEYB_KEYR_MASK 0x00FF0000 +#define MCDE_COLKEYB_KEYR(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYR, __x) +#define MCDE_COLKEYB_KEYA_SHIFT 24 +#define MCDE_COLKEYB_KEYA_MASK 0xFF000000 +#define MCDE_COLKEYB_KEYA(__x) \ + MCDE_VAL2REG(MCDE_COLKEYB, KEYA, __x) +#define MCDE_FCOLKEYA 0x0000080C +#define MCDE_FCOLKEYA_GROUPOFFSET 0x200 +#define MCDE_FCOLKEYA_FKEYB_SHIFT 0 +#define MCDE_FCOLKEYA_FKEYB_MASK 0x000000FF +#define MCDE_FCOLKEYA_FKEYB(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYB, __x) +#define MCDE_FCOLKEYA_FKEYG_SHIFT 8 +#define MCDE_FCOLKEYA_FKEYG_MASK 0x0000FF00 +#define MCDE_FCOLKEYA_FKEYG(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYG, __x) +#define MCDE_FCOLKEYA_FKEYR_SHIFT 16 +#define MCDE_FCOLKEYA_FKEYR_MASK 0x00FF0000 +#define MCDE_FCOLKEYA_FKEYR(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYR, __x) +#define MCDE_FCOLKEYA_FKEYA_SHIFT 24 +#define MCDE_FCOLKEYA_FKEYA_MASK 0xFF000000 +#define MCDE_FCOLKEYA_FKEYA(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYA, FKEYA, __x) +#define MCDE_FCOLKEYB 0x00000A0C +#define MCDE_FCOLKEYB_FKEYB_SHIFT 0 +#define MCDE_FCOLKEYB_FKEYB_MASK 0x000000FF +#define MCDE_FCOLKEYB_FKEYB(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYB, __x) +#define MCDE_FCOLKEYB_FKEYG_SHIFT 8 +#define MCDE_FCOLKEYB_FKEYG_MASK 0x0000FF00 +#define MCDE_FCOLKEYB_FKEYG(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYG, __x) +#define MCDE_FCOLKEYB_FKEYR_SHIFT 16 +#define MCDE_FCOLKEYB_FKEYR_MASK 0x00FF0000 +#define MCDE_FCOLKEYB_FKEYR(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYR, __x) +#define MCDE_FCOLKEYB_FKEYA_SHIFT 24 +#define MCDE_FCOLKEYB_FKEYA_MASK 0xFF000000 +#define MCDE_FCOLKEYB_FKEYA(__x) \ + MCDE_VAL2REG(MCDE_FCOLKEYB, FKEYA, __x) +#define MCDE_RGBCONV1A 0x00000810 +#define MCDE_RGBCONV1A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV1A_YR_GREEN_SHIFT 0 +#define MCDE_RGBCONV1A_YR_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV1A_YR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1A, YR_GREEN, __x) +#define MCDE_RGBCONV1A_YR_RED_SHIFT 16 +#define MCDE_RGBCONV1A_YR_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV1A_YR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1A, YR_RED, __x) +#define MCDE_RGBCONV1B 0x00000A10 +#define MCDE_RGBCONV1B_YR_GREEN_SHIFT 0 +#define MCDE_RGBCONV1B_YR_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV1B_YR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1B, YR_GREEN, __x) +#define MCDE_RGBCONV1B_YR_RED_SHIFT 16 +#define MCDE_RGBCONV1B_YR_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV1B_YR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV1B, YR_RED, __x) +#define MCDE_RGBCONV2A 0x00000814 +#define MCDE_RGBCONV2A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV2A_CR_RED_SHIFT 0 +#define MCDE_RGBCONV2A_CR_RED_MASK 0x000007FF +#define MCDE_RGBCONV2A_CR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2A, CR_RED, __x) +#define MCDE_RGBCONV2A_YR_BLUE_SHIFT 16 +#define MCDE_RGBCONV2A_YR_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV2A_YR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2A, YR_BLUE, __x) +#define MCDE_RGBCONV2B 0x00000A14 +#define MCDE_RGBCONV2B_CR_RED_SHIFT 0 +#define MCDE_RGBCONV2B_CR_RED_MASK 0x000007FF +#define MCDE_RGBCONV2B_CR_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2B, CR_RED, __x) +#define MCDE_RGBCONV2B_YR_BLUE_SHIFT 16 +#define MCDE_RGBCONV2B_YR_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV2B_YR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV2B, YR_BLUE, __x) +#define MCDE_RGBCONV3A 0x00000818 +#define MCDE_RGBCONV3A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV3A_CR_BLUE_SHIFT 0 +#define MCDE_RGBCONV3A_CR_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV3A_CR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3A, CR_BLUE, __x) +#define MCDE_RGBCONV3A_CR_GREEN_SHIFT 16 +#define MCDE_RGBCONV3A_CR_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV3A_CR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3A, CR_GREEN, __x) +#define MCDE_RGBCONV3B 0x00000A18 +#define MCDE_RGBCONV3B_CR_BLUE_SHIFT 0 +#define MCDE_RGBCONV3B_CR_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV3B_CR_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3B, CR_BLUE, __x) +#define MCDE_RGBCONV3B_CR_GREEN_SHIFT 16 +#define MCDE_RGBCONV3B_CR_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV3B_CR_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV3B, CR_GREEN, __x) +#define MCDE_RGBCONV4A 0x0000081C +#define MCDE_RGBCONV4A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV4A_CB_GREEN_SHIFT 0 +#define MCDE_RGBCONV4A_CB_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV4A_CB_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4A, CB_GREEN, __x) +#define MCDE_RGBCONV4A_CB_RED_SHIFT 16 +#define MCDE_RGBCONV4A_CB_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV4A_CB_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4A, CB_RED, __x) +#define MCDE_RGBCONV4B 0x00000A1C +#define MCDE_RGBCONV4B_CB_GREEN_SHIFT 0 +#define MCDE_RGBCONV4B_CB_GREEN_MASK 0x000007FF +#define MCDE_RGBCONV4B_CB_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4B, CB_GREEN, __x) +#define MCDE_RGBCONV4B_CB_RED_SHIFT 16 +#define MCDE_RGBCONV4B_CB_RED_MASK 0x07FF0000 +#define MCDE_RGBCONV4B_CB_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV4B, CB_RED, __x) +#define MCDE_RGBCONV5A 0x00000820 +#define MCDE_RGBCONV5A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV5A_OFF_RED_SHIFT 0 +#define MCDE_RGBCONV5A_OFF_RED_MASK 0x000007FF +#define MCDE_RGBCONV5A_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5A, OFF_RED, __x) +#define MCDE_RGBCONV5A_CB_BLUE_SHIFT 16 +#define MCDE_RGBCONV5A_CB_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV5A_CB_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5A, CB_BLUE, __x) +#define MCDE_RGBCONV5B 0x00000A20 +#define MCDE_RGBCONV5B_OFF_RED_SHIFT 0 +#define MCDE_RGBCONV5B_OFF_RED_MASK 0x000007FF +#define MCDE_RGBCONV5B_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5B, OFF_RED, __x) +#define MCDE_RGBCONV5B_CB_BLUE_SHIFT 16 +#define MCDE_RGBCONV5B_CB_BLUE_MASK 0x07FF0000 +#define MCDE_RGBCONV5B_CB_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV5B, CB_BLUE, __x) +#define MCDE_RGBCONV6A 0x00000824 +#define MCDE_RGBCONV6A_GROUPOFFSET 0x200 +#define MCDE_RGBCONV6A_OFF_BLUE_SHIFT 0 +#define MCDE_RGBCONV6A_OFF_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV6A_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6A, OFF_BLUE, __x) +#define MCDE_RGBCONV6A_OFF_GREEN_SHIFT 16 +#define MCDE_RGBCONV6A_OFF_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV6A_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6A, OFF_GREEN, __x) +#define MCDE_RGBCONV6B 0x00000A24 +#define MCDE_RGBCONV6B_OFF_BLUE_SHIFT 0 +#define MCDE_RGBCONV6B_OFF_BLUE_MASK 0x000007FF +#define MCDE_RGBCONV6B_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6B, OFF_BLUE, __x) +#define MCDE_RGBCONV6B_OFF_GREEN_SHIFT 16 +#define MCDE_RGBCONV6B_OFF_GREEN_MASK 0x07FF0000 +#define MCDE_RGBCONV6B_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_RGBCONV6B, OFF_GREEN, __x) +#define MCDE_FFCOEFA0 0x00000828 +#define MCDE_FFCOEFA0_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA0_COEFF0_N1_SHIFT 0 +#define MCDE_FFCOEFA0_COEFF0_N1_MASK 0x000000FF +#define MCDE_FFCOEFA0_COEFF0_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N1, __x) +#define MCDE_FFCOEFA0_COEFF0_N2_SHIFT 8 +#define MCDE_FFCOEFA0_COEFF0_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA0_COEFF0_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N2, __x) +#define MCDE_FFCOEFA0_COEFF0_N3_SHIFT 16 +#define MCDE_FFCOEFA0_COEFF0_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA0_COEFF0_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, COEFF0_N3, __x) +#define MCDE_FFCOEFA0_T0_SHIFT 24 +#define MCDE_FFCOEFA0_T0_MASK 0x0F000000 +#define MCDE_FFCOEFA0_T0(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA0, T0, __x) +#define MCDE_FFCOEFB0 0x00000A28 +#define MCDE_FFCOEFB0_COEFF0_N1_SHIFT 0 +#define MCDE_FFCOEFB0_COEFF0_N1_MASK 0x000000FF +#define MCDE_FFCOEFB0_COEFF0_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N1, __x) +#define MCDE_FFCOEFB0_COEFF0_N2_SHIFT 8 +#define MCDE_FFCOEFB0_COEFF0_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB0_COEFF0_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N2, __x) +#define MCDE_FFCOEFB0_COEFF0_N3_SHIFT 16 +#define MCDE_FFCOEFB0_COEFF0_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB0_COEFF0_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, COEFF0_N3, __x) +#define MCDE_FFCOEFB0_T0_SHIFT 24 +#define MCDE_FFCOEFB0_T0_MASK 0x0F000000 +#define MCDE_FFCOEFB0_T0(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB0, T0, __x) +#define MCDE_FFCOEFA1 0x0000082C +#define MCDE_FFCOEFA1_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA1_COEFF1_N1_SHIFT 0 +#define MCDE_FFCOEFA1_COEFF1_N1_MASK 0x000000FF +#define MCDE_FFCOEFA1_COEFF1_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N1, __x) +#define MCDE_FFCOEFA1_COEFF1_N2_SHIFT 8 +#define MCDE_FFCOEFA1_COEFF1_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA1_COEFF1_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N2, __x) +#define MCDE_FFCOEFA1_COEFF1_N3_SHIFT 16 +#define MCDE_FFCOEFA1_COEFF1_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA1_COEFF1_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, COEFF1_N3, __x) +#define MCDE_FFCOEFA1_T1_SHIFT 24 +#define MCDE_FFCOEFA1_T1_MASK 0x0F000000 +#define MCDE_FFCOEFA1_T1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA1, T1, __x) +#define MCDE_FFCOEFB1 0x00000A2C +#define MCDE_FFCOEFB1_COEFF1_N1_SHIFT 0 +#define MCDE_FFCOEFB1_COEFF1_N1_MASK 0x000000FF +#define MCDE_FFCOEFB1_COEFF1_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N1, __x) +#define MCDE_FFCOEFB1_COEFF1_N2_SHIFT 8 +#define MCDE_FFCOEFB1_COEFF1_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB1_COEFF1_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N2, __x) +#define MCDE_FFCOEFB1_COEFF1_N3_SHIFT 16 +#define MCDE_FFCOEFB1_COEFF1_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB1_COEFF1_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, COEFF1_N3, __x) +#define MCDE_FFCOEFB1_T1_SHIFT 24 +#define MCDE_FFCOEFB1_T1_MASK 0x0F000000 +#define MCDE_FFCOEFB1_T1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB1, T1, __x) +#define MCDE_FFCOEFA2 0x00000830 +#define MCDE_FFCOEFA2_GROUPOFFSET 0x200 +#define MCDE_FFCOEFA2_COEFF2_N1_SHIFT 0 +#define MCDE_FFCOEFA2_COEFF2_N1_MASK 0x000000FF +#define MCDE_FFCOEFA2_COEFF2_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N1, __x) +#define MCDE_FFCOEFA2_COEFF2_N2_SHIFT 8 +#define MCDE_FFCOEFA2_COEFF2_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFA2_COEFF2_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N2, __x) +#define MCDE_FFCOEFA2_COEFF2_N3_SHIFT 16 +#define MCDE_FFCOEFA2_COEFF2_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFA2_COEFF2_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, COEFF2_N3, __x) +#define MCDE_FFCOEFA2_T2_SHIFT 24 +#define MCDE_FFCOEFA2_T2_MASK 0x0F000000 +#define MCDE_FFCOEFA2_T2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFA2, T2, __x) +#define MCDE_FFCOEFB2 0x00000A30 +#define MCDE_FFCOEFB2_COEFF2_N1_SHIFT 0 +#define MCDE_FFCOEFB2_COEFF2_N1_MASK 0x000000FF +#define MCDE_FFCOEFB2_COEFF2_N1(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N1, __x) +#define MCDE_FFCOEFB2_COEFF2_N2_SHIFT 8 +#define MCDE_FFCOEFB2_COEFF2_N2_MASK 0x0000FF00 +#define MCDE_FFCOEFB2_COEFF2_N2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N2, __x) +#define MCDE_FFCOEFB2_COEFF2_N3_SHIFT 16 +#define MCDE_FFCOEFB2_COEFF2_N3_MASK 0x00FF0000 +#define MCDE_FFCOEFB2_COEFF2_N3(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, COEFF2_N3, __x) +#define MCDE_FFCOEFB2_T2_SHIFT 24 +#define MCDE_FFCOEFB2_T2_MASK 0x0F000000 +#define MCDE_FFCOEFB2_T2(__x) \ + MCDE_VAL2REG(MCDE_FFCOEFB2, T2, __x) +#define MCDE_TVCRA 0x00000838 +#define MCDE_TVCRA_GROUPOFFSET 0x200 +#define MCDE_TVCRA_SEL_MOD_SHIFT 0 +#define MCDE_TVCRA_SEL_MOD_MASK 0x00000001 +#define MCDE_TVCRA_SEL_MOD_LCD 0 +#define MCDE_TVCRA_SEL_MOD_TV 1 +#define MCDE_TVCRA_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SEL_MOD, MCDE_TVCRA_SEL_MOD_##__x) +#define MCDE_TVCRA_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SEL_MOD, __x) +#define MCDE_TVCRA_INTEREN_SHIFT 1 +#define MCDE_TVCRA_INTEREN_MASK 0x00000002 +#define MCDE_TVCRA_INTEREN(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, INTEREN, __x) +#define MCDE_TVCRA_IFIELD_SHIFT 2 +#define MCDE_TVCRA_IFIELD_MASK 0x00000004 +#define MCDE_TVCRA_IFIELD(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, IFIELD, __x) +#define MCDE_TVCRA_TVMODE_SHIFT 3 +#define MCDE_TVCRA_TVMODE_MASK 0x00000038 +#define MCDE_TVCRA_TVMODE_SDTV_656P 0 +#define MCDE_TVCRA_TVMODE_HDTV_480P 1 +#define MCDE_TVCRA_TVMODE_HDTV_720P 2 +#define MCDE_TVCRA_TVMODE_SDTV_656P_LE 3 +#define MCDE_TVCRA_TVMODE_SDTV_656P_BE 4 +#define MCDE_TVCRA_TVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, TVMODE, MCDE_TVCRA_TVMODE_##__x) +#define MCDE_TVCRA_TVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, TVMODE, __x) +#define MCDE_TVCRA_SDTVMODE_SHIFT 6 +#define MCDE_TVCRA_SDTVMODE_MASK 0x000000C0 +#define MCDE_TVCRA_SDTVMODE_Y0CBY1CR 0 +#define MCDE_TVCRA_SDTVMODE_CBY0CRY1 1 +#define MCDE_TVCRA_SDTVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SDTVMODE, MCDE_TVCRA_SDTVMODE_##__x) +#define MCDE_TVCRA_SDTVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, SDTVMODE, __x) +#define MCDE_TVCRA_AVRGEN_SHIFT 8 +#define MCDE_TVCRA_AVRGEN_MASK 0x00000100 +#define MCDE_TVCRA_AVRGEN(__x) \ + MCDE_VAL2REG(MCDE_TVCRA, AVRGEN, __x) +#define MCDE_TVCRB 0x00000A38 +#define MCDE_TVCRB_SEL_MOD_SHIFT 0 +#define MCDE_TVCRB_SEL_MOD_MASK 0x00000001 +#define MCDE_TVCRB_SEL_MOD_LCD 0 +#define MCDE_TVCRB_SEL_MOD_TV 1 +#define MCDE_TVCRB_SEL_MOD_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SEL_MOD, MCDE_TVCRB_SEL_MOD_##__x) +#define MCDE_TVCRB_SEL_MOD(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SEL_MOD, __x) +#define MCDE_TVCRB_INTEREN_SHIFT 1 +#define MCDE_TVCRB_INTEREN_MASK 0x00000002 +#define MCDE_TVCRB_INTEREN(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, INTEREN, __x) +#define MCDE_TVCRB_IFIELD_SHIFT 2 +#define MCDE_TVCRB_IFIELD_MASK 0x00000004 +#define MCDE_TVCRB_IFIELD(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, IFIELD, __x) +#define MCDE_TVCRB_TVMODE_SHIFT 3 +#define MCDE_TVCRB_TVMODE_MASK 0x00000038 +#define MCDE_TVCRB_TVMODE_SDTV_656P 0 +#define MCDE_TVCRB_TVMODE_HDTV_480P 1 +#define MCDE_TVCRB_TVMODE_HDTV_720P 2 +#define MCDE_TVCRB_TVMODE_SDTV_656P_LE 3 +#define MCDE_TVCRB_TVMODE_SDTV_656P_BE 4 +#define MCDE_TVCRB_TVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, TVMODE, MCDE_TVCRB_TVMODE_##__x) +#define MCDE_TVCRB_TVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, TVMODE, __x) +#define MCDE_TVCRB_SDTVMODE_SHIFT 6 +#define MCDE_TVCRB_SDTVMODE_MASK 0x000000C0 +#define MCDE_TVCRB_SDTVMODE_Y0CBY1CR 0 +#define MCDE_TVCRB_SDTVMODE_CBY0CRY1 1 +#define MCDE_TVCRB_SDTVMODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SDTVMODE, MCDE_TVCRB_SDTVMODE_##__x) +#define MCDE_TVCRB_SDTVMODE(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, SDTVMODE, __x) +#define MCDE_TVCRB_AVRGEN_SHIFT 8 +#define MCDE_TVCRB_AVRGEN_MASK 0x00000100 +#define MCDE_TVCRB_AVRGEN(__x) \ + MCDE_VAL2REG(MCDE_TVCRB, AVRGEN, __x) +#define MCDE_TVBL1A 0x0000083C +#define MCDE_TVBL1A_GROUPOFFSET 0x200 +#define MCDE_TVBL1A_BEL1_SHIFT 0 +#define MCDE_TVBL1A_BEL1_MASK 0x000007FF +#define MCDE_TVBL1A_BEL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1A, BEL1, __x) +#define MCDE_TVBL1A_BSL1_SHIFT 16 +#define MCDE_TVBL1A_BSL1_MASK 0x07FF0000 +#define MCDE_TVBL1A_BSL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1A, BSL1, __x) +#define MCDE_TVBL1B 0x00000A3C +#define MCDE_TVBL1B_BEL1_SHIFT 0 +#define MCDE_TVBL1B_BEL1_MASK 0x000007FF +#define MCDE_TVBL1B_BEL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1B, BEL1, __x) +#define MCDE_TVBL1B_BSL1_SHIFT 16 +#define MCDE_TVBL1B_BSL1_MASK 0x07FF0000 +#define MCDE_TVBL1B_BSL1(__x) \ + MCDE_VAL2REG(MCDE_TVBL1B, BSL1, __x) +#define MCDE_TVISLA 0x00000840 +#define MCDE_TVISLA_GROUPOFFSET 0x200 +#define MCDE_TVISLA_FSL1_SHIFT 0 +#define MCDE_TVISLA_FSL1_MASK 0x000007FF +#define MCDE_TVISLA_FSL1(__x) \ + MCDE_VAL2REG(MCDE_TVISLA, FSL1, __x) +#define MCDE_TVISLA_FSL2_SHIFT 16 +#define MCDE_TVISLA_FSL2_MASK 0x07FF0000 +#define MCDE_TVISLA_FSL2(__x) \ + MCDE_VAL2REG(MCDE_TVISLA, FSL2, __x) +#define MCDE_TVISLB 0x00000A40 +#define MCDE_TVISLB_FSL1_SHIFT 0 +#define MCDE_TVISLB_FSL1_MASK 0x000007FF +#define MCDE_TVISLB_FSL1(__x) \ + MCDE_VAL2REG(MCDE_TVISLB, FSL1, __x) +#define MCDE_TVISLB_FSL2_SHIFT 16 +#define MCDE_TVISLB_FSL2_MASK 0x07FF0000 +#define MCDE_TVISLB_FSL2(__x) \ + MCDE_VAL2REG(MCDE_TVISLB, FSL2, __x) +#define MCDE_TVDVOA 0x00000844 +#define MCDE_TVDVOA_GROUPOFFSET 0x200 +#define MCDE_TVDVOA_DVO1_SHIFT 0 +#define MCDE_TVDVOA_DVO1_MASK 0x000007FF +#define MCDE_TVDVOA_DVO1(__x) \ + MCDE_VAL2REG(MCDE_TVDVOA, DVO1, __x) +#define MCDE_TVDVOA_DVO2_SHIFT 16 +#define MCDE_TVDVOA_DVO2_MASK 0x07FF0000 +#define MCDE_TVDVOA_DVO2(__x) \ + MCDE_VAL2REG(MCDE_TVDVOA, DVO2, __x) +#define MCDE_TVDVOB 0x00000A44 +#define MCDE_TVDVOB_DVO1_SHIFT 0 +#define MCDE_TVDVOB_DVO1_MASK 0x000007FF +#define MCDE_TVDVOB_DVO1(__x) \ + MCDE_VAL2REG(MCDE_TVDVOB, DVO1, __x) +#define MCDE_TVDVOB_DVO2_SHIFT 16 +#define MCDE_TVDVOB_DVO2_MASK 0x07FF0000 +#define MCDE_TVDVOB_DVO2(__x) \ + MCDE_VAL2REG(MCDE_TVDVOB, DVO2, __x) +#define MCDE_TVTIM1A 0x0000084C +#define MCDE_TVTIM1A_GROUPOFFSET 0x200 +#define MCDE_TVTIM1A_DHO_SHIFT 0 +#define MCDE_TVTIM1A_DHO_MASK 0x000007FF +#define MCDE_TVTIM1A_DHO(__x) \ + MCDE_VAL2REG(MCDE_TVTIM1A, DHO, __x) +#define MCDE_TVTIM1B 0x00000A4C +#define MCDE_TVTIM1B_DHO_SHIFT 0 +#define MCDE_TVTIM1B_DHO_MASK 0x000007FF +#define MCDE_TVTIM1B_DHO(__x) \ + MCDE_VAL2REG(MCDE_TVTIM1B, DHO, __x) +#define MCDE_TVLBALWA 0x00000850 +#define MCDE_TVLBALWA_GROUPOFFSET 0x200 +#define MCDE_TVLBALWA_ALW_SHIFT 0 +#define MCDE_TVLBALWA_ALW_MASK 0x000007FF +#define MCDE_TVLBALWA_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, ALW, __x) +#define MCDE_TVLBALWA_LBW_SHIFT 16 +#define MCDE_TVLBALWA_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWA_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWA, LBW, __x) +#define MCDE_TVLBALWB 0x00000A50 +#define MCDE_TVLBALWB_ALW_SHIFT 0 +#define MCDE_TVLBALWB_ALW_MASK 0x000007FF +#define MCDE_TVLBALWB_ALW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, ALW, __x) +#define MCDE_TVLBALWB_LBW_SHIFT 16 +#define MCDE_TVLBALWB_LBW_MASK 0x07FF0000 +#define MCDE_TVLBALWB_LBW(__x) \ + MCDE_VAL2REG(MCDE_TVLBALWB, LBW, __x) +#define MCDE_TVBL2A 0x00000854 +#define MCDE_TVBL2A_GROUPOFFSET 0x200 +#define MCDE_TVBL2A_BEL2_SHIFT 0 +#define MCDE_TVBL2A_BEL2_MASK 0x000007FF +#define MCDE_TVBL2A_BEL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2A, BEL2, __x) +#define MCDE_TVBL2A_BSL2_SHIFT 16 +#define MCDE_TVBL2A_BSL2_MASK 0x07FF0000 +#define MCDE_TVBL2A_BSL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2A, BSL2, __x) +#define MCDE_TVBL2B 0x00000A54 +#define MCDE_TVBL2B_BEL2_SHIFT 0 +#define MCDE_TVBL2B_BEL2_MASK 0x000007FF +#define MCDE_TVBL2B_BEL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2B, BEL2, __x) +#define MCDE_TVBL2B_BSL2_SHIFT 16 +#define MCDE_TVBL2B_BSL2_MASK 0x07FF0000 +#define MCDE_TVBL2B_BSL2(__x) \ + MCDE_VAL2REG(MCDE_TVBL2B, BSL2, __x) +#define MCDE_TVBLUA 0x00000858 +#define MCDE_TVBLUA_GROUPOFFSET 0x200 +#define MCDE_TVBLUA_TVBLU_SHIFT 0 +#define MCDE_TVBLUA_TVBLU_MASK 0x000000FF +#define MCDE_TVBLUA_TVBLU(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBLU, __x) +#define MCDE_TVBLUA_TVBCB_SHIFT 8 +#define MCDE_TVBLUA_TVBCB_MASK 0x0000FF00 +#define MCDE_TVBLUA_TVBCB(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBCB, __x) +#define MCDE_TVBLUA_TVBCR_SHIFT 16 +#define MCDE_TVBLUA_TVBCR_MASK 0x00FF0000 +#define MCDE_TVBLUA_TVBCR(__x) \ + MCDE_VAL2REG(MCDE_TVBLUA, TVBCR, __x) +#define MCDE_TVBLUB 0x00000A58 +#define MCDE_TVBLUB_TVBLU_SHIFT 0 +#define MCDE_TVBLUB_TVBLU_MASK 0x000000FF +#define MCDE_TVBLUB_TVBLU(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBLU, __x) +#define MCDE_TVBLUB_TVBCB_SHIFT 8 +#define MCDE_TVBLUB_TVBCB_MASK 0x0000FF00 +#define MCDE_TVBLUB_TVBCB(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBCB, __x) +#define MCDE_TVBLUB_TVBCR_SHIFT 16 +#define MCDE_TVBLUB_TVBCR_MASK 0x00FF0000 +#define MCDE_TVBLUB_TVBCR(__x) \ + MCDE_VAL2REG(MCDE_TVBLUB, TVBCR, __x) +#define MCDE_LCDTIM0A 0x0000085C +#define MCDE_LCDTIM0A_GROUPOFFSET 0x200 +#define MCDE_LCDTIM0A_PSDEL0_SHIFT 0 +#define MCDE_LCDTIM0A_PSDEL0_MASK 0x000000FF +#define MCDE_LCDTIM0A_PSDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL0, __x) +#define MCDE_LCDTIM0A_PSDEL1_SHIFT 1 +#define MCDE_LCDTIM0A_PSDEL1_MASK 0x0000001E +#define MCDE_LCDTIM0A_PSDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSDEL1, __x) +#define MCDE_LCDTIM0A_PSLOADSEL_SHIFT 12 +#define MCDE_LCDTIM0A_PSLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM0A_PSLOADSEL_HBP 0 +#define MCDE_LCDTIM0A_PSLOADSEL_CLP 1 +#define MCDE_LCDTIM0A_PSLOADSEL_HFP 2 +#define MCDE_LCDTIM0A_PSLOADSEL_HSW 3 +#define MCDE_LCDTIM0A_PSLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, MCDE_LCDTIM0A_PSLOADSEL_##__x) +#define MCDE_LCDTIM0A_PSLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSLOADSEL, __x) +#define MCDE_LCDTIM0A_PSTGEN_SHIFT 14 +#define MCDE_LCDTIM0A_PSTGEN_MASK 0x00004000 +#define MCDE_LCDTIM0A_PSTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSTGEN, __x) +#define MCDE_LCDTIM0A_PSVAEN_SHIFT 15 +#define MCDE_LCDTIM0A_PSVAEN_MASK 0x00008000 +#define MCDE_LCDTIM0A_PSVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, PSVAEN, __x) +#define MCDE_LCDTIM0A_REVDEL0_SHIFT 16 +#define MCDE_LCDTIM0A_REVDEL0_MASK 0x00FF0000 +#define MCDE_LCDTIM0A_REVDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL0, __x) +#define MCDE_LCDTIM0A_REVDEL1_SHIFT 24 +#define MCDE_LCDTIM0A_REVDEL1_MASK 0x0F000000 +#define MCDE_LCDTIM0A_REVDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVDEL1, __x) +#define MCDE_LCDTIM0A_REVLOADSEL_SHIFT 28 +#define MCDE_LCDTIM0A_REVLOADSEL_MASK 0x30000000 +#define MCDE_LCDTIM0A_REVLOADSEL_HBP 0 +#define MCDE_LCDTIM0A_REVLOADSEL_CLP 1 +#define MCDE_LCDTIM0A_REVLOADSEL_HFP 2 +#define MCDE_LCDTIM0A_REVLOADSEL_HSW 3 +#define MCDE_LCDTIM0A_REVLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, MCDE_LCDTIM0A_REVLOADSEL_##__x) +#define MCDE_LCDTIM0A_REVLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVLOADSEL, __x) +#define MCDE_LCDTIM0A_REVTGEN_SHIFT 30 +#define MCDE_LCDTIM0A_REVTGEN_MASK 0x40000000 +#define MCDE_LCDTIM0A_REVTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVTGEN, __x) +#define MCDE_LCDTIM0A_REVVAEN_SHIFT 31 +#define MCDE_LCDTIM0A_REVVAEN_MASK 0x80000000 +#define MCDE_LCDTIM0A_REVVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0A, REVVAEN, __x) +#define MCDE_LCDTIM0B 0x00000A5C +#define MCDE_LCDTIM0B_PSDEL0_SHIFT 0 +#define MCDE_LCDTIM0B_PSDEL0_MASK 0x000000FF +#define MCDE_LCDTIM0B_PSDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL0, __x) +#define MCDE_LCDTIM0B_PSDEL1_SHIFT 1 +#define MCDE_LCDTIM0B_PSDEL1_MASK 0x0000001E +#define MCDE_LCDTIM0B_PSDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSDEL1, __x) +#define MCDE_LCDTIM0B_PSLOADSEL_SHIFT 12 +#define MCDE_LCDTIM0B_PSLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM0B_PSLOADSEL_HBP 0 +#define MCDE_LCDTIM0B_PSLOADSEL_CLP 1 +#define MCDE_LCDTIM0B_PSLOADSEL_HFP 2 +#define MCDE_LCDTIM0B_PSLOADSEL_HSW 3 +#define MCDE_LCDTIM0B_PSLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, MCDE_LCDTIM0B_PSLOADSEL_##__x) +#define MCDE_LCDTIM0B_PSLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSLOADSEL, __x) +#define MCDE_LCDTIM0B_PSTGEN_SHIFT 14 +#define MCDE_LCDTIM0B_PSTGEN_MASK 0x00004000 +#define MCDE_LCDTIM0B_PSTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSTGEN, __x) +#define MCDE_LCDTIM0B_PSVAEN_SHIFT 15 +#define MCDE_LCDTIM0B_PSVAEN_MASK 0x00008000 +#define MCDE_LCDTIM0B_PSVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, PSVAEN, __x) +#define MCDE_LCDTIM0B_REVDEL0_SHIFT 16 +#define MCDE_LCDTIM0B_REVDEL0_MASK 0x00FF0000 +#define MCDE_LCDTIM0B_REVDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL0, __x) +#define MCDE_LCDTIM0B_REVDEL1_SHIFT 24 +#define MCDE_LCDTIM0B_REVDEL1_MASK 0x0F000000 +#define MCDE_LCDTIM0B_REVDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVDEL1, __x) +#define MCDE_LCDTIM0B_REVLOADSEL_SHIFT 28 +#define MCDE_LCDTIM0B_REVLOADSEL_MASK 0x30000000 +#define MCDE_LCDTIM0B_REVLOADSEL_HBP 0 +#define MCDE_LCDTIM0B_REVLOADSEL_CLP 1 +#define MCDE_LCDTIM0B_REVLOADSEL_HFP 2 +#define MCDE_LCDTIM0B_REVLOADSEL_HSW 3 +#define MCDE_LCDTIM0B_REVLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, MCDE_LCDTIM0B_REVLOADSEL_##__x) +#define MCDE_LCDTIM0B_REVLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVLOADSEL, __x) +#define MCDE_LCDTIM0B_REVTGEN_SHIFT 30 +#define MCDE_LCDTIM0B_REVTGEN_MASK 0x40000000 +#define MCDE_LCDTIM0B_REVTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVTGEN, __x) +#define MCDE_LCDTIM0B_REVVAEN_SHIFT 31 +#define MCDE_LCDTIM0B_REVVAEN_MASK 0x80000000 +#define MCDE_LCDTIM0B_REVVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM0B, REVVAEN, __x) +#define MCDE_LCDTIM1A 0x00000860 +#define MCDE_LCDTIM1A_GROUPOFFSET 0x200 +#define MCDE_LCDTIM1A_SPLDEL0_SHIFT 0 +#define MCDE_LCDTIM1A_SPLDEL0_MASK 0x000000FF +#define MCDE_LCDTIM1A_SPLDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL0, __x) +#define MCDE_LCDTIM1A_SPLDEL1_SHIFT 8 +#define MCDE_LCDTIM1A_SPLDEL1_MASK 0x00000F00 +#define MCDE_LCDTIM1A_SPLDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLDEL1, __x) +#define MCDE_LCDTIM1A_SPLLOADSEL_SHIFT 12 +#define MCDE_LCDTIM1A_SPLLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM1A_SPLLOADSEL_HBP 0 +#define MCDE_LCDTIM1A_SPLLOADSEL_CLP 1 +#define MCDE_LCDTIM1A_SPLLOADSEL_HFP 2 +#define MCDE_LCDTIM1A_SPLLOADSEL_HSW 3 +#define MCDE_LCDTIM1A_SPLLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, MCDE_LCDTIM1A_SPLLOADSEL_##__x) +#define MCDE_LCDTIM1A_SPLLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLLOADSEL, __x) +#define MCDE_LCDTIM1A_SPLTGEN_SHIFT 14 +#define MCDE_LCDTIM1A_SPLTGEN_MASK 0x00004000 +#define MCDE_LCDTIM1A_SPLTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLTGEN, __x) +#define MCDE_LCDTIM1A_SPLVAEN_SHIFT 15 +#define MCDE_LCDTIM1A_SPLVAEN_MASK 0x00008000 +#define MCDE_LCDTIM1A_SPLVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, SPLVAEN, __x) +#define MCDE_LCDTIM1A_ICLSP_SHIFT 16 +#define MCDE_LCDTIM1A_ICLSP_MASK 0x00010000 +#define MCDE_LCDTIM1A_ICLSP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, ICLSP, __x) +#define MCDE_LCDTIM1A_ICLREV_SHIFT 17 +#define MCDE_LCDTIM1A_ICLREV_MASK 0x00020000 +#define MCDE_LCDTIM1A_ICLREV(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, ICLREV, __x) +#define MCDE_LCDTIM1A_LCLSPL_SHIFT 18 +#define MCDE_LCDTIM1A_LCLSPL_MASK 0x00040000 +#define MCDE_LCDTIM1A_LCLSPL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, LCLSPL, __x) +#define MCDE_LCDTIM1A_IVP_SHIFT 19 +#define MCDE_LCDTIM1A_IVP_MASK 0x00080000 +#define MCDE_LCDTIM1A_IVP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IVP, __x) +#define MCDE_LCDTIM1A_IVS_SHIFT 20 +#define MCDE_LCDTIM1A_IVS_MASK 0x00100000 +#define MCDE_LCDTIM1A_IVS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IVS, __x) +#define MCDE_LCDTIM1A_IHS_SHIFT 21 +#define MCDE_LCDTIM1A_IHS_MASK 0x00200000 +#define MCDE_LCDTIM1A_IHS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IHS, __x) +#define MCDE_LCDTIM1A_IPC_SHIFT 22 +#define MCDE_LCDTIM1A_IPC_MASK 0x00400000 +#define MCDE_LCDTIM1A_IPC(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IPC, __x) +#define MCDE_LCDTIM1A_IOE_SHIFT 23 +#define MCDE_LCDTIM1A_IOE_MASK 0x00800000 +#define MCDE_LCDTIM1A_IOE(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1A, IOE, __x) +#define MCDE_LCDTIM1B 0x00000A60 +#define MCDE_LCDTIM1B_SPLDEL0_SHIFT 0 +#define MCDE_LCDTIM1B_SPLDEL0_MASK 0x000000FF +#define MCDE_LCDTIM1B_SPLDEL0(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL0, __x) +#define MCDE_LCDTIM1B_SPLDEL1_SHIFT 8 +#define MCDE_LCDTIM1B_SPLDEL1_MASK 0x00000F00 +#define MCDE_LCDTIM1B_SPLDEL1(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLDEL1, __x) +#define MCDE_LCDTIM1B_SPLLOADSEL_SHIFT 12 +#define MCDE_LCDTIM1B_SPLLOADSEL_MASK 0x00003000 +#define MCDE_LCDTIM1B_SPLLOADSEL_HBP 0 +#define MCDE_LCDTIM1B_SPLLOADSEL_CLP 1 +#define MCDE_LCDTIM1B_SPLLOADSEL_HFP 2 +#define MCDE_LCDTIM1B_SPLLOADSEL_HSW 3 +#define MCDE_LCDTIM1B_SPLLOADSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, MCDE_LCDTIM1B_SPLLOADSEL_##__x) +#define MCDE_LCDTIM1B_SPLLOADSEL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLLOADSEL, __x) +#define MCDE_LCDTIM1B_SPLTGEN_SHIFT 14 +#define MCDE_LCDTIM1B_SPLTGEN_MASK 0x00004000 +#define MCDE_LCDTIM1B_SPLTGEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLTGEN, __x) +#define MCDE_LCDTIM1B_SPLVAEN_SHIFT 15 +#define MCDE_LCDTIM1B_SPLVAEN_MASK 0x00008000 +#define MCDE_LCDTIM1B_SPLVAEN(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, SPLVAEN, __x) +#define MCDE_LCDTIM1B_ICLSP_SHIFT 16 +#define MCDE_LCDTIM1B_ICLSP_MASK 0x00010000 +#define MCDE_LCDTIM1B_ICLSP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, ICLSP, __x) +#define MCDE_LCDTIM1B_ICLREV_SHIFT 17 +#define MCDE_LCDTIM1B_ICLREV_MASK 0x00020000 +#define MCDE_LCDTIM1B_ICLREV(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, ICLREV, __x) +#define MCDE_LCDTIM1B_LCLSPL_SHIFT 18 +#define MCDE_LCDTIM1B_LCLSPL_MASK 0x00040000 +#define MCDE_LCDTIM1B_LCLSPL(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, LCLSPL, __x) +#define MCDE_LCDTIM1B_IVP_SHIFT 19 +#define MCDE_LCDTIM1B_IVP_MASK 0x00080000 +#define MCDE_LCDTIM1B_IVP(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IVP, __x) +#define MCDE_LCDTIM1B_IVS_SHIFT 20 +#define MCDE_LCDTIM1B_IVS_MASK 0x00100000 +#define MCDE_LCDTIM1B_IVS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IVS, __x) +#define MCDE_LCDTIM1B_IHS_SHIFT 21 +#define MCDE_LCDTIM1B_IHS_MASK 0x00200000 +#define MCDE_LCDTIM1B_IHS(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IHS, __x) +#define MCDE_LCDTIM1B_IPC_SHIFT 22 +#define MCDE_LCDTIM1B_IPC_MASK 0x00400000 +#define MCDE_LCDTIM1B_IPC(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IPC, __x) +#define MCDE_LCDTIM1B_IOE_SHIFT 23 +#define MCDE_LCDTIM1B_IOE_MASK 0x00800000 +#define MCDE_LCDTIM1B_IOE(__x) \ + MCDE_VAL2REG(MCDE_LCDTIM1B, IOE, __x) +#define MCDE_DITCTRLA 0x00000864 +#define MCDE_DITCTRLA_GROUPOFFSET 0x200 +#define MCDE_DITCTRLA_TEMP_SHIFT 0 +#define MCDE_DITCTRLA_TEMP_MASK 0x00000001 +#define MCDE_DITCTRLA_TEMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, TEMP, __x) +#define MCDE_DITCTRLA_COMP_SHIFT 1 +#define MCDE_DITCTRLA_COMP_MASK 0x00000002 +#define MCDE_DITCTRLA_COMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, COMP, __x) +#define MCDE_DITCTRLA_MASK_SHIFT 4 +#define MCDE_DITCTRLA_MASK_MASK 0x00000010 +#define MCDE_DITCTRLA_MASK(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, MASK, __x) +#define MCDE_DITCTRLA_FOFFX_SHIFT 5 +#define MCDE_DITCTRLA_FOFFX_MASK 0x000003E0 +#define MCDE_DITCTRLA_FOFFX(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, FOFFX, __x) +#define MCDE_DITCTRLA_FOFFY_SHIFT 10 +#define MCDE_DITCTRLA_FOFFY_MASK 0x00007C00 +#define MCDE_DITCTRLA_FOFFY(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLA, FOFFY, __x) +#define MCDE_DITCTRLB 0x00000A64 +#define MCDE_DITCTRLB_TEMP_SHIFT 0 +#define MCDE_DITCTRLB_TEMP_MASK 0x00000001 +#define MCDE_DITCTRLB_TEMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, TEMP, __x) +#define MCDE_DITCTRLB_COMP_SHIFT 1 +#define MCDE_DITCTRLB_COMP_MASK 0x00000002 +#define MCDE_DITCTRLB_COMP(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, COMP, __x) +#define MCDE_DITCTRLB_MASK_SHIFT 4 +#define MCDE_DITCTRLB_MASK_MASK 0x00000010 +#define MCDE_DITCTRLB_MASK(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, MASK, __x) +#define MCDE_DITCTRLB_FOFFX_SHIFT 5 +#define MCDE_DITCTRLB_FOFFX_MASK 0x000003E0 +#define MCDE_DITCTRLB_FOFFX(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, FOFFX, __x) +#define MCDE_DITCTRLB_FOFFY_SHIFT 10 +#define MCDE_DITCTRLB_FOFFY_MASK 0x00007C00 +#define MCDE_DITCTRLB_FOFFY(__x) \ + MCDE_VAL2REG(MCDE_DITCTRLB, FOFFY, __x) +#define MCDE_DITOFFA 0x00000868 +#define MCDE_DITOFFA_GROUPOFFSET 0x200 +#define MCDE_DITOFFA_XG_SHIFT 0 +#define MCDE_DITOFFA_XG_MASK 0x0000001F +#define MCDE_DITOFFA_XG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, XG, __x) +#define MCDE_DITOFFA_YG_SHIFT 8 +#define MCDE_DITOFFA_YG_MASK 0x00001F00 +#define MCDE_DITOFFA_YG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, YG, __x) +#define MCDE_DITOFFA_XB_SHIFT 16 +#define MCDE_DITOFFA_XB_MASK 0x001F0000 +#define MCDE_DITOFFA_XB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, XB, __x) +#define MCDE_DITOFFA_YB_SHIFT 24 +#define MCDE_DITOFFA_YB_MASK 0x1F000000 +#define MCDE_DITOFFA_YB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFA, YB, __x) +#define MCDE_DITOFFB 0x00000A68 +#define MCDE_DITOFFB_XG_SHIFT 0 +#define MCDE_DITOFFB_XG_MASK 0x0000001F +#define MCDE_DITOFFB_XG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, XG, __x) +#define MCDE_DITOFFB_YG_SHIFT 8 +#define MCDE_DITOFFB_YG_MASK 0x00001F00 +#define MCDE_DITOFFB_YG(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, YG, __x) +#define MCDE_DITOFFB_XB_SHIFT 16 +#define MCDE_DITOFFB_XB_MASK 0x001F0000 +#define MCDE_DITOFFB_XB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, XB, __x) +#define MCDE_DITOFFB_YB_SHIFT 24 +#define MCDE_DITOFFB_YB_MASK 0x1F000000 +#define MCDE_DITOFFB_YB(__x) \ + MCDE_VAL2REG(MCDE_DITOFFB, YB, __x) +#define MCDE_PAL0A 0x0000086C +#define MCDE_PAL0A_GROUPOFFSET 0x200 +#define MCDE_PAL0A_BLUE_SHIFT 0 +#define MCDE_PAL0A_BLUE_MASK 0x00000FFF +#define MCDE_PAL0A_BLUE(__x) \ + MCDE_VAL2REG(MCDE_PAL0A, BLUE, __x) +#define MCDE_PAL0A_GREEN_SHIFT 16 +#define MCDE_PAL0A_GREEN_MASK 0x0FFF0000 +#define MCDE_PAL0A_GREEN(__x) \ + MCDE_VAL2REG(MCDE_PAL0A, GREEN, __x) +#define MCDE_PAL0B 0x00000A6C +#define MCDE_PAL0B_BLUE_SHIFT 0 +#define MCDE_PAL0B_BLUE_MASK 0x00000FFF +#define MCDE_PAL0B_BLUE(__x) \ + MCDE_VAL2REG(MCDE_PAL0B, BLUE, __x) +#define MCDE_PAL0B_GREEN_SHIFT 16 +#define MCDE_PAL0B_GREEN_MASK 0x0FFF0000 +#define MCDE_PAL0B_GREEN(__x) \ + MCDE_VAL2REG(MCDE_PAL0B, GREEN, __x) +#define MCDE_PAL1A 0x00000870 +#define MCDE_PAL1A_GROUPOFFSET 0x200 +#define MCDE_PAL1A_RED_SHIFT 0 +#define MCDE_PAL1A_RED_MASK 0x00000FFF +#define MCDE_PAL1A_RED(__x) \ + MCDE_VAL2REG(MCDE_PAL1A, RED, __x) +#define MCDE_PAL1B 0x00000A70 +#define MCDE_PAL1B_RED_SHIFT 0 +#define MCDE_PAL1B_RED_MASK 0x00000FFF +#define MCDE_PAL1B_RED(__x) \ + MCDE_VAL2REG(MCDE_PAL1B, RED, __x) +#define MCDE_ROTADD0A 0x00000874 +#define MCDE_ROTADD0A_GROUPOFFSET 0x200 +#define MCDE_ROTADD0A_ROTADD0_SHIFT 0 +#define MCDE_ROTADD0A_ROTADD0_MASK 0xFFFFFFFF +#define MCDE_ROTADD0A_ROTADD0(__x) \ + MCDE_VAL2REG(MCDE_ROTADD0A, ROTADD0, __x) +#define MCDE_ROTADD0B 0x00000A74 +#define MCDE_ROTADD0B_ROTADD0_SHIFT 0 +#define MCDE_ROTADD0B_ROTADD0_MASK 0xFFFFFFFF +#define MCDE_ROTADD0B_ROTADD0(__x) \ + MCDE_VAL2REG(MCDE_ROTADD0B, ROTADD0, __x) +#define MCDE_ROTADD1A 0x00000878 +#define MCDE_ROTADD1A_GROUPOFFSET 0x200 +#define MCDE_ROTADD1A_ROTADD1_SHIFT 0 +#define MCDE_ROTADD1A_ROTADD1_MASK 0xFFFFFFFF +#define MCDE_ROTADD1A_ROTADD1(__x) \ + MCDE_VAL2REG(MCDE_ROTADD1A, ROTADD1, __x) +#define MCDE_ROTADD1B 0x00000A78 +#define MCDE_ROTADD1B_ROTADD1_SHIFT 0 +#define MCDE_ROTADD1B_ROTADD1_MASK 0xFFFFFFFF +#define MCDE_ROTADD1B_ROTADD1(__x) \ + MCDE_VAL2REG(MCDE_ROTADD1B, ROTADD1, __x) +#define MCDE_ROTACONF 0x0000087C +#define MCDE_ROTACONF_GROUPOFFSET 0x200 +#define MCDE_ROTACONF_ROTBURSTSIZE_SHIFT 0 +#define MCDE_ROTACONF_ROTBURSTSIZE_MASK 0x00000003 +#define MCDE_ROTACONF_ROTBURSTSIZE_1W 0 +#define MCDE_ROTACONF_ROTBURSTSIZE_2W 1 +#define MCDE_ROTACONF_ROTBURSTSIZE_4W 2 +#define MCDE_ROTACONF_ROTBURSTSIZE_8W 3 +#define MCDE_ROTACONF_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, \ + MCDE_ROTACONF_ROTBURSTSIZE_##__x) +#define MCDE_ROTACONF_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE, __x) +#define MCDE_ROTACONF_ROTBURSTSIZE_HW_SHIFT 2 +#define MCDE_ROTACONF_ROTBURSTSIZE_HW_MASK 0x00000004 +#define MCDE_ROTACONF_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTBURSTSIZE_HW, __x) +#define MCDE_ROTACONF_ROTDIR_SHIFT 3 +#define MCDE_ROTACONF_ROTDIR_MASK 0x00000008 +#define MCDE_ROTACONF_ROTDIR_CCW 0 +#define MCDE_ROTACONF_ROTDIR_CW 1 +#define MCDE_ROTACONF_ROTDIR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTDIR, MCDE_ROTACONF_ROTDIR_##__x) +#define MCDE_ROTACONF_ROTDIR(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, ROTDIR, __x) +#define MCDE_ROTACONF_WR_MAXOUT_SHIFT 4 +#define MCDE_ROTACONF_WR_MAXOUT_MASK 0x00000030 +#define MCDE_ROTACONF_WR_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, WR_MAXOUT, __x) +#define MCDE_ROTACONF_RD_MAXOUT_SHIFT 6 +#define MCDE_ROTACONF_RD_MAXOUT_MASK 0x000000C0 +#define MCDE_ROTACONF_RD_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, RD_MAXOUT, __x) +#define MCDE_ROTACONF_STRIP_WIDTH_SHIFT 8 +#define MCDE_ROTACONF_STRIP_WIDTH_MASK 0x0000FF00 +#define MCDE_ROTACONF_STRIP_WIDTH_2PIX 0 +#define MCDE_ROTACONF_STRIP_WIDTH_4PIX 1 +#define MCDE_ROTACONF_STRIP_WIDTH_8PIX 2 +#define MCDE_ROTACONF_STRIP_WIDTH_16PIX 3 +#define MCDE_ROTACONF_STRIP_WIDTH_32PIX 4 +#define MCDE_ROTACONF_STRIP_WIDTH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, STRIP_WIDTH, \ + MCDE_ROTACONF_STRIP_WIDTH_##__x) +#define MCDE_ROTACONF_STRIP_WIDTH(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, STRIP_WIDTH, __x) +#define MCDE_ROTACONF_WR_ROPC_SHIFT 16 +#define MCDE_ROTACONF_WR_ROPC_MASK 0x00FF0000 +#define MCDE_ROTACONF_WR_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, WR_ROPC, __x) +#define MCDE_ROTACONF_RD_ROPC_SHIFT 24 +#define MCDE_ROTACONF_RD_ROPC_MASK 0xFF000000 +#define MCDE_ROTACONF_RD_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTACONF, RD_ROPC, __x) +#define MCDE_ROTBCONF 0x00000A7C +#define MCDE_ROTBCONF_ROTBURSTSIZE_SHIFT 0 +#define MCDE_ROTBCONF_ROTBURSTSIZE_MASK 0x00000003 +#define MCDE_ROTBCONF_ROTBURSTSIZE_1W 0 +#define MCDE_ROTBCONF_ROTBURSTSIZE_2W 1 +#define MCDE_ROTBCONF_ROTBURSTSIZE_4W 2 +#define MCDE_ROTBCONF_ROTBURSTSIZE_8W 3 +#define MCDE_ROTBCONF_ROTBURSTSIZE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, \ + MCDE_ROTBCONF_ROTBURSTSIZE_##__x) +#define MCDE_ROTBCONF_ROTBURSTSIZE(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE, __x) +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_SHIFT 2 +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW_MASK 0x00000004 +#define MCDE_ROTBCONF_ROTBURSTSIZE_HW(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTBURSTSIZE_HW, __x) +#define MCDE_ROTBCONF_ROTDIR_SHIFT 3 +#define MCDE_ROTBCONF_ROTDIR_MASK 0x00000008 +#define MCDE_ROTBCONF_ROTDIR_CCW 0 +#define MCDE_ROTBCONF_ROTDIR_CW 1 +#define MCDE_ROTBCONF_ROTDIR_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTDIR, MCDE_ROTBCONF_ROTDIR_##__x) +#define MCDE_ROTBCONF_ROTDIR(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, ROTDIR, __x) +#define MCDE_ROTBCONF_WR_MAXOUT_SHIFT 4 +#define MCDE_ROTBCONF_WR_MAXOUT_MASK 0x00000030 +#define MCDE_ROTBCONF_WR_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, WR_MAXOUT, __x) +#define MCDE_ROTBCONF_RD_MAXOUT_SHIFT 6 +#define MCDE_ROTBCONF_RD_MAXOUT_MASK 0x000000C0 +#define MCDE_ROTBCONF_RD_MAXOUT(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, RD_MAXOUT, __x) +#define MCDE_ROTBCONF_STRIP_WIDTH_SHIFT 8 +#define MCDE_ROTBCONF_STRIP_WIDTH_MASK 0x0000FF00 +#define MCDE_ROTBCONF_STRIP_WIDTH_2PIX 0 +#define MCDE_ROTBCONF_STRIP_WIDTH_4PIX 1 +#define MCDE_ROTBCONF_STRIP_WIDTH_8PIX 2 +#define MCDE_ROTBCONF_STRIP_WIDTH_16PIX 3 +#define MCDE_ROTBCONF_STRIP_WIDTH_32PIX 4 +#define MCDE_ROTBCONF_STRIP_WIDTH_ENUM(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, STRIP_WIDTH, \ + MCDE_ROTBCONF_STRIP_WIDTH_##__x) +#define MCDE_ROTBCONF_STRIP_WIDTH(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, STRIP_WIDTH, __x) +#define MCDE_ROTBCONF_WR_ROPC_SHIFT 16 +#define MCDE_ROTBCONF_WR_ROPC_MASK 0x00FF0000 +#define MCDE_ROTBCONF_WR_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, WR_ROPC, __x) +#define MCDE_ROTBCONF_RD_ROPC_SHIFT 24 +#define MCDE_ROTBCONF_RD_ROPC_MASK 0xFF000000 +#define MCDE_ROTBCONF_RD_ROPC(__x) \ + MCDE_VAL2REG(MCDE_ROTBCONF, RD_ROPC, __x) +#define MCDE_SYNCHCONFA 0x00000880 +#define MCDE_SYNCHCONFA_GROUPOFFSET 0x200 +#define MCDE_SYNCHCONFA_HWREQVEVENT_SHIFT 0 +#define MCDE_SYNCHCONFA_HWREQVEVENT_MASK 0x00000003 +#define MCDE_SYNCHCONFA_HWREQVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFA_HWREQVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFA_HWREQVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFA_HWREQVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFA_HWREQVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVEVENT, \ + MCDE_SYNCHCONFA_HWREQVEVENT_##__x) +#define MCDE_SYNCHCONFA_HWREQVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVEVENT, __x) +#define MCDE_SYNCHCONFA_HWREQVCNT_SHIFT 2 +#define MCDE_SYNCHCONFA_HWREQVCNT_MASK 0x0000FFFC +#define MCDE_SYNCHCONFA_HWREQVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, HWREQVCNT, __x) +#define MCDE_SYNCHCONFA_SWINTVEVENT_SHIFT 16 +#define MCDE_SYNCHCONFA_SWINTVEVENT_MASK 0x00030000 +#define MCDE_SYNCHCONFA_SWINTVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFA_SWINTVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFA_SWINTVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFA_SWINTVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFA_SWINTVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVEVENT, \ + MCDE_SYNCHCONFA_SWINTVEVENT_##__x) +#define MCDE_SYNCHCONFA_SWINTVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVEVENT, __x) +#define MCDE_SYNCHCONFA_SWINTVCNT_SHIFT 18 +#define MCDE_SYNCHCONFA_SWINTVCNT_MASK 0xFFFC0000 +#define MCDE_SYNCHCONFA_SWINTVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFA, SWINTVCNT, __x) +#define MCDE_SYNCHCONFB 0x00000A80 +#define MCDE_SYNCHCONFB_HWREQVEVENT_SHIFT 0 +#define MCDE_SYNCHCONFB_HWREQVEVENT_MASK 0x00000003 +#define MCDE_SYNCHCONFB_HWREQVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFB_HWREQVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFB_HWREQVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFB_HWREQVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFB_HWREQVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVEVENT, \ + MCDE_SYNCHCONFB_HWREQVEVENT_##__x) +#define MCDE_SYNCHCONFB_HWREQVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVEVENT, __x) +#define MCDE_SYNCHCONFB_HWREQVCNT_SHIFT 2 +#define MCDE_SYNCHCONFB_HWREQVCNT_MASK 0x0000FFFC +#define MCDE_SYNCHCONFB_HWREQVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, HWREQVCNT, __x) +#define MCDE_SYNCHCONFB_SWINTVEVENT_SHIFT 16 +#define MCDE_SYNCHCONFB_SWINTVEVENT_MASK 0x00030000 +#define MCDE_SYNCHCONFB_SWINTVEVENT_VSYNC 0 +#define MCDE_SYNCHCONFB_SWINTVEVENT_BACK_PORCH 1 +#define MCDE_SYNCHCONFB_SWINTVEVENT_ACTIVE_VIDEO 2 +#define MCDE_SYNCHCONFB_SWINTVEVENT_FRONT_PORCH 3 +#define MCDE_SYNCHCONFB_SWINTVEVENT_ENUM(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVEVENT, \ + MCDE_SYNCHCONFB_SWINTVEVENT_##__x) +#define MCDE_SYNCHCONFB_SWINTVEVENT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVEVENT, __x) +#define MCDE_SYNCHCONFB_SWINTVCNT_SHIFT 18 +#define MCDE_SYNCHCONFB_SWINTVCNT_MASK 0xFFFC0000 +#define MCDE_SYNCHCONFB_SWINTVCNT(__x) \ + MCDE_VAL2REG(MCDE_SYNCHCONFB, SWINTVCNT, __x) +#define MCDE_GAM0A 0x00000888 +#define MCDE_GAM0A_GROUPOFFSET 0x200 +#define MCDE_GAM0A_BLUE_SHIFT 0 +#define MCDE_GAM0A_BLUE_MASK 0x00FFFFFF +#define MCDE_GAM0A_BLUE(__x) \ + MCDE_VAL2REG(MCDE_GAM0A, BLUE, __x) +#define MCDE_GAM0B 0x00000A88 +#define MCDE_GAM0B_BLUE_SHIFT 0 +#define MCDE_GAM0B_BLUE_MASK 0x00FFFFFF +#define MCDE_GAM0B_BLUE(__x) \ + MCDE_VAL2REG(MCDE_GAM0B, BLUE, __x) +#define MCDE_GAM1A 0x0000088C +#define MCDE_GAM1A_GROUPOFFSET 0x200 +#define MCDE_GAM1A_GREEN_SHIFT 0 +#define MCDE_GAM1A_GREEN_MASK 0x00FFFFFF +#define MCDE_GAM1A_GREEN(__x) \ + MCDE_VAL2REG(MCDE_GAM1A, GREEN, __x) +#define MCDE_GAM1B 0x00000A8C +#define MCDE_GAM1B_GREEN_SHIFT 0 +#define MCDE_GAM1B_GREEN_MASK 0x00FFFFFF +#define MCDE_GAM1B_GREEN(__x) \ + MCDE_VAL2REG(MCDE_GAM1B, GREEN, __x) +#define MCDE_GAM2A 0x00000890 +#define MCDE_GAM2A_GROUPOFFSET 0x200 +#define MCDE_GAM2A_RED_SHIFT 0 +#define MCDE_GAM2A_RED_MASK 0x00FFFFFF +#define MCDE_GAM2A_RED(__x) \ + MCDE_VAL2REG(MCDE_GAM2A, RED, __x) +#define MCDE_GAM2B 0x00000A90 +#define MCDE_GAM2B_RED_SHIFT 0 +#define MCDE_GAM2B_RED_MASK 0x00FFFFFF +#define MCDE_GAM2B_RED(__x) \ + MCDE_VAL2REG(MCDE_GAM2B, RED, __x) +#define MCDE_OLEDCONV1A 0x00000894 +#define MCDE_OLEDCONV1A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV1A_ALPHA_RED_SHIFT 0 +#define MCDE_OLEDCONV1A_ALPHA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV1A_ALPHA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1A, ALPHA_RED, __x) +#define MCDE_OLEDCONV1A_ALPHA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV1A_ALPHA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV1A_ALPHA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1A, ALPHA_GREEN, __x) +#define MCDE_OLEDCONV1B 0x00000A94 +#define MCDE_OLEDCONV1B_ALPHA_RED_SHIFT 0 +#define MCDE_OLEDCONV1B_ALPHA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV1B_ALPHA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1B, ALPHA_RED, __x) +#define MCDE_OLEDCONV1B_ALPHA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV1B_ALPHA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV1B_ALPHA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV1B, ALPHA_GREEN, __x) +#define MCDE_OLEDCONV2A 0x00000898 +#define MCDE_OLEDCONV2A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV2A_ALPHA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV2A_ALPHA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV2A_ALPHA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2A, ALPHA_BLUE, __x) +#define MCDE_OLEDCONV2A_BETA_RED_SHIFT 16 +#define MCDE_OLEDCONV2A_BETA_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV2A_BETA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2A, BETA_RED, __x) +#define MCDE_OLEDCONV2B 0x00000A98 +#define MCDE_OLEDCONV2B_ALPHA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV2B_ALPHA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV2B_ALPHA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2B, ALPHA_BLUE, __x) +#define MCDE_OLEDCONV2B_BETA_RED_SHIFT 16 +#define MCDE_OLEDCONV2B_BETA_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV2B_BETA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV2B, BETA_RED, __x) +#define MCDE_OLEDCONV3A 0x0000089C +#define MCDE_OLEDCONV3A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV3A_BETA_GREEN_SHIFT 0 +#define MCDE_OLEDCONV3A_BETA_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV3A_BETA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3A, BETA_GREEN, __x) +#define MCDE_OLEDCONV3A_BETA_BLUE_SHIFT 16 +#define MCDE_OLEDCONV3A_BETA_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV3A_BETA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3A, BETA_BLUE, __x) +#define MCDE_OLEDCONV3B 0x00000A9C +#define MCDE_OLEDCONV3B_BETA_GREEN_SHIFT 0 +#define MCDE_OLEDCONV3B_BETA_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV3B_BETA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3B, BETA_GREEN, __x) +#define MCDE_OLEDCONV3B_BETA_BLUE_SHIFT 16 +#define MCDE_OLEDCONV3B_BETA_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV3B_BETA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV3B, BETA_BLUE, __x) +#define MCDE_OLEDCONV4A 0x000008A0 +#define MCDE_OLEDCONV4A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV4A_GAMMA_RED_SHIFT 0 +#define MCDE_OLEDCONV4A_GAMMA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV4A_GAMMA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4A, GAMMA_RED, __x) +#define MCDE_OLEDCONV4A_GAMMA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV4A_GAMMA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV4A_GAMMA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4A, GAMMA_GREEN, __x) +#define MCDE_OLEDCONV4B 0x00000AA0 +#define MCDE_OLEDCONV4B_GAMMA_RED_SHIFT 0 +#define MCDE_OLEDCONV4B_GAMMA_RED_MASK 0x00003FFF +#define MCDE_OLEDCONV4B_GAMMA_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4B, GAMMA_RED, __x) +#define MCDE_OLEDCONV4B_GAMMA_GREEN_SHIFT 16 +#define MCDE_OLEDCONV4B_GAMMA_GREEN_MASK 0x3FFF0000 +#define MCDE_OLEDCONV4B_GAMMA_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV4B, GAMMA_GREEN, __x) +#define MCDE_OLEDCONV5A 0x000008A4 +#define MCDE_OLEDCONV5A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV5A_GAMMA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV5A_GAMMA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV5A_GAMMA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5A, GAMMA_BLUE, __x) +#define MCDE_OLEDCONV5A_OFF_RED_SHIFT 16 +#define MCDE_OLEDCONV5A_OFF_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV5A_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5A, OFF_RED, __x) +#define MCDE_OLEDCONV5B 0x00000AA4 +#define MCDE_OLEDCONV5B_GAMMA_BLUE_SHIFT 0 +#define MCDE_OLEDCONV5B_GAMMA_BLUE_MASK 0x00003FFF +#define MCDE_OLEDCONV5B_GAMMA_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5B, GAMMA_BLUE, __x) +#define MCDE_OLEDCONV5B_OFF_RED_SHIFT 16 +#define MCDE_OLEDCONV5B_OFF_RED_MASK 0x3FFF0000 +#define MCDE_OLEDCONV5B_OFF_RED(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV5B, OFF_RED, __x) +#define MCDE_OLEDCONV6A 0x000008A8 +#define MCDE_OLEDCONV6A_GROUPOFFSET 0x200 +#define MCDE_OLEDCONV6A_OFF_GREEN_SHIFT 0 +#define MCDE_OLEDCONV6A_OFF_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV6A_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6A, OFF_GREEN, __x) +#define MCDE_OLEDCONV6A_OFF_BLUE_SHIFT 16 +#define MCDE_OLEDCONV6A_OFF_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV6A_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6A, OFF_BLUE, __x) +#define MCDE_OLEDCONV6B 0x00000AA8 +#define MCDE_OLEDCONV6B_OFF_GREEN_SHIFT 0 +#define MCDE_OLEDCONV6B_OFF_GREEN_MASK 0x00003FFF +#define MCDE_OLEDCONV6B_OFF_GREEN(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6B, OFF_GREEN, __x) +#define MCDE_OLEDCONV6B_OFF_BLUE_SHIFT 16 +#define MCDE_OLEDCONV6B_OFF_BLUE_MASK 0x3FFF0000 +#define MCDE_OLEDCONV6B_OFF_BLUE(__x) \ + MCDE_VAL2REG(MCDE_OLEDCONV6B, OFF_BLUE, __x) +#define MCDE_CRC 0x00000C00 +#define MCDE_CRC_FLOEN_SHIFT 0 +#define MCDE_CRC_FLOEN_MASK 0x00000001 +#define MCDE_CRC_FLOEN(__x) \ + MCDE_VAL2REG(MCDE_CRC, FLOEN, __x) +#define MCDE_CRC_POWEREN_SHIFT 1 +#define MCDE_CRC_POWEREN_MASK 0x00000002 +#define MCDE_CRC_POWEREN(__x) \ + MCDE_VAL2REG(MCDE_CRC, POWEREN, __x) +#define MCDE_CRC_C1EN_SHIFT 2 +#define MCDE_CRC_C1EN_MASK 0x00000004 +#define MCDE_CRC_C1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, C1EN, __x) +#define MCDE_CRC_C2EN_SHIFT 3 +#define MCDE_CRC_C2EN_MASK 0x00000008 +#define MCDE_CRC_C2EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, C2EN, __x) +#define MCDE_CRC_WMLVL1_SHIFT 4 +#define MCDE_CRC_WMLVL1_MASK 0x00000010 +#define MCDE_CRC_WMLVL1(__x) \ + MCDE_VAL2REG(MCDE_CRC, WMLVL1, __x) +#define MCDE_CRC_WMLVL2_SHIFT 5 +#define MCDE_CRC_WMLVL2_MASK 0x00000020 +#define MCDE_CRC_WMLVL2(__x) \ + MCDE_VAL2REG(MCDE_CRC, WMLVL2, __x) +#define MCDE_CRC_SYNCSEL_SHIFT 6 +#define MCDE_CRC_SYNCSEL_MASK 0x00000040 +#define MCDE_CRC_SYNCSEL(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCSEL, __x) +#define MCDE_CRC_SYCEN0_SHIFT 7 +#define MCDE_CRC_SYCEN0_MASK 0x00000080 +#define MCDE_CRC_SYCEN0(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYCEN0, __x) +#define MCDE_CRC_SYCEN1_SHIFT 8 +#define MCDE_CRC_SYCEN1_MASK 0x00000100 +#define MCDE_CRC_SYCEN1(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYCEN1, __x) +#define MCDE_CRC_SIZE1_SHIFT 9 +#define MCDE_CRC_SIZE1_MASK 0x00000200 +#define MCDE_CRC_SIZE1(__x) \ + MCDE_VAL2REG(MCDE_CRC, SIZE1, __x) +#define MCDE_CRC_SIZE2_SHIFT 10 +#define MCDE_CRC_SIZE2_MASK 0x00000400 +#define MCDE_CRC_SIZE2(__x) \ + MCDE_VAL2REG(MCDE_CRC, SIZE2, __x) +#define MCDE_CRC_INBAND1_SHIFT 11 +#define MCDE_CRC_INBAND1_MASK 0x00000800 +#define MCDE_CRC_INBAND1(__x) \ + MCDE_VAL2REG(MCDE_CRC, INBAND1, __x) +#define MCDE_CRC_INBAND2_SHIFT 12 +#define MCDE_CRC_INBAND2_MASK 0x00001000 +#define MCDE_CRC_INBAND2(__x) \ + MCDE_VAL2REG(MCDE_CRC, INBAND2, __x) +#define MCDE_CRC_CLKSEL_SHIFT 13 +#define MCDE_CRC_CLKSEL_MASK 0x00006000 +#define MCDE_CRC_CLKSEL_166MHz 0 +#define MCDE_CRC_CLKSEL_48MHz 1 +#define MCDE_CRC_CLKSEL_LCD 2 +#define MCDE_CRC_CLKSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLKSEL, MCDE_CRC_CLKSEL_##__x) +#define MCDE_CRC_CLKSEL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLKSEL, __x) +#define MCDE_CRC_YUVCONVC1EN_SHIFT 15 +#define MCDE_CRC_YUVCONVC1EN_MASK 0x00008000 +#define MCDE_CRC_YUVCONVC1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, YUVCONVC1EN, __x) +#define MCDE_CRC_CS1EN_SHIFT 16 +#define MCDE_CRC_CS1EN_MASK 0x00010000 +#define MCDE_CRC_CS1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS1EN, __x) +#define MCDE_CRC_CS2EN_SHIFT 17 +#define MCDE_CRC_CS2EN_MASK 0x00020000 +#define MCDE_CRC_CS2EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS2EN, __x) +#define MCDE_CRC_RESEN_SHIFT 18 +#define MCDE_CRC_RESEN_MASK 0x00040000 +#define MCDE_CRC_RESEN(__x) \ + MCDE_VAL2REG(MCDE_CRC, RESEN, __x) +#define MCDE_CRC_CS1POL_SHIFT 19 +#define MCDE_CRC_CS1POL_MASK 0x00080000 +#define MCDE_CRC_CS1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS1POL, __x) +#define MCDE_CRC_CS2POL_SHIFT 20 +#define MCDE_CRC_CS2POL_MASK 0x00100000 +#define MCDE_CRC_CS2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CS2POL, __x) +#define MCDE_CRC_CD1POL_SHIFT 21 +#define MCDE_CRC_CD1POL_MASK 0x00200000 +#define MCDE_CRC_CD1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CD1POL, __x) +#define MCDE_CRC_CD2POL_SHIFT 22 +#define MCDE_CRC_CD2POL_MASK 0x00400000 +#define MCDE_CRC_CD2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, CD2POL, __x) +#define MCDE_CRC_WR1POL_SHIFT 23 +#define MCDE_CRC_WR1POL_MASK 0x00800000 +#define MCDE_CRC_WR1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, WR1POL, __x) +#define MCDE_CRC_WR2POL_SHIFT 24 +#define MCDE_CRC_WR2POL_MASK 0x01000000 +#define MCDE_CRC_WR2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, WR2POL, __x) +#define MCDE_CRC_RD1POL_SHIFT 25 +#define MCDE_CRC_RD1POL_MASK 0x02000000 +#define MCDE_CRC_RD1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RD1POL, __x) +#define MCDE_CRC_RD2POL_SHIFT 26 +#define MCDE_CRC_RD2POL_MASK 0x04000000 +#define MCDE_CRC_RD2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RD2POL, __x) +#define MCDE_CRC_RES1POL_SHIFT 27 +#define MCDE_CRC_RES1POL_MASK 0x08000000 +#define MCDE_CRC_RES1POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RES1POL, __x) +#define MCDE_CRC_RES2POL_SHIFT 28 +#define MCDE_CRC_RES2POL_MASK 0x10000000 +#define MCDE_CRC_RES2POL(__x) \ + MCDE_VAL2REG(MCDE_CRC, RES2POL, __x) +#define MCDE_CRC_SYNCCTRL_SHIFT 29 +#define MCDE_CRC_SYNCCTRL_MASK 0x60000000 +#define MCDE_CRC_SYNCCTRL_OFF 0 +#define MCDE_CRC_SYNCCTRL_C0 1 +#define MCDE_CRC_SYNCCTRL_C1 2 +#define MCDE_CRC_SYNCCTRL_PING_PONG 3 +#define MCDE_CRC_SYNCCTRL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCCTRL, MCDE_CRC_SYNCCTRL_##__x) +#define MCDE_CRC_SYNCCTRL(__x) \ + MCDE_VAL2REG(MCDE_CRC, SYNCCTRL, __x) +#define MCDE_CRC_CLAMPC1EN_SHIFT 31 +#define MCDE_CRC_CLAMPC1EN_MASK 0x80000000 +#define MCDE_CRC_CLAMPC1EN(__x) \ + MCDE_VAL2REG(MCDE_CRC, CLAMPC1EN, __x) +#define MCDE_PBCCRC0 0x00000C04 +#define MCDE_PBCCRC0_GROUPOFFSET 0x4 +#define MCDE_PBCCRC0_BSCM_SHIFT 0 +#define MCDE_PBCCRC0_BSCM_MASK 0x00000007 +#define MCDE_PBCCRC0_BSCM_1_8BIT 0 +#define MCDE_PBCCRC0_BSCM_2_8BIT 1 +#define MCDE_PBCCRC0_BSCM_3_8BIT 2 +#define MCDE_PBCCRC0_BSCM_1_16BIT 3 +#define MCDE_PBCCRC0_BSCM_2_16BIT 4 +#define MCDE_PBCCRC0_BSCM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSCM, MCDE_PBCCRC0_BSCM_##__x) +#define MCDE_PBCCRC0_BSCM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSCM, __x) +#define MCDE_PBCCRC0_BSDM_SHIFT 3 +#define MCDE_PBCCRC0_BSDM_MASK 0x00000038 +#define MCDE_PBCCRC0_BSDM_1_8BIT 0 +#define MCDE_PBCCRC0_BSDM_2_8BIT 1 +#define MCDE_PBCCRC0_BSDM_3_8BIT 2 +#define MCDE_PBCCRC0_BSDM_1_16BIT 3 +#define MCDE_PBCCRC0_BSDM_2_16BIT 4 +#define MCDE_PBCCRC0_BSDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSDM, MCDE_PBCCRC0_BSDM_##__x) +#define MCDE_PBCCRC0_BSDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BSDM, __x) +#define MCDE_PBCCRC0_PDM_SHIFT 6 +#define MCDE_PBCCRC0_PDM_MASK 0x000000C0 +#define MCDE_PBCCRC0_PDM_NORMAL 0 +#define MCDE_PBCCRC0_PDM_16_TO_32 1 +#define MCDE_PBCCRC0_PDM_24_TO_32_RIGHT 2 +#define MCDE_PBCCRC0_PDM_24_TO_32_LEFT 3 +#define MCDE_PBCCRC0_PDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDM, MCDE_PBCCRC0_PDM_##__x) +#define MCDE_PBCCRC0_PDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDM, __x) +#define MCDE_PBCCRC0_PDCTRL_SHIFT 12 +#define MCDE_PBCCRC0_PDCTRL_MASK 0x00001000 +#define MCDE_PBCCRC0_PDCTRL(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, PDCTRL, __x) +#define MCDE_PBCCRC0_BPP_SHIFT 13 +#define MCDE_PBCCRC0_BPP_MASK 0x0000E000 +#define MCDE_PBCCRC0_BPP_8BPP 0 +#define MCDE_PBCCRC0_BPP_12BPP 1 +#define MCDE_PBCCRC0_BPP_15BPP 2 +#define MCDE_PBCCRC0_BPP_16BPP 3 +#define MCDE_PBCCRC0_BPP_18BPP 4 +#define MCDE_PBCCRC0_BPP_24BPP 5 +#define MCDE_PBCCRC0_BPP(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC0, BPP, __x) +#define MCDE_PBCCRC1 0x00000C08 +#define MCDE_PBCCRC1_BSCM_SHIFT 0 +#define MCDE_PBCCRC1_BSCM_MASK 0x00000007 +#define MCDE_PBCCRC1_BSCM_1_8BIT 0 +#define MCDE_PBCCRC1_BSCM_2_8BIT 1 +#define MCDE_PBCCRC1_BSCM_3_8BIT 2 +#define MCDE_PBCCRC1_BSCM_1_16BIT 3 +#define MCDE_PBCCRC1_BSCM_2_16BIT 4 +#define MCDE_PBCCRC1_BSCM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSCM, MCDE_PBCCRC1_BSCM_##__x) +#define MCDE_PBCCRC1_BSCM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSCM, __x) +#define MCDE_PBCCRC1_BSDM_SHIFT 3 +#define MCDE_PBCCRC1_BSDM_MASK 0x00000038 +#define MCDE_PBCCRC1_BSDM_1_8BIT 0 +#define MCDE_PBCCRC1_BSDM_2_8BIT 1 +#define MCDE_PBCCRC1_BSDM_3_8BIT 2 +#define MCDE_PBCCRC1_BSDM_1_16BIT 3 +#define MCDE_PBCCRC1_BSDM_2_16BIT 4 +#define MCDE_PBCCRC1_BSDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSDM, MCDE_PBCCRC1_BSDM_##__x) +#define MCDE_PBCCRC1_BSDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BSDM, __x) +#define MCDE_PBCCRC1_PDM_SHIFT 6 +#define MCDE_PBCCRC1_PDM_MASK 0x000000C0 +#define MCDE_PBCCRC1_PDM_NORMAL 0 +#define MCDE_PBCCRC1_PDM_16_TO_32 1 +#define MCDE_PBCCRC1_PDM_24_TO_32_RIGHT 2 +#define MCDE_PBCCRC1_PDM_24_TO_32_LEFT 3 +#define MCDE_PBCCRC1_PDM_ENUM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDM, MCDE_PBCCRC1_PDM_##__x) +#define MCDE_PBCCRC1_PDM(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDM, __x) +#define MCDE_PBCCRC1_PDCTRL_SHIFT 12 +#define MCDE_PBCCRC1_PDCTRL_MASK 0x00001000 +#define MCDE_PBCCRC1_PDCTRL(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, PDCTRL, __x) +#define MCDE_PBCCRC1_BPP_SHIFT 13 +#define MCDE_PBCCRC1_BPP_MASK 0x0000E000 +#define MCDE_PBCCRC1_BPP_8BPP 0 +#define MCDE_PBCCRC1_BPP_12BPP 1 +#define MCDE_PBCCRC1_BPP_15BPP 2 +#define MCDE_PBCCRC1_BPP_16BPP 3 +#define MCDE_PBCCRC1_BPP_18BPP 4 +#define MCDE_PBCCRC1_BPP_24BPP 5 +#define MCDE_PBCCRC1_BPP(__x) \ + MCDE_VAL2REG(MCDE_PBCCRC1, BPP, __x) +#define MCDE_PBCBMRC00 0x00000C0C +#define MCDE_PBCBMRC00_GROUPOFFSET 0x4 +#define MCDE_PBCBMRC00_MUXI_SHIFT 0 +#define MCDE_PBCBMRC00_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC00_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC00, MUXI, __x) +#define MCDE_PBCBMRC01 0x00000C10 +#define MCDE_PBCBMRC01_MUXI_SHIFT 0 +#define MCDE_PBCBMRC01_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC01_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC01, MUXI, __x) +#define MCDE_PBCBMRC02 0x00000C14 +#define MCDE_PBCBMRC02_MUXI_SHIFT 0 +#define MCDE_PBCBMRC02_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC02_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC02, MUXI, __x) +#define MCDE_PBCBMRC03 0x00000C18 +#define MCDE_PBCBMRC03_MUXI_SHIFT 0 +#define MCDE_PBCBMRC03_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC03_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC03, MUXI, __x) +#define MCDE_PBCBMRC04 0x00000C1C +#define MCDE_PBCBMRC04_MUXI_SHIFT 0 +#define MCDE_PBCBMRC04_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC04_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC04, MUXI, __x) +#define MCDE_PBCBMRC10 0x00000C20 +#define MCDE_PBCBMRC10_MUXI_SHIFT 0 +#define MCDE_PBCBMRC10_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC10_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC10, MUXI, __x) +#define MCDE_PBCBMRC11 0x00000C24 +#define MCDE_PBCBMRC11_MUXI_SHIFT 0 +#define MCDE_PBCBMRC11_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC11_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC11, MUXI, __x) +#define MCDE_PBCBMRC12 0x00000C28 +#define MCDE_PBCBMRC12_MUXI_SHIFT 0 +#define MCDE_PBCBMRC12_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC12_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC12, MUXI, __x) +#define MCDE_PBCBMRC13 0x00000C2C +#define MCDE_PBCBMRC13_MUXI_SHIFT 0 +#define MCDE_PBCBMRC13_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC13_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC13, MUXI, __x) +#define MCDE_PBCBMRC14 0x00000C30 +#define MCDE_PBCBMRC14_MUXI_SHIFT 0 +#define MCDE_PBCBMRC14_MUXI_MASK 0xFFFFFFFF +#define MCDE_PBCBMRC14_MUXI(__x) \ + MCDE_VAL2REG(MCDE_PBCBMRC14, MUXI, __x) +#define MCDE_PBCBCRC00 0x00000C34 +#define MCDE_PBCBCRC00_GROUPOFFSET 0x4 +#define MCDE_PBCBCRC00_CTLI_SHIFT 0 +#define MCDE_PBCBCRC00_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC00_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC00, CTLI, __x) +#define MCDE_PBCBCRC10 0x00000C38 +#define MCDE_PBCBCRC10_CTLI_SHIFT 0 +#define MCDE_PBCBCRC10_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC10_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC10, CTLI, __x) +#define MCDE_PBCBCRC01 0x00000C48 +#define MCDE_PBCBCRC01_GROUPOFFSET 0x4 +#define MCDE_PBCBCRC01_CTLI_SHIFT 0 +#define MCDE_PBCBCRC01_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC01_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC01, CTLI, __x) +#define MCDE_PBCBCRC11 0x00000C4C +#define MCDE_PBCBCRC11_CTLI_SHIFT 0 +#define MCDE_PBCBCRC11_CTLI_MASK 0xFFFFFFFF +#define MCDE_PBCBCRC11_CTLI(__x) \ + MCDE_VAL2REG(MCDE_PBCBCRC11, CTLI, __x) +#define MCDE_VSCRC0 0x00000C5C +#define MCDE_VSCRC0_GROUPOFFSET 0x4 +#define MCDE_VSCRC0_VSPMIN_SHIFT 0 +#define MCDE_VSCRC0_VSPMIN_MASK 0x00000FFF +#define MCDE_VSCRC0_VSPMIN(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPMIN, __x) +#define MCDE_VSCRC0_VSPMAX_SHIFT 12 +#define MCDE_VSCRC0_VSPMAX_MASK 0x00FFF000 +#define MCDE_VSCRC0_VSPMAX(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPMAX, __x) +#define MCDE_VSCRC0_VSPDIV_SHIFT 24 +#define MCDE_VSCRC0_VSPDIV_MASK 0x07000000 +#define MCDE_VSCRC0_VSPDIV(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPDIV, __x) +#define MCDE_VSCRC0_VSPOL_SHIFT 27 +#define MCDE_VSCRC0_VSPOL_MASK 0x08000000 +#define MCDE_VSCRC0_VSPOL_ACTIVE_HIGH 0 +#define MCDE_VSCRC0_VSPOL_ACTIVE_LOW 1 +#define MCDE_VSCRC0_VSPOL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPOL, MCDE_VSCRC0_VSPOL_##__x) +#define MCDE_VSCRC0_VSPOL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSPOL, __x) +#define MCDE_VSCRC0_VSSEL_SHIFT 28 +#define MCDE_VSCRC0_VSSEL_MASK 0x10000000 +#define MCDE_VSCRC0_VSSEL_VSYNC 0 +#define MCDE_VSCRC0_VSSEL_HSYNC 1 +#define MCDE_VSCRC0_VSSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSSEL, MCDE_VSCRC0_VSSEL_##__x) +#define MCDE_VSCRC0_VSSEL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSSEL, __x) +#define MCDE_VSCRC0_VSDBL_SHIFT 29 +#define MCDE_VSCRC0_VSDBL_MASK 0xE0000000 +#define MCDE_VSCRC0_VSDBL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC0, VSDBL, __x) +#define MCDE_VSCRC1 0x00000C60 +#define MCDE_VSCRC1_VSPMIN_SHIFT 0 +#define MCDE_VSCRC1_VSPMIN_MASK 0x00000FFF +#define MCDE_VSCRC1_VSPMIN(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPMIN, __x) +#define MCDE_VSCRC1_VSPMAX_SHIFT 12 +#define MCDE_VSCRC1_VSPMAX_MASK 0x00FFF000 +#define MCDE_VSCRC1_VSPMAX(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPMAX, __x) +#define MCDE_VSCRC1_VSPDIV_SHIFT 24 +#define MCDE_VSCRC1_VSPDIV_MASK 0x07000000 +#define MCDE_VSCRC1_VSPDIV(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPDIV, __x) +#define MCDE_VSCRC1_VSPOL_SHIFT 27 +#define MCDE_VSCRC1_VSPOL_MASK 0x08000000 +#define MCDE_VSCRC1_VSPOL_ACTIVE_HIGH 0 +#define MCDE_VSCRC1_VSPOL_ACTIVE_LOW 1 +#define MCDE_VSCRC1_VSPOL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPOL, MCDE_VSCRC1_VSPOL_##__x) +#define MCDE_VSCRC1_VSPOL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSPOL, __x) +#define MCDE_VSCRC1_VSSEL_SHIFT 28 +#define MCDE_VSCRC1_VSSEL_MASK 0x10000000 +#define MCDE_VSCRC1_VSSEL_VSYNC 0 +#define MCDE_VSCRC1_VSSEL_HSYNC 1 +#define MCDE_VSCRC1_VSSEL_ENUM(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSSEL, MCDE_VSCRC1_VSSEL_##__x) +#define MCDE_VSCRC1_VSSEL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSSEL, __x) +#define MCDE_VSCRC1_VSDBL_SHIFT 29 +#define MCDE_VSCRC1_VSDBL_MASK 0xE0000000 +#define MCDE_VSCRC1_VSDBL(__x) \ + MCDE_VAL2REG(MCDE_VSCRC1, VSDBL, __x) +#define MCDE_SCTRC 0x00000C64 +#define MCDE_SCTRC_SYNCDELC0_SHIFT 0 +#define MCDE_SCTRC_SYNCDELC0_MASK 0x000000FF +#define MCDE_SCTRC_SYNCDELC0(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, SYNCDELC0, __x) +#define MCDE_SCTRC_SYNCDELC1_SHIFT 8 +#define MCDE_SCTRC_SYNCDELC1_MASK 0x0000FF00 +#define MCDE_SCTRC_SYNCDELC1(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, SYNCDELC1, __x) +#define MCDE_SCTRC_TRDELC_SHIFT 16 +#define MCDE_SCTRC_TRDELC_MASK 0x0FFF0000 +#define MCDE_SCTRC_TRDELC(__x) \ + MCDE_VAL2REG(MCDE_SCTRC, TRDELC, __x) +#define MCDE_SCSRC 0x00000C68 +#define MCDE_SCSRC_VSTAC0_SHIFT 0 +#define MCDE_SCSRC_VSTAC0_MASK 0x00000001 +#define MCDE_SCSRC_VSTAC0(__x) \ + MCDE_VAL2REG(MCDE_SCSRC, VSTAC0, __x) +#define MCDE_SCSRC_VSTAC1_SHIFT 1 +#define MCDE_SCSRC_VSTAC1_MASK 0x00000002 +#define MCDE_SCSRC_VSTAC1(__x) \ + MCDE_VAL2REG(MCDE_SCSRC, VSTAC1, __x) +#define MCDE_BCNR0 0x00000C6C +#define MCDE_BCNR0_GROUPOFFSET 0x4 +#define MCDE_BCNR0_BCN_SHIFT 0 +#define MCDE_BCNR0_BCN_MASK 0x000000FF +#define MCDE_BCNR0_BCN(__x) \ + MCDE_VAL2REG(MCDE_BCNR0, BCN, __x) +#define MCDE_BCNR1 0x00000C70 +#define MCDE_BCNR1_BCN_SHIFT 0 +#define MCDE_BCNR1_BCN_MASK 0x000000FF +#define MCDE_BCNR1_BCN(__x) \ + MCDE_VAL2REG(MCDE_BCNR1, BCN, __x) +#define MCDE_CSCDTR0 0x00000C74 +#define MCDE_CSCDTR0_GROUPOFFSET 0x4 +#define MCDE_CSCDTR0_CSCDACT_SHIFT 0 +#define MCDE_CSCDTR0_CSCDACT_MASK 0x000000FF +#define MCDE_CSCDTR0_CSCDACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR0, CSCDACT, __x) +#define MCDE_CSCDTR0_CSCDDEACT_SHIFT 8 +#define MCDE_CSCDTR0_CSCDDEACT_MASK 0x0000FF00 +#define MCDE_CSCDTR0_CSCDDEACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR0, CSCDDEACT, __x) +#define MCDE_CSCDTR1 0x00000C78 +#define MCDE_CSCDTR1_CSCDACT_SHIFT 0 +#define MCDE_CSCDTR1_CSCDACT_MASK 0x000000FF +#define MCDE_CSCDTR1_CSCDACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR1, CSCDACT, __x) +#define MCDE_CSCDTR1_CSCDDEACT_SHIFT 8 +#define MCDE_CSCDTR1_CSCDDEACT_MASK 0x0000FF00 +#define MCDE_CSCDTR1_CSCDDEACT(__x) \ + MCDE_VAL2REG(MCDE_CSCDTR1, CSCDDEACT, __x) +#define MCDE_RDWRTR0 0x00000C7C +#define MCDE_RDWRTR0_GROUPOFFSET 0x4 +#define MCDE_RDWRTR0_RWACT_SHIFT 0 +#define MCDE_RDWRTR0_RWACT_MASK 0x000000FF +#define MCDE_RDWRTR0_RWACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, RWACT, __x) +#define MCDE_RDWRTR0_RWDEACT_SHIFT 8 +#define MCDE_RDWRTR0_RWDEACT_MASK 0x0000FF00 +#define MCDE_RDWRTR0_RWDEACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, RWDEACT, __x) +#define MCDE_RDWRTR0_MOTINT_SHIFT 16 +#define MCDE_RDWRTR0_MOTINT_MASK 0x00010000 +#define MCDE_RDWRTR0_MOTINT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR0, MOTINT, __x) +#define MCDE_RDWRTR1 0x00000C80 +#define MCDE_RDWRTR1_RWACT_SHIFT 0 +#define MCDE_RDWRTR1_RWACT_MASK 0x000000FF +#define MCDE_RDWRTR1_RWACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, RWACT, __x) +#define MCDE_RDWRTR1_RWDEACT_SHIFT 8 +#define MCDE_RDWRTR1_RWDEACT_MASK 0x0000FF00 +#define MCDE_RDWRTR1_RWDEACT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, RWDEACT, __x) +#define MCDE_RDWRTR1_MOTINT_SHIFT 16 +#define MCDE_RDWRTR1_MOTINT_MASK 0x00010000 +#define MCDE_RDWRTR1_MOTINT(__x) \ + MCDE_VAL2REG(MCDE_RDWRTR1, MOTINT, __x) +#define MCDE_DOTR0 0x00000C84 +#define MCDE_DOTR0_GROUPOFFSET 0x4 +#define MCDE_DOTR0_DOACT_SHIFT 0 +#define MCDE_DOTR0_DOACT_MASK 0x000000FF +#define MCDE_DOTR0_DOACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR0, DOACT, __x) +#define MCDE_DOTR0_DODEACT_SHIFT 8 +#define MCDE_DOTR0_DODEACT_MASK 0x0000FF00 +#define MCDE_DOTR0_DODEACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR0, DODEACT, __x) +#define MCDE_DOTR1 0x00000C88 +#define MCDE_DOTR1_DOACT_SHIFT 0 +#define MCDE_DOTR1_DOACT_MASK 0x000000FF +#define MCDE_DOTR1_DOACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR1, DOACT, __x) +#define MCDE_DOTR1_DODEACT_SHIFT 8 +#define MCDE_DOTR1_DODEACT_MASK 0x0000FF00 +#define MCDE_DOTR1_DODEACT(__x) \ + MCDE_VAL2REG(MCDE_DOTR1, DODEACT, __x) +#define MCDE_WCMDC0 0x00000C8C +#define MCDE_WCMDC0_GROUPOFFSET 0x4 +#define MCDE_WCMDC0_COMMANDVALUE_SHIFT 0 +#define MCDE_WCMDC0_COMMANDVALUE_MASK 0x00FFFFFF +#define MCDE_WCMDC0_COMMANDVALUE(__x) \ + MCDE_VAL2REG(MCDE_WCMDC0, COMMANDVALUE, __x) +#define MCDE_WCMDC1 0x00000C90 +#define MCDE_WCMDC1_COMMANDVALUE_SHIFT 0 +#define MCDE_WCMDC1_COMMANDVALUE_MASK 0x00FFFFFF +#define MCDE_WCMDC1_COMMANDVALUE(__x) \ + MCDE_VAL2REG(MCDE_WCMDC1, COMMANDVALUE, __x) +#define MCDE_WDATADC0 0x00000C94 +#define MCDE_WDATADC0_GROUPOFFSET 0x4 +#define MCDE_WDATADC0_DATAVALUE_SHIFT 0 +#define MCDE_WDATADC0_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_WDATADC0_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_WDATADC0, DATAVALUE, __x) +#define MCDE_WDATADC1 0x00000C98 +#define MCDE_WDATADC1_DATAVALUE_SHIFT 0 +#define MCDE_WDATADC1_DATAVALUE_MASK 0x00FFFFFF +#define MCDE_WDATADC1_DATAVALUE(__x) \ + MCDE_VAL2REG(MCDE_WDATADC1, DATAVALUE, __x) +#define MCDE_RDATADC0 0x00000C9C +#define MCDE_RDATADC0_GROUPOFFSET 0x4 +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE_SHIFT 0 +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE_MASK 0x0000FFFF +#define MCDE_RDATADC0_DATAREADFROMDISPLAYMODULE(__x) \ + MCDE_VAL2REG(MCDE_RDATADC0, DATAREADFROMDISPLAYMODULE, __x) +#define MCDE_RDATADC0_STARTREAD_SHIFT 16 +#define MCDE_RDATADC0_STARTREAD_MASK 0x00010000 +#define MCDE_RDATADC0_STARTREAD(__x) \ + MCDE_VAL2REG(MCDE_RDATADC0, STARTREAD, __x) +#define MCDE_RDATADC1 0x00000CA0 +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE_SHIFT 0 +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE_MASK 0x0000FFFF +#define MCDE_RDATADC1_DATAREADFROMDISPLAYMODULE(__x) \ + MCDE_VAL2REG(MCDE_RDATADC1, DATAREADFROMDISPLAYMODULE, __x) +#define MCDE_RDATADC1_STARTREAD_SHIFT 16 +#define MCDE_RDATADC1_STARTREAD_MASK 0x00010000 +#define MCDE_RDATADC1_STARTREAD(__x) \ + MCDE_VAL2REG(MCDE_RDATADC1, STARTREAD, __x) +#define MCDE_STATC 0x00000CA4 +#define MCDE_STATC_STATBUSY0_SHIFT 0 +#define MCDE_STATC_STATBUSY0_MASK 0x00000001 +#define MCDE_STATC_STATBUSY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, STATBUSY0, __x) +#define MCDE_STATC_FIFOEMPTY0_SHIFT 1 +#define MCDE_STATC_FIFOEMPTY0_MASK 0x00000002 +#define MCDE_STATC_FIFOEMPTY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY0, __x) +#define MCDE_STATC_FIFOFULL0_SHIFT 2 +#define MCDE_STATC_FIFOFULL0_MASK 0x00000004 +#define MCDE_STATC_FIFOFULL0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOFULL0, __x) +#define MCDE_STATC_FIFOCMDEMPTY0_SHIFT 3 +#define MCDE_STATC_FIFOCMDEMPTY0_MASK 0x00000008 +#define MCDE_STATC_FIFOCMDEMPTY0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY0, __x) +#define MCDE_STATC_FIFOCMDFULL0_SHIFT 4 +#define MCDE_STATC_FIFOCMDFULL0_MASK 0x00000010 +#define MCDE_STATC_FIFOCMDFULL0(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL0, __x) +#define MCDE_STATC_STATBUSY1_SHIFT 5 +#define MCDE_STATC_STATBUSY1_MASK 0x00000020 +#define MCDE_STATC_STATBUSY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, STATBUSY1, __x) +#define MCDE_STATC_FIFOEMPTY1_SHIFT 6 +#define MCDE_STATC_FIFOEMPTY1_MASK 0x00000040 +#define MCDE_STATC_FIFOEMPTY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOEMPTY1, __x) +#define MCDE_STATC_FIFOFULL1_SHIFT 7 +#define MCDE_STATC_FIFOFULL1_MASK 0x00000080 +#define MCDE_STATC_FIFOFULL1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOFULL1, __x) +#define MCDE_STATC_FIFOCMDEMPTY1_SHIFT 8 +#define MCDE_STATC_FIFOCMDEMPTY1_MASK 0x00000100 +#define MCDE_STATC_FIFOCMDEMPTY1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDEMPTY1, __x) +#define MCDE_STATC_FIFOCMDFULL1_SHIFT 9 +#define MCDE_STATC_FIFOCMDFULL1_MASK 0x00000200 +#define MCDE_STATC_FIFOCMDFULL1(__x) \ + MCDE_VAL2REG(MCDE_STATC, FIFOCMDFULL1, __x) +#define MCDE_CTRLC0 0x00000CA8 +#define MCDE_CTRLC0_GROUPOFFSET 0x4 +#define MCDE_CTRLC0_FIFOWTRMRK_SHIFT 0 +#define MCDE_CTRLC0_FIFOWTRMRK_MASK 0x000000FF +#define MCDE_CTRLC0_FIFOWTRMRK(__x) \ + MCDE_VAL2REG(MCDE_CTRLC0, FIFOWTRMRK, __x) +#define MCDE_CTRLC1 0x00000CAC +#define MCDE_CTRLC1_FIFOWTRMRK_SHIFT 0 +#define MCDE_CTRLC1_FIFOWTRMRK_MASK 0x000000FF +#define MCDE_CTRLC1_FIFOWTRMRK(__x) \ + MCDE_VAL2REG(MCDE_CTRLC1, FIFOWTRMRK, __x) +#define MCDE_DSIVID0CONF0 0x00000E00 +#define MCDE_DSIVID0CONF0_GROUPOFFSET 0x20 +#define MCDE_DSIVID0CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID0CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID0CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BLANKING, __x) +#define MCDE_DSIVID0CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID0CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID0CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID0CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID0CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, VID_MODE, \ + MCDE_DSIVID0CONF0_VID_MODE_##__x) +#define MCDE_DSIVID0CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, VID_MODE, __x) +#define MCDE_DSIVID0CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID0CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID0CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, CMD8, __x) +#define MCDE_DSIVID0CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID0CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID0CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID0CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID0CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID0CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID0CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID0CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID0CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID0CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID0CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID0CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID0CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID0CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID0CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, PACKING, \ + MCDE_DSIVID0CONF0_PACKING_##__x) +#define MCDE_DSIVID0CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CONF0, PACKING, __x) +#define MCDE_DSICMD0CONF0 0x00000E20 +#define MCDE_DSICMD0CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD0CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD0CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BLANKING, __x) +#define MCDE_DSICMD0CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD0CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD0CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD0CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD0CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, VID_MODE, \ + MCDE_DSICMD0CONF0_VID_MODE_##__x) +#define MCDE_DSICMD0CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, VID_MODE, __x) +#define MCDE_DSICMD0CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD0CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD0CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, CMD8, __x) +#define MCDE_DSICMD0CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD0CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD0CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD0CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD0CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD0CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD0CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD0CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD0CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD0CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD0CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD0CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD0CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD0CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD0CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, PACKING, \ + MCDE_DSICMD0CONF0_PACKING_##__x) +#define MCDE_DSICMD0CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CONF0, PACKING, __x) +#define MCDE_DSIVID1CONF0 0x00000E40 +#define MCDE_DSIVID1CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID1CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID1CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BLANKING, __x) +#define MCDE_DSIVID1CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID1CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID1CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID1CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID1CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, VID_MODE, \ + MCDE_DSIVID1CONF0_VID_MODE_##__x) +#define MCDE_DSIVID1CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, VID_MODE, __x) +#define MCDE_DSIVID1CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID1CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID1CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, CMD8, __x) +#define MCDE_DSIVID1CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID1CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID1CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID1CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID1CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID1CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID1CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID1CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID1CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID1CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID1CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID1CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID1CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID1CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID1CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, PACKING, \ + MCDE_DSIVID1CONF0_PACKING_##__x) +#define MCDE_DSIVID1CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CONF0, PACKING, __x) +#define MCDE_DSICMD1CONF0 0x00000E60 +#define MCDE_DSICMD1CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD1CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD1CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BLANKING, __x) +#define MCDE_DSICMD1CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD1CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD1CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD1CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD1CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, VID_MODE, \ + MCDE_DSICMD1CONF0_VID_MODE_##__x) +#define MCDE_DSICMD1CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, VID_MODE, __x) +#define MCDE_DSICMD1CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD1CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD1CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, CMD8, __x) +#define MCDE_DSICMD1CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD1CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD1CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD1CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD1CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD1CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD1CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD1CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD1CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD1CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD1CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD1CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD1CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD1CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD1CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, PACKING, \ + MCDE_DSICMD1CONF0_PACKING_##__x) +#define MCDE_DSICMD1CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CONF0, PACKING, __x) +#define MCDE_DSIVID2CONF0 0x00000E80 +#define MCDE_DSIVID2CONF0_BLANKING_SHIFT 0 +#define MCDE_DSIVID2CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSIVID2CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BLANKING, __x) +#define MCDE_DSIVID2CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSIVID2CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSIVID2CONF0_VID_MODE_CMD 0 +#define MCDE_DSIVID2CONF0_VID_MODE_VID 1 +#define MCDE_DSIVID2CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, VID_MODE, \ + MCDE_DSIVID2CONF0_VID_MODE_##__x) +#define MCDE_DSIVID2CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, VID_MODE, __x) +#define MCDE_DSIVID2CONF0_CMD8_SHIFT 13 +#define MCDE_DSIVID2CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSIVID2CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, CMD8, __x) +#define MCDE_DSIVID2CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSIVID2CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSIVID2CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BIT_SWAP, __x) +#define MCDE_DSIVID2CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSIVID2CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSIVID2CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, BYTE_SWAP, __x) +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSIVID2CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSIVID2CONF0_PACKING_SHIFT 20 +#define MCDE_DSIVID2CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSIVID2CONF0_PACKING_RGB565 0 +#define MCDE_DSIVID2CONF0_PACKING_RGB666 1 +#define MCDE_DSIVID2CONF0_PACKING_RGB888 2 +#define MCDE_DSIVID2CONF0_PACKING_BGR888 3 +#define MCDE_DSIVID2CONF0_PACKING_HDTV 7 +#define MCDE_DSIVID2CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, PACKING, \ + MCDE_DSIVID2CONF0_PACKING_##__x) +#define MCDE_DSIVID2CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CONF0, PACKING, __x) +#define MCDE_DSICMD2CONF0 0x00000EA0 +#define MCDE_DSICMD2CONF0_BLANKING_SHIFT 0 +#define MCDE_DSICMD2CONF0_BLANKING_MASK 0x000000FF +#define MCDE_DSICMD2CONF0_BLANKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BLANKING, __x) +#define MCDE_DSICMD2CONF0_VID_MODE_SHIFT 12 +#define MCDE_DSICMD2CONF0_VID_MODE_MASK 0x00001000 +#define MCDE_DSICMD2CONF0_VID_MODE_CMD 0 +#define MCDE_DSICMD2CONF0_VID_MODE_VID 1 +#define MCDE_DSICMD2CONF0_VID_MODE_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, VID_MODE, \ + MCDE_DSICMD2CONF0_VID_MODE_##__x) +#define MCDE_DSICMD2CONF0_VID_MODE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, VID_MODE, __x) +#define MCDE_DSICMD2CONF0_CMD8_SHIFT 13 +#define MCDE_DSICMD2CONF0_CMD8_MASK 0x00002000 +#define MCDE_DSICMD2CONF0_CMD8(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, CMD8, __x) +#define MCDE_DSICMD2CONF0_BIT_SWAP_SHIFT 16 +#define MCDE_DSICMD2CONF0_BIT_SWAP_MASK 0x00010000 +#define MCDE_DSICMD2CONF0_BIT_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BIT_SWAP, __x) +#define MCDE_DSICMD2CONF0_BYTE_SWAP_SHIFT 17 +#define MCDE_DSICMD2CONF0_BYTE_SWAP_MASK 0x00020000 +#define MCDE_DSICMD2CONF0_BYTE_SWAP(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, BYTE_SWAP, __x) +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN_SHIFT 18 +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN_MASK 0x00040000 +#define MCDE_DSICMD2CONF0_DCSVID_NOTGEN(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, DCSVID_NOTGEN, __x) +#define MCDE_DSICMD2CONF0_PACKING_SHIFT 20 +#define MCDE_DSICMD2CONF0_PACKING_MASK 0x00700000 +#define MCDE_DSICMD2CONF0_PACKING_RGB565 0 +#define MCDE_DSICMD2CONF0_PACKING_RGB666 1 +#define MCDE_DSICMD2CONF0_PACKING_RGB888 2 +#define MCDE_DSICMD2CONF0_PACKING_BGR888 3 +#define MCDE_DSICMD2CONF0_PACKING_HDTV 7 +#define MCDE_DSICMD2CONF0_PACKING_ENUM(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, PACKING, \ + MCDE_DSICMD2CONF0_PACKING_##__x) +#define MCDE_DSICMD2CONF0_PACKING(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CONF0, PACKING, __x) +#define MCDE_DSIVID0FRAME 0x00000E04 +#define MCDE_DSIVID0FRAME_GROUPOFFSET 0x20 +#define MCDE_DSIVID0FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID0FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID0FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0FRAME, FRAME, __x) +#define MCDE_DSICMD0FRAME 0x00000E24 +#define MCDE_DSICMD0FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD0FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD0FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0FRAME, FRAME, __x) +#define MCDE_DSIVID1FRAME 0x00000E44 +#define MCDE_DSIVID1FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID1FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID1FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1FRAME, FRAME, __x) +#define MCDE_DSICMD1FRAME 0x00000E64 +#define MCDE_DSICMD1FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD1FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD1FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1FRAME, FRAME, __x) +#define MCDE_DSIVID2FRAME 0x00000E84 +#define MCDE_DSIVID2FRAME_FRAME_SHIFT 0 +#define MCDE_DSIVID2FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSIVID2FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2FRAME, FRAME, __x) +#define MCDE_DSICMD2FRAME 0x00000EA4 +#define MCDE_DSICMD2FRAME_FRAME_SHIFT 0 +#define MCDE_DSICMD2FRAME_FRAME_MASK 0x00FFFFFF +#define MCDE_DSICMD2FRAME_FRAME(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2FRAME, FRAME, __x) +#define MCDE_DSIVID0PKT 0x00000E08 +#define MCDE_DSIVID0PKT_GROUPOFFSET 0x20 +#define MCDE_DSIVID0PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID0PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID0PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0PKT, PACKET, __x) +#define MCDE_DSICMD0PKT 0x00000E28 +#define MCDE_DSICMD0PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD0PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD0PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0PKT, PACKET, __x) +#define MCDE_DSIVID1PKT 0x00000E48 +#define MCDE_DSIVID1PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID1PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID1PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1PKT, PACKET, __x) +#define MCDE_DSICMD1PKT 0x00000E68 +#define MCDE_DSICMD1PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD1PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD1PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1PKT, PACKET, __x) +#define MCDE_DSIVID2PKT 0x00000E88 +#define MCDE_DSIVID2PKT_PACKET_SHIFT 0 +#define MCDE_DSIVID2PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSIVID2PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2PKT, PACKET, __x) +#define MCDE_DSICMD2PKT 0x00000EA8 +#define MCDE_DSICMD2PKT_PACKET_SHIFT 0 +#define MCDE_DSICMD2PKT_PACKET_MASK 0x0000FFFF +#define MCDE_DSICMD2PKT_PACKET(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2PKT, PACKET, __x) +#define MCDE_DSIVID0SYNC 0x00000E0C +#define MCDE_DSIVID0SYNC_GROUPOFFSET 0x20 +#define MCDE_DSIVID0SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID0SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID0SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0SYNC, DMA, __x) +#define MCDE_DSIVID0SYNC_SW_SHIFT 16 +#define MCDE_DSIVID0SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID0SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0SYNC, SW, __x) +#define MCDE_DSICMD0SYNC 0x00000E2C +#define MCDE_DSICMD0SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD0SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD0SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0SYNC, DMA, __x) +#define MCDE_DSICMD0SYNC_SW_SHIFT 16 +#define MCDE_DSICMD0SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD0SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0SYNC, SW, __x) +#define MCDE_DSIVID1SYNC 0x00000E4C +#define MCDE_DSIVID1SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID1SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID1SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1SYNC, DMA, __x) +#define MCDE_DSIVID1SYNC_SW_SHIFT 16 +#define MCDE_DSIVID1SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID1SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1SYNC, SW, __x) +#define MCDE_DSICMD1SYNC 0x00000E6C +#define MCDE_DSICMD1SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD1SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD1SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1SYNC, DMA, __x) +#define MCDE_DSICMD1SYNC_SW_SHIFT 16 +#define MCDE_DSICMD1SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD1SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1SYNC, SW, __x) +#define MCDE_DSIVID2SYNC 0x00000E8C +#define MCDE_DSIVID2SYNC_DMA_SHIFT 0 +#define MCDE_DSIVID2SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSIVID2SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2SYNC, DMA, __x) +#define MCDE_DSIVID2SYNC_SW_SHIFT 16 +#define MCDE_DSIVID2SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSIVID2SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2SYNC, SW, __x) +#define MCDE_DSICMD2SYNC 0x00000EAC +#define MCDE_DSICMD2SYNC_DMA_SHIFT 0 +#define MCDE_DSICMD2SYNC_DMA_MASK 0x00000FFF +#define MCDE_DSICMD2SYNC_DMA(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2SYNC, DMA, __x) +#define MCDE_DSICMD2SYNC_SW_SHIFT 16 +#define MCDE_DSICMD2SYNC_SW_MASK 0x0FFF0000 +#define MCDE_DSICMD2SYNC_SW(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2SYNC, SW, __x) +#define MCDE_DSIVID0CMDW 0x00000E10 +#define MCDE_DSIVID0CMDW_GROUPOFFSET 0x20 +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID0CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID0CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID0CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID0CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0CMDW, CMDW_START, __x) +#define MCDE_DSICMD0CMDW 0x00000E30 +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD0CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD0CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD0CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD0CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0CMDW, CMDW_START, __x) +#define MCDE_DSIVID1CMDW 0x00000E50 +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID1CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID1CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID1CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID1CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1CMDW, CMDW_START, __x) +#define MCDE_DSICMD1CMDW 0x00000E70 +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD1CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD1CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD1CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD1CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1CMDW, CMDW_START, __x) +#define MCDE_DSIVID2CMDW 0x00000E90 +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSIVID2CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSIVID2CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSIVID2CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSIVID2CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2CMDW, CMDW_START, __x) +#define MCDE_DSICMD2CMDW 0x00000EB0 +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE_SHIFT 0 +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE_MASK 0x0000FFFF +#define MCDE_DSICMD2CMDW_CMDW_CONTINUE(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CMDW, CMDW_CONTINUE, __x) +#define MCDE_DSICMD2CMDW_CMDW_START_SHIFT 16 +#define MCDE_DSICMD2CMDW_CMDW_START_MASK 0xFFFF0000 +#define MCDE_DSICMD2CMDW_CMDW_START(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2CMDW, CMDW_START, __x) +#define MCDE_DSIVID0DELAY0 0x00000E14 +#define MCDE_DSIVID0DELAY0_GROUPOFFSET 0x20 +#define MCDE_DSIVID0DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID0DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID0DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD0DELAY0 0x00000E34 +#define MCDE_DSICMD0DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD0DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD0DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID1DELAY0 0x00000E54 +#define MCDE_DSIVID1DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID1DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID1DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD1DELAY0 0x00000E74 +#define MCDE_DSICMD1DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD1DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD1DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID2DELAY0 0x00000E94 +#define MCDE_DSIVID2DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSIVID2DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSIVID2DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY0, INTPKTDEL, __x) +#define MCDE_DSICMD2DELAY0 0x00000EB4 +#define MCDE_DSICMD2DELAY0_INTPKTDEL_SHIFT 0 +#define MCDE_DSICMD2DELAY0_INTPKTDEL_MASK 0x0000FFFF +#define MCDE_DSICMD2DELAY0_INTPKTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY0, INTPKTDEL, __x) +#define MCDE_DSIVID0DELAY1 0x00000E18 +#define MCDE_DSIVID0DELAY1_GROUPOFFSET 0x20 +#define MCDE_DSIVID0DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID0DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID0DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID0DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID0DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD0DELAY1 0x00000E38 +#define MCDE_DSICMD0DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD0DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD0DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD0DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD0DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSIVID1DELAY1 0x00000E58 +#define MCDE_DSIVID1DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID1DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID1DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID1DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID1DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD1DELAY1 0x00000E78 +#define MCDE_DSICMD1DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD1DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD1DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD1DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD1DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSIVID2DELAY1 0x00000E98 +#define MCDE_DSIVID2DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSIVID2DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSIVID2DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY1, TEREQDEL, __x) +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSIVID2DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSIVID2DELAY1, FRAMESTARTDEL, __x) +#define MCDE_DSICMD2DELAY1 0x00000EB8 +#define MCDE_DSICMD2DELAY1_TEREQDEL_SHIFT 0 +#define MCDE_DSICMD2DELAY1_TEREQDEL_MASK 0x00000FFF +#define MCDE_DSICMD2DELAY1_TEREQDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY1, TEREQDEL, __x) +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL_SHIFT 16 +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL_MASK 0x00FF0000 +#define MCDE_DSICMD2DELAY1_FRAMESTARTDEL(__x) \ + MCDE_VAL2REG(MCDE_DSICMD2DELAY1, FRAMESTARTDEL, __x) diff --git a/drivers/video/mcde/mcde_utils.c b/drivers/video/mcde/mcde_utils.c deleted file mode 100644 index 0c4cac2832e..00000000000 --- a/drivers/video/mcde/mcde_utils.c +++ /dev/null @@ -1,1518 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT -/* HW V1 */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <mach/mcde_common.h> -#include <mach/mcde_a0.h> -extern struct mcdefb_info *gpar[]; - -/** bitmap of which overlays are in use (set) and unused (cleared) */ -u32 mcde_ovl_bmp; -/** color conversion coefficients */ -u32 img_rgb_2_ycbcr[COLCONV_COEFF_OFF]={0x00420081,0x00190070,0x03A203EE,0x03DA03B5,0x00700080,0x00100080}; -u32 img_ycbcr_2_rgb[COLCONV_COEFF_OFF]={0x0330012A,0x039C0199,0x012A0000,0x0000012A,0x01990321,0x00870115}; - -/** get x line length word aligned, and in bytes */ -/*static inline */unsigned long get_line_length(int x, int bpp) -{ - return (unsigned long)((((x*bpp)+31)&~31) >> 3); -} - -unsigned long claim_mcde_lock(mcde_ch_id chid) -{ - unsigned long flags; - spin_lock_irqsave(&(gpar[chid]->mcde_spin_lock), flags); - return flags; -} - -void release_mcde_lock(mcde_ch_id chid, unsigned long flags) -{ - spin_unlock_irqrestore(&(gpar[chid]->mcde_spin_lock), flags); -} - -int convertbpp(u8 bpp) -{ - int hw_bpp = 0; - - switch (bpp) - { - case MCDE_U8500_PANEL_1BPP: - hw_bpp = MCDE_PAL_1_BIT; - break; - - case MCDE_U8500_PANEL_2BPP: - hw_bpp = MCDE_PAL_2_BIT; - break; - - case MCDE_U8500_PANEL_4BPP: - hw_bpp = MCDE_PAL_4_BIT; - break; - - case MCDE_U8500_PANEL_8BPP: - hw_bpp = MCDE_PAL_8_BIT; - break; - - case MCDE_U8500_PANEL_16BPP: - hw_bpp = MCDE_RGB565_16_BIT; - break; - - case MCDE_U8500_PANEL_24BPP_PACKED: - hw_bpp = MCDE_RGB_PACKED_24_BIT; - break; - - case MCDE_U8500_PANEL_24BPP: - hw_bpp = MCDE_RGB_UNPACKED_24_BIT; - break; - - case MCDE_U8500_PANEL_32BPP: - hw_bpp = MCDE_ARGB_32_BIT; - break; - - default: - hw_bpp = -EINVAL; - } - - return hw_bpp; -} - -/** channel specific enable*/ -void mcdefb_enable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - - /* Turn on FLOWEN for this channel */ - mcdesetchnlXflowmode(currentpar->chid, MCDE_FLOW_ENABLE); - - /* Turn on POWEREN for this channel */ - mcdesetchnlXpowermode(currentpar->chid, MCDE_POWER_ENABLE); - - switch (currentpar->chid) { - case MCDE_CH_C0: - /* turn on C1EN or C2EN */ - mcdesetchnlCmode(currentpar->chid, MCDE_PANEL_C0, MCDE_CHANNEL_C_ENABLE); - break; - - case MCDE_CH_C1: - /* turn on C1EN or C2EN */ - mcdesetchnlCmode(currentpar->chid, MCDE_PANEL_C1, MCDE_CHANNEL_C_ENABLE); - break; - - default: - /* do nothing */ - break; - } -} - -/** channel specific disable */ -void mcdefb_disable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - - switch (currentpar->chid) { - case MCDE_CH_C0: - /* turn off C1EN or C2EN */ - mcdesetchnlCmode(currentpar->chid, MCDE_PANEL_C0, MCDE_CHANNEL_C_DISABLE); - break; - - case MCDE_CH_C1: - /* turn off C1EN or C2EN */ - mcdesetchnlCmode(currentpar->chid, MCDE_PANEL_C1, MCDE_CHANNEL_C_DISABLE); - break; - - default: - /* do nothing */ - break; - } - - /* Turn off POWEREN for this channel */ - mcdesetchnlXpowermode(currentpar->chid, MCDE_POWER_DISABLE); - - /* Turn off FLOWEN for this channel */ - mcdesetchnlXflowmode(currentpar->chid, MCDE_FLOW_DISABLE); -} - -int mcde_enable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal=0; - - if (mcdegetchannelstate(currentpar->chid) == MCDE_DISABLE) { - /* Enable MCDE */ - gpar[currentpar->chid]->regbase->mcde_cr &= ~MCDE_CR_MCDEEN; - - mcdesetstate(currentpar->chid, MCDE_ENABLE); - mcdefb_enable(info); - - gpar[currentpar->chid]->regbase->mcde_cr |= MCDE_CR_MCDEEN; - } - return retVal; -} - -int mcde_disable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal=0; - - if (mcdegetchannelstate(currentpar->chid) == MCDE_ENABLE) { - /* Disable MCDE */ - gpar[currentpar->chid]->regbase->mcde_cr &= ~MCDE_CR_MCDEEN; - - mcdesetstate(currentpar->chid, MCDE_DISABLE); - mcdefb_disable(info); - - gpar[currentpar->chid]->regbase->mcde_cr |= MCDE_CR_MCDEEN; - } - return retVal; -} - -int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest) -{ - u32 xorig = source_buff.xwidth; - u32 yorig = source_buff.yheight; - u8 input_bpp = source_buff.bpp; - u32 framesize=0; - u32 retVal = 0; - u8 __iomem *vbuffaddr; - dma_addr_t dma; - u32 line_length; - u8 buffidx; - struct mcdefb_info *currentpar = info->par; - - /** calculate the line jump for getting the frame size */ - if (input_bpp == MCDE_YCbCr_8_BIT) - line_length = xorig * 2; - else - line_length = get_line_length(input_bpp,xorig); - - if (source_buff.doubleBufferingEnabled) - framesize = (line_length * yorig) * 2; - else - framesize = (line_length * yorig); - - for (buffidx = isUserRequest*MCDE_MAX_FRAMEBUFF; buffidx < (MCDE_MAX_FRAMEBUFF + (isUserRequest*MCDE_MAX_FRAMEBUFF)); buffidx++) - { - if (!(mcde_ovl_bmp & (1 << buffidx))) - break; - } - if (buffidx == (MCDE_MAX_FRAMEBUFF + (isUserRequest*MCDE_MAX_FRAMEBUFF))) - { - dbgprintk(MCDE_ERROR_INFO, "Unable to allocate memory for FB, as it reached max FB\n"); - return -EINVAL; - } - /** allocate memory */ - vbuffaddr = (char __iomem *) dma_alloc_coherent(info->dev,framesize,&dma,GFP_KERNEL|GFP_DMA); - if (!vbuffaddr) - { - dbgprintk(MCDE_ERROR_INFO, "Unable to allocate external source memory for new framebuffer\n"); - return -ENOMEM; - } - - mcde_ovl_bmp |= (1 << (buffidx)); - *pkey = buffidx; - - currentpar->buffaddr[buffidx].cpuaddr = (u32) vbuffaddr; - currentpar->buffaddr[buffidx].dmaaddr = dma; - currentpar->buffaddr[buffidx].bufflength = framesize; - - if (isUserRequest == TRUE) - { - source_buff.buff_addr.dmaaddr = dma; - source_buff.buff_addr.bufflength = framesize; - }else if (currentpar->tot_ovl_used < MCDE_MAX_FRAMEBUFF) - { - currentpar->tot_ovl_used++; - currentpar->mcde_cur_ovl_bmp = buffidx; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used -1] = currentpar->mcde_cur_ovl_bmp; - } - - return retVal; -} - -int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest) -{ - u32 retVal = MCDE_OK; - struct mcdefb_info *currentpar = info->par; - - if (!(mcde_ovl_bmp & (1 << srcbufferindex))) - { - dbgprintk(MCDE_ERROR_INFO, "mcde_dealloc_source_buffer: Not a valid source buffer ID\n"); - return -EINVAL; - } - - mcde_ovl_bmp &= ~(1 << srcbufferindex); - if (currentpar->buffaddr[srcbufferindex].dmaaddr != 0x0) - dma_free_coherent(info->dev, currentpar->buffaddr[srcbufferindex].bufflength, - (void*)currentpar->buffaddr[srcbufferindex].cpuaddr, - currentpar->buffaddr[srcbufferindex].dmaaddr); - - currentpar->buffaddr[srcbufferindex].cpuaddr = 0x0 ; - currentpar->buffaddr[srcbufferindex].dmaaddr = 0x0; - currentpar->buffaddr[srcbufferindex].bufflength = 0x0; - if (isUserRequest == FALSE && (currentpar->tot_ovl_used > 0 && currentpar->tot_ovl_used < MCDE_MAX_FRAMEBUFF)) - { - currentpar->tot_ovl_used--; - currentpar->mcde_cur_ovl_bmp = currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used - 1]; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used] = -1; - } - - return retVal; -} - -int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ext_src_ctrl control; - u32 retVal = 0; - - /* requested overlay id is not equal to the current overlay id */ - if(ext_src_config.provr_id != currentpar->mcde_cur_ovl_bmp) - { - dbgprintk(MCDE_ERROR_INFO, "mcde_conf_extsource: Not a valid overlay ID\n"); - return -1; - } - - /* Ext src config registers */ - mcdesetextsrcconf(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ext_src_config); - - control.fs_ctrl = MCDE_FS_FREQ_UNCHANGED; - control.fs_div = MCDE_FS_FREQ_DIV_ENABLE; - control.ovr_ctrl = MCDE_MULTI_CH_CTRL_PRIMARY_OVR; - control.sel_mode = MCDE_BUFFER_SOFTWARE_SELECT; - - /* Ext src control registers */ - mcdesetextsrcctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, control); - /* Set the source buffer address */ - mcdesetbufferaddr(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ext_src_config.buf_id, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].dmaaddr); - - return retVal; -} - -int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - - mcdesetcolorkey(currentpar->chid, chnannel_color_key.color_key, chnannel_color_key.color_key_type); - mcdesetcflowXcolorkeyctrl(currentpar->chid, chnannel_color_key.key_ctrl); - - return retVal; -} - -int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ovr_comp ovr_comp; - struct mcde_ovr_conf2 ovr_conf2; - int retVal = MCDE_OK; - - ovr_conf2.alpha_value = blend_ctrl.ovr1_blend_ctrl.alpha_value; - ovr_conf2.ovr_blend = blend_ctrl.ovr1_blend_ctrl.ovr_blend; - ovr_conf2.ovr_opaq = blend_ctrl.ovr1_blend_ctrl.ovr_opaq; - ovr_conf2.pixoff = 0; - ovr_conf2.watermark_level = 0x20; - mcdesetovrconf2(currentpar->chid, blend_ctrl.ovr1_id, ovr_conf2); - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = blend_ctrl.ovr1_blend_ctrl.ovr_xpos; - ovr_comp.ovr_ypos = blend_ctrl.ovr1_blend_ctrl.ovr_ypos; - ovr_comp.ovr_zlevel = blend_ctrl.ovr1_blend_ctrl.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, blend_ctrl.ovr1_id, ovr_comp); - - if (blend_ctrl.ovr2_enable) - { - ovr_conf2.alpha_value = blend_ctrl.ovr2_blend_ctrl.alpha_value; - ovr_conf2.ovr_blend = blend_ctrl.ovr2_blend_ctrl.ovr_blend; - ovr_conf2.ovr_opaq = blend_ctrl.ovr2_blend_ctrl.ovr_opaq; - ovr_conf2.pixoff = 0; - ovr_conf2.watermark_level = 0x20; - mcdesetovrconf2(currentpar->chid, blend_ctrl.ovr2_id, ovr_conf2); - - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = blend_ctrl.ovr2_blend_ctrl.ovr_xpos; - ovr_comp.ovr_ypos = blend_ctrl.ovr2_blend_ctrl.ovr_ypos; - ovr_comp.ovr_zlevel = blend_ctrl.ovr2_blend_ctrl.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, blend_ctrl.ovr2_id, ovr_comp); - } - - mcdesetblendctrl(currentpar->chid, blend_ctrl); - - return retVal; -} - -int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - - mcdesetrotation(currentpar->chid, rot_dir, rot_ctrl); - mcdesetrotaddr(currentpar->chid, rot_addr0, MCDE_ROTATE0); - mcdesetrotaddr(currentpar->chid, rot_addr1, MCDE_ROTATE1); - - return retVal; -} - -int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - - mcdesetbufferaddr(currentpar->chid, currentpar->mcde_cur_ovl_bmp, buff_id, buffer_address); - - return retVal; -} - -int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chx_rgb_conv_coef convCoef = {0}; - int retVal = MCDE_OK; - - if(color_conv_ctrl.convert_format == COLOR_CONV_NONE) - return retVal; - - if (color_conv_ctrl.convert_format == COLOR_CONV_YUV_RGB) - { - /** write on the RGB conversion registers */ - convCoef.Yr_red = 0x330; - convCoef.Yr_green = 0x12A; - convCoef.Yr_blue = 0x39C; - convCoef.Cr_red = 0x199; - convCoef.Cr_green = 0x12A; - convCoef.Cr_blue = 0x0; - convCoef.Cb_red = 0x0; - convCoef.Cb_green = 0x12A; - convCoef.Cb_blue = 0x199; - convCoef.Off_red = 0x321; - convCoef.Off_green = 0x87; - convCoef.Off_blue = 0x115; - } else if (color_conv_ctrl.convert_format == COLOR_CONV_RGB_YUV) - { - /** write on the RGB conversion registers */ - convCoef.Yr_red = 0x42; - convCoef.Yr_green = 0x81; - convCoef.Yr_blue = 0x19; - convCoef.Cr_red = 0x70; - convCoef.Cr_green = 0x3A2; - convCoef.Cr_blue = 0x3EE; - convCoef.Cb_red = 0x3DA; - convCoef.Cb_green = 0x3B5; - convCoef.Cb_blue = 0x70; - convCoef.Off_red = 0x80; - convCoef.Off_green = 0x10; - convCoef.Off_blue = 0x80; - } else if (color_conv_ctrl.convert_format == COLOR_CONV_YUV422_YUV444) - { - convCoef.Yr_red = 263; - convCoef.Yr_green = 516; - convCoef.Yr_blue = 100; - convCoef.Cr_red = 450; - convCoef.Cr_green = -377; - convCoef.Cr_blue = -73; - convCoef.Cb_red = -152; - convCoef.Cb_green = -298; - convCoef.Cb_blue = 450; - convCoef.Off_red = 128; - convCoef.Off_green = 16; - convCoef.Off_blue = 128; - } - mcdesetcolorconvmatrix(currentpar->chid, convCoef); - mcdesetcolorconvctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, color_conv_ctrl.col_ctrl); - - return retVal; -} - -int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ovr_control ovr_cr; - struct mcde_ovr_config ovr_conf; - struct mcde_ovr_conf2 ovr_conf2; - struct mcde_ovr_comp ovr_comp; - struct mcde_conf_color_conv color_conv_ctrl; - u32 lineJump; - u32 retVal = 0; - - /* Set overlay registers */ - ovr_cr.ovr_state = ovrlayConfig.ovr_state; - ovr_cr.col_ctrl = ovrlayConfig.col_ctrl; - ovr_cr.pal_control = ovrlayConfig.pal_control; - ovr_cr.priority = ovrlayConfig.priority; - ovr_cr.color_key = ovrlayConfig.color_key; - ovr_cr.rot_burst_req = ovrlayConfig.rot_burst_req; - ovr_cr.burst_req = ovrlayConfig.burst_req; - ovr_cr.outstnd_req = ovrlayConfig.outstnd_req; - ovr_cr.alpha = ovrlayConfig.alpha; - ovr_cr.clip = ovrlayConfig.clip; - - /* Overlay ctrl registers */ - mcdesetovrctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_cr); - - ovr_conf.line_per_frame = ovrlayConfig.yheight; - ovr_conf.ovr_ppl = ovrlayConfig.xwidth; - ovr_conf.src_id = currentpar->mcde_cur_ovl_bmp; - - /* Overlay config registers */ - mcdesetovrlayconf(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_conf); - - ovr_conf2.alpha_value = ovrlayConfig.alpha_value; - ovr_conf2.ovr_blend = ovrlayConfig.ovr_blend; - ovr_conf2.ovr_opaq = ovrlayConfig.ovr_opaq; - ovr_conf2.pixoff = ovrlayConfig.pixoff; - ovr_conf2.watermark_level = ovrlayConfig.watermark_level; - - mcdesetovrconf2(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_conf2); - - if (ovrlayConfig.bpp == MCDE_YCbCr_8_BIT) - lineJump = info->var.xres * 2; - else - lineJump = get_line_length(ovrlayConfig.bpp,ovr_conf.ovr_ppl); - - mcdesetovrljinc(currentpar->chid, currentpar->mcde_cur_ovl_bmp, lineJump); - - /* Overlay composition registers */ - /* Base overlay is always in background */ - - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = ovrlayConfig.ovr_xpos; - ovr_comp.ovr_ypos = ovrlayConfig.ovr_ypos; - ovr_comp.ovr_zlevel = ovrlayConfig.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_comp); - - color_conv_ctrl.convert_format = ovrlayConfig.convert_format; - color_conv_ctrl.convert_format = ovrlayConfig.col_ctrl; - mcde_conf_color_conversion(info, color_conv_ctrl); - - return retVal; -} - -int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info, u32 *pkey) -{ - struct mcde_sourcebuffer_alloc source_buff; - struct mcde_conf_overlay ovrlayConfig; - struct mcde_ext_conf config; - struct mcde_conf_color_conv color_conv_ctrl; - struct mcdefb_info *currentpar = info->par; - u32 mcdeOverlayId; - s32 hw_bpp = 0; - u32 flags; - u8 ovl_fore = extsrc_ovl->fg; - mcde_colorconv_type convert_format = COLOR_CONV_NONE; - - if (extsrc_ovl->bpp == MCDE_YCbCr_8_BIT) - { - if (!(currentpar->tvout)) convert_format = COLOR_CONV_YUV_RGB; - hw_bpp = MCDE_YCbCr_8_BIT; - } - else - hw_bpp = convertbpp(extsrc_ovl->bpp); - - if (hw_bpp < 0) return -EINVAL; - - if (hw_bpp <= MCDE_PAL_8_BIT) - info->fix.visual = FB_VISUAL_PSEUDOCOLOR; - - /* Can't be bigger than the base overlay*/ - if ((extsrc_ovl->xwidth > info->var.xres) || (extsrc_ovl->yheight > info->var.yres)) - return -EINVAL; - - if (extsrc_ovl->usedefault == 0) - { - /* Allocate memory */ - source_buff.xwidth = extsrc_ovl->xwidth; - source_buff.yheight = extsrc_ovl->yheight; - source_buff.bpp = extsrc_ovl->bpp; - source_buff.doubleBufferingEnabled = 0; - flags = claim_mcde_lock(currentpar->chid); - mcde_alloc_source_buffer(source_buff, info, &mcdeOverlayId, FALSE); - release_mcde_lock(currentpar->chid, flags); - *pkey = mcdeOverlayId; - } else - *pkey = currentpar->mcde_cur_ovl_bmp; - - /* Set external source registers */ - config.ovr_pxlorder = MCDE_PIXEL_ORDER_LITTLE; - config.endianity = MCDE_BYTE_LITTLE; - config.rgb_format = currentpar->bgrinput; - config.bpp = (u32)hw_bpp; - config.provr_id = currentpar->mcde_cur_ovl_bmp; - config.buf_num = MCDE_BUFFER_USED_1; - config.buf_id = MCDE_BUFFER_ID_0; - mcde_conf_extsource(config ,info); - - /* Set overlay registers */ - ovrlayConfig.ovr_state = MCDE_OVERLAY_ENABLE; - if (convert_format == COLOR_CONV_YUV_RGB) - ovrlayConfig.col_ctrl = MCDE_COL_CONV_NOT_SAT; - else - ovrlayConfig.col_ctrl = MCDE_COL_CONV_DISABLE; - - if (currentpar->actual_bpp <= MCDE_PAL_8_BIT) - ovrlayConfig.pal_control = MCDE_PAL_ENABLE; - else - ovrlayConfig.pal_control = MCDE_PAL_GAMA_DISABLE; - - ovrlayConfig.priority = 0x0; - ovrlayConfig.color_key = MCDE_COLOR_KEY_DISABLE; - ovrlayConfig.rot_burst_req = MCDE_ROTATE_BURST_WORD_4; - ovrlayConfig.burst_req = MCDE_BURST_WORD_HW_8; - ovrlayConfig.outstnd_req = MCDE_OUTSTND_REQ_4; - ovrlayConfig.alpha = MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE; - ovrlayConfig.clip = MCDE_OVR_CLIP_DISABLE; - ovrlayConfig.alpha_value = 0x64; - ovrlayConfig.ovr_blend = MCDE_CONST_ALPHA_SOURCE; - ovrlayConfig.ovr_opaq = MCDE_OVR_OPAQUE_ENABLE; - ovrlayConfig.pixoff = 0x0; - ovrlayConfig.watermark_level = 0x20; - ovrlayConfig.xbrcoor = 0x0; - ovrlayConfig.xtlcoor = 0x0; - ovrlayConfig.ybrcoor = 0x0; - ovrlayConfig.ytlcoor = 0x0; - ovrlayConfig.ovr_xpos = extsrc_ovl->xorig; - ovrlayConfig.ovr_ypos = extsrc_ovl->yorig; - ovrlayConfig.ovr_zlevel = ovl_fore; - ovrlayConfig.xwidth = extsrc_ovl->xwidth; - ovrlayConfig.yheight = extsrc_ovl->yheight; - ovrlayConfig.bpp = extsrc_ovl->bpp; - mcde_conf_overlay(ovrlayConfig, info); - - color_conv_ctrl.convert_format = convert_format; - color_conv_ctrl.convert_format = ovrlayConfig.col_ctrl; - mcde_conf_color_conversion(info, color_conv_ctrl); - - return 0; -} - -int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key) -{ - struct mcdefb_info *currentpar = info->par; - unsigned long flags; - u32 retVal = MCDE_OK; - - /* SPINLOCK in use : deal with the global variables now */ - flags = claim_mcde_lock(currentpar->chid); - - if ((key != currentpar->mcde_cur_ovl_bmp) || (currentpar->tot_ovl_used == 1)) - { - dbgprintk(MCDE_ERROR_INFO, "Overlay not in use for this channel\n"); - release_mcde_lock(currentpar->chid, flags); - return -EINVAL; - } - /* Reset ext src and ovrlay registers to default value */ - mcderesetextsrcovrlay(currentpar->chid); - -#ifdef TESTING - currentpar->tot_ovl_used--; - //mcde_ovl_bmp--; - mcde_ovl_bmp &= ~(1 << key); - dma_free_coherent(info->dev, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].bufflength, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].cpuaddr, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].dmaaddr); - - currentpar->mcde_cur_ovl_bmp = currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used - 1]; - - currentpar->buffaddr[key].cpuaddr = 0x0 ; - currentpar->buffaddr[key].dmaaddr = 0x0; - currentpar->buffaddr[key].bufflength = 0x0; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used] = -1; -#endif - - retVal = mcde_dealloc_source_buffer(info, key, FALSE); - release_mcde_lock(currentpar->chid, flags); - - return retVal; -} - -int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chsyncmod sync_mod; - u32 retVal = 0; - - if (currentpar->chid == CHANNEL_A || currentpar->chid == CHANNEL_B || currentpar->chid == CHANNEL_C0 || currentpar->chid == CHANNEL_C1) - { - sync_mod.out_synch_interface = ch_config.out_synch_interface; - sync_mod.ch_synch_src = ch_config.ch_synch_src; - mcdesetchnlsyncsrc(currentpar->chid, currentpar->chid, sync_mod); - mcdesetchnlXconf(currentpar->chid, currentpar->chid, ch_config.chconfig); - mcdesetswsync(currentpar->chid, currentpar->chid, ch_config.sw_trig); - mcdesetchnlbckgndcol(currentpar->chid, currentpar->chid, ch_config.chbckgrndcolor); - mcdesetchnlsyncprio(currentpar->chid, currentpar->chid, ch_config.ch_priority); - if (sync_mod.out_synch_interface == MCDE_SYNCHRO_OUTPUT_SOURCE) - { - mcdesetchnlsyncevent(currentpar->chid, ch_config); - } - mcdesetpanelctrl(currentpar->chid, ch_config.control1); - } - - return retVal; -} -/** ------------------------------------------------------------------------ - FUNCTION : mcde_conf_lcd_timing - PURPOSE : To configure the parameters for LCD configuration - ------------------------------------------------------------------------ */ -int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chx_lcd_timing0 lcdcontrol0; - struct mcde_chx_lcd_timing1 lcdcontrol1; - u32 retVal = 0; - - mcdesetchnlLCDctrlreg(currentpar->chid, chnl_lcd_ctrl.lcd_ctrl_reg); - mcdesetchnlLCDhorizontaltiming(currentpar->chid, chnl_lcd_ctrl.lcd_horizontal_timing); - mcdesetchnlLCDverticaltiming(currentpar->chid, chnl_lcd_ctrl.lcd_vertical_timing); - - lcdcontrol0.ps_delay0 = 0x0; - lcdcontrol0.ps_delay1 = 0x0; - lcdcontrol0.ps_sync_sel = 0x0; - lcdcontrol0.ps_toggle_enable = 0x0; - lcdcontrol0.ps_va_enable = 0x0; - lcdcontrol0.rev_delay0 = 0x0; - lcdcontrol0.rev_delay1 = 0x0; - lcdcontrol0.rev_sync_sel = 0x0; - lcdcontrol0.rev_toggle_enable = 0x0; - lcdcontrol0.rev_va_enable = 0x0; - mcdesetLCDtiming0ctrl(currentpar->chid, lcdcontrol0); - - lcdcontrol1.iclrev = 0x0; - lcdcontrol1.iclsp = 0x0; - lcdcontrol1.iclspl = 0x0; - lcdcontrol1.ihs = 0x1; - lcdcontrol1.io_enable = 0x0; - lcdcontrol1.ipc = 0x0; - lcdcontrol1.ivp = 0x0; - lcdcontrol1.ivs = 0x1; - lcdcontrol1.mcde_spl = 0x0; - lcdcontrol1.spltgen = 0x0; - lcdcontrol1.spl_delay0 = 0x0; - lcdcontrol1.spl_delay1 = 0x0; - lcdcontrol1.spl_sync_sel = 0x0; - mcdesetLCDtiming1ctrl(currentpar->chid, lcdcontrol1); - return retVal; -} -int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - mcde_chc_panel panel_id; - u32 retVal = MCDE_OK; - - if (currentpar->chid == MCDE_CH_C0) - panel_id = MCDE_PANEL_C0; - else if (currentpar->chid == MCDE_CH_C1) - panel_id = MCDE_PANEL_C1; - else return MCDE_INVALID_PARAMETER; - -#if 0 - mcdesetchnlCconf(currentpar->chid, panel_id, chnlc_config); - mcdesetchnlCctrl(currentpar->chid, chnlc_control); -#endif - - currentpar->ch_c_reg->mcde_crc = /*MCDE_CRC_FLOEN | MCDE_CRC_POWEREN | MCDE_CRC_C1EN | MCDE_CRC_WMLVL1 | - MCDE_CRC_CS1EN | MCDE_CRC_RESEN | MCDE_CRC_CS1POL | MCDE_CRC_CS2POL | - MCDE_CRC_CD1POL | MCDE_CRC_CD2POL | MCDE_CRC_WR2POL | MCDE_CRC_RD2POL | - MCDE_CRC_RES1POL | MCDE_CRC_RES2POL;//*/0x1d7d0017;//0x387b0027; - - /** Add any Channel "C' extra configuration */ - - return retVal; - -} -int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u8 cmdbyte_lsb; - u8 cmdbyte_msb; -#if 0 - u16 sync_dma; - u16 sync_sw; -#endif - u32 retVal = 0; - u16 packet_size = 1+info->var.xres*info->var.bits_per_pixel/8; - - cmdbyte_lsb = TPO_CMD_RAMWR_CONTINUE; - cmdbyte_msb = TPO_CMD_NONE; - - mcdesetdsicommandword( currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, cmdbyte_lsb, cmdbyte_msb); - - mcdesetdsiclk(currentpar->dsi_lnk_no, currentpar->chid, clk_config); -#if 0 - mcdesetdsisyncpulse(currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, sync_dma, sync_sw); -#endif - dsi_conf.blanking = 0; - dsi_conf.vid_mode = currentpar->dsi_lnk_context.dsi_if_mode; - dsi_conf.cmd8 = MCDE_DSI_CMD_8; - dsi_conf.bit_swap = MCDE_DSI_NO_SWAP; - dsi_conf.byte_swap = MCDE_DSI_NO_SWAP; - dsi_conf.synchro = MCDE_DSI_OUT_VIDEO_DCS; - dsi_conf.packing = MCDE_PACKING_RGB888_R; - dsi_conf.words_per_frame = info->var.yres*packet_size; - dsi_conf.words_per_packet = packet_size; - mcdesetdsiconf(currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, dsi_conf); - - return retVal; -} -/** ------------------------------------------------------------------------ - FUNCTION : mcde_conf_dithering_ctrl - PURPOSE : To configure the parameters for dithering - ------------------------------------------------------------------------ */ -int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal = MCDE_OK; - - retVal = mcdesetditherctrl(currentpar->chid, dithering_ctrl_conf.mcde_chx_dither_ctrl); - retVal = mcdesetditheroffset(currentpar->chid, dithering_ctrl_conf.mcde_chx_dithering_offset); - mcdesetditheringctrl(currentpar->chid, dithering_ctrl_conf.dithering_ctrl); - - return retVal; -} - -/** - * mcde_conf_scan_mode() - This routine configures the TV scan mode(progressive/Interlaced). - * @scan_mode: Progressive/Interlaced. - * @info: frame buffer information. - * - * - */ -int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal = MCDE_OK; - - retVal = mcdesetscanmode(currentpar->chid, scan_mode); - if (retVal == MCDE_OK) - info->var.vmode = scan_mode; - return retVal; -} - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ -/* HW ED */ - -#ifdef _cplusplus -extern "C" { -#endif /* _cplusplus */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <mach/mcde_common.h> -extern struct mcdefb_info *gpar[]; - -/** bitmap of which overlays are in use (set) and unused (cleared) */ -u32 mcde_ovl_bmp; -/** color conversion coefficients */ -u32 img_rgb_2_ycbcr[COLCONV_COEFF_OFF]={0x00420081,0x00190070,0x03A203EE,0x03DA03B5,0x00700080,0x00100080}; -u32 img_ycbcr_2_rgb[COLCONV_COEFF_OFF]={0x0330012A,0x039C0199,0x012A0000,0x0000012A,0x01990321,0x00870115}; - -/** get x line length word aligned, and in bytes */ -/*static inline */unsigned long get_line_length(int x, int bpp) -{ - return (unsigned long)((((x*bpp)+31)&~31) >> 3); -} - -unsigned long claim_mcde_lock(mcde_ch_id chid) -{ - unsigned long flags; - spin_lock_irqsave(&(gpar[chid]->mcde_spin_lock), flags); - return flags; -} - -void release_mcde_lock(mcde_ch_id chid, unsigned long flags) -{ - spin_unlock_irqrestore(&(gpar[chid]->mcde_spin_lock), flags); -} -int convertbpp(u8 bpp) -{ - int hw_bpp = 0; - - switch (bpp) - { - case MCDE_U8500_PANEL_1BPP: - hw_bpp = MCDE_PAL_1_BIT; - break; - - case MCDE_U8500_PANEL_2BPP: - hw_bpp = MCDE_PAL_2_BIT; - break; - - case MCDE_U8500_PANEL_4BPP: - hw_bpp = MCDE_PAL_4_BIT; - break; - - case MCDE_U8500_PANEL_8BPP: - hw_bpp = MCDE_PAL_8_BIT; - break; - - case MCDE_U8500_PANEL_16BPP: - hw_bpp = MCDE_RGB565_16_BIT; - break; - - case MCDE_U8500_PANEL_24BPP_PACKED: - hw_bpp = MCDE_RGB_PACKED_24_BIT; - break; - - case MCDE_U8500_PANEL_24BPP: - hw_bpp = MCDE_RGB_UNPACKED_24_BIT; - break; - - case MCDE_U8500_PANEL_32BPP: - hw_bpp = MCDE_ARGB_32_BIT; - break; - - default: - hw_bpp = -EINVAL; - } - - return hw_bpp; -} -/** channel specific enable*/ -void mcdefb_enable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - - /** ---- turn on FLOWEN for this channel */ - mcdesetchnlXflowmode(currentpar->chid, MCDE_FLOW_ENABLE); - - /** ---- turn on POWEREN for this channel */ - mcdesetchnlXpowermode(currentpar->chid, MCDE_POWER_ENABLE); -} - -/** channel specific disable */ -void mcdefb_disable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - - /** ---- turn off POWEREN for this channel */ - mcdesetchnlXpowermode(currentpar->chid, MCDE_POWER_DISABLE); - - /** ---- turn off FLOWEN for this channel */ - mcdesetchnlXflowmode(currentpar->chid, MCDE_FLOW_DISABLE); - -} -int mcde_enable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal=0; - - /** ---- enable MCDE */ - mcdesetstate(currentpar->chid, MCDE_ENABLE); - gpar[currentpar->chid]->regbase->mcde_cr |= 0x80000000; - mcdefb_enable(info); - return retVal; -} -int mcde_disable(struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal=0; - - /** ---- enable MCDE */ - mcdesetstate(currentpar->chid, MCDE_DISABLE); - mcdefb_disable(info); - return retVal; -} - -int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest) -{ - u32 xorig = source_buff.xwidth; - u32 yorig = source_buff.yheight; - u8 input_bpp = source_buff.bpp; - u32 framesize=0; - u32 retVal = 0; - u8 __iomem *vbuffaddr; - dma_addr_t dma; - u32 line_length; - u8 buffidx; - struct mcdefb_info *currentpar = info->par; - - /** calculate the line jump for getting the frame size */ - if (input_bpp == MCDE_YCbCr_8_BIT) - line_length = xorig * 2; - else - line_length = get_line_length(input_bpp,xorig); - - if (source_buff.doubleBufferingEnabled) - framesize = (line_length * yorig) * 2; - else - framesize = (line_length * yorig); - - for (buffidx = isUserRequest*MCDE_MAX_FRAMEBUFF; buffidx < (MCDE_MAX_FRAMEBUFF + (isUserRequest*MCDE_MAX_FRAMEBUFF)); buffidx++) - { - if (!(mcde_ovl_bmp & (1 << buffidx))) - break; - } - if (buffidx == (MCDE_MAX_FRAMEBUFF + (isUserRequest*MCDE_MAX_FRAMEBUFF))) - { - dbgprintk(MCDE_ERROR_INFO, "Unable to allocate memory for FB, as it reached max FB\n"); - return -EINVAL; - } - /** allocate memory */ - vbuffaddr = (char __iomem *) dma_alloc_coherent(info->dev,framesize,&dma,GFP_KERNEL|GFP_DMA); - if (!vbuffaddr) - { - dbgprintk(MCDE_ERROR_INFO, "Unable to allocate external source memory for new framebuffer\n"); - return -ENOMEM; - } - - mcde_ovl_bmp |= (1 << (buffidx)); - *pkey = buffidx; - - currentpar->buffaddr[buffidx].cpuaddr = (u32) vbuffaddr; - currentpar->buffaddr[buffidx].dmaaddr = dma; - currentpar->buffaddr[buffidx].bufflength = framesize; - - if (isUserRequest == TRUE) - { - source_buff.buff_addr.dmaaddr = dma; - source_buff.buff_addr.bufflength = framesize; - }else if (currentpar->tot_ovl_used < MCDE_MAX_FRAMEBUFF) - { - currentpar->tot_ovl_used++; - currentpar->mcde_cur_ovl_bmp = buffidx; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used -1] = currentpar->mcde_cur_ovl_bmp; - } - - return retVal; -} -int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest) -{ - u32 retVal = MCDE_OK; - struct mcdefb_info *currentpar = info->par; - - if (!(mcde_ovl_bmp & (1 << srcbufferindex))) - { - dbgprintk(MCDE_ERROR_INFO, "mcde_dealloc_source_buffer: Not a valid source buffer ID\n"); - return -EINVAL; - } - - mcde_ovl_bmp &= ~(1 << srcbufferindex); - if (currentpar->buffaddr[srcbufferindex].dmaaddr != 0x0) - dma_free_coherent(info->dev, currentpar->buffaddr[srcbufferindex].bufflength, (void*)currentpar->buffaddr[srcbufferindex].cpuaddr, currentpar->buffaddr[srcbufferindex].dmaaddr); - currentpar->buffaddr[srcbufferindex].cpuaddr = 0x0 ; - currentpar->buffaddr[srcbufferindex].dmaaddr = 0x0; - currentpar->buffaddr[srcbufferindex].bufflength = 0x0; - if (isUserRequest == FALSE && (currentpar->tot_ovl_used > 0 && currentpar->tot_ovl_used < MCDE_MAX_FRAMEBUFF)) - { - currentpar->tot_ovl_used--; - currentpar->mcde_cur_ovl_bmp = currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used - 1]; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used] = -1; - } - return retVal; -} - -int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ext_src_ctrl control; - u32 retVal = 0; - - /** requested overlay id is not equal to the current overlay id */ - if(ext_src_config.provr_id != currentpar->mcde_cur_ovl_bmp) - { - dbgprintk(MCDE_ERROR_INFO, "mcde_conf_extsource: Not a valid overlay ID\n"); - return -1; - } - - /**---- ext src config registers */ - mcdesetextsrcconf(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ext_src_config); - - control.fs_ctrl = MCDE_FS_FREQ_UNCHANGED; - control.fs_div = MCDE_FS_FREQ_DIV_ENABLE; - control.ovr_ctrl = MCDE_MULTI_CH_CTRL_PRIMARY_OVR; - control.sel_mode = MCDE_BUFFER_SOFTWARE_SELECT; - /**---- ext src control registers */ - mcdesetextsrcctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, control); - /** set the source buffer address */ - mcdesetbufferaddr(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ext_src_config.buf_id, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].dmaaddr); - - return retVal; -} - -int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - - mcdesetcolorkey(currentpar->chid, chnannel_color_key.color_key, chnannel_color_key.color_key_type); - mcdesetcflowXcolorkeyctrl(currentpar->chid, chnannel_color_key.key_ctrl); - return retVal; -} -int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ovr_comp ovr_comp; - struct mcde_ovr_conf2 ovr_conf2; - int retVal = MCDE_OK; - - ovr_conf2.alpha_value = blend_ctrl.ovr1_blend_ctrl.alpha_value; - ovr_conf2.ovr_blend = blend_ctrl.ovr1_blend_ctrl.ovr_blend; - ovr_conf2.ovr_opaq = blend_ctrl.ovr1_blend_ctrl.ovr_opaq; - ovr_conf2.pixoff = 0; - ovr_conf2.watermark_level = 0x20; - mcdesetovrconf2(currentpar->chid, blend_ctrl.ovr1_id, ovr_conf2); - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = blend_ctrl.ovr1_blend_ctrl.ovr_xpos; - ovr_comp.ovr_ypos = blend_ctrl.ovr1_blend_ctrl.ovr_ypos; - ovr_comp.ovr_zlevel = blend_ctrl.ovr1_blend_ctrl.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, blend_ctrl.ovr1_id, ovr_comp); - - if (blend_ctrl.ovr2_enable) - { - ovr_conf2.alpha_value = blend_ctrl.ovr2_blend_ctrl.alpha_value; - ovr_conf2.ovr_blend = blend_ctrl.ovr2_blend_ctrl.ovr_blend; - ovr_conf2.ovr_opaq = blend_ctrl.ovr2_blend_ctrl.ovr_opaq; - ovr_conf2.pixoff = 0; - ovr_conf2.watermark_level = 0x20; - mcdesetovrconf2(currentpar->chid, blend_ctrl.ovr2_id, ovr_conf2); - - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = blend_ctrl.ovr2_blend_ctrl.ovr_xpos; - ovr_comp.ovr_ypos = blend_ctrl.ovr2_blend_ctrl.ovr_ypos; - ovr_comp.ovr_zlevel = blend_ctrl.ovr2_blend_ctrl.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, blend_ctrl.ovr2_id, ovr_comp); - } - mcdesetblendctrl(currentpar->chid, blend_ctrl); - return retVal; -} -int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - mcdesetrotation(currentpar->chid, rot_dir, rot_ctrl); - mcdesetrotaddr(currentpar->chid, rot_addr0, MCDE_ROTATE0); - mcdesetrotaddr(currentpar->chid, rot_addr1, MCDE_ROTATE1); - return retVal; -} -int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id) -{ - struct mcdefb_info *currentpar = info->par; - int retVal = MCDE_OK; - mcdesetbufferaddr(currentpar->chid, currentpar->mcde_cur_ovl_bmp, buff_id, buffer_address); - return retVal; -} -int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chx_rgb_conv_coef convCoef = {0}; - int retVal = MCDE_OK; - - if(color_conv_ctrl.convert_format == COLOR_CONV_NONE) - return retVal; - - if (color_conv_ctrl.convert_format == COLOR_CONV_YUV_RGB) - { - /** write on the RGB conversion registers */ - convCoef.Yr_red = 0x330; - convCoef.Yr_green = 0x12A; - convCoef.Yr_blue = 0x39C; - convCoef.Cr_red = 0x199; - convCoef.Cr_green = 0x12A; - convCoef.Cr_blue = 0x0; - convCoef.Cb_red = 0x0; - convCoef.Cb_green = 0x12A; - convCoef.Cb_blue = 0x199; - convCoef.Off_red = 0x321; - convCoef.Off_green = 0x87; - convCoef.Off_blue = 0x115; - } else if (color_conv_ctrl.convert_format == COLOR_CONV_RGB_YUV) - { - /** write on the RGB conversion registers */ - convCoef.Yr_red = 0x42; - convCoef.Yr_green = 0x81; - convCoef.Yr_blue = 0x19; - convCoef.Cr_red = 0x70; - convCoef.Cr_green = 0x3A2; - convCoef.Cr_blue = 0x3EE; - convCoef.Cb_red = 0x3DA; - convCoef.Cb_green = 0x3B5; - convCoef.Cb_blue = 0x70; - convCoef.Off_red = 0x80; - convCoef.Off_green = 0x10; - convCoef.Off_blue = 0x80; - } else if (color_conv_ctrl.convert_format == COLOR_CONV_YUV422_YUV444) - { - convCoef.Yr_red = 263; - convCoef.Yr_green = 516; - convCoef.Yr_blue = 100; - convCoef.Cr_red = 450; - convCoef.Cr_green = -377; - convCoef.Cr_blue = -73; - convCoef.Cb_red = -152; - convCoef.Cb_green = -298; - convCoef.Cb_blue = 450; - convCoef.Off_red = 128; - convCoef.Off_green = 16; - convCoef.Off_blue = 128; - } - mcdesetcolorconvmatrix(currentpar->chid, convCoef); - mcdesetcolorconvctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, color_conv_ctrl.col_ctrl); - - return retVal; -} -int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_ovr_control ovr_cr; - struct mcde_ovr_config ovr_conf; - struct mcde_ovr_conf2 ovr_conf2; - //struct mcde_ovr_clip ovr_clip; - struct mcde_ovr_comp ovr_comp; - struct mcde_conf_color_conv color_conv_ctrl; - u32 lineJump; - u32 retVal = 0; - - /** SET OVERLAY REGISTERS */ - ovr_cr.ovr_state = ovrlayConfig.ovr_state; - ovr_cr.col_ctrl = ovrlayConfig.col_ctrl; - ovr_cr.pal_control = ovrlayConfig.pal_control; - ovr_cr.priority = ovrlayConfig.priority; - ovr_cr.color_key = ovrlayConfig.color_key; - ovr_cr.rot_burst_req = ovrlayConfig.rot_burst_req; - ovr_cr.burst_req = ovrlayConfig.burst_req; - ovr_cr.outstnd_req = ovrlayConfig.outstnd_req; - ovr_cr.alpha = ovrlayConfig.alpha; - ovr_cr.clip = ovrlayConfig.clip; - - /**---- overlay ctrl registers */ - mcdesetovrctrl(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_cr); - - ovr_conf.line_per_frame = ovrlayConfig.yheight;//info->var.yres; - ovr_conf.ovr_ppl = ovrlayConfig.xwidth;//info->var.xres; - ovr_conf.src_id = currentpar->mcde_cur_ovl_bmp; - - /**---- overlay config registers */ - mcdesetovrlayconf(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_conf); - - ovr_conf2.alpha_value = ovrlayConfig.alpha_value; - ovr_conf2.ovr_blend = ovrlayConfig.ovr_blend; - ovr_conf2.ovr_opaq = ovrlayConfig.ovr_opaq; - ovr_conf2.pixoff = ovrlayConfig.pixoff; - ovr_conf2.watermark_level = ovrlayConfig.watermark_level; - - mcdesetovrconf2(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_conf2); - - if (ovrlayConfig.bpp == MCDE_YCbCr_8_BIT) - lineJump = info->var.xres * 2; - else - lineJump = get_line_length(ovrlayConfig.bpp,ovr_conf.ovr_ppl); - - mcdesetovrljinc(currentpar->chid, currentpar->mcde_cur_ovl_bmp, lineJump); - - /**---- overlay composition registers */ - /** base overlay is always in background */ - - ovr_comp.ch_id = currentpar->chid; - ovr_comp.ovr_xpos = ovrlayConfig.ovr_xpos; - ovr_comp.ovr_ypos = ovrlayConfig.ovr_ypos; - ovr_comp.ovr_zlevel = ovrlayConfig.ovr_zlevel; - mcdesetovrcomp(currentpar->chid, currentpar->mcde_cur_ovl_bmp, ovr_comp); - - color_conv_ctrl.convert_format = ovrlayConfig.convert_format; - color_conv_ctrl.convert_format = ovrlayConfig.col_ctrl; - mcde_conf_color_conversion(info, color_conv_ctrl); - - return retVal; -} -int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info, u32 *pkey) -{ - struct mcde_sourcebuffer_alloc source_buff; - struct mcde_conf_overlay ovrlayConfig; - struct mcde_ext_conf config; - struct mcde_conf_color_conv color_conv_ctrl; - struct mcdefb_info *currentpar = info->par; - u32 mcdeOverlayId; - s32 hw_bpp = 0; - u32 flags; - u8 ovl_fore = extsrc_ovl->fg; - mcde_colorconv_type convert_format = COLOR_CONV_NONE; - - if (extsrc_ovl->bpp == MCDE_YCbCr_8_BIT) - { - if (!(currentpar->tvout)) convert_format = COLOR_CONV_YUV_RGB; - hw_bpp = MCDE_YCbCr_8_BIT; - } - else - hw_bpp = convertbpp(extsrc_ovl->bpp); - - if (hw_bpp < 0) return -EINVAL; - - if (hw_bpp <= MCDE_PAL_8_BIT) - info->fix.visual = FB_VISUAL_PSEUDOCOLOR; - - /**cant be bigger than the base overlay*/ - if ((extsrc_ovl->xwidth > info->var.xres) || (extsrc_ovl->yheight > info->var.yres)) - return -EINVAL; - if (extsrc_ovl->usedefault == 0) - { - /** allocate memory */ - source_buff.xwidth = extsrc_ovl->xwidth; - source_buff.yheight = extsrc_ovl->yheight; - source_buff.bpp = extsrc_ovl->bpp; - source_buff.doubleBufferingEnabled = 0; - flags = claim_mcde_lock(currentpar->chid); - mcde_alloc_source_buffer(source_buff, info, &mcdeOverlayId, FALSE); - release_mcde_lock(currentpar->chid, flags); - *pkey = mcdeOverlayId; - } else - *pkey = currentpar->mcde_cur_ovl_bmp; - - /** SET EXTERNAL SRC REGISTERS */ - config.ovr_pxlorder = MCDE_PIXEL_ORDER_LITTLE; - config.endianity = MCDE_BYTE_LITTLE; - config.rgb_format = currentpar->bgrinput; - config.bpp = (u32)hw_bpp; - config.provr_id = currentpar->mcde_cur_ovl_bmp; - config.buf_num = MCDE_BUFFER_USED_1; - config.buf_id = MCDE_BUFFER_ID_0; - mcde_conf_extsource(config ,info); - - /** SET OVERLAY REGISTERS */ - ovrlayConfig.ovr_state = MCDE_OVERLAY_ENABLE; - if (convert_format == COLOR_CONV_YUV_RGB) - ovrlayConfig.col_ctrl = MCDE_COL_CONV_NOT_SAT; - else - ovrlayConfig.col_ctrl = MCDE_COL_CONV_DISABLE; - if (currentpar->actual_bpp <= MCDE_PAL_8_BIT) - ovrlayConfig.pal_control = MCDE_PAL_ENABLE; - else - ovrlayConfig.pal_control = MCDE_PAL_GAMA_DISABLE; - ovrlayConfig.priority = 0x0; - ovrlayConfig.color_key = MCDE_COLOR_KEY_DISABLE; - ovrlayConfig.rot_burst_req = MCDE_ROTATE_BURST_WORD_4; - ovrlayConfig.burst_req = MCDE_BURST_WORD_HW_8; - ovrlayConfig.outstnd_req = MCDE_OUTSTND_REQ_4; - ovrlayConfig.alpha = MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE; - ovrlayConfig.clip = MCDE_OVR_CLIP_DISABLE; - ovrlayConfig.alpha_value = 0x64; - ovrlayConfig.ovr_blend = MCDE_CONST_ALPHA_SOURCE; - ovrlayConfig.ovr_opaq = MCDE_OVR_OPAQUE_ENABLE; - ovrlayConfig.pixoff = 0x0; - ovrlayConfig.watermark_level = 0x20; - ovrlayConfig.xbrcoor = 0x0; - ovrlayConfig.xtlcoor = 0x0; - ovrlayConfig.ybrcoor = 0x0; - ovrlayConfig.ytlcoor = 0x0; - ovrlayConfig.ovr_xpos = extsrc_ovl->xorig; - ovrlayConfig.ovr_ypos = extsrc_ovl->yorig; - ovrlayConfig.ovr_zlevel = ovl_fore; - ovrlayConfig.xwidth = extsrc_ovl->xwidth; - ovrlayConfig.yheight = extsrc_ovl->yheight; - ovrlayConfig.bpp = extsrc_ovl->bpp; - mcde_conf_overlay(ovrlayConfig, info); - - color_conv_ctrl.convert_format = convert_format; - color_conv_ctrl.convert_format = ovrlayConfig.col_ctrl; - mcde_conf_color_conversion(info, color_conv_ctrl); - - return 0; -} - -int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key) -{ - struct mcdefb_info *currentpar = info->par; - unsigned long flags; - u32 retVal = MCDE_OK; - - /** SPINLOCK in use : deal with the global variables now */ - flags = claim_mcde_lock(currentpar->chid); - - if ((key != currentpar->mcde_cur_ovl_bmp) || (currentpar->tot_ovl_used == 1)) - { - dbgprintk(MCDE_ERROR_INFO, "Overlay not in use for this channel\n"); - release_mcde_lock(currentpar->chid, flags); - return -EINVAL; - } - /** reset ext src and ovrlay registers to default value */ - mcderesetextsrcovrlay(currentpar->chid); -#ifdef TESTING - currentpar->tot_ovl_used--; - //mcde_ovl_bmp--; - mcde_ovl_bmp &= ~(1 << key); - dma_free_coherent(info->dev, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].bufflength, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].cpuaddr, currentpar->buffaddr[currentpar->mcde_cur_ovl_bmp].dmaaddr); - - currentpar->mcde_cur_ovl_bmp = currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used - 1]; - - currentpar->buffaddr[key].cpuaddr = 0x0 ; - currentpar->buffaddr[key].dmaaddr = 0x0; - currentpar->buffaddr[key].bufflength = 0x0; - currentpar->mcde_ovl_bmp_arr[currentpar->tot_ovl_used] = -1; -#endif - retVal = mcde_dealloc_source_buffer(info, key, FALSE); - release_mcde_lock(currentpar->chid, flags); - return retVal; -} -int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chsyncmod sync_mod; - u32 retVal = 0; - - if (currentpar->chid == CHANNEL_A || currentpar->chid == CHANNEL_B || currentpar->chid == CHANNEL_C0 || currentpar->chid == CHANNEL_C1) - { - sync_mod.out_synch_interface = ch_config.out_synch_interface; - sync_mod.ch_synch_src = ch_config.ch_synch_src; - mcdesetchnlsyncsrc(currentpar->chid, currentpar->chid, sync_mod); - mcdesetchnlXconf(currentpar->chid, currentpar->chid, ch_config.chconfig); - mcdesetswsync(currentpar->chid, currentpar->chid, ch_config.sw_trig); - mcdesetchnlbckgndcol(currentpar->chid, currentpar->chid, ch_config.chbckgrndcolor); - mcdesetchnlsyncprio(currentpar->chid, currentpar->chid, ch_config.ch_priority); - if (sync_mod.out_synch_interface == MCDE_SYNCHRO_OUTPUT_SOURCE) - { - mcdesetchnlsyncevent(currentpar->chid, ch_config); - } - mcdesetpanelctrl(currentpar->chid, ch_config.control1); - } - - return retVal; -} -/** ------------------------------------------------------------------------ - FUNCTION : mcde_conf_lcd_timing - PURPOSE : To configure the parameters for LCD configuration - ------------------------------------------------------------------------ */ -int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - struct mcde_chx_lcd_timing0 lcdcontrol0; - struct mcde_chx_lcd_timing1 lcdcontrol1; - u32 retVal = 0; - - mcdesetchnlLCDctrlreg(currentpar->chid, chnl_lcd_ctrl.lcd_ctrl_reg); - mcdesetchnlLCDhorizontaltiming(currentpar->chid, chnl_lcd_ctrl.lcd_horizontal_timing); - mcdesetchnlLCDverticaltiming(currentpar->chid, chnl_lcd_ctrl.lcd_vertical_timing); - - lcdcontrol0.ps_delay0 = 0x0; - lcdcontrol0.ps_delay1 = 0x0; - lcdcontrol0.ps_sync_sel = 0x0; - lcdcontrol0.ps_toggle_enable = 0x0; - lcdcontrol0.ps_va_enable = 0x0; - lcdcontrol0.rev_delay0 = 0x0; - lcdcontrol0.rev_delay1 = 0x0; - lcdcontrol0.rev_sync_sel = 0x0; - lcdcontrol0.rev_toggle_enable = 0x0; - lcdcontrol0.rev_va_enable = 0x0; - mcdesetLCDtiming0ctrl(currentpar->chid, lcdcontrol0); - - lcdcontrol1.iclrev = 0x0; - lcdcontrol1.iclsp = 0x0; - lcdcontrol1.iclspl = 0x0; - lcdcontrol1.ihs = 0x1; - lcdcontrol1.io_enable = 0x0; - lcdcontrol1.ipc = 0x0; - lcdcontrol1.ivp = 0x0; - lcdcontrol1.ivs = 0x1; - lcdcontrol1.mcde_spl = 0x0; - lcdcontrol1.spltgen = 0x0; - lcdcontrol1.spl_delay0 = 0x0; - lcdcontrol1.spl_delay1 = 0x0; - lcdcontrol1.spl_sync_sel = 0x0; - mcdesetLCDtiming1ctrl(currentpar->chid, lcdcontrol1); - return retVal; -} -int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - mcde_chc_panel panel_id; - u32 retVal = MCDE_OK; - - if (currentpar->chid == MCDE_CH_C0) - panel_id = MCDE_PANEL_C0; - else if (currentpar->chid == MCDE_CH_C1) - panel_id = MCDE_PANEL_C1; - else return MCDE_INVALID_PARAMETER; - -#if 0 - mcdesetchnlCconf(currentpar->chid, panel_id, chnlc_config); - mcdesetchnlCctrl(currentpar->chid, chnlc_control); -#endif - currentpar->ch_c_reg->mcde_chc_crc = 0x1d7d0017;//0x387b0027; - /** Add any Channel "C' extra configuration */ - - return retVal; - -} -int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u8 cmdbyte_lsb; - u8 cmdbyte_msb; -#if 0 - u16 sync_dma; - u16 sync_sw; -#endif - u32 retVal = 0; - u16 packet_size = 1+info->var.xres*info->var.bits_per_pixel/8; - - cmdbyte_lsb = TPO_CMD_RAMWR_CONTINUE; - cmdbyte_msb = TPO_CMD_NONE; - - mcdesetdsicommandword( currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, cmdbyte_lsb, cmdbyte_msb); - - mcdesetdsiclk(currentpar->dsi_lnk_no, currentpar->chid, clk_config); -#if 0 - mcdesetdsisyncpulse(currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, sync_dma, sync_sw); -#endif - dsi_conf.blanking = 0; - dsi_conf.vid_mode = currentpar->dsi_lnk_context.dsi_if_mode; - dsi_conf.cmd8 = MCDE_DSI_CMD_8; - dsi_conf.bit_swap = MCDE_DSI_NO_SWAP; - dsi_conf.byte_swap = MCDE_DSI_NO_SWAP; - dsi_conf.synchro = MCDE_DSI_OUT_VIDEO_DCS; - dsi_conf.packing = MCDE_PACKING_RGB888_R; - dsi_conf.words_per_frame = info->var.yres*packet_size; - dsi_conf.words_per_packet = packet_size; - mcdesetdsiconf(currentpar->dsi_lnk_no, currentpar->chid, currentpar->mcdeDsiChnl, dsi_conf); - - return retVal; -} -/** ------------------------------------------------------------------------ - FUNCTION : mcde_conf_dithering_ctrl - PURPOSE : To configure the parameters for dithering - ------------------------------------------------------------------------ */ -int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal = MCDE_OK; - - retVal = mcdesetditherctrl(currentpar->chid, dithering_ctrl_conf.mcde_chx_dither_ctrl); - retVal = mcdesetditheroffset(currentpar->chid, dithering_ctrl_conf.mcde_chx_dithering_offset); - mcdesetditheringctrl(currentpar->chid, dithering_ctrl_conf.dithering_ctrl); - - return retVal; -} - -/** - * mcde_conf_scan_mode() - This routine configures the TV scan mode(progressive/Interlaced). - * @scan_mode: Progressive/Interlaced. - * @info: frame buffer information. - * - * - */ -int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info) -{ - struct mcdefb_info *currentpar = info->par; - u32 retVal = MCDE_OK; - - retVal = mcdesetscanmode(currentpar->chid, scan_mode); - if (retVal == MCDE_OK) - info->var.vmode = scan_mode; - return retVal; -} - -#ifdef _cplusplus -} -#endif /* _cplusplus */ - -#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */ |