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-rw-r--r--arch/arm/configs/mop500_USB_HOST_defconfig50
-rwxr-xr-xarch/arm/configs/mop500_defconfig50
-rwxr-xr-xarch/arm/configs/mop500_ed_defconfig43
-rwxr-xr-xarch/arm/configs/mop500_power_defconfig50
-rwxr-xr-xarch/arm/mach-ux500/Kconfig-arch696
-rwxr-xr-xarch/arm/mach-ux500/board-mop500.c478
-rwxr-xr-xarch/arm/mach-ux500/clock.c21
-rw-r--r--arch/arm/mach-ux500/include/mach/ab8500_denc.h76
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100.h553
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_fw.h1041
-rwxr-xr-xarch/arm/mach-ux500/include/mach/av8100_p.h227
-rwxr-xr-xarch/arm/mach-ux500/include/mach/devices.h5
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi.h770
-rwxr-xr-xarch/arm/mach-ux500/include/mach/dsi_reg.h488
-rwxr-xr-xarch/arm/mach-ux500/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/mcde-base.h83
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde.h1387
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_a0.h896
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_common.h168
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_ioctls.h737
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mcde_reg.h787
-rw-r--r--arch/arm/mach-ux500/mcde.c788
-rw-r--r--arch/arm/mach-ux500/mop500-regulators.c46
-rw-r--r--drivers/misc/Kconfig1
-rw-r--r--drivers/misc/Makefile1
-rwxr-xr-xdrivers/misc/ab8500_denc/Kconfig6
-rwxr-xr-xdrivers/misc/ab8500_denc/Makefile4
-rw-r--r--drivers/misc/ab8500_denc/ab8500_denc.c620
-rw-r--r--drivers/misc/ab8500_denc/ab8500_denc_regs.h352
-rw-r--r--drivers/video/Kconfig4
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/av8100/Kconfig7
-rw-r--r--drivers/video/av8100/Makefile5
-rw-r--r--drivers/video/av8100/av8100.c4476
-rwxr-xr-xdrivers/video/av8100/av8100_fw.h2065
-rwxr-xr-xdrivers/video/av8100/av8100_regs.h334
-rw-r--r--drivers/video/av8100/hdmi.c195
-rw-r--r--drivers/video/mcde/Kconfig47
-rw-r--r--drivers/video/mcde/Makefile24
-rw-r--r--drivers/video/mcde/display-ab8500.c407
-rwxr-xr-xdrivers/video/mcde/display-av8100.c593
-rw-r--r--drivers/video/mcde/display-generic_dsi.c205
-rw-r--r--drivers/video/mcde/dsi_hwaccess.c1461
-rw-r--r--drivers/video/mcde/dsi_link_utils.c1794
-rw-r--r--drivers/video/mcde/dsilink_regs.h2024
-rw-r--r--drivers/video/mcde/mcde_bus.c261
-rw-r--r--drivers/video/mcde/mcde_display.c424
-rw-r--r--drivers/video/mcde/mcde_dss.c341
-rw-r--r--drivers/video/mcde/mcde_fb.c666
-rw-r--r--drivers/video/mcde/mcde_hw.c2170
-rw-r--r--drivers/video/mcde/mcde_hwaccess.c6577
-rw-r--r--drivers/video/mcde/mcde_mod.c72
-rw-r--r--drivers/video/mcde/mcde_regs.h5085
-rw-r--r--drivers/video/mcde/mcde_utils.c1518
-rwxr-xr-xinclude/video/av8100.h529
-rw-r--r--include/video/hdmi.h50
-rw-r--r--include/video/mcde.h371
-rw-r--r--include/video/mcde_display-ab8500.h22
-rw-r--r--include/video/mcde_display-av8100.h33
-rw-r--r--include/video/mcde_display-generic_dsi.h32
-rw-r--r--include/video/mcde_display.h140
-rw-r--r--include/video/mcde_dss.h79
-rw-r--r--include/video/mcde_fb.h42
63 files changed, 20291 insertions, 22194 deletions
diff --git a/arch/arm/configs/mop500_USB_HOST_defconfig b/arch/arm/configs/mop500_USB_HOST_defconfig
index 4dc0676c98d..7a672a088b4 100644
--- a/arch/arm/configs/mop500_USB_HOST_defconfig
+++ b/arch/arm/configs/mop500_USB_HOST_defconfig
@@ -242,7 +242,6 @@ CONFIG_MACH_U8500_MOP=y
CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -252,44 +251,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1035,8 +1002,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/configs/mop500_defconfig b/arch/arm/configs/mop500_defconfig
index c6721c8605f..1ac286833be 100755
--- a/arch/arm/configs/mop500_defconfig
+++ b/arch/arm/configs/mop500_defconfig
@@ -241,7 +241,6 @@ CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -251,44 +250,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1299,8 +1266,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/configs/mop500_ed_defconfig b/arch/arm/configs/mop500_ed_defconfig
index 9cf47fef7af..23ec4889f89 100755
--- a/arch/arm/configs/mop500_ed_defconfig
+++ b/arch/arm/configs/mop500_ed_defconfig
@@ -240,7 +240,6 @@ CONFIG_MACH_U8500_MOP=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-# CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT is not set
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -250,44 +249,6 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1225,11 +1186,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
#
# Frame buffer hardware drivers
#
-CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
# CONFIG_FB_HDMI is not set
# CONFIG_FB_ARMCLCD is not set
-CONFIG_FB_B2R2=y
+# CONFIG_FB_B2R2 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
diff --git a/arch/arm/configs/mop500_power_defconfig b/arch/arm/configs/mop500_power_defconfig
index 8ca53dcf082..3d0ec148809 100755
--- a/arch/arm/configs/mop500_power_defconfig
+++ b/arch/arm/configs/mop500_power_defconfig
@@ -241,7 +241,6 @@ CONFIG_U8500_CPUFREQ=y
CONFIG_U8500_PM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_SENSORS1P_MOP=y
-CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT=y
CONFIG_GPIO_STM=y
CONFIG_STM_DMA=y
# CONFIG_U8500_SECURE is not set
@@ -251,44 +250,12 @@ CONFIG_STM_DMA=y
#
#
-# Display Channel Selection
-#
-# CONFIG_FB_U8500_MCDE_CHANNELA is not set
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELB is not set
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR=0x0
-CONFIG_FB_U8500_MCDE_CHANNELC0=y
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_8BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_12BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_32BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP=y
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP is not set
-# CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA is not set
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP=16
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE=1
-CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE="WVGA_Portrait"
-CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP=0x2
-CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR=0x0
-# CONFIG_FB_U8500_MCDE_CHANNELC1 is not set
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE=0
-CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR=0x0
+# Display Selection
+#
+CONFIG_DISPLAY_GENERIC_DSI_PRIMARY=y
+# CONFIG_DISPLAY_GENERIC_DSI_SECONDARY is not set
+# CONFIG_DISPLAY_AB8500_TERTIARY is not set
+# CONFIG_DISPLAY_AV8100_TERTIARY is not set
CONFIG_FORCE_MAX_ZONEORDER=12
#
@@ -1312,8 +1279,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# Frame buffer hardware drivers
#
CONFIG_FB_MCDE=y
-CONFIG_FB_MCDE_MULTIBUFFER=y
-CONFIG_FB_HDMI=y
+CONFIG_MCDE_DISPLAY_GENERIC_DSI=y
+# CONFIG_MCDE_DISPLAY_AB8500_DENC is not set
+# CONFIG_MCDE_DISPLAY_AV8100 is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_B2R2=y
# CONFIG_FB_S1D13XXX is not set
diff --git a/arch/arm/mach-ux500/Kconfig-arch b/arch/arm/mach-ux500/Kconfig-arch
index c2235c53682..cbfdd4d3758 100755
--- a/arch/arm/mach-ux500/Kconfig-arch
+++ b/arch/arm/mach-ux500/Kconfig-arch
@@ -1,9 +1,3 @@
-config MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- bool "MCDE HW V1 support"
- default n
- help
- Say yes here if V1 HW
-
config GPIO_STM
bool "STM GPIO driver support"
default y
@@ -41,676 +35,50 @@ config STM_ALSA_DEBUG
* 0 OFF
* 1 ON
endmenu
-#Configuration for MCDE setup
-
-menu "Display Channel Selection"
-
-menuconfig FB_U8500_MCDE_CHANNELA
- depends on FB
- bool "MCDE Channel A configuration"
- default y
- help
- If you want to connect your panel to MCDE channel A then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100
- bool "AV8100 PAL"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- bool "AV8100 NTSC"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT && FB_HDMI
- bool "HDMI A"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-choice
- prompt "HDMI resolution"
- depends on FB && FB_U8500_MCDE_CHANNELA && FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- default FB_U8500_MCDE_HDMI_1280x720P60
-
-config FB_U8500_MCDE_HDMI_1920x1080P30
- bool "1920x1080P @ 30Hz"
-
-config FB_U8500_MCDE_HDMI_1280x720P60
- bool "1280x720P @ 60Hz"
-
-config FB_U8500_MCDE_HDMI_1920x1080I60
- bool "1920x1080I @ 60Hz"
-
-config FB_U8500_MCDE_HDMI_1920x1080I50
- bool "1920x1080I @ 50Hz"
-
-config FB_U8500_MCDE_HDMI_720x576I50
- bool "720x576I @ 50Hz"
-
-config FB_U8500_MCDE_HDMI_720x480I60
- bool "720x480I @ 60Hz"
-
-#config FB_U8500_MCDE_HDMI_720x480P60
-# bool "720x480P@60Hz"
-
-#config FB_U8500_MCDE_HDMI_640x480P60
-# bool "640x480P@60Hz"
-
-endchoice
-
-
-choice
- prompt "InputSource BPP"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
- bool "YCbCr422"
-
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELA
- default no
- help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELA_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELA_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELA_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELA_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELA_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB))
- default 35 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_RGB
- default 36 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_IRGB
- default 37 if FB_U8500_MCDE_CHANNELA_INPUT_16BPP_ARGB
- default 38 if FB_U8500_MCDE_CHANNELA_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- boolean
- depends on FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100 || FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- default y
-
-config FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELA_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELA_DISPLAY_CRT
- default "PAL" if FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100
- default "NTSC" if FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- default "1920x1080I60" if FB_U8500_MCDE_HDMI_1920x1080I60
- default "1920x1080I50" if FB_U8500_MCDE_HDMI_1920x1080I50
- default "1920x1080P30" if FB_U8500_MCDE_HDMI_1920x1080P30
- default "1280x720P60" if FB_U8500_MCDE_HDMI_1280x720P60
- default "NTSC" if FB_U8500_MCDE_HDMI_720x480I60
- default "PAL" if FB_U8500_MCDE_HDMI_720x576I50
- default "HDMI A" if FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELA_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELA_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELA_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELA_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELA_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELA_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELA_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELA_INPUT_BGRDATA
-
-
-menuconfig FB_U8500_MCDE_CHANNELB
- depends on FB
- bool "MCDE Channel B configuration"
- default n
- help
- If you want to connect your panel to MCDE channel B then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- depends on !FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI && !FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100 && !FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
- bool "VUIB WVGA"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- default FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
+#Configuration for MCDE setup
+menu "Display selection"
-config FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELB
- default no
+config DISPLAY_GENERIC_DSI_PRIMARY
+ bool "Main display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_GENERIC_DSI
+ default y
help
- Select this option if your input data is in BGR format
+ Say yes here if main display exists
-
-config FB_U8500_MCDE_CHANNELB_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELB_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELB_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELB_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELB_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELB_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELB_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELB_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELB_DISPLAY_CRT
- default "PAL" if FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELB_DISPLAY_QVGA_LANDSCAPE
- default "VUIB WVGA" if FB_U8500_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
-
-config FB_U8500_MCDE_CHANNELB_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELB_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELB_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELB_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELB_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELB_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELB_INPUT_BGRDATA
-
-config U8500_MCDE_DHO_LBW_SWAPPED
- bool "SDTV-MCDE: Swap LBW and DHO fields"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default y
- help
- In early development the MCDE register fields DHO and LBW are sw
-
-config U8500_TVOUT_DDR_MODE
- bool "SDTV: use Dual Data Rate"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default y
- help
- Set to use dual data rate (using 4 data lines instead of 8)
-
-config TVOUT_TEST_PATTERN
- bool "SDTV: Generate Test Pattern"
- depends on FB_U8500_MCDE_CHANNELB_DISPLAY_SDTV || FB_U8500_MCDE_CHANNEL
- default n
- help
- Only generate a test pattern (MCDE is not used)
-
-menuconfig FB_U8500_MCDE_CHANNELC0
- depends on FB
- bool "MCDE Channel C0 configuration"
- default n
+config DISPLAY_GENERIC_DSI_SECONDARY
+ bool "Sub display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_GENERIC_DSI
+ default n
help
- If you want to connect your panel to MCDE channel C then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
-# depends on MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- bool "CLCD WVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
-
+ Say yes here if sub display exists
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
- bool "24 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELC0
- default no
+config DISPLAY_AB8500_TERTIARY
+ bool "AB8500 TVout display support"
+ depends on MACH_U8500_MOP && !AV8100_SDTV && FB_MCDE
+ select MCDE_DISPLAY_AB8500_DENC
+ default n
help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELC0_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELC0_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELC0_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELC0_INPUT_YCBCR
-
+ Say yes here if tv out support
-config FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELC0_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELC0_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
- default "WVGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELC0_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELC0_DISPLAY_CRT
- default "SDTV" if FB_U8500_MCDE_CHANNELC0_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC0_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELC0_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELC0_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELC0_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELC0_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELC0_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELC0_INPUT_BGRDATA
-
-menuconfig FB_U8500_MCDE_CHANNELC1
- depends on FB
- bool "MCDE Channel C1 configuration"
- default n
+config DISPLAY_AV8100_TERTIARY
+ bool "AV8100 HDMI/CVBS display support"
+ depends on MACH_U8500_MOP && FB_MCDE
+ select MCDE_DISPLAY_AV8100
+ default n
help
- If you want to connect your panel to MCDE channel C then configure this option
-
-choice
- prompt "Display Panel Type"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
- bool "CLCD WVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
- bool "CLCD WVGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
- bool "CLCD VGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
- bool "CRT VGA"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
- bool "SDTV"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
- bool "CLCD QVGA Portrait"
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
- bool "CLCD QVGA Landscape"
-
-endchoice
-
-
-choice
- prompt "InputDataFormat BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- bool "16 BPP IRGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
- bool "8 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- bool "16 BPP ARGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- bool "16 BPP RGB"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
- bool "24 BPP"
+ Say yes here if HDMI output support
-config FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
- bool "24 BPP Packed"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
- bool "32 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
- bool "YCbCr422"
-
-endchoice
-
-
-choice
- prompt "OutputPanel BPP"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
- bool "12 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
- bool "16 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
- bool "18 BPP"
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
- bool "24 BPP"
-
-
-endchoice
-
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
- bool "BGR Input data"
- depends on FB && FB_U8500_MCDE_CHANNELC1
- default no
+config AV8100_SDTV
+ bool "set AV8100 in CVBS mode"
+ depends on DISPLAY_AV8100_TERTIARY
+ default n
help
- Select this option if your input data is in BGR format
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BPP
- int
- default 16 if !FB
- default 8 if FB_U8500_MCDE_CHANNELC1_INPUT_8BPP
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- default 16 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- default 25 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP
- default 24 if FB_U8500_MCDE_CHANNELC1_INPUT_24BPP_PACKED
- default 32 if FB_U8500_MCDE_CHANNELC1_INPUT_32BPP
- default 11 if FB_U8500_MCDE_CHANNELC1_INPUT_YCBCR
-
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE
- int
- default 0 if ((!FB_U8500_MCDE_CHANNELC1_INPUT_12BPP) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB) && (!FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB))
- default 1 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_RGB
- default 2 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_IRGB
- default 3 if FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_ARGB
- default 4 if FB_U8500_MCDE_CHANNELC1_INPUT_12BPP
-
-
-config FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE
- string
- default "VGA" if !FB
- default "WVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA_PORTRAIT
- default "WVGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_WVGA
- default "VGA" if FB_U8500_MCDE_CHANNELC1_DISPLAY_VGA
- default "CRT" if FB_U8500_MCDE_CHANNELC1_DISPLAY_CRT
- default "SDTV" if FB_U8500_MCDE_CHANNELC1_DISPLAY_SDTV
- default "QVGA_Portrait" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_PORTRAIT
- default "QVGA_Landscape" if FB_U8500_MCDE_CHANNELC1_DISPLAY_QVGA_LANDSCAPE
-
-config FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP
- hex
- default 0x2 if !FB
- default 0x1 if FB_U8500_MCDE_CHANNELC1_OUTPUT_12BPP
- default 0x2 if FB_U8500_MCDE_CHANNELC1_OUTPUT_16BPP
- default 0x3 if FB_U8500_MCDE_CHANNELC1_OUTPUT_18BPP
- default 0x4 if FB_U8500_MCDE_CHANNELC1_OUTPUT_24BPP
-
-config FB_U8500_MCDE_CHANNELC1_INPUT_BGR
- hex
- default 0x0 if !FB || !FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
- default 0x1 if FB_U8500_MCDE_CHANNELC1_INPUT_BGRDATA
+ Say yes here if tv out support
endmenu
+
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index dbe51a938e8..5e1e8b1bd59 100755
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -32,7 +32,6 @@
#include <mach/stmpe1601.h>
#include <mach/tc35892.h>
#include <mach/sensors1p.h>
-#include <mach/av8100_p.h>
#include <mach/ab8500.h>
#include <mach/ab8500_bm.h>
#include <mach/mmc.h>
@@ -40,6 +39,15 @@
#include <mach/i2c.h>
#include <mach/u8500_tsc.h>
+#include <video/mcde_display.h>
+#include <video/mcde_display-generic_dsi.h>
+#include <video/mcde_display-av8100.h>
+#include <video/mcde_display-ab8500.h>
+#include <video/mcde_fb.h>
+#include <video/mcde_dss.h>
+#include <video/av8100.h>
+#include <mach/ab8500_denc.h>
+
#define IRQ_KP 1 /*To DO*/
int href_v1_board;
@@ -48,6 +56,8 @@ extern int platform_id;
#define MOP500_PLATFORM_ID 0
#define HREF_PLATFORM_ID 1
+#define AV8100_CUT_1_0
+
/*
* This is only non-static because MCDE accesses it directly. Make this static
* once MCDE is fixed to not depend on these variables.
@@ -111,15 +121,8 @@ static struct gpio_altfun_data gpio_altfun_table[] = {
__GPIO_ALT(GPIO_ALT_SDIO, 208, 214, 0, NMK_GPIO_ALT_A, "sdio"),
__GPIO_ALT(GPIO_ALT_TRACE, 70, 74, 0, NMK_GPIO_ALT_C, "stm"),
__GPIO_ALT(GPIO_ALT_SDMMC2, 128, 138, 0, NMK_GPIO_ALT_A, "mmc2"),
-#ifndef CONFIG_FB_NOMADIK_MCDE_CHANNELB_DISPLAY_VUIB_WVGA
- __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 78, 85, 1, NMK_GPIO_ALT_A, "mcde tvout"),
- __GPIO_ALT(GPIO_ALT_LCD_PANELB_ED, 150, 150, 0, NMK_GPIO_ALT_B, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_LCD_PANELB, 78, 81, 1, NMK_GPIO_ALT_A, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_LCD_PANELB, 150, 150, 0, NMK_GPIO_ALT_B, "mcde tvout"),
-#else
- __GPIO_ALT(GPIO_ALT_LCD_PANELB, 153, 171, 1, NMK_GPIO_ALT_B, "mcde tvout"),
- __GPIO_ALT(GPIO_ALT_LCD_PANELB, 64, 77, 0, NMK_GPIO_ALT_A, "mcde tvout"),
-#endif
__GPIO_ALT(GPIO_ALT_LCD_PANELA, 68, 68, 0, NMK_GPIO_ALT_A, "mcde tvout"),
__GPIO_ALT(GPIO_ALT_MMIO_INIT_BOARD, 141, 142, 0, NMK_GPIO_ALT_B, "mmio"),
__GPIO_ALT(GPIO_ALT_MMIO_CAM_SET_I2C, 8, 9, 0, NMK_GPIO_ALT_A, "mmio"),
@@ -414,17 +417,17 @@ static struct tp_device tsc_plat_device = {
#endif
/* Portrait */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_WVGA_PORTRAIT
-
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+/* Rotation always on */
static struct lsm303dlh_platform_data __initdata lsm303dlh_pdata = {
- .register_irq = NULL,
- .free_irq = NULL,
- .axis_map_x = 0, /* Axis map for HREF ED, HREF v1 and mop500 */
- .axis_map_y = 1,
- .axis_map_z = 2,
- .negative_x = 0,
- .negative_y = 0,
- .negative_z = 0,
+ .register_irq = NULL,
+ .free_irq = NULL,
+ .axis_map_x = 0, /* Axis map for HREF ED, HREF v1 and mop500 */
+ .axis_map_y = 1,
+ .axis_map_z = 2,
+ .negative_x = 0,
+ .negative_y = 0,
+ .negative_z = 0,
};
#else /* Landsacpe */
@@ -900,6 +903,432 @@ struct platform_device sensors1p_device = {
};
#endif
+#ifdef CONFIG_FB_MCDE
+#define DSI_UNIT_INTERVAL_0 0xA
+#define DSI_UNIT_INTERVAL_1 0xA
+#define DSI_UNIT_INTERVAL_2 0x6
+
+static bool rotate_main = true;
+static bool display_initialize_during_boot;
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+static struct mcde_port port0 = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 0,
+ .sync_src = MCDE_SYNCSRC_BTA,
+ .update_auto_trig = false,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_0,
+ },
+ },
+};
+
+struct mcde_display_generic_platform_data generic_display0_pdata = {
+ .reset_gpio = EGPIO_PIN_15,
+ .reset_delay = 1,
+#ifdef CONFIG_REGULATOR
+ .regulator_id = "v-display",
+#endif
+};
+
+struct mcde_display_device generic_display0 = {
+ .name = "mcde_disp_generic",
+ .id = 0,
+ .port = &port0,
+ .chnl_id = MCDE_CHNL_A,
+ .fifo = MCDE_FIFO_C0,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+ .native_x_res = 864,
+ .native_y_res = 480,
+ .synchronized_update = false,
+ /* TODO: Remove rotation buffers once ESRAM driver is completed */
+ .rotbuf1 = U8500_ESRAM_BASE + 0x20000 * 4,
+ .rotbuf2 = U8500_ESRAM_BASE + 0x20000 * 4 + 0x10000,
+ .dev = {
+ .platform_data = &generic_display0_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_GENERIC_DSI_PRIMARY */
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_SECONDARY
+static struct mcde_port subdisplay_port = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 1,
+ .sync_src = MCDE_SYNCSRC_BTA,
+ .update_auto_trig = false,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_1,
+ },
+ },
+};
+
+static struct mcde_display_generic_platform_data generic_subdisplay_pdata = {
+ .reset_gpio = EGPIO_PIN_14,
+ .reset_delay = 1,
+#ifdef CONFIG_REGULATOR
+ .regulator_id = "v-display",
+#endif
+};
+
+static struct mcde_display_device generic_subdisplay = {
+ .name = "mcde_disp_generic_subdisplay",
+ .id = 1,
+ .port = &subdisplay_port,
+ .chnl_id = MCDE_CHNL_C1,
+ .fifo = MCDE_FIFO_C1,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+ .native_x_res = 864,
+ .native_y_res = 480,
+ .synchronized_update = false,
+ .dev = {
+ .platform_data = &generic_subdisplay_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_GENERIC_DSI_SECONDARY */
+
+
+#ifdef CONFIG_DISPLAY_AB8500_TERTIARY
+static struct mcde_port port_tvout1 = {
+ .type = MCDE_PORTTYPE_DPI,
+ .ifc = 0,
+ .link = 1,
+ .sync_src = MCDE_SYNCSRC_OFF,
+ .update_auto_trig = true,
+ .phy = {
+ .dpi = {
+ .num_data_lanes = 4, /* DDR mode */
+ },
+ },
+};
+
+static struct ab8500_display_platform_data ab8500_display_pdata = {
+ /* TODO use this ID as soon as we switch to newer kernel with support or
+ * ab8500 TVout regulator
+ .regulator_id = "v-tvout",
+ */
+};
+
+static int ab8500_platform_enable(struct mcde_display_device *ddev)
+{
+ int res = 0;
+ /* probe checks for pdata */
+ struct ab8500_display_platform_data *pdata = ddev->dev.platform_data;
+
+ pr_info("%s\n", __func__);
+ res = stm_gpio_altfuncenable(GPIO_ALT_LCD_PANELB);
+ if (res != 0)
+ goto alt_func_failed;
+
+ if (pdata->regulator) {
+ res = regulator_enable(pdata->regulator);
+ if (res != 0)
+ goto regu_failed;
+ }
+
+out:
+ return res;
+
+regu_failed:
+ (void) stm_gpio_altfuncdisable(GPIO_ALT_LCD_PANELB);
+alt_func_failed:
+ dev_warn(&ddev->dev, "Failure during %s\n", __func__);
+ goto out;
+}
+
+static int ab8500_platform_disable(struct mcde_display_device *ddev)
+{
+ int res;
+ /* probe checks for pdata */
+ struct ab8500_display_platform_data *pdata = ddev->dev.platform_data;
+
+ dev_info(&ddev->dev, "%s\n", __func__);
+
+ res = stm_gpio_altfuncdisable(GPIO_ALT_LCD_PANELB);
+ if (res != 0)
+ goto alt_func_failed;
+
+ if (pdata->regulator) {
+ res = regulator_disable(pdata->regulator);
+ if (res != 0)
+ goto regu_failed;
+ }
+
+out:
+ return res;
+regu_failed:
+ (void) stm_gpio_altfuncenable(GPIO_ALT_LCD_PANELB);
+alt_func_failed:
+ dev_warn(&ddev->dev, "Failure during %s\n", __func__);
+ goto out;
+
+}
+
+static struct mcde_display_device tvout_ab8500_display = {
+ .name = "mcde_tv_ab8500",
+ .id = 2,
+ .port = &port_tvout1,
+ .chnl_id = MCDE_CHNL_B,
+ .fifo = MCDE_FIFO_B,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DPI_24BPP,
+ .native_x_res = 720,
+ .native_y_res = 576,
+ .synchronized_update = true,
+ .video_mode = {
+ .xres = 720,
+ .yres = 576,
+ },
+ .dev = {
+ .platform_data = &ab8500_display_pdata,
+ },
+
+ /* We might need to describe the std here:
+ * - there are different PAL / NTSC formats (do they require MCDE
+ * settings?)
+ */
+ .platform_enable = ab8500_platform_enable,
+ .platform_disable = ab8500_platform_disable,
+};
+
+static struct ab8500_denc_platform_data ab8500_denc_pdata = {
+ .ddr_enable = true,
+ .ddr_little_endian = false,
+};
+
+static struct platform_device ab8500_denc = {
+ .name = "ab8500_denc",
+ .id = -1,
+ .dev = {
+ .platform_data = &ab8500_denc_pdata,
+ },
+};
+#endif /* CONFIG_DISPLAY_AB8500_TERTIARY */
+
+#ifdef CONFIG_DISPLAY_AV8100_TERTIARY
+static struct mcde_port port2 = {
+ .type = MCDE_PORTTYPE_DSI,
+ .mode = MCDE_PORTMODE_CMD,
+ .ifc = 1,
+ .link = 2,
+ .sync_src = MCDE_SYNCSRC_TE0,
+ .update_auto_trig = true,
+ .phy = {
+ .dsi = {
+ .virt_id = 0,
+ .num_data_lanes = 2,
+ .ui = DSI_UNIT_INTERVAL_2,
+ },
+ },
+};
+
+struct mcde_display_generic_platform_data av8100_hdmi_pdata = {
+ .reset_gpio = 0,
+ .reset_delay = 1,
+ .regulator_id = NULL, /* TODO: "display_main" */
+ .ddb_id = 1,
+};
+
+static int av8100_platform_enable(struct mcde_display_device *dev)
+{
+#define GPIO1B_AFSLA_REG_OFFSET 0x20
+#define GPIO1B_AFSLB_REG_OFFSET 0x24
+
+ int ret = 0;
+ struct mcde_display_hdmi_platform_data *pdata =
+ dev->dev.platform_data;
+
+#ifdef AV8100_CUT_1_0
+ volatile u32 __iomem *gpio_68_remap;
+#endif
+#ifdef AV8100_CUT_2_1
+ volatile u32 __iomem *gpio_69_remap;
+#endif
+
+ /* HW trig begin */
+#ifdef AV8100_CUT_1_0
+ gpio_68_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET) + 1);
+
+ *gpio_68_remap &= 0xffffffef;
+ iounmap(gpio_68_remap);
+
+ gpio_68_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET) + 1);
+ *gpio_68_remap |= 0x10;
+ iounmap(gpio_68_remap);
+#endif
+
+#ifdef AV8100_CUT_2_1
+ gpio_69_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLB_REG_OFFSET) + 1);
+
+ *gpio_69_remap &= 0xffffffdf;
+ iounmap(gpio_69_remap);
+
+ gpio_69_remap = (u32 *) ioremap(
+ U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET,
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET + 3) -
+ (U8500_GPIO1_BASE + GPIO1B_AFSLA_REG_OFFSET) + 1);
+ *gpio_69_remap |= 0x20;
+ iounmap(gpio_69_remap);
+#endif
+ /* HW trig end */
+
+ if (pdata->reset_gpio)
+ gpio_set_value(pdata->reset_gpio, pdata->reset_high);
+ if (pdata->regulator)
+ ret = regulator_enable(pdata->regulator);
+ return ret;
+}
+
+static int av8100_platform_disable(struct mcde_display_device *dev)
+{
+ int ret = 0;
+ struct mcde_display_hdmi_platform_data *pdata =
+ dev->dev.platform_data;
+
+ if (pdata->reset_gpio)
+ gpio_set_value(pdata->reset_gpio, !pdata->reset_high);
+ if (pdata->regulator)
+ ret = regulator_disable(pdata->regulator);
+
+ return ret;
+}
+
+static struct mcde_display_device av8100_hdmi = {
+ .name = "av8100_hdmi",
+ .id = 2,
+ .port = &port2,
+ .chnl_id = MCDE_CHNL_B,
+ .fifo = MCDE_FIFO_B,
+ .default_pixel_format = MCDE_OVLYPIXFMT_RGB565,
+ .port_pixel_format = MCDE_PORTPIXFMT_DSI_24BPP,
+#ifdef CONFIG_AV8100_SDTV
+ .native_x_res = 720,
+ .native_y_res = 576,
+#else
+ .native_x_res = 1280,
+ .native_y_res = 720,
+#endif
+ .synchronized_update = true,
+ .dev = {
+ .platform_data = &av8100_hdmi_pdata,
+ },
+ .platform_enable = av8100_platform_enable,
+ .platform_disable = av8100_platform_disable,
+};
+#endif /* CONFIG_DISPLAY_AV8100_TERTIARY */
+
+static struct fb_info *fbs[3] = { NULL, NULL, NULL };
+static struct mcde_display_device *displays[3] = { NULL, NULL, NULL };
+
+static int display_registered_callback(struct notifier_block *nb,
+ unsigned long event, void *dev)
+{
+ struct mcde_display_device *ddev = dev;
+ u16 width, height;
+ bool rotate;
+ bool display_initialized;
+
+ if (event != MCDE_DSS_EVENT_DISPLAY_REGISTERED)
+ return 0;
+
+ if (ddev->id < 0 || ddev->id >= ARRAY_SIZE(fbs))
+ return 0;
+
+ mcde_dss_get_native_resolution(ddev, &width, &height);
+
+ display_initialized = (ddev->id == 0 && display_initialize_during_boot);
+ rotate = (ddev->id == 0 && rotate_main);
+ if (rotate) {
+ u16 tmp = height;
+ height = width;
+ width = tmp;
+ }
+
+ /* Create frame buffer */
+ fbs[ddev->id] = mcde_fb_create(ddev,
+ width, height,
+ width, height * 2,
+ ddev->default_pixel_format,
+ rotate ? FB_ROTATE_CW : FB_ROTATE_UR,
+ display_initialized);
+ if (IS_ERR(fbs[ddev->id]))
+ pr_warning("Failed to create fb for display %s\n", ddev->name);
+ else
+ pr_info("Framebuffer created (%s)\n", ddev->name);
+
+ return 0;
+}
+
+static struct notifier_block display_nb = {
+ .notifier_call = display_registered_callback,
+};
+
+int __init init_display_devices(void)
+{
+ int ret;
+
+ ret = mcde_dss_register_notifier(&display_nb);
+ if (ret)
+ pr_warning("Failed to register dss notifier\n");
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY
+ ret = mcde_display_device_register(&generic_display0);
+ if (ret)
+ pr_warning("Failed to register generic display device 0\n");
+ displays[0] = &generic_display0;
+#endif
+
+#ifdef CONFIG_DISPLAY_GENERIC_DSI_SECONDARY
+ ret = mcde_display_device_register(&generic_subdisplay);
+ if (ret)
+ pr_warning("Failed to register generic sub display device\n");
+ displays[1] = &generic_subdisplay;
+#endif
+
+#ifdef CONFIG_DISPLAY_AV8100_TERTIARY
+ ret = mcde_display_device_register(&av8100_hdmi);
+ if (ret)
+ pr_warning("Failed to register av8100_hdmi\n");
+ displays[2] = &av8100_hdmi;
+#endif
+#ifdef CONFIG_DISPLAY_AB8500_TERTIARY
+ ret = platform_device_register(&ab8500_denc);
+ if (ret)
+ pr_warning("Failed to register ab8500_denc device\n");
+ else {
+ ret = mcde_display_device_register(&tvout_ab8500_display);
+ if (ret)
+ pr_warning("Failed to register ab8500 tvout device\n");
+ displays[2] = &tvout_ab8500_display;
+ }
+#endif
+
+ return ret;
+}
+
+module_init(init_display_devices);
+#endif /* CONFIG_FB_MCDE */
+
static struct i2s_board_info stm_i2s_board_info[] __initdata = {
{
.modalias = "i2s_device.0",
@@ -1034,19 +1463,8 @@ static struct platform_device *platform_board_devs[] __initdata = {
&ab8500_gpadc_device,
&ab8500_bm_device,
&ux500_musb_device,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- &u8500_mcde2_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- &u8500_mcde3_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- &u8500_mcde1_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
- &u8500_mcde0_device,
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */
&ux500_b2r2_device,
+ &ux500_mcde_device,
#ifdef CONFIG_ANDROID_PMEM
&u8500_pmem_device,
&u8500_pmem_mio_device,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 66e3e98259a..056ecc26140 100755
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -480,22 +480,11 @@ static struct clk_lookup u8500_common_clkregs[] = {
CLK(tvclk, "tv", NULL),
/* With device names */
- CLK(mcdeclk, "U8500-MCDE.0", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.0", "hdmi"),
- CLK(tvclk, "U8500-MCDE.0", "tv"),
- CLK(lcdclk, "U8500-MCDE.0", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.1", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.1", "hdmi"),
- CLK(tvclk, "U8500-MCDE.1", "tv"),
- CLK(lcdclk, "U8500-MCDE.1", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.2", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.2", "hdmi"),
- CLK(tvclk, "U8500-MCDE.2", "tv"),
- CLK(lcdclk, "U8500-MCDE.2", "lcd"),
- CLK(mcdeclk, "U8500-MCDE.3", "mcde"),
- CLK(hdmiclk, "U8500-MCDE.3", "hdmi"),
- CLK(tvclk, "U8500-MCDE.3", "tv"),
- CLK(lcdclk, "U8500-MCDE.3", "lcd"),
+
+ CLK(mcdeclk, "mcde", "mcde"),
+ CLK(hdmiclk, "mcde", "hdmi"),
+ CLK(tvclk, "mcde", "tv"),
+ CLK(lcdclk, "mcde", "lcd"),
CLK(b2r2clk, "U8500-B2R2.0", NULL),
/* Register the clock sources */
diff --git a/arch/arm/mach-ux500/include/mach/ab8500_denc.h b/arch/arm/mach-ux500/include/mach/ab8500_denc.h
new file mode 100644
index 00000000000..917f75d01a1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/ab8500_denc.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * AB8500 tvout driver interface
+ *
+ * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __AB8500_DENC__H__
+#define __AB8500_DENC__H__
+
+struct ab8500_denc_platform_data {
+ /* Platform info */
+ bool ddr_enable;
+ bool ddr_little_endian;
+};
+
+enum ab8500_denc_TV_std {
+ TV_STD_PAL_BDGHI,
+ TV_STD_PAL_N,
+ TV_STD_PAL_M,
+ TV_STD_NTSC_M,
+};
+
+enum ab8500_denc_cr_filter_bandwidth {
+ TV_CR_NTSC_LOW_DEF_FILTER,
+ TV_CR_PAL_LOW_DEF_FILTER,
+ TV_CR_NTSC_HIGH_DEF_FILTER,
+ TV_CR_PAL_HIGH_DEF_FILTER,
+};
+
+enum ab8500_denc_phase_reset_mode {
+ TV_PHASE_RST_MOD_DISABLE,
+ TV_PHASE_RST_MOD_FROM_PHASE_BUF,
+ TV_PHASE_RST_MOD_FROM_INC_DFS,
+ TV_PHASE_RST_MOD_RST,
+};
+
+enum ab8500_denc_plug_time {
+ TV_PLUG_TIME_0_5S,
+ TV_PLUG_TIME_1S,
+ TV_PLUG_TIME_1_5S,
+ TV_PLUG_TIME_2S,
+ TV_PLUG_TIME_2_5S,
+ TV_PLUG_TIME_3S,
+};
+
+struct ab8500_denc_conf {
+ /* register settings for DENC_configuration */
+ bool act_output;
+ enum ab8500_denc_TV_std TV_std;
+ bool progressive;
+ bool test_pattern;
+ bool partial_blanking;
+ bool blank_all;
+ bool black_level_setup;
+ enum ab8500_denc_cr_filter_bandwidth cr_filter;
+ bool suppress_col;
+ enum ab8500_denc_phase_reset_mode phase_reset_mode;
+ bool dac_enable;
+ bool act_dc_output;
+};
+
+void ab8500_denc_power_up(void);
+void ab8500_denc_power_down(void);
+void ab8500_denc_reset(bool hard);
+
+void ab8500_denc_regu_setup(bool enable_v_tv, bool enable_lp_mode);
+void ab8500_denc_conf(struct ab8500_denc_conf *conf);
+void ab8500_denc_conf_plug_detect(bool enable, bool load_RC,
+ enum ab8500_denc_plug_time time);
+void ab8500_denc_mask_int_plug_det(bool plug, bool unplug);
+#endif /* __AB8500_DENC__H__ */
+
diff --git a/arch/arm/mach-ux500/include/mach/av8100.h b/arch/arm/mach-ux500/include/mach/av8100.h
deleted file mode 100755
index 73355229b6a..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __AV8100_H
-#define __AV8100_H
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-
-typedef enum av8100_error
-{
- AV8100_OK = 0x0,
- AV8100_INVALID_COMMAND = 0x1,
- AV8100_INVALID_INTERFACE = 0x2,
- AV8100_INVALID_IOCTL = 0x3,
- AV8100_COMMAND_FAIL = 0x4,
- AV8100_FWDOWNLOAD_FAIL = 0x5,
- AV8100_FAIL = 0xFF,
-}av8100_error;
-
-typedef enum interface
-{
- I2C_INTERFACE = 0x0,
- DSI_INTERFACE = 0x1,
-}interface;
-
-/** AV8100 - DSI dcs command set */
-typedef enum
-{
- DCS_VSYNC_START = 0x1,
- DCS_VSYNC_END = 0x11,
- DCS_HSYNC_START = 0x21,
- DCS_HSYNC_END = 0x31,
- DCS_SHORT_WRITE = 0x15,
- DCS_LONG_WRITE = 0x39,
- DCS_RGB565_PACKED = 0xE,
- DCS_RGB666_PACKED = 0x1E,
- DCS_RGB666_UNPACKED = 0x2E,
- DCS_RGB888_PACKED = 0x3E,
- DCS_RAM_WRITE = 0x3C,
- DCS_RAM_WRITE_CONTINUE = 0x2C,
- DCS_FW_DOWNLOAD = 0xDB,
- DCS_WRITE_UC = 0xDC,
- DCS_READ_UC = 0xDB,
- DCS_NEXT_FILED_TYPE = 0xDA,
- DCS_EXEC_UC = 0xDD,
-}dsi_dcs_command_type;
-
-/** AV8100 Operating modes */
-typedef enum
-{
- AV8100_OPMODE_SHUTDOWN = 0x1,
- AV8100_OPMODE_STANDBY,
- AV8100_OPMODE_SCAN,
- AV8100_OPMODE_INIT,
- AV8100_OPMODE_IDLE,
- AV8100_OPMODE_VIDEO
-}av8100_operating_mode;
-
-/** AV8100 status */
-#define AV8100_PLUGIN_NONE 0x00
-#define AV8100_HDMI_PLUGIN 0x01
-#define AV8100_CVBS_PLUGIN 0x02
-
-/** AV8100 Command Type */
-typedef enum
-{
- AV8100_COMMAND_VIDEO_INPUT_FORMAT = 0x1,
- AV8100_COMMAND_AUDIO_INPUT_FORMAT = 0x2,
- AV8100_COMMAND_VIDEO_OUTPUT_FORMAT = 0x3,
- AV8100_COMMAND_VIDEO_SCALING_FORMAT,
- AV8100_COMMAND_COLORSPACECONVERSION,
- AV8100_COMMAND_CEC_MESSAGEWRITE,
- AV8100_COMMAND_CEC_MESSAGEREAD_BACK,
- AV8100_COMMAND_DENC,
- AV8100_COMMAND_HDMI,
- AV8100_COMMAND_HDCP_SENDKEY,
- AV8100_COMMAND_HDCP_MANAGEMENT,
- AV8100_COMMAND_INFOFRAMES,
- AV8100_COMMAND_EDID_SECTIONREADBACK,
- AV8100_COMMAND_PATTERNGENERATOR,
-
-}av8100_command_type;
-
-/** AV8100 Command Type */
-typedef enum
-{
- AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17,
- AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8,
- AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x18,
- AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x9,
- AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x21,
- AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE = 0x14,
- AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE = 0x14,
- AV8100_COMMAND_DENC_SIZE = 0x7,
- AV8100_COMMAND_HDMI_SIZE = 0x4,
- AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0x9,
- AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4,
- AV8100_COMMAND_INFOFRAMES_SIZE = 0x22,
- AV8100_COMMAND_EDID_SECTIONREADBACK_SIZE = 0x81,
- AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4,
-}av8100_command_size;
-
-/** AV8100 structures register & command definitions */
-
-/** AV8100 Internal registers ~ Register 0x0 to 0xF */
-/** Internal registers for I2C operations */
-
-typedef enum
-{
- STANDBY_REG = 0x0,
- AV8100_5_VOLT_TIME_REG = 0x1,
- STANDBY_INTERRUPT_MASK_REG = 0x2,
- STANDBY_PENDING_INTERRUPT_REG = 0x3,
- GENERAL_INTERRUPT_MASK_REG = 0x4,
- GENERAL_INTERRUPT_REG = 0x5,
- GENERAL_STATUS_REG = 0x6,
- GPIO_CONFIGURATION_REG = 0x7,
- GENERAL_CONTROL_REG = 0x8,
- FIRMWARE_DOWNLOAD_ENTRY_REG = 0xF
-}internal_reg;
-
-struct av8100_registers_internal
-{
- volatile char standby;
- volatile char av8100_5_volt_time;
- volatile char standby_interrupt_mask;
- volatile char standby_pending_interrupt;
- volatile char general_interrupt_mask;
- volatile char general_interrupt;
- volatile char general_status;
- volatile char gpio_configuration;
- volatile char general_control;
- volatile char firmware_download_entry;
-};
-
-/** AV8100 Video Input Format Command */
-struct av8100_video_input_format_command
-{
-
- volatile char Identifier;
- volatile char Mode;
- volatile char Pixel_format;
- volatile char Htotal[2];
- volatile char Hactive[2];
- volatile char Vtotal[2];
- volatile char Vactive[2];
- volatile char Videomode;
- volatile char Number_DSI;
- volatile char Virtualchannelcommandmode;
- volatile char Virtualchannelvideomode;
- volatile char Linenumber[2];
- volatile char Tearingeffect;
- volatile char Master_Clock_frequency[4];
-};
-
-/** AV8100 Audio Input Format Command */
-struct av8100_audio_input_format_command
-{
-
- volatile char Identifier;
- volatile char I2SOrTDM;
- volatile char NumberofI2SentriesFreq;
- volatile char BitFormat;
- volatile char LPCMOrCompress;
- volatile char SlaveOrMaster;
- volatile char Mute;
-
-};
-
-/** AV8100 Video Output Format Command */
-struct av8100_video_output_format_command
-{
-
- volatile char Identifier;
- volatile char Formatter;
- volatile char VSYNCpolarity;
- volatile char HSYNCpolarity;
- volatile char Htotal[2];
- volatile char Hactive[2];
- volatile char Vtotal[2];
- volatile char Vactive[2];
- volatile char HSYNCstart[2];
- volatile char HSYNClength[2];
- volatile char VSYNCstart[2];
- volatile char VSYNClength[2];
- volatile char Pixelfrequency[4];
-};
-
-/** AV8100 Video Video Scaling Format Command */
-struct av8100_video_scaling_format_command
-{
- volatile char Identifier;
- volatile char Hstart[2];
- volatile char Hstop[2];
- volatile char Vstart[2];
- volatile char Vstop[2];
-};
-
-/** AV8100 Video Colorspace Conversion Command */
-struct av8100_colorspace_conversion_command
-{
- volatile char Identifier;
- volatile char C0[2];
- volatile char C1[2];
- volatile char C2[2];
- volatile char C3[2];
- volatile char C4[2];
- volatile char C5[2];
- volatile char C6[2];
- volatile char C7[2];
- volatile char C8[21];
- volatile char AOFFSET[2];
- volatile char BOFFSET[2];
- volatile char COFFSET[2];
- volatile char AMINIMUM;
- volatile char AMAXIMUM;
- volatile char BMINIMUM;
- volatile char BMAXIMUM;
- volatile char CMINIMUM;
- volatile char CMAXIMUM;
-};
-
-/** AV8100 Video CEC message */
-struct av8100_CEC_message
-{
- volatile char Identifier;
- volatile char PhysicaladdressAB;
- volatile char PhysicaladdressCD;
- volatile char Bufferlength;
- volatile char BufferData[16];
-};
-
-/** AV8100 Video CEC message Readback Command */
-struct av8100_CEC_message_readback_command
-{
- volatile char Identifier;
-};
-
-/** AV8100 Video HDMI Command */
-struct av8100_HDMI_command
-{
- volatile char Identifier;
- volatile char OFF_ON_AVMUTE;
- volatile char HDMI_DVI;
- volatile char DVIcontrolbit;
-};
-
-/** AV8100 Video HDCP sendkey Command */
-struct av8100_HDCP_sendkey_command
-{
- volatile char Identifier;
- volatile char Keynumber;
- volatile char Key[7];
-};
-
-/** AV8100 Video HDCP management Command */
-struct av8100_HDCP_management_command
-{
- volatile char Identifier;
- volatile char RequestHDCPauthentication;
- volatile char Requestencryptedtransmission;
- volatile char OESS_EESS;
-};
-
-/** AV8100 Video Infoframe Command */
-struct av8100_Infoframe_command
-{
- volatile char Identifier;
- volatile char Infoframetype;
- volatile char Infoframedata[30];
- volatile char InfoframeCRC;
-};
-
-/** AV8100 Video EDID section readback Command */
-struct av8100_EDIDsectionreadback_command
-{
- volatile char Identifier;
- volatile char EDIDaddress;
- volatile char EDIDblocknumber;
-};
-
-/** AV8100 Video Pattern Generator Command */
-struct av8100_PatternGenerator_command
-{
- volatile char Identifier;
- volatile char Testtypeselection;
- volatile char VideoPatterngeneratorselection;
- volatile char AudioSound;
-};
-
-/** AV8100 Video Command return */
-struct av8100_command_return
-{
- volatile char Identifier;
- volatile char OK_FAIL;
-};
-
-/** AV8100 Video CEC messgae readback command */
-struct av8100_EDID_section_readback
-{
- volatile char Identifier;
- volatile char OK_FAIL;
- volatile char EDID[128];
-};
-
-typedef enum{
- AV8100_AUDIO_I2S_MODE,
- AV8100_AUDIO_I2SDELAYED_MODE, /* I2S Mode by default*/
- AV8100_AUDIO_TDM_MODE /* 8 Channels by default*/
-} av8100_audio_if_format;
-
-typedef enum{
- AV8100_AUDIO_MUTE_DISABLE,
- AV8100_AUDIO_MUTE_ENABLE
-} av8100_audio_mute;
-
-typedef enum{
- AV8100_AUDIO_SLAVE,
- AV8100_AUDIO_MASTER
-} av8100_audio_if_mode;
-
-typedef enum{
- AV8100_AUDIO_LPCM_MODE,
- AV8100_AUDIO_COMPRESS_MODE
-} av8100_audio_format;
-
-typedef enum{
- AV8100_AUDIO_16BITS,
- AV8100_AUDIO_20BITS,
- AV8100_AUDIO_24BITS
-} av8100_audio_word_length;
-
-typedef enum{
- AV8100_AUDIO_FREQ_32KHZ,
- AV8100_AUDIO_FREQ_44_1KHZ,
- AV8100_AUDIO_FREQ_48KHZ,
- AV8100_AUDIO_FREQ_64KHZ,
- AV8100_AUDIO_FREQ_88_2KHZ,
- AV8100_AUDIO_FREQ_96KHZ,
- AV8100_AUDIO_FREQ_128KHZ,
- AV8100_AUDIO_FREQ_176_1KHZ,
- AV8100_AUDIO_FREQ_192KHZ
-} av8100_sample_freq;
-
-
-typedef enum{
- AV8100_PATTERN_AUDIO_OFF,
- AV8100_PATTERN_AUDIO_ON,
- AV8100_PATTERN_AUDIO_I2S_MEM
-} av8100_pattern_audio;
-
-typedef enum{
- AV8100_PATTERN_OFF,
- AV8100_PATTERN_GENERATOR,
- AV8100_PRODUCTION_TESTING
-} av8100_pattern_type;
-
-typedef enum{
- AV8100_NO_PATTERN,
- AV8100_PATTERN_VGA,
- AV8100_PATTERN_720P,
- AV8100_PATTERN_1080P
-} av8100_pattern_format;
-
-typedef enum{
- AV8100_HDMI_OFF,
- AV8100_HDMI_ON,
- AV8100_HDMI_AVMUTE
-} av8100_hdmi_mode;
-
-typedef enum{
- AV8100_HDMI,
- AV8100_DVI
-} av8100_hdmi_format;
-
-typedef enum{
- AV8100_DVI_CTRL_CTL0,
- AV8100_DVI_CTRL_CTL1,
- AV8100_DVI_CTRL_CTL2
-} av8100_DVI_format;
-
-typedef enum{
- AV8100_TV_LINES_625 = 0,
- AV8100_TV_LINES_525
-} av8100_TV_lines;
-
-typedef enum{
- AV8100_TV_STD_PALBDGHI = 0,
- AV8100_TV_STD_PALN,
- AV8100_TV_STD_NTSCM,
- AV8100_TV_STD_PALM
-} av8100_TV_std;
-
-typedef enum{
- AV8100_DENC_OFF = 0,
- AV8100_DENC_ON
-} av8100_DENC_State;
-
-typedef enum{
- AV8100_MACROVISION_OFF = 0,
- AV8100_MACROVISION_ON
-} av8100_macrovision_state;
-
-typedef enum{
- AV8100_INTERNAL_GENERATOR_OFF = 0,
- AV8100_INTERNAL_GENERATOR_ON
-} av8100_internal_generator_state;
-
-typedef enum{
- AV8100_CHROMA_CWS_CAPTURE_OFF = 0,
- AV8100_CHROMA_CWS_CAPTURE_ON
-} av8100_chroma_cws_capture_state;
-
-typedef enum{
- AV8100_SYNC_POSITIVE,
- AV8100_SYNC_NEGATIVE
-} av8100_video_sync_pol;
-
-typedef enum{
-
- AV8100_INPUT_PIX_RGB565,
- AV8100_INPUT_PIX_RGB666,
- AV8100_INPUT_PIX_RGB666P,
- AV8100_INPUT_PIX_RGB888,
- AV8100_INPUT_PIX_YCBCR422
-} av8100_pixel_format;
-
-typedef enum{
- AV8100_TE_OFF, /* NO TE*/
- AV8100_TE_DSI_LANE, /* TE generated on DSI lane */
- AV8100_TE_IT_LINE, /* TE generated on IT line (GPIO) */
- AV8100_TE_DSI_IT /* TE generatedon both DSI lane & IT line*/
-} av8100_te_config;
-
-typedef enum{
-
- AV8100_DATA_LANES_USED_0, /* 0 DSI data lane connected*/
- AV8100_DATA_LANES_USED_1, /* 1 DSI data lane connected */
- AV8100_DATA_LANES_USED_2, /* 2 DSI data lane connected */
- AV8100_DATA_LANES_USED_3, /* 3 DSI data lane connected */
- AV8100_DATA_LANES_USED_4 /* 4 DSI data lane connected */
-} av8100_dsi_nb_data_lane;
-
-typedef enum{
-
- AV8100_VIDEO_INTERLACE,
- AV8100_VIDEO_PROGRESSIVE
-} av8100_video_mode;
-
-typedef enum{
-
- AV8100_HDMI_DSI_OFF,
- AV8100_HDMI_DSI_COMMAND_MODE,
- AV8100_HDMI_DSI_VIDEO_MODE
-} av8100_dsi_mode;
-
-/* AV8100 video modes */
-typedef enum{
- AV8100_CUSTOM,
- AV8100_CEA1_640X480P_59_94HZ,
- AV8100_CEA2_3_720X480P_59_94HZ, // new
- AV8100_CEA4_1280X720P_60HZ,
- AV8100_CEA5_1920X1080I_60HZ,
- AV8100_CEA6_7_NTSC_60HZ, //new
- AV8100_CEA14_15_480p_60HZ, //new
- AV8100_CEA16_1920X1080P_60HZ, //new
- AV8100_CEA17_18_720X576P_50HZ, //new
- AV8100_CEA19_1280X720P_50HZ,
- AV8100_CEA20_1920X1080I_50HZ,
- AV8100_CEA21_22_576I_PAL_50HZ, //new
- AV8100_CEA29_30_576P_50HZ, //new
- AV8100_CEA31_1920x1080P_50Hz, //new
- AV8100_CEA32_1920X1080P_24HZ,
- AV8100_CEA33_1920X1080P_25HZ,
- AV8100_CEA34_1920X1080P_30HZ,
- AV8100_CEA60_1280X720P_24HZ,
- AV8100_CEA61_1280X720P_25HZ,
- AV8100_CEA62_1280X720P_30HZ,
- AV8100_VESA9_800X600P_60_32HZ,
- AV8100_VESA14_848X480P_60HZ,
- AV8100_VESA16_1024X768P_60HZ,
- AV8100_VESA22_1280X768P_59_99HZ,
- AV8100_VESA23_1280X768P_59_87HZ,
- AV8100_VESA27_1280X800P_59_91HZ,
- AV8100_VESA28_1280X800P_59_81HZ,
- AV8100_VESA39_1360X768P_60_02HZ,
- AV8100_VESA81_1366X768P_59_79HZ,
- AV8100_VIDEO_OUTPUT_CEA_VESA_MAX
-} av8100_output_CEA_VESA;
-
-/** AV8100 internal register access structure*/
-struct av8100_register
-{
- char value;
- char offset;
-};
-
-/** AV8100 command configuration registers access structure*/
-struct av8100_command_register
-{
- unsigned char cmd_id; /* input */
- unsigned char buf_len; /* input, output */
- unsigned char buf[128]; /* input, output */
- unsigned char return_status; /* output */
-};
-
-/* IOCTL return status */
-#define HDMI_COMMAND_RETURN_STATUS_OK 0
-#define HDMI_COMMAND_RETURN_STATUS_FAIL 1
-
-#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2
-#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16
-
-/** AV8100 status structure*/
-struct av8100_status
-{
- char av8100_state;
- char av8100_plugin_status;
-};
-
-/** Maximum size of the structure need to passed to AV8100 */
-
-#define AV8100_IOC_MAGIC 0xcc
-
-/** IOCTL Operations for accessing information from AV8100 */
-
-#define IOC_AV8100_READ_REGISTER _IOWR(AV8100_IOC_MAGIC,1,struct av8100_register)
-#define IOC_AV8100_WRITE_REGISTER _IOWR(AV8100_IOC_MAGIC,2,struct av8100_register)
-#define IOC_AV8100_SEND_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,3,struct av8100_command_register)
-//#define IOC_AV8100_READ_CONFIGURATION_COMMAND _IOWR(AV8100_IOC_MAGIC,4,struct av8100_command_register)
-#define IOC_AV8100_GET_STATUS _IOWR(AV8100_IOC_MAGIC,4,struct av8100_status)
-#define IOC_AV8100_ENABLE _IOWR(AV8100_IOC_MAGIC,5,struct av8100_status)
-#define IOC_AV8100_DISABLE _IOWR(AV8100_IOC_MAGIC,6,struct av8100_status)
-#define IOC_AV8100_SET_VIDEO_FORMAT _IOWR(AV8100_IOC_MAGIC,7,struct av8100_status)
-#define IOC_AV8100_HDMI_ON _IOWR(AV8100_IOC_MAGIC,8,struct av8100_status)
-#define IOC_AV8100_HDMI_OFF _IOWR(AV8100_IOC_MAGIC,9,struct av8100_status)
-
-#define AV8100_IOC_MAXNR (1)
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(__AV8100_H) */
diff --git a/arch/arm/mach-ux500/include/mach/av8100_fw.h b/arch/arm/mach-ux500/include/mach/av8100_fw.h
deleted file mode 100755
index b4243c00c55..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100_fw.h
+++ /dev/null
@@ -1,1041 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-/* AV8100 Firmware version : V3.03 */
-#define fw_size 16384
-char ReceiveTab[fw_size];
-char TransmitTab[fw_size];
-char av8100_fw_buff[fw_size] = {
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-};
-
diff --git a/arch/arm/mach-ux500/include/mach/av8100_p.h b/arch/arm/mach-ux500/include/mach/av8100_p.h
deleted file mode 100755
index 9eadd7c2887..00000000000
--- a/arch/arm/mach-ux500/include/mach/av8100_p.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <mach/av8100.h>
-
-/* defines for av8100_ */
-#define AV8100_COMMAND_OFFSET 0x10
-#define AV8100_COMMAND_MAX_LENGTH 0x81
-#define GPIO_AV8100_RSTN 196
-#define GPIO_AV8100_INT 192
-#define AV8100_DRIVER_MINOR_NUMBER 240
-
-/* Standby register */
-#define STANDBY_HPDS_HDMI_PLUGGED 0x04
-#define STANDBY_CVBS_TV_CABLE_PLUGGED 0x08
-
-/* Standby interrupts */
-#define HDMI_HOTPLUG_INTERRUPT 0x1
-#define HDMI_HOTPLUG_INTERRUPT_MASK 0xFE
-#define CVBS_PLUG_INTERRUPT 0x2
-#define CVBS_PLUG_INTERRUPT_MASK 0xFD
-#define STANDBY_INTERRUPT_MASK_ALL 0xF0
-
-/* General interrupts */
-#define UNDER_OVER_FLOW_INTERRUPT 0x20
-#define UNDER_OVER_FLOW_INTERRUPT_MASK 0xDF
-#define TE_INTERRUPT 0x40
-#define TE_INTERRUPT_MASK 0xCF
-#define GENERAL_INTERRUPT_MASK_ALL 0x00
-
-/* General status */
-#define AV8100_GENERAL_STATUS_UC_READY 0x8
-
-#define REG_16_8_LSB(p) (unsigned char)(p & 0xFF)
-#define REG_16_8_MSB(p) (unsigned char)((p & 0xFF00)>>8)
-#define REG_32_8_MSB(p) (unsigned char)((p & 0xFF000000)>>24)
-#define REG_32_8_MMSB(p) (unsigned char)((p & 0x00FF0000)>>16)
-#define REG_32_8_MLSB(p) (unsigned char)((p & 0x0000FF00)>>8)
-#define REG_32_8_LSB(p) (unsigned char)(p & 0x000000FF)
-
-/**
- * struct av8100_cea - CEA(consumer electronic access) standard structure
- * @cea_id:
- * @cea_nb:
- * @vtotale:
- **/
-
- typedef struct {
- char cea_id[40] ;
- int cea_nb ;
- int vtotale;
- int vactive;
- int vsbp ;
- int vslen ;
- int vsfp;
- char vpol[5];
- int htotale;
- int hactive;
- int hbp ;
- int hslen ;
- int hfp;
- int frequence;
- char hpol[5];
- int reg_line_duration;
- int blkoel_duration;
- int uix4;
- int pll_mult;
- int pll_div;
-}av8100_cea;
-
-/**
- * struct av8100_data - av8100_ internal structure
- * @client: pointer to i2c client
- * @work: work_struct scheduled during bottom half
- * @sem: semaphore used for data protection
- * @device_type: hdmi or cvbs
- * @edid: extended display identification data
- **/
-struct av8100_data{
- struct i2c_client *client;
- struct work_struct work;
- struct semaphore sem;
- char device_type;
- char edid[127];
-};
-
-/**
- * struct av8100_platform_data - av8100_ platform data
- * @irq: irq num
- **/
-struct av8100_platform_data {
- unsigned gpio_base;
- int irq;
-};
-
-typedef struct {
- u16 c0;
- u16 c1;
- u16 c2;
- u16 c3;
- u16 c4;
- u16 c5;
- u16 c6;
- u16 c7;
- u16 c8;
- u16 a_offset;
- u16 b_offset;
- u16 c_offset;
- u8 l_max;
- u8 l_min;
- u8 c_max;
- u8 c_min;
-} av8100_color_space_conversion_cmd;
-
-/**
- * struct av8100_video_input_format_cmd - video input format structure
- * @dsi_input_mode:
- * @input_pixel_format:
- * @total_horizontal_pixel:
- **/
-typedef struct {
- av8100_dsi_mode dsi_input_mode;
- av8100_pixel_format input_pixel_format;
- unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
- unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
- unsigned short total_vertical_lines; /*number of total vertical lines in the frame*/
- unsigned short total_vertical_active_lines; /*number of total vertical active lines*/
- av8100_video_mode video_mode;
- av8100_dsi_nb_data_lane nb_data_lane;
- unsigned char nb_virtual_ch_command_mode;
- unsigned char nb_virtual_ch_video_mode;
- unsigned short TE_line_nb; /* Tearing effect line number*/
- av8100_te_config TE_config;
- unsigned long master_clock_freq; /* Master clock frequency in HZ */
- unsigned char ui_x4;
-} av8100_video_input_format_cmd;
-
-/**
- * struct av8100_video_output_format_cmd - video output format structure
- * @dsi_input_mode:
- * @input_pixel_format:
- * @total_horizontal_pixel:
- **/
-typedef struct {
- av8100_output_CEA_VESA video_output_cea_vesa;
- av8100_video_sync_pol vsync_polarity;
- av8100_video_sync_pol hsync_polarity;
- unsigned short total_horizontal_pixel; /*number of total horizontal pixels in the frame*/
- unsigned short total_horizontal_active_pixel; /*number of total horizontal active pixels in the frame*/
- unsigned short total_vertical_in_half_lines; /*number of total vertical lines in the frame*/
- unsigned short total_vertical_active_in_half_lines; /*number of total vertical active lines*/
- unsigned short hsync_start_in_pixel;
- unsigned short hsync_length_in_pixel;
- unsigned short vsync_start_in_half_line;
- unsigned short vsync_length_in_half_line;
- unsigned long pixel_clock_freq_Hz;
-} av8100_video_output_format_cmd;
-/**
- * struct av8100_pattern_generator_cmd - pattern generator format structure
- * @pattern_type:
- * @pattern_video_format:
- * @pattern_audio_mode:
- **/
-typedef struct {
- av8100_pattern_type pattern_type;
- av8100_pattern_format pattern_video_format;
- av8100_pattern_audio pattern_audio_mode;
-} av8100_pattern_generator_cmd;
-/**
- * struct av8100_audio_input_format_cmd - audio input format structure
- * @audio_input_if_format:
- * @i2s_input_nb:
- * @sample_audio_freq:
- **/
-typedef struct {
- av8100_audio_if_format audio_input_if_format; /* mode of the MSP*/
- unsigned char i2s_input_nb; /* 0, 1 2 3 4*/
- av8100_sample_freq sample_audio_freq;
- av8100_audio_word_length audio_word_lg;
- av8100_audio_format audio_format;
- av8100_audio_if_mode audio_if_mode;
- av8100_audio_mute audio_mute;
-} av8100_audio_input_format_cmd;
-/**
- * struct av8100_video_scaling_format_cmd - video scaling format structure
- * @h_start_in_pixel:
- * @h_stop_in_pixel:
- * @v_start_in_line:
- **/
-typedef struct {
- unsigned short h_start_in_pixel;
- unsigned short h_stop_in_pixel;
- unsigned short v_start_in_line;
- unsigned short v_stop_in_line;
-} av8100_video_scaling_format_cmd;
-/**
- * struct av8100_hdmi_cmd - hdmi command structure
- * @hdmi_mode:
- * @hdmi_format:
- * @dvi_format:
- **/
-typedef struct {
- av8100_hdmi_mode hdmi_mode;
- av8100_hdmi_format hdmi_format;
- av8100_DVI_format dvi_format; /* used only if HDMI_format = DVI*/
-} av8100_hdmi_cmd;
-
-/**
- * struct av8100_denc_cmd - denc command structure
- **/
-typedef struct {
- av8100_TV_lines tv_lines;
- av8100_TV_std tv_std;
- av8100_DENC_State denc;
- av8100_macrovision_state macrovision;
- av8100_internal_generator_state internal_generator;
- av8100_chroma_cws_capture_state chroma;
-} av8100_denc_cmd;
-
-/* STWav8100 Private functions */
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 0c998217275..a5973d85d7d 100755
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -27,10 +27,7 @@ extern struct platform_device ux500_i2c_controller1;
extern struct platform_device ux500_i2c_controller2;
extern struct platform_device ux500_i2c_controller3;
extern struct platform_device u8500_i2c4_device;
-extern struct platform_device u8500_mcde2_device;
-extern struct platform_device u8500_mcde3_device;
-extern struct platform_device u8500_mcde1_device;
-extern struct platform_device u8500_mcde0_device;
+extern struct platform_device ux500_mcde_device;
extern struct platform_device u8500_hsit_device;
extern struct platform_device u8500_hsir_device;
extern struct platform_device u8500_shrm_device;
diff --git a/arch/arm/mach-ux500/include/mach/dsi.h b/arch/arm/mach-ux500/include/mach/dsi.h
deleted file mode 100755
index fad90f199d4..00000000000
--- a/arch/arm/mach-ux500/include/mach/dsi.h
+++ /dev/null
@@ -1,770 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _DSI_H_
-#define _DSI_H_
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-#include <mach/mcde.h>
-#ifdef __KERNEL__
-
-#define DSI_DPHY_Z_CALIB_OUT_VALID 0x1
-/*******************************************************************************
-DSI Error Enums
-******************************************************************************/
-
-
- typedef enum
- {
- DSI_OK = 0x1, /** No error.*/
- DSI_NO_PENDING_EVENT_ERROR = 0x2,
- DSI_NO_MORE_FILTER_PENDING_EVENT = 0x3,
- DSI_NO_MORE_PENDING_EVENT = 0x4,
- DSI_REMAINING_FILTER_PENDING_EVENTS = 0x5,
- DSI_REMAINING_PENDING_EVENTS = 0x6,
- DSI_INTERNAL_EVENT = 0x7,
- DSI_INTERNAL_ERROR = 0x8,
- DSI_NOT_CONFIGURED = 0x9,
- DSI_REQUEST_PENDING = 0xA,
- DSI_PLL_PROGRAM_ERROR = 0xB,
- DSI_CLOCK_LANE_NOT_READY = 0xC,
- DSI_DATA_LANE1_NOT_READY = 0xD,
- DSI_DATA_LANE2_NOT_READY = 0xE,
- DSI_REQUEST_NOT_APPLICABLE = 0x10,
- DSI_INVALID_PARAMETER = 0x11,
- DSI_UNSUPPORTED_FEATURE = 0x12,
- DSI_UNSUPPORTED_HW = 0x13
- }dsi_error;
-
-/********************************************************************************
-DSI Interrupt Type Enums
-********************************************************************************/
-#define DSI_NO_INTERRUPT 0x0
-
-typedef enum
-{
- DSI_IRQ_TYPE_MCTL_MAIN = 0x01,
- DSI_IRQ_TYPE_CMD_MODE = 0x02,
- DSI_IRQ_TYPE_DIRECT_CMD_MODE = 0x03,
- DSI_IRQ_TYPE_DIRECT_CMD_RD_MODE = 0x04,
- DSI_IRQ_TYPE_VID_MODE = 0x05,
- DSI_IRQ_TYPE_TG = 0x06,
- DSI_IRQ_TYPE_DPHY_ERROR = 0x07,
- DSI_IRQ_TYPE_DPHY_CLK_TRIM_RD = 0x08
-} dsi_irq_type;
-
-
-
-
-/*******************************************************************************
- DSI Main Setting Registers Enums and structures
-******************************************************************************/
-
- typedef enum
- {
- DSI_INT_MODE_DISABLE = 0x00,
- DSI_INT_MODE_ENABLE = 0x01
- }dsi_int_mode;
-
- typedef enum
- {
- DSI_VSG_MODE_DISABLE = 0x00,
- DSI_VSG_MODE_ENABLE = 0x01
- }dsi_vsg_ctrl;
-
- typedef enum
- {
- DSI_TVG_MODE_DISABLE = 0x00,
- DSI_TVG_MODE_ENABLE = 0x01
- }dsi_tvg_ctrl;
-
- typedef enum
- {
- DSI_TBG_MODE_DISABLE = 0x00,
- DSI_TBG_MODE_ENABLE = 0x01
- }dsi_tbg_ctrl;
-
- typedef enum
- {
- DSI_RD_MODE_DISABLE = 0x00,
- DSI_RD_MODE_ENABLE = 0x01
- }dsi_rd_ctrl;
-
-
- typedef enum
- {
- DSI_SIGNAL_LOW = 0x0,
- DSI_SIGNAL_HIGH = 0x1
- }dsi_signal_state;
-
- typedef enum
- {
- DSI_LINK0 = 0x00,
- DSI_LINK1 = 0x01,
- DSI_LINK2 = 0x02
- }dsi_link;
-
- typedef enum
- {
- DSI_COMMAND_MODE = 0x0,
- DSI_VIDEO_MODE = 0x1,
- DSI_INTERFACE_BOTH = 0x2,
- DSI_INTERFACE_NONE = 0x3
- }dsi_interface_mode;
-
- typedef enum
- {
- DSI_INTERFACE_1 = 0x0,
- DSI_INTERFACE_2 = 0x1
- }dsi_interface;
-
- typedef enum
- {
- DSI_DISABLE = 0x0,
- DSI_ENABLE = 0x1
- }dsi_link_state;
-
- typedef enum
- {
- DSI_SIGNAL_RESET = 0x0,
- DSI_SIGNAL_SET = 0x1
- }dsi_stall_signal_state;
-
- typedef enum
- {
- DSI_IF1_DISABLE = 0x0,
- DSI_IF1_ENABLE = 0x1
- }dsi_if1_state;
-
- typedef enum
- {
- DSI_IF_DISABLE = 0x0,
- DSI_IF_ENABLE = 0x1
- }dsi_if_state;
-
- typedef enum
- {
- DSI_PLL_IN_CLK_27 = 0x0,/** from TV PLL*/
- DSI_PLL_IN_CLK_26 = 0x1 /** from system PLL*/
- }dsi_pll_clk_in;
-
- typedef enum
- {
- DSI_PLL_STOP = 0x0,
- DSI_PLL_START = 0x1
- }dsi_pll_mode;
-
- typedef enum
- {
- DSI_BTA_DISABLE = 0x0,
- DSI_BTA_ENABLE = 0x1
- }dsi_bta_mode;
-
- typedef enum
- {
- DSI_ECC_GEN_DISABLE = 0x0,
- DSI_ECC_GEN_ENABLE = 0x1
- }dsi_ecc_gen_mode;
-
- typedef enum
- {
- DSI_CHECKSUM_GEN_DISABLE = 0x0,
- DSI_CHECKSUM_GEN_ENABLE = 0x1
- }dsi_checksum_gen_mode;
-
- typedef enum
- {
- DSI_EOT_GEN_DISABLE = 0x0,
- DSI_EOT_GEN_ENABLE = 0x1
- }dsi_eot_gen_mode;
-
- typedef enum
- {
- DSI_HOST_EOT_GEN_DISABLE = 0x0,
- DSI_HOST_EOT_GEN_ENABLE = 0x1
- }dsi_host_eot_gen_mode;
-
- typedef enum
- {
- DSI_LANE_STOP = 0x0,
- DSI_LANE_START = 0x1
- }dsi_lane_state;
- typedef enum
- {
- DSI_LANE_DISABLE = 0x0,
- DSI_LANE_ENABLE = 0x1
- }dsi_lane_mode;
- typedef enum
- {
- DSI_CLK_CONTINIOUS_HS_DISABLE = 0x0,
- DSI_CLK_CONTINIOUS_HS_ENABLE = 0x1
- }dsi_clk_continious_hs_mode;
- typedef enum
- {
- DSI_INTERNAL_PLL = 0x0,
- DSI_SYSTEM_PLL = 0x1
- }pll_out_sel; /** DPHY HS bit clock select*/
- typedef enum
- {
- HS_INVERT_DISABLE = 0x0,
- HS_INVERT_ENABLE = 0x1
- }dsi_hs_invert_mode;
- typedef enum
- {
- HS_SWAP_PIN_DISABLE = 0x0,
- HS_SWAP_PIN_ENABLE = 0x1
- }dsi_swap_pin_mode;
- typedef enum
- {
- DSI_PLL_MASTER = 0x0,
- DSI_PLL_SLAVE = 0x1
- }dsi_pll_mode_sel;
-
- typedef struct
- {
- u8 multiplier;
- u8 division_ratio;
- dsi_pll_clk_in pll_in_sel;
- pll_out_sel pll_out_sel;
- dsi_pll_mode_sel pll_master;
- }dsi_pll_ctl;
-
- typedef enum
- {
- DSI_REG_TE = 0x00,
- DSI_IF_TE = 0x01
- }dsi_te_sel;
-
- typedef struct
- {
- dsi_te_sel te_sel;
- dsi_interface interface;
- }dsi_te_en;
-
- typedef enum
- {
- DSI_TE_DISABLE = 0x0,
- DSI_TE_ENABLE = 0x1
- }dsi_te_ctrl;
-
- typedef enum
- {
- DSI_CLK_LANE = 0x00,
- DSI_DATA_LANE1 = 0x01,
- DSI_DATA_LANE2 = 0x02
- }dsi_lane;
-
- typedef enum
- {
- DSI_DAT_LANE1 = 0x0,
- DSI_DAT_LANE2 = 0x1
- }dsi_data_lane;
-
- typedef enum
- {
- DSI_CLK_LANE_START = 0x00,
- DSI_CLK_LANE_IDLE = 0x01,
- DSI_CLK_LANE_HS = 0x02,
- DSI_CLK_LANE_ULPM = 0x03
- }dsi_clk_lane_state;
- typedef enum
- {
- DSI_CLK_LANE_LPM = 0x0,
- DSI_CLK_LANE_HSM = 0x01
- }dsi_interface_mode_type;
- typedef enum
- {
- DSI_DATA_LANE_START = 0x000,
- DSI_DATA_LANE_IDLE = 0x001,
- DSI_DATA_LANE_WRITE = 0x002,
- DSI_DATA_LANE_ULPM = 0x003,
- DSI_DATA_LANE_READ = 0x004
- }dsi_data_lane_state;
-
- typedef struct
- {
- u8 clk_div;
- u16 hs_tx_timeout;
- u16 lp_rx_timeout;
- }dsi_dphy_timeout;
-
- typedef enum
- {
- DSI_PLL_LOCK = 0x01,
- DSI_CLKLANE_READY = 0x02,
- DSI_DAT1_READY = 0x04,
- DSI_DAT2_READY = 0x08,
- DSI_HSTX_TO_ERROR = 0x10,
- DSI_LPRX_TO_ERROR = 0x20,
- DSI_CRS_UNTERM_PCK = 0x40,
- DSI_VRS_UNTERM_PCK = 0x80
- }dsi_link_status;
-
- typedef struct
- {
- u16 if_data;
- dsi_signal_state if_valid;
- dsi_signal_state if_start;
- dsi_signal_state if_frame_sync;
- }dsi_int_read;
-
- typedef enum
- {
- DSI_ERR_SOT_HS_1 = 0x1,
- DSI_ERR_SOT_HS_2 = 0x2,
- DSI_ERR_SOTSYNC_1 = 0x4,
- DSI_ERR_SOTSYNC_2 = 0x8,
- DSI_ERR_EOTSYNC_1 = 0x10,
- DSI_ERR_EOTSYNC_2 = 0x20,
- DSI_ERR_ESC_1 = 0x40,
- DSI_ERR_ESC_2 = 0x80,
- DSI_ERR_SYNCESC_1 = 0x100,
- DSI_ERR_SYNCESC_2 = 0x200,
- DSI_ERR_CONTROL_1 = 0x400,
- DSI_ERR_CONTROL_2 = 0x800,
- DSI_ERR_CONT_LP0_1 = 0x1000,
- DSI_ERR_CONT_LP0_2 = 0x2000,
- DSI_ERR_CONT_LP1_1 = 0x4000,
- DSI_ERR_CONT_LP1_2 = 0x8000,
- }dsi_dphy_err;
-
- typedef enum
- {
- DSI_VIRTUAL_CHANNEL_0 = 0x0,
- DSI_VIRTUAL_CHANNEL_1 = 0x1,
- DSI_VIRTUAL_CHANNEL_2 = 0x2,
- DSI_VIRTUAL_CHANNEL_3 = 0x3
- }dsi_virtual_ch;
-
- typedef enum
- {
- DSI_ERR_NO_TE = 0x1,
- DSI_ERR_TE_MISS = 0x2,
- DSI_ERR_SDI1_UNDERRUN = 0x4,
- DSI_ERR_SDI2_UNDERRUN = 0x8,
- DSI_ERR_UNWANTED_RD = 0x10,
- DSI_CSM_RUNNING = 0x20
- }dsi_cmd_mode_sts;
-
- typedef enum
- {
- DSI_COMMAND_DIRECT = 0x0,
- DSI_COMMAND_GENERIC = 0x1
- }dsi_cmd_type;
-
- typedef struct
- {
- u16 rd_size;
- dsi_virtual_ch rd_id;
- dsi_cmd_type cmd_type;
- }dsi_cmd_rd_property;
-
- typedef enum
- {
- DSI_CMD_WRITE = 0x0,
- DSI_CMD_READ = 0x1,
- DSI_CMD_TE_REQUEST = 0x4,
- DSI_CMD_TRIGGER_REQUEST = 0x5,
- DSI_CMD_BTA_REQUEST = 0x6
- }dsi_cmd_nat;
-
- typedef enum
- {
- DSI_CMD_SHORT = 0x0,
- DSI_CMD_LONG = 0x1
- }dsi_cmd_packet;
-
- typedef struct
- {
- u8 rddat0;
- u8 rddat1;
- u8 rddat2;
- u8 rddat3;
- }dsi_cmd_rddat;
-
- typedef struct
- {
- dsi_cmd_nat cmd_nature;
- dsi_cmd_packet packet_type;
- u8 cmd_header;
- dsi_virtual_ch cmd_id;
- u8 cmd_size;
- dsi_link_state cmd_lp_enable;
- u8 cmd_trigger_val;
- }dsi_cmd_main_setting;
-
- typedef enum
- {
- DSI_CMD_TRANSMISSION = 0x1,
- DSI_WRITE_COMPLETED = 0x2,
- DSI_TRIGGER_COMPLETED = 0x4,
- DSI_READ_COMPLETED = 0x8,
- DSI_ACKNOWLEDGE_RECEIVED = 0x10,
- DSI_ACK_WITH_ERR_RECEIVED = 0x20,
- DSI_TRIGGER_RECEIVED = 0x40,
- DSI_TE_RECEIVED = 0x80,
- DSI_BTA_COMPLETED = 0x100,
- DSI_BTA_FINISHED = 0x200,
- DSI_READ_COMPLETED_WITH_ERR = 0x400,
- DSI_TRIGGER_VAL = 0x7800,
- DSI_ACK_VAL = 0xFFFF0000
- }dsi_direct_cmd_sts;
-
- typedef enum
- {
- DSI_TE_256 = 0x00,
- DSI_TE_512 = 0x01,
- DSI_TE_1024 = 0x02,
- DSI_TE_2048 = 0x03
- }dsi_te_timeout;
-
- typedef enum
- {
- DSI_ARB_MODE_FIXED = 0x0,
- DSI_ARB_MODE_ROUNDROBIN = 0x1
- }dsi_arb_mode;
-
- typedef struct
- {
- dsi_arb_mode arb_mode;
- dsi_interface arb_fixed_if;
- }dsi_arb_ctl;
-
- typedef enum
- {
- DSI_STARTON_VSYNC = 0x00,
- DSI_STARTON_VFP = 0x01,
- }dsi_start_mode;
-
- typedef enum
- {
- DSI_STOPBEFORE_VSYNV = 0x0,
- DSI_STOPAT_LINEEND = 0x1,
- DSI_STOPAT_ACTIVELINEEND = 0x2,
- }dsi_stop_mode;
-
- typedef enum
- {
- DSI_NO_BURST_MODE = 0x0,
- DSI_BURST_MODE = 0x1,
- }dsi_burst_mode;
-
- typedef enum
- {
- DSI_VID_MODE_16_PACKED = 0x0,
- DSI_VID_MODE_18_PACKED = 0x1,
- DSI_VID_MODE_16_LOOSELY = 0x2,
- DSI_VID_MODE_18_LOOSELY = 0x3
- }dsi_vid_pixel_mode;
-
- typedef enum
- {
- DSI_SYNC_PULSE_NOTACTIVE = 0x0,
- DSI_SYNC_PULSE_ACTIVE = 0x1
- }dsi_sync_pulse_active;
-
- typedef enum
- {
- DSI_SYNC_PULSE_HORIZONTAL_NOTACTIVE = 0x0,
- DSI_SYNC_PULSE_HORIZONTAL_ACTIVE = 0x1
- }dsi_sync_pulse_horizontal;
-
- typedef enum
- {
- DSI_NULL_PACKET = 0x0,
- DSI_BLANKING_PACKET = 0x1,
- DSI_LP_MODE = 0x2,
- }dsi_blanking_packet;
-
- typedef enum
- {
- DSI_RECOVERY_HSYNC = 0x0,
- DSI_RECOVERY_VSYNC = 0x1,
- DSI_RECOVERY_STOP = 0x2,
- DSI_RECOVERY_HSYNC_VSYNC = 0x3
- }dsi_recovery_mode;
-
- typedef struct
- {
- dsi_start_mode vid_start_mode;
- dsi_stop_mode vid_stop_mode;
- dsi_virtual_ch vid_id;
- u8 header;
- dsi_vid_pixel_mode vid_pixel_mode;
- dsi_burst_mode vid_burst_mode;
- dsi_sync_pulse_active sync_pulse_active;
- dsi_sync_pulse_horizontal sync_pulse_horizontal;
- dsi_blanking_packet blkline_mode;
- dsi_blanking_packet blkeol_mode;
- dsi_recovery_mode recovery_mode;
- }dsi_vid_main_ctl;
-
- typedef struct
- {
- u16 vact_length;
- u8 vfp_length;
- u8 vbp_length;
- u8 vsa_length;
- }dsi_img_vertical_size;
-
- typedef struct
- {
- u8 hsa_length;
- u8 hbp_length;
- u16 hfp_length;
- u16 rgb_size;
- }dsi_img_horizontal_size;
-
- typedef struct
- {
- u16 line_val;
- u8 line_pos;
- u16 horizontal_val;
- u8 horizontal_pos;
- }dsi_img_position;
-
- typedef enum
- {
- DSI_VSG_RUNNING = 0x1,
- DSI_ERR_MISSING_DATA = 0x2,
- DSI_ERR_MISSING_HSYNC = 0x4,
- DSI_ERR_MISSING_VSYNC = 0x8,
- DSI_ERR_SMALL_LENGTH = 0x10,
- DSI_ERR_SMALL_HEIGHT = 0x20,
- DSI_ERR_BURSTWRITE = 0x40,
- DSI_ERR_LINEWRITE = 0x80,
- DSI_ERR_LONGWRITE = 0x100,
- DSI_ERR_VRS_WRONG_LENGTH = 0x200
- }dsi_vid_mode_sts;
-
- typedef enum
- {
- DSI_NULL_PACK = 0x0,
- DSI_LP = 0x1,
- }dsi_burst_lp;
-
- typedef struct
- {
- dsi_burst_lp burst_lp;
- u16 max_burst_limit;
- u16 max_line_limit;
- u16 exact_burst_limit;
- }dsi_vca_setting;
-
- typedef struct
- {
- u16 blkeol_pck;
- u16 blkline_event_pck;
- u16 blkline_pulse_pck;
- u16 vert_balnking_duration;
- u16 blkeol_duration;
- }dsi_vid_blanking;
-
- typedef struct
- {
- u8 col_red;
- u8 col_green;
- u8 col_blue;
- u8 pad_val;
- }dsi_vid_err_color;
-
- typedef enum
- {
- DSI_TVG_MODE_UNIQUECOLOR = 0x0,
- DSI_TVG_MODE_STRIPES = 0x1,
- }dsi_tvg_mode;
-
- typedef enum
- {
- DSI_TVG_STOP_FRAMEEND = 0x0,
- DSI_TVG_STOP_LINEEND = 0x1,
- DSI_TVG_STOP_IMMEDIATE = 0x2,
- }dsi_tvg_stop_mode;
-
-
-
- typedef struct
- {
- u8 tvg_stripe_size;
- dsi_tvg_mode tvg_mode;
- dsi_tvg_stop_mode stop_mode;
- }dsi_tvg_control;
-
- typedef struct
- {
- u16 tvg_nbline;
- u16 tvg_line_size;
- }dsi_tvg_img_size;
-
- typedef struct
- {
- u8 col_red;
- u8 col_green;
- u8 col_blue;
- }dsi_frame_color;
-
- typedef enum
- {
- DSI_TVG_COLOR1 = 0x0,
- DSI_TVG_COLOR2 = 0x1
- }dsi_color_type;
-
- typedef enum
- {
- DSI_TVG_STOPPED = 0x0,
- DSI_TVG_RUNNING = 0x1
- }dsi_tvg_state;
-
- typedef enum
- {
- DSI_TVG_STOP = 0x0,
- DSI_TVG_START = 0x1
- }dsi_tvg_ctrl_state;
-
- typedef enum
- {
- DSI_TBG_STOPPED = 0x0,
- DSI_TBG_RUNNING = 0x1
- }dsi_tbg_state;
-
- typedef enum
- {
- DSI_SEND_1BYTE = 0x0,
- DSI_SEND_2BYTE = 0x1,
- DSI_SEND_BURST_STOP_COUNTER = 0x3,
- DSI_SEND_BURST_STOP = 0x4
- }dsi_tbg_mode;
-
- typedef enum
- {
- DSI_ERR_FIXED = 0x1,
- DSI_ERR_UNCORRECTABLE = 0x2,
- DSI_ERR_CHECKSUM = 0x4,
- DSI_ERR_UNDECODABLE = 0x8,
- DSI_ERR_RECEIVE = 0x10,
- DSI_ERR_OVERSIZE = 0x20,
- DSI_ERR_WRONG_LENGTH = 0x40,
- DSI_ERR_MISSING_EOT = 0x80,
- DSI_ERR_EOT_WITH_ERR = 0x100
- }dsi_direct_cmd_rd_sts_ctl;
-
- typedef enum
- {
- DSI_TVG_STS = 0x1,
- DSi_TBG_STS = 0x2
- }dsi_tg_sts_ctl;
-
-typedef struct
-{
- dsi_interface_mode dsi_if_mode;
- dsi_interface dsiInterface;
- dsi_if1_state dsi_if1_state;
- dsi_link_state dsi_link_state;
- dsi_int_mode dsi_int_mode;
- dsi_interface_mode_type if_mode_type;
-}dsi_link_context;
-
-struct dsi_dphy_static_conf {
- dsi_hs_invert_mode clocklanehsinvermode;
- dsi_swap_pin_mode clocklaneswappinmode;
- dsi_hs_invert_mode datalane1hsinvermode;
- dsi_swap_pin_mode datalane1swappinmode;
- dsi_hs_invert_mode datalane2hsinvermode;
- dsi_swap_pin_mode datalane2swappinmode;
- u8 ui_x4; /** unit interval time for clock lane*/
-};
-struct dsi_link_conf {
- dsi_link_state dsiLinkState;
- dsi_interface dsiInterface;
- dsi_interface_mode dsiInterfaceMode;
- dsi_interface_mode_type videoModeType; /** for LP/HS mode for vide mode */
- dsi_interface_mode_type commandModeType;/** for LP/HS mode for command mode */
- dsi_lane_mode clockLaneMode;
- dsi_lane_mode dataLane1Mode;
- dsi_lane_mode dataLane2Mode;
- dsi_arb_mode arbMode;
- dsi_te_ctrl if1TeCtrl;
- dsi_te_ctrl if2TeCtrl;
- dsi_te_ctrl regTeCtrl;
- dsi_bta_mode btaMode;
- dsi_rd_ctrl rdCtrl;
- dsi_host_eot_gen_mode hostEotGenMode;
- dsi_eot_gen_mode displayEotGenMode;
- dsi_ecc_gen_mode dispEccGenMode;
- dsi_checksum_gen_mode dispChecksumGenMode;
- dsi_clk_continious_hs_mode clockContiniousMode;
- u8 paddingValue;
-};
-#endif /** __KERNEL_ */
-
-u32 dsiconfdphy1(mcde_pll_ref_clk pll_sel, mcde_ch_id chid, dsi_link link);
-u32 dsidisplayinitLPcmdmode(mcde_ch_id chid, dsi_link link);
-
-dsi_error dsisetlinkstate(dsi_link link, dsi_link_state linkState, mcde_ch_id chid);
-u32 dsiLinkInit(struct dsi_link_conf *pdsiLinkConf, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid, dsi_link link);
-int mcde_dsi_test_LP_directcommand_mode(struct fb_info *info,u32 key);
-int mcde_dsi_start(struct fb_info *info);
-int mcde_dsi_test_dsi_HS_directcommand_mode(struct fb_info *info,u32 key);
-
-int mcde_dsi_read_reg(struct fb_info *info, u32 reg, u32 *value);
-int mcde_dsi_write_reg(struct fb_info *info, u32 reg, u32 value);
-
-dsi_error dsisetPLLcontrol(dsi_link link, mcde_ch_id chid, dsi_pll_ctl pll_ctl);
-dsi_error dsisetPLLmode(dsi_link link, mcde_ch_id chid, dsi_pll_mode mode);
-dsi_error dsigetlinkstatus(dsi_link link, mcde_ch_id chid, u8 *p_status);
-dsi_error dsisetInterface(dsi_link link, mcde_ch_id chid, dsi_if_state state, dsi_interface interface);
-dsi_error dsisetInterface1mode(dsi_link link, dsi_interface_mode mode, mcde_ch_id chid);
-dsi_error dsisetInterfaceInLpm(dsi_link link, mcde_ch_id chid, dsi_interface_mode_type modType, dsi_interface interface);
-dsi_error dsisetTEtimeout(dsi_link link, mcde_ch_id chid, u32 te_timeout);
-dsi_error dsireadset(dsi_link link, dsi_rd_ctrl state, mcde_ch_id chid);
-dsi_error dsisetBTAmode(dsi_link link, dsi_bta_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispEOTGenmode(dsi_link link, dsi_eot_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispHOSTEOTGenmode(dsi_link link, dsi_host_eot_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispCHKSUMGenmode(dsi_link link, dsi_checksum_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetdispECCGenmode(dsi_link link, dsi_ecc_gen_mode mode, mcde_ch_id chid);
-dsi_error dsisetCLKHSsendingmode(dsi_link link, dsi_clk_continious_hs_mode mode, mcde_ch_id chid);
-dsi_error dsisetpaddingval(dsi_link link, mcde_ch_id chid, u8 padding);
-dsi_error dsisetTE(dsi_link link, dsi_te_en tearing, dsi_te_ctrl state, mcde_ch_id chid);
-dsi_error dsisetlaneULPwaittime(dsi_link link, mcde_ch_id chid, dsi_lane lane, u16 timeout);
-
-dsi_error dsisetlanestate(dsi_link link, mcde_ch_id chid, dsi_lane_state mode, dsi_lane lane);
-dsi_error dsiset_hs_clock(dsi_link link, struct dsi_dphy_static_conf dphyStaticConf, mcde_ch_id chid);
-dsi_error dsisetDPHYtimeout(dsi_link link, mcde_ch_id chid, dsi_dphy_timeout timeout);
-void mcde_dsi_tpodisplay_init(struct fb_info *info);
-void mcde_dsi_taaldisplay_init(struct fb_info *info);
-
-/* following Apis are used by stw5810 driver for configuration */
-u32 dsisenddirectcommand(dsi_interface_mode_type mode_type, u32 cmd_head,u32 cmd_size,u32 cmd1,u32 cmd2,u32 cmd3,u32 cmd4, dsi_link link, mcde_ch_id chid);
-
-u32 dsiLPdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
- u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
- u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
-
-u32 dsiLPdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
-u32 dsiLPdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
-
-u32 dsiHSdcslongwrite(u32 VC_ID, u32 NoOfParam, u32 Param0, u32 Param1,u32 Param2, u32 Param3,
- u32 Param4,u32 Param5,u32 Param6,u32 Param7,u32 Param8, u32 Param9,u32 Param10,u32 Param11,
- u32 Param12,u32 Param13,u32 Param14, u32 Param15, mcde_ch_id chid, dsi_link link);
-
-u32 dsiHSdcsshortwrite1parm(u32 VC_ID, u32 Param0,u32 Param1, mcde_ch_id chid, dsi_link link);
-u32 dsiHSdcsshortwritenoparam(u32 VC_ID, u32 Param0, mcde_ch_id chid, dsi_link link);
-u32 dsireaddata(u8* byte0, u8* byte1, u8* byte2, u8* byte3, mcde_ch_id chid, dsi_link link);
-
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(_DSI_H_) */
-
-
diff --git a/arch/arm/mach-ux500/include/mach/dsi_reg.h b/arch/arm/mach-ux500/include/mach/dsi_reg.h
deleted file mode 100755
index a02691e5960..00000000000
--- a/arch/arm/mach-ux500/include/mach/dsi_reg.h
+++ /dev/null
@@ -1,488 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _DSIREG_H_
-#define _DSIREG_H_
-
-#ifdef _cplusplus
-extern "C" {
-#endif /* _cplusplus */
-
-#include <linux/types.h>
-
-#define DSI_SET_BIT 0x1
-#define DSI_CLEAR_BIT 0x0
-#define DSI_SET_ALL_BIT 0xFFFFFFFF
-#define DSI_CLEAR_ALL_BIT 0x0
-#define DSI_MCTL_INTMODE_MASK MASK_BIT0
-#define DSI_MCTL_LINKEN_MASK MASK_BIT0
-#define DSI_MCTL_INTERFACE1_MODE_MASK MASK_BIT1
-#define DSI_MCTL_VID_EN_MASK MASK_BIT2
-#define DSI_MCTL_TVG_SEL_MASK MASK_BIT3
-#define DSI_MCTL_TBG_SEL_MASK MASK_BIT4
-#define DSI_MCTL_READEN_MASK MASK_BIT8
-#define DSI_MCTL_BTAEN_MASK MASK_BIT9
-#define DSI_MCTL_DISPECCGEN_MASK MASK_BIT10
-#define DSI_MCTL_DISPCHECKSUMGEN_MASK MASK_BIT11
-#define DSI_MCTL_HOSTEOTGEN_MASK MASK_BIT12
-#define DSI_MCTL_DISPEOTGEN_MASK MASK_BIT13
-#define DSI_PLL_MASTER_MASK MASK_BIT16
-#define DSI_PLL_OUT_SEL_MASK MASK_BIT11
-#define DSI_PLL_IN_SEL_MASK MASK_BIT10
-#define DSI_PLL_DIV_MASK (MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define DSI_PLL_MULT_MASK (MASK_BYTE0 & 0x7F)
-#define DSI_REG_TE_MASK MASK_BIT7
-#define DSI_IF1_TE_MASK MASK_BIT5
-#define DSI_IF2_TE_MASK MASK_BIT6
-#define DSI_LANE2_EN_MASK MASK_BIT0
-#define DSI_FORCE_STOP_MODE_MASK MASK_BIT1
-#define DSI_CLK_CONTINUOUS_MASK MASK_BIT2
-#define DSI_CLK_ULPM_EN_MASK MASK_BIT3
-#define DSI_DAT1_ULPM_EN_MASK MASK_BIT4
-#define DSI_DAT2_ULPM_EN_MASK MASK_BIT5
-#define DSI_WAIT_BURST_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define DSI_CLKLANESTS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_DATALANE1STS_MASK (MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
-#define DSI_DATALANE2STS_MASK (MASK_BIT5 | MASK_BIT6)
-#define DSI_CLK_DIV_MASK MASK_QUARTET0
-#define DSI_HSTX_TO_MASK (MASK_QUARTET1 | MASK_BYTE1 | MASK_BIT16 | MASK_BIT17)
-#define DSI_LPRX_TO_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 | MASK_BIT18)
-#define DSI_CLK_ULPOUT_MASK (MASK_BYTE0 | MASK_BIT8)
-#define DSI_DATA_ULPOUT_MASK (MASK_QUARTET3 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11 | MASK_BIT16 | MASK_BIT17)
-#define DSI_PLL_START_MASK MASK_BIT0
-#define DSI_CKLANE_EN_MASK MASK_BIT3
-#define DSI_DAT1_EN_MASK MASK_BIT4
-#define DSI_DAT2_EN_MASK MASK_BIT5
-#define DSI_CLK_ULPM_MASK MASK_BIT6
-#define DSI_DAT1_ULPM_MASK MASK_BIT7
-#define DSI_DAT2_ULPM_MASK MASK_BIT8
-#define DSI_IF1_EN_MASK MASK_BIT9
-#define DSI_IF2_EN_MASK MASK_BIT10
-#define DSI_MAIN_STS_MASK MASK_BYTE0
-#define DSI_DPHY_ERROR_MASK MASK_HALFWORD0
-#define DSI_IF_DATA_MASK MASK_HALFWORD0
-#define DSI_IF_VALID_MASK MASK_BIT16
-#define DSI_IF_START_MASK MASK_BIT17
-#define DSI_IF_FRAME_SYNC_MASK MASK_BIT18
-#define DSI_IF_STALL_MASK MASK_BIT0
-#define DSI_INT_VAL_MASK MASK_BIT0
-#define DSI_DIRECT_CMD_RD_STS_MASK (MASK_BYTE0 | MASK_BIT8)
-#define DSI_CMD_MODE_STS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5)
-#define DSI_RD_ID_MASK (MASK_BIT16 | MASK_BIT17 )
-#define DSI_RD_DCSNOTGENERIC_MASK MASK_BIT18
-#define DSI_CMD_NAT_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2)
-#define DSI_CMD_LONGNOTSHORT_MASK MASK_BIT3
-#define DSI_CMD_HEAD_MASK (MASK_QUARTET2 | MASK_BIT12 | MASK_BIT13)
-#define DSI_CMD_ID_MASK (MASK_BIT14 | MASK_BIT15)
-#define DSI_CMD_SIZE_MASK (MASK_QUARTET4 | MASK_BIT20)
-#define DSI_CMD_LP_EN_MASK (MASK_BIT21)
-#define DSI_TRIGGER_VAL_MASK MASK_QUARTET6
-#define DSI_TE_LOWERBIT_MASK MASK_BYTE2
-#define DSI_TE_UPPERBIT_MASK (MASK_BIT24 | MASK_BIT25)
-#define DSI_FIL_VAL_MASK MASK_BYTE1
-#define DSI_ARB_MODE_MASK MASK_BIT6
-#define DSI_ARB_PRI_MASK MASK_BIT7
-#define DSI_START_MODE_MASK (MASK_BIT0 | MASK_BIT1 )
-#define DSI_STOP_MODE_MASK (MASK_BIT2 | MASK_BIT3)
-#define DSI_VID_ID_MASK (MASK_BIT4 | MASK_BIT5)
-#define DSI_HEADER_MASK (MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 | MASK_BIT11)
-#define DSI_PIXEL_MODE_MASK (MASK_BIT12 | MASK_BIT13)
-#define DSI_BURST_MODE_MASK (MASK_BIT14)
-#define DSI_SYNC_PULSE_ACTIVE_MASK (MASK_BIT15)
-#define DSI_SYNC_PULSE_HORIZONTAL_MASK (MASK_BIT16)
-#define DSI_BLKLINE_MASK (MASK_BIT17 | MASK_BIT18)
-#define DSI_BLKEOL_MASK (MASK_BIT19 | MASK_BIT20)
-#define DSI_RECOVERY_MODE_MASK (MASK_BIT21 | MASK_BIT22)
-#define DSI_VSA_LENGTH_MASK MASK_QUARTET0
-#define DSI_VBP_LENGTH_MASK MASK_QUARTET1
-#define DSI_VFP_LENGTH_MASK MASK_BYTE1
-#define DSI_VACT_LENGTH_MASK (MASK_BYTE2 | MASK_QUARTET6)
-#define DSI_HSA_LENGTH_MASK MASK_BYTE0
-#define DSI_HBP_LENGTH_MASK MASK_BYTE1
-#define DSI_HFP_LENGTH_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define DSI_RGB_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_LINE_POS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_LINE_VAL_MASK (MASK_BIT2 | MASK_BIT3 | MASK_QUARTET1 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_HORI_POS_MASK (MASK_BIT0 | MASK_BIT1 |MASK_BIT2)
-#define DSI_HORI_VAL_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)
-#define DSI_VID_MODE_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define DSI_BURST_LP_MASK MASK_BIT16
-#define DSI_MAX_BURST_LIMIT_MASK MASK_HALFWORD0
-#define DSI_MAX_LINE_LIMIT_MASK MASK_HALFWORD1
-#define DSI_EXACT_BURST_LIMIT_MASK MASK_HALFWORD0
-#define DSI_BLKLINE_EVENT_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_BLKEOL_PCK_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
-#define DSI_BLKLINE_PULSE_PCK_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_BLKEOL_DURATION_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_VERT_BLANK_DURATION_MASK (MASK_BYTE2 | MASK_BIT15 | MASK_BIT14 | MASK_BIT13 | MASK_BIT24 | MASK_BIT25)
-#define DSI_COL_RED_MASK MASK_BYTE0
-#define DSI_COL_GREEN_MASK MASK_BYTE1
-#define DSI_COL_BLUE_MASK MASK_BYTE2
-#define DSI_PAD_VAL_MASK MASK_BYTE3
-#define DSI_TVG_STRIPE_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7)
-#define DSI_TVG_MODE_MASK (MASK_BIT3 | MASK_BIT4 )
-#define DSI_TVG_STOPMODE_MASK (MASK_BIT1 | MASK_BIT2 )
-#define DSI_TVG_RUN_MASK MASK_BIT0
-#define DSI_TVG_NBLINE_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define DSI_TVG_LINE_SIZE_MASK (MASK_BYTE0 | MASK_QUARTET2 | MASK_BIT12)
-#define DSI_CMD_MODE_STATUS_MASK (MASK_QUARTET0 | MASK_BIT4 | MASK_BIT5 )
-#define DSI_DIRECT_CMD_STS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10 )
-#define DSI_DIRECT_CMD_RD_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 )
-#define DSI_VID_MODE_STATUS_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 )
-#define DSI_TG_STS_MASK (MASK_BIT0 | MASK_BIT1)
-#define DSI_CLK_TRIM_RD_MASK MASK_BIT0
-#define DSI_IF1_LPM_EN_MASK MASK_BIT4
-#define DSI_IF2_LPM_EN_MASK MASK_BIT5
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2 MASK_BIT5
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2 MASK_BIT4
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1 MASK_BIT3
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1 MASK_BIT2
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK MASK_BIT1
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK MASK_BIT0
-#define DSIMCTL_DPHY_STATIC_UI_X4 (MASK_BIT6 | MASK_BIT7 | MASK_QUARTET2)
-
-#define DSI_MCTL_INTERFACE1_MODE_SHIFT 1
-#define DSI_MCTL_VID_EN_SHIF 2
-#define DSI_MCTL_TVG_SEL_SHIFT 3
-#define DSI_MCTL_TBG_SEL_SHIFT 4
-#define DSI_MCTL_READEN_SHIFT 8
-#define DSI_MCTL_BTAEN_SHIFT 9
-#define DSI_MCTL_DISPECCGEN_SHIFT 10
-#define DSI_MCTL_DISPCHECKSUMGEN_SHIFT 11
-#define DSI_MCTL_HOSTEOTGEN_SHIFT 12
-#define DSI_MCTL_DISPEOTGEN_SHIFT 13
-#define DSI_PLL_MASTER_SHIFT 16
-#define DSI_PLL_OUT_SEL_SHIFT 11
-#define DSI_PLL_IN_SEL_SHIFT 10
-#define DSI_MCTL_VID_EN_SHIFT 2
-#define DSI_PLL_DIV_SHIFT 7
-#define DSI_REG_TE_SHIFT 7
-#define DSI_IF1_TE_SHIFT 5
-#define DSI_IF2_TE_SHIFT 6
-#define DSI_FORCE_STOP_MODE_SHIFT 1
-#define DSI_CLK_CONTINUOUS_SHIFT 2
-#define DSI_CLK_ULPM_EN_SHIFT 3
-#define DSI_DAT1_ULPM_EN_SHIFT 4
-#define DSI_DAT2_ULPM_EN_SHIFT 5
-#define DSI_WAIT_BURST_SHIFT 6
-#define DSI_DATALANE1STS_SHIFT 2
-#define DSI_DATALANE2STS_SHIFT 5
-#define DSI_HSTX_TO_SHIFT 4
-#define DSI_LPRX_TO_SHIFT 18
-#define DSI_DATA_ULPOUT_SHIFT 9
-#define DSI_CKLANE_EN_SHIFT 3
-#define DSI_DAT1_EN_SHIFT 4
-#define DSI_DAT2_EN_SHIFT 5
-#define DSI_CLK_ULPM_SHIFT 6
-#define DSI_DAT1_ULPM_SHIFT 7
-#define DSI_DAT2_ULPM_SHIFT 8
-#define DSI_IF1_EN_SHIFT 9
-#define DSI_IF2_EN_SHIFT 10
-#define DSI_IF_VALID_SHIFT 16
-#define DSI_IF_START_SHIFT 17
-#define DSI_IF_FRAME_SYNC_SHIFT 18
-#define DSI_RD_ID_SHIFT 16
-#define DSI_RD_DCSNOTGENERIC_SHIFT 18
-#define DSI_CMD_LONGNOTSHORT_SHIFT 3
-#define DSI_CMD_HEAD_SHIFT 8
-#define DSI_CMD_ID_SHIFT 14
-#define DSI_CMD_SIZE_SHIFT 16
-#define DSI_CMD_LP_EN_SHIFT 21
-#define DSI_TRIGGER_VAL_SHIFT 24
-#define DSI_TE_LOWERBIT_SHIFT 16
-#define DSI_TE_UPPERBIT_SHIFT 24
-#define DSI_FIL_VAL_SHIFT 8
-#define DSI_ARB_MODE_SHIFT 6
-#define DSI_ARB_PRI_SHIFT 7
-#define DSI_STOP_MODE_SHIFT 2
-#define DSI_VID_ID_SHIFT 4
-#define DSI_HEADER_SHIFT 6
-#define DSI_PIXEL_MODE_SHIFT 12
-#define DSI_BURST_MODE_SHIFT 14
-#define DSI_SYNC_PULSE_ACTIVE_SHIFT 15
-#define DSI_SYNC_PULSE_HORIZONTAL_SHIFT 16
-#define DSI_BLKLINE_SHIFT 17
-#define DSI_BLKEOL_SHIFT 19
-#define DSI_RECOVERY_MODE_SHIFT 21
-#define DSI_VBP_LENGTH_SHIFT 4
-#define DSI_VFP_LENGTH_SHIFT 8
-#define DSI_VACT_LENGTH_SHIFT 16
-#define DSI_HBP_LENGTH_SHIFT 8
-#define DSI_HFP_LENGTH_SHIFT 16
-#define DSI_LINE_VAL_SHIFT 2
-#define DSI_HORI_VAL_SHIFT 3
-#define DSI_BURST_LP_SHIFT 16
-#define DSI_MAX_LINE_LIMIT_SHIFT 16
-#define DSI_BLKEOL_PCK_SHIFT 13
-#define DSI_VERT_BLANK_DURATION_SHIFT 13
-#define DSI_COL_GREEN_SHIFT 8
-#define DSI_COL_BLUE_SHIFT 16
-#define DSI_PAD_VAL_SHIFT 24
-#define DSI_TVG_STRIPE_SHIFT 1
-#define DSI_TVG_MODE_SHIFT 3
-#define DSI_TVG_STOPMODE_SHIFT 5
-#define DSI_TVG_NBLINE_SHIFT 16
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_CLK_SHIFT 0
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_CLK_SHIFT 1
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT1_SHIFT 2
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT1_SHIFT 3
-#define DSIMCTL_DPHY_STATIC_SWAP_PINS_DAT2_SHIFT 4
-#define DSIMCTL_DPHY_STATIC_HS_INVERT_DAT2_SHIFT 5
-#define DSIMCTL_DPHY_STATIC_UI_X4_SHIFT 6
-#define DSI_IF1_LPM_EN_MASK_SHIFT 4
-#define DSI_IF2_LPM_EN_MASK_SHIFT 5
-
-#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK 0x80
-#define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK_SHIFT 7
-
-#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK 0x40
-#define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK_SHIFT 6
-
-#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR 0x20
-#define DSI_MCTL_MAIN_STS_LPRX_TO_ERR_SHIFT 5
-
-#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR 0x10
-#define DSI_MCTL_MAIN_STS_HSTX_TO_ERR_SHIFT 4
-
-#define DSI_MCTL_MAIN_STS_DAT2_READY 0x8
-#define DSI_MCTL_MAIN_STS_DAT2_READY_SHIFT 3
-
-#define DSI_MCTL_MAIN_STS_DAT1_READY 0x4
-#define DSI_MCTL_MAIN_STS_DAT1_READY_SHIFT 2
-
-#define DSI_MCTL_MAIN_STS_CLKLANE_READY 0x2
-#define DSI_MCTL_MAIN_STS_CLKLANE_READY_SHIFT 1
-
-#define DSI_MCTL_MAIN_STS_PLL_LOCK 0x1
-#define DSI_MCTL_MAIN_STS_PLL_LOCK_SHIFT 0
-/** Test mode conf */
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT0 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT0_WRDAT3 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT3 (24)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT2 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT2 (16)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT1 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT1 (8)
-#define DSIDIRECT_CMD_WRDAT0_WRDAT0 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT0_WRDAT0 (0)
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT1 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT1_WRDAT7 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT7 (24)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT6 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT6 (16)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT5 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT5 (8)
-#define DSIDIRECT_CMD_WRDAT1_WRDAT4 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT1_WRDAT4 (0)
-
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT2 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT2_WRDAT11 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT11 (24)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT10 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT10 (16)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT9 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT9 (8)
-#define DSIDIRECT_CMD_WRDAT2_WRDAT8 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT2_WRDAT8 (0)
-
-//**********************************************************************************************************************
-/** - DIRECT_CMD_WRDAT3 */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_WRDAT3_WRDAT15 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT15 (24)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT14 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT14 (16)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT13 (0xFF00)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT13 (8)
-#define DSIDIRECT_CMD_WRDAT3_WRDAT12 (0xFF)
-#define Shift_DSIDIRECT_CMD_WRDAT3_WRDAT12 (0)
-//**********************************************************************************************************************
-/** - DIRECT_CMD_READ */
-//**********************************************************************************************************************
-
-#define DSIDIRECT_CMD_RDAT3 (0xFF000000)
-#define Shift_DSIDIRECT_CMD_RDAT3 (24)
-#define DSIDIRECT_CMD_RDAT2 (0xFF0000)
-#define Shift_DSIDIRECT_CMD_RDAT2 (16)
-#define DSIDIRECT_CMD_RDAT1 (0xFF00)
-#define Shift_DSIDIRECT_CMD_RDAT1 (8)
-#define DSIDIRECT_CMD_RDAT0 (0xFF)
-#define Shift_DSIDIRECT_CMD_RDAT0 (0)
-
-/** TPO COMMAND HEADER */
-#define TPO_CMD_NONE 0x00
-#define TPO_CMD_SWRESET 0x01 /** SWRESET: Software Reset (01h) */
-#define TPO_CMD_SLPOUT 0x11 /** SLPOUT: Sleep Out (11h) */
-#define TPO_CMD_NORON 0x13 /** NORON: Normal Display Mode On (13h) */
-#define TPO_CMD_INVOFF 0x20 /** INVOFF: Display Inversion Off (20h) */
-#define TPO_CMD_INVON 0x21 /** INVOFF: Display Inversion Off (20h) */
-#define TPO_CMD_GAMMA_SET 0x26 /** Gamma set//reset GC0G2.2 */
-
-#define TPO_CMD_DISPOFF 0x28 /** DISPON: Display On (29h) */
-#define TPO_CMD_DISPON 0x29 /** DISPON: Display On (29h) */
-#define TPO_CMD_CASET 0x2A /** CASET :Columen address select */
-#define TPO_CMD_RASET 0x2B /** RASET :Row address select */
-#define TPO_CMD_RAMWR 0x2C /** RAMWR ram write */
-
-#define TPO_CMD_MADCTR 0x36 /** MADCTR: Memory Data Access Control (36h) */
-#define TPO_CMD_IDMOFF 0x38 /** IDMON: Idle Mode On (39h) */
-#define TPO_CMD_IDMON 0x39 /** IDMON: Idle Mode On (39h) */
-#define TPO_CMD_COLMOD 0x3A /** COLMOD: Interface Pixel Format (3Ah). */
-#define TPO_CMD_RAMWR_CONTINUE 0x3C /** Ram write continue */
-#define TPO_CMD_IFMODE 0xB0 /** IFMODE: Set Display Interface Mode (B0h) */
-#define TPO_CMD_DISSET6 0xB7 /** Display Function Setting 6 (B7h) */
-#define TPO_CMD_LPTS_FUNCTION_SET3 0xBC /** LPTS_FUNCTION_SET3 (0xBC) */
-#define TPO_CMD_DSLPOUT 0xCA /** deep sleepout 0xca */
-
-
-#define TPO_CMD_GAMCTRP1 0xE0 /** GAMCTRP1: Set Positive Gamma Correction Characteristics (E0h) */
-#define TPO_CMD_GAMCTRN1 0xE1 /** GAMCTRN1: Set Negative Gamma Correction Characteristics (E1h) */
-#define TPO_CMD_GAMCTRP2 0xE2 /** GAMCTRP2: Gamma (‘+’polarity) Correction Characteristics Setting (E2h) */
-#define TPO_CMD_GAMCTRN2 0xE3 /** GAMCTRN2: Gamma (‘-’polarity) Correction Characteristics Setting (E3h) */
-#define TPO_CMD_GAMCTRP3 0xE4 /** GAMCTRP3: Gamma (‘+’polarity) Correction Characteristics Setting (E4h) */
-#define TPO_CMD_GAMCTRN3 0xE5 /** GAMCTRN3: Gamma (‘-’polarity) Correction Characteristics Setting (E5h) */
-#define TPO_CMD_GAM_R_SEL 0xEA /** GAMMA SELECTION */
-
-
-
-#define VC_ID0 0
-#define VC_ID1 1
-
-
-
-
-struct dsi_link_registers
-{
- /** Main control registers */
- volatile u32 mctl_integration_mode;
- volatile u32 mctl_main_data_ctl;
- volatile u32 mctl_main_phy_ctl;
- volatile u32 mctl_pll_ctl;
- volatile u32 mctl_lane_sts;
- volatile u32 mctl_dphy_timeout;
- volatile u32 mctl_ulpout_time;
- volatile u32 mctl_dphy_static;
- volatile u32 mctl_main_en;
- volatile u32 mctl_main_sts;
- volatile u32 mctl_dphy_err;
-
- volatile u32 reserved1;
- /**
- integration mode registers */
- volatile u32 int_vid_rddata;
- volatile u32 int_vid_gnt;
- volatile u32 int_cmd_rddata;
- volatile u32 int_cmd_gnt;
- volatile u32 int_interrupt_ctl;
- volatile u32 reserved2[3];
- /**
- Command mode registers */
- volatile u32 cmd_mode_ctl;
- volatile u32 cmd_mode_sts;
- volatile u32 reserved3[2];
- /**
- Direct Command registers */
- volatile u32 direct_cmd_send;
- volatile u32 direct_cmd_main_settings;
- volatile u32 direct_cmd_sts;
- volatile u32 direct_cmd_rd_init;
- volatile u32 direct_cmd_wrdat0;
- volatile u32 direct_cmd_wrdat1;
- volatile u32 direct_cmd_wrdat2;
- volatile u32 direct_cmd_wrdat3;
- volatile u32 direct_cmd_rddat;
- volatile u32 direct_cmd_rd_property;
- volatile u32 direct_cmd_rd_sts;
- volatile u32 reserved4;
- /**
- Video mode registers */
- volatile u32 vid_main_ctl;
- volatile u32 vid_vsize;
- volatile u32 vid_hsize1;
- volatile u32 vid_hsize2;
- volatile u32 vid_blksize1;
- volatile u32 vid_blksize2;
- volatile u32 vid_pck_time;
- volatile u32 vid_dphy_time;
- volatile u32 vid_err_color;
- volatile u32 vid_vpos;
- volatile u32 vid_hpos;
- volatile u32 vid_mode_sts;
- volatile u32 vid_vca_setting1;
- volatile u32 vid_vca_setting2;
- /**
- Test Video Mode regsiter */
- volatile u32 tvg_ctl;
- volatile u32 tvg_img_size;
- volatile u32 tvg_color1;
- volatile u32 tvg_color2;
- volatile u32 tvg_sts;
- volatile u32 reserved5;
- /**
- Test Byte generator register */
- volatile u32 tbg_ctl;
- volatile u32 tbg_setting;
- volatile u32 tbg_sts;
- volatile u32 reserved6;
- /**
- Interrupt Enable and Edge detection register */
- volatile u32 mctl_main_sts_ctl;
- volatile u32 cmd_mode_sts_ctl;
- volatile u32 direct_cmd_sts_ctl;
- volatile u32 direct_cmd_rd_sts_ctl;
- volatile u32 vid_mode_sts_ctl;
- volatile u32 tg_sts_ctl;
- volatile u32 mctl_dphy_err_ctl;
- volatile u32 dphy_clk_trim_rd_ctl;
- /**
- Error/Interrupt Clear Register */
- volatile u32 mctl_main_sts_clr;
- volatile u32 cmd_mode_sts_clr;
- volatile u32 direct_cmd_sts_clr;
- volatile u32 direct_cmd_rd_sts_clr;
- volatile u32 vid_mode_sts_clr;
- volatile u32 tg_sts_clr;
- volatile u32 mctl_dphy_err_clr;
- volatile u32 dphy_clk_trim_rd_clr;
- /**
- Flag registers */
- volatile u32 mctl_main_sts_flag;
- volatile u32 cmd_mode_sts_flag;
- volatile u32 direct_cmd_sts_flag;
- volatile u32 direct_cmd_rd_sts_flag;
- volatile u32 vid_mode_sts_flag;
- volatile u32 tg_sts_flag;
- volatile u32 mctl_dphy_err_flag;
- volatile u32 dphy_clk_trim_rd_flag;
- volatile u32 dhy_lanes_trim;
-};
-
-
-
-#ifdef _cplusplus
-}
-#endif /* _cplusplus */
-
-#endif /* !defined(_DSI_H_) */
-
-
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 2cd5a48d02a..a0adb5402ce 100755
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -164,7 +164,11 @@
/* B2R2 clock management register */
#define PRCM_B2R2CLK_MGT_REG 0x80157078 /** B2R2 clock selection */
-#include <mach/mcde-base.h>
+#define U8500_DSI_LINK1_BASE 0xA0351000
+#define U8500_DSI_LINK_SIZE 0x1000
+#define U8500_DSI_LINK_COUNT 0x3
+#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mach-ux500/include/mach/mcde-base.h b/arch/arm/mach-ux500/include/mach/mcde-base.h
deleted file mode 100644
index c785fcac2de..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde-base.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2010 ST-Ericsson
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-/* MCDE specific declaration */
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-#define U8500_MCDE_REGISTER_BANK_SIZE 0x20
-#define U8500_MCDE_BASE_SIZE 0x200
-
-#define U8500_MCDE_EXTSRC_BASE (U8500_MCDE_BASE + U8500_MCDE_BASE_SIZE)
-#define U8500_MCDE_EXTSRC_SIZE (U8500_MCDE_REGISTER_BANK_SIZE * 0x10)
-
-#define U8500_MCDE_OVERLAY_BASE (U8500_MCDE_BASE + 0x400)
-#define U8500_MCDE_OVERLAY_SIZE (0x20 * 0x10)
-
-#define U8500_MCDE_CHANNELA_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELB_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELC0_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNELC1_CONFIG_BASE (U8500_MCDE_BASE + 0x600) /* MCDE channel config registers */
-#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
-
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0x800) /* MCDE channel A specific registers */
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE 0x200
-
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xA00) /* MCDE channel B specific registers */
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE 0x200
-
-#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE (U8500_MCDE_BASE + 0xC00) /* MCDE channel C0/C1 speicific registers */
-#define U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE 0xCB
-
-#define U8500_MCDE_DSI_CHANNEL_BASE (U8500_MCDE_BASE + 0xE00) /* MCDE channelC0 config registers */
-#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
-#define U8500_MCDE_DSI_SIZE 0xF4
-#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
-#define U8500_DSI_LINK1_BASE 0xA0351000
-#define U8500_DSI_LINK_SIZE 0x1000
-#define U8500_DSI_LINK_COUNT 0x3
-#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
-#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
-
-#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
-#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
-#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#define U8500_MCDE_REGISTER_SIZE 0x20
-#define U8500_MCDE_EXTSRC_BASE 0xA0350200
-#define U8500_MCDE_EXTSRC_SIZE (0x20 * 0x10)
-#define U8500_MCDE_OVL_BASE 0xA0350400
-#define U8500_MCDE_OVL_SIZE (0x20 * 0x10)
-#define U8500_MCDE_CHANNELA_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
-#define U8500_MCDE_CHANNEL_CONFIG_SIZE (0x20 * 0x10)
-#define U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE 0xA0350800 /* MCDE channelA specific registers */
-#define U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE 0x80
-#define U8500_MCDE_CHANNELB_CONFIG_BASE 0xA0350600 /* MCDE channelA config registers */
-#define U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE 0xA0350A00 /* MCDE channelA specific registers */
-#define U8500_MCDE_CHANNELC0_CONFIG_BASE 0xA0350600 /* MCDE channelC0 config registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
-#define U8500_MCDE_CHANNELC1_CONFIG_BASE 0xA0350600 /* MCDE channelC1 config registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE 0xA0350C00 /* MCDE channelC specific registers */
-#define U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE 0xA8
-#define U8500_MCDE_DSI_CHANNEL_BASE 0xA0350E00 /* MCDE channelC0 config registers */
-#define U8500_MCDE_DSI_CHANNEL_SIZE 0x20
-#define U8500_MCDE_DSI_SIZE 0xF4
-#define U8500_MCDE_DSI_CLOCK_OFFSET 0xF0 /* MCDE DSI clock */
-#define U8500_DSI_LINK1_BASE 0xA0351000
-#define U8500_DSI_LINK_SIZE 0x1000
-#define U8500_DSI_LINK_COUNT 0x3
-#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
-#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
-
-#define PRCM_HDMICLK_MGT_REG 0x80157058 /** HDMI clock selection */
-#define PRCM_MCDECLK_MGT_REG 0x80157064 /** MCDE clock selection */
-#define PRCM_TVCLK_MGT_REG 0x8015707c /** MCDE clock selection */
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde.h b/arch/arm/mach-ux500/include/mach/mcde.h
deleted file mode 100755
index 20437af76b9..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde.h
+++ /dev/null
@@ -1,1387 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_H_
-#define _MCDE_H_
-#include <linux/gpio.h>
-#include <linux/fb.h>
-#include <mach/mcde_ioctls.h>
-
-#ifdef __KERNEL__
-
-/*******************************************************************************
- MCDE Control Enums and structures
- ******************************************************************************/
-/* typedef enum
-{
- MCDE_CH_A_LSB = 0x00,
- MCDE_CH_A_MID = 0x01,
- MCDE_CH_A_MSB = 0x02,
- MCDE_CH_B_LSB = 0x03,
- MCDE_CH_B_MID = 0x04,
- MCDE_CH_B_MSB = 0x05,
- MCDE_CH_C_LSB = 0x06
-}mcde_out_mux_cfg;
-
-typedef enum
-{
- MCDE_CH_NORMAL_MODE = 0x0,
- MCDE_CH_MUX_MODE = 0x1
-}mcde_ch_ctrl;
-*/
- typedef enum
- {
- MCDE_CH_FIFO_A_ENABLE = 0x0,
- MCDE_CH_FIFO_B_ENABLE = 0x1
- }mcde_ch_fifo_ab_mux_ctrl;
-
- typedef enum
- {
- MCDE_CH_FIFO_0_ENABLE = 0x0,
- MCDE_CH_FIFO_1_ENABLE = 0x1
- }mcde_ch_fifo_01_mux_ctrl;
-
- typedef enum
- {
- MCDE_INPUT_FIFO_DISABLE = 0x0,
- MCDE_INPUT_FIFO_ENABLE = 0x1
- }mcde_input_fifo_ctrl;
-
- typedef enum
- {
- MCDE_DPI_DISABLE = 0x0,
- MCDE_DPI_ENABLE = 0x1
- }mcde_dpi_ctrl;
-
- typedef enum
- {
- MCDE_DBI_DISABLE = 0x0,
- MCDE_DBI_ENABLE = 0x1
- }mcde_dbi_ctrl;
-
- typedef enum
- {
- MCDE_DSIVID_DISABLE = 0x0,
- MCDE_DSIVID_ENABLE = 0x1
- }mcde_dsivid_ctrl;
-
- typedef enum
- {
- MCDE_DSICMD_DISABLE = 0x0,
- MCDE_DSICMD_ENABLE = 0x1
- }mcde_dsicmd_ctrl;
-
- typedef enum
- {
- MCDE_WTRMRK_LEVEL_0,
- MCDE_WTRMRK_LEVEL_1,
- MCDE_WTRMRK_LEVEL_2,
- MCDE_WTRMRK_LEVEL_3,
- MCDE_WTRMRK_LEVEL_4,
- MCDE_WTRMRK_LEVEL_5,
- MCDE_WTRMRK_LEVEL_6,
- MCDE_WTRMRK_LEVEL_7
- }mcde_fifo_wrtmrk_level;
- typedef enum
- {
- MCDE_CH_AB_FRAMESYNC_DPI = 0x0,
- MCDE_CH_AB_FRAMESYNC_DBI = 0x1
- }mcde_ch_ab_framesync_cfg;
-
-typedef enum
-{
- MCDE_DISABLE = 0x0,
- MCDE_ENABLE = 0x1
-}mcde_state;
-
-typedef enum
-{
- MCDE_CH_A_OUTPUT_FIFO_B = 0x0,
- MCDE_CH_A_OUTPUT_FIFO_C1 = 0x1
- }mcde_fifo_sel_bc1_cfg;
-
- typedef enum
- {
- MCDE_CH_A_OUTPUT_FIFO_A = 0x0,
- MCDE_CH_A_OUTPUT_FIFO_C0 = 0x1
- }mcde_fifo_sel_ac0_cfg;
-
- typedef enum
- {
- MCDE_CH_B_PULSE_PANEL7 = 0x0,
- MCDE_CH_C0C1_PULSE_PANEL = 0x1
- }mcde_sync_mux7_cfg;
-
- typedef enum
- {
- MCDE_CH_A_PULSE_PANEL = 0x0,
- MCDE_CH_B_PULSE_PANEL6 = 0x1
- }mcde_sync_mux6_cfg;
-
- typedef enum
- {
- MCDE_CH_B_CLK_PANEL5 = 0x0,
- MCDE_CH_C_CHIP_SELECT5 = 0x1
- }mcde_sync_mux5_cfg;
-
- typedef enum
- {
- MCDE_CH_A_CLK_PANEL4 = 0x0,
- MCDE_CH_B_CLK_PANEL4 = 0x1
- }mcde_sync_mux4_cfg;
-/*
-typedef enum
-{
- MCDE_CHIPSELECT_C0 = 0x0,
- MCDE_CHIPSELECT_C1 = 0x1
-}mcde_sync_mux23_cfg;
-
-typedef enum
-{
- MCDE_CH_A_OUT_ENABLE = 0x0,
- MCDE_CH_C_OUT_ENABLE = 0x1
-}mcde_sync_mux1_cfg;
-*/
- typedef enum
- {
- MCDE_CH_A_CLK_PANEL0 = 0x0,
- MCDE_CH_C_CHIP_SELECT0 = 0x1
- }mcde_sync_mux0_cfg;
-/*
-struct mcde_config
-{
- mcde_out_mux_cfg data_msb1;
- mcde_out_mux_cfg data_msb0;
- mcde_out_mux_cfg data_mid;
- mcde_out_mux_cfg data_lsb1;
- mcde_out_mux_cfg data_lsb0;
- mcde_fifo_wrtmrk_level fifo_wtrmrk_level;
- mcde_ch_ab_framesync_cfg ch_b_frame_sync_ctrl;
- mcde_ch_ab_framesync_cfg ch_a_frame_sync_ctrl;
- mcde_fifo_sel_bc1_cfg ch_b_fifo_sel;
- mcde_fifo_sel_ac0_cfg ch_a_fifo_sel;
- mcde_sync_mux7_cfg panel_mcdeblp;
- mcde_sync_mux6_cfg panel_mcdeealp;
- mcde_sync_mux4_cfg panel_mcdebcp;
- mcde_sync_mux4_cfg panel_mcdeacp4;
- mcde_sync_mux23_cfg panel_mcdeaspl;
- mcde_sync_mux23_cfg panel_mcdeaps;
- mcde_sync_mux1_cfg panel_mcdealp;
- mcde_sync_mux0_cfg panel_mcdeacp;
-};*/
- struct mcde_control
- {
- mcde_ch_fifo_ab_mux_ctrl ch_fifo_ab_mux;
- mcde_ch_fifo_01_mux_ctrl ch_fifo_01_mux;
- mcde_input_fifo_ctrl input_fifo_enable;
- mcde_dpi_ctrl dpi_a_enable;
- mcde_dpi_ctrl dpi_b_enable;
- mcde_dbi_ctrl dbi_c0_enable;
- mcde_dbi_ctrl dbi_c1_enable;
- mcde_dsivid_ctrl dsi_vid0_enable;
- mcde_dsivid_ctrl dsi_vid1_enable;
- mcde_dsivid_ctrl dsi_vid2_enable;
- mcde_dsicmd_ctrl dsi_cmd0_enable;
- mcde_dsicmd_ctrl dsi_cmd1_enable;
- mcde_dsicmd_ctrl dsi_cmd2_enable;
- };
-/*
-struct mcde_ch_mode_ctrl
-{
- mcde_ch_ctrl sync_ctrl_chA;
- mcde_ch_ctrl sync_ctrl_chB;
- mcde_ch_ctrl flow_ctrl_chA;
- mcde_ch_ctrl flow_ctrl_chB;
-};
-*/
- struct mcde_irq_status
- {
- u32 irq_status;
- u32 event_status;
- u8 is_new;
- } ;
-/*
-typedef enum
-{
- MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
- MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
- MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
- MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
- MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
-} mcde_event_id;
-*/
-/* Check *********************************/
-
-typedef enum
-{
- MCDE_CH_A_LSB = 0x00,
- MCDE_CH_A_MID = 0x01,
- MCDE_CH_A_MSB = 0x02,
- MCDE_CH_B_LSB = 0x03,
- MCDE_CH_B_MID = 0x04,
- MCDE_CH_B_MSB = 0x05,
- MCDE_CH_C_LSB = 0x06
-}mcde_out_mux_ctrl;
-
-typedef enum
-{
- MCDE_FIFO_FA = 0x0,
- MCDE_FIFO_FB = 0x1,
- MCDE_FIFO_F0 = 0x2,
- MCDE_FIFO_F1 = 0x3
-}mcde_fifo;
-
-typedef enum
-{
- MCDE_DPI_A = 0x0,
- MCDE_DPI_B = 0x1,
- MCDE_DBI_C0 = 0x2,
- MCDE_DBI_C1 = 0x3,
- MCDE_DSI_VID0 = 0x4,
- MCDE_DSI_VID1 = 0x5,
- MCDE_DSI_VID2 = 0x6,
- MCDE_DSI_CMD0 = 0x7,
- MCDE_DSI_CMD1 = 0x8,
- MCDE_DSI_CMD2 = 0x9
-}mcde_fifo_output;
-
-struct mcde_fifo_ctrl
-{
- mcde_fifo_output out_fifoa;
- mcde_fifo_output out_fifob;
- mcde_fifo_output out_fifo0;
- mcde_fifo_output out_fifo1;
-};
-
-typedef enum
-{
- MCDE_CH_NORMAL_MODE = 0x0,
- MCDE_CH_MUX_MODE = 0x1
-}mcde_ch_ctrl;
-
-typedef enum
-{
- MCDE_CHIPSELECT_C0 = 0x0,
- MCDE_CHIPSELECT_C1 = 0x1
-}mcde_sync_mux_ctrl;
-
-typedef enum
-{
- MCDE_CH_A_OUT_ENABLE = 0x0,
- MCDE_CH_C_OUT_ENABLE = 0x1
-}mcde_sync_mux1_ctrl;
-
-typedef enum
-{
- MCDE_CH_A_CLK_PANEL = 0x0,
- MCDE_CH_C_CHIP_SELECT = 0x1
-}mcde_sync_mux0_ctrl;
-
-typedef enum
-{
- MCDE_CDI_CH_A = 0x0,
- MCDE_CDI_CH_B = 0x1
-}mcde_cdi_ctrl;
-
-typedef enum
-{
- MCDE_CDI_DISABLE = 0x0,
- MCDE_CDI_ENABLE = 0x1
-}mcde_cdi;
-/*
-typedef enum
-{
- MCDE_DISABLE = 0x0,
- MCDE_ENABLE = 0x1
-}mcde_state;
-
-typedef struct
-{
- t_mcde_out_mux_ctrl data_msb1;
- t_mcde_out_mux_ctrl data_msb0;
- t_mcde_out_mux_ctrl data_mid;
- t_mcde_out_mux_ctrl data_lsb1;
- t_mcde_out_mux_ctrl data_lsb0;
- u8 ififo_watermark;
-}mcde_control;
-*/
-typedef enum
-{
- MCDE_OUTPUT_FIFO_B = 0x0,
- MCDE_OUTPUT_FIFO_C1 = 0x1
-}mcde_swap_b_c1_ctrl;
-
-typedef enum
-{
- MCDE_CONF_TVA_DPIC0_LCDB = 0x0,
- MCDE_CONF_TVB_DPIC1_LCDA = 0x1,
- MCDE_CONF_DPIC1_LCDA = 0x2,
- MCDE_CONF_DPIC0_LCDB = 0x3,
- MCDE_CONF_LCDA_LCDB = 0x4,
- MCDE_CONF_DSI = 0x5
-}mcde_output_conf;
-
-typedef enum
-{
- MCDE_OUTPUT_FIFO_A = 0x0,
- MCDE_OUTPUT_FIFO_C0 = 0x1
-}mcde_swap_a_c0_ctrl;
-
-/*
-typedef struct
-{
- u32 irq_status;
- u32 event_status;
- t_bool is_new;
-}mcde_irq_status;
-*/
- typedef enum
- {
- MCDE_EVENT_MASTER_BUS_ERROR = 0x01,
- MCDE_EVENT_END_OF_FRAME_TRANSFER = 0x02,
- MCDE_EVENT_SYNCHRO_CAPTURE_TRIGGER = 0x04,
- MCDE_EVENT_HORIZONTAL_SYNCHRO_CAPTURE = 0x08,
- MCDE_EVENT_VERTICAL_SYNCHRO_CAPTURE = 0x10
- } mcde_event_id;
-
-typedef struct
-{
- u8 pllfreq_div;
- u8 datachannels_num;
- u8 delay_clk;
- u8 delay_d2;
- u8 delay_d1;
- u8 delay_d0;
-}mcde_cdi_delay;
-/*******************************************************************************
- External Source Enums and Structures
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_EXT_SRC_0 = 0x0,
- MCDE_EXT_SRC_1 = 0x1,
- MCDE_EXT_SRC_2 = 0x2,
- MCDE_EXT_SRC_3 = 0x3,
- MCDE_EXT_SRC_4 = 0x4,
- MCDE_EXT_SRC_5 = 0x5,
- MCDE_EXT_SRC_6 = 0x6,
- MCDE_EXT_SRC_7 = 0x7,
- MCDE_EXT_SRC_8 = 0x8,
- MCDE_EXT_SRC_9 = 0x9,
- MCDE_EXT_SRC_10 = 0xA,
- MCDE_EXT_SRC_11 = 0xB,
- MCDE_EXT_SRC_12 = 0xC,
- MCDE_EXT_SRC_13 = 0xD,
- MCDE_EXT_SRC_14 = 0xE,
- MCDE_EXT_SRC_15 = 0xF
- }mcde_ext_src;
-
-
- typedef enum
- {
- MCDE_U8500_PANEL_1BPP=1,
- MCDE_U8500_PANEL_2BPP=2,
- MCDE_U8500_PANEL_4BPP=4,
- MCDE_U8500_PANEL_8BPP=8,
- MCDE_U8500_PANEL_16BPP=16,
- MCDE_U8500_PANEL_24BPP_PACKED=24,
- MCDE_U8500_PANEL_24BPP=25,
- MCDE_U8500_PANEL_32BPP=32,
- MCDE_U8500_PANEL_YCBCR=11,
- }mcde_fb_bpp;
-
- typedef enum
- {
- MCDE_U8500_PANEL_16BPP_RGB=35,
- MCDE_U8500_PANEL_16BPP_IRGB=36,
- MCDE_U8500_PANEL_16BPP_ARGB=37,
- MCDE_U8500_PANEL_12BPP=38,
- }mcde_fb_16bpp_type;
-
-
- typedef enum
- {
- MCDE_FS_FREQ_UNCHANGED = 0x0,
- MCDE_FS_FREQ_DIV_2 = 0x1
- }mcde_fs_div;
-
- typedef enum
- {
- MCDE_FS_FREQ_DIV_ENABLE = 0x0,
- MCDE_FS_FREQ_DIV_DISABLE = 0x1
- }mcde_fs_ctrl;
-
- typedef enum
- {
- MCDE_MULTI_CH_CTRL_ALL_OVR = 0x0,
- MCDE_MULTI_CH_CTRL_PRIMARY_OVR = 0x1
- }mcde_multi_ovr_ctrl;
-
- typedef enum
- {
- MCDE_BUFFER_SEL_EXT = 0x0,
- MCDE_BUFFER_AUTO_TOGGLE = 0x1,
- MCDE_BUFFER_SOFTWARE_SELECT = 0x2,
- MCDE_BUFFER_RESERVED
- }mcde_buffer_sel_mode;
-
- struct mcde_ext_src_ctrl
- {
- mcde_fs_div fs_div;
- mcde_fs_ctrl fs_ctrl;
- mcde_multi_ovr_ctrl ovr_ctrl;
- mcde_buffer_sel_mode sel_mode;
- };
-
-
-/*******************************************************************************
- Overlay Enums and Structures
- ******************************************************************************/
-
-
-/* typedef enum
- {
- MCDE_OVERLAY_0,
- MCDE_OVERLAY_1,
- MCDE_OVERLAY_2,
- MCDE_OVERLAY_3,
- MCDE_OVERLAY_4,
- MCDE_OVERLAY_5,
- MCDE_OVERLAY_6,
- MCDE_OVERLAY_7
- }mcde_overlay_id; */
-
-
-
-
-
-
-
- /* typedef enum
- {
- MCDE_OVR_INTERLACE_DISABLE = 0x0,
- MCDE_OVR_INTERLACE_ENABLE = 0x1
- }mcde_ovr_interlace_ctrl;
-
- typedef enum
- {
- MCDE_OVR_INTERLACE_TOPFIELD = 0x0,
- MCDE_OVR_INTERLACE_BOTTOMFIELD = 0x1
- }mcde_ovr_interlace_mode;*/
-
- typedef enum
- {
- MCDE_CH_A = 0x0,
- MCDE_CH_B = 0x1,
- MCDE_CH_C0 = 0x2,
- MCDE_CH_C1 = 0x3
- }mcde_ch_id;
-
- typedef enum
- {
- MCDE_FETCH_INPROGRESS = 0x0,
- MCDE_FETCH_COMPLETE = 0x1
- }mcde_ovr_fetch_status;
-
- typedef enum
- {
- MCDE_OVR_READ_COMPLETE = 0x0,
- MCDE_OVR_READ_INPROGRESS = 0x1
- }mcde_ovr_read_status;
-
- struct mcde_ovr_control
- {
- mcde_rotate_req rot_burst_req;
- mcde_outsnd_req outstnd_req;
- mcde_burst_req burst_req;
- u8 priority;
- mcde_color_key_ctrl color_key;
- mcde_pal_ctrl pal_control;
- mcde_col_conv_ctrl col_ctrl;
- mcde_overlay_ctrl ovr_state;
- mcde_ovr_alpha_enable alpha;
- mcde_ovr_clip_enable clip;
- };
-
- struct mcde_ovr_config
- {
- u32 line_per_frame;
- /* mcde_ovr_interlace_mode ovr_interlace;
- mcde_ovr_interlace_ctrl ovr_intlace_ctrl;*/
- mcde_ext_src src_id;
- u16 ovr_ppl;
- };
-
- struct mcde_ovr_conf2
- {
- u8 alpha_value;
- u8 pixoff;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- u32 watermark_level;
- };
- /*
- struct mcde_ovr_blend_ctrl
- {
- u8 alpha_value;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- u8 ovr_zlevel;
- u16 ovr_xpos;
- u16 ovr_ypos;
- };*/
-
- struct mcde_ovr_comp
- {
- u8 ovr_zlevel;
- u16 ovr_ypos;
- mcde_ch_id ch_id;
- u16 ovr_xpos;
- };
-
- struct mcde_ovr_clipincr
- {
- u32 lineincr;
- u32 yclip;
- u32 xclip;
- };
-
-struct mcde_ovr_clip
-{
- u32 ytlcoor;
- u32 xtlcoor;
- u32 ybrcoor;
- u32 xbrcoor;
-};
-
-typedef struct
-{
- u16 ovr_ypos;
- u16 ovr_xpos;
-}mcde_ovr_xy;
-
-
-typedef enum
-{
- MCDE_OVERLAY_NOT_BLOCKED = 0x0,
- MCDE_OVERLAY_BLOCKED = 0x1
-}mcde_ovr_blocked_status;
- struct mcde_ovr_status
- {
- mcde_ovr_blocked_status ovrb_status;
- mcde_ovr_fetch_status ovr_status;
- mcde_ovr_read_status ovr_read;
- };
-
- /*******************************************************************************
- Channel Configuration Enums and Structures
- ******************************************************************************/
-
-
-
- /* struct
- {
- u16 InitDelay;
- u16 PPDelay;
- }mcde_ch_delay;*/
-
- struct mcde_chsyncconf
- {
- u16 swint_vcnt;
- mcde_frame_events swint_vevent;
- u16 hwreq_vcnt;
- mcde_frame_events hwreq_vevent;
- };
-
- struct mcde_chsyncmod
- {
- mcde_synchro_out_interface out_synch_interface;
- mcde_synchro_source ch_synch_src;
- mcde_sw_trigger sw_trig;
-
- };
-
-
-
- struct mcde_ch_priority
- {
- u8 ch_priority;
- };
-
-typedef enum
-{
- MCDE_CHNL_RUNNING_NORMALLY = 0x0,
- MCDE_CHNL_ABORT_OCCURRED = 0x1
-}mcde_chnl_abort_state;
-
-typedef enum
-{
- MCDE_CHNL_READ_ONGOING = 0x0,
- MCDE_CHNL_READ_DONE = 0x1
-}mcde_chnl_read_status;
-
-typedef struct
-{
- mcde_chnl_abort_state abort_state;
- mcde_chnl_read_status read_state;
-}mcde_chnl_state;
- /*******************************************************************************
- Channel A/B Enums and Structures
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_CLOCKWISE = 0x0,
- MCDE_ANTICLOCKWISE = 0x1
- }mcde_rot_dir;
-
- typedef enum
- {
- MCDE_GAMMA_ENABLE = 0x0,
- MCDE_GAMMA_DISABLE = 0x1
- }mcde_gamma_ctrl;
-
- typedef enum
- {
- MCDE_INPUT_YCrCb = 0x0,
- MCDE_INPUT_RGB = 0x1
- }mcde_flicker_format;
-
- typedef enum
- {
- MCDE_ALPHA_INPUTSRC = 0x0,
- MCDE_ALPHA_REGISTER = 0x1
- }mcde_blend_control;
-
- typedef enum
- {
- MCDE_FORCE_FILTER0 = 0x0,
- MCDE_ADAPTIVE_FILTER = 0x1,
- MCDE_TEST_MODE = 0x2
- }mcde_flicker_filter_mode;
-
-
- typedef enum
- {
- MCDE_ROTATION_DISABLE = 0x0,
- MCDE_ROTATION_ENABLE = 0x1
- }mcde_roten;
-
- typedef enum
- {
- MCDE_CLR_ENHANCE_DISABLE = 0x0,
- MCDE_CLR_ENHANCE_ENABLE = 0x1
- }mcde_clr_enhance_ctrl;
-
- typedef enum
- {
- MCDE_BLEND_DISABLE = 0x0,
- MCDE_BLEND_ENABLE = 0x1
- }mcde_blend_status;
-
-
- typedef enum
- {
- MCDE_VERTICAL_ACTIVE_FRAME_DISABLE = 0x0,
- MCDE_ALL_FRAME_ENABLE = 0x1
- }mcde_va_enable;
-
- typedef enum
- {
- MCDE_OUTPUT_NORMAL = 0x0,
- MCDE_OUTPUT_TOGGLE = 0x1
- }mcde_toggle_enable;
-
- typedef enum
- {
- MCDE_SYNCHRO_HBP = 0x0,
- MCDE_SYNCHRO_CLP = 0x1,
- MCDE_SYNCHRO_HFP = 0x2,
- MCDE_SYNCHRO_HSW = 0x3
- }mcde_loadsel;
-
- typedef enum
- {
- MCDE_DATA_RISING_EDGE = 0x0,
- MCDE_DATA_FALLING_EDGE = 0x1
- }mcde_data_lines;
-
- struct mcde_chx_control0
- {
- mcde_rotate_req chx_read_request;
- u8 alpha_blend;
- mcde_rot_dir rot_dir;
- mcde_gamma_ctrl gamma_ctrl;
- mcde_flicker_format flicker_format;
- mcde_flicker_filter_mode filter_mode;
- mcde_blend_control blend_ctrl;
- mcde_key_ctrl key_ctrl;
- mcde_roten rot_enable;
- mcde_dithering_control dither_ctrl;
- mcde_clr_enhance_ctrl color_enhance;
- mcde_antiflicker_ctrl anti_flicker;
- mcde_blend_status blend;
- };
- struct mcde_chx_rgb_conv_coef
- {
- u16 Yr_red;
- u16 Yr_green;
- u16 Yr_blue;
- u16 Cr_red;
- u16 Cr_green;
- u16 Cr_blue;
- u16 Cb_red;
- u16 Cb_green;
- u16 Cb_blue;
- u16 Off_red;
- u16 Off_green;
- u16 Off_blue;
- };
-
- struct mcde_chx_flickfilter_coef
- {
- u8 threshold_ctrl0;
- u8 threshold_ctrl1;
- u8 threshold_ctrl2;
- u8 Coeff0_N3;
- u8 Coeff0_N2;
- u8 Coeff0_N1;
- u8 Coeff1_N3;
- u8 Coeff1_N2;
- u8 Coeff1_N1;
- u8 Coeff2_N3;
- u8 Coeff2_N2;
- u8 Coeff2_N1;
- };
-
- struct mcde_chx_tv_control
- {
- u16 num_lines;
- mcde_tvmode tv_mode;
- mcde_signal_level ifield;
- mcde_display_mode sel_mode;
- };
-
- struct mcde_chx_tv_blanking_field
- {
- u16 blanking_start;
- u16 blanking_end;
- };
-
-struct mcde_chx_tv_blanking2_field
- {
- u16 blanking_start;
- u16 blanking_end;
- };
-
-
- struct mcde_chx_tv_start_line
- {
- u16 field2_start_line;
- u16 field1_start_line;
- };
-
- struct mcde_chx_tv_dvo_offset
- {
- u16 field2_window_offset;
- u16 field1_window_offset;
- };
-
- struct mcde_chx_tv_swh_time
- {
- u16 tv_swh2;
- u16 tv_swh1;
- };
-
- struct mcde_chx_tv_timing1
- {
- u16 src_window_width;
- u16 destination_hor_offset;
- };
-
- struct mcde_chx_tv_lbalw_timing
- {
- u16 active_line_width;
- u16 line_blanking_width;
- };
-
- struct mcde_chx_tv_background_time
- {
- u8 background_cr;
- u8 background_cb;
- u8 background_lu;
- };
-
-struct mcde_chx_lcd_timing0
- {
- mcde_va_enable rev_va_enable;
- mcde_toggle_enable rev_toggle_enable;
- mcde_loadsel rev_sync_sel;
- u8 rev_delay1;
- u8 rev_delay0;
- mcde_va_enable ps_va_enable;
- mcde_toggle_enable ps_toggle_enable;
- mcde_loadsel ps_sync_sel;
- u8 ps_delay1;
- u8 ps_delay0;
- };
-
- struct mcde_chx_lcd_timing1
- {
- mcde_signal_level io_enable;
- mcde_data_lines ipc;
- mcde_signal_level ihs;
- mcde_signal_level ivs;
- mcde_signal_level ivp;
- mcde_signal_level iclspl;
- mcde_signal_level iclrev;
- mcde_signal_level iclsp;
- mcde_va_enable mcde_spl;
- mcde_toggle_enable spltgen;
- mcde_loadsel spl_sync_sel;
- u8 spl_delay1;
- u8 spl_delay0;
- };
-
-
- struct mcde_chx_palette
- {
- u16 alphared;
- u8 green;
- u8 blue;
- };
-
- struct mcde_chx_gamma
- {
- u8 red;
- u8 green;
- u8 blue;
- };
- typedef enum
- {
- MCDE_ROTATE0 = 0x0,
- MCDE_ROTATE1 = 0x1
-}mcde_rotate_num;
-
-
- /*******************************************************************************
- Channel C Enums
- ******************************************************************************/
-
- typedef enum
- {
- MCDE_SYNCHRO_NONE = 0x0,
- MCDE_SYNCHRO_C0 = 0x1,
- MCDE_SYNCHRO_C1 = 0x2,
- MCDE_SYNCHRO_PINGPONG = 0x3
- }mcde_sync_ctrl;
-
- typedef enum
- {
- MCDE_SIG_INACTIVE_POL_LOW = 0x0,
- MCDE_SIG_INACTIVE_POL_HIGH = 0x1
- }mcde_sig_pol;
-
- typedef enum
- {
- MCDE_CD_LOW = 0x0, /* CD low for data and high for command */
- MCDE_CD_HIGH = 0x1 /* CD high for data and low for command */
- }mcde_cd_polarity;
-
- typedef enum
- {
- MCDE_RES_INACTIVE = 0x0,
- MCDE_RES_ACTIVE = 0x1
- }mcde_resen;
-
- typedef enum
- {
- MCDE_CSEN_DEACTIVATED = 0x0,
- MCDE_CSEN_ACTIVATED = 0x1
- }mcde_cs_enable_rw;
-
- typedef enum
- {
- MCDE_PCLK_TVCLK1 = 0x0,
- MCDE_PCLK_72 = 0x1,
- MCDE_PCLK_TVCLK2 = 0x2
- }mcde_clk_sel;
-
- typedef enum
- {
- MCDE_SELECT_OUTBAND = 0x0,
- MCDE_SELECT_INBAND = 0x1,
- }mcde_inband_select;
-
- typedef enum
- {
- MCDE_BUS_SIZE_8 = 0x0,
- MCDE_BUS_SIZE_16 = 0x1
- }mcde_bus_size;
-
- typedef enum
- {
- MCDE_SYNCHRO_CAPTURE_DISABLE = 0x0,
- MCDE_SYNCHRO_CAPTURE_ENABLE = 0x1
- }mcde_synchro_capture;
-
- typedef enum
- {
- MCDE_VERTICAL_SYNCHRO_CAPTURE1 = 0x0,
- MCDE_VERTICAL_SYNCHRO_CHANNELA = 0x1,
- }mcde_synchro_select;
-
- typedef enum
- {
- MCDE_FIFO_WMLVL_4 = 0x0,
- MCDE_FIFO_WMLVL_8 = 0x1
- }mcde_fifo_wmlvl_sel;
-
- typedef enum
- {
- MCDE_CHANNEL_C_DISABLE = 0x0,
- MCDE_CHANNEL_C_ENABLE = 0x1
- }mcde_chc_enable;
-
- typedef enum
- {
- MCDE_POWER_DISABLE = 0x0,
- MCDE_POWER_ENABLE = 0x1
- }mcde_powen_select;
-
- typedef enum
- {
- MCDE_FLOW_DISABLE = 0x0,
- MCDE_FLOW_ENABLE = 0x1
- }mcde_flow_select;
-
- typedef enum
- {
- MCDE_DUPLX_DISABLE = 0x0,
- MCDE_DUPLX_ENABLE = 0x1
- }mcde_duplx_ctrl;
-
- typedef enum
- {
- MCDE_DUPLX_MODE_NONE = 0x0,
- MCDE_DUPLX_MODE_16_TO_32 = 0x1,
- MCDE_DUPLX_MODE_24_TO_32_RS = 0x2,
- MCDE_DUPLX_MODE_24_TO_32_LS = 0x3
- }mcde_duplx_mode_select;
-
- typedef enum
- {
- MCDE_TRANSFER_8_1 = 0x0,
- MCDE_TRANSFER_8_2 = 0x1,
- MCDE_TRANSFER_8_3 = 0x2,
- MCDE_TRANSFER_16_1 = 0x4,
- MCDE_TRANSFER_16_2 = 0x5
- }mcde_bit_segmentation_select;
-
- typedef enum
- {
- MCDE_TRANSACTION_COMMAND = 0x0,
- MCDE_TRANSACTION_DATA = 0x1
- }mcde_transaction_type;
-
- typedef enum
- {
- MCDE_VSYNC_SELECT = 0x0,
- MCDE_HSYNC_SELECT = 0x1
- }mcde_vertical_sync_sel;
-
- typedef enum
- {
- MCDE_VSYNC_ACTIVE_HIGH = 0x0,
- MCDE_VSYNC_ACTIVE_LOW = 0x1,
- }mcde_vertical_sync_polarity;
-
- typedef enum
- {
- MCDE_STBCLK_DIV_1 = 0x0,
- MCDE_STBCLK_DIV_2 = 0x1,
- MCDE_STBCLK_DIV_4 = 0x2,
- MCDE_STBCLK_DIV_8 = 0x3,
- MCDE_STBCLK_DIV_16 = 0x4,
- MCDE_STBCLK_DIV_32 = 0x5,
- MCDE_STBCLK_DIV_64 = 0x6,
- MCDE_STBCLK_DIV_128 = 0x7
- }mcde_synchro_clk_div_factor;
-
- typedef enum
- {
- MCDE_PANEL_INTEL_SERIES = 0x0,
- MCDE_PANEL_MOTOROLA_SERIES = 0x1
- }mcde_panel_protocol;
-
- typedef enum
- {
- MCDE_PANEL_C0 = 0x0,
- MCDE_PANEL_C1 = 0x1
- }mcde_chc_panel;
-
- typedef enum
- {
- MCDE_TXFIFO_WRITE_DATA = 0,
- MCDE_TXFIFO_READ_DATA,
- MCDE_TXFIFO_WRITE_COMMAND
- } mcde_txfifo_request_type;
-
-
- struct mcde_chc_ctrl
- {
- mcde_sync_ctrl sync;
- mcde_resen resen;
- mcde_synchro_select synsel;
- mcde_clk_sel clksel;
- };
-
- struct mcde_chc_config
- {
- mcde_sig_pol res_pol;
- mcde_sig_pol rd_pol;
- mcde_sig_pol wr_pol;
- mcde_cd_polarity cd_pol;
- mcde_sig_pol cs_pol;
- mcde_cs_enable_rw csen;
- mcde_inband_select inband_mode;
- mcde_bus_size bus_size;
- mcde_synchro_capture syncen;
- mcde_fifo_wmlvl_sel fifo_watermark;
- mcde_chc_enable chcen;
- };
-
- struct mcde_pbc_config
- {
- mcde_duplx_ctrl duplex_ctrl;
- mcde_duplx_mode_select duplex_mode;
- mcde_bit_segmentation_select data_segment;
- mcde_bit_segmentation_select cmd_segment;
- };
-
- struct mcde_pbc_mux
- {
- u32 imux0;
- u32 imux1;
- u32 imux2;
- u32 imux3;
- u32 imux4;
- };
-
- struct mcde_pbc_bitctrl
- {
- u32 bit_ctrl0;
- u32 bit_ctrl1;
- };
-
- struct mcde_sync_conf
- {
- u8 debounce_length;
- mcde_vertical_sync_sel sync_sel;
- mcde_vertical_sync_polarity sync_pol;
- mcde_synchro_clk_div_factor clk_div;
- u16 vsp_max;
- u16 vsp_min;
- };
-
- struct mcde_sync_trigger
- {
- u16 trigger_delay_cx;
- u8 sync_delay_c1;
- u8 sync_delay_c2;
- };
-
- struct mcde_cd_timing_activate
- {
- u8 cs_cd_deactivate;
- u8 cs_cd_activate;
- };
-
- struct mcde_rw_timing
- {
- mcde_panel_protocol panel_type;
- u8 readwrite_activate;
- u8 readwrite_deactivate;
- };
-
- struct mcde_data_out_timing
- {
- u8 data_out_deactivate;
- u8 data_out_activate;
- };
-
- /*********************************************************************
- DSIX typedefs
- *********************************************************************/
- typedef enum
- {
- MCDE_DSI_CH_VID0 = 0x0,
- MCDE_DSI_CH_CMD0 = 0x1,
- MCDE_DSI_CH_VID1 = 0x2,
- MCDE_DSI_CH_CMD1 = 0x3,
- MCDE_DSI_CH_VID2 = 0x4,
- MCDE_DSI_CH_CMD2 = 0x5
- }mcde_dsi_channel;
-
- typedef enum
- {
- MCDE_PLL_OUT_OFF = 0x0,
- MCDE_PLL_OUT_1 = 0x1,
- MCDE_PLL_OUT_2 = 0x2,
- MCDE_PLL_OUT_4 = 0x3
- }mcde_pll_div_sel;
-
- typedef enum
- {
- MCDE_CLK27 = 0x0,
- MCDE_TV1CLK = 0x1,
- MCDE_HDMICLK = 0x2,
- MCDE_TV2CLK = 0x3,
- MCDE_MXTALI = 0x4
- }mcde_pll_ref_clk;
-
- typedef enum
- {
- MCDE_DSI_CLK27 = 0x0,
- MCDE_DSI_MCDECLK = 0x1
- }mcde_clk_divider;
-
- typedef struct
- {
- mcde_pll_div_sel pllout_divsel2;
- mcde_pll_div_sel pllout_divsel1;
- mcde_pll_div_sel pllout_divsel0;
- mcde_pll_ref_clk pll4in_sel;
- mcde_clk_divider txescdiv_sel;
- u32 txescdiv;
- }mcde_dsi_clk_config;
-
- typedef enum
- {
- MCDE_PACKING_RGB565 = 0x0,
- MCDE_PACKING_RGB666 = 0x1,
- MCDE_PACKING_RGB888_R = 0x2,
- MCDE_PACKING_RGB888_B = 0x3,
- MCDE_PACKING_HDTV = 0x4
- }mcde_dsi_packing;
-
- typedef enum
- {
- MCDE_DSI_OUT_GENERIC_CMD = 0x0,
- MCDE_DSI_OUT_VIDEO_DCS = 0x1
- }mcde_dsi_synchro;
-
- typedef enum
- {
- MCDE_DSI_NO_SWAP = 0x0,
- MCDE_DSI_SWAP = 0x1,
- }mcde_dsi_swap;
-
- typedef enum
- {
- MCDE_DSI_CMD_16 = 0x0,
- MCDE_DSI_CMD_8 = 0x1
- }mcde_dsi_cmd;
-
- typedef enum
- {
- MCDE_DSI_CMD_MODE = 0x0,
- MCDE_DSI_VID_MODE = 0x1,
- }mcde_vid_mode;
-
- typedef struct
- {
- mcde_dsi_packing packing;
- mcde_dsi_synchro synchro;
- mcde_dsi_swap byte_swap;
- mcde_dsi_swap bit_swap;
- mcde_dsi_cmd cmd8;
- mcde_vid_mode vid_mode;
- u8 blanking;
- u32 words_per_frame;
- u32 words_per_packet;
- }mcde_dsi_conf;
-
-
-
-/*******************************************************************************
-MCDE Error Enums
-******************************************************************************/
-typedef enum
-{
- MCDE_OK = 0x00, /* No error.*/
- MCDE_NO_PENDING_EVENT_ERROR = 0x01,
- MCDE_NO_MORE_FILTER_PENDING_EVENT = 0x02,
- MCDE_NO_MORE_PENDING_EVENT = 0x03,
- MCDE_REMAINING_FILTER_PENDING_EVENTS = 0x04,
- MCDE_REMAINING_PENDING_EVENTS = 0x05,
- MCDE_INTERNAL_EVENT = 0x06,
- MCDE_INTERNAL_ERROR = 0x07,
- MCDE_NOT_CONFIGURED = 0x08,
- MCDE_REQUEST_PENDING = 0x09,
- MCDE_REQUEST_NOT_APPLICABLE = 0x0A,
- MCDE_INVALID_PARAMETER = 0x0B,
- MCDE_UNSUPPORTED_FEATURE = 0x0C,
- MCDE_UNSUPPORTED_HW = 0x0D
-}mcde_error;
-
-/*******************************************************************************
-MCDE driver specific structures
-******************************************************************************/
-
-typedef enum {
- CHANNEL_A = 0x0,
- CHANNEL_B = 0x1,
- CHANNEL_C0 = 0x2,
- CHANNEL_C1 = 0x3,
-}channel ;
-
-typedef enum {
- RES_QVGA = 0x0,
- RES_VGA = 0x1,
- RES_WVGA = 0x2,
-}screenres;
-
- typedef struct
- {
- u16 alphared;
- u8 green;
- u8 blue;
- }mcde_palette;
-
-typedef struct
-{
- u8 red;
- u8 green;
- u8 blue;
-}t_mcde_gamma;
-
-struct mcde_channel_data{
- channel channelid;
- u8 nopan;
- u8 nowrap;
- const char *restype;
- mcde_bpp_ctrl inbpp;
- mcde_out_bpp outbpp;
- u8 bpp16_type;
- u8 bgrinput;
- gpio_alt_function gpio_alt_func;
-};
-// per channel structure
-struct mcde_ovlextsrc_conf{
- u16 ovl_id; //bitmap of overlays used
- u8 num_ovl;
-};
-
-struct clut_addrmap {
- u32 clutaddr;
- u32 clutdmaaddr;
-};
-
-
-#endif //__KERNEL__
-
-/* FUNCTION PROTOTYPE */
-void mcdefb_enable(struct fb_info *info);
-void mcdefb_disable(struct fb_info *info);
-int mcde_enable(struct fb_info *info);
-int mcde_disable(struct fb_info *info);
-int convertbpp(u8 bpp);
-int mcde_conf_channel_color_key(struct fb_info *info, struct mcde_channel_color_key chnannel_color_key);
-/*inline */unsigned long get_line_length(int x, int bpp);
-/* inline */unsigned long claim_mcde_lock(mcde_ch_id chid);
-/*inline*/ void release_mcde_lock(mcde_ch_id chid, unsigned long flags);
-int mcde_set_buffer(struct fb_info *info, u32 buffer_address, mcde_buffer_id buff_id);
-int mcde_conf_dithering_ctrl(struct mcde_dithering_ctrl_conf dithering_ctrl_conf, struct fb_info *info);
-bool mcde_get_hdmi_flag(void);
-void mcde_configure_hdmi_channel(void);
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-/* HW V1 */
-void mcde_hdmi_display_init_command_mode(mcde_video_mode video_mode);
-#else
-/* HW ED */
-void mcde_hdmi_display_init_command_mode(void);
-#endif
-void mcde_hdmi_display_init_video_mode(void);
-void mcde_hdmi_test_directcommand_mode_highspeed(void);
-void mcde_send_hdmi_cmd_data(char* buf,int length, int dsicommand);
-void mcde_send_hdmi_cmd(char* buf,int length, int dsicommand);
-
-int mcde_extsrc_ovl_create(struct mcde_overlay_create *extsrc_ovl ,struct fb_info *info,u32 *pkey);
-int mcde_extsrc_ovl_remove(struct fb_info *info,u32 key);
-int mcde_alloc_source_buffer(struct mcde_sourcebuffer_alloc source_buff ,struct fb_info *info, u32 *pkey, u8 isUserRequest);
-int mcde_dealloc_source_buffer(struct fb_info *info, u32 srcbufferindex, u8 isUserRequest);
-int mcde_conf_extsource(struct mcde_ext_conf ext_src_config ,struct fb_info *info);
-int mcde_conf_overlay(struct mcde_conf_overlay ovrlayConfig ,struct fb_info *info);
-int mcde_conf_channel(struct mcde_ch_conf ch_config ,struct fb_info *info);
-int mcde_conf_lcd_timing(struct mcde_chnl_lcd_ctrl chnl_lcd_ctrl, struct fb_info *info);
-int mcde_conf_color_conversion_coeff(struct fb_info *info, mcde_colorconv_type color_conv_type);
-int mcde_conf_color_conversion(struct fb_info *info, struct mcde_conf_color_conv color_conv_ctrl);
-int mcde_conf_blend_ctrl(struct fb_info *info, struct mcde_blend_control blend_ctrl);
-int mcde_conf_rotation(struct fb_info *info, mcde_rot_dir rot_dir, mcde_roten rot_ctrl, u32 rot_addr0, u32 rot_addr1);
-int mcde_conf_chnlc(struct mcde_chc_config chnlc_config, struct mcde_chc_ctrl chnlc_control, struct fb_info *info);
-int mcde_conf_dsi_chnl(mcde_dsi_conf dsi_conf, mcde_dsi_clk_config clk_config, struct fb_info *info);
-int mcde_conf_scan_mode(mcde_scan_mode scan_mode, struct fb_info *info);
-
-mcde_error mcdesetextsrcconf(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_conf config);
-mcde_error mcdesetextsrcctrl(mcde_ch_id chid, mcde_ext_src src_id, struct mcde_ext_src_ctrl control);
-mcde_error mcdesetbufferaddr(mcde_ch_id chid, mcde_ext_src src_id, mcde_buffer_id buffer_id, u32 address);
-mcde_error mcdesetovrctrl(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_control ovr_cr);
-mcde_error mcdesetovrlayconf(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_config ovr_conf);
-mcde_error mcdesetovrconf2(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_conf2 ovr_conf2);
-mcde_error mcdesetovrljinc(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_ljinc);
-mcde_error mcdesettopleftmargincrop(mcde_ch_id chid, mcde_overlay_id overlay, u32 ovr_topmargin, u16 ovr_leftmargin);
-mcde_error mcdesetovrcomp(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_comp ovr_comp);
-mcde_error mcdesetovrclip(mcde_ch_id chid, mcde_overlay_id overlay, struct mcde_ovr_clip ovr_clip);
-mcde_error mcdesetovrstate(mcde_ch_id chid, mcde_overlay_id overlay, mcde_overlay_ctrl state);
-mcde_error mcdesetovrpplandlpf(mcde_ch_id chid, mcde_overlay_id overlay, u16 ppl, u16 lpf);
-mcde_error mcdesetstate(mcde_ch_id chid, mcde_state state);
-mcde_error mcdesetchnlXconf(mcde_ch_id chid, u16 channelnum, struct mcde_chconfig config);
-mcde_error mcdesetswsync(mcde_ch_id chid, u16 channelnum, mcde_sw_trigger sw_trig);
-mcde_error mcdesetchnlbckgndcol(mcde_ch_id chid, u16 channelnum, struct mcde_ch_bckgrnd_col color);
-mcde_error mcdesetchnlsyncprio(mcde_ch_id chid, u16 channelnum, u32 priority);
-mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
-mcde_error mcdesetflowXctrl(mcde_ch_id chid, struct mcde_chx_control0 control);
-mcde_error mcdesetpanelctrl(mcde_ch_id chid, struct mcde_chx_control1 control);
-mcde_error mcdesetcolorkey(mcde_ch_id chid, struct mcde_chx_color_key key, mcde_colorkey_type type);
-mcde_error mcdesetcolorconvmatrix(mcde_ch_id chid, struct mcde_chx_rgb_conv_coef coef);
-mcde_error mcdesetflickerfiltercoef(mcde_ch_id chid, struct mcde_chx_flickfilter_coef coef);
-mcde_error mcdesetLCDtiming0ctrl(mcde_ch_id chid, struct mcde_chx_lcd_timing0 control);
-mcde_error mcdesetLCDtiming1ctrl(mcde_ch_id channel, struct mcde_chx_lcd_timing1 control);
-mcde_error mcdesetrotaddr(mcde_ch_id chid, u32 address, mcde_rotate_num rotnum);
-mcde_error mcdesetpalette(mcde_ch_id chid, mcde_palette palette);
-mcde_error mcdesetditherctrl(mcde_ch_id chid, struct mcde_chx_dither_ctrl control);
-mcde_error mcdesetditheroffset(mcde_ch_id chid, struct mcde_chx_dithering_offset offset);
-mcde_error mcdesetgammacoeff(mcde_ch_id chid, struct mcde_chx_gamma gamma);
-mcde_error mcdesetoutmuxconf(mcde_ch_id chid, mcde_out_bpp outbpp);
-mcde_error mcdesetchnlXpowermode(mcde_ch_id chid, mcde_powen_select power);
-mcde_error mcdesetchnlXflowmode(mcde_ch_id chid, mcde_flow_select flow);
-mcde_error mcdesetcflowXcolorkeyctrl(mcde_ch_id chid, mcde_key_ctrl key_ctrl);
-mcde_error mcdesetblendctrl(mcde_ch_id chid, struct mcde_blend_control blend_ctrl);
-mcde_error mcdesetrotation(mcde_ch_id chid, mcde_rot_dir rot_dir, mcde_roten rot_ctrl);
-mcde_error mcdesetcolorconvctrl(mcde_ch_id chid, mcde_overlay_id overlay, mcde_col_conv_ctrl col_ctrl);
-mcde_error mcderesetextsrcovrlay(mcde_ch_id chid);
-mcde_error mcdesetchnlsyncsrc(mcde_ch_id chid, u16 channelnum, struct mcde_chsyncmod sync_mod);
-mcde_error mcdesetchnlsyncevent(mcde_ch_id chid, struct mcde_ch_conf ch_config);
-mcde_error mcdesetchnlLCDctrlreg(mcde_ch_id chid, struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg);
-mcde_error mcdesetchnlLCDhorizontaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing);
-mcde_error mcdesetchnlLCDverticaltiming(mcde_ch_id chid, struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing);
-mcde_error mcdesetditheringctrl(mcde_ch_id chid, mcde_dithering_ctrl dithering_control);
-mcde_error mcdesetscanmode(mcde_ch_id chid, mcde_scan_mode scan_mode);
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-/* HW V1 */
-mcde_state mcdegetchannelstate(mcde_ch_id chid);
-mcde_error mcdesetchnlCmode(mcde_ch_id chid, mcde_chc_panel panel_id, mcde_chc_enable state);
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#endif
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde_a0.h b/arch/arm/mach-ux500/include/mach/mcde_a0.h
deleted file mode 100755
index 8c06a628479..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_a0.h
+++ /dev/null
@@ -1,896 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#define WRITE_FIELD(reg, field, value) \
- (reg = (reg & (~((field##_MASK) << (field##_SHIFT)))) | ((value & (field##_MASK)) << (field##_SHIFT)) )
-
-
-#define MCDE_CR (MCDE_BASE + 0x0)
-#define MCDE_CR_MCDEEN 0x80000000
-#define MCDE_CR_AUTOCLKG_EN 0x40000000
-#define MCDE_CR_FABMUX 0x00020000
-#define MCDE_CR_F01MUX 0x00010000
-#define MCDE_CR_IFIFOCTRLEN 0x00008000
-#define MCDE_CR_DPIA_EN 0x00000200
-#define MCDE_CR_DPIB_EN 0x00000100
-#define MCDE_CR_DPIC0_EN 0x00000080
-#define MCDE_CR_DPIC1_EN 0x00000040
-#define MCDE_CR_DSIVID0_EN 0x00000020
-#define MCDE_CR_DSIVID1_EN 0x00000010
-#define MCDE_CR_DSIVID2_EN 0x00000008
-#define MCDE_CR_DSICMD0_EN 0x00000004
-#define MCDE_CR_DSICMD1_EN 0x00000002
-#define MCDE_CR_DSICMD2_EN 0x00000001
-
-
-#define MCDE_CONF0 (MCDE_BASE + 0x4)
-#define MCDE_CONF0_OUTMUX4_SHIFT 28
-#define MCDE_CONF0_OUTMUX4_MASK 0x7
-#define MCDE_CONF0_OUTMUX3_SHIFT 25
-#define MCDE_CONF0_OUTMUX3_MASK 0x7
-#define MCDE_CONF0_OUTMUX2_SHIFT 22
-#define MCDE_CONF0_OUTMUX2_MASK 0x7
-#define MCDE_CONF0_OUTMUX1_SHIFT 19
-#define MCDE_CONF0_OUTMUX1_MASK 0x7
-#define MCDE_CONF0_OUTMUX0_SHIFT 16
-#define MCDE_CONF0_OUTMUX0_MASK 0x7
-#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12
-#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x7
-#define MCDE_CONF0_FSYNCTRLB 0x00000800
-#define MCDE_CONF0_FSYNCTRLA 0x00000400
-#define MCDE_CONF0_SWAP_B_C1 0x00000200
-#define MCDE_CONF0_SWAP_A_C0 0x00000100
-#define MCDE_CONF0_SYNCMUX7 0x00000080
-#define MCDE_CONF0_SYNCMUX6 0x00000040
-#define MCDE_CONF0_SYNCMUX5 0x00000020
-#define MCDE_CONF0_SYNCMUX4 0x00000010
-#define MCDE_CONF0_SYNCMUX3 0x00000008
-#define MCDE_CONF0_SYNCMUX2 0x00000004
-#define MCDE_CONF0_SYNCMUX1 0x00000002
-#define MCDE_CONF0_SYNCMUX0 0x00000001
-
-
-#define MCDE_SSP (MCDE_BASE + 0x8)
-#define MCDE_SSP_SSPEN 0x00010000
-#define MCDE_SSP_SSPCMD 0x00000100
-#define MCDE_SSP_SSPDATA_SHIFT 0
-#define MCDE_SSP_SSPDATA_MASK 0xFF
-
-
-#define MCDE_AIS (MCDE_BASE + 0x100)
-#define MCDE_AIS_DSI2AI 0x00000040
-#define MCDE_AIS_DSI1AI 0x00000020
-#define MCDE_AIS_DSI0AI 0x00000010
-#define MCDE_AIS_MCDEERRI 0x00000008
-#define MCDE_AIS_MCDECHNLI 0x00000004
-#define MCDE_AIS_MCDEOVLI 0x00000002
-#define MCDE_AIS_MCDEPPI 0x00000001
-
-
-#define MCDE_IMSCPP (MCDE_BASE + 0x104)
-#define MCDE_IMSCPP_ROTFDIM_SHIFT 6
-#define MCDE_IMSCPP_ROTFDIM_MASK 0x3
-#define MCDE_IMSCPP_VCMPC1IM 0x00000020
-#define MCDE_IMSCPP_VCMPC0IM 0x00000010
-#define MCDE_IMSCPP_VSCC1IM 0x00000008
-#define MCDE_IMSCPP_VSCC0IM 0x00000004
-#define MCDE_IMSCPP_VCMPBIM 0x00000002
-#define MCDE_IMSCPP_VCMPAIM 0x00000001
-
-
-#define MCDE_IMSCOVL (MCDE_BASE + 0x108)
-#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16
-#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF
-#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0
-#define MCDE_IMSCOVL_OVLRDIM_MASK 0xFFFF
-
-
-#define MCDE_IMSCCHNL (MCDE_BASE + 0x10C)
-#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16
-#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF
-#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0
-#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0xFFFF
-
-
-#define MCDE_IMSCERR (MCDE_BASE + 0x110)
-#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16
-#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF
-#define MCDE_IMSCERR_FUC1IM 0x00000100
-#define MCDE_IMSCERR_FUC0IM 0x00000080
-#define MCDE_IMSCERR_ROTBFEIM_SHIFT 5
-#define MCDE_IMSCERR_ROTBFEIM_MASK 0x3
-#define MCDE_IMSCERR_ROTAFEIM_SHIFT 3
-#define MCDE_IMSCERR_ROTAFEIM_MASK 0x3
-#define MCDE_IMSCERR_SCHBLCKDIM 0x00000004
-#define MCDE_IMSCERR_FUBIM 0x00000002
-#define MCDE_IMSCERR_FUAIM 0x00000001
-
-
-#define MCDE_RISPP (MCDE_BASE + 0x114)
-#define MCDE_RISPP_ROTFDRIS_SHIFT 6
-#define MCDE_RISPP_ROTFDRIS_MASK 0x3
-#define MCDE_RISPP_VCMPC1RIS 0x00000020
-#define MCDE_RISPP_VCMPC0RIS 0x00000010
-#define MCDE_RISPP_VSCC1RIS 0x00000008
-#define MCDE_RISPP_VSCC0RIS 0x00000004
-#define MCDE_RISPP_VCMPBRIS 0x00000002
-#define MCDE_RISPP_VCMPARIS 0x00000001
-
-
-#define MCDE_RISOVL (MCDE_BASE + 0x118)
-#define MCDE_RISOVL_OVLFDRIS_SHIFT 16
-#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF
-#define MCDE_RISOVL_OVLRDRIS_SHIFT 0
-#define MCDE_RISOVL_OVLRDRIS_MASK 0xFFFF
-
-
-#define MCDE_RISCHNL (MCDE_BASE + 0x11C)
-#define MCDE_RISCHNL_CHNLARIS_SHIFT 16
-#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF
-#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0
-#define MCDE_RISCHNL_CHNLRDRIS_MASK 0xFFFF
-
-
-#define MCDE_RISERR (MCDE_BASE + 0x120)
-#define MCDE_RISERR_OVLFERRIS_SHIFT 16
-#define MCDE_RISERR_OVLFERRIS_MASK 0xFFFF
-#define MCDE_RISERR_FUC1RIS 0x00000100
-#define MCDE_RISERR_FUC0RIS 0x00000080
-#define MCDE_RISERR_ROTBFERIS_SHIFT 5
-#define MCDE_RISERR_ROTBFERIS_MASK 0x3
-#define MCDE_RISERR_ROTAFERIS_SHIFT 3
-#define MCDE_RISERR_ROTAFERIS_MASK 0x3
-#define MCDE_RISERR_SCHBLCKDRIS 0x00000004
-#define MCDE_RISERR_FUBRIS 0x00000002
-#define MCDE_RISERR_FUARIS 0x00000001
-
-
-#define MCDE_MISPP (MCDE_BASE + 0x124)
-#define MCDE_MISPP_ROTFDMIS_SHIFT 6
-#define MCDE_MISPP_ROTFDMIS_MASK 0x3
-#define MCDE_MISPP_VCMPC1MIS 0x00000020
-#define MCDE_MISPP_VCMPC0MIS 0x00000010
-#define MCDE_MISPP_VSCC1MIS 0x00000008
-#define MCDE_MISPP_VSCC0MIS 0x00000004
-#define MCDE_MISPP_VCMPBMIS 0x00000002
-#define MCDE_MISPP_VCMPAMIS 0x00000001
-
-
-#define MCDE_MISOVL (MCDE_BASE + 0x128)
-#define MCDE_MISOVL_OVLFDMIS_SHIFT 16
-#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF
-#define MCDE_MISOVL_OVLRDMIS_SHIFT 0
-#define MCDE_MISOVL_OVLRDMIS_MASK 0xFFFF
-
-
-#define MCDE_MISCHNL (MCDE_BASE + 0x12C)
-#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16
-#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF
-#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0
-#define MCDE_MISCHNL_CHNLRDMIS_MASK 0xFFFF
-#define MCDE_MISCHNL_CHNL_A 0x00000001
-#define MCDE_MISCHNL_CHNL_B 0x00000002
-#define MCDE_MISCHNL_CHNL_C0 0x00000004
-#define MCDE_MISCHNL_CHNL_C1 0x00000008
-
-
-#define MCDE_MISERR (MCDE_BASE + 0x130)
-#define MCDE_MISERR_OVLFERMIS_SHIFT 16
-#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF
-#define MCDE_MISERR_FUC1MIS 0x00000100
-#define MCDE_MISERR_FUC0MIS 0x00000080
-#define MCDE_MISERR_ROTBFEMIS_SHIFT 5
-#define MCDE_MISERR_ROTBFEMIS_MASK 0x3
-#define MCDE_MISERR_ROTAFEMIS_SHIFT 3
-#define MCDE_MISERR_ROTAFEMIS_MASK 0x3
-#define MCDE_MISERR_SCHBLCKDMIS 0x00000004
-#define MCDE_MISERR_FUBMIS 0x00000002
-#define MCDE_MISERR_FUAMIS 0x00000001
-
-
-#define MCDE_SISPP (MCDE_BASE + 0x134)
-#define MCDE_SISOVL (MCDE_BASE + 0x138)
-#define MCDE_SISCHNL (MCDE_BASE + 0x13C)
-#define MCDE_SISERR (MCDE_BASE + 0x140)
-
-
-#define MCDE_PID (MCDE_BASE + 0x1FC)
-#define MCDE_PID_MAJOR_SHIFT 24
-#define MCDE_PID_MAJOR_MASK 0xFF
-#define MCDE_PID_MINOR_SHIFT 16
-#define MCDE_PID_MINOR_MASK 0xFF
-#define MCDE_PID_DEV_SHIFT 8
-#define MCDE_PID_DEV_MASK 0xFF
-#define MCDE_PID_METALFIX_SHIFT 0
-#define MCDE_PID_METALFIX_MASK 0xFF
-
-
-#define MCDE_EXTSRCA0 (MCDE_BASE + 0x200)
-#define MCDE_EXTSRCA1 (MCDE_BASE + 0x204)
-#define MCDE_EXTSRCA2 (MCDE_BASE + 0x2C8)
-
-
-#define MCDE_EXTSRCCONF (MCDE_BASE + 0x20C)
-#define MCDE_EXTSRCCONF_BEPO 0x00004000
-#define MCDE_EXTSRCCONF_BEBO 0x00002000
-#define MCDE_EXTSRCCONF_BGR 0x00001000
-#define MCDE_EXTSRCCONF_BPP_SHIFT 8
-#define MCDE_EXTSRCCONF_BPP_MASK 0xF
-#define MCDE_EXTSRCCONF_PRI_OVLID_SHIFT 4
-#define MCDE_EXTSRCCONF_PRI_OVLID_MASK 0xF
-#define MCDE_EXTSRCCONF_BUF_NB_SHIFT 2
-#define MCDE_EXTSRCCONF_BUF_NB_MASK 0x3
-#define MCDE_EXTSRCCONF_BUF_ID_SHIFT 0
-#define MCDE_EXTSRCCONF_BUF_ID_MASK 0x3
-
-
-#define MCDE_EXTSRCCR (MCDE_BASE + 0x210)
-#define MCDE_EXTSRCCR_FORCE_FS_DIV 0x00000008
-#define MCDE_EXTSRCCR_FS_DIV_DISABLE 0x00000004
-#define MCDE_EXTSRCCR_MULTIOVL_CTRL 0x00000002
-#define MCDE_EXTSRCCR_SEL_MOD_SHIFT 0
-#define MCDE_EXTSRCCR_SEL_MOD_MASK 0x3
-
-
-#define MCDE_OVLCR (MCDE_BASE + 0x400)
-#define MCDE_OVLCR_ROTBURSTSIZE_SHIFT 28
-#define MCDE_OVLCR_ROTBURSTSIZE_MASK 0xF
-#define MCDE_OVLCR_MAXOUTSTANDING_SHIFT 24
-#define MCDE_OVLCR_MAXOUTSTANDING_MASK 0xF
-#define MCDE_OVLCR_BURSTSIZE_SHIFT 20
-#define MCDE_OVLCR_BURSTSIZE_MASK 0xF
-#define MCDE_OVLCR_STBPRIO_SHIFT 16
-#define MCDE_OVLCR_STBPRIO_MASK 0xF
-#define MCDE_OVLCR_FETCH_ROPC_SHIFT 8
-#define MCDE_OVLCR_GETCH_ROPC_MASK 0xFF
-#define MCDE_OVLCR_OVLB 0x00000080
-#define MCDE_OVLCR_OVLR 0x00000040
-#define MCDE_OVLCR_OVLF 0x00000020
-#define MCDE_OVLCR_ALPHAPMEN 0x00000010
-#define MCDE_OVLCR_CKEYEN 0x00000008
-#define MCDE_OVLCR_COLCCTRL_SHIFT 1
-#define MCDE_OVLCR_COLCCTRL_MASK 0x3
-#define MCDE_OVLCR_OVLEN 0x00000001
-
-
-#define MCDE_OVLCONF (MCDE_BASE + 0x404)
-#define MCDE_OVLCONF_LPF_SHIFT 16
-#define MCDE_OVLCONF_LPF_MASK 0x7FF
-#define MCDE_OVLCONF_EXTSRC_ID_SHIFT 11
-#define MCDE_OVLCONF_EXTSRC_ID_MASK 0xF
-#define MCDE_OVLCONF_PPL_SHIFT 0
-#define MCDE_OVLCONF_PPL_MASK 0x7FF
-
-
-#define MCDE_OVLCONF2 (MCDE_BASE + 0x408)
-#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_SHIFT 16
-#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_MASK 0x1FFF
-#define MCDE_OVLCONF2_PIXOFF_SHIFT 10
-#define MCDE_OVLCONF2_PIXOFF_MASK 0x3F
-#define MCDE_OVLCONF2_OPQ 0x00000200
-#define MCDE_OVLCONF2_ALPHAVALUE_SHIFT 1
-#define MCDE_OVLCONF2_ALPHAVALUE_MASK 0xFF
-#define MCDE_OVLCONF2_BP 0x00000001
-
-
-#define MCDE_OVLLJINC (MCDE_BASE + 0x40C)
-
-
-#define MCDE_OVLCROP (MCDE_BASE + 0x410)
-#define MCDE_OVLCROP_LMRGN_SHIFT 22
-#define MCDE_OVLCROP_LMRGN_MASK 0x3FF
-#define MCDE_OVLCROP_TMRGN_SHIFT 0
-#define MCDE_OVLCROP_TMRGN_MASK 0x3FFFFF
-
-
-#define MCDE_OVLCOMP (MCDE_BASE + 0x414)
-#define MCDE_OVLCOMP_Z_SHIFT 27
-#define MCDE_OVLCOMP_Z_MASK 0xF
-#define MCDE_OVLCOMP_YPOS_SHIFT 16
-#define MCDE_OVLCOMP_YPOS_MASK 0x7FF
-#define MCDE_OVLCOMP_CH_ID_SHIFT 11
-#define MCDE_OVLCOMP_CH_ID_MASK 0xF
-#define MCDE_OVLCOMP_XPOS_SHIFT 0
-#define MCDE_OVLCOMP_XPOS_MASK 0x7FF
-
-
-#define MCDE_CHNLCONF (MCDE_BASE + 0x600)
-#define MCDE_CHNLCONF_LPF_SHIFT 16
-#define MCDE_CHNLCONF_LPF_MASK 0x7FF
-#define MCDE_CHNLCONF_PPL_SHIFT 0
-#define MCDE_CHNLCONF_PPL_MASK 0x7FF
-
-
-#define MCDE_CHNLSTAT (MCDE_BASE + 0x604)
-#define MCDE_CHNLSTAT_CHNLBLBCKGND_EN 0x00010000
-#define MCDE_CHNLSTAT_CHNLA 0x00000002
-#define MCDE_CHNLSTAT_CHNLRD 0x00000001
-
-
-#define MCDE_CHNLSYNCHMOD (MCDE_BASE + 0x608)
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK 0x7
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT 0
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK 0x3
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_SELECTED_FORMATER 0x0
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC0 0x1
-#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC1 0x2
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_OUTPUT 0x0
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_AUTO 0x1
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SW 0x2
-#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_EXTERNAL 0x3
-
-
-#define MCDE_CHNLSYNCHSW (MCDE_BASE + 0x60C)
-#define MCDE_CHNLSYNCHSW_SW_TRIG 0x00000001
-
-
-#define MCDE_CHNLBCKGNDCOL (MCDE_BASE + 0x610)
-#define MCDE_CHNLBCKGNDCOL_R_SHIFT 16
-#define MCDE_CHNLBCKGNDCOL_R_MASK 0xFF
-#define MCDE_CHNLBCKGNDCOL_G_SHIFT 8
-#define MCDE_CHNLBCKGNDCOL_G_MASK 0xFF
-#define MCDE_CHNLBCKGNDCOL_B_SHIFT 0
-#define MCDE_CHNLBCKGNDCOL_B_MASK 0xFF
-
-
-#define MCDE_CHNLPRIO (MCDE_BASE + 0x614)
-#define MCDE_CHNLPRIO_CHNLPRIO_SHIFT 0
-#define MCDE_CHNLPRIO_CHNLPRIO_MASK 0xF
-
-
-#define MCDE_CR0 (MCDE_BASE + 0x800)
-#define MCDE_CR0_ROTBURSTSIZE_SHIFT 25
-#define MCDE_CR0_ROTBURSTSIZE_MASK 0x7F
-#define MCDE_CR0_ROTEN 0x01000000
-#define MCDE_CR0_ALPHABLEND_SHIFT 16
-#define MCDE_CR0_ALPHABLEND_MASK 0xFF
-#define MCDE_CR0_OLEDEN 0x00008000
-#define MCDE_CR0_PALMODE 0x00004000
-#define MCDE_CR0_FLICKFORMAT 0x00002000
-#define MCDE_CR0_FLICKMODE_SHIFT 11
-#define MCDE_CR0_FLICKMODE_MASK 0x3
-#define MCDE_CR0_BLENDCTRL 0x00000400
-#define MCDE_CR0_KEYCTRL_SHIFT 7
-#define MCDE_CR0_KEYCTRL_MASK 0x7
-#define MCDE_CR0_GAMEN 0x00000040
-#define MCDE_CR0_DITHEN 0x00000020
-#define MCDE_CR0_PALEN 0x00000010
-#define MCDE_CR0_AFLICKEN 0x00000008
-#define MCDE_CR0_BLENDEN 0x00000004
-#define MCDE_CR0_POWEREN 0x00000002
-#define MCDE_CR0_FLOEN 0x00000001
-
-#define MCDE_CR1 (MCDE_BASE + 0x804)
-#define MCDE_CR1_TEFFECTEN 0x80000000
-#define MCDE_CR1_CLKTYPE 0x40000000
-#define MCDE_CR1_BCD 0x20000000
-#define MCDE_CR1_OUTBPP_SHIFT 25
-#define MCDE_CR1_OUTBPP_MASK 0xF
-#define MCDE_CR1_CDWIN_SHIFT 13
-#define MCDE_CR1_CDWIN_MASK 0xF
-#define MCDE_CR1_CLKSEL_SHIFT 10
-#define MCDE_CR1_CLKSEL_MASK 0x7
-#define MCDE_CR1_PCD_SHIFT 0
-#define MCDE_CR1_PCD_MASK 0x3FF
-
-
-#define MCDE_COLKEY (MCDE_BASE + 0x808)
-#define MCDE_COLKEY_KEYA_SHIFT 24
-#define MCDE_COLKEY_KEYA_MASK 0xFF
-#define MCDE_COLKEY_KEYR_SHIFT 16
-#define MCDE_COLKEY_KEYR_MASK 0xFF
-#define MCDE_COLKEY_KEYG_SHIFT 8
-#define MCDE_COLKEY_KEYG_MASK 0xFF
-#define MCDE_COLKEY_KEYB_SHIFT 0
-#define MCDE_COLKEY_KEYB_MASK 0xFF
-
-
-#define MCDE_FCOLKEY (MCDE_BASE + 0x80C)
-#define MCDE_FCOLKEY_FKEYA_SHIFT 24
-#define MCDE_FCOLKEY_FKEYA_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYR_SHIFT 16
-#define MCDE_FCOLKEY_FKEYR_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYG_SHIFT 8
-#define MCDE_FCOLKEY_FKEYG_MASK 0xFF
-#define MCDE_FCOLKEY_FKEYB_SHIFT 0
-#define MCDE_FCOLKEY_FKEYB_MASK 0xFF
-
-
-#define MCDE_RGBCONV1 (MCDE_BASE + 0x810)
-#define MCDE_RGBCONV1_YR_RED_SHIFT 16
-#define MCDE_RGBCONV1_YR_RED_MASK 0x7FF
-#define MCDE_RGBCONV1_YR_GREEN_SHIFT 0
-#define MCDE_RGBCONV1_YR_GREEN_MASK 0x7FF
-
-
-#define MCDE_RGBCONV2 (MCDE_BASE + 0x814)
-#define MCDE_RGBCONV2_YR_BLUE_SHIFT 16
-#define MCDE_RGBCONV2_YR_BLUE_MASK 0x7FF
-#define MCDE_RGBCONV2_CR_RED_SHIFT 0
-#define MCDE_RGBCONV2_CR_RED_MASK 0x7FF
-
-
-#define MCDE_RGBCONV3 (MCDE_BASE + 0x818)
-#define MCDE_RGBCONV3_CR_GREEN_SHIFT 16
-#define MCDE_RGBCONV3_CR_GREEN_MASK 0x7FF
-#define MCDE_RGBCONV3_CR_BLUE_SHIFT 0
-#define MCDE_RGBCONV3_CR_BLUE_MASK 0x7FF
-
-
-#define MCDE_RGBCONV4 (MCDE_BASE + 0x81C)
-#define MCDE_RGBCONV4_CB_RED_SHIFT 16
-#define MCDE_RGBCONV4_CB_RED_MASK 0x7FF
-#define MCDE_RGBCONV4_CB_GREEN_SHIFT 0
-#define MCDE_RGBCONV4_CB_GREEN_MASK 0x7FF
-
-
-#define MCDE_RGBCONV5 (MCDE_BASE + 0x820)
-#define MCDE_RGBCONV5_CB_BLUE_SHIFT 16
-#define MCDE_RGBCONV5_CB_BLUE_MASK 0x7FF
-#define MCDE_RGBCONV5_OFF_RED_SHIFT 0
-#define MCDE_RGBCONV5_OFF_RED_MASK 0x7FF
-
-
-#define MCDE_RGBCONV6 (MCDE_BASE + 0x824)
-#define MCDE_RGBCONV6_OFF_GREEN_SHIFT 16
-#define MCDE_RGBCONV6_OFF_GREEN_MASK 0x7FF
-#define MCDE_RGBCONV6_OFF_BLUE_SHIFT 0
-#define MCDE_RGBCONV6_OFF_BLUE_MASK 0x7FF
-
-
-#define MCDE_FFCOEF0 (MCDE_BASE + 0x828)
-#define MCDE_FFCOEF0_TO_SHIFT 24
-#define MCDE_FFCOEF0_TO_MASK 0x0xF
-#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16
-#define MCDE_FFCOEF0_COEFF0_N3_MASK 0xFF
-#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8
-#define MCDE_FFCOEF0_COEFF0_N2_MASK 0xFF
-#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0
-#define MCDE_FFCOEF0_COEFF0_N1_MASK 0xFF
-
-
-#define MCDE_FFCOEF1 (MCDE_BASE + 0x82C)
-#define MCDE_FFCOEF1_T1_SHIFT 24
-#define MCDE_FFCOEF1_T1_MASK 0x0xF
-#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16
-#define MCDE_FFCOEF1_COEFF1_N3_MASK 0xFF
-#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8
-#define MCDE_FFCOEF1_COEFF1_N2_MASK 0xFF
-#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0
-#define MCDE_FFCOEF1_COEFF1_N1_MASK 0xFF
-
-
-#define MCDE_FFCOEF2 (MCDE_BASE + 0x830)
-#define MCDE_FFCOEF2_T2_SHIFT 24
-#define MCDE_FFCOEF2_T2_MASK 0x0xF
-#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16
-#define MCDE_FFCOEF2_COEFF2_N3_MASK 0xFF
-#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8
-#define MCDE_FFCOEF2_COEFF2_N2_MASK 0xFF
-#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0
-#define MCDE_FFCOEF2_COEFF2_N1_MASK 0xFF
-
-
-#define MCDE_TVCR (MCDE_BASE + 0x838)
-#define MCDE_TVCR_AVRGEN 0x00000100
-#define MCDE_TVCR_SDTVMODE_SHIFT 6
-#define MCDE_TVCR_SDTVMODE_MASK 0x3
-#define MCDE_TVCR_SDTVMODE_YC 0x0
-#define MCDE_TVCR_SDTVMODE_CY 0x1
-#define MCDE_TVCR_TVMODE_SHIFT 3
-#define MCDE_TVCR_TVMODE_MASK 0x7
-#define MCDE_TVCR_TVMODE_SDTV 0x0
-#define MCDE_TVCR_TVMODE_HDTV_480P 0x1
-#define MCDE_TVCR_TVMODE_HDTV_720P 0x2
-#define MCDE_TVCR_TVMODE_SDTV_DDR_LS_1ST 0x3
-#define MCDE_TVCR_TVMODE_SDTV_DDR_MS_1ST 0x4
-#define MCDE_TVCR_IFIELD_SHIFT 2
-#define MCDE_TVCR_IFIELD_MASK 0x1
-#define MCDE_TVCR_IFIELD_ACT_HGH 0x0
-#define MCDE_TVCR_IFIELD_ACT_LOW 0x1
-#define MCDE_TVCR_INTEREN 0x00000002
-#define MCDE_TVCR_SEL_MOD_SHIFT 0
-#define MCDE_TVCR_SEL_MOD_MASK 0x1
-#define MCDE_TVCR_SEL_MOD_LCD 0x0
-#define MCDE_TVCR_SEL_MOD_TV 0x1
-
-#define MCDE_TVBL1 (MCDE_BASE + 0x83C)
-#define MCDE_TVBL1_BSL1_SHIFT 16
-#define MCDE_TVBL1_BSL1_MASK 0x7FF
-#define MCDE_TVBL1_BEL1_SHIFT 0
-#define MCDE_TVBL1_BEL1_MASK 0x7FF
-
-
-#define MCDE_TVISL (MCDE_BASE + 0x840)
-#define MCDE_TVISL_FSL2_SHIFT 16
-#define MCDE_TVISL_FSL2_MASK 0x7FF
-#define MCDE_TVISL_FSL1_SHIFT 0
-#define MCDE_TVISL_FSL1_MASK 0x7FF
-
-
-#define MCDE_TVDVO (MCDE_BASE + 0x844)
-#define MCDE_TVDVO_DVO2_SHIFT 16
-#define MCDE_TVDVO_DVO2_MASK 0x7FF
-#define MCDE_TVDVO_DVO1_SHIFT 0
-#define MCDE_TVDVO_DVO1_MASK 0x7FF
-
-
-#define MCDE_TVTIM1 (MCDE_BASE + 0x84C)
-#define MCDE_TVTIM1_DHO_SHIFT 0
-#define MCDE_TVTIM1_DHO_MASK 0x7FF
-
-
-#define MCDE_TVLBALW (MCDE_BASE + 0x850)
-#define MCDE_TVLBALW_ALW_SHIFT 16
-#define MCDE_TVLBALW_ALW_MASK 0x7FF
-#define MCDE_TVLBALW_LBW_SHIFT 0
-#define MCDE_TVLBALW_LBW_MASK 0x7FF
-
-
-#define MCDE_TVBL2 (MCDE_BASE + 0x854)
-#define MCDE_TVBL2_BSL2_SHIFT 16
-#define MCDE_TVBL2_BSL2_MASK 0x7FF
-#define MCDE_TVBL2_BEL2_SHIFT 0
-#define MCDE_TVBL2_BEL2_MASK 0x7FF
-
-
-#define MCDE_TVBLU (MCDE_BASE + 0x858)
-#define MCDE_TVBLU_TVBCR_SHIFT 16
-#define MCDE_TVBLU_TVBCR_MASK 0xFF
-#define MCDE_TVBLU_TVBCB_SHIFT 8
-#define MCDE_TVBLU_TVBCB_MASK 0xFF
-#define MCDE_TVBLU_TVBLU_SHIFT 0
-#define MCDE_TVBLU_TVBLU_MASK 0xFF
-
-
-#define MCDE_LDCTIM0 (MCDE_BASE + 0x85C)
-#define MCDE_LDCTIM0_REVVAEN 0x80000000
-#define MCDE_LDCTIM0_REVTGEN 0x40000000
-#define MCDE_LDCTIM0_REVLOADSEL_SHIFT 28
-#define MCDE_LDCTIM0_REVLOADSEL_MASK 0x3
-#define MCDE_LDCTIM0_REVDEL1_SHIFT 24
-#define MCDE_LDCTIM0_REVDEL1_MASK 0xF
-#define MCDE_LDCTIM0_REVDEL0_SHIFT 16
-#define MCDE_LDCTIM0_REVDEL0_MASK 0xFF
-#define MCDE_LDCTIM0_PSVAEN 0x00008000
-#define MCDE_LDCTIM0_PSTGEN 0x00004000
-#define MCDE_LDCTIM0_PSLOADSEL_SHIFT 12
-#define MCDE_LDCTIM0_PSLOADSEL_MASK 0x3
-#define MCDE_LDCTIM0_PSDEL1_SHIFT 8
-#define MCDE_LDCTIM0_PSDEL1_MASK 0xF
-#define MCDE_LDCTIM0_PSDEL0_SHIFT 0
-#define MCDE_LDCTIM0_PSDEL0_MASK 0xFF
-
-
-#define MCDE_LCDTIM1 (MCDE_BASE + 0x860)
-#define MCDE_LCDTIM1_IOE 0x00800000
-#define MCDE_LCDTIM1_IPC 0x00400000
-#define MCDE_LCDTIM1_IHS 0x00200000
-#define MCDE_LCDTIM1_IVS 0x00100000
-#define MCDE_LCDTIM1_IVP 0x00080000
-#define MCDE_LCDTIM1_ICLSPL 0x00040000
-#define MCDE_LCDTIM1_ICLREV 0x00020000
-#define MCDE_LCDTIM1_ICLSP 0x00010000
-#define MCDE_LCDTIM1_SPLVAEN 0x00008000
-#define MCDE_LCDTIM1_SPLTGEN 0x00004000
-#define MCDE_LCDTIM1_SPLLOADSEL_SHIFT 12
-#define MCDE_LCDTIM1_SPLLOADSEL_MASK 0x3
-#define MCDE_LCDTIM1_SPLDEL1_SHIFT 8
-#define MCDE_LCDTIM1_SPLDEL1_MASK 0xF
-#define MCDE_LCDTIM1_SPLDEL0_SHIFT 0
-#define MCDE_LCDTIM1_SPLDEL0_MASK 0xFF
-
-
-#define MCDE_DITCTRL (MCDE_BASE + 0x864)
-#define MCDE_DITCTRL_FOFFY_SHIFT 10
-#define MCDE_DITCTRL_FOFFY_MASK 0x1F
-#define MCDE_DITCTRL_FOFFX_SHIFT 5
-#define MCDE_DITCTRL_FOFFX_MASK 0x1F
-#define MCDE_DITCTRL_MASK 0x00000010
-#define MCDE_DITCTRL_MODE_SHIFT 2
-#define MCDE_DITCTRL_MODE_MASK 0x3
-#define MCDE_DITCTRL_COMP 0x00000002
-#define MCDE_DITCTRL_TEMP 0x00000001
-
-
-#define MCDE_DITOFF (MCDE_BASE + 0x868)
-#define MCDE_DITOFF_YB_SHIFT 24
-#define MCDE_DITOFF_YB_MASK 0x1F
-#define MCDE_DITOFF_XB_SHIFT 16
-#define MCDE_DITOFF_XB_MASK 0x1F
-#define MCDE_DITOFF_YG_SHIFT 8
-#define MCDE_DITOFF_YG_MASK 0x1F
-#define MCDE_DITOFF_XG_SHIFT 0
-#define MCDE_DITOFF_XG_MASK 0x1F
-
-
-#define MCDE_PAL0 (MCDE_BASE + 0x86C)
-#define MCDE_PAL0_GREEN_SHIFT 16
-#define MCDE_PAL0_GREEN_MASK 0xFFF
-#define MCDE_PAL0_BLUE_SHIFT 0
-#define MCDE_PAL0_BLUE_MASK 0xFFF
-
-
-#define MCDE_PAL1 (MCDE_BASE + 0x870)
-#define MCDE_PAL1_RED_SHIFT 0
-#define MCDE_PAL1_RED_MASK 0xFFF
-
-
-#define MCDE_ROTADD0 (MCDE_BASE + 0x874)
-//#define MCDE_ROTADD0_SHIFT 3
-//#define MCDE_ROTADD0_MASK
-#define MCDE_ROTADD1 (MCDE_BASE + 0x878)
-
-
-#define MCDE_ROTCONF (MCDE_BASE + 0x87C)
-#define MCDE_ROTCONF_RD_ROPC_SHIFT 24
-#define MCDE_ROTCONF_RD_ROPC_MASK 0xFF
-#define MCDE_ROTCONF_WR_ROPC_SHIFT 16
-#define MCDE_ROTCONF_WR_ROPC_MASK 0xFF
-#define MCDE_ROTCONF_STRIP_WIDTH_SHIFT 8
-#define MCDE_ROTCONF_STRIP_WIDTH_MASK 0xFF
-#define MCDE_ROTCONF_RD_MAXOUT_SHIFT 6
-#define MCDE_ROTCONF_RD_MAXOUT_MASK 0x3
-#define MCDE_ROTCONF_WR_MAXOUT_SHIFT 4
-#define MCDE_ROTCONF_WR_MAXOUT_MASK 0x3
-#define MCDE_ROTCONF_ROTDIR 0x00000008
-#define MCDE_ROTCONF_ROTBURSTSIZE_SHIFT 0
-#define MCDE_ROTCONF_ROTBURSTSIZE_MASK 0x7
-
-
-#define MCDE_SYNCHCONF (MCDE_BASE + 0x880)
-#define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18
-#define MCDE_SYNCHCONF_SWINTVCNT_MASK 0x3FFF
-#define MCDE_SYNCHCONF_SWINTVEVENT_SHIFT 16
-#define MCDE_SYNCHCONF_SWINTVEVENT_MASK 0x3
-#define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2
-#define MCDE_SYNCHCONF_HWREQVCNT_MASK 0x3FFF
-#define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0
-#define MCDE_SYNCHCONF_HWREQVEVENT_MASK 0x3
-
-
-#define MCDE_GAM0 (MCDE_BASE + 0x888)
-#define MCDE_GAM0_BLUE_SHIFT 0
-#define MCDE_GAM0_BLUE_MASK 0x00FFFFFF
-
-
-#define MCDE_GAM1 (MCDE_BASE + 0x88C)
-#define MCDE_GAM1_GREEN_SHIFT 0
-#define MCDE_GAM1_GREEN_MASK 0x00FFFFFF
-
-
-#define MCDE_GAM2 (MCDE_BASE + 0x890)
-#define MCDE_GAM2_RED_SHIFT 0
-#define MCDE_GAM2_RED_MASK 0x00FFFFFF
-
-
-#define MCDE_OLEDCONV1 (MCDE_BASE + 0x894)
-#define MCDE_OLEDCONV1_ALPHA_GREEN_SHIFT 16
-#define MCDE_OLEDCONV1_ALPHA_GREEN_MASK 0x3FFF
-#define MCDE_OLEDCONV1_ALPHA_RED_SHIFT 0
-#define MCDE_OLEDCONV1_ALPHA_RED_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV2 (MCDE_BASE + 0x898)
-#define MCDE_OLEDCONV2_BETA_RED_SHIFT 16
-#define MCDE_OLEDCONV2_BETA_RED_MASK 0x3FFF
-#define MCDE_OLEDCONV2_ALPHA_BLUE_SHIFT 0
-#define MCDE_OLEDCONV2_ALPHA_BLUE_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV3 (MCDE_BASE + 0x89C)
-#define MCDE_OLEDCONV3_BETA_BLUE_SHIFT 16
-#define MCDE_OLEDCONV3_BETA_BLUE_MASK 0x3FFF
-#define MCDE_OLEDCONV3_BETA_GREEN_SHIFT 0
-#define MCDE_OLEDCONV3_BETA_GREEN_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV4 (MCDE_BASE + 0x8A0)
-#define MCDE_OLEDCONV4_GAMMA_GREEN_SHIFT 16
-#define MCDE_OLEDCONV4_GAMMA_GREEN_MASK 0x3FFF
-#define MCDE_OLEDCONV4_GAMMA_RED_SHIFT 0
-#define MCDE_OLEDCONV4_GAMMA_RED_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV5 (MCDE_BASE + 0x8A4)
-#define MCDE_OLEDCONV5_OFF_RED_SHIFT 16
-#define MCDE_OLEDCONV5_OFF_RED_MASK 0x3FFF
-#define MCDE_OLEDCONV5_GAMMA_BLUE_SHIFT 0
-#define MCDE_OLEDCONV5_GAMMA_BLUE_MASK 0x3FFF
-
-
-#define MCDE_OLEDCONV6 (MCDE_BASE + 0x8A8)
-#define MCDE_OLEDCONV6_OFF_BLUE_SHIFT 16
-#define MCDE_OLEDCONV6_OFF_BLUE_MASK 0x3FFF
-#define MCDE_OLEDCONV6_OFF_GREEN_SHIFT 0
-#define MCDE_OLEDCONV6_OFF_GREEN_MASK 0x3FFF
-
-
-#define MCDE_CRC (MCDE_BASE + 0xC00)
-#define MCDE_CRC_CLAMPC1EN 0x80000000
-#define MCDE_CRC_SYNCCTRL_SHIFT 29
-#define MCDE_CRC_SYNCCTRL_MASK 0x3
-#define MCDE_CRC_RES2POL 0x10000000
-#define MCDE_CRC_RES1POL 0x08000000
-#define MCDE_CRC_RD2POL 0x04000000
-#define MCDE_CRC_RD1POL 0x02000000
-#define MCDE_CRC_WR2POL 0x01000000
-#define MCDE_CRC_WR1POL 0x00800000
-#define MCDE_CRC_CD2POL 0x00400000
-#define MCDE_CRC_CD1POL 0x00200000
-#define MCDE_CRC_CS2POL 0x00100000
-#define MCDE_CRC_CS1POL 0x00080000
-#define MCDE_CRC_RESEN 0x00040000
-#define MCDE_CRC_CS2EN 0x00020000
-#define MCDE_CRC_CS1EN 0x00010000
-#define MCDE_CRC_YUVCONVC1EN 0x00008000
-#define MCDE_CRC_CLKSEL_SHIFT 13
-#define MCDE_CRC_CLKSEL_MASK 0x3
-#define MCDE_CRC_INBAND2 0x00001000
-#define MCDE_CRC_INBAND1 0x00000800
-#define MCDE_CRC_SIZE2 0x00000400
-#define MCDE_CRC_SIZE1 0x00000200
-#define MCDE_CRC_SYCEN1 0x00000100
-#define MCDE_CRC_SYCEN0 0x00000080
-#define MCDE_CRC_SYNCSEL 0x00000040
-#define MCDE_CRC_WMLVL2 0x00000020
-#define MCDE_CRC_WMLVL1 0x00000010
-#define MCDE_CRC_C2EN 0x00000008
-#define MCDE_CRC_C1EN 0x00000004
-#define MCDE_CRC_POWEREN 0x00000002
-#define MCDE_CRC_FLOEN 0x00000001
-
-
-#define MCDE_PBCCRC (MCDE_BASE + 0xC04)
-#define MCDE_PBCCRC_BPP_SHIFT 13
-#define MCDE_PBCCRC_BPP_MASK 0x7
-#define MCDE_PBCCRC_PDCTRL 0x00001000
-#define MCDE_PBCCRC_PDM_SHIFT 8
-#define MCDE_PBCCRC_PDM_MASK 0x3
-#define MCDE_PBCCRC_BSDM_SHIFT 4
-#define MCDE_PBCCRC_BSDM_MASK 0x7
-#define MCDE_PBCCRC_BSCM_SHIFT 0
-#define MCDE_PBCCRC_BSCM_MASK 0x7
-
-
-#define MCDE_PBCBMRC (MCDE_BASE + 0xC0C)
-#define MCDE_PBCBCRC (MCDE_BASE + 0xC34)
-
-
-#define MCDE_VSCRC (MCDE_BASE + 0xC5C)
-#define MCDE_VSCRC_VSDBL_SHIFT 29
-#define MCDE_VSCRC_VSDBL_MASK 0x7
-#define MCDE_VSCRC_VSSEL 0x10000000
-#define MCDE_VSCRC_VSPOL 0x08000000
-#define MCDE_VSCRC_VSPDIV_SHIFT 24
-#define MCDE_VSCRC_VSPDIV_MASK 0x7
-#define MCDE_VSCRC_VSPMAX_SHIFT 12
-#define MCDE_VSCRC_VSPMAX_MASK 0xFFF
-#define MCDE_VSCRC_VSPMIN_SHIFT 0
-#define MCDE_VSCRC_VSPMIN_MASK 0xFFF
-
-
-#define MCDE_SCTRC (MCDE_BASE + 0xC64)
-#define MCDE_SCTRC_TRDELC_SHIFT 16
-#define MCDE_SCTRC_TRDELC_MASK 0xFFF
-#define MCDE_SCTRC_SYNCDELC1_SHIFT 8
-#define MCDE_SCTRC_SYNCDELC1_MASK 0xFF
-#define MCDE_SCTRC_SYNCDELC0_SHIFT 0
-#define MCDE_SCTRC_SYNCDELC0_MASK 0xFF
-
-
-#define MCDE_SCSRC (MCDE_BASE + 0xC68)
-#define MCDE_SCSRC_VSTAC1 0x00000002
-#define MCDE_SCSRC_VSTAC0 0x00000001
-
-
-#define MCDE_BCNR (MCDE_BASE + 0xC6C)
-#define MCDE_BCNR_BCN_SHIFT 0
-#define MCDE_BCNR_BCN_MASK 0xFF
-
-
-#define MCDE_CSCDTR (MCDE_BASE + 0xC74)
-#define MCDE_CSCDTR_CSCDDEACT_SHIFT 8
-#define MCDE_CSCDTR_CSCDDEACT_MASK 0xFF
-#define MCDE_CSCDTR_CSCDACT_SHIFT 0
-#define MCDE_CSCDTR_CSCDACT_MASK 0xFF
-
-
-#define MCDE_RDWRTR (MCDE_BASE + 0xC7C)
-#define MCDE_RDWRTR_MOTINT 0x00010000
-#define MCDE_RDWRTR_RWDEACT_SHIFT 8
-#define MCDE_RDWRTR_RWDEACT_MASK 0xFF
-#define MCDE_RDWRTR_RWACT_SHIFT 0
-#define MCDE_RDWRTR_RWACT_MASK 0xFF
-
-
-#define MCDE_DOTR (MCDE_BASE + 0xC84)
-#define MCDE_DOTR_DODEACT_SHIFT 8
-#define MCDE_DOTR_DODEACT_MASK 0xFF
-#define MCDE_DOTR_DOACT_SHIFT 0
-#define MCDE_DOTR_DOACT_MASK 0xFF
-
-
-#define MCDE_WCMDC (MCDE_BASE + 0xC8C)
-#define MCDE_WDATADC (MCDE_BASE + 0xC94)
-
-
-#define MCDE_RDATADC (MCDE_BASE + 0xC9C)
-#define MCDE_RDATADC_STARTREAD 0x00010000
-#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_SHIFT 0
-#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_MASK 0xFF
-
-
-#define MCDE_STATC (MCDE_BASE + 0xCA4)
-#define MCDE_STATC_FIFOCMDFULL1 0x00000200
-#define MCDE_STATC_FIFOCMDEMPTY1 0x00000100
-#define MCDE_STATC_FIFOFULL1 0x00000080
-#define MCDE_STATC_FIFOEMPTY1 0x00000040
-#define MCDE_STATC_STATBUSY1 0x00000020
-#define MCDE_STATC_FIFOCMDFULL0 0x00000010
-#define MCDE_STATC_FIFOCMDEMPTY0 0x00000008
-#define MCDE_STATC_FIFOFULL0 0x00000004
-#define MCDE_STATC_FIFOEMPTY0 0x00000002
-#define MCDE_STATC_STATBUSY0 0x00000001
-
-
-#define MCDE_CTRLC (MCDE_BASE + 0xCA8)
-#define MCDE_CTRLC_FIFOWTRMRK_SHIFT 0
-#define MCDE_CTRLC_FIFOWTRMRK_MASK 0xFF
-
-
-#define MCDE_DSICONF0 (MCDE_BASE + 0xE00)
-#define MCDE_DSICONF0_PACKING_SHIFT 20
-#define MCDE_DSICONF0_PACKING_MASK 0x7
-#define MCDE_DSICONF0_DCSVID_NOTGEN 0x00040000
-#define MCDE_DSICONF0_BYTE_SWAP 0x00020000
-#define MCDE_DSICONF0_BIT_SWAP 0x00010000
-#define MCDE_DSICONF0_CMD8 0x00002000
-#define MCDE_DSICONF0_VID_MODE 0x00001000
-#define MCDE_DSICONF0_BLANKING_SHIFT 0
-#define MCDE_DSICONF0_BLANKING_MASK 0xFF
-
-
-#define MCDE_DSIFRAME (MCDE_BASE + 0xE04)
-
-#define MCDE_DSIPKT (MCDE_BASE + 0xE08)
-#define MCDE_DSIPKT_PACKET_SHIFT 0
-#define MCDE_DSIPKT_PACKET_MASK 0xFFFF
-
-
-#define MCDE_DSISYNC (MCDE_BASE + 0xE0C)
-#define MCDE_DSISYNC_SW_SHIFT 16
-#define MCDE_DSISYNC_SW_MASK 0xFFF
-#define MCDE_DSISYNC_DMA_SHIFT 0
-#define MCDE_DSISYNC_DMA_MASK 0xFFF
-
-
-#define MCDE_DSICMDW (MCDE_BASE + 0xE10)
-#define MCDE_DSICMDW_CMDW_START_SHIFT 16
-#define MCDE_DSICMDW_CMDW_START_MASK 0xFFFF
-#define MCDE_DSICMDW_CMDW_CONTINUE_SHIFT 0
-#define MCDE_DSICMDW_CMDW_CONTINUE_MASK 0xFFFF
-#define MCDE_DSICMDW_CMD_START_MEMORY_WRITE 0x2C
-#define MCDE_DSICMDW_CMD_CONTINUE_MEMORY_WRITE 0x3C
-
-
-#define MCDE_DSIDELAY0 (MCDE_BASE + 0xE14)
-#define MCDE_DSIDELAY0_INTPKTDEL_SHIFT 0
-#define MCDE_DSIDELAY0_INTPKTDEL_MASK 0xFFFF
-
-
-#define MCDE_DSIDELAY1 (MCDE_BASE + 0xE18)
-#define MCDE_DSIDELAY1_FRAMESTARTDEL_SHIFT 16
-#define MCDE_DSIDELAY1_FRAMESTARTDEL_MASK 0xFF
-#define MCDE_DSIDELAY1_TEREQDEL_SHIFT 0
-#define MCDE_DSIDELAY1_TEREQDEL_MASK 0xFFF
-
-
diff --git a/arch/arm/mach-ux500/include/mach/mcde_common.h b/arch/arm/mach-ux500/include/mach/mcde_common.h
deleted file mode 100755
index b906114c6a4..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_common.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_COMMON_H_
-#define _MCDE_COMMON_H_
-#include <linux/fb.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/bit_mask.h>
-#include <mach/mcde.h>
-#include <mach/mcde_reg.h>
-#include <mach/dsi.h>
-#include <mach/dsi_reg.h>
-
-#define MCDE_NAME "DRIVER MCDE"
-
-#define MCDE_DEFAULT_LOG_LEVEL 3
-#ifdef CONFIG_FB_NDK_MCDE
-extern int mcde_debug;
-module_param(mcde_debug, int, 0644);
-#endif
-#ifdef CONFIG_FB_NDK_MCDE
-MODULE_PARM_DESC(mcde_debug,"Debug level for messages");
-#define dbgprintk(num, format, args...) \
- do { \
- if(num >= mcde_debug ) \
- printk("MCDE:"format, ##args); \
- } while(0)
-#else
-#define dbgprintk(num, format, args...) \
- do { \
- printk("MCDE:"format, ##args); \
- } while(0)
-#endif
-
-#define MCDE_DEBUG_INFO 1
-#define MCDE_ERROR_INFO 3
-
-/** Global data */
-
-#define MAX_LPF 1080
-#define MAX_PPL 1920
-#define NUM_MCDE_FLOWS 4
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-#define NUM_OVERLAYS 6
-#define NUM_EXT_SRC 10
-#define NUM_MCDE_CHANNELS 4
-#else
-#define NUM_OVERLAYS 16
-#define NUM_EXT_SRC 16
-#define NUM_MCDE_CHANNELS 16
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-#define NUM_FLOWS_A_B 2
-#define NUM_DSI_LINKS 3
-#define NUM_DSI_CHANNEL 6
-#define MCDE_MAX_FRAMEBUFF 16
-#define COLCONV_COEFF_OFF 6
-
-/** clcd events for double buffering */
-struct clcd_event_struct {
- spinlock_t lock;
- int event;
- wait_queue_head_t wait;
- unsigned int base;
-};
-
-/** bitmap of which overlays are in use (set) and unused (cleared) */
-//static u32 mcde_ovl_bmp;
-
-/** MCDE private struct - pointer available in fbinfo */
-struct mcdefb_info {
- struct mcde_channel_data *chnl_info;
- mcde_ch_id chid;
- mcde_video_mode video_mode;
- mcde_fifo_output fifoOutput;
- mcde_output_conf output_conf;
- mcde_dsi_clk_config clk_config;
- mcde_ch_id dsi_formatter_plugged_channel[NUM_DSI_CHANNEL];
- mcde_dsi_channel mcdeDsiChnl;
- mcde_out_bpp outbpp;
- int bpp16_type;
- u8 bgrinput;
- u8 isHwInitalized;
- u16 palette_size;
- u32 cmap[16];
-
- mcde_ch_id pixel_pipeline;
- u32 vcomp_irq;
- u32 dsi_formatter;
- u32 dsi_mode;
- u32 swap;
- u32 started;
-
- /** phy-virtual addresses allocated for framebuffer and overlays */
- struct mcde_addrmap buffaddr[MCDE_MAX_FRAMEBUFF*2];
- struct mcde_addrmap rotationbuffaddr0;
- struct mcde_addrmap rotationbuffaddr1;
-
- /** total number of overlays used in the system */
- u8 tot_ovl_used;
-
- /** bitmap of which overlays are in use (set) and unused (cleared) */
- u16 mcde_cur_ovl_bmp;
- u16 mcde_ovl_bmp_arr[MCDE_MAX_FRAMEBUFF];
- spinlock_t mcde_spin_lock;
-
- /** event for double buffering */
- struct clcd_event_struct clcd_event;
- u8 tvout;
- u32 actual_bpp;
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- struct mcde_top_reg __iomem *regbase;
-#else
- struct mcde_register_base __iomem * regbase;
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
- struct mcde_ext_src_reg __iomem * extsrc_regbase[NUM_EXT_SRC];
- struct mcde_ovl_reg __iomem * ovl_regbase[NUM_OVERLAYS];
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- struct mcde_chnl_conf_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
- struct mcde_chAB_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
- struct mcde_chC0C1_reg __iomem *ch_c_reg;
-#else
- struct mcde_ch_synch_reg __iomem *ch_regbase1[NUM_MCDE_CHANNELS];
- struct mcde_ch_reg __iomem *ch_regbase2[NUM_FLOWS_A_B];
- struct mcde_chc_reg __iomem *ch_c_reg;
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
- struct mcde_dsi_reg __iomem *mcde_dsi_channel_reg[NUM_DSI_CHANNEL];
- volatile u32 __iomem *mcde_clkdsi;
- struct dsi_link_registers __iomem *dsi_lnk_registers[NUM_DSI_LINKS];
- volatile u32 __iomem *prcm_mcde_clk;
- volatile u32 __iomem *prcm_hdmi_clk;
- volatile u32 __iomem *prcm_tv_clk;
- dsi_link dsi_lnk_no;
- dsi_link_context dsi_lnk_context;
- struct dsi_link_conf dsi_lnk_conf;
-
- /* Added by QCSPWAN below for "pink display" */
-#ifdef CONFIG_DEBUG_FS
- struct dentry *debugfs_dentry;
- char debugfs_name[10];
-#endif
- /* To serialize access from user space */
- struct semaphore fb_sem;
- /* End QCSPWAN */
-};
-
-
-//volatile mcde_system_context g_mcde_system_context;
-
-#define NUM_TOTAL_MODES ARRAY_SIZE(mcde_modedb)
-
-mcde_error mcdesetdsiclk(dsi_link link, mcde_ch_id chid, mcde_dsi_clk_config clk_config);
-mcde_error mcdesetfifoctrl(dsi_link link, mcde_ch_id chid, struct mcde_fifo_ctrl fifo_ctrl);
-mcde_error mcdesetoutputconf(dsi_link link, mcde_ch_id chid, mcde_output_conf output_conf);
-mcde_error mcdesetdsicommandword(dsi_link link,mcde_ch_id chid,mcde_dsi_channel dsichannel,u8 cmdbyte_lsb,u8 cmdbyte_msb);
-mcde_error mcdesetdsiconf(dsi_link link, mcde_ch_id chid, mcde_dsi_channel dsichannel, mcde_dsi_conf dsi_conf);
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h b/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
deleted file mode 100755
index 1ba82ea0dbb..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_ioctls.h
+++ /dev/null
@@ -1,737 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDE_IOCTLS_H_
-#define _MCDE_IOCTLS_H_
-
-typedef enum
-{
- COLOR_CONV_NONE = 0x0,
- COLOR_CONV_YUV_RGB = 0x1,
- COLOR_CONV_RGB_YUV = 0x2,
- COLOR_CONV_YUV422_YUV444 = 0x3
-}mcde_colorconv_type;
-
-typedef enum
-{
- MCDE_COL_CONV_DISABLE = 0x0,
- MCDE_COL_CONV_NOT_SAT = 0x1,
- MCDE_COL_CONV_SAT = 0x2,
- MCDE_COL_CONV_RESERVED
-}mcde_col_conv_ctrl;
-
-struct mcde_ovr_blend_ctrl
-{
- char alpha_value;
- char ovr_opaq;
- char ovr_blend;
- char ovr_zlevel;
- unsigned int ovr_xpos;
- unsigned int ovr_ypos;
-};
-
-typedef enum
-{
- MCDE_ROTATE_BURST_WORD_1 = 0x0,
- MCDE_ROTATE_BURST_WORD_2 = 0x1,
- MCDE_ROTATE_BURST_WORD_4 = 0x2,
- MCDE_ROTATE_BURST_WORD_8 = 0x3,
- MCDE_ROTATE_BURST_WORD_16 = 0x04,
- MCDE_ROTATE_BURST_WORD_RESERVED
- }mcde_rotate_req;
-
-typedef enum
-{
- MCDE_OUTSTND_REQ_1 = 0x0,
- MCDE_OUTSTND_REQ_2 = 0x1,
- MCDE_OUTSTND_REQ_4 = 0x2,
- MCDE_OUTSTND_REQ_8 = 0x3,
- MCDE_OUTSTND_REQ_16 = 0x4,
- MCDE_OUTSTND_REQ_RESERVED
-}mcde_outsnd_req;
-typedef enum
-{
- MCDE_BURST_WORD_1 = 0x00,
- MCDE_BURST_WORD_2 = 0x01,
- MCDE_BURST_WORD_4 = 0x02,
- MCDE_BURST_WORD_8 = 0x03,
- MCDE_BURST_WORD_16 = 0x04,
- MCDE_BURST_WORD_HW_1 = 0x8,
- MCDE_BURST_WORD_HW_2 = 0x09,
- MCDE_BURST_WORD_HW_4 = 0x0A,
- MCDE_BURST_WORD_HW_8 = 0x0B,
- MCDE_BURST_WORD_HW_16 = 0x0C
-}mcde_burst_req;
-typedef enum
-{
- MCDE_COLOR_KEY_DISABLE = 0x0,
- MCDE_COLOR_KEY_ENABLE = 0x01
-}mcde_color_key_ctrl;
-typedef enum
-{
- MCDE_PAL_GAMA_DISABLE = 0x0,
- MCDE_GAMA_ENABLE = 0x1,
- MCDE_PAL_ENABLE = 0x2,
- MCDE_PAL_GAMA_RESERVED
-}mcde_pal_ctrl;
-typedef enum
-{
- MCDE_OVERLAY_DISABLE = 0x0,
- MCDE_OVERLAY_ENABLE = 0x1
-}mcde_overlay_ctrl;
-typedef enum
-{
- MCDE_PIXEL_ALPHA_SOURCE = 0x0,
- MCDE_CONST_ALPHA_SOURCE = 0x1
-}mcde_blend_ctrl;
-typedef enum
-{
- MCDE_OVR_OPAQUE_DISABLE = 0x0,
- MCDE_OVR_OPAQUE_ENABLE = 0x1
-}mcde_ovr_opq_ctrl;
-typedef enum
-{
- MCDE_OVR_PREMULTIPLIED_ALPHA_DISABLE = 0x0,
- MCDE_OVR_PREMULTIPLIED_ALPHA_ENABLE = 0x1
-}mcde_ovr_alpha_enable;
-typedef enum
-{
- MCDE_OVR_CLIP_DISABLE = 0x0,
- MCDE_OVR_CLIP_ENABLE = 0x1
-}mcde_ovr_clip_enable;
-
-struct mcde_chconfig
-{
- unsigned short lpf;
- unsigned short ppl;
-};
-typedef enum
-{
- MCDE_LCD_TV_0 = 0x0,
- MCDE_LCD_TV_1 = 0x1,
- MCDE_MDIF_IN_0 = 0x2,
- MCDE_MDIF_IN_1 = 0x3,
- MCDE_MDIF_OUT_0 = 0x4,
- MCDE_MDIF_OUT_1 = 0x5
-}mcde_synchro_out_interface;
-typedef enum
-{
- MCDE_SYNCHRO_OUTPUT_SOURCE = 0x0,
- MCDE_SYNCHRO_AUTO = 0x1,
- MCDE_SYNCHRO_SOFTWARE = 0x2,
- MCDE_SYNCHRO_EXTERNAL_SOURCE = 0x3
-}mcde_synchro_source;
-typedef enum
-{
- MCDE_NO_ACTION = 0x0,
- MCDE_NEW_FRAME_SYNCHRO = 0x1
-}mcde_sw_trigger;
-typedef enum
-{
- MCDE_VERTICAL_SYNCHRO = 0x00,
- MCDE_BACK_PORCH = 0x01,
- MCDE_ACTIVE_VIDEO = 0x02,
- MCDE_FRONT_PORCH = 0x03
-}mcde_frame_events;
-struct mcde_ch_bckgrnd_col
-{
- unsigned char red;
- unsigned char green;
- unsigned char blue;
-};
-typedef enum
-{
- MCDE_TVCLK_EXTERNAL = 0x0,
- MCDE_TVCLK_INTERNAL = 0x1
-}mcde_tv_clk;
-typedef enum
-{
- MCDE_PCD_ENABLE = 0x0,
- MCDE_PCD_BYPASS = 0x1
-}mcde_bcd_ctrl;
-typedef enum
-{
- MCDE_BPP_1_TO_8 = 0x0,
- MCDE_BPP_12 = 0x1,
- MCDE_BPP_16 = 0x2,
- MCDE_BPP_18 = 0x3,
- MCDE_BPP_24 = 0x4
-}mcde_out_bpp;
-typedef enum
-{
- MCDE_BUS_16_CONF1 = 0x0,
- MCDE_BUS_16_CONF2 = 0x1,
- MCDE_BUS_16_CONF3 = 0x2,
- MCDE_BUS_18_CONF1 = 0x3,
- MCDE_BUS_18_CONF2 = 0x4,
- MCDE_BUS_24 = 0x5
-}mcde_lcd_bus;
-typedef enum
-{
- MCDE_CLK_STBUS = 0x0,
- MCDE_CLK_72 = 0x1,
- MCDE_CLK_42 = 0x2,
- MCDE_CLK_27 = 0x3,
- MCDE_CLK_TVCLK1 = 0x4,
- MCDE_CLK_TVCLK2 = 0x5
-}mcde_dpi2_clksel;
-
-struct mcde_chx_control1
-{
- mcde_tv_clk tv_clk;
- mcde_bcd_ctrl bcd_ctrl;
- mcde_out_bpp out_bpp;
- unsigned short clk_per_line;
- mcde_lcd_bus lcd_bus;
- mcde_dpi2_clksel dpi2_clk;
- unsigned short pcd;
-};
-typedef enum
-{
- MCDE_CLR_KEY_DISABLE = 0x0,
- MCDE_ALPHA_RGB_KEY = 0x1,
- MCDE_RGB_KEY = 0x2,
- MCDE_FALPHA_FRGB_KEY = 0x4,
- MCDE_FRGB_KEY = 0x5
-}mcde_key_ctrl;
-typedef enum
-{
- MCDE_COLORKEY_NORMAL = 0x0,
- MCDE_COLORKEY_FORCE= 0x1
-}mcde_colorkey_type;
-struct mcde_chx_color_key
-{
- unsigned char alpha;
- unsigned char red;
- unsigned char green;
- unsigned char blue;
-};
-typedef enum
-{
- MCDE_SDTV_656P = 0x0,
- MCDE_HDTV_480P = 0x1,
- MCDE_HDTV_720P = 0x2,
- MCDE_TV_NOTUSED = 0x3,
-}mcde_tvmode;
-typedef enum
-{
- MCDE_ACTIVE_HIGH = 0x0,
- MCDE_ACTIVE_LOW = 0x1
-}mcde_signal_level;
-typedef enum
-{
- MCDE_MODE_LCD = 0x0,
- MCDE_MODE_TV = 0x1
-}mcde_display_mode;
-typedef enum
-{
- MCDE_SCAN_PROGRESSIVE_MODE = 0x0,
- MCDE_SCAN_INTERLACED_MODE = 0x1,
-}mcde_scan_mode;
-
-typedef enum
-{
- MCDE_TV_PAL = 0x0,
- MCDE_TV_NTSC = 0x1,
-}mcde_tv_mode;
-
-struct mcde_chnl_lcd_ctrl_reg
-{
- unsigned short num_lines;
- unsigned short ppl;
- mcde_tvmode tv_mode;
- mcde_signal_level ifield;
- mcde_scan_mode scan_mode;
- mcde_display_mode sel_mode;
-};
-struct mcde_chnl_lcd_horizontal_timing
-{
- unsigned short hbp;
- unsigned short hfp;
- unsigned short hsw;
-};
-struct mcde_chnl_lcd_vertical_timing
-{
- unsigned short vbp;
- unsigned short vfp;
- unsigned short vsw;
-};
-
-typedef enum
-{
- MCDE_ANTIFLICKER_DISABLE = 0x0,
- MCDE_ANTIFLICKER_ENABLE = 0x1
-}mcde_antiflicker_ctrl;
-
-typedef enum
-{
- MCDE_PIXEL_ORDER_LITTLE = 0x0,
- MCDE_PIXEL_ORDER_BIG = 0x1
-}mcde_pixel_order_in_byte;
-
-typedef enum
-{
- MCDE_BYTE_LITTLE = 0x0,
- MCDE_BYTE_BIG = 0x1
-}mcde_byte_endianity;
-
-typedef enum
-{
- MCDE_COL_RGB = 0x0,
- MCDE_COL_BGR = 0x1
-}mcde_rgb_format_sel;
-
-typedef enum
-{
- MCDE_PAL_1_BIT = 0x0,
- MCDE_PAL_2_BIT = 0x1,
- MCDE_PAL_4_BIT = 0x2,
- MCDE_PAL_8_BIT = 0x3,
- MCDE_RGB444_12_BIT = 0x4,
- MCDE_ARGB_16_BIT = 0x5,
- MCDE_IRGB1555_16_BIT = 0x6,
- MCDE_RGB565_16_BIT = 0x7,
- MCDE_RGB_PACKED_24_BIT = 0x8,
- MCDE_RGB_UNPACKED_24_BIT = 0x9,
- MCDE_ARGB_32_BIT =0xA,
- MCDE_YCbCr_8_BIT = 0xB
-}mcde_bpp_ctrl;
-
-typedef enum
-{
- MCDE_OVERLAY_0 = 0x0,
- MCDE_OVERLAY_1 = 0x1,
- MCDE_OVERLAY_2 = 0x2,
- MCDE_OVERLAY_3 = 0x3,
- MCDE_OVERLAY_4 = 0x4,
- MCDE_OVERLAY_5 = 0x5,
- MCDE_OVERLAY_6 = 0x6,
- MCDE_OVERLAY_7 = 0x7
-}mcde_overlay_id;
-
-typedef enum
-{
- MCDE_BUFFER_USED_NONE = 0x0,
- MCDE_BUFFER_USED_1 = 0x1,
- MCDE_BUFFER_USED_2 = 0x2,
- MCDE_BUFFER_USED_3 = 0x3
-}mcde_num_buffer_used;
-
-typedef enum
-{
- MCDE_BUFFER_ID_0 = 0x0,
- MCDE_BUFFER_ID_1 = 0x1,
- MCDE_BUFFER_ID_2 = 0x2,
- MCDE_BUFFER_ID_RESERVED
-}mcde_buffer_id;
-
-typedef enum
-{
- MCDE_MASK_DISABLE = 0x0,
- MCDE_MASK_ENABLE = 0x1
-}mcde_masking_bit_ctrl;
-
-typedef enum
-{
- MCDE_DITHERING_RESET = 0x0,
- MCDE_DITHERING_ACTIVATE = 0x1
-}mcde_dithering_control;
-typedef enum
-{
- MCDE_DITHERING_DISABLE = 0x0,
- MCDE_DITHERING_ENABLE = 0x1
-}mcde_dithering_ctrl;
-struct mcde_chx_dither_ctrl
-{
- unsigned char y_offset;
- unsigned char x_offset;
- mcde_masking_bit_ctrl masking_ctrl;
- unsigned char mode;
- mcde_dithering_ctrl comp_dithering;
- mcde_dithering_ctrl temp_dithering;
-};
-struct mcde_chx_dithering_offset
-{
- unsigned char y_offset_rb;
- unsigned char x_offset_rb;
- unsigned char y_offset_rg;
- unsigned char x_offset_rg;
-};
-
-typedef enum{
- VMODE_640_350_85_P,
- VMODE_640_400_85_P,
- VMODE_720_400_85_P,
- VMODE_640_480_60_P,
- VMODE_640_480_CRT_60_P,
- VMODE_240_320_60_P,
- VMODE_320_240_60_P,
- VMODE_712_568_60_P,
- VMODE_640_480_75_P,
- VMODE_640_480_85_P,
-//#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- VMODE_480_864_60_P,
-//#endif
- VMODE_864_480_60_P,
- VMODE_800_600_56_P,
- VMODE_800_600_60_P,
- VMODE_800_600_72_P,
- VMODE_800_600_75_P,
- VMODE_800_600_85_P,
- VMODE_1024_768_60_P,
- VMODE_1024_768_70_P,
- VMODE_1024_768_75_P,
- VMODE_1024_768_85_P,
- VMODE_1152_864_75_P,
- VMODE_1280_960_60_P,
- VMODE_1280_960_85_P,
- VMODE_1280_1024_60_P,
- VMODE_1280_1024_75_P,
- VMODE_1280_1024_85_P,
- VMODE_1600_1200_60_P,
- VMODE_1600_1200_65_P,
- VMODE_1600_1200_70_P,
- VMODE_1600_1200_75_P,
- VMODE_1600_1200_85_P,
- VMODE_1792_1344_60_P,
- VMODE_1792_1344_75_P,
- VMODE_1856_1392_60_P,
- VMODE_1856_1392_75_P,
- VMODE_1920_1440_60_P,
- VMODE_1920_1440_75_P,
- VMODE_720_480_60_P,
- VMODE_720_480_60_I,
- VMODE_720_576_50_P,
- VMODE_720_576_50_I,
- VMODE_1280_720_50_P,
- VMODE_1280_720_60_P,
- VMODE_1920_1080_50_I,
- VMODE_1920_1080_60_I,
- VMODE_1920_1080_60_P,
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- VMODE_1280_720_24_P,
- VMODE_1280_720_30_P,
- VMODE_1920_1080_24_P,
- VMODE_1920_1080_25_P,
- VMODE_1920_1080_30_P,
-#endif
-}mcde_video_mode;
-/*****************************************************************************
-IOCTLs for access from user space
-*******************************************************************************/
-
-#define MCDE_IOC_MAGIC 'm'
-
-#define MCDE_IOCTL_OVERLAY_CREATE _IOWR(MCDE_IOC_MAGIC, 0x0,struct mcde_overlay_create)
-#define MCDE_IOCTL_OVERLAY_REMOVE _IOR(MCDE_IOC_MAGIC, 0x1,unsigned long)
-#define MCDE_IOCTL_COLOR_KEYING_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x2,struct mcde_channel_color_key)
-#define MCDE_IOCTL_COLOR_KEYING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x3,unsigned long)
-#define MCDE_IOCTL_COLOR_COVERSION_ENABLE _IOWR(MCDE_IOC_MAGIC, 0x4,struct mcde_conf_color_conv)
-#define MCDE_IOCTL_COLOR_COVERSION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x5,unsigned long)
-#define MCDE_IOCTL_ROTATION_ENABLE _IOR(MCDE_IOC_MAGIC, 0x6,unsigned char)
-#define MCDE_IOCTL_ROTATION_DISABLE _IOR(MCDE_IOC_MAGIC, 0x7,unsigned char)
-#define MCDE_IOCTL_SET_VIDEOMODE _IOR(MCDE_IOC_MAGIC, 0x8, unsigned long)
-#define MCDE_IOCTL_ALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0x9,struct mcde_sourcebuffer_alloc)
-#define MCDE_IOCTL_DEALLOC_FRAMEBUFFER _IOWR(MCDE_IOC_MAGIC, 0xA, unsigned long)
-#define MCDE_IOCTL_CONFIGURE_EXTSRC _IOR(MCDE_IOC_MAGIC, 0xB,struct mcde_ext_conf)
-#define MCDE_IOCTL_CONFIGURE_OVRLAY _IOR(MCDE_IOC_MAGIC, 0xC,struct mcde_conf_overlay)
-#define MCDE_IOCTL_CONFIGURE_CHANNEL _IOR(MCDE_IOC_MAGIC, 0xD,struct mcde_ch_conf)
-#define MCDE_IOCTL_CONFIGURE_PANEL _IOR(MCDE_IOC_MAGIC, 0xE,struct mcde_chnl_lcd_ctrl)
-#define MCDE_IOCTL_MCDE_ENABLE _IOR(MCDE_IOC_MAGIC, 0xF,unsigned long)
-#define MCDE_IOCTL_MCDE_DISABLE _IOR(MCDE_IOC_MAGIC, 0x10,unsigned long)
-#define MCDE_IOCTL_CHANNEL_BLEND_ENABLE _IOWR(MCDE_IOC_MAGIC,0x11,struct mcde_blend_control)
-#define MCDE_IOCTL_CHANNEL_BLEND_DISABLE _IOR(MCDE_IOC_MAGIC, 0x12,unsigned long)
-#define MCDE_IOCTL_CONFIGURE_DENC _IOR(MCDE_IOC_MAGIC, 0x13,unsigned long)
-#define MCDE_IOCTL_CONFIGURE_HDMI _IOR(MCDE_IOC_MAGIC, 0x14,unsigned long)
-#define MCDE_IOCTL_SET_SOURCE_BUFFER _IOR(MCDE_IOC_MAGIC, 0x15,struct mcde_source_buffer)
-#define MCDE_IOCTL_DITHERING_ENABLE _IOR(MCDE_IOC_MAGIC, 0x16,struct mcde_dithering_ctrl_conf)
-#define MCDE_IOCTL_DITHERING_DISABLE _IOR(MCDE_IOC_MAGIC, 0x16,unsigned long)
-#define MCDE_IOCTL_ANTIFLICKER_ENABLE _IOR(MCDE_IOC_MAGIC, 0x17,unsigned long)
-#define MCDE_IOCTL_ANTIFLICKER_DISABLE _IOR(MCDE_IOC_MAGIC, 0x18,unsigned long)
-#define MCDE_IOCTL_TEST_DSI_LPMODE _IOR(MCDE_IOC_MAGIC, 0x19,unsigned long)
-#define MCDE_IOCTL_TEST_DSI_HSMODE _IOR(MCDE_IOC_MAGIC, 0x1A,unsigned long)
-#define MCDE_IOCTL_SET_SCAN_MODE _IOWR(MCDE_IOC_MAGIC, 0x1B,unsigned long)
-#define MCDE_IOCTL_GET_SCAN_MODE _IOR(MCDE_IOC_MAGIC, 0x1C,unsigned long)
-
-#define MCDE_IOCTL_TV_PLUG_STATUS _IOR(MCDE_IOC_MAGIC, 0x1D,unsigned long)
-#define MCDE_IOCTL_TV_CHANGE_MODE _IOWR(MCDE_IOC_MAGIC, 0x1E,unsigned long)
-#define MCDE_IOCTL_TV_GET_MODE _IOR(MCDE_IOC_MAGIC, 0x1F,unsigned long)
-
-#define MCDE_IOCTL_REG_DUMP _IOR(MCDE_IOC_MAGIC, 0x20,unsigned long)
-
-/**
- * struct mcde_overlay_create - To create overlay
- * @xorig: frame buffer x-offset
- * @yorig: frame buffer y-offset
- * @xwidth: frame buffer x-width
- * @yheight - frame buffer y-height
- * @bpp: input source bits per pixel
- * @fg: if set then overlay goes to foreground,else remains in background
- * @key: unique framebuffer key returned by driver
- * @bgrinput: if set then implies BGR input
- * @usedefault: if set then uses base overlay buffer
- *
- *
- **/
-struct mcde_overlay_create {
- unsigned long xorig;
- unsigned long yorig;
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
- char fg; /** if set then overlay goes to foreground,else remains in background */
- unsigned long key; /** unique framebuffer key returned by driver */
- unsigned long bgrinput; /** if set then implies BGR input */
- char usedefault; // if set then uses base overlay buffer
-};
-/**
- * struct mcde_addrmap - source frame buffer address map structure
- * @cpuaddr: logical address of the framebuffer
- * @dmaaddr: physical address of the framebuffer
- * @bufflength: buffer length
- *
- *
- **/
-struct mcde_addrmap {
- unsigned long cpuaddr;
- unsigned long dmaaddr;
- unsigned long bufflength;
-};
-/**
- * struct mcde_source_buffer - source frame buffer addresses structure
- * @buff_addr: frame buffer addresses structure
- * @buffid: buffer id
- *
- *
- **/
-struct mcde_source_buffer
-{
- struct mcde_addrmap buffaddr;
- unsigned char buffid;
-};
-/**
- * struct mcde_sourcebuffer_alloc - source frame buffer allocation structure
- * @xwidth: frame buffer x-width
- * @yheight: frame buffer y-height
- * @bpp: input source bits per pixel
- * @doubleBufferingEnabled: double buffer control
- * @key: unique framebuffer key returned by driver
- * @buff_addr: frame buffer addresses structure
- *
- *
- **/
-struct mcde_sourcebuffer_alloc {
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
- char doubleBufferingEnabled;
- unsigned long key; /** unique framebuffer key returned by driver */
- struct mcde_addrmap buff_addr;
-};
-
-/**
- * struct mcde_dithering_ctrl_conf - Structure of overlay configuration
- * @rot_burst_req: rotation burst request
- * @outstnd_req: outstanding request
- * @burst_req: burst request
- * @priority: priority
- * @color_key: color key control
- * @pal_control: pal control
- * @col_ctrl: color conversion control
- * @convert_format: conversion format
- * @ovr_state: overlay control
- * @ovr_ypos: overlay y-position
- * @ovr_xpos: overlay x-position
- * @alpha: alpha control
- * @alpha_value: alpha value
- * @pixoff: pixel offset
- * @ovr_opaq: overlay opaque control
- * @ovr_blend: overlay blend control
- * @watermark_level: watermark level
- * @ovr_zlevel: foreground level
- * @clip: clip control
- * @ytlcoor: clip y-topleft coordinates
- * @xtlcoor: clip x-topleft coordinates
- * @ybrcoor: clip y-bottomright coordinates
- * @xbrcoor: clip x-bottomright coordinates
- * @xwidth: x-width
- * @yheight: y-height
- * @bpp: input bpp
- *
- *
- **/
-struct mcde_conf_overlay {
- mcde_rotate_req rot_burst_req;
- mcde_outsnd_req outstnd_req;
- mcde_burst_req burst_req;
- unsigned char priority;
- mcde_color_key_ctrl color_key;
- mcde_pal_ctrl pal_control;
- mcde_col_conv_ctrl col_ctrl;
- mcde_colorconv_type convert_format;
- mcde_overlay_ctrl ovr_state;
-
- unsigned short ovr_ypos;
- unsigned short ovr_xpos;
-
- mcde_ovr_alpha_enable alpha;
- unsigned char alpha_value;
- unsigned char pixoff;
- mcde_ovr_opq_ctrl ovr_opaq;
- mcde_blend_ctrl ovr_blend;
- unsigned long watermark_level;
- unsigned char ovr_zlevel;
-
- mcde_ovr_clip_enable clip;
- unsigned long ytlcoor;
- unsigned long xtlcoor;
- unsigned long ybrcoor;
- unsigned long xbrcoor;
-
- unsigned long xwidth;
- unsigned long yheight;
- char bpp; /** input source bits per pixel */
-
-};
-/**
- * struct mcde_blend_control - channel configuration structure
- * @chconfig: channel config structure
- * @out_synch_interface: out sync interface
- * @ch_synch_src: channel sync source
- * @sw_trig: software trigger param
- * @swint_vcnt: int count param
- * @swint_vevent: event count param
- * @chbckgrndcolor: channel background color
- * @ch_priority: channel priority
- * @control1: channel control structure
- *
- *
- **/
-struct mcde_ch_conf
-{
- struct mcde_chconfig chconfig;
- mcde_synchro_out_interface out_synch_interface;
- mcde_synchro_source ch_synch_src;
- mcde_sw_trigger sw_trig;
- unsigned short swint_vcnt;
- mcde_frame_events swint_vevent;
- unsigned short hwreq_vcnt;
- mcde_frame_events hwreq_vevent;
- struct mcde_ch_bckgrnd_col chbckgrndcolor;
- unsigned char ch_priority;
- struct mcde_chx_control1 control1;
-};
-/**
- * struct mcde_blend_control - color keying configuration structure
- * @key_ctrl: color key control
- * @color_key_type: color key type
- * @color_key: channel color key structure
- *
- *
- **/
-struct mcde_channel_color_key
-{
- mcde_key_ctrl key_ctrl;
- mcde_colorkey_type color_key_type;
- struct mcde_chx_color_key color_key;
-};
-/**
- * struct mcde_conf_color_conv - color conversion configuration structure
- * @convert_format: convert format type
- * @col_ctrl: color conversion control
- *
- *
- **/
-struct mcde_conf_color_conv
-{
- mcde_colorconv_type convert_format;
- mcde_col_conv_ctrl col_ctrl;
-};
-/**
- * struct mcde_blend_control - blend control configuration structure
- * @blenden: blend enable
- * @blend_ctrl: blend control
- * @alpha_blend: alpha blend
- * @ovr1_id: overlay1 ID
- * @ovr2_id: overlay2 ID
- * @ovr2_enable: overlay2 enable
- * @ovr1_blend_ctrl: overlay1 blend control structure
- * @ovr2_blend_ctrl: overlay2 blend control structure
- *
- *
- **/
-struct mcde_blend_control
-{
- char blenden;
- char blend_ctrl;
- char alpha_blend;
- char ovr1_id;
- char ovr2_id;
- char ovr2_enable;
- struct mcde_ovr_blend_ctrl ovr1_blend_ctrl;
- struct mcde_ovr_blend_ctrl ovr2_blend_ctrl;
-
-};
-/**
- * struct mcde_chnl_lcd_ctrl - LCD control structure
- * @lcd_ctrl_reg: lcd control reg structure
- * @lcd_horizontal_timing: lcd horizontal timing structure
- * @lcd_vertical_timing: lcd vertical timing structure
- *
- *
- **/
-struct mcde_chnl_lcd_ctrl
-{
- struct mcde_chnl_lcd_ctrl_reg lcd_ctrl_reg;
- struct mcde_chnl_lcd_horizontal_timing lcd_horizontal_timing;
- struct mcde_chnl_lcd_vertical_timing lcd_vertical_timing;
-
-};
-/**
- * struct mcde_ext_conf - External source configuration structure
- * @ovr_pxlorder: overlay pixel order
- * @endianity: byte endianity
- * @rgb_format: format type
- * @bpp: input bpp
- * @provr_id: overlay id
- * @buf_num: number of buffers used
- * @buf_id: buffer id to be used
- *
- *
- **/
-struct mcde_ext_conf
-{
- mcde_pixel_order_in_byte ovr_pxlorder;
- mcde_byte_endianity endianity;
- mcde_rgb_format_sel rgb_format;
- mcde_bpp_ctrl bpp;
- mcde_overlay_id provr_id;
- mcde_num_buffer_used buf_num;
- mcde_buffer_id buf_id;
-};
-/**
- * struct mcde_dithering_ctrl_conf - Structure of dithering configuration
- * @dithering_ctrl: dithering control
- * @input_bpp: input bpp
- * @output_bpp: output bpp
- * @mcde_chx_dither_ctrl: structure of dithering control
- * @mcde_chx_dithering_offset: structure of the dithering offset
- *
- *
- **/
-struct mcde_dithering_ctrl_conf
-{
- mcde_dithering_ctrl dithering_ctrl;
- mcde_bpp_ctrl input_bpp;
- mcde_out_bpp output_bpp;
- struct mcde_chx_dither_ctrl mcde_chx_dither_ctrl;
- struct mcde_chx_dithering_offset mcde_chx_dithering_offset;
-};
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/mcde_reg.h b/arch/arm/mach-ux500/include/mach/mcde_reg.h
deleted file mode 100755
index 7b379cd962c..00000000000
--- a/arch/arm/mach-ux500/include/mach/mcde_reg.h
+++ /dev/null
@@ -1,787 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _MCDEREG_H_
-#define _MCDEREG_H_
-
-#include <linux/types.h>
-#include <mach/bit_mask.h>
-
-/*******************************************************************
- MCDE Control Register Fields
-********************************************************************/
-#define MCDE_DISABLE 0x00000000
-#define MCDE_ENABLE 0x80000000
-#define MCDE_SET_BIT 0x1
-#define MCDE_CLEAR_BIT 0x0
-#define MCDE_CTRL_MCDEEN_MASK MASK_BIT31
-#define MCDE_CTRL_MCDEEN_SHIFT 31
-#define MCDE_CTRL_FABMUX_MASK MASK_BIT17
-#define MCDE_CTRL_FABMUX_SHIFT 17
-#define MCDE_CTRL_F01MUX_MASK MASK_BIT16
-#define MCDE_CTRL_F01MUX_SHIFT 16
-#define MCDE_CTRL_IFIFICTRL_MASK MASK_BIT15
-#define MCDE_CTRL_IFIFICTRL_SHIFT 15
-#define MCDE_CTRL_DPIA_EN_MASK MASK_BIT9
-#define MCDE_CTRL_DPIA_EN_SHIFT 9
-#define MCDE_CTRL_DPIB_EN_MASK MASK_BIT8
-#define MCDE_CTRL_DPIB_EN_SHIFT 8
-#define MCDE_CTRL_DBIC0_EN_MASK MASK_BIT7
-#define MCDE_CTRL_DBIC0_EN_SHIFT 7
-#define MCDE_CTRL_DBIC1_EN_MASK MASK_BIT6
-#define MCDE_CTRL_DBIC1_EN_SHIFT 6
-#define MCDE_DSIVID0_EN_MASK MASK_BIT5
-#define MCDE_DSIVID1_EN_MASK MASK_BIT4
-#define MCDE_DSIVID2_EN_MASK MASK_BIT3
-#define MCDE_DSICMD0_EN_MASK MASK_BIT2
-#define MCDE_DSICMD1_EN_MASK MASK_BIT1
-#define MCDE_DSICMD2_EN_MASK MASK_BIT0
-#define MCDE_DSIVID0_EN_SHIFT 5
-#define MCDE_DSIVID1_EN_SHIFT 4
-#define MCDE_DSIVID2_EN_SHIFT 3
-#define MCDE_DSICMD0_EN_SHIFT 2
-#define MCDE_DSICMD1_EN_SHIFT 1
-#define MCDE_SYNCMUX_MASK 0xFF
-#define MCDE_TVA_DPIC0_LCDB_MASK 0x06
-#define MCDE_TVB_DPIC1_LCDA_MASK 0xD4
-#define MCDE_DPIC1_LCDA_MASK 0xF8
-#define MCDE_DPIC0_LCDB_MASK 0x07
-#define MCDE_LCDA_LCDB_MASK 0x00
-#define MCDE_DSI_MASK 0x01
-#define MCDE_OVR_ALPHAPMEN_SHIFT 6
-#define MCDE_OVR_CLIPEN_SHIFT 7
-
-#define MCDE_CFG_OUTMUX4_MASK (MASK_BIT28 | MASK_BIT29 | MASK_BIT30)
-#define MCDE_CFG_OUTMUX3_MASK (MASK_BIT25 | MASK_BIT26 | MASK_BIT27)
-#define MCDE_CFG_OUTMUX2_MASK (MASK_BIT22 | MASK_BIT23 | MASK_BIT24)
-#define MCDE_CFG_OUTMUX1_MASK (MASK_BIT19 | MASK_BIT20 | MASK_BIT21)
-#define MCDE_CFG_OUTMUX0_MASK (MASK_BIT16 | MASK_BIT17 | MASK_BIT18)
-#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_MASK (MASK_BIT12 | MASK_BIT13 | MASK_BIT14)
-#define MCDE_CFG_FSYNCTRLB_MASK MASK_BIT11
-#define MCDE_CFG_FSYNCTRLA_MASK MASK_BIT10
-#define MCDE_CFG_SWAP_B_C1_MASK MASK_BIT9
-#define MCDE_CFG_SWAP_A_C0_MASK MASK_BIT8
-#define MCDE_CFG_SYNCMUX7_MASK MASK_BIT7
-#define MCDE_CFG_SYNCMUX6_MASK MASK_BIT6
-#define MCDE_CFG_SYNCMUX5_MASK MASK_BIT5
-#define MCDE_CFG_SYNCMUX4_MASK MASK_BIT4
-#define MCDE_CFG_SYNCMUX3_MASK MASK_BIT3
-#define MCDE_CFG_SYNCMUX2_MASK MASK_BIT2
-#define MCDE_CFG_SYNCMUX1_MASK MASK_BIT1
-#define MCDE_CFG_SYNCMUX0_MASK MASK_BIT0
-
-#define MCDE_CFG_OUTMUX4_SHIFT 28
-#define MCDE_CFG_OUTMUX3_SHIFT 25
-#define MCDE_CFG_OUTMUX2_SHIFT 22
-#define MCDE_CFG_OUTMUX1_SHIFT 19
-#define MCDE_CFG_OUTMUX0_SHIFT 16
-#define MCDE_CFG_IFIFOCTRLWTRMRKLVL_SHIFT 12
-#define MCDE_CFG_FSYNCTRLB_SHIFT 11
-#define MCDE_CFG_FSYNCTRLA_SHIFT 10
-#define MCDE_CFG_SWAP_B_C1_SHIFT 9
-#define MCDE_CFG_SWAP_A_C0_SHIFT 8
-#define MCDE_CFG_SYNCMUX7_SHIFT 7
-#define MCDE_CFG_SYNCMUX6_SHIFT 6
-#define MCDE_CFG_SYNCMUX5_SHIFT 5
-#define MCDE_CFG_SYNCMUX4_SHIFT 4
-#define MCDE_CFG_SYNCMUX3_SHIFT 3
-#define MCDE_CFG_SYNCMUX2_SHIFT 2
-#define MCDE_CFG_SYNCMUX1_SHIFT 1
-#define MCDE_CFG_SYNCMUX0_SHIFT 0
-
-
-/*******************************************************************
- MCDE External Source Register Fields
-********************************************************************/
-#define MCDE_EXT_BUFFER_MASK /*(MASK_HALFWORD1 | MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3)*/0xFFFFFFFF
-#define MCDE_EXT_PRI_OVR_MASK MASK_QUARTET1
-#define MCDE_EXT_BUFFER_NUM_MASK (MASK_BIT2 | MASK_BIT3)
-#define MCDE_EXT_BUFFER_ID_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_EXT_FORCEFSDIV_MASK MASK_BIT4
-#define MCDE_EXT_FSDISABLE_MASK MASK_BIT3
-#define MCDE_EXT_OVR_CTRL_MASK MASK_BIT2
-#define MCDE_EXT_BUF_MODE_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_EXT_BEPO_MASK MASK_BIT14
-#define MCDE_EXT_BEBO_MASK MASK_BIT13
-#define MCDE_EXT_BGR_MASK MASK_BIT12
-#define MCDE_EXT_BPP_MASK (MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8)
-
-
-#define MCDE_EXT_BUFFER_SHIFT 0
-#define MCDE_EXT_PRI_OVR_SHIFT SHIFT_QUARTET1
-#define MCDE_EXT_BUFFER_NUM_SHIFT 2
-#define MCDE_EXT_OVR_CTRL_SHIFT 2
-#define MCDE_EXT_FORCEFSDIV_SHIFT 4
-#define MCDE_EXT_FSDISABLE_SHIFT 3
-#define MCDE_EXT_BEPO_SHIFT 14
-#define MCDE_EXT_BEBO_SHIFT 13
-#define MCDE_EXT_BGR_SHIFT 12
-#define MCDE_EXT_BPP_SHIFT 8
-/*******************************************************************
- MCDE Overlay Register Fields
-********************************************************************/
-#define MCDE_OVR_OVLEN_MASK MASK_BIT0
-#define MCDE_OVR_COLCTRL_MASK (MASK_BIT1 | MASK_BIT2)
-#define MCDE_OVR_PALCTRL_MASK (MASK_BIT3 | MASK_BIT4)
-#define MCDE_OVR_CKEYEN_MASK (MASK_BIT5)
-#define MCDE_OVR_STBPRIO_MASK MASK_QUARTET4
-#define MCDE_OVR_BURSTSZ_MASK MASK_QUARTET5
-#define MCDE_OVR_MAXREQ_MASK MASK_QUARTET6
-#define MCDE_OVR_ROTBURSTSIZE_MASK MASK_QUARTET7
-#define MCDE_OVR_BLEND_MASK MASK_BIT0
-#define MCDE_OVR_OPQ_MASK MASK_BIT9
-#define MCDE_OVR_INTERMDE_MASK MASK_BIT29
-#define MCDE_OVR_INTERON_MASK MASK_BIT28
-#define MCDE_OVR_ALPHAPMEN_MASK MASK_BIT6
-#define MCDE_OVR_CLIPEN_MASK MASK_BIT7
-#define MCDE_OVR_LPF_MASK (MASK_BYTE2 | MASK_BIT24 |MASK_BIT25 | MASK_BIT26)
-#define MCDE_OVR_PPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_ALPHAVALUE_MASK (MASK_BYTE0 << 1)
-/**#define MCDE_EXT_SRCID_MASK (MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6)*/
-#define MCDE_EXT_SRCID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
-#define MCDE_PIXOFF_MASK (MASK_BIT10 | MASK_BIT11 |MASK_QUARTET3)
-#define MCDE_OVR_ZLEVEL_MASK (MASK_BIT30 | MASK_BIT27 | MASK_BIT28 | MASK_BIT29)
-#define MCDE_OVR_YPOS_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_OVR_CHID_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11)
-#define MCDE_OVR_XPOS_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_OVR_READ_MASK MASK_BIT9
-#define MCDE_OVR_FETCH_MASK MASK_BIT8
-#define MCDE_OVR_BLOCKED_MASK MASK_BIT10
-//#define MCDE_OVR_READ_MASK MASK_BIT1
-//#define MCDE_OVR_FETCH_MASK MASK_BIT0
-#define MCDE_WATERMARK_MASK (MASK_BYTE2 | MASK_QUARTET6 | MASK_BIT28)
-#define MCDE_LINEINCREMENT_MASK 0xFFFFFFFF
-#define MCDE_YCLIP_MASK 0xFFFFFFFF
-#define MCDE_XCLIP_MASK 0xFFFFFFFF
-#define MCDE_XBRCOOR_MASK 0x7FF
-#define MCDE_YBRCOOR_MASK 0x07FF0000
-
-#define MCDE_OVR_COLCTRL_SHIFT 1
-#define MCDE_OVR_PALCTRL_SHIFT 3
-#define MCDE_OVR_CKEYEN_SHIFT 5
-#define MCDE_OVR_STBPRIO_SHIFT SHIFT_QUARTET4
-#define MCDE_OVR_BURSTSZ_SHIFT SHIFT_QUARTET5
-#define MCDE_OVR_MAXREQ_SHIFT SHIFT_QUARTET6
-#define MCDE_OVR_ROTBURSTSIZE_SHIFT SHIFT_QUARTET7
-#define MCDE_OVR_OPQ_SHIFT 9
-#define MCDE_OVR_INTERMDE_SHIFT 29
-#define MCDE_OVR_INTERON_SHIFT 28
-#define MCDE_OVR_LPF_SHIFT SHIFT_HALFWORD1
-#define MCDE_ALPHAVALUE_SHIFT 1
-//#define MCDE_EXT_SRCID_SHIFT 6
-#define MCDE_EXT_SRCID_SHIFT 11
-#define MCDE_OVR_ZLEVEL_SHIFT 27
-#define MCDE_OVR_YPOS_SHIFT SHIFT_HALFWORD1
-#define MCDE_OVR_CHID_SHIFT 11
-#define MCDE_OVR_READ_SHIFT 1
-#define MCDE_WATERMARK_SHIFT SHIFT_HALFWORD1
-#define MCDE_PIXOFF_SHIFT 10
-#define MCDE_LINEINCREMENT_SHIFT 0
-#define MCDE_YCLIP_SHIFT 0
-#define MCDE_XCLIP_SHIFT 0
-#define MCDE_YBRCOOR_SHIFT 16
-
-/*******************************************************************
- MCDE Channel Configuration Register Fields
-********************************************************************/
-#define MCDE_INITDELAY_MASK MASK_HALFWORD1
-#define MCDE_PPDELAY_MASK MASK_HALFWORD0
-#define MCDE_SWINTVCNT_MASK (MASK_BYTE3 | MASK_QUARTET5 | MASK_BIT18 |MASK_BIT19)
-#define MCDE_SWINTVEVENT_MASK (MASK_BIT16 | MASK_BIT17)
-#define MCDE_HWREQVCNT_MASK (MASK_BYTE1 | MASK_QUARTET1 | MASK_BIT3 | MASK_BIT2)
-#define MCDE_HWREQVEVENT_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_OUTINTERFACE_MASK (MASK_BIT4 | MASK_BIT3 |MASK_BIT2)
-#define MCDE_SRCSYNCH_MASK (MASK_BIT0 | MASK_BIT1)
-#define MCDE_SW_TRIG_MASK MASK_BIT0
-#define MCDE_REDCOLOR_MASK MASK_BYTE2
-#define MCDE_GREENCOLOR_MASK MASK_BYTE1
-#define MCDE_BLUECOLOR_MASK MASK_BYTE0
-#define MCDE_CHPRIORITY_MASK MASK_QUARTET0
-#define MCDE_CHXLPF_MASK (0x03FF0000)
-#define MCDE_CHXPPL_MASK (MASK_BYTE0 | MASK_BIT8 |MASK_BIT9 |MASK_BIT10)
-#define MCDE_CHX_ABORT_MASK MASK_BIT1
-#define MCDE_CHX_READ_MASK MASK_BIT0
-
-#define MCDE_INITDELAY_SHIFT SHIFT_HALFWORD1
-#define MCDE_SWINTVCNT_SHIFT 18
-#define MCDE_SWINTVEVENT_SHIFT SHIFT_HALFWORD1
-#define MCDE_HWREQVCNT_SHIFT 2
-#define MCDE_OUTINTERFACE_SHIFT 2
-#define MCDE_REDCOLOR_SHIFT SHIFT_HALFWORD1
-#define MCDE_GREENCOLOR_SHIFT SHIFT_BYTE1
-#define MCDE_CHPRIORITY_SHIFT SHIFT_QUARTET7
-#define MCDE_CHXLPF_SHIFT 16
-#define MCDE_CHX_ABORT_SHIFT 1
-
-/*******************************************************************
- MCDE Channel A/B Register Fields
-********************************************************************/
-#define MCDE_CHX_BURSTSIZE_MASK (MASK_QUARTET6 & 0x07000000)
-#define MCDE_CHX_ALPHA_MASK (MASK_BYTE2)
-#define MCDE_CHX_ROTDIR_MASK (MASK_BIT15)
-#define MCDE_CHX_GAMAEN_MASK (MASK_BIT14)
-#define MCDE_FLICKFORMAT_MASK (MASK_BIT13)
-#define MCDE_FLICKMODE_MASK (MASK_BIT11 | MASK_BIT12)
-#define MCDE_BLENDCONTROL_MASK (MASK_BIT10)
-#define MCDE_KEYCTRL_MASK (MASK_BIT7|MASK_BIT8|MASK_BIT9)
-#define MCDE_ROTEN_MASK (MASK_BIT6)
-#define MCDE_DITHEN_MASK (MASK_BIT5)
-#define MCDE_CEAEN_MASK (MASK_BIT4)
-#define MCDE_AFLICKEN_MASK (MASK_BIT3)
-#define MCDE_BLENDEN_MASK (MASK_BIT2)
-#define MCDE_CLK_MASK (MASK_BIT30)
-#define MCDE_BCD_MASK (MASK_BIT29)
-#define MCDE_OUTBPP_MASK (MASK_BIT25 |MASK_BIT26 | MASK_BIT27 | MASK_BIT28)
-#define MCDE_CDWIN_MASK (MASK_BIT13 | MASK_BIT14 | MASK_BIT15)
-#define MCDE_CLOCKSEL_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
-#define MCDE_PCD_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_KEYA_MASK (MASK_BYTE3)
-#define MCDE_KEYR_MASK (MASK_BYTE2)
-#define MCDE_KEYG_MASK (MASK_BYTE1)
-#define MCDE_KEYB_MASK (MASK_BYTE0)
-#define MCDE_RGB_MASK1 (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
-#define MCDE_RGB_MASK2 (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_THRESHOLD_MASK (MASK_QUARTET6)
-#define MCDE_COEFFN3_MASK (MASK_BYTE2)
-#define MCDE_COEFFN2_MASK (MASK_BYTE1)
-#define MCDE_COEFFN1_MASK (MASK_BYTE0)
-#define MCDE_TV_LINES_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_TVMODE_MASK (MASK_BIT3 | MASK_BIT4)
-#define MCDE_IFIELD_MASK (MASK_BIT2)
-#define MCDE_INTEREN_MASK (MASK_BIT1)
-#define MCDE_SELMODE_MASK (MASK_BIT0)
-#define MCDE_BSL_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_BEL_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_FSL2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_FSL1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_DVO2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_DVO1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_SWH2_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_SWH1_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_SWW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_DHO_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_ALW_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_LBW_MASK (MASK_BYTE0 | MASK_BIT8 | MASK_BIT9 | MASK_BIT10)
-#define MCDE_TVBCR_MASK MASK_BYTE2
-#define MCDE_TVBCB_MASK MASK_BYTE1
-#define MCDE_TVBLU_MASK MASK_BYTE0
-#define MCDE_REVVAEN_MASK MASK_BIT31
-#define MCDE_REVTGEN_MASK MASK_BIT30
-#define MCDE_REVLOADSEL_MASK (MASK_BIT28 | MASK_BIT29)
-#define MCDE_REVDEL1_MASK (MASK_QUARTET6)
-#define MCDE_REVDEL0_MASK (MASK_BYTE2)
-#define MCDE_PSVAEN_MASK (MASK_BIT15)
-#define MCDE_PSTGEN_MASK (MASK_BIT14)
-#define MCDE_PSLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
-#define MCDE_PSDEL1_MASK (MASK_QUARTET2)
-#define MCDE_PSDEL0_MASK (MASK_BYTE0)
-#define MCDE_IOE_MASK (MASK_BIT23)
-#define MCDE_IPC_MASK (MASK_BIT22)
-#define MCDE_IHS_MASK (MASK_BIT21)
-#define MCDE_IVS_MASK (MASK_BIT20)
-#define MCDE_IVP_MASK (MASK_BIT19)
-#define MCDE_ICLSPL_MASK (MASK_BIT18)
-#define MCDE_ICLREV_MASK (MASK_BIT17)
-#define MCDE_ICLSP_MASK (MASK_BIT16)
-#define MCDE_SPLVAEN_MASK (MASK_BIT15)
-#define MCDE_SPLTGEN_MASK (MASK_BIT14)
-#define MCDE_SPLLOADSEL_MASK (MASK_BIT12 | MASK_BIT13)
-#define MCDE_SPLDEL1_MASK (MASK_QUARTET2)
-#define MCDE_SPLDEL0_MASK (MASK_BYTE0)
-#define MCDE_FOFFY_MASK (MASK_BIT14 | MASK_BIT13 | MASK_BIT12 | MASK_BIT11 | MASK_BIT10)
-#define MCDE_FOFFX_MASK (MASK_BIT5 | MASK_BIT6 | MASK_BIT7 | MASK_BIT8 | MASK_BIT9)
-#define MCDE_MASK_BITCTRL_MASK (MASK_BIT4)
-#define MCDE_MODE_MASK (MASK_BIT2 | MASK_BIT3)
-#define MCDE_COMP_MASK (MASK_BIT1)
-#define MCDE_TEMP_MASK (MASK_BIT0)
-#define MCDE_YB_MASK (MASK_BIT28 | MASK_BIT27 | MASK_BIT26 | MASK_BIT25 | MASK_BIT24)
-#define MCDE_XB_MASK (MASK_BIT20 | MASK_BIT19 | MASK_BIT18 | MASK_BIT17 | MASK_BIT16)
-#define MCDE_YG_MASK (MASK_BIT12 | MASK_BIT11 | MASK_BIT10 | MASK_BIT9 | MASK_BIT8 | MASK_BIT7 | MASK_BIT6 | MASK_BIT5)
-#define MCDE_XG_MASK (MASK_BIT0 | MASK_BIT1 | MASK_BIT2 | MASK_BIT3 | MASK_BIT4)
-#define MCDE_ARED_MASK (MASK_BYTE2 | MASK_BIT24 | MASK_BIT25)
-#define MCDE_GREEN_MASK (MASK_BYTE1)
-#define MCDE_BLUE_MASK (MASK_BYTE0)
-#define MCDE_RED_MASK (MASK_BYTE2)
-
-#define MCDE_CHX_BURSTSIZE_SHIFT SHIFT_QUARTET6
-#define MCDE_CHX_ALPHA_SHIFT SHIFT_HALFWORD1
-#define MCDE_CHX_ROTDIR_SHIFT 15
-#define MCDE_CHX_GAMAEN_SHIFT 14
-#define MCDE_FLICKFORMAT_SHIFT 13
-#define MCDE_FLICKMODE_SHIFT 11
-#define MCDE_BLENDCONTROL_SHIFT 10
-#define MCDE_KEYCTRL_SHIFT 7
-#define MCDE_ROTEN_SHIFT 6
-#define MCDE_DITHEN_SHIFT 5
-#define MCDE_CEAEN_SHIFT 4
-#define MCDE_AFLICKEN_SHIFT 3
-#define MCDE_BLENDEN_SHIFT 2
-#define MCDE_CLK_SHIFT 30
-#define MCDE_BCD_SHIFT 29
-#define MCDE_OUTBPP_SHIFT 25
-#define MCDE_CDWIN_SHIFT 13
-#define MCDE_CLOCKSEL_SHIFT 10
-#define MCDE_KEYA_SHIFT SHIFT_BYTE3
-#define MCDE_KEYR_SHIFT SHIFT_BYTE2
-#define MCDE_KEYG_SHIFT SHIFT_BYTE1
-#define MCDE_RGB_SHIFT SHIFT_HALFWORD1
-#define MCDE_THRESHOLD_SHIFT SHIFT_QUARTET6
-#define MCDE_COEFFN3_SHIFT SHIFT_BYTE2
-#define MCDE_COEFFN2_SHIFT SHIFT_BYTE1
-#define MCDE_COEFFN1_SHIFT (SHIFT_BYTE0)
-#define MCDE_TV_LINES_SHIFT SHIFT_HALFWORD1
-#define MCDE_TVMODE_SHIFT 3
-#define MCDE_IFIELD_SHIFT 2
-#define MCDE_INTEREN_SHIFT 1
-#define MCDE_BSL_SHIFT 16
-#define MCDE_FSL2_SHIFT 16
-#define MCDE_DVO2_SHIFT 16
-#define MCDE_SWW_SHIFT 16
-#define MCDE_ALW_SHIFT 16
-#define MCDE_TVBCR_SHIFT SHIFT_BYTE2
-#define MCDE_TVBCB_SHIFT SHIFT_BYTE1
-#define MCDE_REVVAEN_SHIFT 31
-#define MCDE_REVTGEN_SHIFT 30
-#define MCDE_REVLOADSEL_SHIFT 28
-#define MCDE_REVDEL1_SHIFT SHIFT_QUARTET6
-#define MCDE_REVDEL0_SHIFT SHIFT_HALFWORD1
-#define MCDE_PSVAEN_SHIFT 15
-#define MCDE_PSTGEN_SHIFT 14
-#define MCDE_PSLOADSEL_SHIFT 12
-#define MCDE_PSDEL1_SHIFT 8
-#define MCDE_IOE_SHIFT 23
-#define MCDE_IPC_SHIFT 22
-#define MCDE_IHS_SHIFT 21
-#define MCDE_IVS_SHIFT 20
-#define MCDE_IVP_SHIFT 19
-#define MCDE_ICLSPL_SHIFT 18
-#define MCDE_ICLREV_SHIFT 17
-#define MCDE_ICLSP_SHIFT 16
-#define MCDE_SPLVAEN_SHIFT 15
-#define MCDE_SPLTGEN_SHIFT 14
-#define MCDE_SPLLOADSEL_SHIFT 12
-#define MCDE_SPLDEL1_SHIFT 8
-#define MCDE_FOFFY_SHIFT 10
-#define MCDE_FOFFX_SHIFT 5
-#define MCDE_MASK_BITCTRL_SHIFT 4
-#define MCDE_MODE_SHIFT 2
-#define MCDE_COMP_SHIFT 1
-#define MCDE_YB_SHIFT 24
-#define MCDE_XB_SHIFT SHIFT_HALFWORD1
-#define MCDE_YG_SHIFT 5
-#define MCDE_ARED_SHIFT SHIFT_HALFWORD1
-#define MCDE_GREEN_SHIFT SHIFT_BYTE1
-/*******************************************************************
- MCDE Channel C Register Fields
-********************************************************************/
-#define MCDE_SYNCCTRL_MASK (MASK_BIT30 | MASK_BIT29)
-#define MCDE_RESEN_MASK (MASK_BIT18)
-#define MCDE_CLKSEL_MASK (MASK_BIT14 | MASK_BIT13)
-#define MCDE_SYNCSEL_MASK MASK_BIT6
-#define MCDE_RES2_MASK MASK_BIT28
-#define MCDE_RES1_MASK MASK_BIT27
-#define MCDE_RD2_MASK MASK_BIT26
-#define MCDE_RD1_MASK MASK_BIT25
-#define MCDE_WR2_MASK MASK_BIT24
-#define MCDE_WR1_MASK MASK_BIT23
-#define MCDE_CD2_MASK MASK_BIT22
-#define MCDE_CD1_MASK MASK_BIT21
-#define MCDE_CS2_MASK MASK_BIT20
-#define MCDE_CS1_MASK MASK_BIT19
-#define MCDE_CS2EN_MASK MASK_BIT17
-#define MCDE_CS1EN_MASK MASK_BIT16
-#define MCDE_INBAND2_MASK MASK_BIT12
-#define MCDE_INBAND1_MASK MASK_BIT11
-#define MCDE_BUSSIZE2_MASK MASK_BIT10
-#define MCDE_BUSSIZE1_MASK MASK_BIT9
-#define MCDE_SYNCEN2_MASK MASK_BIT8
-#define MCDE_SYNCEN1_MASK MASK_BIT7
-#define MCDE_WMLVL2_MASK MASK_BIT5
-#define MCDE_WMLVL1_MASK MASK_BIT4
-#define MCDE_C2EN_MASK MASK_BIT3
-#define MCDE_C1EN_MASK MASK_BIT2
-#define MCDE_POWEREN_MASK MASK_BIT1
-#define MCDE_FLOEN_MASK MASK_BIT0
-#define MCDE_PDCTRL_MASK (MASK_BIT10 |MASK_BIT11 | MASK_BIT12)
-#define MCDE_DUPLEXER_MASK (MASK_BIT7 |MASK_BIT8 | MASK_BIT9)
-#define MCDE_BSDM_MASK (MASK_BIT6 | MASK_BIT5 | MASK_BIT4)
-#define MCDE_BSCM_MASK (MASK_BIT2 | MASK_BIT1 | MASK_BIT0)
-#define MCDE_VSDBL_MASK (MASK_BIT29 | MASK_BIT30 | MASK_BIT31)
-#define MCDE_VSSEL_MASK MASK_BIT28
-#define MCDE_VSPOL_MASK MASK_BIT27
-#define MCDE_VSPDIV_MASK (MASK_BIT24 | MASK_BIT25 | MASK_BIT26)
-#define MCDE_VSPMAX_MASK (MASK_BYTE2 | MASK_QUARTET3)
-#define MCDE_VSPMIN_MASK (MASK_BYTE0 | MASK_QUARTET2)
-#define MCDE_TRDELC_MASK (MASK_BYTE2 | MASK_QUARTET6)
-#define MCDE_SYNCDELC1_MASK (MASK_BYTE1)
-#define MCDE_SYNCDELC0_MASK (MASK_BYTE0)
-#define MCDE_VSTAC1_MASK MASK_BIT1
-#define MCDE_VSTAC0_MASK MASK_BIT0
-#define MCDE_BCN_MASK MASK_BYTE0
-#define MCDE_CSCDDEACT_MASK MASK_BYTE1
-#define MCDE_CSCDACT_MASK MASK_BYTE0
-#define MCDE_MOTINT_MASK MASK_BIT16
-#define MCDE_RWDEACT_MASK MASK_BYTE1
-#define MCDE_RWACT_MASK MASK_BYTE0
-#define MCDE_DODEACT_MASK MASK_BYTE1
-#define MCDE_DOACT_MASK MASK_BYTE0
-#define MCDE_READDATA_MASK MASK_HALFWORD0
-#define MCDE_DATACOMMANDMASK 0x01FFFFFF
-
-#define MCDE_SYNCCTRL_SHIFT 29
-#define MCDE_RESEN_SHIFT 18
-#define MCDE_CLKSEL_SHIFT 13
-#define MCDE_SYNCSEL_SHIFT 6
-#define MCDE_RES2_SHIFT 28
-#define MCDE_RES1_SHIFT 27
-#define MCDE_RD2_SHIFT 26
-#define MCDE_RD1_SHIFT 25
-#define MCDE_WR2_SHIFT 24
-#define MCDE_WR1_SHIFT 23
-#define MCDE_CD2_SHIFT 22
-#define MCDE_CD1_SHIFT 21
-#define MCDE_CS2_SHIFT 20
-#define MCDE_CS1_SHIFT 19
-#define MCDE_CS2EN_SHIFT 17
-#define MCDE_CS1EN_SHIFT 16
-#define MCDE_INBAND2_SHIFT 12
-#define MCDE_INBAND1_SHIFT 11
-#define MCDE_BUSSIZE2_SHIFT 10
-#define MCDE_BUSSIZE1_SHIFT 9
-#define MCDE_SYNCEN2_SHIFT 8
-#define MCDE_SYNCEN1_SHIFT 7
-#define MCDE_WMLVL2_SHIFT 5
-#define MCDE_WMLVL1_SHIFT 4
-#define MCDE_C2EN_SHIFT 3
-#define MCDE_C1EN_SHIFT 2
-#define MCDE_POWEREN_SHIFT 1
-#define MCDE_PDCTRL_SHIFT 12
-#define MCDE_DUPLEXER_SHIFT 7
-#define MCDE_BSDM_SHIFT 4
-#define MCDE_VSDBL_SHIFT 29
-#define MCDE_VSSEL_SHIFT 28
-#define MCDE_VSPOL_SHIFT 27
-#define MCDE_VSPDIV_SHIFT 24
-#define MCDE_VSPMAX_SHIFT 12
-#define MCDE_TRDELC_SHIFT SHIFT_HALFWORD1
-#define MCDE_SYNCDELC1_SHIFT SHIFT_BYTE1
-#define MCDE_VSTAC1_SHIFT 1
-#define MCDE_CSCDDEACT_SHIFT SHIFT_BYTE1
-#define MCDE_MOTINT_SHIFT SHIFT_HALFWORD1
-#define MCDE_RWDEACT_SHIFT 8
-#define MCDE_DODEACT_SHIFT SHIFT_BYTE1
-
-/*******************************************************************
- MCDE DSI Register Fields
-********************************************************************/
-#define MCDE_PLLOUT_DIVSEL1_MASK (MASK_BIT22 | MASK_BIT23)
-#define MCDE_PLLOUT_DIVSEL0_MASK (MASK_BIT20 | MASK_BIT21)
-#define MCDE_PLL4IN_SEL_MASK (MASK_BIT16 | MASK_BIT17)
-#define MCDE_TXESCDIV_SEL_MASK MASK_BIT8
-#define MCDE_TXESCDIV_MASK 0xFF
-#define MCDE_CMDBYTE_LSB_MASK 0xFF
-#define MCDE_CMDBYTE_MSB_MASK 0xFF00
-#define MCDE_DSI_SW_MASK 0xFFF0000
-#define MCDE_DSI_DMA_MASK 0xFFF
-#define MCDE_DSI_PACK_MASK (MASK_BIT20 | MASK_BIT21 | MASK_BIT22)
-#define MCDE_DSI_DCSVID_MASK MASK_BIT18
-#define MCDE_DSI_BYTE_SWAP_MASK MASK_BIT17
-#define MCDE_DSI_BIT_SWAP_MASK MASK_BIT16
-#define MCDE_DSI_CMD8_MASK MASK_BIT13
-#define MCDE_DSI_VID_MODE_MASK MASK_BIT12
-#define MCDE_BLANKING_MASK MASK_QUARTET0
-#define MCDE_DSI_FRAME_MASK (MASK_HALFWORD0 | MASK_BYTE2)
-#define MCDE_DSI_PACKET_MASK MASK_HALFWORD0
-
-#define MCDE_PLLOUT_DIVSEL1_SHIFT 22
-#define MCDE_PLLOUT_DIVSEL0_SHIFT 20
-#define MCDE_PLL4IN_SEL_SHIFT 16
-#define MCDE_TXESCDIV_SEL_SHIFT 8
-#define MCDE_CMDBYTE_MSB_SHIFT 8
-#define MCDE_DSI_SW_SHIFT 16
-#define MCDE_DSI_PACK_SHIFT 20
-#define MCDE_DSI_DCSVID_SHIFT 18
-#define MCDE_DSI_BYTE_SWAP_SHIFT 17
-#define MCDE_DSI_BIT_SWAP_SHIFT 16
-#define MCDE_DSI_CMD8_SHIFT 13
-#define MCDE_DSI_VID_MODE_SHIFT 12
-
-/*******************************************************************
- Register Structure
-********************************************************************/
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-struct mcde_ext_src_reg
-{
- volatile u32 mcde_extsrc_a0;
- volatile u32 mcde_extsrc_a1;
- volatile u32 mcde_extsrc_a2;
- volatile u32 mcde_extsrc_conf;
- volatile u32 mcde_extsrc_cr;
- volatile u32 mcde_unused1[3];
-};
-
-struct mcde_ovl_reg
-{
- volatile u32 mcde_ovl_cr;
- volatile u32 mcde_ovl_conf;
- volatile u32 mcde_ovl_conf2;
- volatile u32 mcde_ovl_ljinc;
- volatile u32 mcde_ovl_crop;
- volatile u32 mcde_ovl_comp;
- volatile u32 mcde_unused1[2];
-};
-
-struct mcde_chnl_conf_reg
-{
- volatile u32 mcde_chnl_conf;
- volatile u32 mcde_chnl_stat;
- volatile u32 mcde_chnl_synchmod;
- volatile u32 mcde_chnl_synchsw;
- volatile u32 mcde_chnl_bckgndcol;
- volatile u32 mcde_chnl_prio;
- volatile u32 mcde_unused[2];
-};
-
-struct mcde_chAB_reg
-{
- volatile u32 mcde_cr0;
- volatile u32 mcde_cr1;
- volatile u32 mcde_colkey;
- volatile u32 mcde_fcolkey;
- volatile u32 mcde_rgbconv1;
- volatile u32 mcde_rgbconv2;
- volatile u32 mcde_rgbconv3;
- volatile u32 mcde_rgbconv4;
- volatile u32 mcde_rgbconv5;
- volatile u32 mcde_rgbconv6;
- volatile u32 mcde_ffcoef0;
- volatile u32 mcde_ffcoef1;
- volatile u32 mcde_ffcoef2;
- volatile u32 mcde_unused1[1];
- volatile u32 mcde_tvcr;
- volatile u32 mcde_tvbl1;
- volatile u32 mcde_tvisl;
- volatile u32 mcde_tvdvo;
- volatile u32 mcde_unused2[1];
- volatile u32 mcde_tvtim1;
- volatile u32 mcde_tvlbalw;
- volatile u32 mcde_tvbl2;
- volatile u32 mcde_tvblu;
- volatile u32 mcde_lcdtim0;
- volatile u32 mcde_lcdtim1;
- volatile u32 mcde_ditctrl;
- volatile u32 mcde_ditoff;
- volatile u32 mcde_pal0;
- volatile u32 mcde_pal1;
- volatile u32 mcde_rotadd0;
- volatile u32 mcde_rotadd1;
- volatile u32 mcde_rot_conf;
- volatile u32 mcde_synchconf;
- volatile u32 mcde_unused3[1];
- volatile u32 mcde_gam0;
- volatile u32 mcde_gam1;
- volatile u32 mcde_gam2;
- volatile u32 mcde_oledconv1;
- volatile u32 mcde_oledconv2;
- volatile u32 mcde_oledconv3;
- volatile u32 mcde_oledconv4;
- volatile u32 mcde_oledconv5;
- volatile u32 mcde_oledconv6;
- volatile u32 mcde_unused4[85];
-};
-
-struct mcde_chC0C1_reg
-{
- volatile u32 mcde_crc;
- volatile u32 mcde_pbccrc[2];
- volatile u32 mcde_pbcbmrc0[5];
- volatile u32 mcde_pbcbmrc1[5];
- volatile u32 mcde_pbcbcrc0[2];
- volatile u32 mcde_unused1[3];
- volatile u32 mcde_pbcbcrc1[2];
- volatile u32 mcde_unused2[3];
- volatile u32 mcde_vscrc[2];
- volatile u32 mcde_sctrc;
- volatile u32 mcde_scsrc;
- volatile u32 mcde_bcnr[2];
- volatile u32 mcde_cscdtr[2];
- volatile u32 mcde_rdwrtr[2];
- volatile u32 mcde_dotr[2];
- volatile u32 mcde_wcmdc[2];
- volatile u32 mcde_wdatadc[2];
- volatile u32 mcde_rdatadc[2];
- volatile u32 mcde_statc;
- volatile u32 mcde_ctrlc[2];
-};
-
-struct mcde_dsi_reg
-{
- volatile u32 mcde_dsi_conf0;
- volatile u32 mcde_dsi_frame;
- volatile u32 mcde_dsi_pkt;
- volatile u32 mcde_dsi_sync;
- volatile u32 mcde_dsi_cmdw;
- volatile u32 mcde_dsi_delay0;
- volatile u32 mcde_dsi_delay1;
- volatile u32 mcde_unused1[1];
-};
-
-struct mcde_top_reg
-{
- volatile u32 mcde_cr;
- volatile u32 mcde_conf0;
- volatile u32 mcde_ssp;
- volatile u32 mcde_reserved1[61];
- volatile u32 mcde_ais;
- volatile u32 mcde_imscpp;
- volatile u32 mcde_imscovl;
- volatile u32 mcde_imscchnl;
- volatile u32 mcde_imscerr;
- volatile u32 mcde_rispp;
- volatile u32 mcde_risovl;
- volatile u32 mcde_rischnl;
- volatile u32 mcde_riserr;
- volatile u32 mcde_mispp;
- volatile u32 mcde_misovl;
- volatile u32 mcde_mischnl;
- volatile u32 mcde_miserr;
- volatile u32 mcde_sispp;
- volatile u32 mcde_sisovl;
- volatile u32 mcde_sischnl;
- volatile u32 mcde_siserr;
- volatile u32 mcde_reserved2[46];
- volatile u32 mcde_pid;
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-struct mcde_ext_src_reg
-{
- volatile u32 mcde_extsrc_a0;
- volatile u32 mcde_extsrc_a1;
- volatile u32 mcde_extsrc_a2;
- volatile u32 mcde_extsrc_conf;
- volatile u32 mcde_extsrc_cr;
- volatile u32 mcde_unused1[3];
-};
-
-struct mcde_ovl_reg
-{
- volatile u32 mcde_ovl_cr;
- volatile u32 mcde_ovl_conf;
- volatile u32 mcde_ovl_conf2;
- volatile u32 mcde_ovl_ljinc;
- volatile u32 mcde_ovl_crop;
- volatile u32 mcde_ovl_top_left_clip;
- volatile u32 mcde_ovl_bot_rht_clip;
- volatile u32 mcde_ovl_comp;
-};
-
-struct mcde_ch_synch_reg
-{
- volatile u32 mcde_ch_conf;
- volatile u32 mcde_ch_stat;
- volatile u32 mcde_chsyn_mod;
- volatile u32 mcde_chsyn_sw;
- volatile u32 mcde_chsyn_bck;
- volatile u32 mcde_chsyn_prio;
- volatile u32 mcde_unused3[2];
-};
-
-struct mcde_ch_reg
-{
- volatile u32 mcde_ch_cr0;
- volatile u32 mcde_ch_cr1;
- volatile u32 mcde_ch_colkey;
- volatile u32 mcde_ch_fcolkey;
- volatile u32 mcde_ch_rgbconv1;
- volatile u32 mcde_ch_rgbconv2;
- volatile u32 mcde_ch_rgbconv3;
- volatile u32 mcde_ch_rgbconv4;
- volatile u32 mcde_ch_rgbconv5;
- volatile u32 mcde_ch_rgbconv6;
- volatile u32 mcde_ch_ffcoef0;
- volatile u32 mcde_ch_ffcoef1;
- volatile u32 mcde_ch_ffcoef2;
- volatile u32 unused;
- volatile u32 mcde_ch_tvcr;
- volatile u32 mcde_ch_tvbl1;
- volatile u32 mcde_ch_tvisl;
- volatile u32 mcde_ch_tvdvo;
- volatile u32 mcde_ch_tvswh;
- volatile u32 mcde_ch_tvtim1;
- volatile u32 mcde_ch_tvbalw;
- volatile u32 mcde_ch_tvbl2;
- volatile u32 mcde_ch_tvblu;
- volatile u32 mcde_ch_lcdtim0;
- volatile u32 mcde_ch_lcdtim1;
- volatile u32 mcde_ch_ditctrl;
- volatile u32 mcde_ch_ditoff;
- volatile u32 mcde_ch_pal;
- volatile u32 mcde_ch_gam;
- volatile u32 mcde_rotadd0;
- volatile u32 mcde_rotadd1;
- volatile u32 mcde_chsyn_con;
- volatile u32 mcde_unused7[96];
-};
-
-struct mcde_dsi_reg
-{
- volatile u32 mcde_dsi_conf0;
- volatile u32 mcde_dsi_frame;
- volatile u32 mcde_dsi_pkt;
- volatile u32 mcde_dsi_sync;
- volatile u32 mcde_dsi_cmd;
- volatile u32 mcde_reserved2[3];
-};
-
-struct mcde_chc_reg
-{
- volatile u32 mcde_chc_crc;
- volatile u32 mcde_chc_pbcrc0;
- volatile u32 mcde_chc_pbcrc1;
- volatile u32 mcde_chc_pbcbmrc0[5];
- volatile u32 mcde_chc_pbcbmrc1[5];
- volatile u32 mcde_chc_pbcbcrc0[2];
- volatile u32 mcde_unused5[3];
- volatile u32 mcde_chc_pbcbcrc1[2];
- volatile u32 mcde_unused6[3];
- volatile u32 mcde_chc_vscrc[2];
- volatile u32 mcde_chc_sctrc;
- volatile u32 mcde_chc_scsr;
- volatile u32 mcde_chc_bcnr[2];
- volatile u32 mcde_chc_cscdtr[2];
- volatile u32 mcde_chc_rdwrtr[2];
- volatile u32 mcde_chc_dotr[2];
- volatile u32 mcde_chc_wcmd[2];
- volatile u32 mcde_chc_wd[2];
- volatile u32 mcde_chc_rdata[2];
-};
-
-struct mcde_register_base
-{
- volatile u32 mcde_cr;
- volatile u32 mcde_cfg0;
- volatile u32 mcde_reserved1[62];
- volatile u32 mcde_ais;
- volatile u32 mcde_imsc;
- volatile u32 mcde_ris;
- volatile u32 mcde_mis;
- volatile u32 mcde_sis;
- volatile u32 mcde_ssi;
- volatile u32 mcde_reserved2[57];
- volatile u32 mcde_pid;
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-#endif
diff --git a/arch/arm/mach-ux500/mcde.c b/arch/arm/mach-ux500/mcde.c
index ede2bf310ec..b7b5991cbff 100644
--- a/arch/arm/mach-ux500/mcde.c
+++ b/arch/arm/mach-ux500/mcde.c
@@ -1,777 +1,81 @@
/*
- * Copyright (C) 2010 ST Ericsson
+ * Copyright (C) ST-Ericsson AB 2010
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
+ * MOP500/HREF500 ed/v1 Display platform devices
+ *
+ * Author: Marcus Lorentzon <marcus.xm.lorentzon@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
*/
-
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/devices.h>
#include <mach/hardware.h>
-#include <mach/mcde.h>
-#include <mach/mcde_common.h>
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
-/* Channel C0 */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde2_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_top",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC0_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC0_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chc0_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chc0c1_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_CHANNEL_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [12] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde2_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC0_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC0_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chc0_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde2_channel_data = {
- .channelid = CHANNEL_C0,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- .restype = CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC0_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC0_INPUT_BGR,
-#else
- .restype = "WVGA",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-};
-
-struct platform_device u8500_mcde2_device = {
- .name = "U8500-MCDE",
- .id = 2,
- .dev = {
- .init_name = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde2_channel_data,
- },
- .num_resources = ARRAY_SIZE(mcde2_resources),
- .resource = mcde2_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC0 */
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
-/* Channel C1 */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde3_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_top",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC1_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC1_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chc1_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELC0C1_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chc0c1_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
- [11] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [12] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde3_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELC1_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELC1_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chc1_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNELC_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
+#include <mach/irqs.h>
+#include <video/mcde.h>
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde3_channel_data = {
- .channelid = CHANNEL_C1,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- .restype = CONFIG_FB_U8500_MCDE_CHANNELC1_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELC1_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELC1_INPUT_BGR,
-#else
- .restype = "WVGA",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-};
-
-struct platform_device u8500_mcde3_device = {
- .name = "U8500-MCDE",
- .id = 3,
- .dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde3_channel_data,
- },
-
- .num_resources = ARRAY_SIZE(mcde3_resources),
- .resource = mcde3_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELC1 */
-
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
-/* Channel B */
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-
-static struct resource mcde1_resources[] = {
+static struct resource mcde_resources[] = {
[0] = {
+ .name = MCDE_IO_AREA,
.start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_base",
+ .end = U8500_MCDE_BASE + 0x1000 - 1, /* TODO: Fix size */
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELB_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELB_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_chb_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
+ .name = MCDE_IO_AREA,
.start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde1_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
+ .end = U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
+ .name = MCDE_IO_AREA,
+ .start = U8500_DSI_LINK2_BASE,
+ .end = U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
- .start = U8500_MCDE_CHANNELB_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELB_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "chb_config",
+ .name = MCDE_IO_AREA,
+ .start = U8500_DSI_LINK3_BASE,
+ .end = U8500_DSI_LINK3_BASE + U8500_DSI_LINK_SIZE - 1,
.flags = IORESOURCE_MEM,
},
[4] = {
- .start = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELB_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "chb_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
+ .name = MCDE_IRQ,
.start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
+ .end = IRQ_DISP,
+ .flags = IORESOURCE_IRQ,
},
};
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
+static void dev_release_noop(struct device *dev)
+{
+ /* Do nothing */
+}
-static struct mcde_channel_data mcde1_channel_data = {
- .channelid = CHANNEL_B,
- .nopan = 1,
- .nowrap = 1,
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- .restype = CONFIG_FB_U8500_MCDE_CHANNELB_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELB_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELB_INPUT_BGR,
-#else
- .restype = "PAL",
- .inbpp = 16,
- .outbpp = 0x2,
- .bpp16_type = 1,
- .bgrinput = 0x0,
-#endif
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
- .gpio_alt_func = GPIO_ALT_LCD_PANELB
-#else
- .gpio_alt_func = GPIO_ALT_LCD_PANELB_ED
-#endif
+static struct mcde_platform_data mcde_pdata = {
+ .num_dsilinks = 3,
+ /* YCbCr to AB8500 on D[8:15]: connect LSB Ch B */
+ .outmux = { 0, 3, 0, 0, 0 },
+ .syncmux = 0x01,
+ .regulator_id = "v-ana",
+ .clock_dsi_id = "hdmi",
+ .clock_dsi_lp_id = "tv",
+ .clock_mcde_id = "mcde",
};
-struct platform_device u8500_mcde1_device = {
- .name = "U8500-MCDE",
- .id = 1,
+struct platform_device ux500_mcde_device = {
+ .name = "mcde",
+ .id = -1,
.dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde1_channel_data,
+ .release = dev_release_noop,
+ .platform_data = &mcde_pdata,
},
- .num_resources = ARRAY_SIZE(mcde1_resources),
- .resource = mcde1_resources
+ .num_resources = ARRAY_SIZE(mcde_resources),
+ .resource = mcde_resources,
};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELB */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
-/* Channel A */
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-static struct resource mcde0_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_BASE_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVERLAY_BASE,
- .end = U8500_MCDE_OVERLAY_BASE + (U8500_MCDE_OVERLAY_SIZE - 1),
- .name = "mcde_overlay",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELA_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELA_CONFIG_BASE + (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "mcde_cha_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE + (U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_SIZE - 1),
- .name = "mcde_cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE + ((U8500_DSI_LINK_SIZE * U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#else /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct resource mcde0_resources[] = {
- [0] = {
- .start = U8500_MCDE_BASE,
- .end = U8500_MCDE_BASE + (U8500_MCDE_REGISTER_SIZE - 1),
- .name = "mcde_base",
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = U8500_MCDE_EXTSRC_BASE,
- .end = U8500_MCDE_EXTSRC_BASE + (U8500_MCDE_EXTSRC_SIZE - 1),
- .name = "mcde_extsrc_base",
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = U8500_MCDE_OVL_BASE,
- .end = U8500_MCDE_OVL_BASE + (U8500_MCDE_OVL_SIZE - 1),
- .name = "mcde_overlay_base",
- .flags = IORESOURCE_MEM,
- },
- [3] = {
- .start = U8500_MCDE_CHANNELA_CONFIG_BASE,
- .end = U8500_MCDE_CHANNELA_CONFIG_BASE +
- (U8500_MCDE_CHANNEL_CONFIG_SIZE - 1),
- .name = "cha_config",
- .flags = IORESOURCE_MEM,
- },
- [4] = {
- .start = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE,
- .end = U8500_MCDE_CHANNELA_SPECIFIC_REGISTER_BASE +
- (U8500_MCDE_CHANNEL_SPECIFIC_REGISTER_SIZE - 1),
- .name = "cha_specific",
- .flags = IORESOURCE_MEM,
- },
- [5] = {
- .start = U8500_MCDE_DSI_CHANNEL_BASE,
- .end = U8500_MCDE_DSI_CHANNEL_BASE + (U8500_MCDE_DSI_SIZE - 1),
- .name = "mcde_dsi_channel_base",
- .flags = IORESOURCE_MEM,
- },
- [6] = {
- .start = U8500_DSI_LINK1_BASE,
- .end = U8500_DSI_LINK1_BASE +
- ((U8500_DSI_LINK_SIZE*U8500_DSI_LINK_COUNT) - 1),
- .name = "dsi_link_base",
- .flags = IORESOURCE_MEM,
- },
- [7] = {
- .start = PRCM_MCDECLK_MGT_REG,
- .end = PRCM_MCDECLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_mcde_clk",
- .flags = IORESOURCE_MEM,
- },
- [8] = {
- .start = PRCM_HDMICLK_MGT_REG,
- .end = PRCM_HDMICLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_hdmi_clk",
- .flags = IORESOURCE_MEM,
- },
- [9] = {
- .start = PRCM_TVCLK_MGT_REG,
- .end = PRCM_TVCLK_MGT_REG + (sizeof(u32) - 1),
- .name = "prcm_tv_clk",
- .flags = IORESOURCE_MEM,
- },
- [10] = {
- .start = IRQ_DISP,
- .end = IRQ_DISP,
- .name = "mcde_irq",
- .flags = IORESOURCE_IRQ
- },
-};
-
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
-static struct mcde_channel_data mcde0_channel_data = {
- .channelid = CHANNEL_A,
- .nopan = 1,
- .nowrap = 1,
- .restype = CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_TYPE,
- .inbpp = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BPP,
- .outbpp = CONFIG_FB_U8500_MCDE_CHANNELA_OUTPUT_BPP,
- .bpp16_type = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_16BPP_TYPE,
- .bgrinput = CONFIG_FB_U8500_MCDE_CHANNELA_INPUT_BGR,
- .gpio_alt_func = GPIO_ALT_LCD_PANELA
-};
-struct platform_device u8500_mcde0_device = {
- .name = "U8500-MCDE",
- .id = 0,
- .dev = {
- .bus_id = "mcde_bus",
- .coherent_dma_mask = ~0,
- .platform_data = &mcde0_channel_data,
- },
- .num_resources = ARRAY_SIZE(mcde0_resources),
- .resource = mcde0_resources
-};
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA */
diff --git a/arch/arm/mach-ux500/mop500-regulators.c b/arch/arm/mach-ux500/mop500-regulators.c
index 4b1cea6a14c..977d54b67e6 100644
--- a/arch/arm/mach-ux500/mop500-regulators.c
+++ b/arch/arm/mach-ux500/mop500-regulators.c
@@ -59,30 +59,10 @@ static struct platform_device db8500_vape_regulator_dev = {
#define U8500_VANA_REGULATOR_MAX_VOLTAGE (1200000)
static struct regulator_consumer_supply db8500_vana_consumers[] = {
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
{
- .dev = &u8500_mcde0_device.dev,
+ .dev = &ux500_mcde_device.dev,
.supply = "v-ana",
},
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
- {
- .dev = &u8500_mcde1_device.dev,
- .supply = "v-ana",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- {
- .dev = &u8500_mcde2_device.dev,
- .supply = "v-ana",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- {
- .dev = &u8500_mcde3_device.dev,
- .supply = "v-ana",
- },
-#endif
};
static struct regulator_init_data db8500_vana_init = {
@@ -117,30 +97,10 @@ extern struct platform_device sensors1p_device;
#define AB8500_VAUXN_LDO_MAX_VOLTAGE (3300000)
static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA
- {
- .dev = &u8500_mcde0_device.dev,
- .supply = "v-mcde",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELB
{
- .dev = &u8500_mcde1_device.dev,
- .supply = "v-mcde",
+ .dev = NULL,
+ .supply = "v-display",
},
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0
- {
- .dev = &u8500_mcde2_device.dev,
- .supply = "v-mcde",
- },
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC1
- {
- .dev = &u8500_mcde3_device.dev,
- .supply = "v-mcde",
- },
-#endif
#ifdef CONFIG_SENSORS1P_MOP
{
.dev = &sensors1p_device.dev,
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 976f1d9c586..fac781ca65e 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -399,5 +399,6 @@ source "drivers/misc/i2s/Kconfig"
source "drivers/misc/msw/Kconfig"
source "drivers/misc/shrm/Kconfig"
source "drivers/misc/audio_io_dev/Kconfig"
+source "drivers/misc/ab8500_denc/Kconfig"
endif # MISC_DEVICES
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 044ab6f6b07..5883fa81501 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -39,4 +39,5 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500_gpadc.o
obj-$(CONFIG_ISA_HSI_MODEM) += msw/
obj-$(CONFIG_U8500_SHRM) += shrm/
obj-$(CONFIG_STE_IRRC) += irrc.o
+obj-$(CONFIG_AB8500_DENC) += ab8500_denc/
obj-$(CONFIG_STE_AUDIO_IO_DEV) += audio_io_dev/
diff --git a/drivers/misc/ab8500_denc/Kconfig b/drivers/misc/ab8500_denc/Kconfig
new file mode 100755
index 00000000000..b47bd8d1c51
--- /dev/null
+++ b/drivers/misc/ab8500_denc/Kconfig
@@ -0,0 +1,6 @@
+config AB8500_DENC
+ tristate "AB8500_DENC driver support(CVBS)"
+ depends on AB8500
+ default n
+ help
+ Please enable this feature if tvout driver support is required.
diff --git a/drivers/misc/ab8500_denc/Makefile b/drivers/misc/ab8500_denc/Makefile
new file mode 100755
index 00000000000..ccd5cc99951
--- /dev/null
+++ b/drivers/misc/ab8500_denc/Makefile
@@ -0,0 +1,4 @@
+# Make file for compiling and loadable module HDMI
+
+obj-$(CONFIG_AB8500_DENC) += ab8500_denc.o
+
diff --git a/drivers/misc/ab8500_denc/ab8500_denc.c b/drivers/misc/ab8500_denc/ab8500_denc.c
new file mode 100644
index 00000000000..d96286b9202
--- /dev/null
+++ b/drivers/misc/ab8500_denc/ab8500_denc.c
@@ -0,0 +1,620 @@
+/*
+ * Copyright (C) ST-Ericsson AB 2010
+ *
+ * ST-Ericsson AB8500 DENC base driver
+ *
+ * Author: Marcel Tunnissen <marcel.tuennissen@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/uaccess.h>
+#include <mach/ab8500.h>
+
+#include "ab8500_denc_regs.h"
+#include <video/mcde_display-ab8500.h>
+#include <mach/ab8500_denc.h>
+
+#define AB8500_NAME "ab8500"
+#define AB8500_DENC_NAME "ab8500_denc"
+
+#define AB8500_REG_BANK_NR(__reg) ((0xff00 & (__reg)) >> 8)
+static inline u8 ab8500_rreg(u32 reg)
+{
+ return ab8500_read(AB8500_REG_BANK_NR(reg), reg);
+}
+static inline void ab8500_wreg(u32 reg, u8 val)
+{
+ ab8500_write(AB8500_REG_BANK_NR(reg), reg, val);
+}
+
+#define ab8500_set_fld(__cur_val, __reg, __fld, __val) \
+ (((__cur_val) & ~__reg##_##__fld##_MASK) |\
+ (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK))
+
+#define ab8500_wr_fld(__reg, __fld, __val) \
+ ab8500_wreg(__reg, \
+ ((ab8500_rreg(__reg) & ~__reg##_##__fld##_MASK) |\
+ (((__val) << __reg##_##__fld##_SHIFT) &\
+ __reg##_##__fld##_MASK)))
+
+#define AB8500_DENC_TRACE pr_debug("%s\n", __func__)
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *debugfs_ab8500_denc_dir;
+static struct dentry *debugfs_ab8500_dump_regs_file;
+static struct dentry *debugfs_ab8500_reg_offs_file;
+static struct dentry *debugfs_ab8500_regval_file;
+static u32 ab8500_debugfs_reg_nr;
+static void ab8500_denc_conf_ddr(void);
+static int debugfs_ab8500_open_file(struct inode *inode, struct file *file);
+static int debugfs_ab8500_dump_regs(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos);
+static ssize_t debugfs_ab8500_write_file_dummy(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos);
+static int debugfs_ab8500_read_reg_offs(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos);
+static int debugfs_ab8500_write_reg_offs(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos);
+static int debugfs_ab8500_read_regval(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos);
+static ssize_t debugfs_ab8500_write_regval(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos);
+
+static const struct file_operations debugfs_ab8500_dump_regs_fops = {
+ .owner = THIS_MODULE,
+ .open = debugfs_ab8500_open_file,
+ .read = debugfs_ab8500_dump_regs,
+ .write = debugfs_ab8500_write_file_dummy
+};
+
+static const struct file_operations debugfs_ab8500_reg_offs_fops = {
+ .owner = THIS_MODULE,
+ .open = debugfs_ab8500_open_file,
+ .read = debugfs_ab8500_read_reg_offs,
+ .write = debugfs_ab8500_write_reg_offs
+};
+
+static const struct file_operations debugfs_ab8500_regval_fops = {
+ .owner = THIS_MODULE,
+ .open = debugfs_ab8500_open_file,
+ .read = debugfs_ab8500_read_regval,
+ .write = debugfs_ab8500_write_regval
+};
+#endif /* CONFIG_DEBUG_FS */
+
+static void setup_27mhz(bool enable);
+static u32 map_tv_std(enum ab8500_denc_TV_std std);
+static u32 map_cr_filter(enum ab8500_denc_cr_filter_bandwidth bw);
+static u32 map_phase_rst_mode(enum ab8500_denc_phase_reset_mode mode);
+static u32 map_plug_time(enum ab8500_denc_plug_time time);
+
+static struct platform_device *ab8500_denc_dev;
+
+static int __devinit ab8500_denc_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct ab8500_denc_platform_data *pdata = pdev->dev.platform_data;
+
+ if (pdata == NULL) {
+ dev_err(&pdev->dev, "Platform data missing\n");
+ ret = -EINVAL;
+ goto no_pdata;
+ }
+
+ ab8500_denc_dev = pdev;
+ AB8500_DENC_TRACE; /* note this needs ab8500_denc_dev to be set */
+
+#ifdef CONFIG_DEBUG_FS
+ debugfs_ab8500_denc_dir = debugfs_create_dir(pdev->name, NULL);
+ debugfs_ab8500_reg_offs_file = debugfs_create_file(
+ "regoffset", S_IWUGO | S_IRUGO,
+ debugfs_ab8500_denc_dir, 0,
+ &debugfs_ab8500_reg_offs_fops
+ );
+ debugfs_ab8500_regval_file = debugfs_create_file(
+ "regval", S_IWUGO | S_IRUGO,
+ debugfs_ab8500_denc_dir, 0,
+ &debugfs_ab8500_regval_fops
+ );
+ debugfs_ab8500_dump_regs_file = debugfs_create_file(
+ "dumpregs", S_IRUGO,
+ debugfs_ab8500_denc_dir, 0,
+ &debugfs_ab8500_dump_regs_fops
+ );
+#endif /* CONFIG_DEBUG_FS */
+out:
+ return ret;
+
+no_pdata:
+ goto out;
+}
+
+static void setup_27mhz(bool enable)
+{
+ u8 data = ab8500_rreg(AB8500_SYS_ULP_CLK_CONF);
+
+ AB8500_DENC_TRACE;
+ /* TODO: check if this field needs to be set */
+ data = ab8500_set_fld(data, AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_PD_ENA,
+ true);
+ data = ab8500_set_fld(data, AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_BUF_ENA,
+ enable);
+ data = ab8500_set_fld(data, AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_INV,
+ false);
+ data = ab8500_set_fld(data, AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_DE_IN,
+ false);
+ data = ab8500_set_fld(data, AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_STRE,
+ 1);
+ ab8500_wreg(AB8500_SYS_ULP_CLK_CONF, data);
+
+ data = ab8500_rreg(AB8500_SYS_CLK_CTRL);
+ data = ab8500_set_fld(data, AB8500_SYS_CLK_CTRL, TVOUT_CLK_VALID,
+ enable);
+ data = ab8500_set_fld(data, AB8500_SYS_CLK_CTRL, TVOUT_PLL_ENA,
+ enable);
+ ab8500_wreg(AB8500_SYS_CLK_CTRL, data);
+}
+
+static u32 map_tv_std(enum ab8500_denc_TV_std std)
+{
+ switch (std) {
+ case TV_STD_PAL_BDGHI:
+ return AB8500_DENC_CONF0_STD_PAL_BDGHI;
+ case TV_STD_PAL_N:
+ return AB8500_DENC_CONF0_STD_PAL_N;
+ case TV_STD_PAL_M:
+ return AB8500_DENC_CONF0_STD_PAL_M;
+ case TV_STD_NTSC_M:
+ return AB8500_DENC_CONF0_STD_NTSC_M;
+ default:
+ return 0;
+ }
+}
+
+static u32 map_cr_filter(enum ab8500_denc_cr_filter_bandwidth bw)
+{
+ switch (bw) {
+ case TV_CR_NTSC_LOW_DEF_FILTER:
+ return AB8500_DENC_CONF1_FLT_1_1MHZ;
+ case TV_CR_PAL_LOW_DEF_FILTER:
+ return AB8500_DENC_CONF1_FLT_1_3MHZ;
+ case TV_CR_NTSC_HIGH_DEF_FILTER:
+ return AB8500_DENC_CONF1_FLT_1_6MHZ;
+ case TV_CR_PAL_HIGH_DEF_FILTER:
+ return AB8500_DENC_CONF1_FLT_1_9MHZ;
+ default:
+ return 0;
+ }
+}
+
+static u32 map_phase_rst_mode(enum ab8500_denc_phase_reset_mode mode)
+{
+ switch (mode) {
+ case TV_PHASE_RST_MOD_DISABLE:
+ return AB8500_DENC_CONF8_PH_RST_MODE_DISABLED;
+ case TV_PHASE_RST_MOD_FROM_PHASE_BUF:
+ return AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_PHASE_BUF;
+ case TV_PHASE_RST_MOD_FROM_INC_DFS:
+ return AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_INC_DFS;
+ case TV_PHASE_RST_MOD_RST:
+ return AB8500_DENC_CONF8_PH_RST_MODE_RESET;
+ default:
+ return 0;
+ }
+}
+
+static u32 map_plug_time(enum ab8500_denc_plug_time time)
+{
+ switch (time) {
+ case TV_PLUG_TIME_0_5S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_0_5S;
+ case TV_PLUG_TIME_1S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_1S;
+ case TV_PLUG_TIME_1_5S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_1_5S;
+ case TV_PLUG_TIME_2S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_2S;
+ case TV_PLUG_TIME_2_5S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_2_5S;
+ case TV_PLUG_TIME_3S:
+ return AB8500_TVOUT_CTRL_PLUG_TV_TIME_3S;
+ default:
+ return 0;
+ }
+}
+
+static int __devexit ab8500_denc_remove(struct platform_device *pdev)
+{
+ AB8500_DENC_TRACE;
+#ifdef CONFIG_DEBUG_FS
+ debugfs_remove(debugfs_ab8500_dump_regs_file);
+ debugfs_remove(debugfs_ab8500_regval_file);
+ debugfs_remove(debugfs_ab8500_reg_offs_file);
+ debugfs_remove(debugfs_ab8500_denc_dir);
+#endif /* CONFIG_DEBUG_FS */
+
+ ab8500_denc_dev = NULL;
+
+ return 0;
+}
+
+static struct platform_driver ab8500_denc_driver = {
+ .probe = ab8500_denc_probe,
+ .remove = ab8500_denc_remove,
+ .driver = {
+ .name = "ab8500_denc",
+ },
+};
+
+void ab8500_denc_reset(bool hard)
+{
+ AB8500_DENC_TRACE;
+ if (hard) {
+ u8 data = ab8500_rreg(AB8500_CTRL3);
+ /* reset start */
+ ab8500_wreg(AB8500_CTRL3,
+ ab8500_set_fld(data, AB8500_CTRL3, RESET_DENC_N, 0)
+ );
+ /* reset done */
+ ab8500_wreg(AB8500_CTRL3,
+ ab8500_set_fld(data, AB8500_CTRL3, RESET_DENC_N, 1)
+ );
+ } else {
+ ab8500_wr_fld(AB8500_DENC_CONF6, SOFT_RESET, 1);
+ mdelay(10);
+ }
+}
+EXPORT_SYMBOL(ab8500_denc_reset);
+
+void ab8500_denc_power_up(void)
+{
+ setup_27mhz(true);
+}
+EXPORT_SYMBOL(ab8500_denc_power_up);
+
+void ab8500_denc_power_down(void)
+{
+ setup_27mhz(false);
+}
+EXPORT_SYMBOL(ab8500_denc_power_down);
+
+void ab8500_denc_regu_setup(bool enable_v_tv, bool enable_lp_mode)
+{
+ u8 data = ab8500_rreg(AB8500_REGU_MISC1);
+
+ AB8500_DENC_TRACE;
+ data = ab8500_set_fld(data, AB8500_REGU_MISC1, V_TVOUT_LP,
+ enable_lp_mode);
+ data = ab8500_set_fld(data, AB8500_REGU_MISC1, V_TVOUT_ENA,
+ enable_v_tv);
+ ab8500_wreg(AB8500_REGU_MISC1, data);
+}
+EXPORT_SYMBOL(ab8500_denc_regu_setup);
+
+void ab8500_denc_conf(struct ab8500_denc_conf *conf)
+{
+ u8 data;
+
+ AB8500_DENC_TRACE;
+
+ ab8500_wreg(AB8500_DENC_CONF0,
+ AB8500_VAL2REG(AB8500_DENC_CONF0, STD, map_tv_std(conf->TV_std))
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF0, SYNC,
+ conf->test_pattern ? AB8500_DENC_CONF0_SYNC_AUTO_TEST :
+ AB8500_DENC_CONF0_SYNC_F_BASED_SLAVE
+ )
+ );
+ ab8500_wreg(AB8500_DENC_CONF1,
+ AB8500_VAL2REG(AB8500_DENC_CONF1, BLK_LI,
+ !conf->partial_blanking)
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF1, FLT,
+ map_cr_filter(conf->cr_filter))
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF1, CO_KI, conf->suppress_col)
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF1, SETUP_MAIN,
+ conf->black_level_setup)
+ /* TODO: handle cc field: set to 0 now */
+ );
+
+ data = ab8500_rreg(AB8500_DENC_CONF2);
+ data = ab8500_set_fld(data, AB8500_DENC_CONF2, N_INTRL,
+ conf->progressive);
+ ab8500_wreg(AB8500_DENC_CONF2, data);
+
+ ab8500_wreg(AB8500_DENC_CONF8,
+ AB8500_VAL2REG(AB8500_DENC_CONF8, PH_RST_MODE,
+ map_phase_rst_mode(conf->phase_reset_mode))
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF8, VAL_422_MUX,
+ conf->act_output)
+ |
+ AB8500_VAL2REG(AB8500_DENC_CONF8, BLK_ALL,
+ conf->blank_all)
+ );
+ data = ab8500_rreg(AB8500_TVOUT_CTRL);
+ data = ab8500_set_fld(data, AB8500_TVOUT_CTRL, DAC_CTRL0,
+ conf->dac_enable);
+ data = ab8500_set_fld(data, AB8500_TVOUT_CTRL, DAC_CTRL1,
+ conf->act_dc_output);
+ ab8500_wreg(AB8500_TVOUT_CTRL, data);
+
+ /* no support for DDR in early versions */
+ if (AB8500_REG2VAL(AB8500_REV, FULL_MASK, ab8500_rreg(AB8500_REV)) > 0)
+ ab8500_denc_conf_ddr();
+}
+EXPORT_SYMBOL(ab8500_denc_conf);
+
+void ab8500_denc_conf_plug_detect(bool enable, bool load_RC,
+ enum ab8500_denc_plug_time time)
+{
+ u8 data = ab8500_rreg(AB8500_TVOUT_CTRL);
+
+ AB8500_DENC_TRACE;
+ data = ab8500_set_fld(data, AB8500_TVOUT_CTRL, TV_PLUG_ON, enable);
+ data = ab8500_set_fld(data, AB8500_TVOUT_CTRL, TV_LOAD_RC, load_RC);
+ data = ab8500_set_fld(data, AB8500_TVOUT_CTRL, PLUG_TV_TIME,
+ map_plug_time(time));
+ ab8500_wreg(AB8500_TVOUT_CTRL, data);
+}
+EXPORT_SYMBOL(ab8500_denc_conf_plug_detect);
+
+void ab8500_denc_mask_int_plug_det(bool plug, bool unplug)
+{
+ u8 data = ab8500_rreg(AB8500_IT_MASK1);
+
+ AB8500_DENC_TRACE;
+ data = ab8500_set_fld(data, AB8500_IT_MASK1, PLUG_TV_DET, plug);
+ data = ab8500_set_fld(data, AB8500_IT_MASK1, UNPLUG_TV_DET, unplug);
+ ab8500_wreg(AB8500_IT_MASK1, data);
+}
+EXPORT_SYMBOL(ab8500_denc_mask_int_plug_det);
+
+static void ab8500_denc_conf_ddr(void)
+{
+ struct ab8500_denc_platform_data *pdata;
+
+ AB8500_DENC_TRACE;
+ if (ab8500_denc_dev) {
+ pdata = (struct ab8500_denc_platform_data *)
+ ab8500_denc_dev->dev.platform_data;
+ ab8500_wreg(AB8500_TVOUT_CTRL2,
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL2,
+ DENC_DDR, pdata->ddr_enable)
+ |
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL2, SWAP_DDR_DATA_IN,
+ pdata->ddr_little_endian)
+ );
+ }
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int debugfs_ab8500_open_file(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static ssize_t debugfs_ab8500_write_file_dummy(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ return count;
+}
+
+static int debugfs_ab8500_dump_regs(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos)
+{
+ int ret = 0;
+ size_t data_size = 0;
+ char buffer[PAGE_SIZE];
+
+ data_size += sprintf(buffer + data_size,
+ "AB8500 DENC registers:\n"
+ "CTRL3 : 0x%04x = 0x%02x\n"
+ "SYSULPCLK_CONF: 0x%04x = 0x%02x\n"
+ "SYSCLK_CTRL : 0x%04x = 0x%02x\n"
+ "REGU_MISC1 : 0x%04x = 0x%02x\n"
+ "VAUX12_REGU : 0x%04x = 0x%02x\n"
+ "VAUX1_SEL1 : 0x%04x = 0x%02x\n"
+ "DENC_CONF0 : 0x%04x = 0x%02x\n"
+ "DENC_CONF1 : 0x%04x = 0x%02x\n"
+ "DENC_CONF2 : 0x%04x = 0x%02x\n"
+ "DENC_CONF6 : 0x%04x = 0x%02x\n"
+ "DENC_CONF8 : 0x%04x = 0x%02x\n"
+ "TVOUT_CTRL : 0x%04x = 0x%02x\n"
+ "TVOUT_CTRL2 : 0x%04x = 0x%02x\n"
+ "IT_MASK1 : 0x%04x = 0x%02x\n"
+ ,
+ AB8500_CTRL3, ab8500_rreg(AB8500_CTRL3),
+ AB8500_SYS_ULP_CLK_CONF, ab8500_rreg(AB8500_SYS_ULP_CLK_CONF),
+ AB8500_SYS_CLK_CTRL, ab8500_rreg(AB8500_SYS_CLK_CTRL),
+ AB8500_REGU_MISC1, ab8500_rreg(AB8500_REGU_MISC1),
+ AB8500_VAUX12_REGU, ab8500_rreg(AB8500_VAUX12_REGU),
+ AB8500_VAUX1_SEL, ab8500_rreg(AB8500_VAUX1_SEL),
+ AB8500_DENC_CONF0, ab8500_rreg(AB8500_DENC_CONF0),
+ AB8500_DENC_CONF1, ab8500_rreg(AB8500_DENC_CONF1),
+ AB8500_DENC_CONF2, ab8500_rreg(AB8500_DENC_CONF2),
+ AB8500_DENC_CONF6, ab8500_rreg(AB8500_DENC_CONF6),
+ AB8500_DENC_CONF8, ab8500_rreg(AB8500_DENC_CONF8),
+ AB8500_TVOUT_CTRL, ab8500_rreg(AB8500_TVOUT_CTRL),
+ AB8500_TVOUT_CTRL2, ab8500_rreg(AB8500_TVOUT_CTRL2),
+ AB8500_IT_MASK1, ab8500_rreg(AB8500_IT_MASK1)
+ );
+ if (data_size > PAGE_SIZE) {
+ printk(KERN_EMERG "AB8500 DENC: Buffer overrun\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* check if read done */
+ if (*f_pos > data_size)
+ goto out;
+
+ if (*f_pos + count > data_size)
+ count = data_size - *f_pos;
+
+ if (copy_to_user(buf, buffer + *f_pos, count))
+ ret = -EINVAL;
+ *f_pos += count;
+ ret = count;
+out:
+ return ret;
+}
+
+static int debugfs_ab8500_read_reg_offs(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos)
+{
+ int ret = 0;
+ size_t data_size = 0;
+ char buffer[PAGE_SIZE];
+
+ data_size = sprintf(buffer, "0x%08x\n", ab8500_debugfs_reg_nr);
+
+ if (data_size > PAGE_SIZE) {
+ printk(KERN_EMERG "AB8500 DENC: Buffer overrun\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* check if read done */
+ if (*f_pos > data_size)
+ goto out;
+
+ if (*f_pos + count > data_size)
+ count = data_size - *f_pos;
+
+ if (copy_to_user(buf, buffer + *f_pos, count))
+ ret = -EINVAL;
+ *f_pos += count;
+ ret = count;
+
+out:
+ return ret;
+}
+
+static int debugfs_ab8500_write_reg_offs(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ int buf_size;
+ u32 i;
+ char buf[16] = {0};
+
+ buf_size = min(count, (sizeof(buf)-1));
+ if (copy_from_user(buf, ubuf, buf_size))
+ goto error;
+
+ if (sscanf(buf, "0x%x", &i) <= 0)
+ goto error;
+
+ ab8500_debugfs_reg_nr = i;
+
+ return count;
+error:
+ return -EINVAL;
+}
+
+static int debugfs_ab8500_read_regval(struct file *file, char __user *buf,
+ size_t count, loff_t *f_pos)
+{
+ int ret = 0;
+ size_t data_size = 0;
+ char buffer[PAGE_SIZE];
+ u8 bank = 0;
+
+ bank = 0xF & (ab8500_debugfs_reg_nr >> 8);
+ data_size = sprintf(buffer, "0x%02x\n",
+ ab8500_read(bank, ab8500_debugfs_reg_nr));
+
+ if (data_size > PAGE_SIZE) {
+ printk(KERN_EMERG "AB8500 DENC: Buffer overrun\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* check if read done */
+ if (*f_pos > data_size)
+ goto out;
+
+ if (*f_pos + count > data_size)
+ count = data_size - *f_pos;
+
+ if (copy_to_user(buf, buffer + *f_pos, count))
+ ret = -EINVAL;
+ *f_pos += count;
+ ret = count;
+
+out:
+ return ret;
+}
+
+static ssize_t debugfs_ab8500_write_regval(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ int buf_size;
+ char buf[16] = {0};
+ u8 r = 0x0;
+ u8 bank = 0;
+
+ buf_size = min(count, (sizeof(buf)-1));
+ if (copy_from_user(buf, ubuf, buf_size))
+ goto error;
+
+ if (sscanf(buf, "0x%hhx", &r) <= 0)
+ goto error;
+
+ bank = 0xF & (ab8500_debugfs_reg_nr >> 8);
+
+ printk(KERN_DEBUG
+ "AB8500: write to bank 0x%02x, address: 0x%08x: 0x%02x\n",
+ bank,
+ ab8500_debugfs_reg_nr,
+ r);
+ printk(KERN_DEBUG "; old value 0x%02x\n",
+ ab8500_read(bank, ab8500_debugfs_reg_nr));
+
+ ab8500_write(bank, ab8500_debugfs_reg_nr, r);
+
+ printk(KERN_DEBUG "AB8500: write reg: new value 0x%02x\n",
+ ab8500_read(bank, ab8500_debugfs_reg_nr));
+
+ return count;
+error:
+ return -EINVAL;
+}
+
+#endif /* CONFIG_DEBUG_FS */
+
+/* Module init */
+static int __init ab8500_denc_init(void)
+{
+ return platform_driver_register(&ab8500_denc_driver);
+}
+module_init(ab8500_denc_init);
+
+static void __exit ab8500_denc_exit(void)
+{
+ platform_driver_unregister(&ab8500_denc_driver);
+}
+module_exit(ab8500_denc_exit);
+
+MODULE_AUTHOR("Marcel Tunnissen <marcel.tuennissen@stericsson.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ST-Ericsson AB8500 DENC driver");
diff --git a/drivers/misc/ab8500_denc/ab8500_denc_regs.h b/drivers/misc/ab8500_denc/ab8500_denc_regs.h
new file mode 100644
index 00000000000..284fb9ec195
--- /dev/null
+++ b/drivers/misc/ab8500_denc/ab8500_denc_regs.h
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * ST-Ericsson AB8500 DENC related registers
+ *
+ * Author: Marcus Tunnissen <marcel.tuennissen@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#define AB8500_VAL2REG(__reg, __fld, __val) \
+ (((__val) << __reg##_##__fld##_SHIFT) & __reg##_##__fld##_MASK)
+#define AB8500_REG2VAL(__reg, __fld, __val) \
+ (((__val) & __reg##_##__fld##_MASK) >> __reg##_##__fld##_SHIFT)
+
+#define AB8500_CTRL3 0x00000200
+#define AB8500_CTRL3_TH_SD_ENA_SHIFT 3
+#define AB8500_CTRL3_TH_SD_ENA_MASK 0x00000008
+#define AB8500_CTRL3_TH_SD_ENA(__x) \
+ AB8500_VAL2REG(AB8500_CTRL3, TH_SD_ENA, __x)
+#define AB8500_CTRL3_RESET_DENC_N_SHIFT 2
+#define AB8500_CTRL3_RESET_DENC_N_MASK 0x00000004
+#define AB8500_CTRL3_RESET_DENC_N(__x) \
+ AB8500_VAL2REG(AB8500_CTRL3, RESET_DENC_N, __x)
+#define AB8500_CTRL3_RESET_AUD_N_SHIFT 1
+#define AB8500_CTRL3_RESET_AUD_N_MASK 0x00000002
+#define AB8500_CTRL3_RESET_AUD_N(__x) \
+ AB8500_VAL2REG(AB8500_CTRL3, RESET_AUD_N, __x)
+#define AB8500_CTRL3_CLK_32K_OUT2_IS_SHIFT 0
+#define AB8500_CTRL3_CLK_32K_OUT2_IS_MASK 0x00000001
+#define AB8500_CTRL3_CLK_32K_OUT2_IS(__x) \
+ AB8500_VAL2REG(AB8500_CTRL3, CLK_32K_OUT2_IS, __x)
+#define AB8500_SYS_ULP_CLK_CONF 0x0000020A
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA_SHIFT 7
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA_MASK 0x00000080
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_PD_ENA(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_PD_ENA, __x)
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA_SHIFT 6
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA_MASK 0x00000040
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_BUF_ENA(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_BUF_ENA, __x)
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE_SHIFT 5
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE_MASK 0x00000020
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_STRE(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, ULP_CLK_STRE, __x)
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV_SHIFT 4
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV_MASK 0x00000010
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_INV(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_INV, __x)
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN_SHIFT 3
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN_MASK 0x00000008
+#define AB8500_SYS_ULP_CLK_CONF_TVOUT_CLK_DE_IN(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, TVOUT_CLK_DE_IN, __x)
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE_SHIFT 2
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE_MASK 0x00000004
+#define AB8500_SYS_ULP_CLK_CONF_CLK_27MHZ_STRE(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, CLK_27MHZ_STRE, __x)
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_SHIFT 0
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_MASK 0x00000003
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_NO_FUNC 0
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_AS_OUTPUT 1
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_AS_INPUT 2
+#define AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF(__x) \
+ AB8500_VAL2REG(AB8500_SYS_ULP_CLK_CONF, ULP_CLK_CONF, \
+ AB8500_SYS_ULP_CLK_CONF_ULP_CLK_CONF_##__x)
+#define AB8500_SYS_CLK_CTRL 0x0000020C
+#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID_SHIFT 2
+#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID_MASK 0x00000004
+#define AB8500_SYS_CLK_CTRL_USB_CLK_VALID(__x) \
+ AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, USB_CLK_VALID, __x)
+#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID_SHIFT 1
+#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID_MASK 0x00000002
+#define AB8500_SYS_CLK_CTRL_TVOUT_CLK_VALID(__x) \
+ AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, TVOUT_CLK_VALID, __x)
+#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA_SHIFT 0
+#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA_MASK 0x00000001
+#define AB8500_SYS_CLK_CTRL_TVOUT_PLL_ENA(__x) \
+ AB8500_VAL2REG(AB8500_SYS_CLK_CTRL, TVOUT_PLL_ENA, __x)
+#define AB8500_REGU_MISC1 0x00000380
+#define AB8500_REGU_MISC1_V_TVOUT_LP_SHIFT 7
+#define AB8500_REGU_MISC1_V_TVOUT_LP_MASK 0x00000080
+#define AB8500_REGU_MISC1_V_TVOUT_LP(__x) \
+ AB8500_VAL2REG(AB8500_REGU_MISC1, V_TVOUT_LP, __x)
+#define AB8500_REGU_MISC1_V_INT_CORE_12_LP_SHIFT 6
+#define AB8500_REGU_MISC1_V_INT_CORE_12_LP_MASK 0x00000040
+#define AB8500_REGU_MISC1_V_INT_CORE_12_LP(__x) \
+ AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_LP, __x)
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_SHIFT 3
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_MASK 0x00000038
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_2V 0
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_225V 1
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_25V 2
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_275V 3
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_3V 4
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_325V 5
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL_1_35V 6
+#define AB8500_REGU_MISC1_V_INT_CORE_12_SEL(__x) \
+ AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_SEL, \
+ AB8500_REGU_MISC1_V_INT_CORE_12_SEL_##__x)
+#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA_SHIFT 2
+#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA_MASK 0x00000004
+#define AB8500_REGU_MISC1_V_INT_CORE_12_ENA(__x) \
+ AB8500_VAL2REG(AB8500_REGU_MISC1, V_INT_CORE_12_ENA, __x)
+#define AB8500_REGU_MISC1_V_TVOUT_ENA_SHIFT 1
+#define AB8500_REGU_MISC1_V_TVOUT_ENA_MASK 0x00000002
+#define AB8500_REGU_MISC1_V_TVOUT_ENA(__x) \
+ AB8500_VAL2REG(AB8500_REGU_MISC1, V_TVOUT_ENA, __x)
+#define AB8500_VAUX12_REGU 0x00000409
+#define AB8500_VAUX12_REGU_VAUX_1_SHIFT 2
+#define AB8500_VAUX12_REGU_VAUX_1_MASK 0x0000000C
+#define AB8500_VAUX12_REGU_VAUX_1_DISABLE 0
+#define AB8500_VAUX12_REGU_VAUX_1_FORCE_HP 1
+#define AB8500_VAUX12_REGU_VAUX_1_BY_CTRL_REG 2
+#define AB8500_VAUX12_REGU_VAUX_1_FORCE_LP 3
+#define AB8500_VAUX12_REGU_VAUX_1(__x) \
+ AB8500_VAL2REG(AB8500_VAUX12_REGU, VAUX_1, \
+ AB8500_VAUX12_REGU_VAUX_1_##__x)
+#define AB8500_VAUX12_REGU_VAUX_2_SHIFT 0
+#define AB8500_VAUX12_REGU_VAUX_2_MASK 0x00000003
+#define AB8500_VAUX12_REGU_VAUX_2_DISABLE 0
+#define AB8500_VAUX12_REGU_VAUX_2_FORCE_HP 1
+#define AB8500_VAUX12_REGU_VAUX_2_BY_CTRL_REG 2
+#define AB8500_VAUX12_REGU_VAUX_2_FORCE_LP 3
+#define AB8500_VAUX12_REGU_VAUX_2(__x) \
+ AB8500_VAL2REG(AB8500_VAUX12_REGU, VAUX_2, \
+ AB8500_VAUX12_REGU_VAUX_2_##__x)
+#define AB8500_VAUX1_SEL 0x0000041F
+#define AB8500_VAUX1_SEL_VAL_SHIFT 0
+#define AB8500_VAUX1_SEL_VAL_MASK 0x0000000F
+#define AB8500_VAUX1_SEL_VAL_1_1V 0
+#define AB8500_VAUX1_SEL_VAL_1_2V 1
+#define AB8500_VAUX1_SEL_VAL_1_3V 2
+#define AB8500_VAUX1_SEL_VAL_1_4V 3
+#define AB8500_VAUX1_SEL_VAL_1_5V 4
+#define AB8500_VAUX1_SEL_VAL_1_8V 5
+#define AB8500_VAUX1_SEL_VAL_1_85V 6
+#define AB8500_VAUX1_SEL_VAL_1_9V 7
+#define AB8500_VAUX1_SEL_VAL_2_5V 8
+#define AB8500_VAUX1_SEL_VAL_2_65V 9
+#define AB8500_VAUX1_SEL_VAL_2_7V 10
+#define AB8500_VAUX1_SEL_VAL_2_75V 11
+#define AB8500_VAUX1_SEL_VAL_2_8V 12
+#define AB8500_VAUX1_SEL_VAL_2_9V 13
+#define AB8500_VAUX1_SEL_VAL_3_0V 14
+#define AB8500_VAUX1_SEL_VAL_3_3V 15
+#define AB8500_VAUX1_SEL_VAL(__x) \
+ AB8500_VAL2REG(AB8500_VAUX1_SEL, VAL, AB8500_VAUX1_SEL_VAL_##__x)
+#define AB8500_DENC_CONF0 0x00000600
+#define AB8500_DENC_CONF0_STD_SHIFT 6
+#define AB8500_DENC_CONF0_STD_MASK 0x000000C0
+#define AB8500_DENC_CONF0_STD_PAL_BDGHI 0
+#define AB8500_DENC_CONF0_STD_PAL_N 1
+#define AB8500_DENC_CONF0_STD_NTSC_M 2
+#define AB8500_DENC_CONF0_STD_PAL_M 3
+#define AB8500_DENC_CONF0_STD(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF0, STD, AB8500_DENC_CONF0_STD_##__x)
+#define AB8500_DENC_CONF0_SYNC_SHIFT 3
+#define AB8500_DENC_CONF0_SYNC_MASK 0x00000038
+#define AB8500_DENC_CONF0_SYNC_F_BASED_SLAVE 1
+#define AB8500_DENC_CONF0_SYNC_AUTO_TEST 7
+#define AB8500_DENC_CONF0_SYNC(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF0, SYNC, AB8500_DENC_CONF0_SYNC_##__x)
+#define AB8500_DENC_CONF1 0x00000601
+#define AB8500_DENC_CONF1_BLK_LI_SHIFT 7
+#define AB8500_DENC_CONF1_BLK_LI_MASK 0x00000080
+#define AB8500_DENC_CONF1_BLK_LI_PARTIAL 0
+#define AB8500_DENC_CONF1_BLK_LI_FULL 1
+#define AB8500_DENC_CONF1_BLK_LI(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF1, BLK_LI, \
+ AB8500_DENC_CONF1_BLK_LI_##__x)
+#define AB8500_DENC_CONF1_FLT_SHIFT 5
+#define AB8500_DENC_CONF1_FLT_MASK 0x00000060
+#define AB8500_DENC_CONF1_FLT_1_1MHZ 0
+#define AB8500_DENC_CONF1_FLT_1_3MHZ 1
+#define AB8500_DENC_CONF1_FLT_1_6MHZ 2
+#define AB8500_DENC_CONF1_FLT_1_9MHZ 3
+#define AB8500_DENC_CONF1_FLT(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF1, FLT, AB8500_DENC_CONF1_FLT_##__x)
+#define AB8500_DENC_CONF1_CO_KI_SHIFT 3
+#define AB8500_DENC_CONF1_CO_KI_MASK 0x00000008
+#define AB8500_DENC_CONF1_CO_KI(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF1, CO_KI, __x)
+#define AB8500_DENC_CONF1_SETUP_MAIN_SHIFT 2
+#define AB8500_DENC_CONF1_SETUP_MAIN_MASK 0x00000004
+#define AB8500_DENC_CONF1_SETUP_MAIN_BLACK_EQ_BLANK 0
+#define AB8500_DENC_CONF1_SETUP_MAIN_BLACK_GT_BLANK 1
+#define AB8500_DENC_CONF1_SETUP_MAIN(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF1, SETUP_MAIN, \
+ AB8500_DENC_CONF1_SETUP_MAIN_##__x)
+#define AB8500_DENC_CONF1_CC_SHIFT 0
+#define AB8500_DENC_CONF1_CC_MASK 0x00000003
+#define AB8500_DENC_CONF1_CC_NONE 0
+#define AB8500_DENC_CONF1_CC_FIELD_1 1
+#define AB8500_DENC_CONF1_CC_FIELD_2 2
+#define AB8500_DENC_CONF1_CC_ALL 3
+#define AB8500_DENC_CONF1_CC(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF1, CC, AB8500_DENC_CONF1_CC_##__x)
+#define AB8500_DENC_CONF2 0x00000602
+#define AB8500_DENC_CONF2_N_INTRL_SHIFT 7
+#define AB8500_DENC_CONF2_N_INTRL_MASK 0x00000080
+#define AB8500_DENC_CONF2_N_INTRL(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, N_INTRL, __x)
+#define AB8500_DENC_CONF2_EN_RST_SHIFT 6
+#define AB8500_DENC_CONF2_EN_RST_MASK 0x00000040
+#define AB8500_DENC_CONF2_EN_RST(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, EN_RST, __x)
+#define AB8500_DENC_CONF2_BURST_EN_SHIFT 5
+#define AB8500_DENC_CONF2_BURST_EN_MASK 0x00000020
+#define AB8500_DENC_CONF2_BURST_EN(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, BURST_EN, __x)
+#define AB8500_DENC_CONF2_SEL_RST_SHIFT 4
+#define AB8500_DENC_CONF2_SEL_RST_MASK 0x00000010
+#define AB8500_DENC_CONF2_SEL_RST_USE_HW_VAL 0
+#define AB8500_DENC_CONF2_SEL_RST_USE_PROG_VAL 1
+#define AB8500_DENC_CONF2_SEL_RST(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, SEL_RST, \
+ AB8500_DENC_CONF2_SEL_RST_##__x)
+#define AB8500_DENC_CONF2_RST_OSC_BUF_SHIFT 2
+#define AB8500_DENC_CONF2_RST_OSC_BUF_MASK 0x00000004
+#define AB8500_DENC_CONF2_RST_OSC_BUF(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, RST_OSC_BUF, __x)
+#define AB8500_DENC_CONF2_VAL_RST_SHIFT 0
+#define AB8500_DENC_CONF2_VAL_RST_MASK 0x00000003
+#define AB8500_DENC_CONF2_VAL_RST_ALL_LINES 0
+#define AB8500_DENC_CONF2_VAL_RST_EVERY_2ND_FIELD 1
+#define AB8500_DENC_CONF2_VAL_RST_EVERY_4TH_FIELD 2
+#define AB8500_DENC_CONF2_VAL_RST_EVERY_8TH_FIELD 3
+#define AB8500_DENC_CONF2_VAL_RST(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF2, VAL_RST, \
+ AB8500_DENC_CONF2_VAL_RST_##__x)
+#define AB8500_DENC_CONF6 0x00000606
+#define AB8500_DENC_CONF6_SOFT_RESET_SHIFT 7
+#define AB8500_DENC_CONF6_SOFT_RESET_MASK 0x00000080
+#define AB8500_DENC_CONF6_SOFT_RESET(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF6, SOFT_RESET, __x)
+#define AB8500_DENC_CONF6_JUMP_SHIFT 6
+#define AB8500_DENC_CONF6_JUMP_MASK 0x00000040
+#define AB8500_DENC_CONF6_JUMP(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF6, JUMP, __x)
+#define AB8500_DENC_CONF6_DEC_NINC_SHIFT 5
+#define AB8500_DENC_CONF6_DEC_NINC_MASK 0x00000020
+#define AB8500_DENC_CONF6_DEC_NINC(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF6, DEC_NINC, __x)
+#define AB8500_DENC_CONF6_FREE_JUMP_SHIFT 4
+#define AB8500_DENC_CONF6_FREE_JUMP_MASK 0x00000010
+#define AB8500_DENC_CONF6_FREE_JUMP(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF6, FREE_JUMP, __x)
+#define AB8500_DENC_CONF6_MAX_DYN_SHIFT 0
+#define AB8500_DENC_CONF6_MAX_DYN_MASK 0x00000001
+#define AB8500_DENC_CONF6_MAX_DYN(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF6, MAX_DYN, __x)
+#define AB8500_DENC_CONF8 0x00000608
+#define AB8500_DENC_CONF8_PH_RST_MODE_SHIFT 6
+#define AB8500_DENC_CONF8_PH_RST_MODE_MASK 0x000000C0
+#define AB8500_DENC_CONF8_PH_RST_MODE_DISABLED 0
+#define AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_PHASE_BUF 1
+#define AB8500_DENC_CONF8_PH_RST_MODE_UPDATE_FROM_INC_DFS 2
+#define AB8500_DENC_CONF8_PH_RST_MODE_RESET 3
+#define AB8500_DENC_CONF8_PH_RST_MODE(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF8, PH_RST_MODE, \
+ AB8500_DENC_CONF8_PH_RST_MODE_##__x)
+#define AB8500_DENC_CONF8_VAL_422_MUX_SHIFT 4
+#define AB8500_DENC_CONF8_VAL_422_MUX_MASK 0x00000010
+#define AB8500_DENC_CONF8_VAL_422_MUX_TEST 0
+#define AB8500_DENC_CONF8_VAL_422_MUX_ACTIVE 1
+#define AB8500_DENC_CONF8_VAL_422_MUX(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF8, VAL_422_MUX, \
+ AB8500_DENC_CONF8_VAL_422_MUX_##__x)
+#define AB8500_DENC_CONF8_BLK_ALL_SHIFT 3
+#define AB8500_DENC_CONF8_BLK_ALL_MASK 0x00000008
+#define AB8500_DENC_CONF8_BLK_ALL(__x) \
+ AB8500_VAL2REG(AB8500_DENC_CONF8, BLK_ALL, __x)
+#define AB8500_TVOUT_CTRL 0x00000680
+#define AB8500_TVOUT_CTRL_TV_LOAD_RC_SHIFT 6
+#define AB8500_TVOUT_CTRL_TV_LOAD_RC_MASK 0x00000040
+#define AB8500_TVOUT_CTRL_TV_LOAD_RC(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL, TV_LOAD_RC, __x)
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_SHIFT 3
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_MASK 0x00000038
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_0_5S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_1S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_1_5S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_2S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_2_5S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME_3S 0
+#define AB8500_TVOUT_CTRL_PLUG_TV_TIME(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL, PLUG_TV_TIME, \
+ AB8500_TVOUT_CTRL_PLUG_TV_TIME_##__x)
+#define AB8500_TVOUT_CTRL_TV_PLUG_ON_SHIFT 2
+#define AB8500_TVOUT_CTRL_TV_PLUG_ON_MASK 0x00000004
+#define AB8500_TVOUT_CTRL_TV_PLUG_ON(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL, TV_PLUG_ON, __x)
+#define AB8500_TVOUT_CTRL_DAC_CTRL0_SHIFT 1
+#define AB8500_TVOUT_CTRL_DAC_CTRL0_MASK 0x00000002
+#define AB8500_TVOUT_CTRL_DAC_CTRL0(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL, DAC_CTRL0, __x)
+#define AB8500_TVOUT_CTRL_DAC_CTRL1_SHIFT 0
+#define AB8500_TVOUT_CTRL_DAC_CTRL1_MASK 0x00000001
+#define AB8500_TVOUT_CTRL_DAC_CTRL1(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL, DAC_CTRL1, __x)
+#define AB8500_TVOUT_CTRL2 0x00000681
+#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN_SHIFT 1
+#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN_MASK 0x00000002
+#define AB8500_TVOUT_CTRL2_SWAP_DDR_DATA_IN(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL2, SWAP_DDR_DATA_IN, __x)
+#define AB8500_TVOUT_CTRL2_DENC_DDR_SHIFT 0
+#define AB8500_TVOUT_CTRL2_DENC_DDR_MASK 0x00000001
+#define AB8500_TVOUT_CTRL2_DENC_DDR(__x) \
+ AB8500_VAL2REG(AB8500_TVOUT_CTRL2, DENC_DDR, __x)
+#define AB8500_IT_MASK1 0x00000E40
+#define AB8500_IT_MASK1_PON_KEY1_DBR_SHIFT 7
+#define AB8500_IT_MASK1_PON_KEY1_DBR_MASK 0x00000080
+#define AB8500_IT_MASK1_PON_KEY1_DBR(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY1_DBR, __x)
+#define AB8500_IT_MASK1_PON_KEY1_DBF_SHIFT 6
+#define AB8500_IT_MASK1_PON_KEY1_DBF_MASK 0x00000040
+#define AB8500_IT_MASK1_PON_KEY1_DBF(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY1_DBF, __x)
+#define AB8500_IT_MASK1_PON_KEY2_DBR_SHIFT 5
+#define AB8500_IT_MASK1_PON_KEY2_DBR_MASK 0x00000020
+#define AB8500_IT_MASK1_PON_KEY2_DBR(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY2_DBR, __x)
+#define AB8500_IT_MASK1_PON_KEY2_DBF_SHIFT 4
+#define AB8500_IT_MASK1_PON_KEY2_DBF_MASK 0x00000010
+#define AB8500_IT_MASK1_PON_KEY2_DBF(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, PON_KEY2_DBF, __x)
+#define AB8500_IT_MASK1_TEMP_WARN_SHIFT 3
+#define AB8500_IT_MASK1_TEMP_WARN_MASK 0x00000008
+#define AB8500_IT_MASK1_TEMP_WARN(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, TEMP_WARN, __x)
+#define AB8500_IT_MASK1_PLUG_TV_DET_SHIFT 2
+#define AB8500_IT_MASK1_PLUG_TV_DET_MASK 0x00000004
+#define AB8500_IT_MASK1_PLUG_TV_DET(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, PLUG_TV_DET, __x)
+#define AB8500_IT_MASK1_UNPLUG_TV_DET_SHIFT 1
+#define AB8500_IT_MASK1_UNPLUG_TV_DET_MASK 0x00000002
+#define AB8500_IT_MASK1_UNPLUG_TV_DET(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, UNPLUG_TV_DET, __x)
+#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK_SHIFT 0
+#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK_MASK 0x00000001
+#define AB8500_IT_MASK1_MAIN_EXT_CH_NOK(__x) \
+ AB8500_VAL2REG(AB8500_IT_MASK1, MAIN_EXT_CH_NOK, __x)
+#define AB8500_REV 0x00001080
+#define AB8500_REV_FULL_MASK_SHIFT 4
+#define AB8500_REV_FULL_MASK_MASK 0x000000F0
+#define AB8500_REV_FULL_MASK(__x) \
+ AB8500_VAL2REG(AB8500_REV, FULL_MASK, __x)
+#define AB8500_REV_METAL_FIX_SHIFT 0
+#define AB8500_REV_METAL_FIX_MASK 0x0000000F
+#define AB8500_REV_METAL_FIX(__x) \
+ AB8500_VAL2REG(AB8500_REV, METAL_FIX, __x)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index f30502f4c70..274e0acb76c 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -244,8 +244,6 @@ comment "Frame buffer hardware drivers"
source "drivers/video/mcde/Kconfig"
-source "drivers/video/av8100/Kconfig"
-
config FB_CIRRUS
tristate "Cirrus Logic support"
depends on FB && (ZORRO || PCI)
@@ -2227,6 +2225,8 @@ source "drivers/video/omap2/Kconfig"
source "drivers/video/backlight/Kconfig"
source "drivers/video/display/Kconfig"
+source "drivers/video/av8100/Kconfig"
+
if VT
source "drivers/video/console/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a74a33bd5f0..c79033e839a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -127,7 +127,7 @@ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
obj-$(CONFIG_FB_OMAP) += omap/
obj-y += omap2/
obj-$(CONFIG_FB_MCDE) += mcde/
-obj-$(CONFIG_FB_HDMI) += av8100/
++obj-$(CONFIG_AV8100) += av8100/
obj-y += b2r2/
obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
obj-$(CONFIG_FB_CARMINE) += carminefb.o
diff --git a/drivers/video/av8100/Kconfig b/drivers/video/av8100/Kconfig
index 959b986c6ce..12e44e2c430 100644
--- a/drivers/video/av8100/Kconfig
+++ b/drivers/video/av8100/Kconfig
@@ -1,6 +1,5 @@
-config FB_HDMI
+config AV8100
tristate "AV8100 driver support(HDMI/CVBS)"
- depends on (FB_MCDE)
- default y
+ default n
help
- Please disable this feature if hdmi driver support not required.
+ Please enable this feature if hdmi/tvout driver support is required.
diff --git a/drivers/video/av8100/Makefile b/drivers/video/av8100/Makefile
index b834027d3ef..d857753b4bc 100644
--- a/drivers/video/av8100/Makefile
+++ b/drivers/video/av8100/Makefile
@@ -1,8 +1,7 @@
# Make file for compiling and loadable module HDMI
-obj- := av8100.o # Dummy rule to force built-in.o to be made
+obj-$(CONFIG_AV8100) += av8100.o hdmi.o
-obj-$(CONFIG_FB_HDMI) += av8100.o
-clean-files := av8100.o built-in.o modules.order
+clean-files := av8100.o hdmi.o built-in.o modules.order
diff --git a/drivers/video/av8100/av8100.c b/drivers/video/av8100/av8100.c
index 631654ab02a..ccabeb8caa8 100644
--- a/drivers/video/av8100/av8100.c
+++ b/drivers/video/av8100/av8100.c
@@ -1,2432 +1,2898 @@
/*
- * Copyright (C) ST-Ericsson SA 2010
+ * Copyright (C) ST-Ericsson AB 2010
*
- * License terms:
+ * AV8100 driver
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
+ * Author: Per Persson <per.xb.persson@stericsson.com>
+ * for ST-Ericsson.
+ *
+ * License terms: GNU General Public License (GPL), version 2.
*/
-#include <linux/types.h>
+
#include <linux/kernel.h>
-#include <linux/init.h>
#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/proc_fs.h>
-#include <linux/smp_lock.h>
+#include <linux/device.h>
#include <linux/miscdevice.h>
#include <linux/platform_device.h>
-#include <linux/poll.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
#include <linux/i2c.h>
-#include <linux/workqueue.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
#include <linux/kthread.h>
+#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <asm/irq.h>
-#include <asm/ioctl.h>
-#include <asm/bitops.h>
-#include <asm/io.h>
-#include <asm/types.h>
-#include <mach/hardware.h>
-#include <mach/debug.h>
-#include <linux/gpio.h>
-#include <mach/mcde.h>
-#include <mach/dsi.h>
-
-#include <mach/av8100_p.h>
-#include <mach/av8100_fw.h>
-
-#define DRIVER_NAME (av8100_driver.driver.name)
+#include <linux/timer.h>
+#include <linux/mutex.h>
+
+#include "av8100_regs.h"
+#include <video/av8100.h>
+#include <video/hdmi.h>
+#include "av8100_fw.h"
+
+#define AV8100_INT_EVENT 0x1
+#define AV8100_TIMER_INT_EVENT 0x2
+
+#define AV8100_TIMER_INTERRUPT_POLLING_TIME 250
+
+#define AV8100_DRIVER_MINOR_NUMBER 240
+#define GPIO_AV8100_RSTN 196
+#define AV8100_MASTER_CLOCK_TIMING 0x3
+#define AV8100_ON_TIME 1
+#define AV8100_OFF_TIME 0
+#define AV8100_COMMAND_OFFSET 0x10
+#define AV8100_COMMAND_MAX_LENGTH 0x81
+
+#define AV8100_TE_LINE_NB_14 14
+#define AV8100_TE_LINE_NB_17 17
+#define AV8100_TE_LINE_NB_18 18
+#define AV8100_TE_LINE_NB_21 21
+#define AV8100_TE_LINE_NB_22 22
+#define AV8100_TE_LINE_NB_30 30
+#define AV8100_TE_LINE_NB_38 38
+#define AV8100_TE_LINE_NB_40 40
+#define AV8100_UI_X4_DEFAULT 6
+
+#define HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT 2
+#define HDMI_CEC_MESSAGE_WRITE_BUFFER_SIZE 16
+#define HDMI_HDCP_SEND_KEY_SIZE 7
+#define HDMI_INFOFRAME_DATA_SIZE 28
+#define HDMI_CEC_MESSAGE_READBACK_MAXSIZE 16
+#define HDMI_FUSE_AES_KEY_SIZE 16
+
+#define REG_16_8_LSB(p) (u8)(p & 0xFF)
+#define REG_16_8_MSB(p) (u8)((p & 0xFF00)>>8)
+#define REG_32_8_MSB(p) (u8)((p & 0xFF000000)>>24)
+#define REG_32_8_MMSB(p) (u8)((p & 0x00FF0000)>>16)
+#define REG_32_8_MLSB(p) (u8)((p & 0x0000FF00)>>8)
+#define REG_32_8_LSB(p) (u8)(p & 0x000000FF)
+#define REG_10_8_MSB(p) (u8)((p & 0x300)>>8)
+
+
+struct av8100_config_t {
+ struct i2c_client *client;
+ struct i2c_device_id *id;
+ struct av8100_video_input_format_cmd hdmi_video_input_cmd;
+ struct av8100_audio_input_format_cmd hdmi_audio_input_cmd;
+ struct av8100_video_output_format_cmd hdmi_video_output_cmd;
+ struct av8100_video_scaling_format_cmd hdmi_video_scaling_cmd;
+ struct av8100_color_space_conversion_format_cmd
+ hdmi_color_space_conversion_cmd;
+ struct av8100_cec_message_write_format_cmd
+ hdmi_cec_message_write_cmd;
+ struct av8100_cec_message_read_back_format_cmd
+ hdmi_cec_message_read_back_cmd;
+ struct av8100_denc_format_cmd hdmi_denc_cmd;
+ struct av8100_hdmi_cmd hdmi_cmd;
+ struct av8100_hdcp_send_key_format_cmd hdmi_hdcp_send_key_cmd;
+ struct av8100_hdcp_management_format_cmd
+ hdmi_hdcp_management_format_cmd;
+ struct av8100_infoframes_format_cmd hdmi_infoframes_cmd;
+ struct av8100_edid_section_readback_format_cmd
+ hdmi_edid_section_readback_cmd;
+ struct av8100_pattern_generator_format_cmd hdmi_pattern_generator_cmd;
+ struct av8100_fuse_aes_key_format_cmd hdmi_fuse_aes_key_cmd;
+};
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("JAYARAMI REDDY");
-MODULE_DESCRIPTION("AV8100 driver for U8500");
+/**
+ * struct av8100_cea - CEA(consumer electronic access) standard structure
+ * @cea_id:
+ * @cea_nb:
+ * @vtotale:
+ **/
-extern void u8500_mcde_tasklet_4(unsigned long);
+struct av8100_cea {
+ char cea_id[40];
+ int cea_nb;
+ int vtotale;
+ int vactive;
+ int vsbp;
+ int vslen;
+ int vsfp;
+ char vpol[5];
+ int htotale;
+ int hactive;
+ int hbp;
+ int hslen;
+ int hfp;
+ int frequence;
+ char hpol[5];
+ int reg_line_duration;
+ int blkoel_duration;
+ int uix4;
+ int pll_mult;
+ int pll_div;
+};
-/*#define AV8100_USE_KERNEL_THREAD*/
+enum av8100_command_size {
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE = 0x17,
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE = 0x8,
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE = 0x1E,
+ AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE = 0x11,
+ AV8100_COMMAND_COLORSPACECONVERSION_SIZE = 0x1D,
+ AV8100_COMMAND_CEC_MESSAGE_WRITE_SIZE = 0x12,
+ AV8100_COMMAND_CEC_MESSAGE_READ_BACK_SIZE = 0x1,
+ AV8100_COMMAND_DENC_SIZE = 0x6,
+ AV8100_COMMAND_HDMI_SIZE = 0x4,
+ AV8100_COMMAND_HDCP_SENDKEY_SIZE = 0xA,
+ AV8100_COMMAND_HDCP_MANAGEMENT_SIZE = 0x4,
+ AV8100_COMMAND_INFOFRAMES_SIZE = 0x21,
+ AV8100_COMMAND_EDID_SECTION_READBACK_SIZE = 0x3,
+ AV8100_COMMAND_PATTERNGENERATOR_SIZE = 0x4,
+ AV8100_COMMAND_FUSE_AES_KEY_SIZE = 0x12,
+};
-#if !defined CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI && \
- !defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI && \
- !defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
-#define TEST_PATTERN_TEST
-#endif
+DEFINE_MUTEX(av8100_hw_mutex);
+#define LOCK_AV8100_HW mutex_lock(&av8100_hw_mutex)
+#define UNLOCK_AV8100_HW mutex_unlock(&av8100_hw_mutex)
-#define HDMI_LOGGING
-#define CONFIG_MCDE_COLOURED_PRINTS
-
-#define PRNK_COL_BLACK 30
-#define PRNK_COL_RED 31
-#define PRNK_COL_GREEN 32
-#define PRNK_COL_YELLOW 33
-#define PRNK_COL_BLUE 34
-#define PRNK_COL_MAGENTA 35
-#define PRNK_COL_CYAN 36
-#define PRNK_COL_WHITE 37
-
-#ifdef CONFIG_MCDE_COLOURED_PRINTS
-#define PRNK_COL(_col) printk(KERN_ERR "%c[0;%d;40m\n", 0x1b, _col)
-#else /* CONFIG_MCDE_COLOURED_PRINTS */
-#define PRNK_COL(_col)
-#endif /* CONFIG_MCDE_COLOURED_PRINTS */
-
-#ifdef HDMI_LOGGING
-#define HDMI_TRACE do {\
- PRNK_COL(PRNK_COL_YELLOW);\
- printk(KERN_DEBUG "HDMI send cmd %s\n", __func__);\
- PRNK_COL(PRNK_COL_WHITE);\
-} while (0)
-#else
-#define HDMI_TRACE
-#endif
+#define AV8100_DEBUG_EXTRA
+#define AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
static int av8100_open(struct inode *inode, struct file *filp);
static int av8100_release(struct inode *inode, struct file *filp);
-static int av8100_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
-static void av8100_configure_hdmi(struct i2c_client *i2c);
-static void av8100_configure_denc(struct av8100_data *av8100DataTemp);
-static irqreturn_t av8100_intr_handler(int irq, void *p);
-
-static int av8100_write_multi_byte(struct i2c_client *client, unsigned char regOffset,unsigned char *buf,unsigned char nbytes);
-static int av8100_write_single_byte(struct i2c_client *client, unsigned char reg,unsigned char data);
-#if 0
-static int av8100_read_multi_byte(struct i2c_client *client,unsigned char reg,unsigned char *buf, unsigned char nbytes);
-#endif
-static int av8100_read_single_byte(struct i2c_client *client,unsigned char reg, unsigned char* val);
-static void av8100_hdmi_on(struct av8100_data *av8100DataTemp);
-static void av8100_hdmi_off(struct av8100_data *av8100DataTemp);
-static int configure_av8100_video_input(char* buffer_temp);
-static int configure_av8100_audio_input(char* buffer_temp);
-static int configure_av8100_video_output(char* buffer_temp);
-static int configure_av8100_video_scaling(char* buffer_temp);
-static int configure_av8100_colorspace_conversion(char* buffer_temp);
-static int configure_av8100_cec_message_write(char* buffer_temp);
-static int configure_av8100_cec_message_read(char* buffer_temp);
-static int configure_av8100_denc(char* buffer_temp);
-static int configure_av8100_hdmi(char* buffer_temp);
-static int configure_av8100_hdcp_senkey(char* buffer_temp);
-static int configure_av8100_hdcp_management(char* buffer_temp);
-static int configure_av8100_infoframe(char* buffer_temp);
-static int configure_av8100_pattern_generator(char* buffer_temp);
-#if 0
-static int read_edid_info(struct i2c_client *i2c, char* buff);
-#endif
-static int av8100_send_command (struct i2c_client *i2cClient, char command_type, enum interface if_type);
-static int av8100_powerdown(void);
-static int av8100_powerup(struct i2c_client *i2c, const struct i2c_device_id *id);
-static int av8100_enable_interrupt(struct i2c_client *i2c);
-static int av8100_probe(struct i2c_client *i2cClient,const struct i2c_device_id *id);
-static int __exit av8100_remove(struct i2c_client *i2cClient);
-static int av8100_download_firmware(struct i2c_client *i2c, char regoffset, char* fw_buff, int numOfBytes, enum interface if_type);
-static unsigned short av8100_get_ui_x4(av8100_output_CEA_VESA output_video_format);
-static unsigned short av8100_get_te_line_nb(av8100_output_CEA_VESA output_video_format);
-static void av8100_init_config_params(void);
-static void av8100_config_output_dep_params(void);
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
-static mcde_video_mode av8100_get_mcde_video_mode(av8100_output_CEA_VESA format);
+static int av8100_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+static int __devinit av8100_probe(struct i2c_client *i2cClient,
+ const struct i2c_device_id *id);
+static int __devexit av8100_remove(struct i2c_client *i2cClient);
+
+static struct av8100_config_t *av8100_config;
+static struct av8100_status g_av8100_status = {0};
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+static struct timer_list av8100_timer;
#endif
-static void av8100_set_state(av8100_operating_mode state);
-static av8100_operating_mode av8100_get_state(void);
-
-#define uint8 unsigned char
-
-/** global data */
-unsigned int g_av8100_cmd_length=0;
-unsigned int g_dcs_data_count_index = 0;
-unsigned int g_dcs_data_count_last = 0;
-struct av8100_data *av8100Data;
-av8100_operating_mode g_av8100_state = AV8100_OPMODE_SHUTDOWN;
-
-av8100_video_input_format_cmd hdmi_video_input_cmd;
-av8100_video_output_format_cmd hdmi_video_output_cmd;
-av8100_hdmi_cmd hdmi_cmd;
-av8100_pattern_generator_cmd hdmi_pattern_generator_cmd;
-av8100_audio_input_format_cmd hdmi_audio_input_cmd;
-av8100_color_space_conversion_cmd hdmi_color_conversion_cmd;
-av8100_denc_cmd hdmi_denc_cmd;
-
-wait_queue_head_t av8100_event;
-bool av8100_flag = 0x0;
-
-int length = 0x0;
-extern unsigned int isReady;
-#define DSI_MAX_DATA_WRITE 15
-
-av8100_cea av8100_all_cea[29] ={
-/* cea id cea_nr vtot vact vsbpp vslen vsfp vpol htot hact hbp hslen hfp freq hpol rld,bd,uix4,pm,pd */
-{ "0 CUSTOM " , 0 ,0 , 0 ,0 , 0 , 0 , "-" , 800 ,640 , 16 , 96 , 10, 25200000 ,"-",0,0,0,0,0},//Settings to be define
-{ "1 CEA 1 VESA 4 640x480p @ 60 Hz " , 1 ,525 , 480 ,33 , 2 , 10 , "-" , 800 ,640 , 49 , 290 , 146, 25200000 ,"-",2438,1270,6,32,1},//RGB888
-{ "2 CEA 2 - 3 720x480p @ 60 Hz 4:3 " , 2 ,525 , 480 ,30 , 6 , 9 , "-" , 858 ,720 , 34 , 130 , 128, 27027000 ,"-",1828,0x3C0,8,24,1},//RGB565
-{ "3 CEA 4 1280x720p @ 60 Hz " , 4 ,750 , 720 ,20 , 5 , 5 , "+" , 1650 ,1280 , 114 , 39 , 228, 74250000 ,"+",1706,164,6,32,1},//RGB565
-{ "4 CEA 5 1920x1080i @ 60 Hz " , 5 ,1125 , 540 ,20 , 5 , 0 , "+" , 2200 ,1920 , 88 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define
-{ "5 CEA 6-7 480i (NTSC) " , 6 ,525 , 240 ,44 , 5 , 0 , "-" , 1716 ,1440 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "6 CEA 14-15 480p @ 60 Hz " , 14 ,525 , 480 ,44 , 5 , 0 , "-" , 858 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "7 CEA 16 1920x1080p @ 60 Hz " , 16 ,1125 , 1080 ,36 , 5 , 0 , "+" , 1980 ,1280 , 440 , 40 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define
-{ "8 CEA 17-18 720x576p @ 50 Hz " , 17 ,625 , 576 ,44 , 5 , 0 , "-" , 864 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "9 CEA 19 1280x720p @ 50 Hz " , 19 ,750 , 720 ,25 , 5 , 0 , "+" , 1980 ,1280 , 440 , 40 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define
-{ "10 CEA 20 1920 x 1080i @ 50 Hz " , 20 ,1125 , 540 ,20 , 5 , 0 , "+" , 2640 ,1920 , 528 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define
-{ "11 CEA 21-22 576i (PAL) " , 21 ,625 , 288 ,44 , 5 , 0 , "-" , 1728 ,1440 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "12 CEA 29/30 576p " , 29 ,625 , 576 ,44 , 5 , 0 , "-" , 864 ,720 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "13 CEA 31 1080p 50Hz " , 31 ,1125 , 1080 ,44 , 5 , 0 , "-" , 2750 ,1920 , 12 , 64 , 10, 27000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "14 CEA 32 1920x1080p @ 24 Hz " , 32 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2750 ,1920 , 660 , 44 , 153, 74250000 ,"+",2844,0x530,6,32,1},//RGB565
-{ "15 CEA 33 1920x1080p @ 25 Hz " , 33 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2640 ,1920 , 528 , 44 , 10, 74250000 ,"+",0,0,0,0,0},//Settings to be define
-{ "16 CEA 34 1920x1080p @ 30Hz " , 34 ,1125 , 1080 ,36 , 5 , 4 , "+" , 2200 ,1920 , 91 , 44 , 153, 74250000 ,"+",2275,0xAB,6,32,1},//RGB565
-{ "17 CEA 60 1280x720p @ 24 Hz " , 60 ,750 , 720 ,20 , 5 , 5 , "+" , 3300 ,1280 , 284 , 50 , 2276, 29700000 ,"+",4266,0xAD0,5,32,1},//RGB565
-{ "18 CEA 61 1280x720p @ 25 Hz " , 61 ,750 , 720 ,20 , 5 , 5 , "+" , 3960 ,1280 , 228 , 39 , 2503 ,30937500 ,"+",4096,0x500,5,32,1},//RGB565
-{ "19 CEA 62 1280x720p @ 30 Hz " , 62 ,750 , 720 ,20 , 5 , 5 , "+" , 3300 ,1280 , 228 , 39 , 1820, 37125000 ,"+",3413,0x770,5,32,1},//RGB565
-{ "20 VESA 9 800x600 @ 60 Hz " , 109 ,628 , 600 ,28 , 4 , 0 , "+" , 1056 ,800 , 40 , 128 , 10, 40000000 ,"+",0,0,0,0,0},//Settings to be define
-{ "21 VESA 14 848x480 @ 60 Hz " , 114 ,500 , 480 ,20 , 5 , 0 , "+" , 1056 ,848 , 24 , 80 , 10, 31500000 ,"-",0,0,0,0,0},//Settings to be define
-{ "22 VESA 16 1024x768 @ 60 Hz " , 116 ,806 , 768 ,38 , 6 , 0 , "-" , 1344 ,1024 , 24 , 135 , 10, 65000000 ,"-",0,0,0,0,0},//Settings to be define
-{ "23 VESA 22 1280x768 @ 60 Hz " , 122 ,802 , 768 ,34 , 4 , 0 , "+" , 1688 ,1280 , 48 , 160 , 10, 81250000 ,"-",0,0,0,0,0},//Settings to be define
-{ "24 VESA 23 1280x768 @ 60 Hz " , 123 ,798 , 768 ,30 , 7 , 0 , "+" , 1664 ,1280 , 64 , 128 , 10, 79500000 ,"-",0,0,0,0,0},//Settings to be define
-{ "25 VESA 27 1280x800 @ 60 Hz " , 127 ,823 , 800 ,23 , 6 , 0 , "+" , 1440 ,1280 , 48 , 32 , 10, 71000000 ,"+",0,0,0,0,0},//Settings to be define
-{ "26 VESA 28 1280x800 @ 60 Hz " , 128 ,831 , 800 ,31 , 6 , 0 , "+" , 1680 ,1280 , 72 , 128 , 10, 83500000 ,"-",0,0,0,0,0},//Settings to be define
-{ "27 VESA 39 1360x768 @ 60 Hz " , 139 ,790 , 768 ,22 , 5 , 0 , "-" , 1520 ,1360 , 48 , 32 , 10, 72000000 ,"+",0,0,0,0,0},//Settings to be define
-{ "28 VESA 81 1360x768 @ 60 Hz " , 181 ,798 , 768 ,30 , 5 , 0 , "+" , 1776 ,1360 , 72 , 136 , 10, 84750000 ,"-",0,0,0,0,0}//Settings to be define
-};
+static wait_queue_head_t av8100_event;
+static int av8100_flag = 0x0;
-/** av8100 file operations */
-static struct file_operations av8100_fops = {
+static const struct file_operations av8100_fops = {
.owner = THIS_MODULE,
.open = av8100_open,
.release = av8100_release,
.ioctl = av8100_ioctl
};
-/** av8100 misc device structure */
-static struct miscdevice av8100_miscdev =
-{
+static struct miscdevice av8100_miscdev = {
AV8100_DRIVER_MINOR_NUMBER,
"av8100",
&av8100_fops
};
-/**
- * av8100_write_multi_byte() - Write a multiple bytes to av8100 chip(av8100) through i2c interface.
- * @client: i2c client structure
- * @buf: buffer to be written
- * @nbytes: nunmber of bytes to be written
- *
- * This funtion uses smbus block write API's to write n number of bytes to the av8100
- **/
-static int av8100_write_multi_byte(struct i2c_client *client, uint8 regOffset,
- uint8 *buf,uint8 nbytes)
-{
- int ret = AV8100_OK;
- //u8 temp;
-
- ret = i2c_smbus_write_i2c_block_data(client, regOffset,nbytes, buf);
- if (ret < 0) {
- printk("i2c smbus write multi byte error\n");
- return ret;
- }
- length += nbytes;
- //printk("length:%d\n", length);
-#if 0
- if(nbytes < 40)
- {
- for (temp = 0; temp < nbytes; temp++)
- printk("value:%0x\n", buf[temp]);
- printk("FW size:%d\n", length);
- }
-#endif
+struct av8100_cea av8100_all_cea[29] = {
+/* cea id
+ * cea_nr vtot vact vsbpp vslen
+ * vsfp vpol htot hact hbp hslen hfp freq
+ * hpol rld bd uix4 pm pd */
+{ "0 CUSTOM ",
+ 0, 0, 0, 0, 0,
+ 0, "-", 800, 640, 16, 96, 10, 25200000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be defined*/
+{ "1 CEA 1 VESA 4 640x480p @ 60 Hz ",
+ 1, 525, 480, 33, 2,
+ 10, "-", 800, 640, 49, 290, 146, 25200000,
+ "-", 2438, 1270, 6, 32, 1},/*RGB888*/
+{ "2 CEA 2 - 3 720x480p @ 60 Hz 4:3 ",
+ 2, 525, 480, 30, 6,
+ 9, "-", 858, 720, 34, 130, 128, 27027000,
+ "-", 1828, 0x3C0, 8, 24, 1},/*RGB565*/
+{ "3 CEA 4 1280x720p @ 60 Hz ",
+ 4, 750, 720, 20, 5,
+ 5, "+", 1650, 1280, 114, 39, 228, 74250000,
+ "+", 1706, 164, 6, 32, 1},/*RGB565*/
+{ "4 CEA 5 1920x1080i @ 60 Hz ",
+ 5, 1125, 540, 20, 5,
+ 0, "+", 2200, 1920, 88, 44, 10, 74250000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "5 CEA 6-7 480i (NTSC) ",
+ 6, 525, 240, 44, 5,
+ 0, "-", 858, 720, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "6 CEA 14-15 480p @ 60 Hz ",
+ 14, 525, 480, 44, 5,
+ 0, "-", 858, 720, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "7 CEA 16 1920x1080p @ 60 Hz ",
+ 16, 1125, 1080, 36, 5,
+ 0, "+", 1980, 1280, 440, 40, 10, 74250000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "8 CEA 17-18 720x576p @ 50 Hz ",
+ 17, 625, 576, 44, 5,
+ 0, "-", 864, 720, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "9 CEA 19 1280x720p @ 50 Hz ",
+ 19, 750, 720, 25, 5,
+ 0, "+", 1980, 1280, 440, 40, 10, 74250000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "10 CEA 20 1920 x 1080i @ 50 Hz ",
+ 20, 1125, 540, 20, 5,
+ 0, "+", 2640, 1920, 528, 44, 10, 74250000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "11 CEA 21-22 576i (PAL) ",
+ 21, 625, 288, 44, 5,
+ 0, "-", 864, 720, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "12 CEA 29/30 576p ",
+ 29, 625, 576, 44, 5,
+ 0, "-", 864, 720, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "13 CEA 31 1080p 50Hz ",
+ 31, 1125, 1080, 44, 5,
+ 0, "-", 2750, 1920, 12, 64, 10, 27000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "14 CEA 32 1920x1080p @ 24 Hz ",
+ 32, 1125, 1080, 36, 5,
+ 4, "+", 2750, 1920, 660, 44, 153, 74250000,
+ "+", 2844, 0x530, 6, 32, 1},/*RGB565*/
+{ "15 CEA 33 1920x1080p @ 25 Hz ",
+ 33, 1125, 1080, 36, 5,
+ 4, "+", 2640, 1920, 528, 44, 10, 74250000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "16 CEA 34 1920x1080p @ 30Hz ",
+ 34, 1125, 1080, 36, 5,
+ 4, "+", 2200, 1920, 91, 44, 153, 74250000,
+ "+", 2275, 0xAB, 6, 32, 1},/*RGB565*/
+{ "17 CEA 60 1280x720p @ 24 Hz ",
+ 60, 750, 720, 20, 5,
+ 5, "+", 3300, 1280, 284, 50, 2276, 29700000,
+ "+", 4266, 0xAD0, 5, 32, 1},/*RGB565*/
+{ "18 CEA 61 1280x720p @ 25 Hz ",
+ 61, 750, 720, 20, 5,
+ 5, "+", 3960, 1280, 228, 39, 2503, 30937500,
+ "+", 4096, 0x500, 5, 32, 1},/*RGB565*/
+{ "19 CEA 62 1280x720p @ 30 Hz ",
+ 62, 750, 720, 20, 5,
+ 5, "+", 3300, 1280, 228, 39, 1820, 37125000,
+ "+", 3413, 0x770, 5, 32, 1},/*RGB565*/
+{ "20 VESA 9 800x600 @ 60 Hz ",
+ 109, 628, 600, 28, 4,
+ 0, "+", 1056, 800, 40, 128, 10, 40000000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "21 VESA 14 848x480 @ 60 Hz ",
+ 114, 500, 480, 20, 5,
+ 0, "+", 1056, 848, 24, 80, 10, 31500000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "22 VESA 16 1024x768 @ 60 Hz ",
+ 116, 806, 768, 38, 6,
+ 0, "-", 1344, 1024, 24, 135, 10, 65000000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "23 VESA 22 1280x768 @ 60 Hz ",
+ 122, 802, 768, 34, 4,
+ 0, "+", 1688, 1280, 48, 160, 10, 81250000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "24 VESA 23 1280x768 @ 60 Hz ",
+ 123, 798, 768, 30, 7,
+ 0, "+", 1664, 1280, 64, 128, 10, 79500000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "25 VESA 27 1280x800 @ 60 Hz ",
+ 127, 823, 800, 23, 6,
+ 0, "+", 1440, 1280, 48, 32, 10, 71000000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "26 VESA 28 1280x800 @ 60 Hz ",
+ 128, 831, 800, 31, 6,
+ 0, "+", 1680, 1280, 72, 128, 10, 83500000,
+ "-", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "27 VESA 39 1360x768 @ 60 Hz ",
+ 139, 790, 768, 22, 5,
+ 0, "-", 1520, 1360, 48, 32, 10, 72000000,
+ "+", 0, 0, 0, 0, 0},/*Settings to be define*/
+{ "28 VESA 81 1360x768 @ 60 Hz ",
+ 181, 798, 768, 30, 5,
+ 0, "+", 1776, 1360, 72, 136, 10, 84750000,
+ "-", 0, 0, 0, 0, 0} /*Settings to be define*/
+};
- /* FIXME- workaround,i2c_smbus_write_i2c_block_data doesn't work on this platform!*/
-#if 0
- for(temp=0;temp<nbytes-1;temp++) {
- ret = i2c_smbus_write_byte_data(client,0xF/*(regOffset)*/,buf[temp]);
- if (ret < 0) {
- printk("i2c smbus write byte error\n");
- return ret;
- }else
- printk("av8100_write_multi_byte ret:%x\n", ret);
- }
-#endif
- return ret;
-}
-/**
- * av8100_write_single_byte() - Write a single byte to av8100 chip(av8100) through i2c interface.
- * @client: i2c client structure
- * @reg: register offset
- * @data: data byte to be written
- *
- * This funtion uses smbus byte write API to write a single byte to av8100
- **/
-static int av8100_write_single_byte(struct i2c_client *client, uint8 reg,
- uint8 data)
-{
- int ret = AV8100_OK;
+static const struct i2c_device_id av8100_id[] = {
+ { "av8100", 0 },
+ { }
+};
- //printk("av8100_write_single_byte: reg=%x,data = %x\n", reg,data);
- ret = i2c_smbus_write_byte_data(client,reg,data);
- if(ret < 0) {
- printk("i2c smbus write byte failed\n");
- return ret;
- }
- return ret;
-}
+static struct i2c_driver av8100_driver = {
+ .probe = av8100_probe,
+ .remove = av8100_remove,
+ .driver = {
+ .name = "av8100",
+ },
+ .id_table = av8100_id,
+};
-/**
- * av8100_read_multi_byte() - read multiple bytes from av8100 chip(av8100) through i2c interface
- * @client: i2c client structure
- * @reg: register offset
- * @buf: read the data in this buffer
- * @nbytes: number of bytes to read
- *
- * This funtion uses smbus read block API to read multiple bytes from the reg offset.
- **/
-#if 0
-static int av8100_read_multi_byte(struct i2c_client *client,uint8 reg,
- uint8 *buf, uint8 nbytes)
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+static void av8100_timer_int(unsigned long value)
{
- int ret = AV8100_OK;
+ av8100_flag |= AV8100_TIMER_INT_EVENT;
+ wake_up_interruptible(&av8100_event);
- ret = i2c_smbus_read_i2c_block_data(client,reg,nbytes,buf);
- if(ret < 0){
- printk("i2c smbus read multi byte failed\n");
- return ret;
+ if (g_av8100_status.av8100_state >= AV8100_OPMODE_STANDBY) {
+ av8100_timer.expires = jiffies +
+ AV8100_TIMER_INTERRUPT_POLLING_TIME;
+ add_timer(&av8100_timer);
}
- if (ret < nbytes){
- printk("i2c smbus read multi byte failed\n");
- return -EIO;
- }
- return ret;
}
#endif
-/**
- * av8100_read_single_byte() - read single byte from av8100 chip(av8100) through i2c interface
- * @client: i2c client structure
- * @reg: register offset
- * @val: register value
- *
- * This funtion uses smbus read block API to read single byte from the reg offset.
- **/
-static int av8100_read_single_byte(struct i2c_client *client,uint8 reg, unsigned char* val)
+static int av8100_thread(void *p)
{
- int ret = AV8100_OK;
- int value = 0x0;
- value = i2c_smbus_read_byte_data(client, reg);
- if(value < 0){
- printk("i2c smbus read byte failed,read data = %x from offset: %x\n" ,value,reg);
- return ret;
- }
- //printk("read data = %x from offset: %x\n" ,value,reg);
- *val = value;
- return ret;
-}
-
-/**
- * get_dcs_data_index_params() - This API is used to get the number of times the data to be sent with the commands.
- **/
-void get_dcs_data_index_params(void)
-{
- g_dcs_data_count_index = 0;
- g_dcs_data_count_last = 0;
- g_dcs_data_count_index = g_av8100_cmd_length/DSI_MAX_DATA_WRITE;
- g_dcs_data_count_last = g_av8100_cmd_length%DSI_MAX_DATA_WRITE;
-}
+ u8 cpd = 0;
+ u8 stby = 0;
+ u8 hpds = 0;
+ u8 cpds = 0;
+ u8 mclkrng = 0;
+ int ret = 0;
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+ u8 hpds_old = 0xf;
+ u8 cpds_old = 0xf;
+#else
+ u8 sid = 0;
+ u8 oni = 0;
+ u8 hpdi = 0;
+ u8 cpdi = 0;
+#endif
-/**
- * av8100_intr_handler() - To handle av8100 interrupts.
- * @irq: irq context
- * @av8100Data:av8100 data
- *
- * This funtion handles the av8100 interrupts. It handles the plugin and plugout(HDMI/CVBS) interrupts.
- **/
-static irqreturn_t av8100_intr_handler(int irq, void *p)
-{
+ while (1) {
+ wait_event_interruptible(av8100_event, (av8100_flag != 0));
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+ if (av8100_flag & AV8100_TIMER_INT_EVENT) {
+ if (g_av8100_status.av8100_state >=
+ AV8100_OPMODE_STANDBY) {
+ /* STANDBY */
+ ret = av8100_register_standby_read(
+ &cpd,
+ &stby,
+ &hpds,
+ &cpds,
+ &mclkrng);
+ if (ret != 0)
+ printk(KERN_DEBUG "av8100_register_"
+ "standby_read fail\n");
+
+ /* TVout plugin change */
+ if ((cpds == 1) && (cpds != cpds_old)) {
+ cpds_old = 1;
+
+ g_av8100_status.av8100_plugin_status |=
+ AV8100_CVBS_PLUGIN;
+
+ /* TODO: notify */
+ printk(KERN_DEBUG "TVout plugin detected\n");
+ } else if ((cpds == 0) && (cpds != cpds_old)) {
+ cpds_old = 0;
+
+ g_av8100_status.av8100_plugin_status &=
+ ~AV8100_CVBS_PLUGIN;
+
+ /* TODO: notify */
+ printk(KERN_DEBUG "TVout plugout detected\n");
+ }
-#if 0
- struct av8100_data *av8100DataTemp = p;
-#endif
+ /* HDMI plugin change */
+ if ((hpds == 1) && (hpds != hpds_old)) {
+ hpds_old = 1;
-#if 0
- char val = 0x0;
- int retval = AV8100_OK;
- char val1 = 0x0;
-
- //printk("av8100_intr_handler is called\n");
- //mdelay(100);
-
- av8100_read_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, &val);
- printk("av8100_intr_handler is called, val:%x, av8100Data->client:%x\n",val, av8100DataTemp->client);
- if (start == 0/*val && HDMI_HOTPLUG_INTERRUPT*/)
- {
- printk("hdmi cable plugin interrupt\n");
- g_av8100_plugin_status = AV8100_HDMI_PLUGIN;
- av8100_set_state(AV8100_OPMODE_INIT);
- val = 0x0;//~ HDMI_HOTPLUG_INTERRUPT_MASK;
- start = 1;
-
- retval = av8100_write_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, val);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to the av8100 STANDBY_PENDING_INTERRUPT_REG register\n");
- return -EFAULT;
- }
- retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_VIDEO_INPUT_FORMAT, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n");
- return -EFAULT;
- }
+ g_av8100_status.av8100_plugin_status |=
+ AV8100_HDMI_PLUGIN;
- retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n");
- return -EFAULT;
- }
+ /* TODO: notify */
+ printk(KERN_DEBUG "HDMI plugin detected\n");
+ } else if ((hpds == 0) && (hpds != hpds_old)) {
+ hpds_old = 0;
- mcde_hdmi_display_init();
- mcde_configure_hdmi_channel();
+ g_av8100_status.av8100_plugin_status &=
+ ~AV8100_HDMI_PLUGIN;
- retval = av8100_write_single_byte(av8100DataTemp, GENERAL_INTERRUPT_MASK_REG, 0x60); /* enable TE */
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to the av8100 register\n");
- return -EFAULT;
+ /* TODO: notify */
+ printk(KERN_DEBUG "HDMI plugout detected\n");
+ }
+ }
}
-
- retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n");
- return -EFAULT;
+#else
+ /* STANDBY_PENDING_INTERRUPT */
+ ret = av8100_register_standby_pending_interrupt_read(
+ &hpdi,
+ &cpdi,
+ &oni,
+ &sid);
+
+ if (ret)
+ printk(KERN_DEBUG "av8100_register_standby_"
+ "pending_interrupt_read failed\n");
+
+ if (hpdi | cpdi | oni) {
+ /* STANDBY */
+ ret = av8100_register_standby_read(
+ &cpd,
+ &stby,
+ &hpds,
+ &cpds,
+ &mclkrng);
+ if (ret)
+ printk(KERN_DEBUG "av8100_register_standby_"
+ "read fail\n");
}
-
- }
- else if (val && CVBS_PLUG_INTERRUPT) {
- g_av8100_plugin_status = AV8100_CVBS_PLUGIN;
- av8100_set_state(AV8100_OPMODE_INIT);
- val = ~CVBS_PLUG_INTERRUPT_MASK;
- av8100_write_single_byte(av8100DataTemp->client, STANDBY_PENDING_INTERRUPT_REG, val);
- }
- else {
- g_av8100_plugin_status = AV8100_PLUGIN_NONE;
- }
-
- retval = av8100_read_single_byte(av8100DataTemp->client, 0x0/*STANDBY_PENDING_INTERRUPT_REG*/, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the STANDBY_PENDING_INTERRUPT_REG\n");
- return -EFAULT;
- }
-
- printk("av8100_read_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, &val1)\n");
- retval = av8100_read_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, &val1);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the GENERAL_INTERRUPT_REG\n");
- return -EFAULT;
- }
-
- if(val1 && TE_INTERRUPT_MASK)
- {
- //printk("Received the TE interrupt\n");
- retval = av8100_write_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, TE_INTERRUPT_MASK);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to the av8100 GENERAL_INTERRUPT_REG register\n");
- return -EFAULT;
+ if (cpdi) {
+ /* TVout plugin change */
+ if (cpds)
+ g_av8100_status.av8100_plugin_status |=
+ AV8100_CVBS_PLUGIN;
+ else
+ g_av8100_status.av8100_plugin_status &=
+ ~AV8100_CVBS_PLUGIN;
+
+ /* TODO: notify */
+ printk(KERN_DEBUG "TVout plugin: %d\n", (
+ g_av8100_status.av8100_plugin_status &
+ AV8100_CVBS_PLUGIN) == AV8100_CVBS_PLUGIN);
+ } else if (hpdi) {
+ /* HDMI plugin change */
+ if (hpds)
+ g_av8100_status.av8100_plugin_status |=
+ AV8100_HDMI_PLUGIN;
+ else
+ g_av8100_status.av8100_plugin_status &=
+ ~AV8100_HDMI_PLUGIN;
+
+ /* TODO: notify */
+ printk(KERN_DEBUG "HDMI plugin: %d\n", (
+ g_av8100_status.av8100_plugin_status &
+ AV8100_HDMI_PLUGIN) == AV8100_HDMI_PLUGIN);
}
- }
- if(val1 && UNDER_OVER_FLOW_INTERRUPT_MASK)
- {
- //printk("Received the underflow/overflow interrupt\n");
- retval = av8100_write_single_byte(av8100DataTemp->client, GENERAL_INTERRUPT_REG, UNDER_OVER_FLOW_INTERRUPT_MASK);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to the av8100 GENERAL_INTERRUPT_REG register\n");
- return -EFAULT;
+ if (hpdi | cpdi | oni) {
+ /* Clear pending interrupts */
+ ret = av8100_register_standby_pending_interrupt_write(
+ hpdi,
+ cpdi,
+ oni);
+ if (ret)
+ printk(KERN_DEBUG "av8100_register_standby_"
+ "read fail\n");
}
- }
#endif
+ av8100_flag = 0;
+ }
-#ifdef AV8100_USE_KERNEL_THREAD
- av8100_flag = 1;
+ return ret;
+}
+
+static irqreturn_t av8100_intr_handler(int irq, void *p)
+{
+ av8100_flag |= AV8100_INT_EVENT;
wake_up_interruptible(&av8100_event);
-#else
- u8500_mcde_tasklet_4(0);
-#endif
return IRQ_HANDLED;
}
-
-/**
- * av8100_configure_hdmi() - To configure the av8100 chip for hdmi.
- * @av8100Data:av8100 data
- *
- * This funtion configures the video input, video output, test pattern and hdmi on commands.
- **/
-static void av8100_configure_hdmi(struct i2c_client *i2c)
+static u16 av8100_get_te_line_nb(
+ enum av8100_output_CEA_VESA output_video_format)
{
- char val = 0x0;
- int retval = AV8100_OK;
+ u16 retval;
-#if 0
- av8100_read_single_byte(i2c, STANDBY_PENDING_INTERRUPT_REG, &val);
- printk("av8100_intr_handler is called, val:%x, av8100Data->client:%x\n",val, i2c);
-#endif
+ switch (output_video_format) {
+ case AV8100_CEA1_640X480P_59_94HZ:
+ case AV8100_CEA2_3_720X480P_59_94HZ:
+ retval = AV8100_TE_LINE_NB_30;
+ break;
- retval = av8100_write_single_byte(i2c, STANDBY_PENDING_INTERRUPT_REG, val);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to the av8100 STANDBY_PENDING_INTERRUPT_REG register\n");
- return;
- }
+ case AV8100_CEA5_1920X1080I_60HZ:
+ case AV8100_CEA6_7_NTSC_60HZ:
+ case AV8100_CEA20_1920X1080I_50HZ:
+ retval = AV8100_TE_LINE_NB_18;
+ break;
-#ifndef TEST_PATTERN_TEST
- retval = av8100_send_command (i2c, AV8100_COMMAND_VIDEO_INPUT_FORMAT,/*DSI_INTERFACE*/I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_VIDEO_INPUT_FORMAT command\n");
- return;
- }
+ case AV8100_CEA4_1280X720P_60HZ:
+ retval = AV8100_TE_LINE_NB_21;
+ break;
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- retval = av8100_send_command (i2c, AV8100_COMMAND_COLORSPACECONVERSION, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_COLORSPACECONVERSION command\n");
- return;
- }
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
+ case AV8100_CEA17_18_720X576P_50HZ:
+ retval = AV8100_TE_LINE_NB_40;
+ break;
-#else /* TEST_PATTERN_TEST */
-#ifndef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
+ case AV8100_CEA19_1280X720P_50HZ:
+ retval = AV8100_TE_LINE_NB_22;
+ break;
- retval = av8100_send_command (i2c, AV8100_COMMAND_PATTERNGENERATOR, /*DSI_INTERFACE*/I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_PATTERNGENERATOR command\n");
- return;
- }
-#endif /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
-#endif
- retval = av8100_send_command (i2c, AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_VIDEO_OUTPUT_FORMAT command\n");
- return;
- }
-#ifndef TEST_PATTERN_TEST
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI
- mcde_hdmi_display_init_video_mode();
+ case AV8100_CEA21_22_576I_PAL_50HZ:
+ /* Different values below come from LLD,
+ * TODO: check if this is really needed
+ * if not merge with AV8100_CEA6_7_NTSC_60HZ case
+ */
+#ifdef CONFIG_AV8100_SDTV
+ retval = AV8100_TE_LINE_NB_18;
+#else
+ retval = AV8100_TE_LINE_NB_17;
#endif
- retval = av8100_send_command (i2c, AV8100_COMMAND_AUDIO_INPUT_FORMAT, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_AUDIO_INPUT_FORMAT command\n");
- return;
+ break;
+
+ case AV8100_CEA32_1920X1080P_24HZ:
+ case AV8100_CEA33_1920X1080P_25HZ:
+ case AV8100_CEA34_1920X1080P_30HZ:
+ retval = AV8100_TE_LINE_NB_38;
+ break;
+
+ case AV8100_CEA60_1280X720P_24HZ:
+ case AV8100_CEA62_1280X720P_30HZ:
+ retval = AV8100_TE_LINE_NB_21;
+ break;
+
+ case AV8100_CEA14_15_480p_60HZ:
+ case AV8100_VESA14_848X480P_60HZ:
+ case AV8100_CEA61_1280X720P_25HZ:
+ case AV8100_CEA16_1920X1080P_60HZ:
+ case AV8100_CEA31_1920x1080P_50Hz:
+ case AV8100_CEA29_30_576P_50HZ:
+ case AV8100_VESA9_800X600P_60_32HZ:
+ case AV8100_VESA16_1024X768P_60HZ:
+ case AV8100_VESA22_1280X768P_59_99HZ:
+ case AV8100_VESA23_1280X768P_59_87HZ:
+ case AV8100_VESA27_1280X800P_59_91HZ:
+ case AV8100_VESA28_1280X800P_59_81HZ:
+ case AV8100_VESA39_1360X768P_60_02HZ:
+ case AV8100_VESA81_1366X768P_59_79HZ:
+ default:
+ /* TODO */
+ retval = AV8100_TE_LINE_NB_14;
+ break;
}
-#endif /* TEST_PATTERN_TEST */
- av8100_configure_denc(av8100Data);
- return;
+
+ return retval;
}
-static void av8100_configure_denc(struct av8100_data *av8100DataTemp)
+static u16 av8100_get_ui_x4(
+ enum av8100_output_CEA_VESA output_video_format)
{
- if (AV8100_OK != av8100_send_command(av8100DataTemp->client,
- AV8100_COMMAND_DENC, I2C_INTERFACE)) {
- printk("Failed to send the AV8100_COMMAND_DENC command\n");
- }
- return;
+ return AV8100_UI_X4_DEFAULT;
}
-static void av8100_hdmi_on(struct av8100_data *av8100DataTemp)
+static int av8100_config_video_output_dep(enum av8100_output_CEA_VESA
+ output_format)
{
- int retval = AV8100_OK;
+ int retval = 0;
+ union av8100_configuration config;
+
+ /* video input */
+ config.video_input_format.dsi_input_mode =
+ AV8100_HDMI_DSI_COMMAND_MODE;
+ config.video_input_format.input_pixel_format = AV8100_INPUT_PIX_RGB565;
+ config.video_input_format.total_horizontal_pixel =
+ av8100_all_cea[output_format].htotale;
+ config.video_input_format.total_horizontal_active_pixel =
+ av8100_all_cea[output_format].hactive;
+ config.video_input_format.total_vertical_lines =
+ av8100_all_cea[output_format].vtotale;
+ config.video_input_format.total_vertical_active_lines =
+ av8100_all_cea[output_format].vactive;
+
+ switch (output_format) {
+ case AV8100_CEA5_1920X1080I_60HZ:
+ case AV8100_CEA20_1920X1080I_50HZ:
+ case AV8100_CEA21_22_576I_PAL_50HZ:
+ case AV8100_CEA6_7_NTSC_60HZ:
+ config.video_input_format.video_mode =
+ AV8100_VIDEO_INTERLACE;
+ break;
- HDMI_TRACE;
- hdmi_cmd.hdmi_mode = AV8100_HDMI_ON;
- hdmi_cmd.hdmi_format = AV8100_HDMI;
+ default:
+ config.video_input_format.video_mode =
+ AV8100_VIDEO_PROGRESSIVE;
+ break;
+ }
- retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_HDMI command\n");
- return;
+ config.video_input_format.nb_data_lane =
+ AV8100_DATA_LANES_USED_2;
+ config.video_input_format.nb_virtual_ch_command_mode = 0;
+ config.video_input_format.nb_virtual_ch_video_mode = 0;
+ config.video_input_format.ui_x4 = av8100_get_ui_x4(output_format);
+ config.video_input_format.TE_line_nb = av8100_get_te_line_nb(
+ output_format);
+ config.video_input_format.TE_config = AV8100_TE_IT_LINE;
+ config.video_input_format.master_clock_freq = 0;
+
+ retval = av8100_configuration_prepare(
+ AV8100_COMMAND_VIDEO_INPUT_FORMAT, &config);
+
+ /* DENC */
+ switch (output_format) {
+ case AV8100_CEA21_22_576I_PAL_50HZ:
+ config.denc_format.cvbs_video_format = AV8100_CVBS_625;
+ config.denc_format.standard_selection = AV8100_PAL_BDGHI;
+ break;
+
+ case AV8100_CEA6_7_NTSC_60HZ:
+ config.denc_format.cvbs_video_format = AV8100_CVBS_525;
+ config.denc_format.standard_selection = AV8100_NTSC_M;
+ break;
+
+ default:
+ /* Not supported */
+ break;
}
- return;
+
+ return retval;
}
-static void av8100_hdmi_off(struct av8100_data *av8100DataTemp)
+static int av8100_config_init(void)
{
- int retval = AV8100_OK;
+ int retval = 0;
+ union av8100_configuration config;
- HDMI_TRACE;
- hdmi_cmd.hdmi_mode = AV8100_HDMI_OFF;
- hdmi_cmd.hdmi_format = AV8100_HDMI;
+ printk(KERN_DEBUG "%s\n", __func__);
- retval = av8100_send_command (av8100DataTemp->client, AV8100_COMMAND_HDMI, I2C_INTERFACE);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the AV8100_COMMAND_HDMI command\n");
- return;
+ av8100_config = kzalloc(sizeof(struct av8100_config_t), GFP_KERNEL);
+ if (!av8100_config) {
+ pr_err("%s: Failed to allocate config\n", __func__);
+ return AV8100_FAIL;
}
- return;
-}
-/**
- * configure_av8100_video_input() - This function will be used to configure the video input of AV8100.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_video_input(char* buffer_temp)
-{
- int retval = AV8100_OK;
-
- HDMI_TRACE;
- buffer_temp[0] = hdmi_video_input_cmd.dsi_input_mode;//mcde_get_dsi_mode_config();
- buffer_temp[1] = hdmi_video_input_cmd.input_pixel_format;//mcde_get_input_bpp();
- buffer_temp[2] = REG_16_8_MSB(hdmi_video_input_cmd.total_horizontal_pixel);
- buffer_temp[3] = REG_16_8_LSB(hdmi_video_input_cmd.total_horizontal_pixel);
- buffer_temp[4] = REG_16_8_MSB(hdmi_video_input_cmd.total_horizontal_active_pixel);
- buffer_temp[5] = REG_16_8_LSB(hdmi_video_input_cmd.total_horizontal_active_pixel);
-
- buffer_temp[6] = REG_16_8_MSB(hdmi_video_input_cmd.total_vertical_lines);
- buffer_temp[7] = REG_16_8_LSB(hdmi_video_input_cmd.total_vertical_lines);
- buffer_temp[8] = REG_16_8_MSB(hdmi_video_input_cmd.total_vertical_active_lines);
- buffer_temp[9] = REG_16_8_LSB(hdmi_video_input_cmd.total_vertical_active_lines);
- buffer_temp[10] = hdmi_video_input_cmd.video_mode;//mcde_get_hdmi_scan_mode();
- buffer_temp[11] = hdmi_video_input_cmd.nb_data_lane;//AV8100_DATA_LANES_USED_2;
- buffer_temp[12] = hdmi_video_input_cmd.nb_virtual_ch_command_mode;
- buffer_temp[13] = hdmi_video_input_cmd.nb_virtual_ch_video_mode;
- buffer_temp[14] = REG_16_8_MSB(hdmi_video_input_cmd.TE_line_nb);
- buffer_temp[15] = REG_16_8_LSB(hdmi_video_input_cmd.TE_line_nb);
- buffer_temp[16] = hdmi_video_input_cmd.TE_config;
- buffer_temp[17] = REG_32_8_MSB(hdmi_video_input_cmd.master_clock_freq);
- buffer_temp[18] = REG_32_8_MMSB(hdmi_video_input_cmd.master_clock_freq);
- buffer_temp[19] = REG_32_8_MLSB(hdmi_video_input_cmd.master_clock_freq);
- buffer_temp[20] = REG_32_8_LSB(hdmi_video_input_cmd.master_clock_freq);
- buffer_temp[21] = hdmi_video_input_cmd.ui_x4; /* UI value */
-
- g_av8100_cmd_length = AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE - 1;
+ memset(&config, 0, sizeof(union av8100_configuration));
+ memset(av8100_config, 0, sizeof(union av8100_configuration));
+
+ /* Color conversion */
+ config.color_space_conversion_format.c0 = 0xFFDA;
+ config.color_space_conversion_format.c1 = 0xFFB6;
+ config.color_space_conversion_format.c2 = 0x0070;
+ config.color_space_conversion_format.c3 = 0x0042;
+ config.color_space_conversion_format.c4 = 0x0081;
+ config.color_space_conversion_format.c5 = 0x0019;
+ config.color_space_conversion_format.c6 = 0x0070;
+ config.color_space_conversion_format.c7 = 0xFFA2;
+ config.color_space_conversion_format.c8 = 0xFFEE;
+ config.color_space_conversion_format.aoffset = 0x007F;
+ config.color_space_conversion_format.boffset = 0x0010;
+ config.color_space_conversion_format.coffset = 0x007F;
+ config.color_space_conversion_format.lmax = 0xEB;
+ config.color_space_conversion_format.lmin = 0x10;
+ config.color_space_conversion_format.cmax = 0xF0;
+ config.color_space_conversion_format.cmin = 0x10;
+ retval = av8100_configuration_prepare(
+ AV8100_COMMAND_COLORSPACECONVERSION, &config);
+ if (retval)
+ return AV8100_FAIL;
+
+ /* DENC */
+ config.denc_format.cvbs_video_format = AV8100_CVBS_625;
+ config.denc_format.standard_selection = AV8100_PAL_BDGHI;
+ config.denc_format.on_off = 0;
+ config.denc_format.macrovision_on_off = 0;
+ config.denc_format.internal_generator = 0;
+
+ /* Video output */
+ config.video_output_format.video_output_cea_vesa =
+ AV8100_CEA4_1280X720P_60HZ;
+
+ retval = av8100_configuration_prepare(
+ AV8100_COMMAND_VIDEO_OUTPUT_FORMAT, &config);
+ if (retval)
+ return AV8100_FAIL;
+
+ /* Video input */
+ av8100_config_video_output_dep(
+ config.video_output_format.video_output_cea_vesa);
+
+ /* Pattern generator */
+ config.pattern_generator_format.pattern_audio_mode =
+ AV8100_PATTERN_AUDIO_OFF;
+ config.pattern_generator_format.pattern_type =
+ AV8100_PATTERN_GENERATOR;
+ config.pattern_generator_format.pattern_video_format =
+ AV8100_PATTERN_720P;
+ retval = av8100_configuration_prepare(AV8100_COMMAND_PATTERNGENERATOR,
+ &config);
+ if (retval)
+ return AV8100_FAIL;
+
+ /* Audio input */
+ config.audio_input_format.audio_input_if_format =
+ AV8100_AUDIO_I2SDELAYED_MODE;
+ config.audio_input_format.i2s_input_nb = 1;
+ config.audio_input_format.sample_audio_freq = AV8100_AUDIO_FREQ_48KHZ;
+ config.audio_input_format.audio_word_lg = AV8100_AUDIO_16BITS;
+ config.audio_input_format.audio_format = AV8100_AUDIO_LPCM_MODE;
+ config.audio_input_format.audio_if_mode = AV8100_AUDIO_MASTER;
+ config.audio_input_format.audio_mute = AV8100_AUDIO_MUTE_DISABLE;
+ retval = av8100_configuration_prepare(
+ AV8100_COMMAND_AUDIO_INPUT_FORMAT, &config);
+ if (retval)
+ return AV8100_FAIL;
+
+ /* HDMI mode */
+ config.hdmi_format.hdmi_mode = AV8100_HDMI_ON;
+ config.hdmi_format.hdmi_format = AV8100_HDMI;
+ config.hdmi_format.dvi_format = AV8100_DVI_CTRL_CTL0;
+ retval = av8100_configuration_prepare(AV8100_COMMAND_HDMI, &config);
+ if (retval)
+ return AV8100_FAIL;
+
+ /* EDID section readback */
+ config.edid_section_readback_format.address = 0xA0;
+ config.edid_section_readback_format.block_number = 0;
+ retval = av8100_configuration_prepare(
+ AV8100_COMMAND_EDID_SECTION_READBACK, &config);
+ if (retval)
+ return AV8100_FAIL;
+
return retval;
+}
+static void av8100_config_exit(void)
+{
+ printk(KERN_DEBUG "%s\n", __func__);
+
+ kfree(av8100_config);
+ av8100_config = NULL;
+}
+
+static void av8100_set_state(enum av8100_operating_mode state)
+{
+ g_av8100_status.av8100_state = state;
}
+
/**
- * configure_av8100_audio_output() - This function will be used to configure the audio input of AV8100.
- * @buffer_temp: configuration pointer
+ * write_single_byte() - Write a single byte to av8100
+ * through i2c interface.
+ * @client: i2c client structure
+ * @reg: register offset
+ * @data: data byte to be written
*
+ * This funtion uses smbus byte write API to write a single byte to av8100
**/
-static int configure_av8100_audio_input(char* buffer_temp)
+static int write_single_byte(struct i2c_client *client, u8 reg,
+ u8 data)
{
- int retval = AV8100_OK;
+ int ret;
- HDMI_TRACE;
- buffer_temp[0] = hdmi_audio_input_cmd.audio_input_if_format;
- buffer_temp[1] = hdmi_audio_input_cmd.i2s_input_nb;
- buffer_temp[2] = hdmi_audio_input_cmd.sample_audio_freq;
- buffer_temp[3] = hdmi_audio_input_cmd.audio_word_lg;
- buffer_temp[4] = hdmi_audio_input_cmd.audio_format;
- buffer_temp[5] = hdmi_audio_input_cmd.audio_if_mode;
- buffer_temp[6] = hdmi_audio_input_cmd.audio_mute;
+ ret = i2c_smbus_write_byte_data(client, reg, data);
+ if (ret < 0)
+ printk(KERN_DEBUG "i2c smbus write byte failed\n");
- g_av8100_cmd_length = AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE - 1;
- return retval;
+ return ret;
}
/**
- * configure_av8100_video_output() - This function will be used to configure the video output of AV8100.
- * @buffer_temp: configuration pointer
+ * read_single_byte() - read single byte from av8100
+ * through i2c interface
+ * @client: i2c client structure
+ * @reg: register offset
+ * @val: register value
*
+ * This funtion uses smbus read block API to read single byte from the reg
+ * offset.
**/
-static int configure_av8100_video_output(char* buffer_temp)
-{
- int retval = AV8100_OK;
-
- HDMI_TRACE;
- buffer_temp[0] = hdmi_video_output_cmd.video_output_cea_vesa;
-
- if (buffer_temp[0] == AV8100_CUSTOM) {
- buffer_temp[1] = hdmi_video_output_cmd.vsync_polarity;
- buffer_temp[2] = hdmi_video_output_cmd.hsync_polarity;
- buffer_temp[3] = REG_16_8_MSB(hdmi_video_output_cmd.total_horizontal_pixel);
- buffer_temp[4] = REG_16_8_LSB(hdmi_video_output_cmd.total_horizontal_pixel);
- buffer_temp[5] = REG_16_8_MSB(hdmi_video_output_cmd.total_horizontal_active_pixel);
- buffer_temp[6] = REG_16_8_LSB(hdmi_video_output_cmd.total_horizontal_active_pixel);
- buffer_temp[7] = REG_16_8_MSB(hdmi_video_output_cmd.total_vertical_in_half_lines);
- buffer_temp[8] = REG_16_8_LSB(hdmi_video_output_cmd.total_vertical_in_half_lines);
- buffer_temp[9] = REG_16_8_MSB(hdmi_video_output_cmd.total_vertical_active_in_half_lines);
- buffer_temp[10] = REG_16_8_LSB(hdmi_video_output_cmd.total_vertical_active_in_half_lines);
- buffer_temp[11] = REG_16_8_MSB(hdmi_video_output_cmd.hsync_start_in_pixel);
- buffer_temp[12] = REG_16_8_LSB(hdmi_video_output_cmd.hsync_start_in_pixel);
- buffer_temp[13] = REG_16_8_MSB(hdmi_video_output_cmd.hsync_length_in_pixel);
- buffer_temp[14] = REG_16_8_LSB(hdmi_video_output_cmd.hsync_length_in_pixel);
- buffer_temp[15] = REG_16_8_MSB(hdmi_video_output_cmd.vsync_start_in_half_line);
- buffer_temp[16] = REG_16_8_LSB(hdmi_video_output_cmd.vsync_start_in_half_line);
- buffer_temp[17] = REG_16_8_MSB(hdmi_video_output_cmd.vsync_length_in_half_line);
- buffer_temp[18] = REG_16_8_LSB(hdmi_video_output_cmd.vsync_length_in_half_line);
- buffer_temp[19] = REG_32_8_MSB(hdmi_video_output_cmd.pixel_clock_freq_Hz);
- buffer_temp[20] = REG_32_8_MMSB(hdmi_video_output_cmd.pixel_clock_freq_Hz);
- buffer_temp[21] = REG_32_8_MLSB(hdmi_video_output_cmd.pixel_clock_freq_Hz);
- buffer_temp[22] = REG_32_8_LSB(hdmi_video_output_cmd.pixel_clock_freq_Hz);
-
- g_av8100_cmd_length = AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE - 1;
- }
- else {
- g_av8100_cmd_length = 1;
+static int read_single_byte(struct i2c_client *client, u8 reg, u8 *val)
+{
+ int value;
+
+ value = i2c_smbus_read_byte_data(client, reg);
+ if (value < 0) {
+ printk(KERN_DEBUG "i2c smbus read byte failed,read data = %x "
+ "from offset:%x\n" , value, reg);
+ return AV8100_FAIL;
}
- return retval;
+ *val = (u8) value;
+ return 0;
}
/**
- * configure_av8100_video_scaling() - This function will be used to configure the video scaling params of AV8100.
- * @buffer_temp: configuration pointer
+ * write_multi_byte() - Write a multiple bytes to av8100 through
+ * i2c interface.
+ * @client: i2c client structure
+ * @buf: buffer to be written
+ * @nbytes: nunmber of bytes to be written
*
+ * This funtion uses smbus block write API's to write n number of bytes to the
+ * av8100
**/
-static int configure_av8100_video_scaling(char* buffer_temp)
+static int write_multi_byte(struct i2c_client *client, u8 reg,
+ u8 *buf, u8 nbytes)
{
- int retval = AV8100_OK;
+ int ret;
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE - 1;
- return retval;
+ ret = i2c_smbus_write_i2c_block_data(client, reg, nbytes, buf);
+ if (ret < 0)
+ printk(KERN_DEBUG "i2c smbus write multi byte error\n");
+
+ return ret;
}
-/**
- * configure_av8100_colorspace_conversion() - This function will be used to configure the color conversion params of AV8100.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_colorspace_conversion(char* buffer_temp)
-{
- int retval = AV8100_OK;
- int i = 0;
-
- HDMI_TRACE;
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c0);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c0);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c1);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c1);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c2);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c2);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c3);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c3);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c4);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c4);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c5);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c5);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c6);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c6);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c7);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c7);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c8);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c8);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.a_offset);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.a_offset);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.b_offset);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.b_offset);
- buffer_temp[i++] = REG_16_8_MSB(hdmi_color_conversion_cmd.c_offset);
- buffer_temp[i++] = REG_16_8_LSB(hdmi_color_conversion_cmd.c_offset);
- buffer_temp[i++] = hdmi_color_conversion_cmd.l_max;
- buffer_temp[i++] = hdmi_color_conversion_cmd.l_min;
- buffer_temp[i++] = hdmi_color_conversion_cmd.c_max;
- buffer_temp[i++] = hdmi_color_conversion_cmd.c_min;
- g_av8100_cmd_length = i;
- return retval;
+static int configuration_video_input_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_video_input_cmd.dsi_input_mode;
+ buffer[1] = av8100_config->hdmi_video_input_cmd.input_pixel_format;
+ buffer[2] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd.
+ total_horizontal_pixel);
+ buffer[3] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd.
+ total_horizontal_pixel);
+ buffer[4] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd.
+ total_horizontal_active_pixel);
+ buffer[5] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd.
+ total_horizontal_active_pixel);
+ buffer[6] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd.
+ total_vertical_lines);
+ buffer[7] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd.
+ total_vertical_lines);
+ buffer[8] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd.
+ total_vertical_active_lines);
+ buffer[9] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd.
+ total_vertical_active_lines);
+ buffer[10] = av8100_config->hdmi_video_input_cmd.video_mode;
+ buffer[11] = av8100_config->hdmi_video_input_cmd.nb_data_lane;
+ buffer[12] = av8100_config->hdmi_video_input_cmd.
+ nb_virtual_ch_command_mode;
+ buffer[13] = av8100_config->hdmi_video_input_cmd.
+ nb_virtual_ch_video_mode;
+ buffer[14] = REG_16_8_MSB(av8100_config->hdmi_video_input_cmd.
+ TE_line_nb);
+ buffer[15] = REG_16_8_LSB(av8100_config->hdmi_video_input_cmd.
+ TE_line_nb);
+ buffer[16] = av8100_config->hdmi_video_input_cmd.TE_config;
+ buffer[17] = REG_32_8_MSB(av8100_config->hdmi_video_input_cmd.
+ master_clock_freq);
+ buffer[18] = REG_32_8_MMSB(av8100_config->hdmi_video_input_cmd.
+ master_clock_freq);
+ buffer[19] = REG_32_8_MLSB(av8100_config->hdmi_video_input_cmd.
+ master_clock_freq);
+ buffer[20] = REG_32_8_LSB(av8100_config->hdmi_video_input_cmd.
+ master_clock_freq);
+ buffer[21] = av8100_config->hdmi_video_input_cmd.ui_x4;
+
+ *length = AV8100_COMMAND_VIDEO_INPUT_FORMAT_SIZE - 1;
+ return 0;
+
}
-/**
- * configure_av8100_cec_message_write() - This function will be used to configure the CEC message to AV8100.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_cec_message_write(char* buffer_temp)
+static int configuration_audio_input_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_audio_input_cmd.
+ audio_input_if_format;
+ buffer[1] = av8100_config->hdmi_audio_input_cmd.i2s_input_nb;
+ buffer[2] = av8100_config->hdmi_audio_input_cmd.sample_audio_freq;
+ buffer[3] = av8100_config->hdmi_audio_input_cmd.audio_word_lg;
+ buffer[4] = av8100_config->hdmi_audio_input_cmd.audio_format;
+ buffer[5] = av8100_config->hdmi_audio_input_cmd.audio_if_mode;
+ buffer[6] = av8100_config->hdmi_audio_input_cmd.audio_mute;
+
+ *length = AV8100_COMMAND_AUDIO_INPUT_FORMAT_SIZE - 1;
+ return 0;
+}
+
+static int configuration_video_output_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_video_output_cmd.
+ video_output_cea_vesa;
+
+ if (buffer[0] == AV8100_CUSTOM) {
+ buffer[1] = av8100_config->hdmi_video_output_cmd.
+ vsync_polarity;
+ buffer[2] = av8100_config->hdmi_video_output_cmd.
+ hsync_polarity;
+ buffer[3] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.total_horizontal_pixel);
+ buffer[4] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.total_horizontal_pixel);
+ buffer[5] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.total_horizontal_active_pixel);
+ buffer[6] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.total_horizontal_active_pixel);
+ buffer[7] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.total_vertical_in_half_lines);
+ buffer[8] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.total_vertical_in_half_lines);
+ buffer[9] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.
+ total_vertical_active_in_half_lines);
+ buffer[10] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.
+ total_vertical_active_in_half_lines);
+ buffer[11] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.hsync_start_in_pixel);
+ buffer[12] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.hsync_start_in_pixel);
+ buffer[13] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.hsync_length_in_pixel);
+ buffer[14] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.hsync_length_in_pixel);
+ buffer[15] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.vsync_start_in_half_line);
+ buffer[16] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.vsync_start_in_half_line);
+ buffer[17] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.vsync_length_in_half_line);
+ buffer[18] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.vsync_length_in_half_line);
+ buffer[19] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.hor_video_start_pixel);
+ buffer[20] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.hor_video_start_pixel);
+ buffer[21] = REG_16_8_MSB(av8100_config->
+ hdmi_video_output_cmd.vert_video_start_pixel);
+ buffer[22] = REG_16_8_LSB(av8100_config->
+ hdmi_video_output_cmd.vert_video_start_pixel);
+ buffer[23] = av8100_config->
+ hdmi_video_output_cmd.video_type;
+ buffer[24] = av8100_config->
+ hdmi_video_output_cmd.pixel_repeat;
+ buffer[25] = REG_32_8_MSB(av8100_config->
+ hdmi_video_output_cmd.pixel_clock_freq_Hz);
+ buffer[26] = REG_32_8_MMSB(av8100_config->
+ hdmi_video_output_cmd.pixel_clock_freq_Hz);
+ buffer[27] = REG_32_8_MLSB(av8100_config->
+ hdmi_video_output_cmd.pixel_clock_freq_Hz);
+ buffer[28] = REG_32_8_LSB(av8100_config->
+ hdmi_video_output_cmd.pixel_clock_freq_Hz);
+
+ *length = AV8100_COMMAND_VIDEO_OUTPUT_FORMAT_SIZE - 1;
+ } else {
+ *length = 1;
+ }
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_CEC_MESSAGEWRITE_SIZE;
- return retval;
+ return 0;
}
-/**
- * configure_av8100_cec_message_read() - This function will be used to read CEC message from AV8100.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_cec_message_read(char* buffer_temp)
+static int configuration_video_scaling_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ h_start_in_pixel);
+ buffer[1] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ h_start_in_pixel);
+ buffer[2] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ h_stop_in_pixel);
+ buffer[3] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ h_stop_in_pixel);
+ buffer[4] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ v_start_in_line);
+ buffer[5] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ v_start_in_line);
+ buffer[6] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ v_stop_in_line);
+ buffer[7] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ v_stop_in_line);
+ buffer[8] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ h_start_out_pixel);
+ buffer[9] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd
+ .h_start_out_pixel);
+ buffer[10] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ h_stop_out_pixel);
+ buffer[11] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ h_stop_out_pixel);
+ buffer[12] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ v_start_out_line);
+ buffer[13] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ v_start_out_line);
+ buffer[14] = REG_16_8_MSB(av8100_config->hdmi_video_scaling_cmd.
+ v_stop_out_line);
+ buffer[15] = REG_16_8_LSB(av8100_config->hdmi_video_scaling_cmd.
+ v_stop_out_line);
+
+ *length = AV8100_COMMAND_VIDEO_SCALING_FORMAT_SIZE - 1;
+ return 0;
+}
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_CEC_MESSAGEREAD_BACK_SIZE;
- return retval;
+static int configuration_colorspace_conversion_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c0);
+ buffer[1] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c0);
+ buffer[2] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c1);
+ buffer[3] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c1);
+ buffer[4] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c2);
+ buffer[5] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c2);
+ buffer[6] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c3);
+ buffer[7] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c3);
+ buffer[8] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c4);
+ buffer[9] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c4);
+ buffer[10] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c5);
+ buffer[11] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c5);
+ buffer[12] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c6);
+ buffer[13] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c6);
+ buffer[14] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c7);
+ buffer[15] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c7);
+ buffer[16] = REG_10_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c8);
+ buffer[17] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.c8);
+ buffer[18] = REG_16_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.aoffset);
+ buffer[19] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.aoffset);
+ buffer[20] = REG_16_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.boffset);
+ buffer[21] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.boffset);
+ buffer[22] = REG_16_8_MSB(av8100_config->
+ hdmi_color_space_conversion_cmd.coffset);
+ buffer[23] = REG_16_8_LSB(av8100_config->
+ hdmi_color_space_conversion_cmd.coffset);
+ buffer[24] = av8100_config->hdmi_color_space_conversion_cmd.lmax;
+ buffer[25] = av8100_config->hdmi_color_space_conversion_cmd.lmin;
+ buffer[26] = av8100_config->hdmi_color_space_conversion_cmd.cmax;
+ buffer[27] = av8100_config->hdmi_color_space_conversion_cmd.cmin;
+
+ *length = AV8100_COMMAND_COLORSPACECONVERSION_SIZE - 1;
+ return 0;
}
-/**
- * configure_av8100_denc() - This function will be used to configure the denc,
- * which is used for SDTV (CVBS).
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_denc(char* buffer_temp)
+static int configuration_cec_message_write_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
- HDMI_TRACE;
+ buffer[0] = av8100_config->hdmi_cec_message_write_cmd.buffer_length;
+ memcpy(&buffer[1], av8100_config->hdmi_cec_message_write_cmd.buffer,
+ HDMI_CEC_MESSAGE_WRITE_BUFFER_SIZE);
- /* Start with PAL std format */
- buffer_temp[0] = hdmi_denc_cmd.tv_lines;
- buffer_temp[1] = hdmi_denc_cmd.tv_std;
- buffer_temp[2] = hdmi_denc_cmd.denc;
- buffer_temp[3] = hdmi_denc_cmd.macrovision;
- buffer_temp[4] = hdmi_denc_cmd.internal_generator;
- buffer_temp[5] = hdmi_denc_cmd.chroma;
+ *length = AV8100_COMMAND_CEC_MESSAGE_WRITE_SIZE - 1;
+ return 0;
+}
- g_av8100_cmd_length = AV8100_COMMAND_DENC_SIZE - 1;
- return retval;
+static int configuration_cec_message_read_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ /* No buffer data */
+ *length = AV8100_COMMAND_CEC_MESSAGE_READ_BACK_SIZE - 1;
+ return 0;
}
-/**
- * configure_av8100_hdmi() - This function will be used to configure the HDMI .
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_hdmi(char* buffer_temp)
+static int configuration_denc_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
- HDMI_TRACE;
- buffer_temp[0] = hdmi_cmd.hdmi_mode;
- buffer_temp[1] = hdmi_cmd.hdmi_format;
- buffer_temp[2] = hdmi_cmd.dvi_format;
+ buffer[0] = av8100_config->hdmi_denc_cmd.cvbs_video_format;
+ buffer[1] = av8100_config->hdmi_denc_cmd.standard_selection;
+ buffer[2] = av8100_config->hdmi_denc_cmd.on_off;
+ buffer[3] = av8100_config->hdmi_denc_cmd.macrovision_on_off;
+ buffer[4] = av8100_config->hdmi_denc_cmd.internal_generator;
- g_av8100_cmd_length = AV8100_COMMAND_HDMI_SIZE - 1;
- return retval;
+ *length = AV8100_COMMAND_DENC_SIZE - 1;
+ return 0;
}
-/**
- * configure_av8100_hdcp_senkey() - This function will be used to configure the hdcp send key.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_hdcp_senkey(char* buffer_temp)
+static int configuration_hdmi_get(char *buffer, unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_HDCP_SENDKEY_SIZE;
- return retval;
+ buffer[0] = av8100_config->hdmi_cmd.hdmi_mode;
+ buffer[1] = av8100_config->hdmi_cmd.hdmi_format;
+ buffer[2] = av8100_config->hdmi_cmd.dvi_format;
+
+ *length = AV8100_COMMAND_HDMI_SIZE - 1;
+ return 0;
}
-/**
- * configure_av8100_hdcp_management() - This function will be used to configure the hdcp management.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_hdcp_management(char* buffer_temp)
+static int configuration_hdcp_sendkey_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_HDCP_MANAGEMENT_SIZE;
- return retval;
+ buffer[0] = av8100_config->hdmi_hdcp_send_key_cmd.key_number;
+ buffer[1] = 0;
+ memcpy(&buffer[2], av8100_config->hdmi_hdcp_send_key_cmd.key,
+ HDMI_HDCP_SEND_KEY_SIZE);
+
+ *length = AV8100_COMMAND_HDCP_SENDKEY_SIZE - 1;
+ return 0;
}
-/**
- * configure_av8100_infoframe() - This function will be used to configure the info frame.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_infoframe(char* buffer_temp)
+static int configuration_hdcp_management_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_hdcp_management_format_cmd.
+ request_hdcp_revocation_list;
+ buffer[1] = av8100_config->hdmi_hdcp_management_format_cmd.
+ request_encrypted_transmission;
+ buffer[2] = av8100_config->hdmi_hdcp_management_format_cmd.
+ oess_eess_encryption_use;
+
+ *length = AV8100_COMMAND_HDCP_MANAGEMENT_SIZE - 1;
+ return 0;
+}
+
+static int configuration_infoframe_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_infoframes_cmd.type;
+ buffer[1] = av8100_config->hdmi_infoframes_cmd.version;
+ buffer[2] = av8100_config->hdmi_infoframes_cmd.length;
+ buffer[3] = av8100_config->hdmi_infoframes_cmd.crc;
+ memcpy(&buffer[4], av8100_config->hdmi_infoframes_cmd.data,
+ HDMI_INFOFRAME_DATA_SIZE);
+
+ *length = AV8100_COMMAND_INFOFRAMES_SIZE - 1;
+ return 0;
+}
+
+static int av8100_edid_section_readback_get(char *buffer, unsigned int *length)
+{
+ buffer[0] = av8100_config->hdmi_edid_section_readback_cmd.address;
+ buffer[1] = av8100_config->hdmi_edid_section_readback_cmd.
+ block_number;
+
+ *length = AV8100_COMMAND_EDID_SECTION_READBACK_SIZE - 1;
+ return 0;
+}
+
+static int configuration_pattern_generator_get(char *buffer,
+ unsigned int *length)
+{
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_pattern_generator_cmd.pattern_type;
+ buffer[1] = av8100_config->hdmi_pattern_generator_cmd.
+ pattern_video_format;
+ buffer[2] = av8100_config->hdmi_pattern_generator_cmd.
+ pattern_audio_mode;
+
+ *length = AV8100_COMMAND_PATTERNGENERATOR_SIZE - 1;
+ return 0;
+}
+
+static int configuration_fuse_aes_key_get(char *buffer,
+ unsigned int *length)
{
- int retval = AV8100_OK;
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ buffer[0] = av8100_config->hdmi_fuse_aes_key_cmd.fuse_operation;
+ memcpy(&buffer[1], av8100_config->hdmi_fuse_aes_key_cmd.key,
+ HDMI_FUSE_AES_KEY_SIZE);
+
+ *length = AV8100_COMMAND_FUSE_AES_KEY_SIZE - 1;
+ return 0;
+}
+
+static int get_command_return_data(struct i2c_client *i2c,
+ enum av8100_command_type command_type,
+ u8 *command_buffer,
+ u8 *buffer_length,
+ u8 *buffer)
+{
+ int retval = 0;
+ char val;
+ int index = 0;
+
+ /* Get the first return byte */
+ retval = read_single_byte(i2c, AV8100_COMMAND_OFFSET, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ if (val != (0x80 | command_type)) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ switch (command_type) {
+ case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
+ case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
+ case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
+ case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
+ case AV8100_COMMAND_COLORSPACECONVERSION:
+ case AV8100_COMMAND_CEC_MESSAGE_WRITE:
+ case AV8100_COMMAND_DENC:
+ case AV8100_COMMAND_HDMI:
+ case AV8100_COMMAND_HDCP_SENDKEY:
+ case AV8100_COMMAND_INFOFRAMES:
+ case AV8100_COMMAND_PATTERNGENERATOR:
+ /* Get the second return byte */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ if (val) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+ break;
+
+ case AV8100_COMMAND_CEC_MESSAGE_READ_BACK:
+ if ((buffer == NULL) || (buffer_length == NULL)) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ /* Get the return buffer length */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 3, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ *buffer_length = val;
+
+ if (*buffer_length >
+ HDMI_CEC_MESSAGE_READBACK_MAXSIZE) {
+ printk(KERN_DEBUG "CEC size too large %d\n",
+ *buffer_length);
+ *buffer_length = HDMI_CEC_MESSAGE_READBACK_MAXSIZE;
+ }
+
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "return data: ");
+#endif
+
+ /* Get the return buffer */
+ for (index = 0; index < *buffer_length; ++index) {
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 4 + index,
+ &val);
+ if (retval) {
+ *buffer_length = 0;
+ goto get_command_return_data_fail;
+ } else {
+ *(buffer + index) = val;
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "%02x ", *(buffer + index));
+#endif
+ }
+ }
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "\n");
+#endif
+ break;
+
+ case AV8100_COMMAND_HDCP_MANAGEMENT:
+ if ((buffer == NULL) || (buffer_length == NULL) ||
+ (command_buffer == NULL)) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ /* Get the second return byte */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, &val);
+ if (retval) {
+ goto get_command_return_data_fail;
+ } else {
+ /* Check the second return byte */
+ if (val)
+ goto get_command_return_data_fail;
+ }
+
+ /* Get the return buffer length */
+ if (command_buffer[0] ==
+ HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT) {
+ *buffer_length = 0x1F;
+ } else {
+ *buffer_length = 0x0;
+ }
+
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "return data: ");
+#endif
+ /* Get the return buffer */
+ for (index = 0; index < *buffer_length; ++index) {
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 2 + index,
+ &val);
+ if (retval) {
+ *buffer_length = 0;
+ goto get_command_return_data_fail;
+ } else {
+ *(buffer + index) = val;
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "%02x ", *(buffer + index));
+#endif
+ }
+ }
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "\n");
+#endif
+ break;
+
+ case AV8100_COMMAND_EDID_SECTION_READBACK:
+ if ((buffer == NULL) || (buffer_length == NULL)) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ /* Return buffer length is fixed */
+ *buffer_length = 0x80;
+
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "return data: ");
+#endif
+ /* Get the return buffer */
+ for (index = 0; index < *buffer_length; ++index) {
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1 + index,
+ &val);
+ if (retval) {
+ *buffer_length = 0;
+ goto get_command_return_data_fail;
+ } else {
+ *(buffer + index) = val;
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "%02x ", *(buffer + index));
+#endif
+ }
+ }
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "\n");
+#endif
+ break;
+
+ case AV8100_COMMAND_FUSE_AES_KEY:
+ if ((buffer == NULL) || (buffer_length == NULL)) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ /* Get the second return byte */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ /* Check the second return byte */
+ if (val) {
+ retval = AV8100_FAIL;
+ goto get_command_return_data_fail;
+ }
+
+ /* Return buffer length is fixed */
+ *buffer_length = 0x2;
+
+ /* Get CRC */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ *(buffer + 0) = val;
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "CRC:%02x ", val);
+#endif
+
+ /* Get programmed status */
+ retval = read_single_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, &val);
+ if (retval)
+ goto get_command_return_data_fail;
+
+ *(buffer + 1) = val;
+#ifdef AV8100_DEBUG_EXTRA
+ printk(KERN_DEBUG "programmed:%02x ", val);
+#endif
+ break;
+
+ default:
+ retval = AV8100_INVALID_COMMAND;
+ break;
+ }
- HDMI_TRACE;
- g_av8100_cmd_length = AV8100_COMMAND_INFOFRAMES_SIZE;
+ return retval;
+get_command_return_data_fail:
+ printk(KERN_DEBUG "get_command_return_data FAIL\n");
return retval;
}
-/**
- * configure_av8100_pattern_generator() - This function will be used to configure the pattern generator.
- * @buffer_temp: configuration pointer
- *
- **/
-static int configure_av8100_pattern_generator(char* buffer_temp)
+int av8100_powerup(void)
{
- int retval = AV8100_OK;
+ int retval = 0;
+ struct i2c_client *i2c;
+ u8 cpd;
+ u8 stby;
+ u8 hpds;
+ u8 cpds;
+ u8 mclkrng;
+ u8 off_time;
+ u8 on_time;
+ u8 fdl;
+ u8 hld;
+ u8 wa;
+ u8 ra;
+
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ i2c = av8100_config->client;
+
+ /* Reset av8100 */
+ gpio_set_value(GPIO_AV8100_RSTN, 1);
+ av8100_set_state(AV8100_OPMODE_STANDBY);
+
+ /* Master clock timing, running, search for plug */
+ retval = av8100_register_standby_write(AV8100_STANDBY_CPD_HIGH,
+ AV8100_STANDBY_STBY_HIGH, AV8100_MASTER_CLOCK_TIMING);
+ if (retval) {
+ pr_err("Failed to write the value to av8100 register\n");
+ return -EFAULT;
+ }
+
+ retval = av8100_register_standby_read(&cpd, &stby, &hpds, &cpds,
+ &mclkrng);
+ if (retval) {
+ pr_err("Failed to read the value from av8100 register\n");
+ return -EFAULT;
+ } else {
+ printk(KERN_DEBUG "STANDBY_REG register cpd:%d stby:%d "
+ "hpds:%d cpds:%d mclkrng:%0x\n", cpd, stby, hpds,
+ cpds, mclkrng);
+ }
+
+ /* ON time & OFF time on 5v HDMI plug detect */
+ retval = av8100_register_hdmi_5_volt_time_write(AV8100_OFF_TIME,
+ AV8100_ON_TIME);
+ if (retval) {
+ pr_err("Failed to write the value to av8100 register\n");
+ return -EFAULT;
+ }
+
+ retval = av8100_register_hdmi_5_volt_time_read(&off_time, &on_time);
+ if (retval) {
+ pr_err("Failed to read the value from av8100 register\n");
+ return -EFAULT;
+ } else {
+ printk(KERN_DEBUG "AV8100_5_VOLT_TIME_REG register "
+ "off_time:%0x on_time:%0x\n", off_time, on_time);
+ }
+
+ /* Device in hold mode, enable firmware download*/
+ retval = av8100_register_general_control_write(
+ AV8100_GENERAL_CONTROL_FDL_HIGH,
+ AV8100_GENERAL_CONTROL_HLD_HIGH,
+ AV8100_GENERAL_CONTROL_WA_LOW,
+ AV8100_GENERAL_CONTROL_RA_LOW);
+ if (retval) {
+ pr_err("Failed to write the value to av8100 register\n");
+ return -EFAULT;
+ }
- HDMI_TRACE;
- buffer_temp[0] = hdmi_pattern_generator_cmd.pattern_type;
- buffer_temp[1] = hdmi_pattern_generator_cmd.pattern_video_format;
- buffer_temp[2] = hdmi_pattern_generator_cmd.pattern_audio_mode;
+ retval = av8100_register_general_control_read(&fdl, &hld, &wa, &ra);
+ if (retval) {
+ pr_err("Failed to read the value from av8100 register\n");
+ return -EFAULT;
+ } else {
+ printk(KERN_DEBUG "GENERAL_CONTROL_REG register fdl:%d "
+ "hld:%d wa:%d ra:%d\n", fdl, hld, wa, ra);
+ }
- g_av8100_cmd_length = AV8100_COMMAND_PATTERNGENERATOR_SIZE - 1;
+ av8100_set_state(AV8100_OPMODE_SCAN);
return retval;
}
-/**
- * read_edid_info() - This function will be used to EDID info.
- * @i2c: i2c client device
- * @buff: pointer to EDID buffer
- *
- **/
-#if 0
-static int read_edid_info(struct i2c_client *i2c, char* buff)
+int av8100_powerdown(void)
{
-int retval = AV8100_OK;
-return retval;
+ gpio_set_value(GPIO_AV8100_RSTN, 0);
+ av8100_set_state(AV8100_OPMODE_SHUTDOWN);
+
+ return 0;
}
-#endif
-/**
- * av8100_download_firmware() - This function will be used to download firmware.
- * @i2c: i2c client device
- * @fw_buff: pointer to firmware buffer
- * @numOfBytes: number of bytes
- *
- **/
-static int av8100_download_firmware(struct i2c_client *i2c, char regOffset, char* fw_buff, int numOfBytes, enum interface if_type)
+int av8100_download_firmware(char *fw_buff, int nbytes,
+ enum interface_type if_type)
{
- int retval = AV8100_OK;
+ int retval = 0;
int temp = 0x0;
- int increment = 15, index = 0;
- int size = 0x0, tempnext = 0x0;
- char val = 0x0 ;
+ int increment = 15;
+ int index = 0;
+ int size = 0x0;
+ int tempnext = 0x0;
+ char val = 0x0;
char CheckSum = 0;
int cnt = 10;
+ struct i2c_client *i2c;
+ u8 cecrec;
+ u8 cectrx;
+ u8 uc;
+ u8 onuvb;
+ u8 hdcps;
+
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_download_firmware_out;
+ }
- temp = numOfBytes % increment;
- for(size=0;size<(numOfBytes-temp);size=size+increment, index+=increment)
- {
- if(if_type == I2C_INTERFACE) {
- retval = av8100_write_multi_byte(i2c, regOffset, fw_buff + size, increment);
- if(retval != AV8100_OK) {
- printk("Failed to download the av8100 firmware\n");
- return -EFAULT;
- }
- }
- else if(if_type == DSI_INTERFACE) {
- retval = dsiLPdcslongwrite(0, 0x10, DCS_FW_DOWNLOAD,fw_buff[index],fw_buff[index + 1],fw_buff[index + 2],
- fw_buff[index + 3],fw_buff[index + 4],fw_buff[index + 5],fw_buff[index + 6],fw_buff[index + 7], fw_buff[index + 8],
- fw_buff[index + 9],fw_buff[index + 10],fw_buff[index + 11],fw_buff[index + 12],fw_buff[index + 13], fw_buff[index + 14],
- CHANNEL_A, DSI_LINK2);
- if(retval != AV8100_OK) {
- printk("Failed to send the data through dsi interface\n");
- return retval;
+ if (fw_buff == NULL) {
+ /* use default fw buffer */
+ fw_buff = av8100_fw_buff;
+ nbytes = AV8100_FW_SIZE;
+ }
+
+ i2c = av8100_config->client;
+
+ LOCK_AV8100_HW;
+
+ temp = nbytes % increment;
+ for (size = 0; size < (nbytes-temp); size = size + increment,
+ index += increment) {
+ if (if_type == I2C_INTERFACE) {
+ retval = write_multi_byte(i2c,
+ AV8100_FIRMWARE_DOWNLOAD_ENTRY, fw_buff + size,
+ increment);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to download the "
+ "av8100 firmware\n");
+ retval = -EFAULT;
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
}
+ } else if (if_type == DSI_INTERFACE) {
+ printk(KERN_DEBUG "DSI_INTERFACE is currently not supported\n");
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
+ } else {
+ retval = AV8100_INVALID_INTERFACE;
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
}
- else
- return AV8100_INVALID_INTERFACE;
- for(tempnext=size;tempnext<(increment+size);tempnext++)
- ReceiveTab[tempnext] = fw_buff[tempnext];
+ for (tempnext = size; tempnext < (increment+size); tempnext++)
+ av8100_receivetab[tempnext] = fw_buff[tempnext];
}
- // Transfer last firmware bytes
- if(if_type == I2C_INTERFACE) {
- retval = av8100_write_multi_byte(i2c, regOffset, fw_buff + size, temp);
- if(retval != AV8100_OK) {
- printk("Failed to download the av8100 firmware\n");
- return -EFAULT;
- }
- }
- else if(if_type == DSI_INTERFACE) {
- retval = dsiLPdcslongwrite(0, temp+1, DCS_FW_DOWNLOAD,fw_buff[index],fw_buff[index + 1],fw_buff[index + 2],
- fw_buff[index + 3],fw_buff[index + 4],fw_buff[index + 5],fw_buff[index + 6],fw_buff[index + 7], fw_buff[index + 8],
- fw_buff[index + 9],fw_buff[index + 10],fw_buff[index + 11],fw_buff[index + 12],fw_buff[index + 13], fw_buff[index + 14],
- CHANNEL_A, DSI_LINK2);
-
- if(retval != AV8100_OK) {
- printk("Failed to send the data through dsi interface\n");
- return retval;
+ /* Transfer last firmware bytes */
+ if (if_type == I2C_INTERFACE) {
+ retval = write_multi_byte(i2c,
+ AV8100_FIRMWARE_DOWNLOAD_ENTRY, fw_buff + size, temp);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to download the av8100 firmware\n");
+ retval = -EFAULT;
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
}
+ } else if (if_type == DSI_INTERFACE) {
+ /* TODO: Add support for DSI firmware download */
+ retval = AV8100_INVALID_INTERFACE;
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
+ } else {
+ retval = AV8100_INVALID_INTERFACE;
+ UNLOCK_AV8100_HW;
+ goto av8100_download_firmware_out;
}
- else
- return AV8100_INVALID_INTERFACE;
- for(tempnext=size;tempnext<(size+temp);tempnext++) {
- ReceiveTab[tempnext] = fw_buff[tempnext];
- }
+ for (tempnext = size; tempnext < (size+temp); tempnext++)
+ av8100_receivetab[tempnext] = fw_buff[tempnext];
- // check transfer
- for(size=0;size<numOfBytes;size++) {
+ /* check transfer*/
+ for (size = 0; size < nbytes; size++) {
CheckSum = CheckSum ^ fw_buff[size];
- if(ReceiveTab[size] != fw_buff[size]) {
- printk(">Fw download fail....i=%d\n",size);
- printk("Transm = %x, Receiv = %x\n",fw_buff[size],ReceiveTab[size]);
+ if (av8100_receivetab[size] != fw_buff[size]) {
+ printk(KERN_DEBUG ">Fw download fail....i=%d\n", size);
+ printk(KERN_DEBUG "Transm = %x, Receiv = %x\n",
+ fw_buff[size], av8100_receivetab[size]);
}
}
- retval = av8100_read_single_byte(i2c, regOffset, &val);
- if(retval != AV8100_OK) {
- printk("Failed to read the value in to the av8100 register\n");
- return -EFAULT;
+ UNLOCK_AV8100_HW;
+
+ retval = av8100_register_firmware_download_entry_read(&val);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to read the value from the av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_download_firmware_out;
}
- printk("CheckSum:%x,val:%x\n",CheckSum,val);
+ printk(KERN_DEBUG "CheckSum:%x,val:%x\n", CheckSum, val);
- if(CheckSum != val) {
- printk(">Fw downloading.... FAIL CheckSum issue\n");
- printk("Checksum = %d\n",CheckSum);
- printk("Checksum read: %d\n",val);
- return AV8100_FWDOWNLOAD_FAIL;
+ if (CheckSum != val) {
+ printk(KERN_DEBUG ">Fw downloading.... FAIL CheckSum issue\n");
+ printk(KERN_DEBUG "Checksum = %d\n", CheckSum);
+ printk(KERN_DEBUG "Checksum read: %d\n", val);
+ retval = AV8100_FWDOWNLOAD_FAIL;
+ goto av8100_download_firmware_out;
+ } else {
+ printk(KERN_DEBUG ">Fw downloading.... success\n");
}
- else
- printk(">Fw downloading.... success\n");
/* Set to idle mode */
- retval = av8100_write_single_byte(i2c, GENERAL_CONTROL_REG, 0x0);
- if(retval != AV8100_OK) {
- printk("Failed to write the value in to the av8100 registers\n");
- return -EFAULT;
+ av8100_register_general_control_write(AV8100_GENERAL_CONTROL_FDL_LOW,
+ AV8100_GENERAL_CONTROL_HLD_LOW, AV8100_GENERAL_CONTROL_WA_LOW,
+ AV8100_GENERAL_CONTROL_RA_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to the av8100 registers\n");
+ retval = -EFAULT;
+ goto av8100_download_firmware_out;
}
/* Wait Internal Micro controler ready */
cnt = 3;
- retval = av8100_read_single_byte(i2c, GENERAL_STATUS_REG, &val);
- while((retval == AV8100_OK) && (val != AV8100_GENERAL_STATUS_UC_READY) && (cnt-- > 0)) {
- printk("av8100 wait2\n");
+ retval = av8100_register_general_status_read(&cecrec, &cectrx, &uc,
+ &onuvb, &hdcps);
+ while ((retval == 0) && (uc != 0x1) && (cnt-- > 0)) {
+ printk(KERN_DEBUG "av8100 wait2\n");
/* TODO */
- for(temp=0;temp<0xFFFFF;temp++);
+ for (temp = 0; temp < 0xFFFFF; temp++)
+ ;
- retval = av8100_read_single_byte(i2c, GENERAL_STATUS_REG, &val);
+ retval = av8100_register_general_status_read(&cecrec, &cectrx,
+ &uc, &onuvb, &hdcps);
}
- if(retval != AV8100_OK) {
- printk("Failed to read the value in to the av8100 register\n");
- return -EFAULT;
+ if (retval) {
+ printk(KERN_DEBUG "Failed to read the value from the av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_download_firmware_out;
}
av8100_set_state(AV8100_OPMODE_IDLE);
+
+av8100_download_firmware_out:
return retval;
}
-/**
- * av8100_send_command() - This function will be used to send the command to AV8100.
- * @i2cClient: i2c client device
- * @command_type: command type
- * @if_type: interface type.
- *
- **/
-static int av8100_send_command (struct i2c_client *i2cClient, char command_type, enum interface if_type)
+int av8100_disable_interrupt(void)
{
- int retval = AV8100_OK, temp = 0, index = 0;
- char val = 0x0, val1 = 0x0;
- //char val2 = 0x0, val3 = 0x0;
- int reg_offset = AV8100_COMMAND_OFFSET + 1;
- char buffer[AV8100_COMMAND_MAX_LENGTH];
+ int retval;
+ struct i2c_client *i2c;
- g_av8100_cmd_length=0;
- memset(buffer, 0x00, AV8100_COMMAND_MAX_LENGTH);
- switch(command_type)
- {
- case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
- configure_av8100_video_input(buffer);
- break;
- case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
- configure_av8100_audio_input(buffer);
- break;
- case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
- configure_av8100_video_output(buffer);
- break;
- case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
- configure_av8100_video_scaling(buffer);
- break;
- case AV8100_COMMAND_COLORSPACECONVERSION:
- configure_av8100_colorspace_conversion(buffer);
- break;
- case AV8100_COMMAND_CEC_MESSAGEWRITE:
- configure_av8100_cec_message_write(buffer);
- break;
- case AV8100_COMMAND_CEC_MESSAGEREAD_BACK:
- configure_av8100_cec_message_read(buffer);
- break;
- case AV8100_COMMAND_DENC:
- configure_av8100_denc(buffer);
- break;
- case AV8100_COMMAND_HDMI:
- configure_av8100_hdmi(buffer);
- break;
- case AV8100_COMMAND_HDCP_SENDKEY:
- configure_av8100_hdcp_senkey(buffer);
- break;
- case AV8100_COMMAND_HDCP_MANAGEMENT:
- configure_av8100_hdcp_management(buffer);
- break;
- case AV8100_COMMAND_INFOFRAMES:
- configure_av8100_infoframe(buffer);
- break;
- case AV8100_COMMAND_EDID_SECTIONREADBACK:
- break;
- case AV8100_COMMAND_PATTERNGENERATOR:
- configure_av8100_pattern_generator(buffer);
- break;
- default:
- printk(KERN_INFO "Invalid command type\n");
- retval = AV8100_INVALID_COMMAND;
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_disable_interrupt_out;
+ }
+ i2c = av8100_config->client;
+
+ retval = av8100_register_standby_pending_interrupt_write(
+ AV8100_STANDBY_PENDING_INTERRUPT_HPDI_LOW,
+ AV8100_STANDBY_PENDING_INTERRUPT_CPDI_LOW,
+ AV8100_STANDBY_PENDING_INTERRUPT_ONI_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_disable_interrupt_out;
}
-#ifdef HDMI_LOGGING
- PRNK_COL(PRNK_COL_YELLOW);
- printk(KERN_DEBUG "HDMI send cmd parameters: ");
- { int i;
- for (i = 0; i < g_av8100_cmd_length; i++)
- printk("0x%02x ", buffer[i]);
+ retval = av8100_register_general_interrupt_mask_write(
+ AV8100_GENERAL_INTERRUPT_MASK_EOCM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_VSIM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_VSOM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_CECM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_HDCPM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_UOVBM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_TEM_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_disable_interrupt_out;
}
- printk("\n");
- printk(KERN_DEBUG "HDMI send cmd: 0x%02x\n", command_type);
- PRNK_COL(PRNK_COL_WHITE);
-#endif /* HDMI_LOGGING */
- if(if_type == I2C_INTERFACE)
- {
- /* writing the command configuration */
- retval = av8100_write_multi_byte(i2cClient, reg_offset, buffer, g_av8100_cmd_length);
- if(retval != AV8100_OK)
- return retval;
- /* writing the command */
- retval = av8100_write_single_byte(i2cClient, AV8100_COMMAND_OFFSET, command_type);
- if(retval != AV8100_OK)
- return retval;
- mdelay(10);
- retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET, &val);
- if(retval != AV8100_OK)
- return retval;
+ retval = av8100_register_standby_interrupt_mask_write(
+ AV8100_STANDBY_INTERRUPT_MASK_HPDM_LOW,
+ AV8100_STANDBY_INTERRUPT_MASK_CPDM_LOW,
+ AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_INPUT,
+ AV8100_STANDBY_INTERRUPT_MASK_IPOL_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_disable_interrupt_out;
+ }
- if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier
- return AV8100_COMMAND_FAIL;
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+ del_timer(&av8100_timer);
+#endif
- retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET+1, &val1);
- if(retval != AV8100_OK)
- return retval;
+av8100_disable_interrupt_out:
+ return retval;
+}
- if(val1 != AV8100_OK) // 0x11
- return AV8100_COMMAND_FAIL;
+int av8100_enable_interrupt(void)
+{
+ int retval;
+ struct i2c_client *i2c;
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_enable_interrupt_out;
+ }
- }else
- if(if_type == DSI_INTERFACE)
- {
- get_dcs_data_index_params();
- for (temp = 0, index = 0; temp < g_dcs_data_count_index; temp++, /*index++*/ index +=15)
- {
-#if 0
- retval = dsiLPdcslongwrite(0, 0x10, DCS_WRITE_UC,buffer[index],buffer[++index],buffer[++index],
- buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index],
- buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index],
- CHANNEL_A, DSI_LINK2);
-
- if(retval != AV8100_OK)
- {
- printk("Failed to send the data through dsi interface\n");
- return retval;
- }
-#endif
- mcde_send_hdmi_cmd_data(&buffer[index],0x10, DCS_WRITE_UC);
+ i2c = av8100_config->client;
- }
- if(g_dcs_data_count_last != 0)
- {
-#if 0
- retval = dsiLPdcslongwrite(0, g_dcs_data_count_last+1, DCS_WRITE_UC,buffer[index],buffer[++index],buffer[++index],
- buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index],
- buffer[++index],buffer[++index],buffer[++index],buffer[++index],buffer[++index], buffer[++index],
- CHANNEL_A, DSI_LINK2);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the data through dsi interface\n");
- return retval;
- }
-#endif
+ retval = av8100_register_standby_pending_interrupt_write(
+ AV8100_STANDBY_PENDING_INTERRUPT_HPDI_LOW,
+ AV8100_STANDBY_PENDING_INTERRUPT_CPDI_LOW,
+ AV8100_STANDBY_PENDING_INTERRUPT_ONI_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_enable_interrupt_out;
+ }
- mcde_send_hdmi_cmd_data(&buffer[index],g_dcs_data_count_last+1, DCS_WRITE_UC);
- }
-#if 0
- retval = dsiLPdcsshortwrite1parm(0, DCS_EXEC_UC,command_type, CHANNEL_A, DSI_LINK2);
- if(retval != AV8100_OK)
- {
- printk("Failed to send the command through dsi interface\n");
- return retval;
- }
-#endif
-#if 0
- mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC);
- dsireaddata(&val, &val1, &val2, &val3, CHANNEL_A, DSI_LINK2);
- printk("data read from dsi val:%x, val1:%x\n",val, val1);
- if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier
- return AV8100_COMMAND_FAIL;
- if(val1 != AV8100_OK) // 0x11
- return AV8100_COMMAND_FAIL;
- mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC);
-#endif
-#if 0
- /* writing the command */
- retval = av8100_write_single_byte(i2cClient, AV8100_COMMAND_OFFSET, command_type);
- if(retval != AV8100_OK)
- return retval;
+ retval = av8100_register_general_interrupt_mask_write(
+ AV8100_GENERAL_INTERRUPT_MASK_EOCM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_VSIM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_VSOM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_CECM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_HDCPM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_UOVBM_LOW,
+ AV8100_GENERAL_INTERRUPT_MASK_TEM_HIGH);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_enable_interrupt_out;
+ }
+
+ retval = av8100_register_standby_interrupt_mask_write(
+ AV8100_STANDBY_INTERRUPT_MASK_HPDM_LOW,
+ AV8100_STANDBY_INTERRUPT_MASK_CPDM_LOW,
+ AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_INPUT,
+ AV8100_STANDBY_INTERRUPT_MASK_IPOL_LOW);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_enable_interrupt_out;
+ }
+
+#ifdef AV8100_PLUGIN_DETECT_VIA_TIMER_INTERRUPTS
+ init_timer(&av8100_timer);
+ av8100_timer.expires = jiffies + AV8100_TIMER_INTERRUPT_POLLING_TIME;
+ av8100_timer.function = av8100_timer_int;
+ av8100_timer.data = 0;
+ add_timer(&av8100_timer);
#endif
- mcde_send_hdmi_cmd(&command_type,2, DCS_EXEC_UC);
- mdelay(10);
- retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET, &val);
- if(retval != AV8100_OK)
- return retval;
- printk("value:%x\n", val);
- if(val != (0x80 | command_type)) //0x10 == 0x80 | Identifier
- return AV8100_COMMAND_FAIL;
- retval = av8100_read_single_byte(i2cClient, AV8100_COMMAND_OFFSET+1, &val1);
- if(retval != AV8100_OK)
- return retval;
-printk("value1:%x\n", val1);
- if(val1 != AV8100_OK) // 0x11
- return AV8100_COMMAND_FAIL;
+av8100_enable_interrupt_out:
+ return retval;
+}
-printk("sending command is successful!!!val:%x, val1:%x\n", val, val1);
- }else
- {
- retval = AV8100_INVALID_INTERFACE;
- printk(KERN_INFO "Invalid command type\n");
+static int register_write_internal(u8 offset, u8 value)
+{
+ int retval;
+ struct i2c_client *i2c;
+
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_register_write_out;
+ }
+
+ i2c = av8100_config->client;
+
+ /* Write to register */
+ retval = write_single_byte(i2c, offset, value);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
}
+
+av8100_register_write_out:
return retval;
}
-/**
- *
- * av8100_powerdown() - This function will be used to powerdown the AV8100.
- * @i2c: i2c client device
- * @id: device id
- *
- **/
-static int av8100_powerdown(void)
+int av8100_register_standby_write(
+ u8 cpd, u8 stby, u8 mclkrng)
{
- int retval = AV8100_OK;
+ int retval;
+ u8 val;
- /** reset the av8100 */
- gpio_set_value(GPIO_AV8100_RSTN,GPIO_LOW);
+ LOCK_AV8100_HW;
- av8100_set_state(AV8100_OPMODE_SHUTDOWN);
+ /* Set register value */
+ val = AV8100_STANDBY_CPD(cpd) | AV8100_STANDBY_STBY(stby) |
+ AV8100_STANDBY_MCLKRNG(mclkrng);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_STANDBY, val);
+ UNLOCK_AV8100_HW;
return retval;
}
-/**
- *
- * av8100_powerup() - This function will be used to powerup the AV8100.
- * @i2c: i2c client device
- * @id: device id
- *
- **/
-static int av8100_powerup(struct i2c_client *i2c, const struct i2c_device_id *id)
+int av8100_register_hdmi_5_volt_time_write(u8 off_time, u8 on_time)
{
- int retval = AV8100_OK;
- char val = 0x0;
+ int retval;
+ u8 val;
- /* configuration length */
- g_av8100_cmd_length = 6;
- /** reset the av8100 */
- gpio_set_value(GPIO_AV8100_RSTN, 1);
- av8100_set_state(AV8100_OPMODE_STANDBY);
+ LOCK_AV8100_HW;
- retval = av8100_write_single_byte(i2c, STANDBY_REG, 0x3B); /* Device runing, master clock = 38.4Mhz, Enable searching CVBS cable*/
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
- }
+ /* Set register value */
+ val = AV8100_HDMI_5_VOLT_TIME_OFF_TIME(off_time) |
+ AV8100_HDMI_5_VOLT_TIME_ON_TIME(on_time);
- retval = av8100_read_single_byte(i2c, STANDBY_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the value in to av8100 register\n");
- return -EFAULT;
- }else
- printk("STANDBY_REG register value:%0x\n",val);
+ /* Write to register */
+ retval = register_write_internal(AV8100_HDMI_5_VOLT_TIME, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- retval = av8100_write_single_byte(i2c, AV8100_5_VOLT_TIME_REG, 0x20); /* Define ON TIME & OFF time on 5v HDMI plug detect*/
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
+int av8100_register_standby_interrupt_mask_write(
+ u8 hpdm, u8 cpdm, u8 stbygpiocfg, u8 ipol)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_STANDBY_INTERRUPT_MASK_HPDM(hpdm) |
+ AV8100_STANDBY_INTERRUPT_MASK_CPDM(cpdm) |
+ AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG(stbygpiocfg) |
+ AV8100_STANDBY_INTERRUPT_MASK_IPOL(ipol);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_STANDBY_INTERRUPT_MASK, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_standby_pending_interrupt_write(
+ u8 hpdi, u8 cpdi, u8 oni)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_STANDBY_PENDING_INTERRUPT_HPDI(hpdi) |
+ AV8100_STANDBY_PENDING_INTERRUPT_CPDI(cpdi) |
+ AV8100_STANDBY_PENDING_INTERRUPT_ONI(oni);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_STANDBY_PENDING_INTERRUPT, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_general_interrupt_mask_write(
+ u8 eocm, u8 vsim, u8 vsom, u8 cecm, u8 hdcpm, u8 uovbm, u8 tem)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_GENERAL_INTERRUPT_MASK_EOCM(eocm) |
+ AV8100_GENERAL_INTERRUPT_MASK_VSIM(vsim) |
+ AV8100_GENERAL_INTERRUPT_MASK_VSOM(vsom) |
+ AV8100_GENERAL_INTERRUPT_MASK_CECM(cecm) |
+ AV8100_GENERAL_INTERRUPT_MASK_HDCPM(hdcpm) |
+ AV8100_GENERAL_INTERRUPT_MASK_UOVBM(uovbm) |
+ AV8100_GENERAL_INTERRUPT_MASK_TEM(tem);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_GENERAL_INTERRUPT_MASK, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_general_interrupt_write(
+ u8 eoci, u8 vsii, u8 vsoi, u8 ceci, u8 hdcpi, u8 uovbi)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_GENERAL_INTERRUPT_EOCI(eoci) |
+ AV8100_GENERAL_INTERRUPT_VSII(vsii) |
+ AV8100_GENERAL_INTERRUPT_VSOI(vsoi) |
+ AV8100_GENERAL_INTERRUPT_CECI(ceci) |
+ AV8100_GENERAL_INTERRUPT_HDCPI(hdcpi) |
+ AV8100_GENERAL_INTERRUPT_UOVBI(uovbi);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_GENERAL_INTERRUPT, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_gpio_configuration_write(
+ u8 dat3dir, u8 dat3val, u8 dat2dir, u8 dat2val, u8 dat1dir,
+ u8 dat1val, u8 ucdbg)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_GPIO_CONFIGURATION_DAT3DIR(dat3dir) |
+ AV8100_GPIO_CONFIGURATION_DAT3VAL(dat3val) |
+ AV8100_GPIO_CONFIGURATION_DAT2DIR(dat2dir) |
+ AV8100_GPIO_CONFIGURATION_DAT2VAL(dat2val) |
+ AV8100_GPIO_CONFIGURATION_DAT1DIR(dat1dir) |
+ AV8100_GPIO_CONFIGURATION_DAT1VAL(dat1val) |
+ AV8100_GPIO_CONFIGURATION_UCDBG(ucdbg);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_GPIO_CONFIGURATION, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_general_control_write(
+ u8 fdl, u8 hld, u8 wa, u8 ra)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_GENERAL_CONTROL_FDL(fdl) |
+ AV8100_GENERAL_CONTROL_HLD(hld) |
+ AV8100_GENERAL_CONTROL_WA(wa) |
+ AV8100_GENERAL_CONTROL_RA(ra);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_GENERAL_CONTROL, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_firmware_download_entry_write(
+ u8 mbyte_code_entry)
+{
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Set register value */
+ val = AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY(
+ mbyte_code_entry);
+
+ /* Write to register */
+ retval = register_write_internal(AV8100_FIRMWARE_DOWNLOAD_ENTRY, val);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_register_write(
+ u8 offset, u8 value)
+{
+ int retval = 0;
+ struct i2c_client *i2c;
+
+ LOCK_AV8100_HW;
+
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_register_write_out;
}
- retval = av8100_read_single_byte(i2c, AV8100_5_VOLT_TIME_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the value in to av8100 register\n");
- return -EFAULT;
- }else
- printk("AV8100_5_VOLT_TIME_REG register value:%0x\n",val);
+ i2c = av8100_config->client;
- retval = av8100_write_single_byte(i2c, GENERAL_CONTROL_REG, 0x30); /* Device in hold mode + enable firmware download*/
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
+ /* Write to register */
+ retval = write_single_byte(i2c, offset, value);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to write the value to av8100 register\n");
+ retval = -EFAULT;
}
- retval = av8100_read_single_byte(i2c, GENERAL_CONTROL_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the value in to av8100 register\n");
- return -EFAULT;
- }else
- printk("GENERAL_CONTROL_REG register value:%0x\n",val);
- av8100_set_state(AV8100_OPMODE_SCAN);
+av8100_register_write_out:
+ UNLOCK_AV8100_HW;
return retval;
}
-/**
- *
- * av8100_enable_interrupt() - This function will enable the hdmi/tvout plugin interrupts.
- * @i2c: i2c client device
- * @id: device id
- *
- **/
-static int av8100_enable_interrupt(struct i2c_client *i2c)
+int register_read_internal(u8 offset, u8 *value)
{
- int retval = AV8100_OK;
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI || \
- defined CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI|| \
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- char val = 0x0;
-#endif
+ int retval = 0;
+ struct i2c_client *i2c;
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- val = TE_INTERRUPT;
- retval = av8100_write_single_byte(i2c, GENERAL_INTERRUPT_MASK_REG, val);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_register_read_out;
}
- val = 0x0;
- retval = av8100_write_single_byte(i2c, STANDBY_INTERRUPT_MASK_REG, val);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
- }
-#endif
+ i2c = av8100_config->client;
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI
- val = 0x60;//0x60; // tearing & overflow/underflow interrupts
- retval = av8100_write_single_byte(i2c, GENERAL_INTERRUPT_MASK_REG, val);
- if(retval != AV8100_OK)
- {
- printk("Failed to write the value in to av8100 register\n");
- return -EFAULT;
+ /* Read from register */
+ retval = read_single_byte(i2c, offset, value);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to read the value from av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_register_read_out;
}
-#endif
+av8100_register_read_out:
return retval;
}
-/**
- * av8100_open() - This function will be used to open the av8100 device.
- * @inode: pointer to inode
- * @filp: pointer to file structure
- *
- **/
-static int av8100_open(struct inode *inode, struct file *filp)
+int av8100_register_standby_read(
+ u8 *cpd, u8 *stby, u8 *hpds, u8 *cpds, u8 *mclkrng)
{
- int retval = AV8100_OK;
- printk("av8100_open is called\n");
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Read from register */
+ retval = register_read_internal(AV8100_STANDBY, &val);
+
+ /* Set return params */
+ *cpd = AV8100_STANDBY_CPD_GET(val);
+ *stby = AV8100_STANDBY_STBY_GET(val);
+ *hpds = AV8100_STANDBY_HPDS_GET(val);
+ *cpds = AV8100_STANDBY_CPDS_GET(val);
+ *mclkrng = AV8100_STANDBY_MCLKRNG_GET(val);
+
+ UNLOCK_AV8100_HW;
return retval;
}
-/**
- * av8100_release() - This function will be used to close the av8100 device.
- * @inode: pointer to inode
- * @filp: pointer to file structure
- *
- **/
-static int av8100_release(struct inode *inode, struct file *filp)
+int av8100_register_hdmi_5_volt_time_read(
+ u8 *off_time, u8 *on_time)
{
- int retval = AV8100_OK;
- printk("av8100_release is called\n");
+ int retval;
+ u8 val;
+
+ LOCK_AV8100_HW;
+
+ /* Read from register */
+ retval = register_read_internal(AV8100_HDMI_5_VOLT_TIME, &val);
+
+ /* Set return params */
+ *off_time = AV8100_HDMI_5_VOLT_TIME_OFF_TIME_GET(val);
+ *on_time = AV8100_HDMI_5_VOLT_TIME_ON_TIME_GET(val);
+
+ UNLOCK_AV8100_HW;
return retval;
}
-/**
- * av8100_ioctl - This routine implements av8100 supported ioctls
- * @inode: inode pointer.
- * @file: file pointer.
- * @cmd : ioctl command.
- * @arg: input argument for ioctl.
- *
- * This Api supports the IOC_AV8100_READ_REGISTER,IOC_AV8100_WRITE_REGISTER,IOC_AV8100_SEND_CONFIGURATION_COMMAND
- * IOC_AV8100_READ_CONFIGURATION_COMMAND and IOC_AV8100_GET_STATUS ioctl commands.
- */
-static int av8100_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int retval = AV8100_OK;
- struct av8100_register internalReg;
- struct av8100_command_register commandReg;
- struct av8100_status status;
- av8100_output_CEA_VESA video_output_format;
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- mcde_video_mode mcde_mode;
-#endif
- char val = 0x0;
-
- /** Process actual ioctl */
- switch(cmd)
- {
- case IOC_AV8100_READ_REGISTER:
- if(copy_from_user(&internalReg, (void *)arg, sizeof(struct av8100_register))) {
- return -EFAULT;
- }
+int av8100_register_standby_interrupt_mask_read(
+ u8 *hpdm, u8 *cpdm, u8 *stbygpiocfg, u8 *ipol)
+{
+ int retval;
+ u8 val;
- if (internalReg.offset <= FIRMWARE_DOWNLOAD_ENTRY_REG) {
- retval = av8100_read_single_byte(av8100Data->client, internalReg.offset, &internalReg.value);
+ LOCK_AV8100_HW;
- if(retval != AV8100_OK) {
- printk("Failed to read the value in to the av8100 register\n");
- return -EFAULT;
- }
- }
- else
- return AV8100_INVALID_COMMAND;
+ /* Read from register */
+ retval = register_read_internal(AV8100_STANDBY_INTERRUPT_MASK, &val);
- if (copy_to_user((void *)arg, (void *)&internalReg, sizeof(struct av8100_register))) {
- return -EFAULT;
- }
- break;
+ /* Set return params */
+ *hpdm = AV8100_STANDBY_INTERRUPT_MASK_HPDM_GET(val);
+ *cpdm = AV8100_STANDBY_INTERRUPT_MASK_CPDM_GET(val);
+ *stbygpiocfg = AV8100_STANDBY_INTERRUPT_MASK_STBYGPIOCFG_GET(val);
+ *ipol = AV8100_STANDBY_INTERRUPT_MASK_IPOL_GET(val);
- case IOC_AV8100_WRITE_REGISTER:
- if(copy_from_user(&internalReg, (void *)arg, sizeof(struct av8100_register))) {
- return -EFAULT;
- }
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- if (internalReg.offset <= FIRMWARE_DOWNLOAD_ENTRY_REG) {
- retval = av8100_write_single_byte(av8100Data->client, internalReg.offset, internalReg.value);
- if(retval != AV8100_OK) {
- printk("Failed to write the value in to the av8100 register\n");
- return -EFAULT;
- }
- }
- else
- return AV8100_INVALID_COMMAND;
- //if(copy_to_user((void *)arg, (void *)&internalReg, sizeof(struct av8100_register))) {
- // return -EFAULT;
- //}
- break;
-
- case IOC_AV8100_SEND_CONFIGURATION_COMMAND:
- {
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_OK;
- val = 0x0;
+int av8100_register_standby_pending_interrupt_read(
+ u8 *hpdi, u8 *cpdi, u8 *oni, u8 *sid)
+{
+ int retval;
+ u8 val;
- if(copy_from_user(&commandReg, (void *)arg, sizeof(struct av8100_command_register)) != 0) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 1\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
+ LOCK_AV8100_HW;
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- if(commandReg.cmd_id >= AV8100_COMMAND_VIDEO_INPUT_FORMAT && commandReg.cmd_id <= AV8100_COMMAND_PATTERNGENERATOR) {
- /* Writing the command buffer */
- retval = av8100_write_multi_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, commandReg.buf, commandReg.buf_len);
- if(retval != AV8100_OK) {
- printk("Failed to send the command to the av8100\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
- else {
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
+ /* Read from register */
+ retval = register_read_internal(AV8100_STANDBY_PENDING_INTERRUPT, &val);
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- /* Writing the command */
- retval = av8100_write_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET, commandReg.cmd_id);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 2\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
+ /* Set return params */
+ *hpdi = AV8100_STANDBY_PENDING_INTERRUPT_HPDI_GET(val);
+ *cpdi = AV8100_STANDBY_PENDING_INTERRUPT_CPDI_GET(val);
+ *oni = AV8100_STANDBY_PENDING_INTERRUPT_ONI_GET(val);
+ *sid = AV8100_STANDBY_PENDING_INTERRUPT_SID_GET(val);
- /* TODO */
- mdelay(100);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- /* Getting the first return byte */
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 3\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- /* Checking the first return byte */
- if(val != (0x80 | commandReg.cmd_id)) { //offset 0x10 == 0x80 | Identifier
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 4 %0x\n", val);
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
- }
+int av8100_register_general_interrupt_mask_read(
+ u8 *eocm,
+ u8 *vsim,
+ u8 *vsom,
+ u8 *cecm,
+ u8 *hdcpm,
+ u8 *uovbm,
+ u8 *tem)
+{
+ int retval;
+ u8 val;
- commandReg.buf_len = 0;
-
- switch(commandReg.cmd_id) {
- case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
- case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
- case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
- case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
- case AV8100_COMMAND_COLORSPACECONVERSION:
- case AV8100_COMMAND_CEC_MESSAGEWRITE:
- case AV8100_COMMAND_DENC:
- case AV8100_COMMAND_HDMI:
- case AV8100_COMMAND_HDCP_SENDKEY:
- case AV8100_COMMAND_INFOFRAMES:
- case AV8100_COMMAND_PATTERNGENERATOR:
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- /* Getting the second return byte */
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 5\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- /* Checking the second return byte */
- if (val != AV8100_OK) {
- printk("Invalid Response for the command %0x\n", val);
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
- }
- break;
+ LOCK_AV8100_HW;
- case AV8100_COMMAND_CEC_MESSAGEREAD_BACK:
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
+ /* Read from register */
+ retval = register_read_internal(AV8100_GENERAL_INTERRUPT_MASK, &val);
-#if 0
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6a\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- printk("AV8100_COMMAND_OFFSET + 1:%x\n", val);
- }
+ /* Set return params */
+ *eocm = AV8100_GENERAL_INTERRUPT_MASK_EOCM_GET(val);
+ *vsim = AV8100_GENERAL_INTERRUPT_MASK_VSIM_GET(val);
+ *vsom = AV8100_GENERAL_INTERRUPT_MASK_VSOM_GET(val);
+ *cecm = AV8100_GENERAL_INTERRUPT_MASK_CECM_GET(val);
+ *hdcpm = AV8100_GENERAL_INTERRUPT_MASK_HDCPM_GET(val);
+ *uovbm = AV8100_GENERAL_INTERRUPT_MASK_UOVBM_GET(val);
+ *tem = AV8100_GENERAL_INTERRUPT_MASK_TEM_GET(val);
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 2, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6b\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- printk("AV8100_COMMAND_OFFSET + 2:%x\n", val);
- }
-#endif
- /* Getting the buffer length */
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 3, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 6\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- commandReg.buf_len = val;
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- if (commandReg.buf_len > HDMI_CEC_MESSAGE_READBACK_MAXSIZE) {
- printk("AV8100_COMMAND_CEC_MESSAGEREAD_BACK buf_len: %d larger than maxsize\n", commandReg.buf_len);
- commandReg.buf_len = 16;
- }
- }
- }
+int av8100_register_general_interrupt_read(
+ u8 *eoci,
+ u8 *vsii,
+ u8 *vsoi,
+ u8 *ceci,
+ u8 *hdcpi,
+ u8 *uovbi,
+ u8 *tei)
+{
+ int retval;
+ u8 val;
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- int index = 0;
-
- /* Getting the buffer */
- while ((index < commandReg.buf_len) && (index < HDMI_CEC_MESSAGE_READBACK_MAXSIZE)) {
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 4 + index, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 7\n");
- commandReg.buf_len = 0;
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- break;
- }
- else {
- commandReg.buf[index] = val;
- }
-
- index++;
- }
- }
- break;
+ LOCK_AV8100_HW;
- case AV8100_COMMAND_HDCP_MANAGEMENT:
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
+ /* Read from register */
+ retval = register_read_internal(AV8100_GENERAL_INTERRUPT, &val);
- /* Getting the second return byte */
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 5\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- else {
- /* Checking the second return byte */
- if (val != AV8100_OK) {
- printk("Invalid Response for the command\n");
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- }
- }
- }
+ /* Set return params */
+ *eoci = AV8100_GENERAL_INTERRUPT_EOCI_GET(val);
+ *vsii = AV8100_GENERAL_INTERRUPT_VSII_GET(val);
+ *vsoi = AV8100_GENERAL_INTERRUPT_VSOI_GET(val);
+ *ceci = AV8100_GENERAL_INTERRUPT_CECI_GET(val);
+ *hdcpi = AV8100_GENERAL_INTERRUPT_HDCPI_GET(val);
+ *uovbi = AV8100_GENERAL_INTERRUPT_UOVBI_GET(val);
+ *tei = AV8100_GENERAL_INTERRUPT_TEI_GET(val);
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- int index = 0;
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- /* Getting the buffer length */
- if(commandReg.buf[0] == HDMI_REQUEST_FOR_REVOCATION_LIST_INPUT) {
- commandReg.buf_len = 0x1F;
- }
- else {
- commandReg.buf_len = 0x0;
- }
+int av8100_register_general_status_read(
+ u8 *cecrec,
+ u8 *cectrx,
+ u8 *uc,
+ u8 *onuvb,
+ u8 *hdcps)
+{
+ int retval;
+ u8 val;
- /* Getting the buffer */
- while (index < commandReg.buf_len) {
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 2 + index, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 8\n");
- commandReg.buf_len = 0;
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- break;
- }
- else {
- commandReg.buf[index] = val;
- }
-
- index++;
- }
- }
- break;
-
- case AV8100_COMMAND_EDID_SECTIONREADBACK:
- if(commandReg.return_status == HDMI_COMMAND_RETURN_STATUS_OK) {
- int index = 0;
-
- commandReg.buf_len = 0x80;
-
- /* Getting the buffer */
- while (index < commandReg.buf_len) {
- retval = av8100_read_single_byte(av8100Data->client, AV8100_COMMAND_OFFSET + 1 + index, &val);
- if(retval != AV8100_OK) {
- printk("IOC_AV8100_SEND_CONFIGURATION_COMMAND fail 9\n");
- commandReg.buf_len = 0;
- commandReg.return_status = HDMI_COMMAND_RETURN_STATUS_FAIL;
- break;
- }
- else {
- commandReg.buf[index] = val;
- }
-
- index++;
- }
- }
- break;
- }
+ LOCK_AV8100_HW;
- if(copy_to_user((void *)arg, (void *)&commandReg, sizeof(struct av8100_command_register)) != 0) {
- return -EFAULT;
- }
- }
- break;
-#if 0
- case IOC_AV8100_READ_CONFIGURATION_COMMAND:
- if(copy_from_user(&commandReg, (void *)arg, sizeof(struct av8100_command_register))) {
- return -EFAULT;
- }
+ /* Read from register */
+ retval = register_read_internal(AV8100_GENERAL_STATUS, &val);
- if(copy_to_user((void *)arg, (void *)&commandReg, sizeof(struct av8100_command_register))) {
- return -EFAULT;
- }
- break;
-#endif
- case IOC_AV8100_GET_STATUS:
- {
- char val = 0;
+ /* Set return params */
+ *cecrec = AV8100_GENERAL_STATUS_CECREC_GET(val);
+ *cectrx = AV8100_GENERAL_STATUS_CECTRX_GET(val);
+ *uc = AV8100_GENERAL_STATUS_UC_GET(val);
+ *onuvb = AV8100_GENERAL_STATUS_ONUVB_GET(val);
+ *hdcps = AV8100_GENERAL_STATUS_HDCPS_GET(val);
- status.av8100_state = av8100_get_state();
- status.av8100_plugin_status = 0;
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- if(status.av8100_state != AV8100_OPMODE_SHUTDOWN) {
- retval = av8100_read_single_byte(av8100Data->client, STANDBY_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the value in to av8100 register\n");
- return -EFAULT;
- }
+int av8100_register_gpio_configuration_read(
+ u8 *dat3dir,
+ u8 *dat3val,
+ u8 *dat2dir,
+ u8 *dat2val,
+ u8 *dat1dir,
+ u8 *dat1val,
+ u8 *ucdbg)
+{
+ int retval;
+ u8 val;
- status.av8100_plugin_status = AV8100_PLUGIN_NONE;
- if(val & STANDBY_HPDS_HDMI_PLUGGED) {
- status.av8100_plugin_status |= AV8100_HDMI_PLUGIN;
- }
+ LOCK_AV8100_HW;
- if(val & STANDBY_CVBS_TV_CABLE_PLUGGED) {
- status.av8100_plugin_status |= AV8100_CVBS_PLUGIN;
- }
- }
+ /* Read from register */
+ retval = register_read_internal(AV8100_GPIO_CONFIGURATION, &val);
- printk("av8100_state:%0x av8100_plugin_status:%0x\n", status.av8100_state, status.av8100_plugin_status);
+ /* Set return params */
+ *dat3dir = AV8100_GPIO_CONFIGURATION_DAT3DIR_GET(val);
+ *dat3val = AV8100_GPIO_CONFIGURATION_DAT3VAL_GET(val);
+ *dat2dir = AV8100_GPIO_CONFIGURATION_DAT2DIR_GET(val);
+ *dat2val = AV8100_GPIO_CONFIGURATION_DAT2VAL_GET(val);
+ *dat1dir = AV8100_GPIO_CONFIGURATION_DAT1DIR_GET(val);
+ *dat1val = AV8100_GPIO_CONFIGURATION_DAT1VAL_GET(val);
+ *ucdbg = AV8100_GPIO_CONFIGURATION_UCDBG_GET(val);
- if(copy_to_user((void *)arg, (void *)&status, sizeof(struct av8100_status))) {
- return -EFAULT;
- }
- }
- break;
-
- case IOC_AV8100_ENABLE:
- /* Use the latest video mode */
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- mcde_mode = av8100_get_mcde_video_mode(hdmi_video_output_cmd.video_output_cea_vesa);
- mcde_hdmi_display_init_command_mode(mcde_mode);
-#endif
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- retval = av8100_powerup(av8100Data->client, 0);
- if(retval != AV8100_OK){
- printk("error in av8100_powerup\n");
- break;
- }
+int av8100_register_general_control_read(
+ u8 *fdl,
+ u8 *hld,
+ u8 *wa,
+ u8 *ra)
+{
+ int retval;
+ u8 val;
- g_av8100_state = AV8100_OPMODE_INIT;
+ LOCK_AV8100_HW;
- retval = av8100_download_firmware(av8100Data->client, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE);
- if(retval != AV8100_OK){
- printk("error in av8100_download_firmware\n");
- break;
- }
+ /* Read from register */
+ retval = register_read_internal(AV8100_GENERAL_CONTROL, &val);
+ /* Set return params */
+ *fdl = AV8100_GENERAL_CONTROL_FDL_GET(val);
+ *hld = AV8100_GENERAL_CONTROL_HLD_GET(val);
+ *wa = AV8100_GENERAL_CONTROL_WA_GET(val);
+ *ra = AV8100_GENERAL_CONTROL_RA_GET(val);
- av8100_configure_hdmi(av8100Data->client);
-
- retval = av8100_enable_interrupt(av8100Data->client);
- if(retval != AV8100_OK){
- printk("error in av8100_enable_interrupt\n");
- break;
- }
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- av8100_hdmi_on(av8100Data);
- break;
+int av8100_register_firmware_download_entry_read(
+ u8 *mbyte_code_entry)
+{
+ int retval;
+ u8 val;
- case IOC_AV8100_DISABLE:
- av8100_hdmi_off(av8100Data);
- av8100_powerdown();
- break;
+ LOCK_AV8100_HW;
- case IOC_AV8100_SET_VIDEO_FORMAT:
- printk(KERN_INFO "IOC_AV8100_SET_VIDEO_FORMAT\n");
+ /* Read from register */
+ retval = register_read_internal(AV8100_FIRMWARE_DOWNLOAD_ENTRY, &val);
- if(copy_from_user(&video_output_format, (void *)arg, sizeof(av8100_output_CEA_VESA))) {
- return -EFAULT;
- }
+ /* Set return params */
+ *mbyte_code_entry =
+ AV8100_FIRMWARE_DOWNLOAD_ENTRY_MBYTE_CODE_ENTRY_GET(val);
- if (video_output_format < AV8100_VIDEO_OUTPUT_CEA_VESA_MAX) {
- /* hdmi_off */
- av8100_hdmi_off(av8100Data);
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- /* powerdown */
- av8100_powerdown();
+int av8100_register_read(
+ u8 offset,
+ u8 *value)
+{
+ int retval = 0;
+ struct i2c_client *i2c;
- /* mcde */
- hdmi_video_output_cmd.video_output_cea_vesa = video_output_format;
- av8100_config_output_dep_params();
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- mcde_mode = av8100_get_mcde_video_mode(video_output_format);
- mcde_hdmi_display_init_command_mode(mcde_mode);
-#endif
+ LOCK_AV8100_HW;
- /* powerup */
- retval = av8100_powerup(av8100Data->client, 0);
- if(retval != AV8100_OK){
- printk("error in av8100_powerup\n");
- break;
- }
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_register_read_out;
+ }
- g_av8100_state = AV8100_OPMODE_INIT;
+ i2c = av8100_config->client;
- /* download fw */
- retval = av8100_download_firmware(av8100Data->client, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE);
- if(retval != AV8100_OK){
- printk("error in av8100_download_firmware\n");
- break;
- }
+ /* Read from register */
+ retval = read_single_byte(i2c, offset, value);
+ if (retval) {
+ printk(KERN_DEBUG "Failed to read the value from av8100 register\n");
+ retval = -EFAULT;
+ goto av8100_register_read_out;
+ }
- hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb(video_output_format);
- hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4(video_output_format);
+av8100_register_read_out:
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- /* configure hdmi */
- av8100_configure_hdmi(av8100Data->client);
+int av8100_configuration_get(enum av8100_command_type command_type,
+ union av8100_configuration *config)
+{
+ if (!av8100_config || !config)
+ return AV8100_FAIL;
+
+ /* Put configuration data to the corresponding data struct depending
+ * on command type */
+ switch (command_type) {
+ case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
+ memcpy(&config->video_input_format,
+ &av8100_config->hdmi_video_input_cmd,
+ sizeof(struct av8100_video_input_format_cmd));
+ break;
- /* enable int */
- retval = av8100_enable_interrupt(av8100Data->client);
- if(retval != AV8100_OK){
- printk("error in av8100_enable_interrupt\n");
- break;
- }
+ case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
+ memcpy(&config->audio_input_format,
+ &av8100_config->hdmi_audio_input_cmd,
+ sizeof(struct av8100_audio_input_format_cmd));
+ break;
- /* hdmi on */
- av8100_hdmi_on(av8100Data);
- }
- else {
- retval = AV8100_INVALID_COMMAND;
- }
+ case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
+ memcpy(&config->video_output_format,
+ &av8100_config->hdmi_video_output_cmd,
+ sizeof(struct av8100_video_output_format_cmd));
break;
-#if 1
-//Test
- case IOC_AV8100_HDMI_ON:
- printk(KERN_INFO "IOC_AV8100_HDMI_ON\n");
- av8100_hdmi_on(av8100Data);
+ case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
+ memcpy(&config->video_scaling_format,
+ &av8100_config->hdmi_video_scaling_cmd,
+ sizeof(struct av8100_video_scaling_format_cmd));
break;
- case IOC_AV8100_HDMI_OFF:
- printk(KERN_INFO "IOC_AV8100_HDMI_OFF\n");
- av8100_hdmi_off(av8100Data);
+ case AV8100_COMMAND_COLORSPACECONVERSION:
+ memcpy(&config->color_space_conversion_format,
+ &av8100_config->hdmi_color_space_conversion_cmd,
+ sizeof(struct
+ av8100_color_space_conversion_format_cmd));
break;
-#endif
- default:
- return AV8100_INVALID_IOCTL;
- }
- return retval;
-}
+ case AV8100_COMMAND_CEC_MESSAGE_WRITE:
+ memcpy(&config->cec_message_write_format,
+ &av8100_config->hdmi_cec_message_write_cmd,
+ sizeof(struct av8100_cec_message_write_format_cmd));
+ break;
-static unsigned short av8100_get_te_line_nb(av8100_output_CEA_VESA output_video_format)
-{
- unsigned short retval;
+ case AV8100_COMMAND_CEC_MESSAGE_READ_BACK:
+ memcpy(&config->cec_message_read_back_format,
+ &av8100_config->hdmi_cec_message_read_back_cmd,
+ sizeof(struct av8100_cec_message_read_back_format_cmd));
+ break;
- switch(output_video_format) {
- case AV8100_CEA1_640X480P_59_94HZ:
- case AV8100_CEA2_3_720X480P_59_94HZ:
- retval = 30;
+ case AV8100_COMMAND_DENC:
+ memcpy(&config->denc_format, &av8100_config->hdmi_denc_cmd,
+ sizeof(struct av8100_denc_format_cmd));
break;
- case AV8100_CEA5_1920X1080I_60HZ:
- case AV8100_CEA6_7_NTSC_60HZ:
- case AV8100_CEA20_1920X1080I_50HZ:
- retval = 18;
+ case AV8100_COMMAND_HDMI:
+ memcpy(&config->hdmi_format, &av8100_config->hdmi_cmd,
+ sizeof(struct av8100_hdmi_cmd));
break;
- case AV8100_CEA4_1280X720P_60HZ:
- retval = 21;
+ case AV8100_COMMAND_HDCP_SENDKEY:
+ memcpy(&config->hdcp_send_key_format,
+ &av8100_config->hdmi_hdcp_send_key_cmd,
+ sizeof(struct av8100_hdcp_send_key_format_cmd));
break;
- case AV8100_CEA17_18_720X576P_50HZ:
- retval = 40;
+ case AV8100_COMMAND_HDCP_MANAGEMENT:
+ memcpy(&config->hdcp_management_format,
+ &av8100_config->hdmi_hdcp_management_format_cmd,
+ sizeof(struct av8100_hdcp_management_format_cmd));
break;
- case AV8100_CEA19_1280X720P_50HZ:
- retval = 22;
+ case AV8100_COMMAND_INFOFRAMES:
+ memcpy(&config->infoframes_format,
+ &av8100_config->hdmi_infoframes_cmd,
+ sizeof(struct av8100_infoframes_format_cmd));
break;
- case AV8100_CEA21_22_576I_PAL_50HZ:
- /* Different values below come from LLD,
- * TODO: check if this is really needed
- * if not merge with AV8100_CEA6_7_NTSC_60HZ case
- */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- retval = 18;
-#else
- retval = 17;
-#endif
+ case AV8100_COMMAND_EDID_SECTION_READBACK:
+ memcpy(&config->edid_section_readback_format,
+ &av8100_config->hdmi_edid_section_readback_cmd,
+ sizeof(struct
+ av8100_edid_section_readback_format_cmd));
break;
- case AV8100_CEA32_1920X1080P_24HZ:
- case AV8100_CEA33_1920X1080P_25HZ:
- case AV8100_CEA34_1920X1080P_30HZ:
- retval = 38;
+ case AV8100_COMMAND_PATTERNGENERATOR:
+ memcpy(&config->pattern_generator_format,
+ &av8100_config->hdmi_pattern_generator_cmd,
+ sizeof(struct av8100_pattern_generator_format_cmd));
break;
- case AV8100_CEA60_1280X720P_24HZ:
- case AV8100_CEA62_1280X720P_30HZ:
- retval = 21;
+ case AV8100_COMMAND_FUSE_AES_KEY:
+ memcpy(&config->fuse_aes_key_format,
+ &av8100_config->hdmi_fuse_aes_key_cmd,
+ sizeof(struct av8100_fuse_aes_key_format_cmd));
break;
- case AV8100_CEA14_15_480p_60HZ:
- case AV8100_VESA14_848X480P_60HZ:
- case AV8100_CEA61_1280X720P_25HZ:
- case AV8100_CEA16_1920X1080P_60HZ:
- case AV8100_CEA31_1920x1080P_50Hz:
- case AV8100_CEA29_30_576P_50HZ:
- case AV8100_VESA9_800X600P_60_32HZ:
- case AV8100_VESA16_1024X768P_60HZ:
- case AV8100_VESA22_1280X768P_59_99HZ:
- case AV8100_VESA23_1280X768P_59_87HZ:
- case AV8100_VESA27_1280X800P_59_91HZ:
- case AV8100_VESA28_1280X800P_59_81HZ:
- case AV8100_VESA39_1360X768P_60_02HZ:
- case AV8100_VESA81_1366X768P_59_79HZ:
default:
- /* TODO */
- retval = 14;
+ return AV8100_FAIL;
break;
}
- return retval;
+ return 0;
}
-static unsigned short av8100_get_ui_x4(av8100_output_CEA_VESA output_video_format)
+int av8100_configuration_prepare(enum av8100_command_type command_type,
+ union av8100_configuration *config)
{
- unsigned short retval = 6;
+ if (!av8100_config || !config)
+ return AV8100_FAIL;
+
+ /* Put configuration data to the corresponding data struct depending
+ * on command type */
+ switch (command_type) {
+ case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
+ memcpy(&av8100_config->hdmi_video_input_cmd,
+ &config->video_input_format,
+ sizeof(struct av8100_video_input_format_cmd));
+ break;
- switch(output_video_format) {
- case AV8100_CEA1_640X480P_59_94HZ:
- case AV8100_CEA2_3_720X480P_59_94HZ:
- case AV8100_CEA4_1280X720P_60HZ:
- case AV8100_CEA5_1920X1080I_60HZ:
- case AV8100_CEA6_7_NTSC_60HZ:
- case AV8100_CEA17_18_720X576P_50HZ:
- case AV8100_CEA19_1280X720P_50HZ:
- case AV8100_CEA20_1920X1080I_50HZ:
- case AV8100_CEA21_22_576I_PAL_50HZ:
- case AV8100_CEA32_1920X1080P_24HZ:
- case AV8100_CEA33_1920X1080P_25HZ:
- case AV8100_CEA34_1920X1080P_30HZ:
- case AV8100_CEA60_1280X720P_24HZ:
- case AV8100_CEA62_1280X720P_30HZ:
- retval = 6;
+ case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
+ memcpy(&av8100_config->hdmi_audio_input_cmd,
+ &config->audio_input_format,
+ sizeof(struct av8100_audio_input_format_cmd));
break;
- case AV8100_CEA14_15_480p_60HZ:
- case AV8100_VESA14_848X480P_60HZ:
- case AV8100_CEA61_1280X720P_25HZ:
- case AV8100_CEA16_1920X1080P_60HZ:
- case AV8100_CEA31_1920x1080P_50Hz:
- case AV8100_CEA29_30_576P_50HZ:
- case AV8100_VESA9_800X600P_60_32HZ:
- case AV8100_VESA16_1024X768P_60HZ:
- case AV8100_VESA22_1280X768P_59_99HZ:
- case AV8100_VESA23_1280X768P_59_87HZ:
- case AV8100_VESA27_1280X800P_59_91HZ:
- case AV8100_VESA28_1280X800P_59_81HZ:
- case AV8100_VESA39_1360X768P_60_02HZ:
- case AV8100_VESA81_1366X768P_59_79HZ:
- default:
- /* TODO */
- retval = 6;
+ case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
+ memcpy(&av8100_config->hdmi_video_output_cmd,
+ &config->video_output_format,
+ sizeof(struct av8100_video_output_format_cmd));
+
+ /* Set params that depend on video output */
+ av8100_config_video_output_dep(av8100_config->
+ hdmi_video_output_cmd.video_output_cea_vesa);
break;
- }
- return retval;
-}
+ case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
+ memcpy(&av8100_config->hdmi_video_scaling_cmd,
+ &config->video_scaling_format,
+ sizeof(struct av8100_video_scaling_format_cmd));
+ break;
-static void av8100_init_config_params(void)
-{
- memset(&hdmi_video_output_cmd, 0x0, sizeof(av8100_video_output_format_cmd));
+ case AV8100_COMMAND_COLORSPACECONVERSION:
+ memcpy(&av8100_config->hdmi_color_space_conversion_cmd,
+ &config->color_space_conversion_format,
+ sizeof(struct
+ av8100_color_space_conversion_format_cmd));
+ break;
+ case AV8100_COMMAND_CEC_MESSAGE_WRITE:
+ memcpy(&av8100_config->hdmi_cec_message_write_cmd,
+ &config->cec_message_write_format,
+ sizeof(struct av8100_cec_message_write_format_cmd));
+ break;
- /* SDTV mode settings */
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
+ case AV8100_COMMAND_CEC_MESSAGE_READ_BACK:
+ memcpy(&av8100_config->hdmi_cec_message_read_back_cmd,
+ &config->cec_message_read_back_format,
+ sizeof(struct av8100_cec_message_read_back_format_cmd));
+ break;
- /* Default output mode */
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ;
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_PAL_THRU_AV8100
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ;
-#elif defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_NTSC_THRU_AV8100
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA6_7_NTSC_60HZ;
-#endif
+ case AV8100_COMMAND_DENC:
+ memcpy(&av8100_config->hdmi_denc_cmd, &config->denc_format,
+ sizeof(struct av8100_denc_format_cmd));
+ break;
- hdmi_color_conversion_cmd.c0 = 0xFFDA;
- hdmi_color_conversion_cmd.c1 = 0xFFB6;
- hdmi_color_conversion_cmd.c2 = 0x0070;
- hdmi_color_conversion_cmd.c3 = 0x0042;
- hdmi_color_conversion_cmd.c4 = 0x0081;
- hdmi_color_conversion_cmd.c5 = 0x0019;
- hdmi_color_conversion_cmd.c6 = 0x0070;
- hdmi_color_conversion_cmd.c7 = 0xFFA2;
- hdmi_color_conversion_cmd.c8 = 0xFFEE;
- hdmi_color_conversion_cmd.a_offset = 0x007F;
- hdmi_color_conversion_cmd.b_offset = 0x0010;
- hdmi_color_conversion_cmd.c_offset = 0x007F;
- hdmi_color_conversion_cmd.l_max = 0xEB;
- hdmi_color_conversion_cmd.l_min = 0x10;
- hdmi_color_conversion_cmd.c_max = 0xF0;
- hdmi_color_conversion_cmd.c_min = 0x10;
-
-#else /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
-
- /* Default output mode */
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA4_1280X720P_60HZ;
-
- /* HDMI mode settings */
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_640x480P60
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA1_640X480P_59_94HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x480P60
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA2_3_720X480P_59_94HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_1280x720P60
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA4_1280X720P_60HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080I60
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA5_1920X1080I_60HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080I50
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA20_1920X1080I_50HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_1920x1080P30
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA34_1920X1080P_30HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x576I50
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA21_22_576I_PAL_50HZ;
-#endif
-#ifdef CONFIG_FB_U8500_MCDE_HDMI_720x480I60
- hdmi_video_output_cmd.video_output_cea_vesa = AV8100_CEA6_7_NTSC_60HZ;
-#endif
-#endif /* else of if CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
- av8100_config_output_dep_params();
-}
-
-static void av8100_config_output_dep_params(void)
-{
- memset(&hdmi_cmd, 0x0, sizeof(av8100_hdmi_cmd));
- memset(&hdmi_video_input_cmd, 0x0, sizeof(av8100_video_input_format_cmd));
- memset(&hdmi_pattern_generator_cmd, 0x0, sizeof(av8100_pattern_generator_cmd));
- memset(&hdmi_audio_input_cmd, 0x0, sizeof(av8100_audio_input_format_cmd));
- memset(&hdmi_denc_cmd, 0x0, sizeof(av8100_denc_cmd));
-
- hdmi_video_input_cmd.dsi_input_mode = AV8100_HDMI_DSI_COMMAND_MODE;
- hdmi_video_input_cmd.total_horizontal_pixel = av8100_all_cea[
- hdmi_video_output_cmd.video_output_cea_vesa].htotale;
- hdmi_video_input_cmd.total_horizontal_active_pixel = av8100_all_cea[
- hdmi_video_output_cmd.video_output_cea_vesa].hactive;
- hdmi_video_input_cmd.total_vertical_lines = av8100_all_cea[
- hdmi_video_output_cmd.video_output_cea_vesa].vtotale;
- hdmi_video_input_cmd.total_vertical_active_lines = av8100_all_cea[
- hdmi_video_output_cmd.video_output_cea_vesa].vactive;
-
- hdmi_video_input_cmd.nb_data_lane = AV8100_DATA_LANES_USED_2;
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- /* hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_YCBCR422;
- */
- hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_RGB565;
- hdmi_video_input_cmd.video_mode = AV8100_VIDEO_INTERLACE;
-
- /* only shared for channel A */
- hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4(
- hdmi_video_output_cmd.video_output_cea_vesa);
- hdmi_video_input_cmd.TE_config = AV8100_TE_IT_LINE;
- hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb(
- hdmi_video_output_cmd.video_output_cea_vesa);
-
- if (hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA21_22_576I_PAL_50HZ
- ) {
- hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_625;
- hdmi_denc_cmd.tv_std = AV8100_TV_STD_PALBDGHI;
- } else if (
- hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA6_7_NTSC_60HZ
- ) {
- hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_525;
- hdmi_denc_cmd.tv_std = AV8100_TV_STD_NTSCM;
- } else {
- printk(KERN_WARNING "AV8100: unsupported video mode, using default\n");
- hdmi_denc_cmd.tv_lines = AV8100_TV_LINES_625;
- }
- hdmi_denc_cmd.denc = AV8100_DENC_ON;
- hdmi_denc_cmd.macrovision = AV8100_MACROVISION_OFF;
+ case AV8100_COMMAND_HDMI:
+ memcpy(&av8100_config->hdmi_cmd, &config->hdmi_format,
+ sizeof(struct av8100_hdmi_cmd));
+ break;
-#ifdef TEST_PATTERN_TEST
- hdmi_denc_cmd.internal_generator = AV8100_INTERNAL_GENERATOR_ON;
- hdmi_denc_cmd.chroma = AV8100_CHROMA_CWS_CAPTURE_ON;
-#else
- hdmi_denc_cmd.internal_generator = AV8100_INTERNAL_GENERATOR_OFF;
- hdmi_denc_cmd.chroma = AV8100_CHROMA_CWS_CAPTURE_OFF;
-#endif /* CONFIG_AV8100_TEST_PATTERN */
-
-#else /* CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
-
- /** Config for command mode **/
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI
- hdmi_video_input_cmd.ui_x4 = av8100_get_ui_x4(hdmi_video_output_cmd.video_output_cea_vesa);
- hdmi_video_input_cmd.TE_line_nb = av8100_get_te_line_nb(hdmi_video_output_cmd.video_output_cea_vesa);
- // hdmi_video_input_cmd.TE_config = AV8100_TE_DSI_IT; // IT on both I/F (DSI & GPIO)
- hdmi_video_input_cmd.TE_config = AV8100_TE_IT_LINE; // IT on both I/F (DSI & GPIO)
-#endif
+ case AV8100_COMMAND_HDCP_SENDKEY:
+ memcpy(&av8100_config->hdmi_hdcp_send_key_cmd,
+ &config->hdcp_send_key_format,
+ sizeof(struct av8100_hdcp_send_key_format_cmd));
+ break;
-#ifdef CONFIG_FB_U8500_MCDE_CHANNELC0_DISPLAY_HDMI
- /** Config for video mode **/
- hdmi_video_input_cmd.dsi_input_mode = AV8100_HDMI_DSI_VIDEO_MODE;
- hdmi_video_input_cmd.TE_line_nb = 0;
- hdmi_video_input_cmd.TE_config = AV8100_TE_OFF; // No TE IT
-#endif
+ case AV8100_COMMAND_HDCP_MANAGEMENT:
+ memcpy(&av8100_config->hdmi_hdcp_management_format_cmd,
+ &config->hdcp_management_format,
+ sizeof(struct av8100_hdcp_management_format_cmd));
+ break;
- hdmi_video_input_cmd.input_pixel_format = AV8100_INPUT_PIX_RGB565;
- if (hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA5_1920X1080I_60HZ
- ||
- hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA20_1920X1080I_50HZ
- ||
- hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA21_22_576I_PAL_50HZ
- ||
- hdmi_video_output_cmd.video_output_cea_vesa ==
- AV8100_CEA6_7_NTSC_60HZ
- ) {
- hdmi_video_input_cmd.video_mode = AV8100_VIDEO_INTERLACE;
- } else {
- hdmi_video_input_cmd.video_mode = AV8100_VIDEO_PROGRESSIVE;
- }
+ case AV8100_COMMAND_INFOFRAMES:
+ memcpy(&av8100_config->hdmi_infoframes_cmd,
+ &config->infoframes_format,
+ sizeof(struct av8100_infoframes_format_cmd));
+ break;
- hdmi_pattern_generator_cmd.pattern_audio_mode = AV8100_PATTERN_AUDIO_OFF;
- hdmi_pattern_generator_cmd.pattern_type = AV8100_PATTERN_GENERATOR;
+ case AV8100_COMMAND_EDID_SECTION_READBACK:
+ memcpy(&av8100_config->hdmi_edid_section_readback_cmd,
+ &config->edid_section_readback_format,
+ sizeof(struct
+ av8100_edid_section_readback_format_cmd));
+ break;
- if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA4_1280X720P_60HZ)
- hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_720P;
- else if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA1_640X480P_59_94HZ)
- hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_VGA;
- else if(hdmi_video_output_cmd.video_output_cea_vesa == AV8100_CEA34_1920X1080P_30HZ)
- hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_1080P;
- else
- hdmi_pattern_generator_cmd.pattern_video_format = AV8100_PATTERN_720P;
+ case AV8100_COMMAND_PATTERNGENERATOR:
+ memcpy(&av8100_config->hdmi_pattern_generator_cmd,
+ &config->pattern_generator_format,
+ sizeof(struct av8100_pattern_generator_format_cmd));
+ break;
- hdmi_denc_cmd.denc = AV8100_DENC_OFF;
+ case AV8100_COMMAND_FUSE_AES_KEY:
+ memcpy(&av8100_config->hdmi_fuse_aes_key_cmd,
+ &config->fuse_aes_key_format,
+ sizeof(struct av8100_fuse_aes_key_format_cmd));
+ break;
- /* default audio configurations in i2s mode*/
- hdmi_audio_input_cmd.audio_input_if_format = AV8100_AUDIO_I2SDELAYED_MODE; // mode of the MSP
- hdmi_audio_input_cmd.i2s_input_nb = 1; // 0, 1 2 3 4
- hdmi_audio_input_cmd.sample_audio_freq = AV8100_AUDIO_FREQ_48KHZ;
- hdmi_audio_input_cmd.audio_word_lg = AV8100_AUDIO_16BITS;
- hdmi_audio_input_cmd.audio_format = AV8100_AUDIO_LPCM_MODE;
- hdmi_audio_input_cmd.audio_if_mode = AV8100_AUDIO_MASTER;
- hdmi_audio_input_cmd.audio_mute = AV8100_AUDIO_MUTE_DISABLE;
+ default:
+ return AV8100_FAIL;
+ break;
+ }
-#endif /* if..else CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV */
- // HDMI mode
- hdmi_cmd.hdmi_mode = AV8100_HDMI_ON;
- hdmi_cmd.hdmi_format = AV8100_HDMI;
- return;
+ return 0;
}
-
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
-static mcde_video_mode av8100_get_mcde_video_mode(av8100_output_CEA_VESA format)
+int av8100_configuration_write(enum av8100_command_type command_type,
+ u8 *return_buffer_length,
+ u8 *return_buffer, enum interface_type if_type)
{
- mcde_video_mode retval = VMODE_1280_720_60_P;
+ int retval = 0;
+ u8 cmd_buffer[AV8100_COMMAND_MAX_LENGTH];
+ u32 cmd_length = 0;
+ struct i2c_client *i2c;
-#define PRNK_MODE(_m, _n) \
- printk(KERN_DEBUG "AV8100 mapped mode: " #_m " on " #_n "\n");
+ if (return_buffer_length)
+ *return_buffer_length = 0;
- switch(format) {
- case AV8100_CEA1_640X480P_59_94HZ:
- PRNK_MODE(AV8100_CEA1_640X480P_59_94HZ, VMODE_640_480_60_P);
- retval = VMODE_640_480_60_P;
+ if (!av8100_config)
+ return AV8100_FAIL;
+
+ i2c = av8100_config->client;
+
+ memset(&cmd_buffer, 0x00, AV8100_COMMAND_MAX_LENGTH);
+
+#ifdef AV8100_DEBUG_EXTRA
+#define PRNK_MODE(_m) printk(KERN_DEBUG "cmd: " #_m "\n");
+#else
+#define PRNK_MODE(_m)
+#endif
+
+ /* Fill the command buffer with configuration data */
+ switch (command_type) {
+ case AV8100_COMMAND_VIDEO_INPUT_FORMAT:
+ PRNK_MODE(AV8100_COMMAND_VIDEO_INPUT_FORMAT);
+ configuration_video_input_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA2_3_720X480P_59_94HZ:
- PRNK_MODE(AV8100_CEA2_3_720X480P_59_94HZ, VMODE_720_480_60_P);
- retval = VMODE_720_480_60_P;
+
+ case AV8100_COMMAND_AUDIO_INPUT_FORMAT:
+ PRNK_MODE(AV8100_COMMAND_AUDIO_INPUT_FORMAT);
+ configuration_audio_input_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA5_1920X1080I_60HZ:
- PRNK_MODE(AV8100_CEA5_1920X1080I_60HZ, VMODE_1920_1080_60_I);
- retval = VMODE_1920_1080_60_I;
+
+ case AV8100_COMMAND_VIDEO_OUTPUT_FORMAT:
+ PRNK_MODE(AV8100_COMMAND_VIDEO_OUTPUT_FORMAT);
+ configuration_video_output_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA6_7_NTSC_60HZ:
- PRNK_MODE(AV8100_CEA6_7_NTSC_60HZ, VMODE_720_480_60_I);
- retval = VMODE_720_480_60_I;
+
+ case AV8100_COMMAND_VIDEO_SCALING_FORMAT:
+ PRNK_MODE(AV8100_COMMAND_VIDEO_SCALING_FORMAT);
+ configuration_video_scaling_get(cmd_buffer,
+ &cmd_length);
break;
- case AV8100_CEA4_1280X720P_60HZ:
- PRNK_MODE(AV8100_CEA4_1280X720P_60HZ, VMODE_1280_720_60_P);
- retval = VMODE_1280_720_60_P;
+
+ case AV8100_COMMAND_COLORSPACECONVERSION:
+ PRNK_MODE(AV8100_COMMAND_COLORSPACECONVERSION);
+ configuration_colorspace_conversion_get(cmd_buffer,
+ &cmd_length);
break;
- case AV8100_CEA17_18_720X576P_50HZ:
- PRNK_MODE(AV8100_CEA17_18_720X576P_50HZ, VMODE_720_576_50_P);
- retval = VMODE_720_576_50_P;
+
+ case AV8100_COMMAND_CEC_MESSAGE_WRITE:
+ PRNK_MODE(AV8100_COMMAND_CEC_MESSAGE_WRITE);
+ configuration_cec_message_write_get(cmd_buffer,
+ &cmd_length);
break;
- case AV8100_CEA19_1280X720P_50HZ:
- PRNK_MODE(AV8100_CEA19_1280X720P_50HZ, VMODE_1280_720_50_P);
- retval = VMODE_1280_720_50_P;
+
+ case AV8100_COMMAND_CEC_MESSAGE_READ_BACK:
+ PRNK_MODE(AV8100_COMMAND_CEC_MESSAGE_READ_BACK);
+ configuration_cec_message_read_get(cmd_buffer,
+ &cmd_length);
break;
- case AV8100_CEA20_1920X1080I_50HZ:
- PRNK_MODE(AV8100_CEA20_1920X1080I_50HZ, VMODE_1920_1080_50_I);
- retval = VMODE_1920_1080_50_I;
+
+ case AV8100_COMMAND_DENC:
+ PRNK_MODE(AV8100_COMMAND_DENC);
+ configuration_denc_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA21_22_576I_PAL_50HZ:
- PRNK_MODE(AV8100_CEA21_22_576I_PAL_50HZ, VMODE_720_576_50_I);
- retval = VMODE_720_576_50_I;
+
+ case AV8100_COMMAND_HDMI:
+ PRNK_MODE(AV8100_COMMAND_HDMI);
+ configuration_hdmi_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA32_1920X1080P_24HZ:
- PRNK_MODE(AV8100_CEA32_1920X1080P_24HZ, VMODE_1920_1080_24_P);
- retval = VMODE_1920_1080_24_P;
+
+ case AV8100_COMMAND_HDCP_SENDKEY:
+ PRNK_MODE(AV8100_COMMAND_HDCP_SENDKEY);
+ configuration_hdcp_sendkey_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA33_1920X1080P_25HZ:
- PRNK_MODE(AV8100_CEA33_1920X1080P_25HZ, VMODE_1920_1080_25_P);
- retval = VMODE_1920_1080_25_P;
+
+ case AV8100_COMMAND_HDCP_MANAGEMENT:
+ PRNK_MODE(AV8100_COMMAND_HDCP_MANAGEMENT);
+ configuration_hdcp_management_get(cmd_buffer,
+ &cmd_length);
break;
- case AV8100_CEA34_1920X1080P_30HZ:
- PRNK_MODE(AV8100_CEA34_1920X1080P_30HZ, VMODE_1920_1080_30_P);
- retval = VMODE_1920_1080_30_P;
+
+ case AV8100_COMMAND_INFOFRAMES:
+ PRNK_MODE(AV8100_COMMAND_INFOFRAMES);
+ configuration_infoframe_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA60_1280X720P_24HZ:
- PRNK_MODE(AV8100_CEA60_1280X720P_24HZ, VMODE_1280_720_24_P);
- retval = VMODE_1280_720_24_P;
+
+ case AV8100_COMMAND_EDID_SECTION_READBACK:
+ PRNK_MODE(AV8100_COMMAND_EDID_SECTION_READBACK);
+ av8100_edid_section_readback_get(cmd_buffer, &cmd_length);
break;
- case AV8100_CEA62_1280X720P_30HZ:
- PRNK_MODE(AV8100_CEA62_1280X720P_30HZ, VMODE_1280_720_30_P);
- retval = VMODE_1280_720_30_P;
+
+ case AV8100_COMMAND_PATTERNGENERATOR:
+ PRNK_MODE(AV8100_COMMAND_PATTERNGENERATOR);
+ configuration_pattern_generator_get(cmd_buffer,
+ &cmd_length);
+ break;
+
+ case AV8100_COMMAND_FUSE_AES_KEY:
+ PRNK_MODE(AV8100_COMMAND_FUSE_AES_KEY);
+ configuration_fuse_aes_key_get(cmd_buffer, &cmd_length);
break;
- case AV8100_VESA9_800X600P_60_32HZ:
- case AV8100_CEA14_15_480p_60HZ:
- case AV8100_CEA16_1920X1080P_60HZ:
- case AV8100_CEA29_30_576P_50HZ:
- case AV8100_CEA31_1920x1080P_50Hz:
- case AV8100_CEA61_1280X720P_25HZ:
- case AV8100_VESA14_848X480P_60HZ:
- case AV8100_VESA16_1024X768P_60HZ:
- case AV8100_VESA22_1280X768P_59_99HZ:
- case AV8100_VESA23_1280X768P_59_87HZ:
- case AV8100_VESA27_1280X800P_59_91HZ:
- case AV8100_VESA28_1280X800P_59_81HZ:
- case AV8100_VESA39_1360X768P_60_02HZ:
- case AV8100_VESA81_1366X768P_59_79HZ:
default:
- /* TODO */
- PRNK_MODE(AV8100_UNKNOWN_OR_TODO_MODE, VMODE_1280_720_60_P);
- retval = VMODE_1280_720_60_P;
+ printk(KERN_INFO "Invalid command type\n");
+ retval = AV8100_INVALID_COMMAND;
break;
}
- return retval;
-}
+ LOCK_AV8100_HW;
+
+ if (if_type == I2C_INTERFACE) {
+#ifdef AV8100_DEBUG_EXTRA
+ {
+ int cnt = 0;
+ printk(KERN_DEBUG "av8100_configuration_write cmd_type:%02x length:%02x ",
+ command_type, cmd_length);
+ printk(KERN_DEBUG "buffer: ");
+ while (cnt < cmd_length) {
+ printk(KERN_DEBUG "%02x ", cmd_buffer[cnt]);
+ cnt++;
+ }
+ printk(KERN_DEBUG "\n");
+ }
#endif
-static void av8100_set_state(av8100_operating_mode state)
-{
- g_av8100_state = state;
-}
+ /* Write the command buffer */
+ retval = write_multi_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, cmd_buffer, cmd_length);
+ if (retval) {
+ UNLOCK_AV8100_HW;
+ return retval;
+ }
-static av8100_operating_mode av8100_get_state(void)
-{
- return g_av8100_state;
-}
+ /* Write the command */
+ retval = write_single_byte(i2c, AV8100_COMMAND_OFFSET,
+ command_type);
+ if (retval) {
+ UNLOCK_AV8100_HW;
+ return retval;
+ }
+ /* TODO */
+ mdelay(100);
-#ifdef AV8100_USE_KERNEL_THREAD
-/**
- * av8100_thread() - This function will be used to send the data from 8500(MCDE/VTG) to hdmi chip.
- *
- **/
-static int av8100_thread(void)
+ retval = get_command_return_data(i2c, command_type, cmd_buffer,
+ return_buffer_length, return_buffer);
+ } else if (if_type == DSI_INTERFACE) {
+ /* TODO */
+ } else {
+ retval = AV8100_INVALID_INTERFACE;
+ printk(KERN_INFO "Invalid command type\n");
+ }
+
+ if (command_type == AV8100_COMMAND_HDMI) {
+ g_av8100_status.hdmi_on = ((av8100_config->hdmi_cmd.
+ hdmi_mode == AV8100_HDMI_ON) &&
+ (av8100_config->hdmi_cmd.hdmi_format == AV8100_HDMI));
+ }
+
+ UNLOCK_AV8100_HW;
+ return retval;
+}
+
+int av8100_configuration_write_raw(enum av8100_command_type command_type,
+ u8 buffer_length,
+ u8 *buffer,
+ u8 *return_buffer_length,
+ u8 *return_buffer)
{
- int retval = AV8100_OK;
- char val = 0x0;
+ int retval = 0;
+ struct i2c_client *i2c;
- daemonize("hdmi_feeding_thread");
- allow_signal(SIGKILL);
+ LOCK_AV8100_HW;
- while (1)
- {
- wait_event_interruptible(av8100_event, (av8100_flag == 1) );
- av8100_flag = 0;
+ if (return_buffer_length)
+ *return_buffer_length = 0;
- /* STANDBY interrupts */
- retval = av8100_read_single_byte(av8100Data->client, STANDBY_PENDING_INTERRUPT_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the STANDBY_PENDING_INTERRUPT_REG\n");
- return -EFAULT;
- }
+ if (!av8100_config) {
+ retval = AV8100_FAIL;
+ goto av8100_configuration_write_raw_out;
+ }
- if (val && HDMI_HOTPLUG_INTERRUPT) {
- //printk("HDMI_HOTPLUG_INTERRUPT\n");
+ i2c = av8100_config->client;
- /* TODO */
- }
+ /* Write the command buffer */
+ retval = write_multi_byte(i2c,
+ AV8100_COMMAND_OFFSET + 1, buffer, buffer_length);
+ if (retval)
+ goto av8100_configuration_write_raw_out;
- if (val && CVBS_PLUG_INTERRUPT) {
- //printk("CVBS_PLUG_INTERRUPT\n");
+ /* Write the command */
+ retval = write_single_byte(i2c, AV8100_COMMAND_OFFSET,
+ command_type);
+ if (retval)
+ goto av8100_configuration_write_raw_out;
- /* TODO */
- }
+ /* TODO */
+ mdelay(100);
- /* Clear interrupts */
- av8100_write_single_byte(av8100Data->client, STANDBY_PENDING_INTERRUPT_REG, STANDBY_INTERRUPT_MASK_ALL);
+ retval = get_command_return_data(i2c, command_type, buffer,
+ return_buffer_length, return_buffer);
- /* General interrupts */
- retval = av8100_read_single_byte(av8100Data->client, GENERAL_INTERRUPT_REG, &val);
- if(retval != AV8100_OK)
- {
- printk("Failed to read the GENERAL_INTERRUPT_REG\n");
- return -EFAULT;
- }
+av8100_configuration_write_raw_out:
+ UNLOCK_AV8100_HW;
+ return retval;
+}
- if(val & TE_INTERRUPT)
- {
- u8500_mcde_tasklet_4(0);
+struct av8100_status av8100_status_get(void)
+{
+ return g_av8100_status;
+}
+
+enum av8100_output_CEA_VESA av8100_video_output_format_get(int xres,
+ int yres,
+ int htot,
+ int vtot,
+ bool interlaced)
+{
+ enum av8100_output_CEA_VESA index = 1;
+ int yres_div = (interlaced == false ? 1 : 2);
+
+ while (index < sizeof(av8100_all_cea)/sizeof(struct av8100_cea)) {
+ if ((xres == av8100_all_cea[index].hactive) &&
+ (yres == av8100_all_cea[index].vactive * yres_div) &&
+ (htot == av8100_all_cea[index].htotale) &&
+ (vtot == av8100_all_cea[index].vtotale)) {
+ goto av8100_video_output_format_get_out;
}
+ index++;
+ }
- if(val & UNDER_OVER_FLOW_INTERRUPT)
- {
- //printk("Received the underflow/overflow interrupt\n");
+av8100_video_output_format_get_out:
+ /* TODO remove */
+ printk(KERN_DEBUG "av8100_video_output_format_get %d %d %d %d %d\n",
+ xres, yres, htot, vtot, index);
+ return index;
+}
- /* TODO */
- }
+static int av8100_open(struct inode *inode, struct file *filp)
+{
+ printk(KERN_DEBUG "av8100_open is called\n");
+ return 0;
+}
- /* Clear interrupts */
- retval = av8100_write_single_byte(av8100Data->client, GENERAL_INTERRUPT_REG, GENERAL_INTERRUPT_MASK_ALL);
- }
+static int av8100_release(struct inode *inode, struct file *filp)
+{
+ printk(KERN_DEBUG "av8100_release is called\n");
return 0;
}
-#endif
-/**
- * av8100_probe() - This function will be used to powerup and initialize the av8100.
- * @i2c: i2c client device
- * @id: device id
- *
- **/
-static int av8100_probe(struct i2c_client *i2cClient,
- const struct i2c_device_id *id)
+static int av8100_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
{
- int ret= 0;
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- mcde_video_mode mcde_mode;
-#endif
+ return 0;
+}
-#ifndef TEST_PATTERN_TEST
+static int __devinit av8100_probe(struct i2c_client *i2cClient,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
struct av8100_platform_data *pdata = i2cClient->dev.platform_data;
-#endif
- //printk(KERN_INFO "av8100 probe\n");
- //printk("av8100 probe\n");
+ printk(KERN_DEBUG "%s\n", __func__);
- PRNK_COL(PRNK_COL_GREEN);
- printk(KERN_DEBUG "av8100_probe\n");
- PRNK_COL(PRNK_COL_WHITE);
+ g_av8100_status.av8100_state = AV8100_OPMODE_SHUTDOWN;
+ g_av8100_status.av8100_plugin_status = AV8100_PLUGIN_NONE;
+ g_av8100_status.hdmi_on = false;
- av8100_init_config_params();
-
-#ifdef CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT
-#if defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_HDMI ||\
- defined CONFIG_FB_U8500_MCDE_CHANNELA_DISPLAY_SDTV
- mcde_mode = av8100_get_mcde_video_mode(hdmi_video_output_cmd.video_output_cea_vesa);
- PRNK_COL(PRNK_COL_GREEN);
- printk(KERN_DEBUG "av8100_probe: mcde_hdmi_display_init_command_mode\n");
- PRNK_COL(PRNK_COL_WHITE);
- mcde_hdmi_display_init_command_mode(mcde_mode);
-#endif
-#endif /* CONFIG_MCDE_ENABLE_FEATURE_HW_V1_SUPPORT */
-
- /** Register av8100 driver */
- ret = misc_register(&av8100_miscdev);
+ ret = av8100_config_init();
if (ret) {
- printk("registering av8100 driver as misc device fails\n");
- goto av8100_misc_fail;
- }
- if (!i2c_check_functionality(i2cClient->adapter, I2C_FUNC_SMBUS_BYTE_DATA |
- I2C_FUNC_SMBUS_READ_WORD_DATA)) {
- ret = -ENODEV;
- goto err;
+ pr_info("av8100_config_init failed\n");
+ goto err;
}
- av8100Data = kcalloc(1, sizeof(*av8100Data), GFP_KERNEL);
- if(!av8100Data) {
- ret = -ENOMEM;
+ if (!i2c_check_functionality(i2cClient->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA |
+ I2C_FUNC_SMBUS_READ_WORD_DATA)) {
+ ret = -ENODEV;
+ pr_info("av8100 i2c_check_functionality failed\n");
goto err;
}
- init_waitqueue_head(&av8100_event);
- //INIT_WORK(&av8100Data->work, u8500_av8100_wq);
- av8100Data->client = i2cClient;
- i2c_set_clientdata(i2cClient,av8100Data);
- /* Test pattern is local to AV8100 driver so if set no MCDE probe as no interaction with it */
- if(mcde_get_hdmi_flag())
- {
- printk("HDMI is included in the menuconfig\n");
-
- /** powerup the av8100IC */
- ret = av8100_powerup(i2cClient, id);
- if(ret != AV8100_OK){
- printk("error in init the hdmi client\n");
- goto err;
- }
- g_av8100_state = AV8100_OPMODE_INIT;
-
- ret = av8100_download_firmware(i2cClient, FIRMWARE_DOWNLOAD_ENTRY_REG, av8100_fw_buff, fw_size, I2C_INTERFACE);
- if(ret != AV8100_OK){
- printk("error in av8100 firmware download: failed\n");
- goto err;
- }
-
- av8100_configure_hdmi(i2cClient);
+ init_waitqueue_head(&av8100_event);
-#ifndef TEST_PATTERN_TEST
-#ifdef AV8100_USE_KERNEL_THREAD
- kernel_thread((void*)av8100_thread, NULL, CLONE_FS | CLONE_SIGHAND);
-#endif
+ av8100_config->client = i2cClient;
+ av8100_config->id = (struct i2c_device_id *) id;
+ i2c_set_clientdata(i2cClient, av8100_config);
- ret = request_irq(pdata->irq, av8100_intr_handler,
- IRQF_TRIGGER_RISING, "av8100", av8100Data);
- if (ret) {
- printk(KERN_ERR "unable to request for the irq %d\n", GPIO_TO_IRQ(192));
- gpio_free(pdata->irq);
- goto err;
- }
- ret = av8100_enable_interrupt(i2cClient);
- if(ret != AV8100_OK){
- printk("error in enabling the interrupts\n");
- goto err;
- }
+ kthread_run(av8100_thread, NULL, "hdmi_thread");
- av8100_hdmi_on(av8100Data);
-#endif /* TEST_PATTERN_TEST */
+ ret = request_irq(pdata->irq, av8100_intr_handler,
+ IRQF_TRIGGER_RISING, "av8100", av8100_config);
+ if (ret) {
+ printk(KERN_ERR "av8100_hw request_irq %d failed %d\n",
+ pdata->irq, ret);
+ gpio_free(pdata->irq);
+ goto err;
}
+
return ret;
err:
- kfree(i2cClient);
-av8100_misc_fail:
return ret;
}
-
-/**
- * av8100_remove() - This function will be used to unload the av8100 driver.
- * @i2c: i2c client device
- *
- **/
-static int __exit av8100_remove(struct i2c_client *i2cClient)
+static int __devexit av8100_remove(struct i2c_client *i2cClient)
{
- i2c_set_clientdata(i2cClient,NULL);
+ printk(KERN_DEBUG "%s\n", __func__);
+
+ av8100_config_exit();
+
return 0;
}
-static const struct i2c_device_id av8100_id[] = {
- { "av8100", 0 },
- { }
-};
-MODULE_DEVICE_TABLE(i2c, av8100);
+int av8100_init(void)
+{
+ int ret;
-static struct i2c_driver av8100_driver = {
- .driver = {
- .name = "av8100",
- .owner = THIS_MODULE,
- },
- .probe = av8100_probe,
- .remove = __exit_p(av8100_remove),
- .id_table = av8100_id,
-};
+ printk(KERN_DEBUG "%s\n", __func__);
-static int __init av8100_init(void)
-{
- return i2c_add_driver(&av8100_driver);
-}
+ ret = i2c_add_driver(&av8100_driver);
+ if (ret) {
+ printk(KERN_DEBUG "av8100 i2c_add_driver failed\n");
+ goto av8100_init_err;
+ }
+ ret = misc_register(&av8100_miscdev);
+ if (ret) {
+ printk(KERN_DEBUG "av8100 misc_register failed\n");
+ goto av8100_init_err;
+ }
+
+ hdmi_init();
+
+ return ret;
+
+av8100_init_err:
+ return ret;
+}
module_init(av8100_init);
-static void __exit av8100_exit(void)
+
+void av8100_exit(void)
{
+ printk(KERN_DEBUG "%s\n", __func__);
+
+ hdmi_exit();
+
+ misc_deregister(&av8100_miscdev);
i2c_del_driver(&av8100_driver);
}
-
module_exit(av8100_exit);
+
+MODULE_AUTHOR("Per Persson <per.xb.persson@stericsson.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ST-Ericsson hdmi display driver");
diff --git a/drivers/video/av8100/av8100_fw.h b/drivers/video/av8100/av8100_fw.h
new file mode 100755
index 00000000000..5c668476077
--- /dev/null
+++ b/drivers/video/av8100/av8100_fw.h
@@ -0,0 +1,2065 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+/* AV8100 Firmware version : V4.0 HDCP 1.0 + 3D supported */
+#define AV8100_FW_SIZE 16384
+char av8100_receivetab[AV8100_FW_SIZE];
+char av8100_transmittab[AV8100_FW_SIZE];
+char av8100_fw_buff[AV8100_FW_SIZE] = {
+0x80, 0xfe, 0xcb, 0xfe, 0x8b, 0xf4, 0x42, 0xf6,
+0x42, 0xf6, 0x98, 0xf7, 0x41, 0xf5, 0x9d, 0xf7,
+0xe5, 0xf8, 0xa7, 0xfa, 0xbc, 0xfa, 0xcd, 0xfa,
+0xdf, 0xfa, 0xf2, 0xfa, 0xf7, 0xfa, 0xfc, 0xfa,
+0x01, 0xfb, 0x06, 0xfb, 0x1b, 0xfb, 0x55, 0xfb,
+0xec, 0xfb, 0x85, 0xf4, 0x85, 0xf4, 0x86, 0xf4,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x81, 0xea, 0xad, 0xec, 0xad,
+0x38, 0x20, 0x1b, 0x72, 0x80, 0x81, 0x4d, 0x51,
+0x4d, 0x51, 0x4d, 0x51, 0x4d, 0x51, 0x4d, 0x51,
+0x4d, 0x51, 0xb4, 0x20, 0xf4, 0x2a, 0x5a, 0x90,
+0x82, 0xfe, 0xcd, 0x80, 0x00, 0xaf, 0x72, 0x93,
+0xa3, 0x20, 0x5f, 0x90, 0x80, 0x80, 0x97, 0x90,
+0x8d, 0x20, 0x0f, 0xab, 0x01, 0xa6, 0x88, 0x89,
+0x90, 0x96, 0xad, 0x97, 0x90, 0x9a, 0xad, 0x8b,
+0x93, 0x9e, 0xad, 0x97, 0x90, 0xa2, 0xad, 0x80,
+0xb7, 0xa6, 0xad, 0x81, 0xb7, 0xaa, 0xad, 0x82,
+0xb7, 0xae, 0xad, 0x26, 0x31, 0x20, 0x08, 0x72,
+0x82, 0xb7, 0x21, 0xa6, 0x81, 0xb7, 0xc2, 0xa6,
+0x80, 0xb7, 0x01, 0xa6, 0xb4, 0x20, 0xf5, 0x2a,
+0x5a, 0x90, 0x80, 0x00, 0xa7, 0x72, 0x93, 0xcc,
+0xad, 0x49, 0x27, 0x97, 0x90, 0x5d, 0x90, 0xd4,
+0xad, 0x82, 0xb7, 0xd8, 0xad, 0x81, 0xb7, 0xdc,
+0xad, 0x80, 0xb7, 0xe0, 0xad, 0xff, 0xae, 0x90,
+0x81, 0x59, 0x29, 0xea, 0x26, 0x5a, 0xfb, 0x38,
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