diff options
Diffstat (limited to 'arch/arm/mach-ux500/include/mach/mcde_a0.h')
| -rwxr-xr-x | arch/arm/mach-ux500/include/mach/mcde_a0.h | 896 |
1 files changed, 0 insertions, 896 deletions
diff --git a/arch/arm/mach-ux500/include/mach/mcde_a0.h b/arch/arm/mach-ux500/include/mach/mcde_a0.h deleted file mode 100755 index 8c06a628479..00000000000 --- a/arch/arm/mach-ux500/include/mach/mcde_a0.h +++ /dev/null @@ -1,896 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#define WRITE_FIELD(reg, field, value) \ - (reg = (reg & (~((field##_MASK) << (field##_SHIFT)))) | ((value & (field##_MASK)) << (field##_SHIFT)) ) - - -#define MCDE_CR (MCDE_BASE + 0x0) -#define MCDE_CR_MCDEEN 0x80000000 -#define MCDE_CR_AUTOCLKG_EN 0x40000000 -#define MCDE_CR_FABMUX 0x00020000 -#define MCDE_CR_F01MUX 0x00010000 -#define MCDE_CR_IFIFOCTRLEN 0x00008000 -#define MCDE_CR_DPIA_EN 0x00000200 -#define MCDE_CR_DPIB_EN 0x00000100 -#define MCDE_CR_DPIC0_EN 0x00000080 -#define MCDE_CR_DPIC1_EN 0x00000040 -#define MCDE_CR_DSIVID0_EN 0x00000020 -#define MCDE_CR_DSIVID1_EN 0x00000010 -#define MCDE_CR_DSIVID2_EN 0x00000008 -#define MCDE_CR_DSICMD0_EN 0x00000004 -#define MCDE_CR_DSICMD1_EN 0x00000002 -#define MCDE_CR_DSICMD2_EN 0x00000001 - - -#define MCDE_CONF0 (MCDE_BASE + 0x4) -#define MCDE_CONF0_OUTMUX4_SHIFT 28 -#define MCDE_CONF0_OUTMUX4_MASK 0x7 -#define MCDE_CONF0_OUTMUX3_SHIFT 25 -#define MCDE_CONF0_OUTMUX3_MASK 0x7 -#define MCDE_CONF0_OUTMUX2_SHIFT 22 -#define MCDE_CONF0_OUTMUX2_MASK 0x7 -#define MCDE_CONF0_OUTMUX1_SHIFT 19 -#define MCDE_CONF0_OUTMUX1_MASK 0x7 -#define MCDE_CONF0_OUTMUX0_SHIFT 16 -#define MCDE_CONF0_OUTMUX0_MASK 0x7 -#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT 12 -#define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x7 -#define MCDE_CONF0_FSYNCTRLB 0x00000800 -#define MCDE_CONF0_FSYNCTRLA 0x00000400 -#define MCDE_CONF0_SWAP_B_C1 0x00000200 -#define MCDE_CONF0_SWAP_A_C0 0x00000100 -#define MCDE_CONF0_SYNCMUX7 0x00000080 -#define MCDE_CONF0_SYNCMUX6 0x00000040 -#define MCDE_CONF0_SYNCMUX5 0x00000020 -#define MCDE_CONF0_SYNCMUX4 0x00000010 -#define MCDE_CONF0_SYNCMUX3 0x00000008 -#define MCDE_CONF0_SYNCMUX2 0x00000004 -#define MCDE_CONF0_SYNCMUX1 0x00000002 -#define MCDE_CONF0_SYNCMUX0 0x00000001 - - -#define MCDE_SSP (MCDE_BASE + 0x8) -#define MCDE_SSP_SSPEN 0x00010000 -#define MCDE_SSP_SSPCMD 0x00000100 -#define MCDE_SSP_SSPDATA_SHIFT 0 -#define MCDE_SSP_SSPDATA_MASK 0xFF - - -#define MCDE_AIS (MCDE_BASE + 0x100) -#define MCDE_AIS_DSI2AI 0x00000040 -#define MCDE_AIS_DSI1AI 0x00000020 -#define MCDE_AIS_DSI0AI 0x00000010 -#define MCDE_AIS_MCDEERRI 0x00000008 -#define MCDE_AIS_MCDECHNLI 0x00000004 -#define MCDE_AIS_MCDEOVLI 0x00000002 -#define MCDE_AIS_MCDEPPI 0x00000001 - - -#define MCDE_IMSCPP (MCDE_BASE + 0x104) -#define MCDE_IMSCPP_ROTFDIM_SHIFT 6 -#define MCDE_IMSCPP_ROTFDIM_MASK 0x3 -#define MCDE_IMSCPP_VCMPC1IM 0x00000020 -#define MCDE_IMSCPP_VCMPC0IM 0x00000010 -#define MCDE_IMSCPP_VSCC1IM 0x00000008 -#define MCDE_IMSCPP_VSCC0IM 0x00000004 -#define MCDE_IMSCPP_VCMPBIM 0x00000002 -#define MCDE_IMSCPP_VCMPAIM 0x00000001 - - -#define MCDE_IMSCOVL (MCDE_BASE + 0x108) -#define MCDE_IMSCOVL_OVLFDIM_SHIFT 16 -#define MCDE_IMSCOVL_OVLFDIM_MASK 0xFFFF -#define MCDE_IMSCOVL_OVLRDIM_SHIFT 0 -#define MCDE_IMSCOVL_OVLRDIM_MASK 0xFFFF - - -#define MCDE_IMSCCHNL (MCDE_BASE + 0x10C) -#define MCDE_IMSCCHNL_CHNLAIM_SHIFT 16 -#define MCDE_IMSCCHNL_CHNLAIM_MASK 0xFFFF -#define MCDE_IMSCCHNL_CHNLRDIM_SHIFT 0 -#define MCDE_IMSCCHNL_CHNLRDIM_MASK 0xFFFF - - -#define MCDE_IMSCERR (MCDE_BASE + 0x110) -#define MCDE_IMSCERR_OVLFERRIM_SHIFT 16 -#define MCDE_IMSCERR_OVLFERRIM_MASK 0xFFFF -#define MCDE_IMSCERR_FUC1IM 0x00000100 -#define MCDE_IMSCERR_FUC0IM 0x00000080 -#define MCDE_IMSCERR_ROTBFEIM_SHIFT 5 -#define MCDE_IMSCERR_ROTBFEIM_MASK 0x3 -#define MCDE_IMSCERR_ROTAFEIM_SHIFT 3 -#define MCDE_IMSCERR_ROTAFEIM_MASK 0x3 -#define MCDE_IMSCERR_SCHBLCKDIM 0x00000004 -#define MCDE_IMSCERR_FUBIM 0x00000002 -#define MCDE_IMSCERR_FUAIM 0x00000001 - - -#define MCDE_RISPP (MCDE_BASE + 0x114) -#define MCDE_RISPP_ROTFDRIS_SHIFT 6 -#define MCDE_RISPP_ROTFDRIS_MASK 0x3 -#define MCDE_RISPP_VCMPC1RIS 0x00000020 -#define MCDE_RISPP_VCMPC0RIS 0x00000010 -#define MCDE_RISPP_VSCC1RIS 0x00000008 -#define MCDE_RISPP_VSCC0RIS 0x00000004 -#define MCDE_RISPP_VCMPBRIS 0x00000002 -#define MCDE_RISPP_VCMPARIS 0x00000001 - - -#define MCDE_RISOVL (MCDE_BASE + 0x118) -#define MCDE_RISOVL_OVLFDRIS_SHIFT 16 -#define MCDE_RISOVL_OVLFDRIS_MASK 0xFFFF -#define MCDE_RISOVL_OVLRDRIS_SHIFT 0 -#define MCDE_RISOVL_OVLRDRIS_MASK 0xFFFF - - -#define MCDE_RISCHNL (MCDE_BASE + 0x11C) -#define MCDE_RISCHNL_CHNLARIS_SHIFT 16 -#define MCDE_RISCHNL_CHNLARIS_MASK 0xFFFF -#define MCDE_RISCHNL_CHNLRDRIS_SHIFT 0 -#define MCDE_RISCHNL_CHNLRDRIS_MASK 0xFFFF - - -#define MCDE_RISERR (MCDE_BASE + 0x120) -#define MCDE_RISERR_OVLFERRIS_SHIFT 16 -#define MCDE_RISERR_OVLFERRIS_MASK 0xFFFF -#define MCDE_RISERR_FUC1RIS 0x00000100 -#define MCDE_RISERR_FUC0RIS 0x00000080 -#define MCDE_RISERR_ROTBFERIS_SHIFT 5 -#define MCDE_RISERR_ROTBFERIS_MASK 0x3 -#define MCDE_RISERR_ROTAFERIS_SHIFT 3 -#define MCDE_RISERR_ROTAFERIS_MASK 0x3 -#define MCDE_RISERR_SCHBLCKDRIS 0x00000004 -#define MCDE_RISERR_FUBRIS 0x00000002 -#define MCDE_RISERR_FUARIS 0x00000001 - - -#define MCDE_MISPP (MCDE_BASE + 0x124) -#define MCDE_MISPP_ROTFDMIS_SHIFT 6 -#define MCDE_MISPP_ROTFDMIS_MASK 0x3 -#define MCDE_MISPP_VCMPC1MIS 0x00000020 -#define MCDE_MISPP_VCMPC0MIS 0x00000010 -#define MCDE_MISPP_VSCC1MIS 0x00000008 -#define MCDE_MISPP_VSCC0MIS 0x00000004 -#define MCDE_MISPP_VCMPBMIS 0x00000002 -#define MCDE_MISPP_VCMPAMIS 0x00000001 - - -#define MCDE_MISOVL (MCDE_BASE + 0x128) -#define MCDE_MISOVL_OVLFDMIS_SHIFT 16 -#define MCDE_MISOVL_OVLFDMIS_MASK 0xFFFF -#define MCDE_MISOVL_OVLRDMIS_SHIFT 0 -#define MCDE_MISOVL_OVLRDMIS_MASK 0xFFFF - - -#define MCDE_MISCHNL (MCDE_BASE + 0x12C) -#define MCDE_MISCHNL_CHNLAMIS_SHIFT 16 -#define MCDE_MISCHNL_CHNLAMIS_MASK 0xFFFF -#define MCDE_MISCHNL_CHNLRDMIS_SHIFT 0 -#define MCDE_MISCHNL_CHNLRDMIS_MASK 0xFFFF -#define MCDE_MISCHNL_CHNL_A 0x00000001 -#define MCDE_MISCHNL_CHNL_B 0x00000002 -#define MCDE_MISCHNL_CHNL_C0 0x00000004 -#define MCDE_MISCHNL_CHNL_C1 0x00000008 - - -#define MCDE_MISERR (MCDE_BASE + 0x130) -#define MCDE_MISERR_OVLFERMIS_SHIFT 16 -#define MCDE_MISERR_OVLFERMIS_MASK 0xFFFF -#define MCDE_MISERR_FUC1MIS 0x00000100 -#define MCDE_MISERR_FUC0MIS 0x00000080 -#define MCDE_MISERR_ROTBFEMIS_SHIFT 5 -#define MCDE_MISERR_ROTBFEMIS_MASK 0x3 -#define MCDE_MISERR_ROTAFEMIS_SHIFT 3 -#define MCDE_MISERR_ROTAFEMIS_MASK 0x3 -#define MCDE_MISERR_SCHBLCKDMIS 0x00000004 -#define MCDE_MISERR_FUBMIS 0x00000002 -#define MCDE_MISERR_FUAMIS 0x00000001 - - -#define MCDE_SISPP (MCDE_BASE + 0x134) -#define MCDE_SISOVL (MCDE_BASE + 0x138) -#define MCDE_SISCHNL (MCDE_BASE + 0x13C) -#define MCDE_SISERR (MCDE_BASE + 0x140) - - -#define MCDE_PID (MCDE_BASE + 0x1FC) -#define MCDE_PID_MAJOR_SHIFT 24 -#define MCDE_PID_MAJOR_MASK 0xFF -#define MCDE_PID_MINOR_SHIFT 16 -#define MCDE_PID_MINOR_MASK 0xFF -#define MCDE_PID_DEV_SHIFT 8 -#define MCDE_PID_DEV_MASK 0xFF -#define MCDE_PID_METALFIX_SHIFT 0 -#define MCDE_PID_METALFIX_MASK 0xFF - - -#define MCDE_EXTSRCA0 (MCDE_BASE + 0x200) -#define MCDE_EXTSRCA1 (MCDE_BASE + 0x204) -#define MCDE_EXTSRCA2 (MCDE_BASE + 0x2C8) - - -#define MCDE_EXTSRCCONF (MCDE_BASE + 0x20C) -#define MCDE_EXTSRCCONF_BEPO 0x00004000 -#define MCDE_EXTSRCCONF_BEBO 0x00002000 -#define MCDE_EXTSRCCONF_BGR 0x00001000 -#define MCDE_EXTSRCCONF_BPP_SHIFT 8 -#define MCDE_EXTSRCCONF_BPP_MASK 0xF -#define MCDE_EXTSRCCONF_PRI_OVLID_SHIFT 4 -#define MCDE_EXTSRCCONF_PRI_OVLID_MASK 0xF -#define MCDE_EXTSRCCONF_BUF_NB_SHIFT 2 -#define MCDE_EXTSRCCONF_BUF_NB_MASK 0x3 -#define MCDE_EXTSRCCONF_BUF_ID_SHIFT 0 -#define MCDE_EXTSRCCONF_BUF_ID_MASK 0x3 - - -#define MCDE_EXTSRCCR (MCDE_BASE + 0x210) -#define MCDE_EXTSRCCR_FORCE_FS_DIV 0x00000008 -#define MCDE_EXTSRCCR_FS_DIV_DISABLE 0x00000004 -#define MCDE_EXTSRCCR_MULTIOVL_CTRL 0x00000002 -#define MCDE_EXTSRCCR_SEL_MOD_SHIFT 0 -#define MCDE_EXTSRCCR_SEL_MOD_MASK 0x3 - - -#define MCDE_OVLCR (MCDE_BASE + 0x400) -#define MCDE_OVLCR_ROTBURSTSIZE_SHIFT 28 -#define MCDE_OVLCR_ROTBURSTSIZE_MASK 0xF -#define MCDE_OVLCR_MAXOUTSTANDING_SHIFT 24 -#define MCDE_OVLCR_MAXOUTSTANDING_MASK 0xF -#define MCDE_OVLCR_BURSTSIZE_SHIFT 20 -#define MCDE_OVLCR_BURSTSIZE_MASK 0xF -#define MCDE_OVLCR_STBPRIO_SHIFT 16 -#define MCDE_OVLCR_STBPRIO_MASK 0xF -#define MCDE_OVLCR_FETCH_ROPC_SHIFT 8 -#define MCDE_OVLCR_GETCH_ROPC_MASK 0xFF -#define MCDE_OVLCR_OVLB 0x00000080 -#define MCDE_OVLCR_OVLR 0x00000040 -#define MCDE_OVLCR_OVLF 0x00000020 -#define MCDE_OVLCR_ALPHAPMEN 0x00000010 -#define MCDE_OVLCR_CKEYEN 0x00000008 -#define MCDE_OVLCR_COLCCTRL_SHIFT 1 -#define MCDE_OVLCR_COLCCTRL_MASK 0x3 -#define MCDE_OVLCR_OVLEN 0x00000001 - - -#define MCDE_OVLCONF (MCDE_BASE + 0x404) -#define MCDE_OVLCONF_LPF_SHIFT 16 -#define MCDE_OVLCONF_LPF_MASK 0x7FF -#define MCDE_OVLCONF_EXTSRC_ID_SHIFT 11 -#define MCDE_OVLCONF_EXTSRC_ID_MASK 0xF -#define MCDE_OVLCONF_PPL_SHIFT 0 -#define MCDE_OVLCONF_PPL_MASK 0x7FF - - -#define MCDE_OVLCONF2 (MCDE_BASE + 0x408) -#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_SHIFT 16 -#define MCDE_OVLCONF2_PIXELFETCHWATERMARKLEVEL_MASK 0x1FFF -#define MCDE_OVLCONF2_PIXOFF_SHIFT 10 -#define MCDE_OVLCONF2_PIXOFF_MASK 0x3F -#define MCDE_OVLCONF2_OPQ 0x00000200 -#define MCDE_OVLCONF2_ALPHAVALUE_SHIFT 1 -#define MCDE_OVLCONF2_ALPHAVALUE_MASK 0xFF -#define MCDE_OVLCONF2_BP 0x00000001 - - -#define MCDE_OVLLJINC (MCDE_BASE + 0x40C) - - -#define MCDE_OVLCROP (MCDE_BASE + 0x410) -#define MCDE_OVLCROP_LMRGN_SHIFT 22 -#define MCDE_OVLCROP_LMRGN_MASK 0x3FF -#define MCDE_OVLCROP_TMRGN_SHIFT 0 -#define MCDE_OVLCROP_TMRGN_MASK 0x3FFFFF - - -#define MCDE_OVLCOMP (MCDE_BASE + 0x414) -#define MCDE_OVLCOMP_Z_SHIFT 27 -#define MCDE_OVLCOMP_Z_MASK 0xF -#define MCDE_OVLCOMP_YPOS_SHIFT 16 -#define MCDE_OVLCOMP_YPOS_MASK 0x7FF -#define MCDE_OVLCOMP_CH_ID_SHIFT 11 -#define MCDE_OVLCOMP_CH_ID_MASK 0xF -#define MCDE_OVLCOMP_XPOS_SHIFT 0 -#define MCDE_OVLCOMP_XPOS_MASK 0x7FF - - -#define MCDE_CHNLCONF (MCDE_BASE + 0x600) -#define MCDE_CHNLCONF_LPF_SHIFT 16 -#define MCDE_CHNLCONF_LPF_MASK 0x7FF -#define MCDE_CHNLCONF_PPL_SHIFT 0 -#define MCDE_CHNLCONF_PPL_MASK 0x7FF - - -#define MCDE_CHNLSTAT (MCDE_BASE + 0x604) -#define MCDE_CHNLSTAT_CHNLBLBCKGND_EN 0x00010000 -#define MCDE_CHNLSTAT_CHNLA 0x00000002 -#define MCDE_CHNLSTAT_CHNLRD 0x00000001 - - -#define MCDE_CHNLSYNCHMOD (MCDE_BASE + 0x608) -#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_SHIFT 2 -#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_MASK 0x7 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SHIFT 0 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_MASK 0x3 -#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_SELECTED_FORMATER 0x0 -#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC0 0x1 -#define MCDE_CHNLSYNCHMOD_OUT_SYNCH_SRC_FROM_MCDEVSYNC1 0x2 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_OUTPUT 0x0 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_AUTO 0x1 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_SW 0x2 -#define MCDE_CHNLSYNCHMOD_SRC_SYNCH_EXTERNAL 0x3 - - -#define MCDE_CHNLSYNCHSW (MCDE_BASE + 0x60C) -#define MCDE_CHNLSYNCHSW_SW_TRIG 0x00000001 - - -#define MCDE_CHNLBCKGNDCOL (MCDE_BASE + 0x610) -#define MCDE_CHNLBCKGNDCOL_R_SHIFT 16 -#define MCDE_CHNLBCKGNDCOL_R_MASK 0xFF -#define MCDE_CHNLBCKGNDCOL_G_SHIFT 8 -#define MCDE_CHNLBCKGNDCOL_G_MASK 0xFF -#define MCDE_CHNLBCKGNDCOL_B_SHIFT 0 -#define MCDE_CHNLBCKGNDCOL_B_MASK 0xFF - - -#define MCDE_CHNLPRIO (MCDE_BASE + 0x614) -#define MCDE_CHNLPRIO_CHNLPRIO_SHIFT 0 -#define MCDE_CHNLPRIO_CHNLPRIO_MASK 0xF - - -#define MCDE_CR0 (MCDE_BASE + 0x800) -#define MCDE_CR0_ROTBURSTSIZE_SHIFT 25 -#define MCDE_CR0_ROTBURSTSIZE_MASK 0x7F -#define MCDE_CR0_ROTEN 0x01000000 -#define MCDE_CR0_ALPHABLEND_SHIFT 16 -#define MCDE_CR0_ALPHABLEND_MASK 0xFF -#define MCDE_CR0_OLEDEN 0x00008000 -#define MCDE_CR0_PALMODE 0x00004000 -#define MCDE_CR0_FLICKFORMAT 0x00002000 -#define MCDE_CR0_FLICKMODE_SHIFT 11 -#define MCDE_CR0_FLICKMODE_MASK 0x3 -#define MCDE_CR0_BLENDCTRL 0x00000400 -#define MCDE_CR0_KEYCTRL_SHIFT 7 -#define MCDE_CR0_KEYCTRL_MASK 0x7 -#define MCDE_CR0_GAMEN 0x00000040 -#define MCDE_CR0_DITHEN 0x00000020 -#define MCDE_CR0_PALEN 0x00000010 -#define MCDE_CR0_AFLICKEN 0x00000008 -#define MCDE_CR0_BLENDEN 0x00000004 -#define MCDE_CR0_POWEREN 0x00000002 -#define MCDE_CR0_FLOEN 0x00000001 - -#define MCDE_CR1 (MCDE_BASE + 0x804) -#define MCDE_CR1_TEFFECTEN 0x80000000 -#define MCDE_CR1_CLKTYPE 0x40000000 -#define MCDE_CR1_BCD 0x20000000 -#define MCDE_CR1_OUTBPP_SHIFT 25 -#define MCDE_CR1_OUTBPP_MASK 0xF -#define MCDE_CR1_CDWIN_SHIFT 13 -#define MCDE_CR1_CDWIN_MASK 0xF -#define MCDE_CR1_CLKSEL_SHIFT 10 -#define MCDE_CR1_CLKSEL_MASK 0x7 -#define MCDE_CR1_PCD_SHIFT 0 -#define MCDE_CR1_PCD_MASK 0x3FF - - -#define MCDE_COLKEY (MCDE_BASE + 0x808) -#define MCDE_COLKEY_KEYA_SHIFT 24 -#define MCDE_COLKEY_KEYA_MASK 0xFF -#define MCDE_COLKEY_KEYR_SHIFT 16 -#define MCDE_COLKEY_KEYR_MASK 0xFF -#define MCDE_COLKEY_KEYG_SHIFT 8 -#define MCDE_COLKEY_KEYG_MASK 0xFF -#define MCDE_COLKEY_KEYB_SHIFT 0 -#define MCDE_COLKEY_KEYB_MASK 0xFF - - -#define MCDE_FCOLKEY (MCDE_BASE + 0x80C) -#define MCDE_FCOLKEY_FKEYA_SHIFT 24 -#define MCDE_FCOLKEY_FKEYA_MASK 0xFF -#define MCDE_FCOLKEY_FKEYR_SHIFT 16 -#define MCDE_FCOLKEY_FKEYR_MASK 0xFF -#define MCDE_FCOLKEY_FKEYG_SHIFT 8 -#define MCDE_FCOLKEY_FKEYG_MASK 0xFF -#define MCDE_FCOLKEY_FKEYB_SHIFT 0 -#define MCDE_FCOLKEY_FKEYB_MASK 0xFF - - -#define MCDE_RGBCONV1 (MCDE_BASE + 0x810) -#define MCDE_RGBCONV1_YR_RED_SHIFT 16 -#define MCDE_RGBCONV1_YR_RED_MASK 0x7FF -#define MCDE_RGBCONV1_YR_GREEN_SHIFT 0 -#define MCDE_RGBCONV1_YR_GREEN_MASK 0x7FF - - -#define MCDE_RGBCONV2 (MCDE_BASE + 0x814) -#define MCDE_RGBCONV2_YR_BLUE_SHIFT 16 -#define MCDE_RGBCONV2_YR_BLUE_MASK 0x7FF -#define MCDE_RGBCONV2_CR_RED_SHIFT 0 -#define MCDE_RGBCONV2_CR_RED_MASK 0x7FF - - -#define MCDE_RGBCONV3 (MCDE_BASE + 0x818) -#define MCDE_RGBCONV3_CR_GREEN_SHIFT 16 -#define MCDE_RGBCONV3_CR_GREEN_MASK 0x7FF -#define MCDE_RGBCONV3_CR_BLUE_SHIFT 0 -#define MCDE_RGBCONV3_CR_BLUE_MASK 0x7FF - - -#define MCDE_RGBCONV4 (MCDE_BASE + 0x81C) -#define MCDE_RGBCONV4_CB_RED_SHIFT 16 -#define MCDE_RGBCONV4_CB_RED_MASK 0x7FF -#define MCDE_RGBCONV4_CB_GREEN_SHIFT 0 -#define MCDE_RGBCONV4_CB_GREEN_MASK 0x7FF - - -#define MCDE_RGBCONV5 (MCDE_BASE + 0x820) -#define MCDE_RGBCONV5_CB_BLUE_SHIFT 16 -#define MCDE_RGBCONV5_CB_BLUE_MASK 0x7FF -#define MCDE_RGBCONV5_OFF_RED_SHIFT 0 -#define MCDE_RGBCONV5_OFF_RED_MASK 0x7FF - - -#define MCDE_RGBCONV6 (MCDE_BASE + 0x824) -#define MCDE_RGBCONV6_OFF_GREEN_SHIFT 16 -#define MCDE_RGBCONV6_OFF_GREEN_MASK 0x7FF -#define MCDE_RGBCONV6_OFF_BLUE_SHIFT 0 -#define MCDE_RGBCONV6_OFF_BLUE_MASK 0x7FF - - -#define MCDE_FFCOEF0 (MCDE_BASE + 0x828) -#define MCDE_FFCOEF0_TO_SHIFT 24 -#define MCDE_FFCOEF0_TO_MASK 0x0xF -#define MCDE_FFCOEF0_COEFF0_N3_SHIFT 16 -#define MCDE_FFCOEF0_COEFF0_N3_MASK 0xFF -#define MCDE_FFCOEF0_COEFF0_N2_SHIFT 8 -#define MCDE_FFCOEF0_COEFF0_N2_MASK 0xFF -#define MCDE_FFCOEF0_COEFF0_N1_SHIFT 0 -#define MCDE_FFCOEF0_COEFF0_N1_MASK 0xFF - - -#define MCDE_FFCOEF1 (MCDE_BASE + 0x82C) -#define MCDE_FFCOEF1_T1_SHIFT 24 -#define MCDE_FFCOEF1_T1_MASK 0x0xF -#define MCDE_FFCOEF1_COEFF1_N3_SHIFT 16 -#define MCDE_FFCOEF1_COEFF1_N3_MASK 0xFF -#define MCDE_FFCOEF1_COEFF1_N2_SHIFT 8 -#define MCDE_FFCOEF1_COEFF1_N2_MASK 0xFF -#define MCDE_FFCOEF1_COEFF1_N1_SHIFT 0 -#define MCDE_FFCOEF1_COEFF1_N1_MASK 0xFF - - -#define MCDE_FFCOEF2 (MCDE_BASE + 0x830) -#define MCDE_FFCOEF2_T2_SHIFT 24 -#define MCDE_FFCOEF2_T2_MASK 0x0xF -#define MCDE_FFCOEF2_COEFF2_N3_SHIFT 16 -#define MCDE_FFCOEF2_COEFF2_N3_MASK 0xFF -#define MCDE_FFCOEF2_COEFF2_N2_SHIFT 8 -#define MCDE_FFCOEF2_COEFF2_N2_MASK 0xFF -#define MCDE_FFCOEF2_COEFF2_N1_SHIFT 0 -#define MCDE_FFCOEF2_COEFF2_N1_MASK 0xFF - - -#define MCDE_TVCR (MCDE_BASE + 0x838) -#define MCDE_TVCR_AVRGEN 0x00000100 -#define MCDE_TVCR_SDTVMODE_SHIFT 6 -#define MCDE_TVCR_SDTVMODE_MASK 0x3 -#define MCDE_TVCR_SDTVMODE_YC 0x0 -#define MCDE_TVCR_SDTVMODE_CY 0x1 -#define MCDE_TVCR_TVMODE_SHIFT 3 -#define MCDE_TVCR_TVMODE_MASK 0x7 -#define MCDE_TVCR_TVMODE_SDTV 0x0 -#define MCDE_TVCR_TVMODE_HDTV_480P 0x1 -#define MCDE_TVCR_TVMODE_HDTV_720P 0x2 -#define MCDE_TVCR_TVMODE_SDTV_DDR_LS_1ST 0x3 -#define MCDE_TVCR_TVMODE_SDTV_DDR_MS_1ST 0x4 -#define MCDE_TVCR_IFIELD_SHIFT 2 -#define MCDE_TVCR_IFIELD_MASK 0x1 -#define MCDE_TVCR_IFIELD_ACT_HGH 0x0 -#define MCDE_TVCR_IFIELD_ACT_LOW 0x1 -#define MCDE_TVCR_INTEREN 0x00000002 -#define MCDE_TVCR_SEL_MOD_SHIFT 0 -#define MCDE_TVCR_SEL_MOD_MASK 0x1 -#define MCDE_TVCR_SEL_MOD_LCD 0x0 -#define MCDE_TVCR_SEL_MOD_TV 0x1 - -#define MCDE_TVBL1 (MCDE_BASE + 0x83C) -#define MCDE_TVBL1_BSL1_SHIFT 16 -#define MCDE_TVBL1_BSL1_MASK 0x7FF -#define MCDE_TVBL1_BEL1_SHIFT 0 -#define MCDE_TVBL1_BEL1_MASK 0x7FF - - -#define MCDE_TVISL (MCDE_BASE + 0x840) -#define MCDE_TVISL_FSL2_SHIFT 16 -#define MCDE_TVISL_FSL2_MASK 0x7FF -#define MCDE_TVISL_FSL1_SHIFT 0 -#define MCDE_TVISL_FSL1_MASK 0x7FF - - -#define MCDE_TVDVO (MCDE_BASE + 0x844) -#define MCDE_TVDVO_DVO2_SHIFT 16 -#define MCDE_TVDVO_DVO2_MASK 0x7FF -#define MCDE_TVDVO_DVO1_SHIFT 0 -#define MCDE_TVDVO_DVO1_MASK 0x7FF - - -#define MCDE_TVTIM1 (MCDE_BASE + 0x84C) -#define MCDE_TVTIM1_DHO_SHIFT 0 -#define MCDE_TVTIM1_DHO_MASK 0x7FF - - -#define MCDE_TVLBALW (MCDE_BASE + 0x850) -#define MCDE_TVLBALW_ALW_SHIFT 16 -#define MCDE_TVLBALW_ALW_MASK 0x7FF -#define MCDE_TVLBALW_LBW_SHIFT 0 -#define MCDE_TVLBALW_LBW_MASK 0x7FF - - -#define MCDE_TVBL2 (MCDE_BASE + 0x854) -#define MCDE_TVBL2_BSL2_SHIFT 16 -#define MCDE_TVBL2_BSL2_MASK 0x7FF -#define MCDE_TVBL2_BEL2_SHIFT 0 -#define MCDE_TVBL2_BEL2_MASK 0x7FF - - -#define MCDE_TVBLU (MCDE_BASE + 0x858) -#define MCDE_TVBLU_TVBCR_SHIFT 16 -#define MCDE_TVBLU_TVBCR_MASK 0xFF -#define MCDE_TVBLU_TVBCB_SHIFT 8 -#define MCDE_TVBLU_TVBCB_MASK 0xFF -#define MCDE_TVBLU_TVBLU_SHIFT 0 -#define MCDE_TVBLU_TVBLU_MASK 0xFF - - -#define MCDE_LDCTIM0 (MCDE_BASE + 0x85C) -#define MCDE_LDCTIM0_REVVAEN 0x80000000 -#define MCDE_LDCTIM0_REVTGEN 0x40000000 -#define MCDE_LDCTIM0_REVLOADSEL_SHIFT 28 -#define MCDE_LDCTIM0_REVLOADSEL_MASK 0x3 -#define MCDE_LDCTIM0_REVDEL1_SHIFT 24 -#define MCDE_LDCTIM0_REVDEL1_MASK 0xF -#define MCDE_LDCTIM0_REVDEL0_SHIFT 16 -#define MCDE_LDCTIM0_REVDEL0_MASK 0xFF -#define MCDE_LDCTIM0_PSVAEN 0x00008000 -#define MCDE_LDCTIM0_PSTGEN 0x00004000 -#define MCDE_LDCTIM0_PSLOADSEL_SHIFT 12 -#define MCDE_LDCTIM0_PSLOADSEL_MASK 0x3 -#define MCDE_LDCTIM0_PSDEL1_SHIFT 8 -#define MCDE_LDCTIM0_PSDEL1_MASK 0xF -#define MCDE_LDCTIM0_PSDEL0_SHIFT 0 -#define MCDE_LDCTIM0_PSDEL0_MASK 0xFF - - -#define MCDE_LCDTIM1 (MCDE_BASE + 0x860) -#define MCDE_LCDTIM1_IOE 0x00800000 -#define MCDE_LCDTIM1_IPC 0x00400000 -#define MCDE_LCDTIM1_IHS 0x00200000 -#define MCDE_LCDTIM1_IVS 0x00100000 -#define MCDE_LCDTIM1_IVP 0x00080000 -#define MCDE_LCDTIM1_ICLSPL 0x00040000 -#define MCDE_LCDTIM1_ICLREV 0x00020000 -#define MCDE_LCDTIM1_ICLSP 0x00010000 -#define MCDE_LCDTIM1_SPLVAEN 0x00008000 -#define MCDE_LCDTIM1_SPLTGEN 0x00004000 -#define MCDE_LCDTIM1_SPLLOADSEL_SHIFT 12 -#define MCDE_LCDTIM1_SPLLOADSEL_MASK 0x3 -#define MCDE_LCDTIM1_SPLDEL1_SHIFT 8 -#define MCDE_LCDTIM1_SPLDEL1_MASK 0xF -#define MCDE_LCDTIM1_SPLDEL0_SHIFT 0 -#define MCDE_LCDTIM1_SPLDEL0_MASK 0xFF - - -#define MCDE_DITCTRL (MCDE_BASE + 0x864) -#define MCDE_DITCTRL_FOFFY_SHIFT 10 -#define MCDE_DITCTRL_FOFFY_MASK 0x1F -#define MCDE_DITCTRL_FOFFX_SHIFT 5 -#define MCDE_DITCTRL_FOFFX_MASK 0x1F -#define MCDE_DITCTRL_MASK 0x00000010 -#define MCDE_DITCTRL_MODE_SHIFT 2 -#define MCDE_DITCTRL_MODE_MASK 0x3 -#define MCDE_DITCTRL_COMP 0x00000002 -#define MCDE_DITCTRL_TEMP 0x00000001 - - -#define MCDE_DITOFF (MCDE_BASE + 0x868) -#define MCDE_DITOFF_YB_SHIFT 24 -#define MCDE_DITOFF_YB_MASK 0x1F -#define MCDE_DITOFF_XB_SHIFT 16 -#define MCDE_DITOFF_XB_MASK 0x1F -#define MCDE_DITOFF_YG_SHIFT 8 -#define MCDE_DITOFF_YG_MASK 0x1F -#define MCDE_DITOFF_XG_SHIFT 0 -#define MCDE_DITOFF_XG_MASK 0x1F - - -#define MCDE_PAL0 (MCDE_BASE + 0x86C) -#define MCDE_PAL0_GREEN_SHIFT 16 -#define MCDE_PAL0_GREEN_MASK 0xFFF -#define MCDE_PAL0_BLUE_SHIFT 0 -#define MCDE_PAL0_BLUE_MASK 0xFFF - - -#define MCDE_PAL1 (MCDE_BASE + 0x870) -#define MCDE_PAL1_RED_SHIFT 0 -#define MCDE_PAL1_RED_MASK 0xFFF - - -#define MCDE_ROTADD0 (MCDE_BASE + 0x874) -//#define MCDE_ROTADD0_SHIFT 3 -//#define MCDE_ROTADD0_MASK -#define MCDE_ROTADD1 (MCDE_BASE + 0x878) - - -#define MCDE_ROTCONF (MCDE_BASE + 0x87C) -#define MCDE_ROTCONF_RD_ROPC_SHIFT 24 -#define MCDE_ROTCONF_RD_ROPC_MASK 0xFF -#define MCDE_ROTCONF_WR_ROPC_SHIFT 16 -#define MCDE_ROTCONF_WR_ROPC_MASK 0xFF -#define MCDE_ROTCONF_STRIP_WIDTH_SHIFT 8 -#define MCDE_ROTCONF_STRIP_WIDTH_MASK 0xFF -#define MCDE_ROTCONF_RD_MAXOUT_SHIFT 6 -#define MCDE_ROTCONF_RD_MAXOUT_MASK 0x3 -#define MCDE_ROTCONF_WR_MAXOUT_SHIFT 4 -#define MCDE_ROTCONF_WR_MAXOUT_MASK 0x3 -#define MCDE_ROTCONF_ROTDIR 0x00000008 -#define MCDE_ROTCONF_ROTBURSTSIZE_SHIFT 0 -#define MCDE_ROTCONF_ROTBURSTSIZE_MASK 0x7 - - -#define MCDE_SYNCHCONF (MCDE_BASE + 0x880) -#define MCDE_SYNCHCONF_SWINTVCNT_SHIFT 18 -#define MCDE_SYNCHCONF_SWINTVCNT_MASK 0x3FFF -#define MCDE_SYNCHCONF_SWINTVEVENT_SHIFT 16 -#define MCDE_SYNCHCONF_SWINTVEVENT_MASK 0x3 -#define MCDE_SYNCHCONF_HWREQVCNT_SHIFT 2 -#define MCDE_SYNCHCONF_HWREQVCNT_MASK 0x3FFF -#define MCDE_SYNCHCONF_HWREQVEVENT_SHIFT 0 -#define MCDE_SYNCHCONF_HWREQVEVENT_MASK 0x3 - - -#define MCDE_GAM0 (MCDE_BASE + 0x888) -#define MCDE_GAM0_BLUE_SHIFT 0 -#define MCDE_GAM0_BLUE_MASK 0x00FFFFFF - - -#define MCDE_GAM1 (MCDE_BASE + 0x88C) -#define MCDE_GAM1_GREEN_SHIFT 0 -#define MCDE_GAM1_GREEN_MASK 0x00FFFFFF - - -#define MCDE_GAM2 (MCDE_BASE + 0x890) -#define MCDE_GAM2_RED_SHIFT 0 -#define MCDE_GAM2_RED_MASK 0x00FFFFFF - - -#define MCDE_OLEDCONV1 (MCDE_BASE + 0x894) -#define MCDE_OLEDCONV1_ALPHA_GREEN_SHIFT 16 -#define MCDE_OLEDCONV1_ALPHA_GREEN_MASK 0x3FFF -#define MCDE_OLEDCONV1_ALPHA_RED_SHIFT 0 -#define MCDE_OLEDCONV1_ALPHA_RED_MASK 0x3FFF - - -#define MCDE_OLEDCONV2 (MCDE_BASE + 0x898) -#define MCDE_OLEDCONV2_BETA_RED_SHIFT 16 -#define MCDE_OLEDCONV2_BETA_RED_MASK 0x3FFF -#define MCDE_OLEDCONV2_ALPHA_BLUE_SHIFT 0 -#define MCDE_OLEDCONV2_ALPHA_BLUE_MASK 0x3FFF - - -#define MCDE_OLEDCONV3 (MCDE_BASE + 0x89C) -#define MCDE_OLEDCONV3_BETA_BLUE_SHIFT 16 -#define MCDE_OLEDCONV3_BETA_BLUE_MASK 0x3FFF -#define MCDE_OLEDCONV3_BETA_GREEN_SHIFT 0 -#define MCDE_OLEDCONV3_BETA_GREEN_MASK 0x3FFF - - -#define MCDE_OLEDCONV4 (MCDE_BASE + 0x8A0) -#define MCDE_OLEDCONV4_GAMMA_GREEN_SHIFT 16 -#define MCDE_OLEDCONV4_GAMMA_GREEN_MASK 0x3FFF -#define MCDE_OLEDCONV4_GAMMA_RED_SHIFT 0 -#define MCDE_OLEDCONV4_GAMMA_RED_MASK 0x3FFF - - -#define MCDE_OLEDCONV5 (MCDE_BASE + 0x8A4) -#define MCDE_OLEDCONV5_OFF_RED_SHIFT 16 -#define MCDE_OLEDCONV5_OFF_RED_MASK 0x3FFF -#define MCDE_OLEDCONV5_GAMMA_BLUE_SHIFT 0 -#define MCDE_OLEDCONV5_GAMMA_BLUE_MASK 0x3FFF - - -#define MCDE_OLEDCONV6 (MCDE_BASE + 0x8A8) -#define MCDE_OLEDCONV6_OFF_BLUE_SHIFT 16 -#define MCDE_OLEDCONV6_OFF_BLUE_MASK 0x3FFF -#define MCDE_OLEDCONV6_OFF_GREEN_SHIFT 0 -#define MCDE_OLEDCONV6_OFF_GREEN_MASK 0x3FFF - - -#define MCDE_CRC (MCDE_BASE + 0xC00) -#define MCDE_CRC_CLAMPC1EN 0x80000000 -#define MCDE_CRC_SYNCCTRL_SHIFT 29 -#define MCDE_CRC_SYNCCTRL_MASK 0x3 -#define MCDE_CRC_RES2POL 0x10000000 -#define MCDE_CRC_RES1POL 0x08000000 -#define MCDE_CRC_RD2POL 0x04000000 -#define MCDE_CRC_RD1POL 0x02000000 -#define MCDE_CRC_WR2POL 0x01000000 -#define MCDE_CRC_WR1POL 0x00800000 -#define MCDE_CRC_CD2POL 0x00400000 -#define MCDE_CRC_CD1POL 0x00200000 -#define MCDE_CRC_CS2POL 0x00100000 -#define MCDE_CRC_CS1POL 0x00080000 -#define MCDE_CRC_RESEN 0x00040000 -#define MCDE_CRC_CS2EN 0x00020000 -#define MCDE_CRC_CS1EN 0x00010000 -#define MCDE_CRC_YUVCONVC1EN 0x00008000 -#define MCDE_CRC_CLKSEL_SHIFT 13 -#define MCDE_CRC_CLKSEL_MASK 0x3 -#define MCDE_CRC_INBAND2 0x00001000 -#define MCDE_CRC_INBAND1 0x00000800 -#define MCDE_CRC_SIZE2 0x00000400 -#define MCDE_CRC_SIZE1 0x00000200 -#define MCDE_CRC_SYCEN1 0x00000100 -#define MCDE_CRC_SYCEN0 0x00000080 -#define MCDE_CRC_SYNCSEL 0x00000040 -#define MCDE_CRC_WMLVL2 0x00000020 -#define MCDE_CRC_WMLVL1 0x00000010 -#define MCDE_CRC_C2EN 0x00000008 -#define MCDE_CRC_C1EN 0x00000004 -#define MCDE_CRC_POWEREN 0x00000002 -#define MCDE_CRC_FLOEN 0x00000001 - - -#define MCDE_PBCCRC (MCDE_BASE + 0xC04) -#define MCDE_PBCCRC_BPP_SHIFT 13 -#define MCDE_PBCCRC_BPP_MASK 0x7 -#define MCDE_PBCCRC_PDCTRL 0x00001000 -#define MCDE_PBCCRC_PDM_SHIFT 8 -#define MCDE_PBCCRC_PDM_MASK 0x3 -#define MCDE_PBCCRC_BSDM_SHIFT 4 -#define MCDE_PBCCRC_BSDM_MASK 0x7 -#define MCDE_PBCCRC_BSCM_SHIFT 0 -#define MCDE_PBCCRC_BSCM_MASK 0x7 - - -#define MCDE_PBCBMRC (MCDE_BASE + 0xC0C) -#define MCDE_PBCBCRC (MCDE_BASE + 0xC34) - - -#define MCDE_VSCRC (MCDE_BASE + 0xC5C) -#define MCDE_VSCRC_VSDBL_SHIFT 29 -#define MCDE_VSCRC_VSDBL_MASK 0x7 -#define MCDE_VSCRC_VSSEL 0x10000000 -#define MCDE_VSCRC_VSPOL 0x08000000 -#define MCDE_VSCRC_VSPDIV_SHIFT 24 -#define MCDE_VSCRC_VSPDIV_MASK 0x7 -#define MCDE_VSCRC_VSPMAX_SHIFT 12 -#define MCDE_VSCRC_VSPMAX_MASK 0xFFF -#define MCDE_VSCRC_VSPMIN_SHIFT 0 -#define MCDE_VSCRC_VSPMIN_MASK 0xFFF - - -#define MCDE_SCTRC (MCDE_BASE + 0xC64) -#define MCDE_SCTRC_TRDELC_SHIFT 16 -#define MCDE_SCTRC_TRDELC_MASK 0xFFF -#define MCDE_SCTRC_SYNCDELC1_SHIFT 8 -#define MCDE_SCTRC_SYNCDELC1_MASK 0xFF -#define MCDE_SCTRC_SYNCDELC0_SHIFT 0 -#define MCDE_SCTRC_SYNCDELC0_MASK 0xFF - - -#define MCDE_SCSRC (MCDE_BASE + 0xC68) -#define MCDE_SCSRC_VSTAC1 0x00000002 -#define MCDE_SCSRC_VSTAC0 0x00000001 - - -#define MCDE_BCNR (MCDE_BASE + 0xC6C) -#define MCDE_BCNR_BCN_SHIFT 0 -#define MCDE_BCNR_BCN_MASK 0xFF - - -#define MCDE_CSCDTR (MCDE_BASE + 0xC74) -#define MCDE_CSCDTR_CSCDDEACT_SHIFT 8 -#define MCDE_CSCDTR_CSCDDEACT_MASK 0xFF -#define MCDE_CSCDTR_CSCDACT_SHIFT 0 -#define MCDE_CSCDTR_CSCDACT_MASK 0xFF - - -#define MCDE_RDWRTR (MCDE_BASE + 0xC7C) -#define MCDE_RDWRTR_MOTINT 0x00010000 -#define MCDE_RDWRTR_RWDEACT_SHIFT 8 -#define MCDE_RDWRTR_RWDEACT_MASK 0xFF -#define MCDE_RDWRTR_RWACT_SHIFT 0 -#define MCDE_RDWRTR_RWACT_MASK 0xFF - - -#define MCDE_DOTR (MCDE_BASE + 0xC84) -#define MCDE_DOTR_DODEACT_SHIFT 8 -#define MCDE_DOTR_DODEACT_MASK 0xFF -#define MCDE_DOTR_DOACT_SHIFT 0 -#define MCDE_DOTR_DOACT_MASK 0xFF - - -#define MCDE_WCMDC (MCDE_BASE + 0xC8C) -#define MCDE_WDATADC (MCDE_BASE + 0xC94) - - -#define MCDE_RDATADC (MCDE_BASE + 0xC9C) -#define MCDE_RDATADC_STARTREAD 0x00010000 -#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_SHIFT 0 -#define MCDE_RDATADC_DATAREADFROMDISPLAYMODULE_MASK 0xFF - - -#define MCDE_STATC (MCDE_BASE + 0xCA4) -#define MCDE_STATC_FIFOCMDFULL1 0x00000200 -#define MCDE_STATC_FIFOCMDEMPTY1 0x00000100 -#define MCDE_STATC_FIFOFULL1 0x00000080 -#define MCDE_STATC_FIFOEMPTY1 0x00000040 -#define MCDE_STATC_STATBUSY1 0x00000020 -#define MCDE_STATC_FIFOCMDFULL0 0x00000010 -#define MCDE_STATC_FIFOCMDEMPTY0 0x00000008 -#define MCDE_STATC_FIFOFULL0 0x00000004 -#define MCDE_STATC_FIFOEMPTY0 0x00000002 -#define MCDE_STATC_STATBUSY0 0x00000001 - - -#define MCDE_CTRLC (MCDE_BASE + 0xCA8) -#define MCDE_CTRLC_FIFOWTRMRK_SHIFT 0 -#define MCDE_CTRLC_FIFOWTRMRK_MASK 0xFF - - -#define MCDE_DSICONF0 (MCDE_BASE + 0xE00) -#define MCDE_DSICONF0_PACKING_SHIFT 20 -#define MCDE_DSICONF0_PACKING_MASK 0x7 -#define MCDE_DSICONF0_DCSVID_NOTGEN 0x00040000 -#define MCDE_DSICONF0_BYTE_SWAP 0x00020000 -#define MCDE_DSICONF0_BIT_SWAP 0x00010000 -#define MCDE_DSICONF0_CMD8 0x00002000 -#define MCDE_DSICONF0_VID_MODE 0x00001000 -#define MCDE_DSICONF0_BLANKING_SHIFT 0 -#define MCDE_DSICONF0_BLANKING_MASK 0xFF - - -#define MCDE_DSIFRAME (MCDE_BASE + 0xE04) - -#define MCDE_DSIPKT (MCDE_BASE + 0xE08) -#define MCDE_DSIPKT_PACKET_SHIFT 0 -#define MCDE_DSIPKT_PACKET_MASK 0xFFFF - - -#define MCDE_DSISYNC (MCDE_BASE + 0xE0C) -#define MCDE_DSISYNC_SW_SHIFT 16 -#define MCDE_DSISYNC_SW_MASK 0xFFF -#define MCDE_DSISYNC_DMA_SHIFT 0 -#define MCDE_DSISYNC_DMA_MASK 0xFFF - - -#define MCDE_DSICMDW (MCDE_BASE + 0xE10) -#define MCDE_DSICMDW_CMDW_START_SHIFT 16 -#define MCDE_DSICMDW_CMDW_START_MASK 0xFFFF -#define MCDE_DSICMDW_CMDW_CONTINUE_SHIFT 0 -#define MCDE_DSICMDW_CMDW_CONTINUE_MASK 0xFFFF -#define MCDE_DSICMDW_CMD_START_MEMORY_WRITE 0x2C -#define MCDE_DSICMDW_CMD_CONTINUE_MEMORY_WRITE 0x3C - - -#define MCDE_DSIDELAY0 (MCDE_BASE + 0xE14) -#define MCDE_DSIDELAY0_INTPKTDEL_SHIFT 0 -#define MCDE_DSIDELAY0_INTPKTDEL_MASK 0xFFFF - - -#define MCDE_DSIDELAY1 (MCDE_BASE + 0xE18) -#define MCDE_DSIDELAY1_FRAMESTARTDEL_SHIFT 16 -#define MCDE_DSIDELAY1_FRAMESTARTDEL_MASK 0xFF -#define MCDE_DSIDELAY1_TEREQDEL_SHIFT 0 -#define MCDE_DSIDELAY1_TEREQDEL_MASK 0xFFF - - |