path: root/arch
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authorGirish K S <girish@avatar.(none)>2012-11-06 11:23:07 +0100
committerJohn Rigby <john.rigby@linaro.org>2012-12-06 13:51:47 -0700
commit26c1532583a31650c83a7b502fc06504076157c8 (patch)
tree5512827beab7de67abc3bdec708ea1ccae5f8a4a /arch
parented3ca71f89bc0216e1bab7df0b9d689eeca0a40d (diff)
The exynos dwmmc Ip has 2 stage divider. The first divider Register is in the vendor specific region of the dwmmc core (CLK_SEL), and second is part of the dwmmc generic registers (CLK_DIV). The goal of this patch is to maintain a 100MHz clock output before dividing it further by using the CLK_DIV. Depending on the card enumeration, it can be further divided by writing a correct divider in the dwmmc CLK_DIV register.
Signed-off-by: Girish K S <ks.giri@samsung.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions