|author||Girish K S <girish@avatar.(none)>||2012-11-06 11:23:07 +0100|
|committer||John Rigby <firstname.lastname@example.org>||2012-12-06 13:51:47 -0700|
The exynos dwmmc Ip has 2 stage divider. The first divider Register is in the vendor specific region of the dwmmc core (CLK_SEL), and second is part of the dwmmc generic registers (CLK_DIV). The goal of this patch is to maintain a 100MHz clock output before dividing it further by using the CLK_DIV. Depending on the card enumeration, it can be further divided by writing a correct divider in the dwmmc CLK_DIV register.
Signed-off-by: Girish K S <email@example.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions