diff options
author | Girish K S <girish@avatar.(none)> | 2012-10-06 14:24:36 +0900 |
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committer | John Rigby <john.rigby@linaro.org> | 2012-12-06 13:51:46 -0700 |
commit | ed3ca71f89bc0216e1bab7df0b9d689eeca0a40d (patch) | |
tree | 1a8197922ce5ae98fbd4fa09b8418cc48ac0e968 /arch | |
parent | 3380a7e653325adb9312f02ed4150c72131b6431 (diff) |
driver: dwmmc: Add the clock divider code for exynos dwmmc
The exynos dwmmc Ip has 2 stage divider. The first divider
Register is in the vendor specific region of the dwmmc core
(CLK_SEL), and second is part of the dwmmc generic registers
(CLK_DIV).
The goal of this patch is to maintain a 100MHz clock output
before dividing it further by using the CLK_DIV.
Depending on the card enumeration, it can be further divided
by writing a correct divider in the dwmmc CLK_DIV register.
Signed-off-by: Girish K S <ks.giri@samsung.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions