diff options
| author | Dietmar Eggemann <dietmar.eggemann@arm.com> | 2012-04-19 12:22:06 +0100 |
|---|---|---|
| committer | Dietmar Eggemann <dietmar.eggemann@arm.com> | 2012-05-23 12:44:34 +0100 |
| commit | 7dd470a6165adbec91a7536c0c4d2e303d45af24 (patch) | |
| tree | f0de31ba35565ed1f40f881587b02d6d50a2c081 /big-little | |
| parent | aa7cae38b7d7d3ec24b6ce80cbcd6ba3dfb6b96b (diff) | |
Migrate CSSELR from host to target.
CSSELR as a cache id register is trapped on the host cluster and the
corresponding target value is exported. This works fine for read accesses.
However for write accesses, i.e. the selection of the cache level and type,
the information is captured on the host but not migrated to the target.
This can cause problems if a cluster switch takes place between selecting a
cache level and performing the corresponding cache operation.
This patch makes sure that the CSSELR value selected on the host updates the
target cache geometry data structure as well as the physical CSSELR cp15
register.
The CSSELR cp15 register will be saved and restored as part of the architectural
state during the next switch.
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Diffstat (limited to 'big-little')
| -rw-r--r-- | big-little/virtualisor/virt_handle.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/big-little/virtualisor/virt_handle.c b/big-little/virtualisor/virt_handle.c index 56de995..092af67 100644 --- a/big-little/virtualisor/virt_handle.c +++ b/big-little/virtualisor/virt_handle.c @@ -213,10 +213,12 @@ void trap_cp15_mrc_mcr_handle(unsigned hsr, gp_regs * regs) case 0: switch (Op2) { case CSSELR: - if (write) + if (write) { target_cache_geometry [cpu_id].csselr = regs->r[Rt]; + write_csselr(regs->r[Rt]); + } else regs->r[Rt] = target_cache_geometry |