diff options
Diffstat (limited to 'test/CodeGen/ARM/GlobalISel')
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir | 35 | ||||
-rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir | 16 |
2 files changed, 45 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index d96463f00c7..939c851584c 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -1,6 +1,7 @@ # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_mla() #0 { ret void } + define void @test_mla_commutative() #0 { ret void } define void @test_mla_v5() #1 { ret void } define void @test_mls() #2 { ret void } @@ -45,6 +46,40 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- +name: test_mla_commutative +# CHECK-LABEL: name: test_mla_commutative +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } + - { id: 3, class: gprb } + - { id: 4, class: gprb } +body: | + bb.0: + liveins: %r0, %r1, %r2 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = COPY %r2 + ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 + ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 + ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 + + %3(s32) = G_MUL %0, %1 + %4(s32) = G_ADD %2, %3 + ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ + + %r0 = COPY %4(s32) + ; CHECK: %r0 = COPY [[VREGR]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- name: test_mla_v5 # CHECK-LABEL: name: test_mla_v5 legalized: true diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 0fdd485ba90..588ceaca2c4 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -970,9 +970,10 @@ registers: - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } + - { id: 4, class: gprb } body: | bb.0: - liveins: %r0, %r1 + liveins: %r0, %r1, %r2 %0(p0) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 @@ -980,14 +981,17 @@ body: | %1(p0) = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 - %2(s1) = G_TRUNC %1(p0) - ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]] + %2(s32) = COPY %r2 + ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2 - %3(p0) = G_SELECT %2(s1), %0, %1 - ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr + %3(s1) = G_TRUNC %2(s32) + ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]] + + %4(p0) = G_SELECT %3(s1), %0, %1 + ; CHECK: CMPri [[VREGD]], 0, 14, _, implicit-def %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr - %r0 = COPY %3(p0) + %r0 = COPY %4(p0) ; CHECK: %r0 = COPY [[RES]] BX_RET 14, _, implicit %r0 |