diff options
author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-02-26 15:23:42 +0000 |
---|---|---|
committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2018-02-26 15:23:42 +0000 |
commit | 454e6dcd0d78c02de79fa631b346a0757cb3e72f (patch) | |
tree | 4f8a6b04525cd652cc12befca9732947e244ad79 | |
parent | bf0378a7115e337f932bb80c811b6c1de16d8eaa (diff) |
[CodeGen] Don't omit any redundant information in -debug output
In r322867, we introduced IsStandalone when printing MIR in -debug
output. The default behaviour for that was:
1) If any of MBB, MI, or MO are -debug-printed separately, don't omit any
redundant information.
2) When -debug-printing a MF entirely, don't print any redundant
information.
3) When printing MIR, don't print any redundant information.
I'd like to change 2) to:
2) When -debug-printing a MF entirely, don't omit any redundant information.
Differential Revision: https://reviews.llvm.org/D43337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326094 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/MachineBasicBlock.cpp | 6 | ||||
-rw-r--r-- | lib/CodeGen/MachineFunction.cpp | 5 | ||||
-rw-r--r-- | test/CodeGen/AArch64/tailcall_misched_graph.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/ARM/Windows/dbzchk.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/Hexagon/post-inc-aa-metadata.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 2 |
6 files changed, 9 insertions, 10 deletions
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index cf58c33aa4e..8fef85ff82c 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -328,7 +328,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, bool HasLineAttributes = false; // Print the preds of this block according to the CFG. - if (!pred_empty()) { + if (!pred_empty() && IsStandalone) { if (Indexes) OS << '\t'; // Don't indent(2), align with previous line attributes. OS << "; predecessors: "; @@ -354,7 +354,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, << format("0x%08" PRIx32, getSuccProbability(I).getNumerator()) << ')'; } - if (!Probs.empty()) { + if (!Probs.empty() && IsStandalone) { // Print human readable probabilities as comments. OS << "; "; for (auto I = succ_begin(), E = succ_end(); I != E; ++I) { @@ -419,7 +419,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (IsInBundle) OS.indent(2) << "}\n"; - if (IrrLoopHeaderWeight) { + if (IrrLoopHeaderWeight && IsStandalone) { if (Indexes) OS << '\t'; OS.indent(2) << "; Irreducible loop header weight: " << IrrLoopHeaderWeight.getValue() << '\n'; diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 58ad3c96c34..e7a1502cc5a 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -522,9 +522,8 @@ void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const { MST.incorporateFunction(getFunction()); for (const auto &BB : *this) { OS << '\n'; - // If we print the whole function, don't print any verbose information, - // since that information is already present. - BB.print(OS, MST, Indexes, /*IsStandalone=*/false); + // If we print the whole function, print it at its most verbose level. + BB.print(OS, MST, Indexes, /*IsStandalone=*/true); } OS << "\n# End machine code for function " << getName() << ".\n\n"; diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll index b926594e450..8b7f9796e61 100644 --- a/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -29,7 +29,7 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3 ; CHECK: [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2 ; CHECK: STRXui %{{.*}}, %fixed-stack.0 -; CHECK: STRXui [[VRB]], %fixed-stack.1 +; CHECK: STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1 ; Make sure that there is an dependence edge between fi#-2 and fi#-4. ; Without this edge the scheduler would be free to move the store accross the load. diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll index 28932023ff0..324808cb0bf 100644 --- a/test/CodeGen/ARM/Windows/dbzchk.ll +++ b/test/CodeGen/ARM/Windows/dbzchk.ll @@ -119,7 +119,7 @@ attributes #0 = { optsize } ; CHECK-CFG-DAG: t2B %bb.3 ; CHECK-CFG-DAG: %bb.2 -; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0 +; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}{{[^,]*}}, 0 ; CHECK-CFG-DAG: t2Bcc %bb.5 ; CHECK-CFG-DAG: %bb.4 diff --git a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index 9357aa7d5a8..fd327cc53f9 100644 --- a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -3,7 +3,7 @@ ; Check that the generated post-increment load has TBAA information. ; CHECK-LABEL: Machine code for function fred: -; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa= +; CHECK: = V6_vL32b_pi %{{[0-9]+}}{{[^,]*}}, 64; mem:LD64[{{.*}}](tbaa= target triple = "hexagon" diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll index a64cf1199de..a247be7852c 100644 --- a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -42,7 +42,7 @@ bar: ; CHECK-LABEL: fn3 define signext i32 @fn3(i32 %a) { -; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def $cr0 +; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0 ; CHECK: BCC 76, killed [[CREG]] %1 = and i32 %a, 10 |