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authorEric Miao <eric.miao@linaro.org>2012-01-11 21:38:33 +0800
committerEric Miao <eric.miao@linaro.org>2012-01-11 21:38:33 +0800
commit3ffa6554d683f636518844887d5dc259b367e731 (patch)
treef174b6b0f9892726c9b5ecdbd66d724a3e2ddc54
parent143920b70301cd37462a2902f2965ef138ae90e6 (diff)
parent20401bffc83f4e9fd18fd6032fea22082099ce88 (diff)
downloadlinux-linaro-topic/lt-3.2-imx6-ugly.tar.gz
Merge branch 'lt-3.2-imx5' into topic/lt-3.2-imx6-uglytopic/lt-3.2-imx6-ugly
* lt-3.2-imx5: (124 commits) SAUCE: fix the missing header of <linux/module.h> SAUCE: fix the removal of mxc_register_device() SAUCE: mx53_loco: fix gpio_to_irq() being non-constant SAUCE: fix building errors after rebased to v3.2 LINARO: Add lt-mx5_defconfig ARM i.MX5: fix system_rev if not set by atag or DT ENGR00162701 mxc_vout: fix potential deadlock of fb_blank ENGR00162666 mxc_vout: v4l2 playback blocking issue ENGR00162665 ipuv3 fb: fix non-interleave format wrong color issue ENGR00162664 mxc_vout: modify pp bypass condition ENGR00162663 ipuv3 fb: add vertical flip support ENGR00162475 ipuv3 fb: fix camera preview failure ENGR00162360 mxc_vout: fix STREAMOFF and G_CROP issues ENGR00162358 ipuv3 fb: only check pos when fb is unblank ENGR00162354 ipuv3 device: correct kthread operation for split task SAUCE: mx53: add mxc_lcdif support SAUCE: add arm-pmu device SAUCE: remove unnecessary suspend/resume functions from mxc_spdif ENGR00162218 mxc_vout: put set position function before set var ENGR00162208 ipuv3 device: fix jitter issue of split mode ...
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-rw-r--r--include/linux/mfd/da9052/reg.h929
-rw-r--r--include/linux/mfd/da9052/rtc.h322
-rw-r--r--include/linux/mfd/da9052/tsi.h427
-rw-r--r--include/linux/mfd/da9052/tsi_calibrate.h47
-rw-r--r--include/linux/mfd/da9052/tsi_cfg.h132
-rw-r--r--include/linux/mfd/da9052/tsi_filter.h58
-rw-r--r--include/linux/mfd/da9052/wdt.h83
-rw-r--r--include/linux/mxc_srtc.h25
-rw-r--r--include/linux/mxc_v4l2.h27
-rw-r--r--include/linux/mxcfb.h161
-rw-r--r--include/linux/regulator/da9052-regulator.h15
-rw-r--r--include/linux/usb/fsl_xcvr.h58
-rw-r--r--sound/soc/codecs/Kconfig3
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/mxc_spdif.c1242
-rw-r--r--sound/soc/codecs/mxc_spdif.h164
-rw-r--r--sound/soc/codecs/sgtl5000.c32
-rw-r--r--sound/soc/imx/Kconfig24
-rw-r--r--sound/soc/imx/Makefile6
-rw-r--r--sound/soc/imx/imx-pcm-dma-mx2.c2
-rw-r--r--sound/soc/imx/imx-sgtl5000.c396
-rw-r--r--sound/soc/imx/imx-spdif-dai.c137
-rw-r--r--sound/soc/imx/imx-spdif.c144
-rw-r--r--sound/soc/imx/imx-ssi.c28
-rw-r--r--sound/soc/imx/imx-ssi.h6
297 files changed, 336274 insertions, 316 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b259c7c644e..0d9bfb600e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1700,6 +1700,7 @@ config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE
range 11 64 if ARCH_SHMOBILE
default "9" if SA1111
+ default "14" if ARCH_MX5
default "11"
help
The kernel memory allocator divides physically contiguous memory
diff --git a/arch/arm/configs/lt-mx5_defconfig b/arch/arm/configs/lt-mx5_defconfig
new file mode 100644
index 00000000000..cb080218092
--- /dev/null
+++ b/arch/arm/configs/lt-mx5_defconfig
@@ -0,0 +1,2323 @@
+#
+# Common config options automatically generated by splitconfig.pl
+#
+# CONFIG_ABX500_CORE is not set
+CONFIG_AC97_BUS=y
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ADFS_FS is not set
+CONFIG_AEABI=y
+# CONFIG_AFFS_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_AIO=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_AMIGA_PARTITION is not set
+CONFIG_ANON_INODES=y
+# CONFIG_APDS9802ALS is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_EXYNOS4 is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MX1 is not set
+# CONFIG_ARCH_MX2 is not set
+# CONFIG_ARCH_MX25 is not set
+# CONFIG_ARCH_MX3 is not set
+CONFIG_ARCH_MX5=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MXC_AUDMUX_V2=y
+CONFIG_ARCH_MXC_IOMUX_V3=y
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_REALVIEW is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_ZYNQ is not set
+CONFIG_ARM=y
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+# CONFIG_ARM_KPROBES_TEST is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_ARPD is not set
+# CONFIG_ASYNC_TX_DMA is not set
+CONFIG_AT76C50X_USB=m
+CONFIG_ATA=y
+CONFIG_ATAGS_PROC=y
+# CONFIG_ATALK is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_ATA_BMDMA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_ATA_SFF=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATM is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+CONFIG_AUDIT=y
+CONFIG_AUDIT_GENERIC=y
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AUXDISPLAY is not set
+CONFIG_AVERAGE=y
+# CONFIG_AX88796 is not set
+CONFIG_B43=m
+CONFIG_B43LEGACY=m
+CONFIG_B43LEGACY_DEBUG=y
+CONFIG_B43LEGACY_DMA=y
+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
+# CONFIG_B43LEGACY_DMA_MODE is not set
+CONFIG_B43LEGACY_HWRNG=y
+CONFIG_B43LEGACY_LEDS=y
+CONFIG_B43LEGACY_PIO=y
+# CONFIG_B43LEGACY_PIO_MODE is not set
+# CONFIG_B43_DEBUG is not set
+CONFIG_B43_HWRNG=y
+CONFIG_B43_LEDS=y
+CONFIG_B43_PHY_LP=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_PIO=y
+# CONFIG_B43_SDIO is not set
+CONFIG_B43_SSB=y
+# CONFIG_B44 is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_DA9052=m
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+CONFIG_BASE_FULL=y
+CONFIG_BASE_SMALL=0
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_DA9052 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_BCMA is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_BINARY_PRINTF=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_RBD is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_BLOCK=y
+# CONFIG_BMP085 is not set
+# CONFIG_BONDING is not set
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOT_PRINTK_DELAY is not set
+CONFIG_BOUNCE=y
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_BRIDGE is not set
+# CONFIG_BROADCOM_PHY is not set
+CONFIG_BROKEN_ON_SMP=y
+# CONFIG_BSD_DISKLABEL is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_BT=m
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
+CONFIG_BT_HCIBCM203X=m
+# CONFIG_BT_HCIBFUSB is not set
+CONFIG_BT_HCIBPA10X=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_L2CAP is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_SCO is not set
+CONFIG_BUG=y
+# CONFIG_C2PORT is not set
+# CONFIG_CAIF is not set
+# CONFIG_CAN is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CEPH_LIB is not set
+CONFIG_CFG80211=m
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_PERF is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CIFS is not set
+# CONFIG_CLEANCACHE is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_DEBUG=y
+CONFIG_CMDLINE=""
+# CONFIG_CODA_FS is not set
+CONFIG_COMPACTION=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_POLL=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+# CONFIG_CORDIC is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_IMX=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRAMFS=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+# CONFIG_CRC8 is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_COMPILE=""
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CCM is not set
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_DES is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+# CONFIG_CRYPTO_HMAC is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=m
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_PCOMP2=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_SERPENT=m
+# CONFIG_CRYPTO_SHA1 is not set
+CONFIG_CRYPTO_SHA256=m
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_DA9052_GPIO_ENABLE=y
+CONFIG_DA9052_WATCHDOG=m
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_DCB is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_USER=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DECNET is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_SECURITY="apparmor"
+CONFIG_DEFAULT_SECURITY_APPARMOR=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DM9000 is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+# CONFIG_DMATEST is not set
+# CONFIG_DMA_API_DEBUG is not set
+CONFIG_DMA_ENGINE=y
+# CONFIG_DM_CRYPT is not set
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DNET is not set
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_DRM is not set
+# CONFIG_DS1682 is not set
+CONFIG_DTC=y
+# CONFIG_DUMMY is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_DVB_CORE is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_WATCHDOG is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+CONFIG_DYNAMIC_FTRACE=y
+# CONFIG_ECONET is not set
+# CONFIG_ECRYPT_FS is not set
+CONFIG_EEPROM_93CX6=m
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_EFS_FS is not set
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_EPOLL=y
+# CONFIG_EQUALIZER is not set
+# CONFIG_ETHOC is not set
+CONFIG_EVENTFD=y
+CONFIG_EVENT_POWER_TRACING_DEPRECATED=y
+CONFIG_EVENT_TRACING=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXPERT=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_EZX_PCAP is not set
+# CONFIG_FANOTIFY is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_FAT_FS=y
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_FB=y
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_METRONOME is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_SII902X=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_TVOUT_TVE=y
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+CONFIG_FEC=y
+# CONFIG_FHANDLE is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FIQ=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FIRMWARE_IN_KERNEL=y
+# CONFIG_FIXED_PHY is not set
+CONFIG_FLATMEM=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FORCE_MAX_ZONEORDER=14
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_FPE_NWFPE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=1024
+CONFIG_FREEZER=y
+# CONFIG_FSCACHE is not set
+CONFIG_FSNOTIFY=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_FTGMAC100 is not set
+# CONFIG_FTL is not set
+# CONFIG_FTMAC100 is not set
+CONFIG_FTRACE=y
+CONFIG_FTRACE_MCOUNT_RECORD=y
+# CONFIG_FTRACE_STARTUP_TEST is not set
+CONFIG_FUNCTION_GRAPH_TRACER=y
+# CONFIG_FUNCTION_PROFILER is not set
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_FUSE_FS is not set
+CONFIG_FUTEX=y
+CONFIG_FW_LOADER=y
+# CONFIG_GAMEPORT is not set
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_GENERIC_ACL=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_TRACER=y
+# CONFIG_GFS2_FS is not set
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_ADP5588 is not set
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+CONFIG_GPIO_MXC=y
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_AOUT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_PWM=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_HAVE_SPARSE_IRQ=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+CONFIG_HID_A4TECH=y
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+# CONFIG_HID_EMS_FF is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_GYRATION=y
+# CONFIG_HID_HOLTEK is not set
+CONFIG_HID_KENSINGTON=y
+# CONFIG_HID_KEYTOUCH is not set
+CONFIG_HID_KYE=y
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_MULTITOUCH is not set
+CONFIG_HID_NTRIG=y
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PID is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_SONY=y
+# CONFIG_HID_SPEEDLINK is not set
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_TWINHAN=y
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+CONFIG_HID_ZEROPLUS=y
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_HMC6352 is not set
+# CONFIG_HOSTAP is not set
+CONFIG_HOTPLUG=y
+# CONFIG_HPFS_FS is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_HVC_DCC is not set
+CONFIG_HWMON=m
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_HWMON_VID is not set
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HZ=100
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_IDE is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IMA is not set
+CONFIG_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_AHCI=y
+CONFIG_IMX_HAVE_PLATFORM_FEC=y
+CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
+CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IIM=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_TVE=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
+CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y
+CONFIG_IMX_HAVE_PLATFORM_LDB=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_GPU=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
+CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y
+CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
+CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
+CONFIG_IMX_SDMA=y
+CONFIG_INET=y
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_DIAG=y
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INFTL is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_INPUT=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_CMA3000 is not set
+CONFIG_INPUT_DA9052_ONKEY=m
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_JOYDEV=y
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MMA8450=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_PCF8574 is not set
+CONFIG_INPUT_POLLDEV=m
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPX is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IP_SCTP is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IRDA is not set
+# CONFIG_IRQSOFF_TRACER is not set
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISDN is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+CONFIG_ISO9660_FS=m
+# CONFIG_IWM is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_JBD=y
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFS_FS is not set
+CONFIG_JOLIET=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_KEXEC=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+CONFIG_KGDB=y
+# CONFIG_KGDB_KDB is not set
+CONFIG_KGDB_SERIAL_CONSOLE=y
+# CONFIG_KGDB_TESTS is not set
+CONFIG_KPROBES=y
+CONFIG_KPROBES_SANITY_TEST=y
+CONFIG_KPROBE_EVENT=y
+CONFIG_KRETPROBES=y
+# CONFIG_KS8842 is not set
+CONFIG_KS8851=y
+CONFIG_KS8851_MLL=y
+# CONFIG_KSM is not set
+CONFIG_KTIME_SCALAR=y
+# CONFIG_L2TP is not set
+# CONFIG_LAPB is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_LBDAF=y
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_DA9052=m
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_REGISTER=y
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_LIBCRC32C=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LLC2 is not set
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKDEP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_LOCKD_V4=y
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_LOGFS is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIWII_FF is not set
+# CONFIG_LOGO is not set
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_LSM_MMAP_MIN_ADDR=0
+# CONFIG_LXT_PHY is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_HWSIM=m
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MACH_EUKREA_CPUIMX51=y
+CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD=y
+CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y
+CONFIG_MACH_MX51_3DS=y
+CONFIG_MACH_MX51_BABBAGE=y
+CONFIG_MACH_MX51_EFIKAMX=y
+CONFIG_MACH_MX51_EFIKASB=y
+CONFIG_MACH_MX53_ARD=y
+CONFIG_MACH_MX53_EVK=y
+CONFIG_MACH_MX53_LOCO=y
+CONFIG_MACH_MX53_SMD=y
+# CONFIG_MACVLAN is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_MD=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MEDIA_ATTACH is not set
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_ASIC3 is not set
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_STMPE is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MICREL_PHY is not set
+CONFIG_MIGRATION=y
+CONFIG_MII=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_BLOCK_MINORS=8
+# CONFIG_MMC_CLKGATE is not set
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_DW is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_TEST is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_VUB300 is not set
+CONFIG_MMU=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MSDOS_FS=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_MTD=y
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_AR7_PARTS is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_M25P80 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_MXC is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_OOPS=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MX51_EFIKA_COMMON=y
+CONFIG_MXC_AMD_GPU=m
+CONFIG_MXC_DEBUG_BOARD=y
+CONFIG_MXC_IIM=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_IPU_V3=y
+CONFIG_MXC_IPU_V3EX=y
+# CONFIG_MXC_IRQ_PRIOR is not set
+CONFIG_MXC_PWM=y
+CONFIG_MXC_TZIC=y
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NCP_FS is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEON=y
+CONFIG_NET=y
+# CONFIG_NETCONSOLE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_XTABLES is not set
+CONFIG_NETLABEL=y
+# CONFIG_NETPOLL is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NET_9P is not set
+# CONFIG_NET_DMA is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_NET_DSA is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_NET_IPIP is not set
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_NS is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_TCPPROBE is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_NFC is not set
+# CONFIG_NFSD is not set
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+# CONFIG_NFTL is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_NF_DEFRAG_IPV6 is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NL80211_TESTMODE is not set
+CONFIG_NLATTR=y
+CONFIG_NLS=y
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_NOP_TRACER=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+# CONFIG_NTFS_FS is not set
+# CONFIG_N_GSM is not set
+CONFIG_OABI_COMPAT=y
+# CONFIG_OC_ETM is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OLD_MCOUNT=y
+# CONFIG_OMFS_FS is not set
+CONFIG_OPROFILE=y
+# CONFIG_OSF_PARTITION is not set
+CONFIG_P54_COMMON=m
+CONFIG_P54_LEDS=y
+CONFIG_P54_SPI=m
+# CONFIG_P54_SPI_DEFAULT_EEPROM is not set
+CONFIG_P54_USB=m
+CONFIG_PACKET=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0x80000000
+# CONFIG_PANTHERLORD_FF is not set
+# CONFIG_PARPORT is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_IMX is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PCCARD is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+# CONFIG_PHONE is not set
+# CONFIG_PHONET is not set
+CONFIG_PHYLIB=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_PID_NS is not set
+# CONFIG_PLAT_SPEAR is not set
+CONFIG_PM=y
+# CONFIG_PMBUS is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_DA9052 is not set
+# CONFIG_PMIC_DA9053AA is not set
+CONFIG_PMIC_DA9053Bx=y
+CONFIG_PMIC_DIALOG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_SLEEP=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PPP is not set
+# CONFIG_PPS is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_PRINTK=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PROC_DEVICETREE is not set
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_VMCORE=y
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+CONFIG_PROFILING=y
+CONFIG_PROVE_LOCKING=y
+# CONFIG_PROVE_RCU is not set
+# CONFIG_PSTORE is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_R3964 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_RATIONAL=y
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_RCU_BOOST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_RDS is not set
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+# CONFIG_REALTEK_PHY is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_DA9052=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+CONFIG_REGULATOR_TPS65023=y
+CONFIG_REGULATOR_TPS6507X=y
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REISERFS_FS is not set
+CONFIG_RELAY=y
+# CONFIG_RESOURCE_COUNTERS is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_RFKILL is not set
+# CONFIG_RFKILL_REGULATOR is not set
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_ROOT_NFS=y
+CONFIG_RT2500USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00=m
+# CONFIG_RT2X00_DEBUG is not set
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_LEDS=y
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT73USB=m
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DEBUG is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DA9052=m
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+CONFIG_RTC_DRV_MXC_V2=y
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_MXC=y
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
+CONFIG_RTL8192CU=m
+CONFIG_RTL8192C_COMMON=m
+# CONFIG_RTL8192DE is not set
+CONFIG_RTL8192SE=m
+CONFIG_RTLWIFI=m
+CONFIG_RT_MUTEXES=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_SAMPLES is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_PMP is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_TRACER is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_WAIT_SCAN=m
+CONFIG_SDIO_UART=y
+CONFIG_SECCOMP=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_APPARMOR=y
+CONFIG_SECURITY_APPARMOR_BOOTPARAM_VALUE=1
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+# CONFIG_SECURITY_SELINUX_DISABLE is not set
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+CONFIG_SECURITY_SMACK=y
+# CONFIG_SECURITY_TOMOYO is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_DA9052 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_IFX6X60 is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_ALTERA_PS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SGI_PARTITION is not set
+CONFIG_SHMEM=y
+CONFIG_SIGNALFD=y
+CONFIG_SLAB=y
+CONFIG_SLABINFO=y
+# CONFIG_SLIP is not set
+# CONFIG_SLOB is not set
+# CONFIG_SLUB is not set
+# CONFIG_SMARTJOYPLUS_FF is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_SM_FTL is not set
+CONFIG_SND=y
+# CONFIG_SND_ALOOP is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_HWDEP=m
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_JACK=y
+CONFIG_SND_MIXER_OSS=m
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_MTPAV is not set
+CONFIG_SND_MXC_SOC_FIQ=y
+CONFIG_SND_MXC_SOC_MX2=y
+CONFIG_SND_MXC_SOC_SPDIF_DAI=y
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_CACHE_LZO=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_MXC_SPDIF=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SOC_TLV320AIC23=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_UA101 is not set
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SOC_CAMERA is not set
+CONFIG_SOC_IMX51=y
+CONFIG_SOC_IMX53=y
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_SPARSE_IRQ is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_SPI=y
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_XILINX is not set
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_SQUASHFS is not set
+CONFIG_SSB=m
+CONFIG_SSB_BLOCKIO=y
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB_SDIOHOST is not set
+CONFIG_SSB_SDIOHOST_POSSIBLE=y
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSFDC is not set
+CONFIG_STACKTRACE=y
+CONFIG_STACKTRACE_SUPPORT=y
+# CONFIG_STACK_TRACER is not set
+# CONFIG_STAGING is not set
+CONFIG_STANDALONE=y
+# CONFIG_STE10XP is not set
+# CONFIG_STMMAC_ETH is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUN_PARTITION is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWAP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_SYSFS=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TARGET_CORE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_ONESHOT=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_TIMERFD=y
+CONFIG_TIMER_STATS=y
+# CONFIG_TINY_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_TIPC is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_TI_ST is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+CONFIG_TOUCHSCREEN_ADS7846=m
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+CONFIG_TOUCHSCREEN_DA9052=m
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WM97XX is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+CONFIG_TRACEPOINTS=y
+CONFIG_TRACE_IRQFLAGS=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_TRACE_SINK is not set
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_TREE_PREEMPT_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_TUN is not set
+# CONFIG_TWL4030_CORE is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_UBIFS_FS_LZO=y
+# CONFIG_UBIFS_FS_XATTR is not set
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_UDF_FS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_UFS_FS is not set
+CONFIG_UID16=y
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_UNIX=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_USB=y
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ADUTUX is not set
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_ARC=m
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_AUDIO=m
+CONFIG_USB_BELKIN=y
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_CATC is not set
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_DEBUG=y
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DUMMY_HCD is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_EHCI_ARC=y
+CONFIG_USB_EHCI_ARC_OTG=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_EMI62 is not set
+CONFIG_USB_EPSON2888=y
+# CONFIG_USB_ET61X251 is not set
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_FSL_USB2 is not set
+# CONFIG_USB_FTDI_ELAN is not set
+CONFIG_USB_FUNCTIONFS=m
+# CONFIG_USB_FUNCTIONFS_ETH is not set
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+# CONFIG_USB_FUNCTIONFS_RNDIS is not set
+# CONFIG_USB_FUSB300 is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_GADGET_ARC=m
+CONFIG_USB_GADGET_DEBUG=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_USB_G_DBGP is not set
+CONFIG_USB_G_HID=m
+CONFIG_USB_G_MULTI=m
+# CONFIG_USB_G_MULTI_CDC is not set
+CONFIG_USB_G_MULTI_RNDIS=y
+CONFIG_USB_G_NCM=m
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_G_WEBCAM is not set
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_KC2190=y
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LIBUSUAL=y
+# CONFIG_USB_M66592 is not set
+CONFIG_USB_MASS_STORAGE=m
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_MON=y
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_NET2272 is not set
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_MCS7830 is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_RNDIS_WLAN=m
+# CONFIG_USB_NET_SMSC75XX is not set
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STATIC_IRAM is not set
+# CONFIG_USB_STKWEBCAM is not set
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+CONFIG_USB_TEST=y
+# CONFIG_USB_TMC is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_VL600 is not set
+CONFIG_USB_WDM=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_ZD1201=m
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USER_NS is not set
+CONFIG_USE_OF=y
+CONFIG_UTMI_MXC=y
+# CONFIG_UTS_NS is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_VETH is not set
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEOBUF_GEN=y
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_AK881X is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_CX2341X is not set
+# CONFIG_VIDEO_CX25840 is not set
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_M52790 is not set
+CONFIG_VIDEO_MEDIA=y
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+# CONFIG_VIDEO_NOON010PC30 is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_SAA6588 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_USBVISION is not set
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_VPX3220 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_VXFS_FS is not set
+CONFIG_W1=y
+CONFIG_W1_CON=y
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_GPIO is not set
+CONFIG_W1_MASTER_MXC=y
+# CONFIG_W1_SLAVE_BQ27000 is not set
+# CONFIG_W1_SLAVE_DS2408 is not set
+# CONFIG_W1_SLAVE_DS2423 is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2760 is not set
+# CONFIG_W1_SLAVE_DS2780 is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_WAN is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+# CONFIG_WIMAX is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_WL1251=m
+CONFIG_WL1251_SDIO=m
+CONFIG_WL1251_SPI=m
+CONFIG_WL12XX=m
+CONFIG_WL12XX_HT=y
+CONFIG_WL12XX_MENU=m
+CONFIG_WL12XX_PLATFORM_DATA=y
+CONFIG_WL12XX_SDIO=m
+CONFIG_WL12XX_SDIO_TEST=m
+CONFIG_WL12XX_SPI=m
+CONFIG_WLAN=y
+# CONFIG_X25 is not set
+CONFIG_XFRM=y
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_USER=y
+# CONFIG_XFS_FS is not set
+# CONFIG_XIP_KERNEL is not set
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_ZISOFS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index af0c212e3c7..da99de76ae0 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -31,6 +31,11 @@ config SOC_IMX51
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
select ARCH_MX51
+ select IMX_HAVE_PLATFORM_IMX_IIM
+ select IMX_HAVE_PLATFORM_IMX_IPUV3
+ select IMX_HAVE_PLATFORM_IMX_TVE
+ select IMX_HAVE_PLATFORM_IMX_VPU
+ select IMX_HAVE_PLATFORM_IMX_SPDIF
config SOC_IMX53
bool
@@ -38,7 +43,15 @@ config SOC_IMX53
select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
+ select ARCH_MXC_AUDMUX_V2
+ select ARCH_HAS_CPUFREQ
select ARCH_MX53
+ select IMX_HAVE_PLATFORM_IMX_IIM
+ select IMX_HAVE_PLATFORM_IMX_IPUV3
+ select IMX_HAVE_PLATFORM_IMX_TVE
+ select IMX_HAVE_PLATFORM_LDB
+ select IMX_HAVE_PLATFORM_IMX_VPU
+ select IMX_HAVE_PLATFORM_IMX_SPDIF
#comment "i.MX50 machines:"
@@ -221,10 +234,14 @@ config MACH_MX53_LOCO
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_SRTC
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_GPU
+ select IMX_HAVE_PLATFORM_MXC_PWM
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
select LEDS_GPIO_REGISTER
+ select IMX_HAVE_PLATFORM_IMX_SSI
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0fc60807fa2..5411507ce16 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,15 +3,19 @@
#
# Object file lists.
-obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
+obj-y := cpu.o mm.o devices.o ehci.o system.o bus_freq.o sdram_autogating.o \
+ suspend.o
+obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
+obj-$(CONFIG_SOC_IMX51) += clock.o
+obj-$(CONFIG_SOC_IMX53) += clock.o
obj-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
+obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o cpu_op-mx53.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o mx53_loco_pmic_da9053.o
obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
@@ -24,3 +28,4 @@ obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_USB_SUPPORT) += usb_h1.o usb_dr.o
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 237bdecd933..458fe9c9b64 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -23,10 +23,15 @@
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
+#include <linux/fsl_devices.h>
+#include <linux/ipu.h>
+#include <linux/pwm_backlight.h>
+#include <linux/memblock.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
+#include <mach/ipu-v3.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -34,8 +39,11 @@
#include "crm_regs.h"
#include "devices-imx53.h"
+#include "devices.h"
+#include "usb.h"
#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
+#define LOCO_HEADPHONE_DET IMX_GPIO_NR(2, 5)
#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
@@ -44,6 +52,14 @@
#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
+#define LOCO_DISP0_PWR IMX_GPIO_NR(3, 24)
+#define LOCO_DISP0_DET_INT IMX_GPIO_NR(3, 31)
+#define LOCO_DISP0_RESET IMX_GPIO_NR(5, 0)
+
+extern void __iomem *ccm_base;
+extern void __iomem *imx_otg_base;
+
+#define LOCO_USBH1_VBUS IMX_GPIO_NR(7, 8)
static iomux_v3_cfg_t mx53_loco_pads[] = {
/* FEC */
@@ -227,6 +243,52 @@ static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
.wp_type = ESDHC_WP_GPIO,
};
+static struct mxc_audio_platform_data loco_audio_data;
+
+static int loco_sgtl5000_init(void)
+{
+ struct clk *ssi_ext1;
+ int rate;
+
+ ssi_ext1 = clk_get(NULL, "ssi_ext1_clk");
+ if (IS_ERR(ssi_ext1))
+ return -1;
+
+ rate = clk_round_rate(ssi_ext1, 24000000);
+ if (rate < 8000000 || rate > 27000000) {
+ pr_err("Error: SGTL5000 mclk freq %d out of range!\n",
+ rate);
+ clk_put(ssi_ext1);
+ return -1;
+ }
+
+ loco_audio_data.sysclk = rate;
+ clk_set_rate(ssi_ext1, rate);
+ clk_enable(ssi_ext1);
+
+ return 0;
+}
+
+static struct imx_ssi_platform_data loco_ssi_pdata = {
+ .flags = IMX_SSI_DMA | IMX_SSI_SYN,
+};
+
+static struct mxc_audio_platform_data loco_audio_data = {
+ .ssi_num = 1,
+ .src_port = 2,
+ .ext_port = 5,
+ .init = loco_sgtl5000_init,
+ .hp_gpio = LOCO_HEADPHONE_DET,
+ .hp_active_low = 1,
+};
+
+static struct platform_device loco_audio_device = {
+ .name = "imx-sgtl5000",
+ .dev = {
+ .platform_data = &loco_audio_data,
+ }
+};
+
static inline void mx53_loco_fec_reset(void)
{
int ret;
@@ -246,10 +308,80 @@ static const struct fec_platform_data mx53_loco_fec_data __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
+static void sii902x_hdmi_reset(void)
+{
+ gpio_set_value(LOCO_DISP0_RESET, 0);
+ msleep(10);
+ gpio_set_value(LOCO_DISP0_RESET, 1);
+ msleep(10);
+}
+
+static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = {
+ .ipu_id = 0,
+ .disp_id = 0,
+ .reset = sii902x_hdmi_reset,
+};
+
static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
.bitrate = 100000,
};
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+ {
+ .type = "mma8450",
+ .addr = 0x1C,
+ },
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+ [0] = {
+ .type = "sgtl5000",
+ .addr = 0x0a,
+ },
+ [1] = {
+ .type = "sii902x",
+ .addr = 0x39,
+ .platform_data = &sii902x_hdmi_data,
+ },
+};
+
+static struct fsl_mxc_lcd_platform_data lcdif_data = {
+ .ipu_id = 0,
+ .disp_id = 0,
+ .default_ifmt = IPU_PIX_FMT_RGB565,
+};
+
+static struct fsl_mxc_ldb_platform_data ldb_data = {
+ .ipu_id = 0,
+ .disp_id = 0,
+ .ext_ref = 1,
+ .mode = LDB_SIN0,
+};
+
+static struct fsl_mxc_tve_platform_data tve_data = {
+ .dac_reg = "DA9052_LDO7",
+};
+
+static struct ipuv3_fb_platform_data loco_fb_data[] = {
+ { /*fb0*/
+ .disp_dev = "hdmi",
+ .interface_pix_fmt = IPU_PIX_FMT_RGB24,
+ .mode_str = "1920x1080M@60",
+ .default_bpp = 16,
+ .int_clk = false,
+ }, {
+ .disp_dev = "vga",
+ .interface_pix_fmt = IPU_PIX_FMT_GBR24,
+ .mode_str = "VGA-XGA",
+ .default_bpp = 16,
+ .int_clk = false,
+ },
+};
+
+static struct imx_ipuv3_platform_data ipu_data = {
+ .rev = 3,
+};
+
static const struct gpio_led mx53loco_leds[] __initconst = {
{
.name = "green",
@@ -275,12 +407,137 @@ static struct i2c_board_info mx53loco_i2c_devices[] = {
},
};
-static void __init mx53_loco_board_init(void)
+static struct mxc_gpu_platform_data gpu_data __initdata = {
+ .reserved_mem_size = SZ_64M,
+};
+
+static void mxc_iim_enable_fuse(void)
+{
+ u32 reg;
+ if (!ccm_base)
+ return;
+ /* enable fuse blown */
+ reg = readl(ccm_base + 0x64);
+ reg |= 0x10;
+ writel(reg, ccm_base + 0x64);
+}
+
+static void mxc_iim_disable_fuse(void)
+{
+ u32 reg;
+ if (!ccm_base)
+ return;
+ /* enable fuse blown */
+ reg = readl(ccm_base + 0x64);
+ reg &= ~0x10;
+ writel(reg, ccm_base + 0x64);
+}
+
+static struct mxc_iim_platform_data iim_data = {
+ .bank_start = MXC_IIM_MX53_BANK_START_ADDR,
+ .bank_end = MXC_IIM_MX53_BANK_END_ADDR,
+ .enable_fuse = mxc_iim_enable_fuse,
+ .disable_fuse = mxc_iim_disable_fuse,
+};
+
+static void loco_suspend_enter(void)
+{
+ /* da9053 suspend preparation */
+}
+
+static void loco_suspend_exit(void)
+{
+ /*clear the EMPGC0/1 bits */
+ __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+ __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+ /* da9053 resmue resore */
+}
+
+static struct mxc_pm_platform_data loco_pm_data = {
+ .suspend_enter = loco_suspend_enter,
+ .suspend_exit = loco_suspend_exit,
+};
+
+extern int __init mx53_loco_init_da9052(void);
+extern void da9053_power_off(void);
+
+static struct platform_pwm_backlight_data loco_pwm_backlight_data = {
+ .pwm_id = 1,
+ .max_brightness = 255,
+ .dft_brightness = 128,
+ .pwm_period_ns = 50000,
+};
+
+static void mx53_loco_usbh1_vbus(bool on)
+{
+ if (on)
+ gpio_set_value(LOCO_USBH1_VBUS, 1);
+ else
+ gpio_set_value(LOCO_USBH1_VBUS, 0);
+}
+
+static void __init mx53_loco_io_init(void)
{
int ret;
imx53_soc_init();
imx53_qsb_common_init();
+ mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
+ ARRAY_SIZE(mx53_loco_pads));
+
+ /* Sii902x HDMI controller */
+ ret = gpio_request(LOCO_DISP0_RESET, "disp0-reset");
+ if (ret) {
+ printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_RESET: %d\n", ret);
+ return;
+ }
+ gpio_direction_output(LOCO_DISP0_RESET, 0);
+
+ ret = gpio_request(LOCO_DISP0_DET_INT, "disp0-detect");
+ if (ret) {
+ printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_DET_INT: %d\n", ret);
+ return;
+ }
+ gpio_direction_input(LOCO_DISP0_DET_INT);
+
+ /* enable disp0 power */
+ ret = gpio_request(LOCO_DISP0_PWR, "disp0-power-en");
+ if (ret) {
+ printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_PWR: %d\n", ret);
+ return;
+ }
+ gpio_direction_output(LOCO_DISP0_PWR, 1);
+}
+
+static struct mxc_spdif_platform_data mxc_spdif_data = {
+ .spdif_tx = 1,
+ .spdif_rx = 0,
+ .spdif_clk_44100 = -1, /* No source for 44.1K */
+ /* Source from CCM spdif_clk (24M) for 48k and 32k
+ * It's not accurate: for 48Khz it is actually 46875Hz (2.3% off)
+ */
+ .spdif_clk_48000 = 1,
+ .spdif_clkid = 0,
+ .spdif_clk = NULL, /* spdif bus clk */
+};
+
+static void __init mx53_loco_board_init(void)
+{
+ int i, ret;
+
+ mx53_loco_io_init();
+
+ imx53_add_ipuv3(0, &ipu_data);
+
+ for (i = 0; i < ARRAY_SIZE(loco_fb_data); i++)
+ imx53_add_ipuv3fb(i, &loco_fb_data[i]);
+
+ imx53_add_vpu();
+ imx53_add_lcdif(&lcdif_data);
+ imx53_add_ldb(&ldb_data);
+ imx53_add_tve(&tve_data);
+ imx53_add_v4l2_output(0);
+
imx53_add_imx_uart(0, NULL);
mx53_loco_fec_reset();
imx53_add_fec(&mx53_loco_fec_data);
@@ -294,11 +551,62 @@ static void __init mx53_loco_board_init(void)
ARRAY_SIZE(mx53loco_i2c_devices));
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+ i2c_register_board_info(0, mxc_i2c0_board_info,
+ ARRAY_SIZE(mxc_i2c0_board_info));
+
+ mxc_i2c1_board_info[1].irq = gpio_to_irq(LOCO_DISP0_DET_INT);
+
+ i2c_register_board_info(1, mxc_i2c1_board_info,
+ ARRAY_SIZE(mxc_i2c1_board_info));
+
imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
+ platform_device_register(&loco_audio_device);
+ imx53_add_imx_ssi(1, &loco_ssi_pdata);
+ imx53_add_srtc();
imx_add_gpio_keys(&loco_button_data);
gpio_led_register_device(-1, &mx53loco_leds_data);
imx53_add_ahci_imx();
+ irq_set_irq_wake(gpio_to_irq(MX53_LOCO_POWER), 1);
+ imx53_add_iim(&iim_data);
+
+ i2c_register_board_info(0, mxc_i2c0_board_info,
+ ARRAY_SIZE(mxc_i2c0_board_info));
+
+ mxc_pm_device.dev.platform_data = &loco_pm_data;
+ platform_device_register(&mxc_pm_device);
+ mx53_loco_init_da9052();
+ pm_power_off = da9053_power_off;
+
+ imx53_add_mxc_pwm(1);
+ imx53_add_mxc_pwm_backlight(0, &loco_pwm_backlight_data);
+
+ mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
+ clk_put(mxc_spdif_data.spdif_core_clk);
+
+ imx53_add_spdif(&mxc_spdif_data);
+ imx53_add_spdif_dai();
+ imx53_add_spdif_audio_device();
+
+ /*GPU*/
+ if (mx53_revision() >= IMX_CHIP_REVISION_2_0)
+ gpu_data.z160_revision = 1;
+ else
+ gpu_data.z160_revision = 0;
+ imx53_add_mxc_gpu(&gpu_data);
+
+ /* USB */
+ imx_otg_base = MX53_IO_ADDRESS(MX53_OTG_BASE_ADDR);
+ /* usb host1 vbus */
+ ret = gpio_request(LOCO_USBH1_VBUS, "usbh1-vbus");
+ if (ret) {
+ printk(KERN_ERR"failed to get GPIO LOCO_USBH1_VBUS: %d\n", ret);
+ return;
+ }
+ gpio_direction_output(LOCO_USBH1_VBUS, 0);
+ mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus);
+ mx5_usbh1_init();
+ mx5_usb_dr_init();
}
static void __init mx53_loco_timer_init(void)
@@ -310,6 +618,18 @@ static struct sys_timer mx53_loco_timer = {
.init = mx53_loco_timer_init,
};
+static void __init mx53_loco_reserve(void)
+{
+ phys_addr_t phys;
+
+ if (gpu_data.reserved_mem_size) {
+ phys = memblock_alloc(gpu_data.reserved_mem_size, SZ_4K);
+ memblock_free(phys, gpu_data.reserved_mem_size);
+ memblock_remove(phys, gpu_data.reserved_mem_size);
+ gpu_data.reserved_mem_base = phys;
+ }
+}
+
MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
@@ -317,4 +637,5 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
.handle_irq = imx53_handle_irq,
.timer = &mx53_loco_timer,
.init_machine = mx53_loco_board_init,
+ .reserve = mx53_loco_reserve,
MACHINE_END
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c
new file mode 100644
index 00000000000..c2cbbd02d52
--- /dev/null
+++ b/arch/arm/mach-mx5/bus_freq.c
@@ -0,0 +1,1065 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file bus_freq.c
+ *
+ * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module
+ * and DVFS CORE module.
+ *
+ * The APIs are for setting bus frequency to low or high.
+ *
+ * @ingroup PM
+ */
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/mutex.h>
+#include <mach/iram.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/sdram_autogating.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <asm/cacheflush.h>
+#include <asm/tlb.h>
+#include "crm_regs.h"
+
+#define LP_LOW_VOLTAGE 1050000
+#define LP_NORMAL_VOLTAGE 1250000
+#define LP_APM_CLK 24000000
+#define NAND_LP_APM_CLK 12000000
+#define AXI_A_NORMAL_CLK 166250000
+#define AXI_A_CLK_NORMAL_DIV 4
+#define AXI_B_CLK_NORMAL_DIV 5
+#define AHB_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV
+#define EMI_SLOW_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV
+#define NFC_CLK_NORMAL_DIV 4
+#define SPIN_DELAY 1000000 /* in nanoseconds */
+#define DDR_TYPE_DDR3 0x0
+#define DDR_TYPE_DDR2 0x1
+
+DEFINE_SPINLOCK(ddr_freq_lock);
+
+unsigned long lp_normal_rate;
+unsigned long lp_med_rate;
+unsigned long ddr_normal_rate;
+unsigned long ddr_med_rate;
+unsigned long ddr_low_rate;
+static int cur_ddr_rate;
+static unsigned char mx53_ddr_type;
+
+static struct clk *ddr_clk;
+static struct clk *pll1_sw_clk;
+static struct clk *pll1;
+static struct clk *pll2;
+static struct clk *pll3;
+static struct clk *pll4;
+static struct clk *main_bus_clk;
+static struct clk *axi_a_clk;
+static struct clk *axi_b_clk;
+static struct clk *cpu_clk;
+static struct clk *ddr_hf_clk;
+static struct clk *ahb_clk;
+static struct clk *ddr_clk;
+static struct clk *periph_apm_clk;
+static struct clk *lp_apm;
+static struct clk *gpc_dvfs_clk;
+static struct clk *emi_garb_clk;
+static void __iomem *pll1_base;
+static void __iomem *pll4_base;
+
+struct regulator *pll_regulator;
+
+struct regulator *lp_regulator;
+int low_bus_freq_mode;
+int high_bus_freq_mode;
+int med_bus_freq_mode;
+
+int bus_freq_scaling_initialized;
+char *gp_reg_id;
+char *lp_reg_id;
+
+static struct cpu_op *cpu_op_tbl;
+static struct device *busfreq_dev;
+static int busfreq_suspended;
+static int cpu_podf;
+/* True if bus_frequency is scaled not using DVFS-PER */
+int bus_freq_scaling_is_active;
+
+int cpu_op_nr;
+int lp_high_freq;
+int lp_med_freq;
+
+static int lp_voltage;
+struct workqueue_struct *voltage_wq;
+static struct work_struct voltage_change_handler;
+struct completion voltage_change_cmpl;
+
+void enter_lpapm_mode_mx50(void);
+void enter_lpapm_mode_mx51(void);
+void enter_lpapm_mode_mx53(void);
+void exit_lpapm_mode_mx50(int high_bus_freq);
+void exit_lpapm_mode_mx51(void);
+void exit_lpapm_mode_mx53(void);
+int low_freq_bus_used(void);
+void set_ddr_freq(int ddr_freq);
+
+extern int dvfs_core_is_active;
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void __iomem *ccm_base;
+extern void __iomem *databahn_base;
+extern int update_ddr_freq(int ddr_rate);
+extern unsigned int mx50_ddr_type;
+
+
+struct dvfs_wp dvfs_core_setpoint[] = {
+ {33, 8, 33, 10, 10, 0x08},
+ {26, 0, 33, 20, 10, 0x08},
+ {28, 8, 33, 20, 30, 0x08},
+ {29, 0, 33, 20, 10, 0x08},};
+
+static DEFINE_SPINLOCK(voltage_lock);
+struct mutex bus_freq_mutex;
+
+struct timeval start_time;
+struct timeval end_time;
+
+static void voltage_work_handler(struct work_struct *work)
+{
+ if (lp_regulator != NULL) {
+ u32 ret = 0;
+ ret = regulator_set_voltage(lp_regulator,
+ lp_voltage, lp_voltage);
+ udelay(400);
+ if (ret < 0) {
+ printk(KERN_ERR "COULD NOT SET LP VOLTAGE!!!!!!\n");
+ return;
+ }
+ }
+ complete_all(&voltage_change_cmpl);
+}
+
+int set_low_bus_freq(void)
+{
+ if (busfreq_suspended)
+ return 0;
+ if (bus_freq_scaling_initialized) {
+ /* can not enter low bus freq, when cpu is in higher freq
+ * or only have one working point */
+ if ((clk_get_rate(cpu_clk) >
+ cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+ || (cpu_op_nr == 1)) {
+ return 0;
+ }
+
+ mutex_lock(&bus_freq_mutex);
+
+ stop_dvfs_per();
+
+ stop_sdram_autogating();
+
+ if (cpu_is_mx50())
+ enter_lpapm_mode_mx50();
+ else if (cpu_is_mx51())
+ enter_lpapm_mode_mx51();
+ else
+ enter_lpapm_mode_mx53();
+ mutex_unlock(&bus_freq_mutex);
+ }
+ return 0;
+}
+
+void enter_lpapm_mode_mx50()
+{
+ u32 reg;
+ unsigned long flags;
+ spin_lock_irqsave(&ddr_freq_lock, flags);
+
+ set_ddr_freq(LP_APM_CLK);
+ /* Set the parent of main_bus_clk to be PLL3 */
+ clk_set_parent(main_bus_clk, pll3);
+
+ /* Set the AHB dividers to be 2.
+ * Set the dividers so that clock rates
+ * are not greater than current clock rate.
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F)
+ udelay(10);
+
+ low_bus_freq_mode = 1;
+ high_bus_freq_mode = 0;
+ med_bus_freq_mode = 0;
+
+ /* Set the source of main_bus_clk to be lp-apm. */
+ clk_set_parent(main_bus_clk, lp_apm);
+
+ /* Set the AHB dividers to be 1. */
+ /* Set the dividers to be 1, so the clock rates
+ * are at 24Mhz
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F)
+ udelay(10);
+
+ spin_unlock_irqrestore(&ddr_freq_lock, flags);
+
+ spin_lock_irqsave(&voltage_lock, flags);
+ lp_voltage = LP_LOW_VOLTAGE;
+ INIT_COMPLETION(voltage_change_cmpl);
+ queue_work(voltage_wq, &voltage_change_handler);
+ spin_unlock_irqrestore(&voltage_lock, flags);
+
+ if (clk_get_usecount(pll1_sw_clk) == 1) {
+ /* Relock PLL1 to 160MHz. */
+ clk_set_parent(pll1_sw_clk, pll2);
+ /* Set the divider to ARM_PODF to 3. */
+ __raw_writel(0x02, MXC_CCM_CACRR);
+
+ clk_set_rate(pll1, 160000000);
+ clk_set_parent(pll1_sw_clk, pll1);
+ /* Set the divider to ARM_PODF to 1. */
+ __raw_writel(0x0, MXC_CCM_CACRR);
+ }
+
+ udelay(100);
+}
+
+void enter_lpapm_mode_mx51()
+{
+ u32 reg;
+ /* Set PLL3 to 133Mhz if no-one is using it. */
+ if (clk_get_usecount(pll3) == 0) {
+ u32 pll3_rate = clk_get_rate(pll3);
+
+ clk_enable(pll3);
+ clk_set_rate(pll3, clk_round_rate(pll3, 133000000));
+
+ /*Change the DDR freq to 133Mhz. */
+ clk_set_rate(ddr_hf_clk,
+ clk_round_rate(ddr_hf_clk, ddr_low_rate));
+
+ /* Set the parent of Periph_apm_clk to be PLL3 */
+ clk_set_parent(periph_apm_clk, pll3);
+ clk_set_parent(main_bus_clk, periph_apm_clk);
+
+ /* Set the dividers to be 1, so the clock rates
+ * are at 133MHz.
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MXC_CCM_CBCDR_EMI_PODF_MASK
+ | MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+ | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ clk_enable(emi_garb_clk);
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+ udelay(10);
+ clk_disable(emi_garb_clk);
+
+ low_bus_freq_mode = 1;
+ high_bus_freq_mode = 0;
+ med_bus_freq_mode = 0;
+
+ /* Set the source of Periph_APM_Clock to be lp-apm. */
+ clk_set_parent(periph_apm_clk, lp_apm);
+
+ /* Set PLL3 back to original rate. */
+ clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate));
+ clk_disable(pll3);
+ }
+}
+
+void enter_lpapm_mode_mx53()
+{
+ u32 reg;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ /* TBD: Reduce DDR frequency for DDR2 */
+ /* if (mx53_ddr_type == DDR_TYPE_DDR2) {
+ } */
+
+ /* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu */
+ /* Change the source of pll1_sw_clk to be the step_clk */
+ reg = __raw_readl(MXC_CCM_CCSR);
+ reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+ __raw_writel(reg, MXC_CCM_CCSR);
+
+ cpu_podf = __raw_readl(MXC_CCM_CACRR);
+ reg = __raw_readl(MXC_CCM_CDHIPR);
+ if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0)
+ __raw_writel(0x2, MXC_CCM_CACRR);
+ else
+ printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
+ clk_set_parent(pll1_sw_clk, pll2);
+
+ /* ahb = pll2/8, axi_b = pll2/8, axi_a = pll2/1*/
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) &
+ (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
+ MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
+ MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec
+ > SPIN_DELAY)
+ panic("low bus freq set rate error\n");
+ }
+
+ /* keep this infront of propagating */
+ low_bus_freq_mode = 1;
+ high_bus_freq_mode = 0;
+ med_bus_freq_mode = 0;
+
+ if (clk_get_usecount(pll1) == 0) {
+ reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ reg &= ~MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+ }
+ if (clk_get_usecount(pll4) == 0) {
+ reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL);
+ reg &= ~MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pll4_base + MXC_PLL_DP_CTL);
+ }
+}
+
+int set_high_bus_freq(int high_bus_freq)
+{
+ u32 reg;
+ if (bus_freq_scaling_initialized) {
+ mutex_lock(&bus_freq_mutex);
+ /*
+ * If the CPU freq is 800MHz, set the bus to the high
+ * setpoint (133MHz) and DDR to 200MHz.
+ */
+ if ((clk_get_rate(cpu_clk) >
+ cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+ || lp_high_freq)
+ high_bus_freq = 1;
+
+ stop_sdram_autogating();
+
+ if (low_bus_freq_mode) {
+ /* Relock PLL3 to 133MHz */
+ if (cpu_is_mx50())
+ exit_lpapm_mode_mx50(high_bus_freq);
+ else if (cpu_is_mx51())
+ exit_lpapm_mode_mx51();
+ else
+ exit_lpapm_mode_mx53();
+ start_dvfs_per();
+ }
+ if (bus_freq_scaling_is_active) {
+ if (!high_bus_freq_mode && high_bus_freq) {
+ if (cpu_is_mx50()) {
+ if (med_bus_freq_mode) {
+ /* Increase SYS_CLK */
+ reg = __raw_readl(MXC_CCM_CLK_SYS);
+ reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK;
+ reg |= 4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CLK_SYS);
+
+ /* Set the dividers to the default dividers */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+ udelay(10);
+ }
+ } else {
+ clk_set_rate(ahb_clk,
+ clk_round_rate(ahb_clk,
+ lp_normal_rate));
+ clk_set_rate(ddr_hf_clk,
+ clk_round_rate(ddr_hf_clk,
+ ddr_normal_rate));
+ }
+ /* Set to the high setpoint. */
+ high_bus_freq_mode = 1;
+ low_bus_freq_mode = 0;
+ med_bus_freq_mode = 0;
+ } else if (!med_bus_freq_mode && !high_bus_freq) {
+ if (cpu_is_mx50()) {
+ /* Set the dividers to the medium setpoint dividers */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ |3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ |5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+ udelay(10);
+ /* Reduce SYS_CLK */
+ reg = __raw_readl(MXC_CCM_CLK_SYS);
+ reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK;
+ reg |= 8 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CLK_SYS);
+ } else {
+ if (cpu_is_mx51())
+ clk_set_rate(ddr_hf_clk,
+ clk_round_rate(
+ ddr_hf_clk,
+ ddr_low_rate));
+ clk_set_rate(ahb_clk,
+ clk_round_rate(
+ ahb_clk, lp_med_rate));
+ }
+ /* Set to the medium setpoint. */
+ high_bus_freq_mode = 0;
+ low_bus_freq_mode = 0;
+ med_bus_freq_mode = 1;
+ }
+ if (cpu_is_mx50()) {
+ if (med_bus_freq_mode &&
+ (cur_ddr_rate != ddr_med_rate))
+ set_ddr_freq(ddr_med_rate);
+ if (high_bus_freq_mode &&
+ (cur_ddr_rate != ddr_normal_rate))
+ set_ddr_freq(ddr_normal_rate);
+ }
+ }
+ start_sdram_autogating();
+ mutex_unlock(&bus_freq_mutex);
+ }
+ return 0;
+}
+
+void exit_lpapm_mode_mx50(int high_bus_freq)
+{
+ u32 reg;
+ unsigned long flags;
+
+ if (clk_get_usecount(pll1_sw_clk) == 1) {
+ /* Relock PLL1 to 800MHz. */
+ clk_set_parent(pll1_sw_clk, pll2);
+ /* Set the divider to ARM_PODF to 3, cpu is at 160MHz. */
+ __raw_writel(0x02, MXC_CCM_CACRR);
+
+ clk_set_rate(pll1, 800000000);
+ clk_set_parent(pll1_sw_clk, pll1);
+ /* Set the divider to ARM_PODF to 5. */
+ __raw_writel(0x4, MXC_CCM_CACRR);
+ }
+
+ if (!completion_done(&voltage_change_cmpl))
+ wait_for_completion_interruptible(&voltage_change_cmpl);
+ spin_lock_irqsave(&voltage_lock, flags);
+ if (lp_voltage != LP_NORMAL_VOLTAGE) {
+ INIT_COMPLETION(voltage_change_cmpl);
+ lp_voltage = LP_NORMAL_VOLTAGE;
+ if (!queue_work(voltage_wq, &voltage_change_handler))
+ printk(KERN_ERR "WORK_NOT_ADDED\n");
+ spin_unlock_irqrestore(&voltage_lock, flags);
+ wait_for_completion_interruptible(&voltage_change_cmpl);
+ } else {
+ spin_unlock_irqrestore(&voltage_lock, flags);
+ if (!completion_done(&voltage_change_cmpl))
+ wait_for_completion_interruptible(&voltage_change_cmpl);
+ }
+
+ spin_lock_irqsave(&ddr_freq_lock, flags);
+ if (!low_bus_freq_mode) {
+ spin_unlock_irqrestore(&ddr_freq_lock, flags);
+ return;
+ }
+
+ /* Temporarily set the dividers when the source is PLL3.
+ * No clock rate is above 133MHz.
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ |1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+ udelay(10);
+
+ clk_set_parent(main_bus_clk, pll3);
+
+ if (bus_freq_scaling_is_active && !high_bus_freq) {
+ /* Set the dividers to the medium setpoint dividers */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ |3 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ |5 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+ udelay(10);
+
+ /*Set the main_bus_clk parent to be PLL2. */
+ clk_set_parent(main_bus_clk, pll2);
+
+ /* Set to the medium setpoint. */
+ high_bus_freq_mode = 0;
+ low_bus_freq_mode = 0;
+ med_bus_freq_mode = 1;
+ set_ddr_freq(ddr_med_rate);
+ } else {
+ /* Set the dividers to the default dividers */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MX50_CCM_CBCDR_WEIM_PODF_MASK);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0xF)
+ udelay(10);
+
+ /*Set the main_bus_clk parent to be PLL2. */
+ clk_set_parent(main_bus_clk, pll2);
+
+ /* Set to the high setpoint. */
+ high_bus_freq_mode = 1;
+ low_bus_freq_mode = 0;
+ med_bus_freq_mode = 0;
+ set_ddr_freq(ddr_normal_rate);
+ }
+
+ spin_unlock_irqrestore(&ddr_freq_lock, flags);
+
+ udelay(100);
+}
+
+void exit_lpapm_mode_mx51()
+{
+ u32 reg;
+
+ /* Temporarily Set the dividers is PLL3.
+ * No clock rate is above 133MHz.
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MXC_CCM_CBCDR_EMI_PODF_MASK
+ | MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ reg |= (1 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+ | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ clk_enable(emi_garb_clk);
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+ udelay(10);
+ clk_disable(emi_garb_clk);
+
+ clk_set_parent(periph_apm_clk, pll3);
+
+ /* Set the dividers to the default dividers */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK
+ | MXC_CCM_CBCDR_EMI_PODF_MASK
+ | MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET
+ | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET
+ | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ clk_enable(emi_garb_clk);
+ while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F)
+ udelay(10);
+
+ low_bus_freq_mode = 0;
+ high_bus_freq_mode = 1;
+ clk_disable(emi_garb_clk);
+
+ /*Set the main_bus_clk parent to be PLL2. */
+ clk_set_parent(main_bus_clk, pll2);
+
+ /*Change the DDR freq to 200MHz*/
+ clk_set_rate(ddr_hf_clk,
+ clk_round_rate(ddr_hf_clk, ddr_normal_rate));
+}
+
+void exit_lpapm_mode_mx53()
+{
+ u32 reg;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+
+ /* move cpu clk to pll1 */
+ reg = __raw_readl(MXC_CCM_CDHIPR);
+ if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) != 0)
+ __raw_writel(cpu_podf & 0x7,
+ MXC_CCM_CACRR);
+ else
+ printk(KERN_DEBUG
+ "ARM_PODF still in busy!!!!\n");
+
+ clk_set_parent(pll1_sw_clk, pll1);
+
+
+ /* ahb = 400/3, axi_b = 400/2, axi_a = 400*/
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK
+ | MXC_CCM_CBCDR_AXI_B_PODF_MASK
+ | MXC_CCM_CBCDR_AHB_PODF_MASK);
+ reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET
+ | 1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET
+ | 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) &
+ (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY |
+ MXC_CCM_CDHIPR_AXI_B_PODF_BUSY |
+ MXC_CCM_CDHIPR_AHB_PODF_BUSY)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec
+ - nstimeofday.tv_nsec
+ > SPIN_DELAY)
+ panic("bus freq error\n");
+ }
+
+ /* keep this infront of propagating */
+ low_bus_freq_mode = 0;
+ high_bus_freq_mode = 1;
+ med_bus_freq_mode = 0;
+
+ /* TBD: Restore DDR frequency for DDR2 */
+ /* if (mx53_ddr_type == DDR_TYPE_DDR2) {
+ } */
+}
+
+void set_ddr_freq(int ddr_rate)
+{
+ unsigned long flags;
+ unsigned int ret = 0;
+
+ spin_lock_irqsave(&ddr_freq_lock, flags);
+
+ if (cpu_is_mx50())
+ ret = update_ddr_freq(ddr_rate);
+
+ spin_unlock_irqrestore(&ddr_freq_lock, flags);
+ if (!ret)
+ cur_ddr_rate = ddr_rate;
+ udelay(100);
+}
+
+int low_freq_bus_used(void)
+{
+ if ((lp_high_freq == 0)
+ && (lp_med_freq == 0))
+ return 1;
+ else
+ return 0;
+}
+
+void setup_pll(void)
+{
+}
+
+static ssize_t bus_freq_scaling_enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (bus_freq_scaling_is_active)
+ return sprintf(buf, "Bus frequency scaling is enabled\n");
+ else
+ return sprintf(buf, "Bus frequency scaling is disabled\n");
+}
+
+static ssize_t bus_freq_scaling_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ u32 reg;
+
+ if (strncmp(buf, "1", 1) == 0) {
+ if (dvfs_per_active()) {
+ printk(KERN_INFO "bus frequency scaling cannot be\
+ enabled when DVFS-PER is active\n");
+ return size;
+ }
+ if (!cpu_is_mx50()) {
+ /* Initialize DVFS-PODF to 0. */
+ reg = __raw_readl(MXC_CCM_CDCR);
+ reg &= ~MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK;
+ __raw_writel(reg, MXC_CCM_CDCR);
+ clk_set_parent(main_bus_clk, pll2);
+ }
+ bus_freq_scaling_is_active = 1;
+ set_high_bus_freq(0);
+ } else if (strncmp(buf, "0", 1) == 0) {
+ if (bus_freq_scaling_is_active)
+ set_high_bus_freq(1);
+ bus_freq_scaling_is_active = 0;
+ }
+
+ return size;
+}
+
+static int busfreq_suspend(struct platform_device *pdev, pm_message_t message)
+{
+ if (low_bus_freq_mode)
+ set_high_bus_freq(1);
+ busfreq_suspended = 1;
+ return 0;
+}
+
+static int busfreq_resume(struct platform_device *pdev)
+{
+ busfreq_suspended = 0;
+ return 0;
+}
+
+static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
+ bus_freq_scaling_enable_store);
+
+/*!
+ * This is the probe routine for the bus frequency driver.
+ *
+ * @param pdev The platform device structure
+ *
+ * @return The function returns 0 on success
+ *
+ */
+static int __devinit busfreq_probe(struct platform_device *pdev)
+{
+ int err = 0;
+ unsigned long pll2_rate, pll1_rate;
+ struct mxc_bus_freq_platform_data *p_bus_freq_data;
+
+ p_bus_freq_data = pdev->dev.platform_data;
+ gp_reg_id = p_bus_freq_data->gp_reg_id;
+ lp_reg_id = p_bus_freq_data->lp_reg_id;
+
+ if (cpu_is_mx51()) {
+ pll1_base = MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR);
+ } else if (cpu_is_mx53()) {
+ pll1_base = MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR);
+ pll4_base = MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR);
+ } else if (cpu_is_mx50()) {
+ pll1_base = MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR);
+ }
+
+ busfreq_dev = &pdev->dev;
+
+ main_bus_clk = clk_get(NULL, "main_bus_clk");
+ if (IS_ERR(main_bus_clk)) {
+ printk(KERN_DEBUG "%s: failed to get main_bus_clk\n",
+ __func__);
+ return PTR_ERR(main_bus_clk);
+ }
+
+ pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
+ if (IS_ERR(pll1_sw_clk)) {
+ printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", __func__);
+ return PTR_ERR(pll1_sw_clk);
+ }
+
+ pll1 = clk_get(NULL, "pll1_main_clk");
+ if (IS_ERR(pll1)) {
+ printk(KERN_DEBUG "%s: failed to get pll1\n", __func__);
+ return PTR_ERR(pll1);
+ }
+
+ pll2 = clk_get(NULL, "pll2");
+ if (IS_ERR(pll2)) {
+ printk(KERN_DEBUG "%s: failed to get pll2\n", __func__);
+ return PTR_ERR(pll2);
+ }
+
+ pll3 = clk_get(NULL, "pll3");
+ if (IS_ERR(pll3)) {
+ printk(KERN_DEBUG "%s: failed to get pll3\n", __func__);
+ return PTR_ERR(pll3);
+ }
+
+ if (cpu_is_mx53()) {
+ pll4 = clk_get(NULL, "pll4");
+ if (IS_ERR(pll4)) {
+ printk(KERN_DEBUG "%s: failed to get pll4\n", __func__);
+ return PTR_ERR(pll4);
+ }
+ }
+
+ axi_a_clk = clk_get(NULL, "axi_a_clk");
+ if (IS_ERR(axi_a_clk)) {
+ printk(KERN_DEBUG "%s: failed to get axi_a_clk\n",
+ __func__);
+ return PTR_ERR(axi_a_clk);
+ }
+
+ axi_b_clk = clk_get(NULL, "axi_b_clk");
+ if (IS_ERR(axi_b_clk)) {
+ printk(KERN_DEBUG "%s: failed to get axi_b_clk\n",
+ __func__);
+ return PTR_ERR(axi_b_clk);
+ }
+
+ ddr_clk = clk_get(NULL, "ddr_clk");
+ if (IS_ERR(ddr_clk)) {
+ printk(KERN_DEBUG "%s: failed to get ddr_clk\n",
+ __func__);
+ return PTR_ERR(ddr_clk);
+ }
+
+ ddr_hf_clk = clk_get_parent(ddr_clk);
+
+ if (IS_ERR(ddr_hf_clk)) {
+ printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n",
+ __func__);
+ return PTR_ERR(ddr_hf_clk);
+ }
+
+ ahb_clk = clk_get(NULL, "ahb_clk");
+ if (IS_ERR(ahb_clk)) {
+ printk(KERN_DEBUG "%s: failed to get ahb_clk\n",
+ __func__);
+ return PTR_ERR(ahb_clk);
+ }
+
+ cpu_clk = clk_get(NULL, "cpu_clk");
+ if (IS_ERR(cpu_clk)) {
+ printk(KERN_DEBUG "%s: failed to get cpu_clk\n",
+ __func__);
+ return PTR_ERR(cpu_clk);
+ }
+
+ if (cpu_is_mx51())
+ emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
+ else if (cpu_is_mx53())
+ emi_garb_clk = clk_get(NULL, "emi_intr_clk.1");
+ else
+ emi_garb_clk = clk_get(NULL, "ocram_clk");
+ if (IS_ERR(emi_garb_clk)) {
+ printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n",
+ __func__);
+ return PTR_ERR(emi_garb_clk);
+ }
+
+ if (cpu_is_mx51() || cpu_is_mx53()) {
+ periph_apm_clk = clk_get(NULL, "periph_apm_clk");
+ if (IS_ERR(periph_apm_clk)) {
+ printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n",
+ __func__);
+ return PTR_ERR(periph_apm_clk);
+ }
+ }
+
+ lp_apm = clk_get(NULL, "lp_apm");
+ if (IS_ERR(lp_apm)) {
+ printk(KERN_DEBUG "%s: failed to get lp_apm\n",
+ __func__);
+ return PTR_ERR(lp_apm);
+ }
+
+ gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
+ if (IS_ERR(gpc_dvfs_clk)) {
+ printk(KERN_DEBUG "%s: failed to get gpc_dvfs_clk\n", __func__);
+ return PTR_ERR(gpc_dvfs_clk);
+ }
+
+ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
+ if (err) {
+ printk(KERN_ERR
+ "Unable to register sysdev entry for BUSFREQ");
+ return err;
+ }
+
+ pll1_rate = clk_get_rate(pll1_sw_clk);
+ pll2_rate = clk_get_rate(pll2);
+
+ if (pll2_rate == 665000000) {
+ /* for mx51 */
+ lp_normal_rate = pll2_rate / 5;
+ lp_med_rate = pll2_rate / 8;
+ ddr_normal_rate = pll1_rate / 4; /* 200M */
+ ddr_low_rate = pll1_rate / 6; /* 133M */
+ } else if (pll2_rate == 600000000) {
+ /* for mx53 evk rev.A */
+ lp_normal_rate = pll2_rate / 5;
+ lp_med_rate = pll2_rate / 8;
+ ddr_normal_rate = pll2_rate / 2;
+ ddr_low_rate = pll2_rate / 2;
+ } else if (pll2_rate == 400000000) {
+ if (cpu_is_mx50()) {
+ lp_normal_rate = pll2_rate / 3;
+ ddr_normal_rate = clk_get_rate(ddr_clk);
+ lp_med_rate = pll2_rate / 6;
+ ddr_low_rate = LP_APM_CLK;
+ if (mx50_ddr_type == MX50_LPDDR2)
+ ddr_med_rate = pll2_rate / 3;
+ else
+ /* mDDR @ 133Mhz currently does not work */
+ ddr_med_rate = ddr_normal_rate;
+ }
+ }
+
+ /* for mx53 */
+ if (cpu_is_mx53()) {
+ /* set DDR type */
+ if (machine_is_mx53_evk() || machine_is_mx53_ard())
+ mx53_ddr_type = DDR_TYPE_DDR2;
+ else
+ mx53_ddr_type = DDR_TYPE_DDR3;
+ if (mx53_ddr_type == DDR_TYPE_DDR2) {
+ /* DDR2 */
+ lp_normal_rate = pll2_rate / 3;
+ lp_med_rate = pll2_rate / 5;
+ ddr_normal_rate = pll2_rate / 1;
+ ddr_low_rate = pll2_rate / 3;
+ } else {
+ /* DDR3: DDR3 frequency can not be lower than 300MHZ */
+ lp_normal_rate = pll2_rate / 3;
+ lp_med_rate = pll2_rate / 5;
+ ddr_normal_rate = pll2_rate / 1;
+ ddr_low_rate = pll2_rate / 1;
+ }
+ }
+
+ if (cpu_is_mx50()) {
+ cur_ddr_rate = ddr_normal_rate;
+
+ lp_regulator = regulator_get(NULL, lp_reg_id);
+ if (IS_ERR(lp_regulator)) {
+ printk(KERN_DEBUG
+ "%s: failed to get lp regulator\n", __func__);
+ return PTR_ERR(lp_regulator);
+ }
+ voltage_wq = create_workqueue("voltage_change");
+ INIT_WORK(&voltage_change_handler, voltage_work_handler);
+
+ init_completion(&voltage_change_cmpl);
+ }
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+ low_bus_freq_mode = 0;
+ high_bus_freq_mode = 1;
+ med_bus_freq_mode = 0;
+ bus_freq_scaling_is_active = 0;
+ bus_freq_scaling_initialized = 1;
+
+ mutex_init(&bus_freq_mutex);
+ return 0;
+}
+
+static struct platform_driver busfreq_driver = {
+ .driver = {
+ .name = "busfreq",
+ },
+ .probe = busfreq_probe,
+ .suspend = busfreq_suspend,
+ .resume = busfreq_resume,
+};
+
+/*!
+ * Initialise the busfreq_driver.
+ *
+ * @return The function always returns 0.
+ */
+
+static int __init busfreq_init(void)
+{
+ if (platform_driver_register(&busfreq_driver) != 0) {
+ printk(KERN_ERR "busfreq_driver register failed\n");
+ return -ENODEV;
+ }
+
+ printk(KERN_INFO "Bus freq driver module loaded\n");
+ return 0;
+}
+
+static void __exit busfreq_cleanup(void)
+{
+ sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
+
+ /* Unregister the device structure */
+ platform_driver_unregister(&busfreq_driver);
+ bus_freq_scaling_initialized = 0;
+}
+
+module_init(busfreq_init);
+module_exit(busfreq_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("BusFreq driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
new file mode 100644
index 00000000000..4cbc05bbdc6
--- /dev/null
+++ b/arch/arm/mach-mx5/clock.c
@@ -0,0 +1,5250 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/time.h>
+#include <linux/hrtimer.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <asm/div64.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+#include <mach/mxc_dvfs.h>
+#include <mach/sdram_autogating.h>
+
+#include "crm_regs.h"
+#include "cpu_op-mx51.h"
+#include "cpu_op-mx53.h"
+
+/* External clock values passed-in by the board code */
+static unsigned long external_high_reference, external_low_reference;
+static unsigned long oscillator_reference, ckih2_reference;
+
+static struct clk dummy_clk;
+static struct clk pll1_main_clk;
+static struct clk pll1_sw_clk;
+static struct clk pll2_sw_clk;
+static struct clk pll3_sw_clk;
+static struct clk pll4_sw_clk;
+static struct clk lp_apm_clk;
+static struct clk tve_clk;
+static struct clk emi_fast_clk;
+static struct clk emi_slow_clk;
+static struct clk emi_intr_clk[];
+static struct clk ddr_clk;
+static struct clk ipu_clk[];
+static struct clk ldb_di_clk[];
+static struct clk axi_a_clk;
+static struct clk axi_b_clk;
+static struct clk ddr_hf_clk;
+static struct clk mipi_hsp_clk;
+static struct clk gpu3d_clk;
+static struct clk gpu2d_clk;
+static struct clk vpu_clk[];
+static int cpu_curr_op;
+static struct cpu_op *cpu_op_tbl;
+
+static void __iomem *pll1_base;
+static void __iomem *pll2_base;
+static void __iomem *pll3_base;
+static void __iomem *pll4_base;
+
+extern int cpu_op_nr;
+extern int lp_high_freq;
+extern int lp_med_freq;
+static int max_axi_a_clk;
+static int max_axi_b_clk;
+static int max_ahb_clk;
+static int max_emi_slow_clk;
+extern int dvfs_core_is_active;
+
+#define SPIN_DELAY 1000000 /* in nanoseconds */
+#define MAX_AXI_A_CLK_MX51 166250000
+#define MAX_AXI_A_CLK_MX53 400000000
+#define MAX_AXI_B_CLK_MX51 133000000
+#define MAX_AXI_B_CLK_MX53 200000000
+#define MAX_AHB_CLK_MX51 133000000
+#define MAX_EMI_SLOW_CLK_MX51 133000000
+#define MAX_AHB_CLK_MX53 133333333
+#define MAX_EMI_SLOW_CLK_MX53 133333333
+#define MAX_DDR_HF_RATE 200000000
+/* To keep compatible with some NAND flash, limit
+ * max NAND clk to 34MHZ. The user can modify it for
+ * dedicate NAND flash */
+#define MAX_NFC_CLK 34000000
+
+#define UART1_DMA_ENABLE 0
+#define UART2_DMA_ENABLE 0
+#define UART3_DMA_ENABLE 0
+#define UART4_DMA_ENABLE 0
+#define UART5_DMA_ENABLE 0
+
+#ifdef CONFIG_CLK_DEBUG
+#define __INIT_CLK_DEBUG(n) .name = #n,
+#else
+#define __INIT_CLK_DEBUG(n)
+#endif
+
+extern int mxc_jtag_enabled;
+extern int uart_at_24;
+extern int cpufreq_trig_needed;
+extern int low_bus_freq_mode;
+
+static int cpu_clk_set_op(int op);
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+
+static struct clk esdhc3_clk[];
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+ u32 min_pre, temp_pre, old_err, err;
+
+ if (div >= 512) {
+ *pre = 8;
+ *post = 64;
+ } else if (div >= 8) {
+ min_pre = (div - 1) / 64 + 1;
+ old_err = 8;
+ for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+ err = div % temp_pre;
+ if (err == 0) {
+ *pre = temp_pre;
+ break;
+ }
+ err = temp_pre - err;
+ if (err < old_err) {
+ old_err = err;
+ *pre = temp_pre;
+ }
+ }
+ *post = (div + *pre - 1) / *pre;
+ } else if (div < 8) {
+ *pre = div;
+ *post = 1;
+ }
+}
+
+static int _clk_enable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ if (clk->flags & AHB_HIGH_SET_POINT)
+ lp_high_freq++;
+ else if (clk->flags & AHB_MED_SET_POINT)
+ lp_med_freq++;
+
+ return 0;
+}
+
+static int _clk_enable_inrun(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+ return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+
+ if (clk->flags & AHB_HIGH_SET_POINT)
+ lp_high_freq--;
+ else if (clk->flags & AHB_MED_SET_POINT)
+ lp_med_freq--;
+}
+
+static void _clk_disable_inwait(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+}
+
+/*
+ * For the 4-to-1 muxed input clock
+ */
+static inline u32 _get_mux(struct clk *parent, struct clk *m0,
+ struct clk *m1, struct clk *m2, struct clk *m3)
+{
+ if (parent == m0)
+ return 0;
+ else if (parent == m1)
+ return 1;
+ else if (parent == m2)
+ return 2;
+ else if (parent == m3)
+ return 3;
+ else
+ BUG();
+
+ return 0;
+}
+
+/*
+ * For the ddr muxed input clock
+ */
+static inline u32 _get_mux_ddr(struct clk *parent, struct clk *m0,
+ struct clk *m1, struct clk *m2, struct clk *m3, struct clk *m4)
+{
+ if (parent == m0)
+ return 0;
+ else if (parent == m1)
+ return 1;
+ else if (parent == m2)
+ return 2;
+ else if (parent == m3)
+ return 3;
+ else if (parent == m4)
+ return 4;
+ else
+ BUG();
+
+ return 0;
+}
+
+static inline void __iomem *_get_pll_base(struct clk *pll)
+{
+ if (pll == &pll1_main_clk)
+ return pll1_base;
+ else if (pll == &pll2_sw_clk)
+ return pll2_base;
+ else if (pll == &pll3_sw_clk)
+ return pll3_base;
+ else if (pll == &pll4_sw_clk)
+ return pll4_base;
+ else
+ BUG();
+
+ return NULL;
+}
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+ return external_high_reference;
+}
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+ return external_low_reference;
+}
+
+static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
+{
+ return oscillator_reference;
+}
+
+static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
+{
+ return ckih2_reference;
+}
+
+/* External high frequency clock */
+static struct clk ckih_clk = {
+ __INIT_CLK_DEBUG(ckih_clk)
+ .get_rate = get_high_reference_clock_rate,
+};
+
+static struct clk ckih2_clk = {
+ __INIT_CLK_DEBUG(ckih2_clk)
+ .get_rate = get_ckih2_reference_clock_rate,
+};
+
+static struct clk osc_clk = {
+ __INIT_CLK_DEBUG(osc_clk)
+ .get_rate = get_oscillator_reference_clock_rate,
+};
+
+/* External low frequency (32kHz) clock */
+static struct clk ckil_clk = {
+ __INIT_CLK_DEBUG(ckil_clk)
+ .get_rate = get_low_reference_clock_rate,
+};
+
+static unsigned long _fpm_get_rate(struct clk *clk)
+{
+ u32 rate = ckil_clk.get_rate(&ckil_clk) * 512;
+ if ((__raw_readl(MXC_CCM_CCR) & MXC_CCM_CCR_FPM_MULT_MASK) != 0)
+ rate *= 2;
+ return rate;
+}
+
+static int _fpm_enable(struct clk *clk)
+{
+ u32 reg = __raw_readl(MXC_CCM_CCR);
+ reg |= MXC_CCM_CCR_FPM_EN;
+ __raw_writel(reg, MXC_CCM_CCR);
+ return 0;
+}
+
+static void _fpm_disable(struct clk *clk)
+{
+ u32 reg = __raw_readl(MXC_CCM_CCR);
+ reg &= ~MXC_CCM_CCR_FPM_EN;
+ __raw_writel(reg, MXC_CCM_CCR);
+}
+
+static struct clk fpm_clk = {
+ __INIT_CLK_DEBUG(fpm_clk)
+ .parent = &ckil_clk,
+ .get_rate = _fpm_get_rate,
+ .enable = _fpm_enable,
+ .disable = _fpm_disable,
+};
+
+static unsigned long _fpm_div2_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk fpm_div2_clk = {
+ __INIT_CLK_DEBUG(fpm_div2_clk)
+ .parent = &fpm_clk,
+ .get_rate = _fpm_div2_get_rate,
+};
+
+static unsigned long _clk_pll_get_rate(struct clk *clk)
+{
+ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+ unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+ void __iomem *pllbase;
+ s64 temp;
+
+ pllbase = _get_pll_base(clk);
+
+ dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+ dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+ if (pll_hfsm == 0) {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+ } else {
+ dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+ dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+ dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+ }
+ pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+ mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+ mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+ /* Sign extend to 32-bits */
+ if (mfn >= 0x04000000) {
+ mfn |= 0xFC000000;
+ mfn_abs = -mfn;
+ }
+
+ ref_clk = 2 * clk_get_rate(clk->parent);
+ if (dbl != 0)
+ ref_clk *= 2;
+
+ ref_clk /= (pdf + 1);
+ temp = (u64) ref_clk * mfn_abs;
+ do_div(temp, mfd + 1);
+ if (mfn < 0)
+ temp = -temp;
+ temp = (ref_clk * mfi) + temp;
+
+ return temp;
+}
+
+static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, reg1;
+ void __iomem *pllbase;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ long mfi, pdf, mfn, mfd = 999999;
+ s64 temp64;
+ unsigned long quad_parent_rate;
+ unsigned long pll_hfsm, dp_ctl;
+
+ pllbase = _get_pll_base(clk);
+
+ quad_parent_rate = 4 * clk_get_rate(clk->parent);
+ pdf = mfi = -1;
+ while (++pdf < 16 && mfi < 5)
+ mfi = rate * (pdf+1) / quad_parent_rate;
+ if (mfi > 15)
+ return -1;
+ pdf--;
+
+ temp64 = rate*(pdf+1) - quad_parent_rate*mfi;
+ do_div(temp64, quad_parent_rate/1000000);
+ mfn = (long)temp64;
+
+ dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ /* use dpdck0_2 */
+ __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+ pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+ if (pll_hfsm == 0) {
+ reg = mfi<<4 | pdf;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+ __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+ __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+ } else {
+ reg = mfi<<4 | pdf;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+ __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+ __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+ }
+ /* If auto restart is disabled, restart the PLL and
+ * wait for it to lock.
+ */
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ if (reg & MXC_PLL_DP_CTL_UPEN) {
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CONFIG);
+ if (!(reg & MXC_PLL_DP_CONFIG_AREN)) {
+ reg1 = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+ reg1 |= MXC_PLL_DP_CTL_RST;
+ __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
+ }
+ /* Wait for lock */
+ getnstimeofday(&nstimeofday);
+ while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+ & MXC_PLL_DP_CTL_LRF)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll_set_rate: pll relock failed\n");
+ }
+ }
+ return 0;
+}
+
+static int _clk_pll_enable(struct clk *clk)
+{
+ u32 reg;
+ void __iomem *pllbase;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ pllbase = _get_pll_base(clk);
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+
+ if (reg & MXC_PLL_DP_CTL_UPEN)
+ return 0;
+
+ reg |= MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+ /* Wait for lock */
+ getnstimeofday(&nstimeofday);
+ while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll relock failed\n");
+ }
+ return 0;
+}
+
+static void _clk_pll_disable(struct clk *clk)
+{
+ u32 reg;
+ void __iomem *pllbase;
+
+ pllbase = _get_pll_base(clk);
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+static struct clk pll1_main_clk = {
+ __INIT_CLK_DEBUG(pll1_main_clk)
+ .parent = &osc_clk,
+ .get_rate = _clk_pll_get_rate,
+ .enable = _clk_pll_enable,
+ .disable = _clk_pll_disable,
+};
+
+static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CCSR);
+
+ if (parent == &pll1_main_clk) {
+ reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+ __raw_writel(reg, MXC_CCM_CCSR);
+ /* Set the step_clk parent to be lp_apm, to save power. */
+ mux = _get_mux(&lp_apm_clk, &lp_apm_clk, NULL, &pll2_sw_clk,
+ &pll3_sw_clk);
+ reg = __raw_readl(MXC_CCM_CCSR);
+ reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+ (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+ } else {
+ if (parent == &lp_apm_clk) {
+ reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+ reg = __raw_readl(MXC_CCM_CCSR);
+ mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
+ &pll3_sw_clk);
+ reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+ (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+ } else {
+ mux = _get_mux(parent, &lp_apm_clk, NULL, &pll2_sw_clk,
+ &pll3_sw_clk);
+ reg = (reg & ~MXC_CCM_CCSR_STEP_SEL_MASK) |
+ (mux << MXC_CCM_CCSR_STEP_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CCSR);
+ reg = __raw_readl(MXC_CCM_CCSR);
+ reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+
+ }
+ }
+ __raw_writel(reg, MXC_CCM_CCSR);
+
+ return 0;
+}
+
+static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+ div = 1;
+ reg = __raw_readl(MXC_CCM_CCSR);
+
+ if (clk->parent == &pll2_sw_clk) {
+ div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
+ MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
+ } else if (clk->parent == &pll3_sw_clk) {
+ div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
+ MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+/* pll1 switch clock */
+static struct clk pll1_sw_clk = {
+ __INIT_CLK_DEBUG(pll1_sw_clk)
+ .parent = &pll1_main_clk,
+ .set_parent = _clk_pll1_sw_set_parent,
+ .get_rate = _clk_pll1_sw_get_rate,
+};
+
+static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCSR);
+
+ if (parent == &pll2_sw_clk) {
+ reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+ } else {
+ reg = (reg & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL);
+ reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
+ }
+ __raw_writel(reg, MXC_CCM_CCSR);
+ return 0;
+}
+
+/* same as pll2_main_clk. These two clocks should always be the same */
+static struct clk pll2_sw_clk = {
+ __INIT_CLK_DEBUG(pll2_sw_clk)
+ .parent = &osc_clk,
+ .get_rate = _clk_pll_get_rate,
+ .enable = _clk_pll_enable,
+ .disable = _clk_pll_disable,
+ .set_rate = _clk_pll_set_rate,
+ .set_parent = _clk_pll2_sw_set_parent,
+};
+
+/* same as pll3_main_clk. These two clocks should always be the same */
+static struct clk pll3_sw_clk = {
+ __INIT_CLK_DEBUG(pll3_sw_clk)
+ .parent = &osc_clk,
+ .set_rate = _clk_pll_set_rate,
+ .get_rate = _clk_pll_get_rate,
+ .enable = _clk_pll_enable,
+ .disable = _clk_pll_disable,
+};
+
+/* same as pll4_main_clk. These two clocks should always be the same */
+static struct clk pll4_sw_clk = {
+ __INIT_CLK_DEBUG(pll4_sw_clk)
+ .parent = &osc_clk,
+ .set_rate = _clk_pll_set_rate,
+ .get_rate = _clk_pll_get_rate,
+ .enable = _clk_pll_enable,
+ .disable = _clk_pll_disable,
+};
+
+static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ if (parent == &osc_clk)
+ reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
+ else if (parent == &fpm_clk)
+ reg = __raw_readl(MXC_CCM_CCSR) | MXC_CCM_CCSR_LP_APM_SEL;
+ else
+ return -EINVAL;
+
+ __raw_writel(reg, MXC_CCM_CCSR);
+
+ return 0;
+}
+
+static struct clk lp_apm_clk = {
+ __INIT_CLK_DEBUG(lp_apm_clk)
+ .parent = &osc_clk,
+ .set_parent = _clk_lp_apm_set_parent,
+};
+
+static unsigned long _clk_arm_get_rate(struct clk *clk)
+{
+ u32 cacrr, div;
+
+ cacrr = __raw_readl(MXC_CCM_CACRR);
+ div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 i;
+ for (i = 0; i < cpu_op_nr; i++) {
+ if (rate == cpu_op_tbl[i].cpu_rate)
+ break;
+ }
+ if (i >= cpu_op_nr)
+ return -EINVAL;
+ cpu_clk_set_op(i);
+
+ return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 i;
+ u32 op;
+
+ for (i = 0; i < cpu_op_nr; i++) {
+ if (rate == cpu_op_tbl[i].cpu_rate)
+ break;
+ }
+
+ if (i > cpu_op_nr)
+ op = 0;
+
+ return cpu_op_tbl[op].cpu_rate;
+}
+
+
+static struct clk cpu_clk = {
+ __INIT_CLK_DEBUG(cpu_clk)
+ .parent = &pll1_sw_clk,
+ .get_rate = _clk_arm_get_rate,
+ .set_rate = _clk_cpu_set_rate,
+ .round_rate = _clk_cpu_round_rate,
+};
+
+static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
+
+ reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) &
+ MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll _clk_periph_apm_set_parent failed\n");
+ }
+ return 0;
+}
+
+static struct clk periph_apm_clk = {
+ __INIT_CLK_DEBUG(periph_apm_clk)
+ .parent = &pll1_sw_clk,
+ .set_parent = _clk_periph_apm_set_parent,
+};
+
+/* TODO: Need to sync with GPC to determine if DVFS is in place so that
+ * the DVFS_PODF divider can be applied in CDCR register.
+ */
+static unsigned long _clk_main_bus_get_rate(struct clk *clk)
+{
+ u32 div = 0;
+
+ if (dvfs_per_divider_active() || low_bus_freq_mode)
+ div = (__raw_readl(MXC_CCM_CDCR) & 0x3);
+ return clk_get_rate(clk->parent) / (div + 1);
+}
+
+static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ if (parent == &pll2_sw_clk) {
+ reg = __raw_readl(MXC_CCM_CBCDR) &
+ ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+ } else if (parent == &periph_apm_clk) {
+ reg = __raw_readl(MXC_CCM_CBCDR) | MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+ } else {
+ return -EINVAL;
+ }
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static struct clk main_bus_clk = {
+ __INIT_CLK_DEBUG(main_bus_clk)
+ .parent = &pll2_sw_clk,
+ .set_parent = _clk_main_bus_set_parent,
+ .get_rate = _clk_main_bus_get_rate,
+};
+
+static unsigned long _clk_axi_a_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_AXI_A_PODF_MASK) >>
+ MXC_CCM_CBCDR_AXI_A_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll _clk_axi_a_set_rate failed\n");
+ }
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static unsigned long _clk_axi_a_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ /* Make sure rate is not greater than the maximum value for the clock.
+ * Also prevent a div of 0.
+ */
+ if (div == 0)
+ div++;
+ if (parent_rate / div > max_axi_a_clk)
+ div++;
+
+ if (div > 8)
+ div = 8;
+
+ return parent_rate / div;
+}
+
+
+static struct clk axi_a_clk = {
+ __INIT_CLK_DEBUG(axi_a_clk)
+ .parent = &main_bus_clk,
+ .get_rate = _clk_axi_a_get_rate,
+ .set_rate = _clk_axi_a_set_rate,
+ .round_rate = _clk_axi_a_round_rate,
+};
+
+static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
+ MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_ddr_hf_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ /* Make sure rate is not greater than the maximum value for the clock.
+ * Also prevent a div of 0.
+ */
+ if (div == 0)
+ div++;
+ if (parent_rate / div > MAX_DDR_HF_RATE)
+ div++;
+
+ if (div > 8)
+ div = 8;
+
+ return parent_rate / div;
+}
+
+static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_DDR_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_DDR_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("clk_ddr_hf_set_rate failed\n");
+ }
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static struct clk ddr_hf_clk = {
+ __INIT_CLK_DEBUG(ddr_hf_clk)
+ .parent = &pll1_sw_clk,
+ .get_rate = _clk_ddr_hf_get_rate,
+ .round_rate = _clk_ddr_hf_round_rate,
+ .set_rate = _clk_ddr_hf_set_rate,
+};
+
+static unsigned long _clk_axi_b_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_AXI_B_PODF_MASK) >>
+ MXC_CCM_CBCDR_AXI_B_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("_clk_axi_b_set_rate failed\n");
+ }
+
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static unsigned long _clk_axi_b_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ /* Make sure rate is not greater than the maximum value for the clock.
+ * Also prevent a div of 0.
+ */
+ if (div == 0)
+ div++;
+ if (parent_rate / div > max_axi_b_clk)
+ div++;
+
+ if (div > 8)
+ div = 8;
+
+ return parent_rate / div;
+}
+
+
+static struct clk axi_b_clk = {
+ __INIT_CLK_DEBUG(axi_b_clk)
+ .parent = &main_bus_clk,
+ .get_rate = _clk_axi_b_get_rate,
+ .set_rate = _clk_axi_b_set_rate,
+ .round_rate = _clk_axi_b_round_rate,
+};
+
+static unsigned long _clk_ahb_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+
+static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("_clk_ahb_set_rate failed\n");
+ }
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static unsigned long _clk_ahb_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ /* Make sure rate is not greater than the maximum value for the clock.
+ * Also prevent a div of 0.
+ */
+ if (div == 0)
+ div++;
+ if (parent_rate / div > max_ahb_clk)
+ div++;
+
+ if (div > 8)
+ div = 8;
+
+ return parent_rate / div;
+}
+
+
+static struct clk ahb_clk = {
+ __INIT_CLK_DEBUG(ahb_clk)
+ .parent = &main_bus_clk,
+ .get_rate = _clk_ahb_get_rate,
+ .set_rate = _clk_ahb_set_rate,
+ .round_rate = _clk_ahb_round_rate,
+};
+
+static int _clk_max_enable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_enable(clk);
+
+ /* Handshake with MAX when LPM is entered. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ if (cpu_is_mx51())
+ reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51;
+ else
+ reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ return 0;
+}
+
+
+static void _clk_max_disable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_disable_inwait(clk);
+
+ /* No Handshake with MAX when LPM is entered as its disabled. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ if (cpu_is_mx51())
+ reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51;
+ else
+ reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+
+static struct clk ahb_max_clk = {
+ __INIT_CLK_DEBUG(ahb_max_clk)
+ .parent = &ahb_clk,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .enable = _clk_max_enable,
+ .disable = _clk_max_disable,
+};
+
+static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ if (parent == &ahb_clk) {
+ reg |= MXC_CCM_CBCDR_EMI_CLK_SEL;
+ } else if (parent == &main_bus_clk) {
+ reg &= ~MXC_CCM_CBCDR_EMI_CLK_SEL;
+ } else {
+ BUG();
+ }
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+ MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+ panic("_clk_emi_slow_set_rate failed\n");
+ }
+
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+
+ return 0;
+}
+
+static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ /* Make sure rate is not greater than the maximum value for the clock.
+ * Also prevent a div of 0.
+ */
+ if (div == 0)
+ div++;
+ if (parent_rate / div > max_emi_slow_clk)
+ div++;
+
+ if (div > 8)
+ div = 8;
+
+ return parent_rate / div;
+}
+
+
+static struct clk emi_slow_clk = {
+ __INIT_CLK_DEBUG(emi_slow_clk)
+ .parent = &main_bus_clk,
+ .set_parent = _clk_emi_slow_set_parent,
+ .get_rate = _clk_emi_slow_get_rate,
+ .set_rate = _clk_emi_slow_set_rate,
+ .round_rate = _clk_emi_slow_round_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .disable = _clk_disable_inwait,
+};
+
+static struct clk ahbmux1_clk = {
+ __INIT_CLK_DEBUG(ahbmux1_clk)
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .disable = _clk_disable_inwait,
+};
+
+static struct clk ahbmux2_clk = {
+ __INIT_CLK_DEBUG(ahbmux2_clk)
+ .id = 0,
+ .parent = &ahb_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .disable = _clk_disable_inwait,
+};
+
+
+static struct clk emi_fast_clk = {
+ __INIT_CLK_DEBUG(emi_fast_clk)
+ .parent = &ddr_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .disable = _clk_disable_inwait,
+};
+
+static struct clk emi_intr_clk[] = {
+ {
+ __INIT_CLK_DEBUG(emi_intr_clk_0)
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahbmux2_clk,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+ },
+ {
+ /* On MX51 - this clock is name emi_garb_clk, and controls the
+ * access of ARM to GARB.
+ */
+ __INIT_CLK_DEBUG(emi_intr_clk_1)
+ .id = 1,
+ .parent = &ahb_clk,
+ .secondary = &ahbmux2_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+ }
+};
+
+static unsigned long _clk_ipg_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk ipg_clk = {
+ __INIT_CLK_DEBUG(ipg_clk)
+ .parent = &ahb_clk,
+ .get_rate = _clk_ipg_get_rate,
+};
+
+static unsigned long _clk_ipg_per_get_rate(struct clk *clk)
+{
+ u32 reg, prediv1, prediv2, podf;
+
+ if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
+ /* the main_bus_clk is the one before the DVFS engine */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
+ prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / (prediv1 * prediv2 * podf);
+ } else if (clk->parent == &ipg_clk) {
+ return clk_get_rate(&ipg_clk);
+ }
+ BUG();
+ return 0;
+}
+
+static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &main_bus_clk, &lp_apm_clk, &ipg_clk, NULL);
+ if (mux == 2) {
+ reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+ } else {
+ reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
+ if (mux == 0)
+ reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+ else
+ reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
+ }
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+static struct clk ipg_perclk = {
+ __INIT_CLK_DEBUG(ipg_perclk)
+ .parent = &lp_apm_clk,
+ .get_rate = _clk_ipg_per_get_rate,
+ .set_parent = _clk_ipg_per_set_parent,
+};
+
+static int _clk_ipmux_enable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void _clk_ipmux_disable(struct clk *clk)
+{
+ u32 reg;
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(0x1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static struct clk ipumux1_clk = {
+ __INIT_CLK_DEBUG(ipumux1_clk)
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGR5_CG6_1_OFFSET,
+ .enable = _clk_ipmux_enable,
+ .disable = _clk_ipmux_disable,
+};
+
+static struct clk ipumux2_clk = {
+ __INIT_CLK_DEBUG(ipumux2_clk)
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGR5_CG6_2_OFFSET,
+ .enable = _clk_ipmux_enable,
+ .disable = _clk_ipmux_disable,
+};
+
+static int _clk_ocram_enable(struct clk *clk)
+{
+ return 0;
+}
+
+static void _clk_ocram_disable(struct clk *clk)
+{
+}
+
+static struct clk ocram_clk = {
+ __INIT_CLK_DEBUG(ocram_clk)
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .enable = _clk_ocram_enable,
+ .disable = _clk_ocram_disable,
+};
+
+
+static struct clk aips_tz1_clk = {
+ __INIT_CLK_DEBUG(aips_tz1_clk)
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+};
+
+static struct clk aips_tz2_clk = {
+ __INIT_CLK_DEBUG(aips_tz2_clk)
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable_inwait,
+};
+
+static struct clk gpc_dvfs_clk = {
+ __INIT_CLK_DEBUG(gpc_dvfs_clk)
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static int _clk_sdma_enable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_enable(clk);
+
+ /* Handshake with SDMA when LPM is entered. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ if (cpu_is_mx51())
+ reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+ else
+ reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ return 0;
+}
+
+static void _clk_sdma_disable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_disable(clk);
+ /* No handshake with SDMA as its not enabled. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ if (cpu_is_mx51())
+ reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+ else
+ reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+
+static struct clk sdma_clk[] = {
+ {
+ __INIT_CLK_DEBUG(sdma_clk)
+ .parent = &ahb_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .enable = _clk_sdma_enable,
+ .disable = _clk_sdma_disable,
+ },
+ {
+ .parent = &ipg_clk,
+#ifdef CONFIG_SDMA_IRAM
+ .secondary = &emi_intr_clk[0],
+#endif
+ },
+};
+
+static int _clk_ipu_enable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_enable(clk);
+ /* Handshake with IPU when certain clock rates are changed. */
+ reg = __raw_readl(MXC_CCM_CCDR);
+ if (cpu_is_mx51())
+ reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+ else
+ reg &= ~MXC_CCM_CCDR_IPU_HS_MX53_MASK;
+ __raw_writel(reg, MXC_CCM_CCDR);
+
+ /* Handshake with IPU when LPM is entered as its enabled. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ start_sdram_autogating();
+
+ return 0;
+}
+
+static void _clk_ipu_disable(struct clk *clk)
+{
+ u32 reg;
+
+ if (sdram_autogating_active())
+ stop_sdram_autogating();
+
+ _clk_disable(clk);
+
+ /* No handshake with IPU whe dividers are changed
+ * as its not enabled. */
+ reg = __raw_readl(MXC_CCM_CCDR);
+ if (cpu_is_mx51())
+ reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+ else
+ reg |= MXC_CCM_CCDR_IPU_HS_MX53_MASK;
+ __raw_writel(reg, MXC_CCM_CCDR);
+
+ /* No handshake with IPU when LPM is entered as its not enabled. */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static int _clk_ipu_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &ahb_clk,
+ &emi_slow_clk);
+ reg = (reg & ~MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+
+static struct clk ipu_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ipu_clk)
+ .parent = &ahb_clk,
+ .secondary = &ipu_clk[1],
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_ipu_enable,
+ .disable = _clk_ipu_disable,
+ .set_parent = _clk_ipu_set_parent,
+ .flags = CPU_FREQ_TRIG_UPDATE | AHB_MED_SET_POINT,
+ },
+ {
+ __INIT_CLK_DEBUG(ipu_clk_1)
+ .parent = &emi_fast_clk,
+ .secondary = &ahbmux1_clk,
+ }
+};
+
+static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ reg &= ~MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id);
+ if (parent == &pll3_sw_clk)
+ ;
+ else if (parent == &osc_clk)
+ reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ else if (parent == &ckih_clk)
+ reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ else if ((parent == &pll4_sw_clk) && (clk->id == 0)) {
+ if (cpu_is_mx51())
+ return -EINVAL;
+ reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ } else if ((parent == &tve_clk) && (clk->id == 1))
+ reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ else if ((parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())
+ reg |= 5 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ else /* Assume any other clock is external clock pin */
+ reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static int priv_div;
+static unsigned long _clk_ipu_di_get_rate(struct clk *clk)
+{
+ u32 reg, mux;
+ u32 div = 1;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ mux = (reg & MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(clk->id)) >>
+ MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id);
+ if (mux == 0) {
+ reg = __raw_readl(MXC_CCM_CDCDR) &
+ MXC_CCM_CDCDR_DI1_CLK_PRED_MASK;
+ div = (reg >> MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET) + 1;
+ } else if ((mux == 3) && (clk->id == 1)) {
+ if (priv_div)
+ div = priv_div;
+ } else if ((mux == 3) && (clk->id == 0)) {
+ reg = __raw_readl(MXC_CCM_CDCDR) &
+ MXC_CCM_CDCDR_DI_PLL4_PODF_MASK;
+ div = (reg >> MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET) + 1;
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+
+ if ((clk->parent == &pll4_sw_clk) && (clk->id == 0)) {
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ reg &= ~MXC_CCM_CDCDR_DI_PLL4_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+ } else if (clk->parent == &pll3_sw_clk) {
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ reg &= ~MXC_CCM_CDCDR_DI1_CLK_PRED_MASK;
+ reg |= (div - 1) << MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+ } else if (((clk->parent == &tve_clk) && (clk->id == 1)) ||
+ ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())) {
+ priv_div = div;
+ return 0;
+ } else
+ return -EINVAL;
+
+ return 0;
+}
+
+static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53())
+ return parent_rate;
+ else {
+ div = (parent_rate + rate/2) / rate;
+ if (div > 8)
+ div = 8;
+ else if (div == 0)
+ div++;
+ return parent_rate / div;
+ }
+}
+
+static struct clk ipu_di_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ipu_di_clk_0)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .get_rate = _clk_ipu_di_get_rate,
+ .set_parent = _clk_ipu_di_set_parent,
+ .round_rate = _clk_ipu_di_round_rate,
+ .set_rate = _clk_ipu_di_set_rate,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ipu_di_clk_1)
+ .id = 1,
+ .parent = &pll3_sw_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .get_rate = _clk_ipu_di_get_rate,
+ .set_parent = _clk_ipu_di_set_parent,
+ .round_rate = _clk_ipu_di_round_rate,
+ .set_rate = _clk_ipu_di_set_rate,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static int _clk_ldb_di_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+
+ if ((parent == &pll3_sw_clk)) {
+ if (clk->id == 0)
+ reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL);
+ else
+ reg &= ~(MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL);
+ } else if ((parent == &pll4_sw_clk)) {
+ if (clk->id == 0)
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL;
+ else
+ reg |= MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL;
+ } else {
+ BUG();
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+ return 0;
+}
+
+static unsigned long _clk_ldb_di_get_rate(struct clk *clk)
+{
+ u32 div;
+
+ if (clk->id == 0)
+ div = __raw_readl(MXC_CCM_CSCMR2) &
+ MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ else
+ div = __raw_readl(MXC_CCM_CSCMR2) &
+ MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+
+ if (div)
+ return clk_get_rate(clk->parent) / 7;
+
+ return (2 * clk_get_rate(clk->parent)) / 7;
+}
+
+static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if (rate * 7 <= parent_rate + parent_rate/20)
+ return parent_rate / 7;
+ else
+ return 2 * parent_rate / 7;
+}
+
+static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div = 0;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if (rate * 7 <= parent_rate + parent_rate/20) {
+ div = 7;
+ rate = parent_rate / 7;
+ } else
+ rate = 2 * parent_rate / 7;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ if (div == 7)
+ reg |= (clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV :
+ MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+ else
+ reg &= ~(clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV :
+ MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static int _clk_ldb_di_enable(struct clk *clk)
+{
+ _clk_enable(clk);
+ ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk);
+ ipu_di_clk[clk->id].parent = clk;
+ ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]);
+ ipu_di_clk[clk->id].usecount++;
+ return 0;
+}
+
+static void _clk_ldb_di_disable(struct clk *clk)
+{
+ _clk_disable(clk);
+ ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]);
+ ipu_di_clk[clk->id].usecount--;
+}
+
+static struct clk ldb_di_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ldb_di_clk_0)
+ .id = 0,
+ .parent = &pll4_sw_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .get_rate = _clk_ldb_di_get_rate,
+ .set_parent = _clk_ldb_di_set_parent,
+ .round_rate = _clk_ldb_di_round_rate,
+ .set_rate = _clk_ldb_di_set_rate,
+ .enable = _clk_ldb_di_enable,
+ .disable = _clk_ldb_di_disable,
+ .flags = AHB_MED_SET_POINT,
+ },
+ {
+ __INIT_CLK_DEBUG(ldb_di_clk_1)
+ .id = 1,
+ .parent = &pll4_sw_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .get_rate = _clk_ldb_di_get_rate,
+ .set_parent = _clk_ldb_di_set_parent,
+ .round_rate = _clk_ldb_di_round_rate,
+ .set_rate = _clk_ldb_di_set_rate,
+ .enable = _clk_ldb_di_enable,
+ .disable = _clk_ldb_di_disable,
+ .flags = AHB_MED_SET_POINT,
+ },
+};
+
+static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+ reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_csi0_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR4);
+ pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent)/(pred * podf);
+}
+
+static unsigned long _clk_csi0_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set CSI clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR4) &
+ ~(MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK |
+ MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR4);
+
+ return 0;
+}
+
+static struct clk csi0_clk = {
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_csi0_set_parent,
+ .get_rate = _clk_csi0_get_rate,
+ .round_rate = _clk_csi0_round_rate,
+ .set_rate = _clk_csi0_set_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+};
+
+static int _clk_csi1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+ reg = (reg & ~MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_csi1_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR4);
+ pred = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent)/(pred * podf) ;
+}
+
+static unsigned long _clk_csi1_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set CSI clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR4) &
+ ~(MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK |
+ MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR4);
+
+ return 0;
+}
+
+static struct clk csi1_clk = {
+ __INIT_CLK_DEBUG(csi1_clk)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_csi1_set_parent,
+ .get_rate = _clk_csi1_get_rate,
+ .round_rate = _clk_csi1_round_rate,
+ .set_rate = _clk_csi1_set_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .disable = _clk_disable,
+};
+
+
+static int _clk_hsc_enable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_enable(clk);
+ /* Handshake with IPU when certain clock rates are changed. */
+ reg = __raw_readl(MXC_CCM_CCDR);
+ reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
+ __raw_writel(reg, MXC_CCM_CCDR);
+
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ return 0;
+}
+
+static void _clk_hsc_disable(struct clk *clk)
+{
+ u32 reg;
+
+ _clk_disable(clk);
+ /* No handshake with HSC as its not enabled. */
+ reg = __raw_readl(MXC_CCM_CCDR);
+ reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+ __raw_writel(reg, MXC_CCM_CCDR);
+
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk mipi_esc_clk = {
+ __INIT_CLK_DEBUG(mipi_esc_clk)
+ .parent = &pll2_sw_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+};
+
+static struct clk mipi_hsc2_clk = {
+ __INIT_CLK_DEBUG(mipi_hsc2_clk)
+ .parent = &pll2_sw_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .secondary = &mipi_esc_clk,
+};
+
+static struct clk mipi_hsc1_clk = {
+ __INIT_CLK_DEBUG(mipi_hsc1_clk)
+ .parent = &pll2_sw_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .secondary = &mipi_hsc2_clk,
+};
+
+static struct clk mipi_hsp_clk = {
+ __INIT_CLK_DEBUG(mipi_hsp_clk)
+ .parent = &ipu_clk[0],
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .enable = _clk_hsc_enable,
+ .disable = _clk_hsc_disable,
+ .secondary = &mipi_hsc1_clk,
+};
+
+static int _clk_tve_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+
+ if ((parent == &pll3_sw_clk) && cpu_is_mx51()) {
+ reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL);
+ } else if ((parent == &pll4_sw_clk) && cpu_is_mx53()) {
+ reg &= ~(MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL);
+ } else if ((parent == &osc_clk) && cpu_is_mx51()) {
+ reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL;
+ reg &= ~MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
+ } else if (parent == &ckih_clk) {
+ reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL;
+ reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; /* Reserved on MX53 */
+ } else {
+ BUG();
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+ return 0;
+}
+
+static unsigned long _clk_tve_get_rate(struct clk *clk)
+{
+ u32 reg, div = 1;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if ((reg & (MXC_CCM_CSCMR1_TVE_CLK_SEL | MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) == 0) {
+ reg = __raw_readl(MXC_CCM_CDCDR) &
+ MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
+ div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1;
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_tve_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 reg, div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL))
+ return -EINVAL;
+ if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
+ return -EINVAL;
+
+ div = (parent_rate + rate/2) / rate;
+ if (div > 8)
+ div = 8;
+ else if (div == 0)
+ div++;
+ return parent_rate / div;
+}
+
+static int _clk_tve_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL))
+ return -EINVAL;
+ if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
+ return -EINVAL;
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+
+ div--;
+ reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_TVE_CLK_PRED_MASK;
+ reg |= div << MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+ return 0;
+}
+
+static struct clk tve_clk = {
+ __INIT_CLK_DEBUG(tve_clk)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_tve_set_parent,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .get_rate = _clk_tve_get_rate,
+ .round_rate = _clk_tve_round_rate,
+ .set_rate = _clk_tve_set_rate,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static struct clk spba_clk = {
+ __INIT_CLK_DEBUG(spba_clk)
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_uart_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent)/(prediv * podf) ;
+}
+
+static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk uart_main_clk = {
+ __INIT_CLK_DEBUG(uart_main_clk)
+ .parent = &pll2_sw_clk,
+ .get_rate = _clk_uart_get_rate,
+ .set_parent = _clk_uart_set_parent,
+};
+
+static struct clk uart1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(uart1_clk_0)
+ .id = 0,
+ .parent = &uart_main_clk,
+ .secondary = &uart1_clk[1],
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+#if UART1_DMA_ENABLE
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+ },
+ {
+ __INIT_CLK_DEBUG(uart1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+#if UART1_DMA_ENABLE
+ .secondary = &aips_tz1_clk,
+#endif
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk uart2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(uart2_clk_0)
+ .id = 1,
+ .parent = &uart_main_clk,
+ .secondary = &uart2_clk[1],
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+#if UART2_DMA_ENABLE
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+ },
+ {
+ __INIT_CLK_DEBUG(uart2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+#if UART2_DMA_ENABLE
+ .secondary = &aips_tz1_clk,
+#endif
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk uart3_clk[] = {
+ {
+ __INIT_CLK_DEBUG(uart3_clk_0)
+ .id = 2,
+ .parent = &uart_main_clk,
+ .secondary = &uart3_clk[1],
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+#if UART3_DMA_ENABLE
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+ },
+ {
+ __INIT_CLK_DEBUG(uart3_clk_1)
+ .id = 2,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk uart4_clk[] = {
+ {
+ __INIT_CLK_DEBUG(uart4_clk_0)
+ .id = 3,
+ .parent = &uart_main_clk,
+ .secondary = &uart4_clk[1],
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+#if UART4_DMA_ENABLE
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+ },
+ {
+ __INIT_CLK_DEBUG(uart4_clk_1)
+ .id = 3,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk uart5_clk[] = {
+ {
+ __INIT_CLK_DEBUG(uart5_clk_0)
+ .id = 4,
+ .parent = &uart_main_clk,
+ .secondary = &uart5_clk[1],
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+#if UART5_DMA_ENABLE
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+#endif
+ },
+ {
+ __INIT_CLK_DEBUG(uart5_clk_1)
+ .id = 4,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk gpt_clk[] = {
+ {
+ __INIT_CLK_DEBUG(gpt_clki_0)
+ .parent = &ipg_perclk,
+ .id = 0,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .secondary = &gpt_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(gpt_clki_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(gpt_clki_2)
+ .id = 0,
+ .parent = &ckil_clk,
+ },
+};
+
+static struct clk pwm1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(pwm1_clk_0)
+ .parent = &ipg_perclk,
+ .id = 0,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .secondary = &pwm1_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(pwm1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(pwm1_clk_2)
+ .id = 0,
+ .parent = &ckil_clk,
+ },
+};
+
+static struct clk pwm2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(pwm2_clk_0)
+ .parent = &ipg_perclk,
+ .id = 1,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .secondary = &pwm2_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(pwm2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(pwm2_clk_2)
+ .id = 1,
+ .parent = &ckil_clk,
+ },
+};
+
+static struct clk i2c_clk[] = {
+ {
+ __INIT_CLK_DEBUG(i2c_clk_0)
+ .id = 0,
+ .parent = &ipg_perclk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(i2c_clk_1)
+ .id = 1,
+ .parent = &ipg_perclk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(i2c_clk_2)
+ .id = 2,
+ .parent = &ipg_perclk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static unsigned long _clk_hsi2c_serial_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR3);
+ prediv = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static struct clk hsi2c_serial_clk = {
+ __INIT_CLK_DEBUG(hsi2c_serial_clk)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .secondary = &spba_clk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .get_rate = _clk_hsi2c_serial_get_rate,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static struct clk hsi2c_clk = {
+ __INIT_CLK_DEBUG(hsi2c_clk)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static unsigned long _clk_cspi_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk cspi_main_clk = {
+ __INIT_CLK_DEBUG(cspi_main_clk)
+ .parent = &pll3_sw_clk,
+ .get_rate = _clk_cspi_get_rate,
+ .set_parent = _clk_cspi_set_parent,
+};
+
+static struct clk cspi1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(cspi1_clk_0)
+ .id = 0,
+ .parent = &cspi_main_clk,
+ .secondary = &cspi1_clk[1],
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(cspi1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk cspi2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(cspi2_clk_0)
+ .id = 1,
+ .parent = &cspi_main_clk,
+ .secondary = &cspi2_clk[1],
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(cspi2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+ .secondary = &aips_tz2_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .enable = _clk_enable_inrun, /*Active only when ARM is running. */
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk cspi3_clk = {
+ __INIT_CLK_DEBUG(cspi3_clk)
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ .secondary = &aips_tz2_clk,
+};
+
+static unsigned long _clk_ieee_rtc_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ prediv = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_ieee_rtc_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div, pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || div > 512)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ reg &= ~(MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK |
+ MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR2);
+
+ return 0;
+}
+
+static unsigned long _clk_ieee_rtc_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static int _clk_ieee_rtc_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll3_sw_clk, &pll4_sw_clk,
+ NULL, NULL);
+ reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static struct clk ieee_rtc_clk = {
+ __INIT_CLK_DEBUG(ieee_rtc_clk)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_ieee_rtc_set_parent,
+ .set_rate = _clk_ieee_rtc_set_rate,
+ .round_rate = _clk_ieee_rtc_round_rate,
+ .get_rate = _clk_ieee_rtc_get_rate,
+};
+
+static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &ckih_clk, &lp_apm_clk, &ckih2_clk, NULL);
+ reg = __raw_readl(MXC_CCM_CSCMR1) &
+ ~MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk ssi_lp_apm_clk = {
+ __INIT_CLK_DEBUG(ssi_lp_apm_clk)
+ .parent = &ckih_clk,
+ .set_parent = _clk_ssi_lp_apm_set_parent,
+};
+
+static unsigned long _clk_ssi1_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) >>
+ MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) >>
+ MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
+ &pll3_sw_clk, &ssi_lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk ssi1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ssi1_clk_0)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_ssi1_set_parent,
+ .secondary = &ssi1_clk[1],
+ .get_rate = _clk_ssi1_get_rate,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .secondary = &ssi1_clk[2],
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi1_clk_2)
+ .id = 0,
+ .parent = &aips_tz2_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+ .secondary = &emi_intr_clk[0],
+#else
+ .secondary = &emi_fast_clk,
+#endif
+ },
+};
+
+static unsigned long _clk_ssi2_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CS2CDR);
+ prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) >>
+ MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) >>
+ MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,
+ &pll3_sw_clk, &ssi_lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk ssi2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ssi2_clk_0)
+ .id = 1,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_ssi2_set_parent,
+ .secondary = &ssi2_clk[1],
+ .get_rate = _clk_ssi2_get_rate,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+ .secondary = &ssi2_clk[2],
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi2_clk_2)
+ .id = 1,
+ .parent = &spba_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+ .secondary = &emi_intr_clk[0],
+#else
+ .secondary = &emi_fast_clk,
+#endif
+ },
+};
+
+static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+
+ if (parent == &ssi1_clk[0])
+ reg &= ~MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+ else if (parent == &ssi2_clk[0])
+ reg |= MXC_CCM_CSCMR1_SSI3_CLK_SEL;
+ else {
+ printk(KERN_ERR"Set ssi3 clock parent failed!\n");
+ printk(KERN_ERR"ssi3 only support");
+ printk(KERN_ERR"ssi1 and ssi2 as parent clock\n");
+ return -1;
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+ return 0;
+}
+
+static struct clk ssi3_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ssi3_clk_0)
+ .id = 2,
+ .parent = &ssi1_clk[0],
+ .set_parent = _clk_ssi3_set_parent,
+ .secondary = &ssi3_clk[1],
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi3_clk_1)
+ .id = 2,
+ .parent = &ipg_clk,
+ .secondary = &ssi3_clk[2],
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(ssi3_clk_2)
+ .id = 2,
+ .parent = &aips_tz2_clk,
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+ .secondary = &emi_intr_clk,
+#else
+ .secondary = &emi_fast_clk,
+#endif
+ },
+};
+
+static unsigned long _clk_ssi_ext1_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+ u32 div = 1;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if ((reg & MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL) == 0) {
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ prediv = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK) >>
+ MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK) >>
+ MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET) + 1;
+ div = prediv * podf;
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div, pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || div > 512)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ reg &= ~(MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK |
+ MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CS1CDR);
+
+ return 0;
+}
+
+static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &ssi1_clk[0]) {
+ reg |= MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
+ } else {
+ reg &= ~MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL;
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &ssi_lp_apm_clk);
+ reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET);
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static struct clk ssi_ext1_clk = {
+ __INIT_CLK_DEBUG(ssi_ext1_clk)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_ssi_ext1_set_parent,
+ .set_rate = _clk_ssi_ext1_set_rate,
+ .round_rate = _clk_ssi_ext1_round_rate,
+ .get_rate = _clk_ssi_ext1_get_rate,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_ssi_ext2_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+ u32 div = 1;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if ((reg & MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL) == 0) {
+ reg = __raw_readl(MXC_CCM_CS2CDR);
+ prediv = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK) >>
+ MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK) >>
+ MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET) + 1;
+ div = prediv * podf;
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_ssi_ext2_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &ssi2_clk[0]) {
+ reg |= MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
+ } else {
+ reg &= ~MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL;
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &ssi_lp_apm_clk);
+ reg = (reg & ~MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET);
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk ssi_ext2_clk = {
+ __INIT_CLK_DEBUG(ssi_ext2_clk)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_ssi_ext2_set_parent,
+ .get_rate = _clk_ssi_ext2_get_rate,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+};
+
+static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ if (parent == &pll1_sw_clk || parent == &pll2_sw_clk ||
+ parent == &pll3_sw_clk) {
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ NULL);
+ reg &= ~MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET;
+ reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK;
+ reg |= 0 << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET;
+ /* divider setting */
+ } else {
+ mux = _get_mux(parent, &ssi1_clk[0], &ssi2_clk[0], &ckih_clk,
+ &ckih2_clk);
+ reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK;
+ reg |= (mux + 1) << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET;
+ /* divider setting */
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ /* set podf = 0 */
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ reg &= ~MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK;
+ __raw_writel(reg, MXC_CCM_CS1CDR);
+
+ return 0;
+}
+
+static unsigned long _clk_esai_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ if (clk->parent == &pll1_sw_clk || clk->parent == &pll2_sw_clk ||
+ clk->parent == &pll3_sw_clk) {
+ pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK) >>
+ MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >>
+ MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (pred * podf);
+ } else {
+ podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >>
+ MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / podf;
+ }
+}
+
+static struct clk esai_clk[] = {
+ {
+ __INIT_CLK_DEBUG(esai_clk_0)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_esai_set_parent,
+ .get_rate = _clk_esai_get_rate,
+ .secondary = &esai_clk[1],
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(esai_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk iim_clk = {
+ __INIT_CLK_DEBUG(iim_clk)
+ .parent = &ipg_clk,
+ .secondary = &aips_tz2_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk tmax1_clk = {
+ __INIT_CLK_DEBUG(tmax1_clk)
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .disable = _clk_disable,
+ };
+
+static struct clk tmax2_clk = {
+ __INIT_CLK_DEBUG(tmax2_clk)
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk tmax3_clk = {
+ __INIT_CLK_DEBUG(tmax3_clk)
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_usboh3_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk usboh3_clk[] = {
+ {
+ __INIT_CLK_DEBUG(usboh3_clk_0)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_usboh3_set_parent,
+ .get_rate = _clk_usboh3_get_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &usboh3_clk[1],
+ .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(usboh3_clk_1)
+ .parent = &tmax2_clk,
+#if defined(CONFIG_USB_STATIC_IRAM) \
+ || defined(CONFIG_USB_STATIC_IRAM_PPH)
+ .secondary = &emi_intr_clk[0],
+#else
+ .secondary = &emi_fast_clk,
+#endif
+ },
+};
+
+static struct clk usb_ahb_clk = {
+ __INIT_CLK_DEBUG(usb_ahb_clk)
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_usb_phy_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+ u32 div = 1;
+
+ if (clk->parent == &pll3_sw_clk) {
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ prediv = ((reg & MXC_CCM_CDCDR_USB_PHY_PRED_MASK) >>
+ MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CDCDR_USB_PHY_PODF_MASK) >>
+ MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET) + 1;
+
+ div = (prediv * podf);
+ }
+
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &osc_clk)
+ reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ else if (parent == &pll3_sw_clk)
+ reg |= MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ else
+ BUG();
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+ return 0;
+}
+
+static struct clk usb_phy_clk[] = {
+ {
+ __INIT_CLK_DEBUG(usb_phy_clk_0)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .secondary = &tmax3_clk,
+ .set_parent = _clk_usb_phy_set_parent,
+ .get_rate = _clk_usb_phy_get_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(usb_phy_clk_1)
+ .id = 1,
+ .parent = &pll3_sw_clk,
+ .secondary = &tmax3_clk,
+ .set_parent = _clk_usb_phy_set_parent,
+ .get_rate = _clk_usb_phy_get_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .disable = _clk_disable,
+ }
+};
+
+static struct clk esdhc_dep_clks = {
+ __INIT_CLK_DEBUG(esdhc_dep_clks)
+ .parent = &spba_clk,
+ .secondary = &emi_fast_clk,
+};
+
+static unsigned long _clk_esdhc1_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) &
+ ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+
+static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set sdhc1 clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR1) &
+ ~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK |
+ MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+
+ return 0;
+}
+
+static struct clk esdhc1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(esdhc1_clk_0)
+ .id = 0,
+ .parent = &pll2_sw_clk,
+ .set_parent = _clk_esdhc1_set_parent,
+ .get_rate = _clk_esdhc1_get_rate,
+ .set_rate = _clk_sdhc1_set_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &esdhc1_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .secondary = &esdhc1_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc1_clk_2)
+ .id = 0,
+ .parent = &tmax3_clk,
+ .secondary = &esdhc_dep_clks,
+ },
+
+};
+
+static unsigned long _clk_esdhc2_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ if (cpu_is_mx51()) {
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+ }
+ return clk_get_rate(clk->parent);
+}
+
+static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ if (cpu_is_mx51()) {
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) &
+ ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
+ } else { /* MX53 */
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk[0])
+ reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
+ else if (parent == &esdhc3_clk[0])
+ reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
+ else
+ BUG();
+ }
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+ return 0;
+}
+
+static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if (cpu_is_mx51()) {
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set sdhc1 clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR1) &
+ ~(MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK |
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK);
+ reg |= (post - 1) <<
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET;
+ reg |= (pre - 1) <<
+ MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+ }
+ return 0;
+}
+
+static struct clk esdhc2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(esdhc2_clk_0)
+ .id = 1,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_esdhc2_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &esdhc2_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+ .secondary = &esdhc2_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc2_clk_2)
+ .id = 0,
+ .parent = &tmax2_clk,
+ .secondary = &esdhc_dep_clks,
+ },
+};
+
+static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ if (cpu_is_mx51()) {
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk[0])
+ reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51;
+ else if (parent == &esdhc2_clk[0])
+ reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51;
+ else
+ BUG();
+ } else { /* MX53 */
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR1) &
+ ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static unsigned long _clk_esdhc3_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if (cpu_is_mx53()) {
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set sdhc1 clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR1) &
+ ~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK |
+ MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+ }
+ return 0;
+}
+
+
+static struct clk esdhc3_clk[] = {
+ {
+ __INIT_CLK_DEBUG(esdhc3_clk_0)
+ .id = 2,
+ .parent = &esdhc1_clk[0],
+ .set_parent = _clk_esdhc3_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &esdhc3_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc3_clk_1)
+ .id = 2,
+ .parent = &ipg_clk,
+ .secondary = &esdhc3_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc3_clk_2)
+ .id = 0,
+ .parent = &ahb_max_clk,
+ .secondary = &esdhc_dep_clks,
+ },
+};
+
+static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+ if (cpu_is_mx51()) {
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk[0])
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc2_clk[0])
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ BUG();
+ } else {/*MX53 */
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ if (parent == &esdhc1_clk[0])
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else if (parent == &esdhc3_clk[0])
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ else
+ BUG();
+ }
+
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk esdhc4_clk[] = {
+ {
+ __INIT_CLK_DEBUG(esdhc4_clk_0)
+ .id = 3,
+ .parent = &esdhc1_clk[0],
+ .set_parent = _clk_esdhc4_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &esdhc4_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc4_clk_1)
+ .id = 3,
+ .parent = &ipg_clk,
+ .secondary = &esdhc4_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR3,
+ .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(esdhc4_clk_2)
+ .id = 0,
+ .parent = &tmax3_clk,
+ .secondary = &esdhc_dep_clks,
+ },
+};
+
+static struct clk sata_clk = {
+ __INIT_CLK_DEBUG(sata_clk)
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk ieee_1588_clk = {
+ __INIT_CLK_DEBUG(ieee_1588_clk)
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk mlb_clk[] = {
+ {
+ __INIT_CLK_DEBUG(mlb_clk_0)
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &mlb_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(mlb_clk_1)
+ .parent = &emi_fast_clk,
+ .secondary = &emi_intr_clk[1],
+ },
+};
+
+static int _can_root_clk_set(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &ipg_clk, &ckih_clk, &ckih2_clk, &lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static struct clk can1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(can1_clk_0)
+ .id = 0,
+ .parent = &lp_apm_clk,
+ .set_parent = _can_root_clk_set,
+ .enable = _clk_enable,
+ .secondary = &can1_clk[1],
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(can1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk can2_clk[] = {
+ {
+ __INIT_CLK_DEBUG(can2_clk_0)
+ .id = 1,
+ .parent = &lp_apm_clk,
+ .set_parent = _can_root_clk_set,
+ .enable = _clk_enable,
+ .secondary = &can2_clk[1],
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(can2_clk_1)
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static int _clk_sim_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, NULL);
+ reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_sim_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ pred = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / (pred * podf);
+}
+
+static unsigned long _clk_sim_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static int _clk_sim_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set SIM clock divider */
+ reg = __raw_readl(MXC_CCM_CSCDR2) &
+ ~(MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK |
+ MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR2);
+
+ return 0;
+
+}
+
+static struct clk sim_clk[] = {
+ {
+ __INIT_CLK_DEBUG(sim_clk_0)
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_sim_set_parent,
+ .secondary = &sim_clk[1],
+ .get_rate = _clk_sim_get_rate,
+ .round_rate = _clk_sim_round_rate,
+ .set_rate = _clk_sim_set_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(sim_clk_1)
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static unsigned long _clk_nfc_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
+ MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long _clk_nfc_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ /*
+ * Compute the divider we'd have to use to reach the target rate.
+ */
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (parent_rate / div > MAX_NFC_CLK)
+ div++;
+
+ /*
+ * The divider for this clock is 3 bits wide, so we can't possibly
+ * divide the parent by more than eight.
+ */
+
+ if (div > 8)
+ return -EINVAL;
+
+ return parent_rate / div;
+
+}
+
+static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate) || (div > 8))
+ return -EINVAL;
+
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.enable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.enable(&emi_slow_clk);
+
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) &
+ MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
+ getnstimeofday(&curtime);
+ if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+ panic("_clk_nfc_set_rate failed\n");
+ }
+ if (emi_fast_clk.usecount == 0)
+ emi_fast_clk.disable(&emi_fast_clk);
+ if (emi_slow_clk.usecount == 0)
+ emi_slow_clk.disable(&emi_slow_clk);
+
+ return 0;
+}
+
+static struct clk emi_enfc_clk = {
+ __INIT_CLK_DEBUG(emi_enfc_clk)
+ .parent = &emi_slow_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
+ .disable = _clk_disable_inwait,
+ .get_rate = _clk_nfc_get_rate,
+ .round_rate = _clk_nfc_round_rate,
+ .set_rate = _clk_nfc_set_rate,
+};
+
+static int _clk_spdif_xtal_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ mux = _get_mux(parent, &osc_clk, &ckih_clk, &ckih2_clk, NULL);
+ reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCMR1);
+
+ return 0;
+}
+
+static struct clk spdif_xtal_clk = {
+ __INIT_CLK_DEBUG(spdif_xtal_clk)
+ .parent = &osc_clk,
+ .set_parent = _clk_spdif_xtal_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .disable = _clk_disable,
+};
+
+static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ reg |= MXC_CCM_CSCMR2_SPDIF0_COM;
+ if (parent != &ssi1_clk[0]) {
+ reg &= ~MXC_CCM_CSCMR2_SPDIF0_COM;
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &spdif_xtal_clk);
+ reg = (reg & ~MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET);
+ }
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_spdif0_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+ u32 div = 1;
+
+ if (clk->parent != &ssi1_clk[0]) {
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) >>
+ MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) >>
+ MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
+ div = (pred * podf);
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk spdif0_clk[] = {
+ {
+ __INIT_CLK_DEBUG(spdif0_clk_0)
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_spdif0_set_parent,
+ .get_rate = _clk_spdif0_get_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(spdif0_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ reg |= MXC_CCM_CSCMR2_SPDIF1_COM;
+ if (parent != &ssi2_clk[0]) {
+ reg &= ~MXC_CCM_CSCMR2_SPDIF1_COM;
+ mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+ &spdif_xtal_clk);
+ reg = (reg & ~MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET);
+ }
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_spdif1_get_rate(struct clk *clk)
+{
+ u32 reg, pred, podf;
+ u32 div = 1;
+
+ if (clk->parent != &ssi2_clk[0]) {
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK) >>
+ MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK) >>
+ MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
+ div = (pred * podf);
+ }
+ return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk spdif1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(spdif1_clk_0)
+ .id = 1,
+ .parent = &pll3_sw_clk,
+ .set_parent = _clk_spdif1_set_parent,
+ .get_rate = _clk_spdif1_get_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(spdif1_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, reg2, mux;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ reg2 = __raw_readl(MXC_CCM_CBCDR);
+ if (cpu_is_mx51()) {
+ clk->parent = &ddr_hf_clk;
+ mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk);
+ } else {
+ clk->parent = &axi_a_clk;
+ mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, NULL);
+ }
+ if (mux < 4) {
+ reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+ if (cpu_is_mx51())
+ reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL);
+ } else {
+ reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) |
+ (MXC_CCM_CBCDR_DDR_HF_SEL);
+ }
+ if (cpu_is_mx51()) {
+ __raw_writel(reg2, MXC_CCM_CBCDR);
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) &
+ MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){
+ getnstimeofday(&curtime);
+ if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+ panic("_clk_ddr_set_parent failed\n");
+ }
+ }
+ return 0;
+}
+
+static struct clk ddr_clk = {
+ __INIT_CLK_DEBUG(ddr_clk)
+ .parent = &axi_b_clk,
+ .set_parent = _clk_ddr_set_parent,
+};
+
+static int _clk_arm_axi_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+ reg = (reg & ~MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+static struct clk arm_axi_clk = {
+ __INIT_CLK_DEBUG(arm_axi_clk)
+ .parent = &axi_a_clk,
+ .set_parent = _clk_arm_axi_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR0,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+};
+
+static int _clk_vpu_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+ reg = (reg & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+static struct clk vpu_clk[] = {
+ {
+ __INIT_CLK_DEBUG(vpu_clk_0)
+ .set_parent = _clk_vpu_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &vpu_clk[1],
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(vpu_clk_1)
+ .set_parent = _clk_vpu_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &vpu_clk[2],
+ },
+ {
+ __INIT_CLK_DEBUG(vpu_clk_2)
+ .parent = &emi_fast_clk,
+ }
+};
+
+static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ mux = _get_mux(parent, &ckil_clk, &osc_clk, NULL, NULL);
+ reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ return 0;
+}
+
+static struct clk lpsr_clk = {
+ __INIT_CLK_DEBUG(lpsr_clk)
+ .parent = &ckil_clk,
+ .set_parent = _clk_lpsr_set_parent,
+};
+
+static unsigned long _clk_pgc_get_rate(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET;
+ div = 1 >> div;
+ return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk pgc_clk = {
+ __INIT_CLK_DEBUG(pgc_clk)
+ .parent = &ipg_clk,
+ .get_rate = _clk_pgc_get_rate,
+};
+
+static unsigned long _clk_usb_get_rate(struct clk *clk)
+{
+ return 60000000;
+}
+
+/*usb OTG clock */
+static struct clk usb_clk = {
+ __INIT_CLK_DEBUG(usb_clk)
+ .get_rate = _clk_usb_get_rate,
+};
+
+static struct clk usb_utmi_clk = {
+ __INIT_CLK_DEBUG(usb_utmi_clk)
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CSCMR1,
+ .enable_shift = MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+ __INIT_CLK_DEBUG(rtc_clk)
+ .parent = &ckil_clk,
+ .secondary = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk ata_clk = {
+ __INIT_CLK_DEBUG(ata_clk)
+ .parent = &ipg_clk,
+ .secondary = &spba_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static struct clk owire_clk = {
+ __INIT_CLK_DEBUG(owire_clk)
+ .parent = &ipg_perclk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+ .disable = _clk_disable,
+};
+
+
+static struct clk fec_clk[] = {
+ {
+ __INIT_CLK_DEBUG(fec_clk_0)
+ .parent = &ipg_clk,
+ .secondary = &fec_clk[1],
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(fec_clk_1)
+ .parent = &tmax2_clk,
+ .secondary = &fec_clk[2],
+ },
+ {
+ __INIT_CLK_DEBUG(fec_clk_2)
+ .parent = &aips_tz2_clk,
+ .secondary = &emi_fast_clk,
+ },
+};
+
+static struct clk sahara_clk[] = {
+ {
+ __INIT_CLK_DEBUG(sahara_clk_0)
+ .parent = &ahb_clk,
+ .secondary = &sahara_clk[1],
+ .enable_reg = MXC_CCM_CCGR4,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(sahara_clk_1)
+ .parent = &tmax1_clk,
+ .secondary = &emi_fast_clk,
+ }
+};
+
+static struct clk scc_clk[] = {
+ {
+ __INIT_CLK_DEBUG(scc_clk_0)
+ .parent = &ahb_clk,
+ .secondary = &scc_clk[1],
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(scc_clk_1)
+ .parent = &tmax1_clk,
+ .secondary = &emi_fast_clk,
+ }
+};
+
+
+static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+ reg = (reg & ~MXC_CCM_CBCMR_GPU_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+
+static struct clk garb_clk = {
+ __INIT_CLK_DEBUG(garb_clk)
+ .parent = &axi_a_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk gpu3d_clk = {
+ __INIT_CLK_DEBUG(gpu3d_clk)
+ .parent = &axi_a_clk,
+ .set_parent = _clk_gpu3d_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ .secondary = &garb_clk,
+};
+
+static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg, mux;
+
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk);
+ reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
+ (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCMR);
+
+ return 0;
+}
+
+static struct clk gpu2d_clk = {
+ __INIT_CLK_DEBUG(gpu2d_clk)
+ .parent = &axi_a_clk,
+ .set_parent = _clk_gpu2d_set_parent,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+ .disable = _clk_disable,
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+};
+
+static unsigned long cko1_get_rate(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCOSR);
+ reg &= MXC_CCM_CCOSR_CKOL_DIV_MASK;
+ reg = reg >> MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
+ return clk_get_rate(clk->parent) / (reg + 1);
+}
+
+static int cko1_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCOSR);
+ reg |= MXC_CCM_CCOSR_CKOL_EN;
+ __raw_writel(reg, MXC_CCM_CCOSR);
+ return 0;
+}
+
+static void cko1_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCOSR);
+ reg &= ~MXC_CCM_CCOSR_CKOL_EN;
+ __raw_writel(reg, MXC_CCM_CCOSR);
+}
+
+static int cko1_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = (parent_rate/rate - 1) & 0x7;
+ reg = __raw_readl(MXC_CCM_CCOSR);
+ reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
+ reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
+ __raw_writel(reg, MXC_CCM_CCOSR);
+ return 0;
+}
+
+static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 div;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ div = div < 1 ? 1 : div;
+ div = div > 8 ? 8 : div;
+ return parent_rate / div;
+}
+
+static int cko1_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 sel, reg;
+
+ if (parent == &cpu_clk)
+ sel = 0;
+ else if (parent == &pll1_sw_clk)
+ sel = 1;
+ else if (parent == &pll2_sw_clk)
+ sel = 2;
+ else if (parent == &pll3_sw_clk)
+ sel = 3;
+ else if (parent == &emi_slow_clk)
+ sel = 4;
+ else if (parent == &pll4_sw_clk)
+ sel = 5;
+ else if (parent == &emi_enfc_clk)
+ sel = 6;
+ else if (parent == &ipu_di_clk[0])
+ sel = 8;
+ else if (parent == &ahb_clk)
+ sel = 11;
+ else if (parent == &ipg_clk)
+ sel = 12;
+ else if (parent == &ipg_perclk)
+ sel = 13;
+ else if (parent == &ckil_clk)
+ sel = 14;
+ else
+ return -EINVAL;
+
+ reg = __raw_readl(MXC_CCM_CCOSR);
+ reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
+ reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
+ __raw_writel(reg, MXC_CCM_CCOSR);
+ return 0;
+}
+static struct clk cko1_clk = {
+ __INIT_CLK_DEBUG(cko1_clk)
+ .get_rate = cko1_get_rate,
+ .enable = cko1_enable,
+ .disable = cko1_disable,
+ .set_rate = cko1_set_rate,
+ .round_rate = cko1_round_rate,
+ .set_parent = cko1_set_parent,
+};
+static int _clk_asrc_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CSCMR2);
+ if (parent == &pll4_sw_clk)
+ reg |= MXC_CCM_CSCMR2_ASRC_CLK_SEL;
+ else
+ reg &= ~MXC_CCM_CSCMR2_ASRC_CLK_SEL;
+ __raw_writel(reg, MXC_CCM_CSCMR2);
+
+ return 0;
+}
+
+static unsigned long _clk_asrc_get_rate(struct clk *clk)
+{
+ u32 reg, prediv, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCDR2);
+ prediv = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET) + 1;
+ if (prediv == 1)
+ BUG();
+ podf = ((reg & MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET) + 1;
+
+ return clk_get_rate(clk->parent) / (prediv * podf);
+}
+
+static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if ((parent_rate / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ reg = __raw_readl(MXC_CCM_CSCDR2) &
+ ~(MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK |
+ MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR2);
+
+ return 0;
+}
+
+static unsigned long _clk_asrc_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+ u32 div = parent_rate / rate;
+
+ if (parent_rate % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent_rate / (pre * post);
+}
+
+static struct clk asrc_clk[] = {
+ {
+ __INIT_CLK_DEBUG(asrc_clk_0)
+ .id = 0,
+ .parent = &pll4_sw_clk,
+ .set_parent = _clk_asrc_set_parent,
+ .get_rate = _clk_asrc_get_rate,
+ .set_rate = _clk_asrc_set_rate,
+ .round_rate = _clk_asrc_round_rate,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(asrc_clk_1)
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR7,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk dummy_clk = {
+ .id = 0,
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ }
+
+static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK(NULL, "osc", osc_clk),
+ _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
+ _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
+ _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
+ _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_main_clk),
+ _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
+ _REGISTER_CLOCK(NULL, "pll2", pll2_sw_clk),
+ _REGISTER_CLOCK(NULL, "pll3", pll3_sw_clk),
+ _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk),
+ _REGISTER_CLOCK(NULL, "lp_apm", lp_apm_clk),
+ _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
+ _REGISTER_CLOCK(NULL, "periph_apm_clk", periph_apm_clk),
+ _REGISTER_CLOCK(NULL, "main_bus_clk", main_bus_clk),
+ _REGISTER_CLOCK(NULL, "axi_a_clk", axi_a_clk),
+ _REGISTER_CLOCK(NULL, "axi_b_clk", axi_b_clk),
+ _REGISTER_CLOCK(NULL, "ahb_clk", ahb_clk),
+ _REGISTER_CLOCK(NULL, "ahb_max_clk", ahb_max_clk),
+ _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
+ _REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]),
+ _REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk),
+ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk[0]),
+ _REGISTER_CLOCK(NULL, "ipu1_clk", ipu_clk[0]),
+ _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu_di_clk[0]),
+ _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu_di_clk[1]),
+ _REGISTER_CLOCK(NULL, "csi_mclk1", csi0_clk),
+ _REGISTER_CLOCK(NULL, "csi_mclk2", csi1_clk),
+ _REGISTER_CLOCK(NULL, "tve_clk", tve_clk),
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk[0]),
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk[0]),
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk[0]),
+ _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
+ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
+ _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk[0]),
+ _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk[0]),
+ _REGISTER_CLOCK(NULL, "ssi_lp_apm_clk", ssi_lp_apm_clk),
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk[0]),
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk[0]),
+ _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk[0]),
+ _REGISTER_CLOCK(NULL, "ssi_ext1_clk", ssi_ext1_clk),
+ _REGISTER_CLOCK(NULL, "ssi_ext2_clk", ssi_ext2_clk),
+ _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
+ _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
+ _REGISTER_CLOCK(NULL, "usb_ahb_clk", usb_ahb_clk),
+ _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy_clk[0]),
+ _REGISTER_CLOCK(NULL, "usb_utmi_clk", usb_utmi_clk),
+ _REGISTER_CLOCK(NULL, "usb_clk", usb_clk),
+ _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
+ _REGISTER_CLOCK(NULL, "ddr_clk", ddr_clk),
+ _REGISTER_CLOCK(NULL, "emi_enfc_clk", emi_enfc_clk),
+ _REGISTER_CLOCK(NULL, "emi_fast_clk", emi_fast_clk),
+ _REGISTER_CLOCK(NULL, "emi_intr_clk.0", emi_intr_clk[0]),
+ _REGISTER_CLOCK(NULL, "emi_intr_clk.1", emi_intr_clk[1]),
+ _REGISTER_CLOCK(NULL, "spdif_xtal_clk", spdif_xtal_clk),
+ _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
+ _REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]),
+ _REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk),
+ _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk),
+ _REGISTER_CLOCK("pata_fsl", NULL, ata_clk),
+ _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
+ _REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]),
+ _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk),
+ _REGISTER_CLOCK(NULL, "garb_clk", garb_clk),
+ _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk),
+ _REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]),
+ _REGISTER_CLOCK(NULL, "cko1", cko1_clk),
+ _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
+ _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
+};
+
+static struct clk_lookup mx51_lookups[] = {
+ _REGISTER_CLOCK("mxc_i2c_hs.3", NULL, hsi2c_serial_clk),
+ _REGISTER_CLOCK("mxc_sim.0", NULL, sim_clk[0]),
+ _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif1_clk[0]),
+ _REGISTER_CLOCK(NULL, "mipi_hsp_clk", mipi_hsp_clk),
+ _REGISTER_CLOCK(NULL, "ddr_hf_clk", ddr_hf_clk),
+ _REGISTER_CLOCK("imx51-ecspi.0", NULL, cspi1_clk[0]),
+ _REGISTER_CLOCK("imx51-ecspi.1", NULL, cspi2_clk[0]),
+ _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi3_clk),
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk[0]),
+ _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk[0]),
+ _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
+ _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+};
+
+static struct clk_lookup mx53_lookups[] = {
+ _REGISTER_CLOCK(NULL, "pll4", pll4_sw_clk),
+ _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk[0]),
+ _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk[0]),
+ _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
+ _REGISTER_CLOCK(NULL, "usb_phy2_clk", usb_phy_clk[1]),
+ _REGISTER_CLOCK(NULL, "ocram_clk", ocram_clk),
+ _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk),
+ _REGISTER_CLOCK(NULL, "ieee_1588_clk", ieee_1588_clk),
+ _REGISTER_CLOCK(NULL, "ieee_rtc_clk", ieee_rtc_clk),
+ _REGISTER_CLOCK("mxc_mlb.0", NULL, mlb_clk[0]),
+ _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
+ _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
+ _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di_clk[0]),
+ _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di_clk[1]),
+ _REGISTER_CLOCK(NULL, "esai_clk", esai_clk[0]),
+ _REGISTER_CLOCK(NULL, "esai_ipg_clk", esai_clk[1]),
+ _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[1]),
+ _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[0]),
+ _REGISTER_CLOCK("imx53-ecspi.0", NULL, cspi1_clk[0]),
+ _REGISTER_CLOCK("imx53-ecspi.1", NULL, cspi2_clk[0]),
+ _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi3_clk),
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_clk[0]),
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_clk[0]),
+ _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk[0]),
+ _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
+ _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+};
+
+static void clk_tree_init(void)
+{
+ u32 reg, dp_ctl;
+
+ ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
+
+ /*
+ *Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
+ * 8MHz, its derived from lp_apm.
+ */
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
+ reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
+ reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
+ reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ /* set pll1_main_clk parent */
+ pll1_main_clk.parent = &osc_clk;
+
+ /* set pll2_sw_clk parent */
+ pll2_sw_clk.parent = &osc_clk;
+
+ /* set pll3_clk parent */
+ pll3_sw_clk.parent = &osc_clk;
+
+ if (cpu_is_mx51()) {
+ dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+ pll1_main_clk.parent = &fpm_clk;
+
+ dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL);
+ if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+ pll2_sw_clk.parent = &fpm_clk;
+
+ dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL);
+ if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+ pll3_sw_clk.parent = &fpm_clk;
+ } else {
+ /* set pll4_clk parent */
+ pll4_sw_clk.parent = &osc_clk;
+ }
+
+ /* set emi_slow_clk parent */
+ emi_slow_clk.parent = &main_bus_clk;
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ if ((reg & MXC_CCM_CBCDR_EMI_CLK_SEL) != 0)
+ emi_slow_clk.parent = &ahb_clk;
+
+ /* set ipg_perclk parent */
+ ipg_perclk.parent = &lp_apm_clk;
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ if ((reg & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) != 0) {
+ ipg_perclk.parent = &ipg_clk;
+ } else {
+ if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0)
+ ipg_perclk.parent = &main_bus_clk;
+ }
+}
+
+
+int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
+{
+ __iomem void *base;
+ struct clk *tclk;
+ int i = 0, j = 0, reg;
+ int op_cnt = 0;
+ u32 pll1_rate;
+
+ pll1_base = MX51_DPLL1_BASE;
+ pll2_base = MX51_DPLL2_BASE;
+ pll3_base = MX51_DPLL3_BASE;
+
+ /* Turn off all possible clocks */
+ if (mxc_jtag_enabled) {
+ __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG1_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG2_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG3_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG4_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG12_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG13_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+ } else {
+ __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG1_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG2_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG3_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG12_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG13_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+ }
+ __raw_writel(0, MXC_CCM_CCGR1);
+ __raw_writel(0, MXC_CCM_CCGR2);
+ __raw_writel(0, MXC_CCM_CCGR3);
+ __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4);
+
+ __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET |
+ 1 << MXC_CCM_CCGR5_CG6_1_OFFSET |
+ 1 << MXC_CCM_CCGR5_CG6_2_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG7_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG10_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5);
+
+ __raw_writel(1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR6);
+
+ external_low_reference = ckil;
+ external_high_reference = ckih1;
+ ckih2_reference = ckih2;
+ oscillator_reference = osc;
+
+ /* Fix up clocks unique to MX51. */
+ esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate;
+ esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate;
+
+ clk_tree_init();
+
+ for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+ clkdev_add(&lookups[i]);
+ clk_debug_register(lookups[i].clk);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) {
+ clkdev_add(&mx51_lookups[i]);
+ clk_debug_register(mx51_lookups[i].clk);
+ }
+
+ max_axi_a_clk = MAX_AXI_A_CLK_MX51;
+ max_axi_b_clk = MAX_AXI_B_CLK_MX51;
+ max_ahb_clk = MAX_AHB_CLK_MX51;
+ max_emi_slow_clk = MAX_AHB_CLK_MX51;
+
+ /* set DDR clock parent */
+ reg = 0;
+ if (mx51_revision() >= IMX_CHIP_REVISION_2_0) {
+ reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL;
+ reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET;
+
+ if (reg)
+ tclk = &ddr_hf_clk;
+ }
+ if (reg == 0) {
+ reg = __raw_readl(MXC_CCM_CBCMR) &
+ MXC_CCM_CBCMR_DDR_CLK_SEL_MASK;
+ reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+
+ if (reg == 0) {
+ tclk = &axi_a_clk;
+ } else if (reg == 1) {
+ tclk = &axi_b_clk;
+ } else if (reg == 2) {
+ tclk = &emi_slow_clk;
+ } else {
+ tclk = &ahb_clk;
+ }
+ }
+ clk_set_parent(&ddr_clk, tclk);
+
+ /*Setup the LPM bypass bits */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51
+ | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+
+ /* Disable the handshake with HSC block as its not
+ * initialised right now.
+ */
+ reg = __raw_readl(MXC_CCM_CCDR);
+ reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+ __raw_writel(reg, MXC_CCM_CCDR);
+
+ clk_enable(&cpu_clk);
+
+ /* Set SDHC parents to be PLL2 */
+ clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk);
+ clk_set_parent(&esdhc2_clk[0], &pll2_sw_clk);
+
+ /* set SDHC root clock as 166.25MHZ*/
+ clk_set_rate(&esdhc1_clk[0], 166250000);
+ clk_set_rate(&esdhc2_clk[0], 166250000);
+
+ /* Initialise the parents to be axi_b, parents are set to
+ * axi_a when the clocks are enabled.
+ */
+ clk_set_parent(&vpu_clk[0], &axi_a_clk);
+ clk_set_parent(&vpu_clk[1], &axi_a_clk);
+ clk_set_parent(&gpu3d_clk, &axi_a_clk);
+ clk_set_parent(&gpu2d_clk, &axi_a_clk);
+
+ /* move cspi to 24MHz */
+ clk_set_parent(&cspi_main_clk, &lp_apm_clk);
+ clk_set_rate(&cspi_main_clk, 12000000);
+ /*move the spdif0 to spdif_xtal_ckl */
+ clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk);
+ /*set the SPDIF dividers to 1 */
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+
+ /* move the spdif1 to 24MHz */
+ clk_set_parent(&spdif1_clk[0], &spdif_xtal_clk);
+ /* set the spdif1 dividers to 1 */
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+
+ /* Move SSI clocks to SSI_LP_APM clock */
+ clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
+
+ clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk);
+ /* set the SSI dividers to divide by 2 */
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK;
+ reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CS1CDR);
+
+ clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CS2CDR);
+ reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK;
+ reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CS2CDR);
+
+ /*
+ * SSI3 has no clock divide register,
+ * we always set SSI3 parent clock to SSI1 and freq same to SSI1
+ */
+ clk_set_parent(&ssi3_clk[0], &ssi1_clk[0]);
+
+ /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
+ clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
+ clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
+
+ /* move usb_phy_clk to 24MHz */
+ clk_set_parent(&usb_phy_clk[0], &osc_clk);
+
+ /* set usboh3_clk to pll2 */
+ clk_set_parent(&usboh3_clk[0], &pll2_sw_clk);
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+ reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+ reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+
+ mx51_cpu_op_init();
+ /* Set the current working point. */
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+ /* Update the cpu working point table based on the PLL1 freq
+ * at boot time
+ */
+ pll1_rate = clk_get_rate(&pll1_main_clk);
+ if (pll1_rate <= cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+ op_cnt = 1;
+ else if (pll1_rate <= cpu_op_tbl[1].cpu_rate &&
+ pll1_rate > cpu_op_tbl[2].cpu_rate)
+ op_cnt = cpu_op_nr - 1;
+ else
+ op_cnt = cpu_op_nr;
+
+ cpu_op_tbl[0].cpu_rate = pll1_rate;
+
+ if (op_cnt == 1) {
+ cpu_op_tbl[0] = cpu_op_tbl[cpu_op_nr - 1];
+ memset(&cpu_op_tbl[cpu_op_nr - 1], 0, sizeof(struct cpu_op));
+ memset(&cpu_op_tbl[cpu_op_nr - 2], 0, sizeof(struct cpu_op));
+ } else if (op_cnt < cpu_op_nr) {
+ for (i = 0; i < op_cnt; i++)
+ cpu_op_tbl[i] = cpu_op_tbl[i+1];
+ memset(&cpu_op_tbl[i], 0, sizeof(struct cpu_op));
+ }
+
+ if (op_cnt < cpu_op_nr) {
+ set_num_cpu_op(op_cnt);
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+ }
+
+ pll1_rate = clk_get_rate(&pll1_main_clk);
+ for (j = 0; j < cpu_op_nr; j++) {
+ if ((ddr_clk.parent == &ddr_hf_clk)) {
+ /* Change the CPU podf divider based on the boot up
+ * pll1 rate.
+ */
+ cpu_op_tbl[j].cpu_podf =
+ (pll1_rate / cpu_op_tbl[j].cpu_rate)
+ - 1;
+ if (pll1_rate / (cpu_op_tbl[j].cpu_podf + 1) >
+ cpu_op_tbl[j].cpu_rate) {
+ cpu_op_tbl[j].cpu_podf++;
+ cpu_op_tbl[j].cpu_rate =
+ pll1_rate /
+ (1000 * (cpu_op_tbl[j].cpu_podf + 1));
+ cpu_op_tbl[j].cpu_rate *= 1000;
+ }
+ if (pll1_rate / (cpu_op_tbl[j].cpu_podf + 1) <
+ cpu_op_tbl[j].cpu_rate) {
+ cpu_op_tbl[j].cpu_rate = pll1_rate;
+ }
+ }
+ cpu_op_tbl[j].pll_rate = pll1_rate;
+ }
+ /* Set the current working point. */
+ for (i = 0; i < cpu_op_nr; i++) {
+ if (clk_get_rate(&cpu_clk) == cpu_op_tbl[i].cpu_rate) {
+ cpu_curr_op = i;
+ break;
+ }
+ }
+ if (i > cpu_op_nr)
+ BUG();
+
+ clk_set_parent(&arm_axi_clk, &axi_a_clk);
+ clk_set_parent(&ipu_clk[0], &axi_b_clk);
+
+ if (uart_at_24) {
+ /* Move UART to run from lp_apm */
+ clk_set_parent(&uart_main_clk, &lp_apm_clk);
+
+ /* Set the UART dividers to divide, so the UART_CLK is 24MHz. */
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
+ reg |= (0 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
+ (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+ } else {
+ clk_set_parent(&uart_main_clk, &pll2_sw_clk);
+
+ /* Set the UART dividers to divide, so the UART_CLK is 66.5MHz. */
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK;
+ reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) |
+ (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+ }
+
+ clk_set_parent(&emi_slow_clk, &ahb_clk);
+ clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 130000000));
+
+ /* Change the NFC clock rate to be 1:4 ratio with emi clock. */
+ clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk,
+ (clk_get_rate(&emi_slow_clk))/4));
+
+ /* System timer */
+ mxc_timer_init(&gpt_clk[0], MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+ MX51_INT_GPT);
+
+ return 0;
+}
+
+int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
+{
+ __iomem void *base;
+ struct clk *tclk;
+ int i = 0, j = 0, reg;
+ u32 pll1_rate;
+
+ pll1_base = MX53_DPLL1_BASE;
+ pll2_base = MX53_DPLL2_BASE;
+ pll3_base = MX53_DPLL3_BASE;
+ pll4_base = MX53_DPLL4_BASE;
+
+ /* Turn off all possible clocks */
+ if (mxc_jtag_enabled) {
+ __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG1_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG2_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG3_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG4_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG12_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG13_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+ } else {
+ __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG1_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG3_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG12_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG13_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG14_OFFSET, MXC_CCM_CCGR0);
+ }
+
+ __raw_writel(0, MXC_CCM_CCGR1);
+ __raw_writel(0, MXC_CCM_CCGR2);
+ __raw_writel(0, MXC_CCM_CCGR3);
+ __raw_writel(1 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR4);
+
+ __raw_writel(1 << MXC_CCM_CCGRx_CG2_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG6_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG7_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG8_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG9_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR5);
+
+ __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG1_OFFSET |
+ 1 << MXC_CCM_CCGRx_CG4_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG12_OFFSET |
+ 3 << MXC_CCM_CCGRx_CG13_OFFSET , MXC_CCM_CCGR6);
+
+ __raw_writel(0, MXC_CCM_CCGR7);
+
+ external_low_reference = ckil;
+ external_high_reference = ckih1;
+ ckih2_reference = ckih2;
+ oscillator_reference = osc;
+
+ usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4;
+ usb_phy_clk[0].enable_shift = MXC_CCM_CCGRx_CG5_OFFSET;
+
+ ipumux1_clk.enable_reg = MXC_CCM_CCGR5;
+ ipumux1_clk.enable_shift = MXC_CCM_CCGRx_CG6_OFFSET;
+ ipumux2_clk.enable_reg = MXC_CCM_CCGR6;
+ ipumux2_clk.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET;
+
+ esdhc3_clk[0].get_rate = _clk_esdhc3_get_rate;
+ esdhc3_clk[0].set_rate = _clk_sdhc3_set_rate;
+
+ vpu_clk[2].secondary = &emi_intr_clk[0];
+
+#if defined(CONFIG_USB_STATIC_IRAM) \
+ || defined(CONFIG_USB_STATIC_IRAM_PPH)
+ usboh3_clk[1].secondary = &emi_intr_clk[1];
+#endif
+#ifdef CONFIG_SND_MXC_SOC_IRAM
+ ssi2_clk[2].secondary = &emi_intr_clk[1];
+ ssi1_clk[2].secondary = &emi_intr_clk[1];
+#endif
+#ifdef CONFIG_SDMA_IRAM
+ sdma_clk[1].secondary = &emi_intr_clk[1];
+#endif
+
+ clk_tree_init();
+
+ for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+ clkdev_add(&lookups[i]);
+ clk_debug_register(lookups[i].clk);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) {
+ clkdev_add(&mx53_lookups[i]);
+ clk_debug_register(mx53_lookups[i].clk);
+ }
+
+ clk_set_parent(&esai_clk[0], &ckih_clk);
+
+ ldb_di_clk[0].parent = ldb_di_clk[1].parent =
+ tve_clk.parent = &pll4_sw_clk;
+
+ max_axi_a_clk = MAX_AXI_A_CLK_MX53;
+ max_axi_b_clk = MAX_AXI_B_CLK_MX53;
+ max_ahb_clk = MAX_AHB_CLK_MX53;
+ max_emi_slow_clk = MAX_AHB_CLK_MX53;
+
+
+ /* set DDR clock parent */
+ reg = __raw_readl(MXC_CCM_CBCMR) &
+ MXC_CCM_CBCMR_DDR_CLK_SEL_MASK;
+ reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+ if (reg == 0) {
+ tclk = &axi_a_clk;
+ } else if (reg == 1) {
+ tclk = &axi_b_clk;
+ } else if (reg == 2) {
+ tclk = &emi_slow_clk;
+ } else {
+ tclk = &ahb_clk;
+ }
+ clk_set_parent(&ddr_clk, tclk);
+
+ clk_set_parent(&esdhc1_clk[2], &tmax2_clk);
+ clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]);
+ clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk);
+
+#if 0
+ /*Setup the LPM bypass bits */
+ reg = __raw_readl(MXC_CCM_CLPCR);
+ reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS
+ | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS;
+ __raw_writel(reg, MXC_CCM_CLPCR);
+#endif
+
+ clk_enable(&cpu_clk);
+
+ clk_enable(&main_bus_clk);
+
+ /* Set AXI_B_CLK to be 200MHz */
+ clk_set_rate(&axi_b_clk, 200000000);
+
+ /* Initialise the parents to be axi_b, parents are set to
+ * axi_a when the clocks are enabled.
+ */
+
+ clk_set_parent(&vpu_clk[0], &axi_b_clk);
+ clk_set_parent(&vpu_clk[1], &axi_b_clk);
+
+ /* move cspi to 24MHz */
+ clk_set_parent(&cspi_main_clk, &lp_apm_clk);
+ clk_set_rate(&cspi_main_clk, 12000000);
+ /*move the spdif0 to spdif_xtal_ckl */
+ clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk);
+ /*set the SPDIF dividers to 1 */
+ reg = __raw_readl(MXC_CCM_CDCDR);
+ reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK;
+ __raw_writel(reg, MXC_CCM_CDCDR);
+
+ /* Move SSI clocks to SSI_LP_APM clock */
+ clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
+
+ clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk);
+ /* set the SSI dividers to divide by 2 */
+ reg = __raw_readl(MXC_CCM_CS1CDR);
+ reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK;
+ reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CS1CDR);
+
+ clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk);
+ reg = __raw_readl(MXC_CCM_CS2CDR);
+ reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK;
+ reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CS2CDR);
+
+ /* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */
+ clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk);
+ clk_set_rate(&ssi_ext1_clk, 24000000);
+ clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
+
+ /* move usb_phy_clk to 24MHz */
+ clk_set_parent(&usb_phy_clk[0], &osc_clk);
+ clk_set_parent(&usb_phy_clk[1], &osc_clk);
+
+ /* set usboh3_clk to pll2 */
+ clk_set_parent(&usboh3_clk[0], &pll2_sw_clk);
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+ reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+ reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR1);
+
+ /* set SDHC root clock as 200MHZ*/
+ clk_set_rate(&esdhc1_clk[0], 200000000);
+ clk_set_rate(&esdhc3_clk[0], 200000000);
+
+ /* Set the 1588 RTC input clocks as 108MHZ */
+ clk_set_parent(&ieee_rtc_clk, &pll3_sw_clk);
+ clk_set_rate(&ieee_rtc_clk, 108000000);
+
+ /* The CPU working point should be set according to part number
+ * information. But part number information is not clear now.
+ * So update the cpu working point table based on the PLL1 freq
+ * at boot time
+ */
+ pll1_rate = clk_get_rate(&pll1_main_clk);
+
+ if (pll1_rate > 1000000000)
+ mx53_set_cpu_part_number(IMX53_CEC_1_2G);
+ else if (pll1_rate > 800000000)
+ mx53_set_cpu_part_number(IMX53_CEC);
+ else
+ mx53_set_cpu_part_number(IMX53_AEC);
+
+ /* Set the current working point. */
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+ for (i = 0; i < cpu_op_nr; i++) {
+ if (clk_get_rate(&cpu_clk) == cpu_op_tbl[i].cpu_rate) {
+ cpu_curr_op = i;
+ break;
+ }
+ }
+ if (i > cpu_op_nr)
+ BUG();
+
+ clk_set_parent(&arm_axi_clk, &axi_b_clk);
+ clk_set_parent(&ipu_clk[0], &axi_b_clk);
+ clk_set_parent(&gpu3d_clk, &axi_b_clk);
+ clk_set_parent(&gpu2d_clk, &axi_b_clk);
+
+ clk_set_parent(&emi_slow_clk, &ahb_clk);
+ clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 133333333));
+
+ clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk,
+ MAX_NFC_CLK));
+
+ /* set the freq of asrc_serial_clk */
+ clk_set_rate(&asrc_clk[0], clk_round_rate(&asrc_clk[0],
+ 1190000));
+ clk_set_parent(&uart_main_clk, &pll2_sw_clk);
+ /* System timer */
+ mxc_timer_init(&gpt_clk[0], MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+ MX53_INT_GPT);
+ return 0;
+}
+
+/*!
+ * Setup cpu clock based on working point.
+ * @param op cpu freq working point
+ * @return 0 on success or error code on failure.
+ */
+static int cpu_clk_set_op(int op)
+{
+ struct cpu_op *p;
+ u32 reg, pll_hfsm;
+ u32 stat;
+ int relock_timeout = 10;
+
+ if (op == cpu_curr_op)
+ return 0;
+
+ p = &cpu_op_tbl[op];
+
+ /*
+ * If DDR clock is sourced from PLL1, we cannot drop PLL1 freq.
+ * Use the ARM_PODF to change the freq of the core, leave the PLL1
+ * freq unchanged. Meanwhile, if pll_rate is same, use the ARM_PODF
+ * to change the freq of core
+ */
+ if ((ddr_clk.parent == &ddr_hf_clk) ||
+ (p->pll_rate == cpu_op_tbl[cpu_curr_op].pll_rate)) {
+ reg = __raw_readl(MXC_CCM_CACRR);
+ reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+ reg |= cpu_op_tbl[op].cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CACRR);
+ cpu_curr_op = op;
+ } else {
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ /* Change the ARM clock to requested frequency */
+ /* First move the ARM clock to step clock which is running
+ * at 24MHz.
+ */
+
+ /* Change the source of pll1_sw_clk to be the step_clk */
+ reg = __raw_readl(MXC_CCM_CCSR);
+ reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+ __raw_writel(reg, MXC_CCM_CCSR);
+
+ /* Stop the PLL */
+ reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ reg &= ~MXC_PLL_DP_CTL_UPEN;
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+
+ reg = __raw_readl(MXC_CCM_CACRR);
+ reg = (reg & ~MXC_CCM_CACRR_ARM_PODF_MASK)
+ | p->cpu_podf;
+ __raw_writel(reg, MXC_CCM_CACRR);
+
+ reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ pll_hfsm = reg & MXC_PLL_DP_CTL_HFSM;
+ /* PDF and MFI */
+ reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET;
+ if (pll_hfsm == 0) {
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_OP);
+ __raw_writel(p->mfd, pll1_base + MXC_PLL_DP_MFD);
+ __raw_writel(p->mfn, pll1_base + MXC_PLL_DP_MFN);
+ } else {
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_HFS_OP);
+ __raw_writel(p->mfd, pll1_base + MXC_PLL_DP_HFS_MFD);
+ __raw_writel(p->mfn, pll1_base + MXC_PLL_DP_HFS_MFN);
+ }
+
+ reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ reg |= MXC_PLL_DP_CTL_UPEN;
+ /* Set the UPEN bits */
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+ /* Forcefully restart the PLL */
+ reg |= MXC_PLL_DP_CTL_RST;
+ __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL);
+
+ /* Wait for the PLL to lock */
+ do {
+ stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL);
+ if (stat & MXC_PLL_DP_CTL_LRF)
+ break;
+ udelay(100);
+ } while (--relock_timeout);
+
+ reg = __raw_readl(MXC_CCM_CCSR);
+ /* Move the PLL1 back to the pll1_main_clk */
+ reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
+ __raw_writel(reg, MXC_CCM_CCSR);
+
+ cpu_curr_op = op;
+ }
+
+#if defined(CONFIG_CPU_FREQ)
+ cpufreq_trig_needed = 1;
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 5e2e7a84386..9d2bddcee09 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -14,12 +14,32 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk.h>
#include <linux/module.h>
#include <mach/hardware.h>
#include <linux/io.h>
+#include <mach/iram.h>
static int mx5_cpu_rev = -1;
+#define CORTEXA8_PLAT_AMC 0x18
+#define SRPG_NEON_PUPSCR 0x284
+#define SRPG_NEON_PDNSCR 0x288
+#define SRPG_ARM_PUPSCR 0x2A4
+#define SRPG_ARM_PDNSCR 0x2A8
+#define SRPG_EMPGC0_PUPSCR 0x2E4
+#define SRPG_EMPGC0_PDNSCR 0x2E8
+#define SRPG_EMPGC1_PUPSCR 0x304
+#define SRPG_EMPGC1_PDNSCR 0x308
+
+void __iomem *arm_plat_base;
+void __iomem *gpc_base;
+void __iomem *ccm_base;
+extern void init_ddr_settings(void);
+
+static int cpu_silicon_rev = -1;
+void (*set_num_cpu_op)(int num);
+
#define IIM_SREV 0x24
#define MX50_HW_ADADIG_DIGPROG 0xB0
@@ -111,6 +131,7 @@ int mx53_revision(void)
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx53_revision);
+#define MX50_HW_ADADIG_DIGPROG 0xB0
static int get_mx50_srev(void)
{
@@ -154,6 +175,24 @@ static int __init post_cpu_init(void)
{
unsigned int reg;
void __iomem *base;
+ struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk");
+
+ if (cpu_is_mx51()) {
+ ccm_base = MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR);
+ gpc_base = MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR);
+ arm_plat_base = MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR);
+ iram_init(MX51_IRAM_BASE_ADDR, MX51_IRAM_SIZE);
+ } else if (cpu_is_mx53()) {
+ ccm_base = MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR);
+ gpc_base = MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR);
+ arm_plat_base = MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR);
+ iram_init(MX53_IRAM_BASE_ADDR, MX53_IRAM_SIZE);
+ } else {
+ ccm_base = MX50_IO_ADDRESS(MX50_CCM_BASE_ADDR);
+ gpc_base = MX50_IO_ADDRESS(MX50_GPC_BASE_ADDR);
+ arm_plat_base = MX50_IO_ADDRESS(MX50_ARM_BASE_ADDR);
+ iram_init(MX50_IRAM_BASE_ADDR, MX50_IRAM_SIZE);
+ }
if (cpu_is_mx51() || cpu_is_mx53()) {
if (cpu_is_mx51())
@@ -180,6 +219,30 @@ static int __init post_cpu_init(void)
reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
__raw_writel(reg, base + 0x50);
}
+ clk_enable(gpcclk);
+
+ /* Setup the number of clock cycles to wait for SRPG
+ * power up and power down requests.
+ */
+ __raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR);
+ __raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR);
+ __raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR);
+ __raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR);
+
+ __raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR);
+ __raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR);
+ __raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR);
+ __raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR);
+
+ clk_disable(gpcclk);
+ clk_put(gpcclk);
+
+ /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
+ reg = 0x8;
+ __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC);
+
+ if (cpu_is_mx50())
+ init_ddr_settings();
return 0;
}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
index 9d34c3d4c02..c721a47a0db 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.c
+++ b/arch/arm/mach-mx5/cpu_op-mx51.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -15,15 +15,55 @@
#include <mach/hardware.h>
#include <linux/kernel.h>
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+static int num_cpu_op;
+
+/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
static struct cpu_op mx51_cpu_op[] = {
{
- .cpu_rate = 160000000,},
+ .pll_rate = 1000000000,
+ .cpu_rate = 1000000000,
+ .pdf = 0,
+ .mfi = 10,
+ .mfd = 11,
+ .mfn = 5,
+ .cpu_podf = 0,
+ .cpu_voltage = 1175000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 800000000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
+ .cpu_podf = 0,
+ .cpu_voltage = 1100000,
+ },
{
- .cpu_rate = 800000000,},
+ .pll_rate = 800000000,
+ .cpu_rate = 166250000,
+ .cpu_podf = 4,
+ .cpu_voltage = 850000,
+ },
};
struct cpu_op *mx51_get_cpu_op(int *op)
{
- *op = ARRAY_SIZE(mx51_cpu_op);
+ *op = num_cpu_op;
return mx51_cpu_op;
}
+
+void mx51_set_num_cpu_op(int num)
+{
+ num_cpu_op = num;
+ return;
+}
+
+void mx51_cpu_op_init()
+{
+ get_cpu_op = mx51_get_cpu_op;
+ set_num_cpu_op = mx51_set_num_cpu_op;
+
+ num_cpu_op = ARRAY_SIZE(mx51_cpu_op);
+}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
index 97477fecb46..03564bd3712 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.h
+++ b/arch/arm/mach-mx5/cpu_op-mx51.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -11,4 +11,5 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-extern struct cpu_op *mx51_get_cpu_op(int *op);
+struct cpu_op *mx51_get_cpu_op(int *op);
+extern void mx51_cpu_op_init(void);
diff --git a/arch/arm/mach-mx5/cpu_op-mx53.c b/arch/arm/mach-mx5/cpu_op-mx53.c
new file mode 100644
index 00000000000..a0d0700548f
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx53.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include "cpu_op-mx53.h"
+
+/*!
+ * @file mach-mx5/cpu_op-mx53.c
+ *
+ * @brief This file contains the information about MX53 CPU working points.
+ *
+ * @ingroup MSL_MX53
+ */
+extern struct cpu_op *(*get_cpu_op)(int *op);
+extern void (*set_num_cpu_op)(int num);
+static int num_cpu_op;
+static struct cpu_op *cpu_op_table;
+
+/* working point for auto*/
+static struct cpu_op cpu_op_aec[] = {
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 800000000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
+ .cpu_podf = 0,
+ .cpu_voltage = 1050000,},
+};
+
+/* working point for consumer 1G*/
+static struct cpu_op cpu_op_ces[] = {
+ {
+ .pll_rate = 1000000000,
+ .cpu_rate = 1000000000,
+ .pdf = 0,
+ .mfi = 10,
+ .mfd = 11,
+ .mfn = 5,
+ .cpu_podf = 0,
+ .cpu_voltage = 1200000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 800000000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
+ .cpu_podf = 0,
+ .cpu_voltage = 1050000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 400000000,
+ .cpu_podf = 1,
+ .cpu_voltage = 950000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 160000000,
+ .cpu_podf = 4,
+ .cpu_voltage = 900000,},
+};
+
+/* working point for consumer 1.2G*/
+static struct cpu_op cpu_op_ces_1_2g[] = {
+ {
+ .pll_rate = 1200000000,
+ .cpu_rate = 1200000000,
+ .pdf = 0,
+ .mfi = 12,
+ .mfd = 1,
+ .mfn = 1,
+ .cpu_podf = 0,
+ .cpu_voltage = 1300000,},
+ {
+ .pll_rate = 1000000000,
+ .cpu_rate = 1000000000,
+ .pdf = 0,
+ .mfi = 10,
+ .mfd = 11,
+ .mfn = 5,
+ .cpu_podf = 0,
+ .cpu_voltage = 1200000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 800000000,
+ .pdf = 0,
+ .mfi = 8,
+ .mfd = 2,
+ .mfn = 1,
+ .cpu_podf = 0,
+ .cpu_voltage = 1050000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 400000000,
+ .cpu_podf = 1,
+ .cpu_voltage = 950000,},
+ {
+ .pll_rate = 800000000,
+ .cpu_rate = 160000000,
+ .cpu_podf = 4,
+ .cpu_voltage = 900000,},
+};
+
+
+struct cpu_op *mx53_get_cpu_op(int *op)
+{
+ *op = num_cpu_op;
+ return cpu_op_table;
+}
+
+void mx53_set_num_cpu_op(int num)
+{
+ num_cpu_op = num;
+ return;
+}
+
+void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num)
+{
+ get_cpu_op = mx53_get_cpu_op;
+ set_num_cpu_op = mx53_set_num_cpu_op;
+
+ switch (part_num) {
+ case IMX53_CEC_1_2G:
+ cpu_op_table = cpu_op_ces_1_2g;
+ num_cpu_op = ARRAY_SIZE(cpu_op_ces_1_2g);
+ break;
+ case IMX53_CEC:
+ cpu_op_table = cpu_op_ces;
+ num_cpu_op = ARRAY_SIZE(cpu_op_ces);
+ break;
+ case IMX53_AEC:
+ default:
+ cpu_op_table = cpu_op_aec;
+ num_cpu_op = ARRAY_SIZE(cpu_op_aec);
+ break;
+ }
+}
+
+
diff --git a/arch/arm/mach-mx5/cpu_op-mx53.h b/arch/arm/mach-mx5/cpu_op-mx53.h
new file mode 100644
index 00000000000..5bd8f4fd73c
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx53.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX53_WP_H__
+#define __ARCH_ARM_MACH_MX53_WP_H__
+#include <linux/types.h>
+
+/*!
+ * @file mach-mx5/cpu_op-mx53.h
+ *
+ * @brief This file contains the information about MX53 CPU working points.
+ *
+ * @ingroup MSL_MX53
+ */
+enum mx53_cpu_part_number {
+ IMX53_AEC, /* automative and infotainment AP */
+ IMX53_CEC, /* Consumer AP, CPU freq is up to 1G */
+ IMX53_CEC_1_2G, /* Consumer AP, CPU freq is up to 1.2GHZ */
+};
+
+void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num);
+
+#endif /*__ARCH_ARM_MACH_MX53_WP_H__ */
+
+
+
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 5e11ba7daee..b28737fb263 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -11,19 +11,21 @@
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+#define MXC_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
+
#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
-#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
-#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
-/*MX53*/
-#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
+
+#define MX50_DPLL1_BASE MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR)
+#define MX50_DPLL2_BASE MX50_IO_ADDRESS(MX50_PLL2_BASE_ADDR)
+#define MX50_DPLL3_BASE MX50_IO_ADDRESS(MX50_PLL3_BASE_ADDR)
+#define MX50_ANATOP_BASE MX50_IO_ADDRESS(MX50_ANATOP_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
@@ -80,43 +82,108 @@
#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+/* Register addresses of apll and pfd*/
+#define MXC_ANADIG_FRAC0 0x10
+#define MXC_ANADIG_FRAC0_SET 0x14
+#define MXC_ANADIG_FRAC0_CLR 0x18
+#define MXC_ANADIG_FRAC1 0x20
+#define MXC_ANADIG_FRAC1_SET 0x24
+#define MXC_ANADIG_FRAC1_CLR 0x28
+#define MXC_ANADIG_MISC 0x60
+#define MXC_ANADIG_MISC_SET 0x64
+#define MXC_ANADIG_MISC_CLR 0x68
+#define MXC_ANADIG_PLLCTRL 0x70
+#define MXC_ANADIG_PLLCTRL_SET 0x74
+#define MXC_ANADIG_PLLCTRL_CLR 0x78
+
+/* apll and pfd Register Bit definitions */
+
+#define MXC_ANADIG_PFD3_CLKGATE (1 << 31)
+#define MXC_ANADIG_PFD3_STABLE (1 << 30)
+#define MXC_ANADIG_PFD3_FRAC_OFFSET 24
+#define MXC_ANADIG_PFD_FRAC_MASK 0x3F
+#define MXC_ANADIG_PFD2_CLKGATE (1 << 23)
+#define MXC_ANADIG_PFD2_STABLE (1 << 22)
+#define MXC_ANADIG_PFD2_FRAC_OFFSET 16
+#define MXC_ANADIG_PFD1_CLKGATE (1 << 15)
+#define MXC_ANADIG_PFD1_STABLE (1 << 14)
+#define MXC_ANADIG_PFD1_FRAC_OFFSET 8
+#define MXC_ANADIG_PFD0_CLKGATE (1 << 7)
+#define MXC_ANADIG_PFD0_STABLE (1 << 6)
+#define MXC_ANADIG_PFD0_FRAC_OFFSET 0
+
+#define MXC_ANADIG_PFD7_CLKGATE (1 << 31)
+#define MXC_ANADIG_PFD7_STABLE (1 << 30)
+#define MXC_ANADIG_PFD7_FRAC_OFFSET 24
+#define MXC_ANADIG_PFD6_CLKGATE (1 << 23)
+#define MXC_ANADIG_PFD6_STABLE (1 << 22)
+#define MXC_ANADIG_PFD6_FRAC_OFFSET 16
+#define MXC_ANADIG_PFD5_CLKGATE (1 << 15)
+#define MXC_ANADIG_PFD5_STABLE (1 << 14)
+#define MXC_ANADIG_PFD5_FRAC_OFFSET 8
+#define MXC_ANADIG_PFD4_CLKGATE (1 << 7)
+#define MXC_ANADIG_PFD4_STABLE (1 << 6)
+#define MXC_ANADIG_PFD4_FRAC_OFFSET 0
+
+#define MXC_ANADIG_APLL_LOCK (1 << 31)
+#define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30)
+#define MXC_ANADIG_PFD_DIS_OFFSET 16
+#define MXC_ANADIG_PFD_DIS_MASK 0xff
+#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET 0
+#define MXC_ANADIG_APLL_LOCK_CNT_MASK 0xffff
+
/* Register addresses of CCM*/
-#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
-#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
-#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
-#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
-#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
-#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
-#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
-#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
-#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
-#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
-#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
-#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
-#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
-#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
-#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
-#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
-#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
-#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
-#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
-#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
-#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
-#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
-#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
-#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
-#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
-#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
-#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
-#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
-#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
-#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
-#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
-#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
-#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
-#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
-
-#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
+#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84)
+#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88)
+#define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C)
+#define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90)
+#define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94)
+#define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98)
+#define MXC_CCM_ELCDIFPIX (MXC_CCM_BASE + 0x9C)
+#define MXC_CCM_EPDCPIX (MXC_CCM_BASE + 0xA0)
+#define MXC_CCM_DISPLAY_AXI (MXC_CCM_BASE + 0xA4)
+#define MXC_CCM_EPDC_AXI (MXC_CCM_BASE + 0xA8)
+#define MXC_CCM_GPMI (MXC_CCM_BASE + 0xAC)
+#define MXC_CCM_BCH (MXC_CCM_BASE + 0xB0)
+#define MXC_CCM_MSHC_XMSCKI (MXC_CCM_BASE + 0xB4)
+
+/* CCM Register Offsets. */
+#define MXC_CCM_CDCR_OFFSET 0x4C
+#define MXC_CCM_CACRR_OFFSET 0x10
+#define MXC_CCM_CDHIPR_OFFSET 0x48
/* Define the bits in register CCR */
#define MXC_CCM_CCR_COSC_EN (1 << 12)
@@ -128,82 +195,103 @@
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
/* Define the bits in register CCDR */
+/* MX51 */
#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
+/* MX53 */
+#define MXC_CCM_CCDR_IPU_HS_MX53_MASK (0x1 << 21)
+#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20)
+#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19)
+#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18)
+#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSR_READY (1 << 5)
-#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
+#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
#define MXC_CCM_CSR_FPM_READY (1 << 1)
-#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
/* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
-#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
-#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13)
+#define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12)
+#define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11)
+#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10)
+#define MXC_CCM_CCSR_LP_APM_SE_MX51L (0x1 << 9)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
-#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
-#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
1: step_clk */
-#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
-#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
-#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
/* Define the bits in register CBCDR */
-#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MX50_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27)
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25)
#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
-#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET (22)
+#define MX50_CCM_CBCDR_WEIM_PODF_MASK (0x7 << 22)
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
-#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
-#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
-#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
-#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
-#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
-#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
-#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
-#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
-#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
-#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
@@ -212,103 +300,128 @@
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
-#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51 (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
-#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
-#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
-#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
-#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
-#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21)
+#define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20)
+#define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
-#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
-#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
-#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
-#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
/* Define the bits in register CSCMR2 */
#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
-#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
-#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+/* MX51 */
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
-#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
+/* MX53 */
+#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16)
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
+/* MX51 */
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
-#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
-#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
+/* MX53 */
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (0x1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (0x1 << 10)
+#define MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL (0x1 << 9)
+#define MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL (0x1 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6)
#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
-#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
-#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
-#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
-#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
-#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK (0x7 << 11)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
-#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
/* Define the bits in register CS1CDR and CS2CDR */
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
-#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
@@ -316,50 +429,74 @@
/* Define the bits in register CDCDR */
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
-#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
+/* MX51 */
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
+/* MX53 */
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16)
+#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
-#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
-#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
/* Define the bits in register CHSCCDR */
+/* MX51 */
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
-#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
-#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
-#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
+/* MX53 */
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6)
+#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4)
+#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2)
+#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2)
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0)
+#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3)
/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28)
+#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28)
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+/* MX51 */
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
-#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
+/* MX53 */
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F)
/* Define the bits in register CSCDR3 */
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
-#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
@@ -368,13 +505,13 @@
/* Define the bits in register CSCDR4 */
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
-#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
-#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
/* Define the bits in register CDHIPR */
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
@@ -389,59 +526,92 @@
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
/* Define the bits in register CDCR */
-#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
-#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7)
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6)
+#define MX50_CCM_CDCR_SW_DVFS_EN (0x1 << 5)
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
/* Define the bits in register CLPCR */
+/* MX51 */
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
-#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
-#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51 (0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51 (0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51 (0x1 << 20)
+/* MX53 */
+#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53 (0x1 << 26)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23)
+#define MX50_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20)
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
-#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
-#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
-#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
-#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
-#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
-#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
-#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
-#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
+#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
-#define MXC_CCM_CLPCR_LPM_OFFSET (0)
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2)
+#define MXC_CCM_CLPCR_LPM_OFFSET (0)
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
/* Define the bits in register CISR */
-#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
-#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CISR_ARM_PODF_LOADED_MX51 (0x1 << 25)
+#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26)
+#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25)
+#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23)
+#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
-#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
-#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
+#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
+#define MX50_CCM_CISR_CAMP1_READY (0x1 << 4)
#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
-#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
-#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
-#define MXC_CCM_CISR_LRF_PLL1 (0x1)
+#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1 (0x1)
/* Define the bits in register CIMR */
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51 (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51 (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51 (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26)
+#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23)
+#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22)
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
-#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
-#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53 (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53 (0x1 << 19)
+#define MX50_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19)
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
-#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
+/* MX51 */
+#define MXC_CCM_CIMR_MASK_COSC_READY_MX51 (0x1 << 5)
#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
+/* MX53/MX50 */
+#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6)
+#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3)
#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
@@ -459,11 +629,20 @@
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24)
+#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23)
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
+#define MX50_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8)
+#define MX50_CCM_CCOSR_CKO1_EN (0x1 << 7)
+#define MX50_CCM_CCOSR_CKO1_DIV_OFFSET (4)
+#define MX50_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4)
+#define MX50_CCM_CCOSR_CKO1_SEL_OFFSET (0)
+#define MX50_CCM_CCOSR_CKO1_SEL_MASK (0xF)
+
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGRx_CG_MASK 0x3
#define MXC_CCM_CCGRx_MOD_OFF 0x0
@@ -502,30 +681,120 @@
#define MXC_CCM_CCGRx_CG1_OFFSET 2
#define MXC_CCM_CCGRx_CG0_OFFSET 0
-#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
-#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
-#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
-#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
-#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
-#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
-#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
-#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
-#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
-#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
-#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
-#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
-#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
+#define MXC_CCM_CCGR5_CG6_1_OFFSET 12
+#define MXC_CCM_CCGR5_CG6_2_OFFSET 13
+
+/* Define the bits in registers CSR2 */
+#define MXC_CCM_CSR2_ELCDIF_PIX_BUSY (0x1 << 9)
+#define MXC_CCM_CSR2_EPDC_PIX_BUSY (0x1 << 8)
+#define MXC_CCM_CSR2_EPDC_AXI_BUSY (0x1 << 4)
+#define MXC_CCM_CSR2_DISPLAY_AXI_BUSY (0x1 << 3)
+
+/* Define the bits in registers CLKSEQ_BYPASS */
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET 14
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET 12
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_OFFSET 6
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_GPMI_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_OFFSET 8
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_BCH_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET 4
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET 2
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK (0x3 << 2)
+
+/* Define the bits in registers CLK_SYS */
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET (30)
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET (28)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK (0x3 << 28)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET (6)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xF << 6)
+#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET (0)
+#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3F)
+
+/* Define the bits in registers CLK_DDR */
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30)
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F)
+
+/* Define the bits in register DISPLAY_AXI */
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET (30)
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_EN (1 << 13)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_MASK (0x7 << 10)
+#define MXC_CCM_DISPLAY_AXI_PXP_ASM_DIV_OFFSET 10
+#define MXC_CCM_DISPLAY_AXI_DIV_OFFSET (0)
+#define MXC_CCM_DISPLAY_AXI_DIV_MASK (0x3F)
+
+/* Define the bits in register EPDC_AXI */
+#define MXC_CCM_EPDC_AXI_CLKGATE_OFFSET (30)
+#define MXC_CCM_EPDC_AXI_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_EPDC_AXI_ASM_EN (1 << 9)
+#define MXC_CCM_EPDC_AXI_ASM_DIV_OFFSET (6)
+#define MXC_CCM_EPDC_AXI_ASM_DIV_MASK (0x7 << 6)
+#define MXC_CCM_EPDC_AXI_DIV_OFFSET (0)
+#define MXC_CCM_EPDC_AXI_DIV_MASK (0x3F)
+
+/* Define the bits in register EPDCPIX */
+#define MXC_CCM_EPDC_PIX_CLKGATE_OFFSET (30)
+#define MXC_CCM_EPDC_PIX_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET (12)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_MASK (0x3 << 12)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET (0)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_MASK (0xFFF)
+
+/* Define the bits in register ELCDIFPIX */
+#define MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET (30)
+#define MXC_CCM_ELCDIFPIX_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET (12)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_MASK (0x3 << 12)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET (0)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK (0xFFF)
+
+
+/* Define the bits in register GPMI */
+#define MXC_CCM_GPMI_CLKGATE_OFFSET (30)
+#define MXC_CCM_GPMI_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_GPMI_CLK_DIV_OFFSET (0)
+#define MXC_CCM_GPMI_CLK_DIV_MASK (0x3F)
+
+/* Define the bits in register BCH */
+#define MXC_CCM_BCH_CLKGATE_OFFSET (30)
+#define MXC_CCM_BCH_CLKGATE_MASK (0x3 << 30)
+#define MXC_CCM_BCH_CLK_DIV_OFFSET (0)
+#define MXC_CCM_BCH_CLK_DIV_MASK (0x3F)
+
+#define MXC_GPC_BASE (MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR))
+#define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80)
+#define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100)
+#define MXC_DVFS_CORE_BASE (MXC_GPC_BASE + 0x180)
+#define MXC_DVFS_PER_BASE (MXC_GPC_BASE + 0x1C4)
+#define MXC_PGC_IPU_BASE (MXC_GPC_BASE + 0x220)
+#define MXC_PGC_VPU_BASE (MXC_GPC_BASE + 0x240)
+#define MXC_PGC_GPU_BASE (MXC_GPC_BASE + 0x260)
+#define MXC_SRPG_NEON_BASE (MXC_GPC_BASE + 0x280)
+#define MXC_SRPG_ARM_BASE (MXC_GPC_BASE + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE (MXC_GPC_BASE + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE (MXC_GPC_BASE + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0)
+#define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300)
/* CORTEXA8 platform */
-#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
-#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
-#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
-#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
-#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
-#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
-#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
-#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
-#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
+extern void __iomem *arm_plat_base;
+#define MXC_CORTEXA8_BASE (arm_plat_base)
+#define MXC_CORTEXA8_PLAT_PVID (arm_plat_base + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC (arm_plat_base + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC (arm_plat_base + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC (arm_plat_base + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC (arm_plat_base + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC (arm_plat_base + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC (arm_plat_base + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC (arm_plat_base + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS (arm_plat_base + 0x24)
/* DVFS CORE */
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
@@ -546,28 +815,23 @@
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-/* GPC */
-#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
-#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
-#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
-#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
-#define MXC_GPC_PGR_ARMPG_OFFSET 8
-#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
-
-/* PGC */
-#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
-#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
-#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
-#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
-#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
-#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
-
-#define MXC_PGCR_PCR 1
-#define MXC_SRPGCR_PCR 1
-#define MXC_EMPGCR_PCR 1
-#define MXC_PGSR_PSR 1
+/* DVFS PER */
+#define MXC_DVFSPER_LTR0 (MXC_DVFS_PER_BASE)
+#define MXC_DVFSPER_LTR1 (MXC_DVFS_PER_BASE + 0x04)
+#define MXC_DVFSPER_LTR2 (MXC_DVFS_PER_BASE + 0x08)
+#define MXC_DVFSPER_LTR3 (MXC_DVFS_PER_BASE + 0x0C)
+#define MXC_DVFSPER_LTBR0 (MXC_DVFS_PER_BASE + 0x10)
+#define MXC_DVFSPER_LTBR1 (MXC_DVFS_PER_BASE + 0x14)
+#define MXC_DVFSPER_PMCR0 (MXC_DVFS_PER_BASE + 0x18)
+#define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C)
+/* GPC */
+#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
+#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
+#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
+#define MXC_GPC_CNTR_OFFSET 0x0
+#define MXC_GPC_PGR_OFFSET 0x4
+#define MXC_GPC_VCR_OFFSET 0x8
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index af488bc0e22..b7a941aa905 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -69,3 +69,23 @@ extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
extern const struct imx_pata_imx_data imx51_pata_imx_data;
#define imx51_add_pata_imx() \
imx_add_pata_imx(&imx51_pata_imx_data)
+
+extern const struct imx_ipuv3_data imx51_ipuv3_data __initconst;
+#define imx51_add_ipuv3(id, pdata) imx_add_ipuv3(id, &imx51_ipuv3_data, pdata)
+#define imx51_add_ipuv3fb(id, pdata) imx_add_ipuv3_fb(id, pdata)
+
+extern const struct imx_tve_data imx51_tve_data __initconst;
+#define imx51_add_tve(pdata) \
+ imx_add_tve(&imx51_tve_data, pdata)
+
+#define imx51_add_v4l2_output(id) \
+ platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+ id, NULL, 0, NULL, 0);
+
+extern const struct imx_spdif_data imx51_imx_spdif_data __initconst;
+#define imx51_add_spdif(pdata) imx_add_spdif(&imx51_imx_spdif_data, pdata)
+
+extern const struct imx_spdif_dai_data imx51_spdif_dai_data __initconst;
+#define imx51_add_spdif_dai() imx_add_spdif_dai(&imx51_spdif_dai_data)
+
+#define imx51_add_spdif_audio_device(pdata) imx_add_spdif_audio_device()
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 6e1e5d1f8c3..8d15ee5e35c 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,6 +29,10 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
#define imx53_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
+extern const struct imx_mxc_gpu_data imx53_gpu_data __initconst;
+#define imx53_add_mxc_gpu(pdata) \
+ imx_add_mxc_gpu(&imx53_gpu_data, pdata)
+
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
@@ -37,6 +41,14 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
#define imx53_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
+extern const struct imx_spdif_data imx53_imx_spdif_data __initconst;
+#define imx53_add_spdif(pdata) imx_add_spdif(&imx53_imx_spdif_data, pdata)
+
+extern const struct imx_spdif_dai_data imx53_spdif_dai_data __initconst;
+#define imx53_add_spdif_dai() imx_add_spdif_dai(&imx53_spdif_dai_data)
+
+#define imx53_add_spdif_audio_device(pdata) imx_add_spdif_audio_device()
+
extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
#define imx53_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
@@ -46,3 +58,42 @@ extern const struct imx_pata_imx_data imx53_pata_imx_data;
imx_add_pata_imx(&imx53_pata_imx_data)
extern struct platform_device *__init imx53_add_ahci_imx(void);
+
+extern const struct imx_srtc_data imx53_imx_srtc_data __initconst;
+#define imx53_add_srtc() \
+ imx_add_srtc(&imx53_imx_srtc_data)
+
+extern const struct imx_iim_data imx53_imx_iim_data __initconst;
+#define imx53_add_iim(pdata) \
+ imx_add_iim(&imx53_imx_iim_data, pdata)
+
+extern const struct imx_ipuv3_data imx53_ipuv3_data __initconst;
+#define imx53_add_ipuv3(id, pdata) imx_add_ipuv3(id, &imx53_ipuv3_data, pdata)
+#define imx53_add_ipuv3fb(id, pdata) imx_add_ipuv3_fb(id, pdata)
+
+extern const struct imx_tve_data imx53_tve_data __initconst;
+#define imx53_add_tve(pdata) \
+ imx_add_tve(&imx53_tve_data, pdata)
+
+extern const struct imx_ldb_data imx53_ldb_data __initconst;
+#define imx53_add_ldb(pdata) \
+ imx_add_ldb(&imx53_ldb_data, pdata);
+
+extern const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst;
+#define imx53_add_mxc_pwm(id) \
+ imx_add_mxc_pwm(&imx53_mxc_pwm_data[id])
+
+#define imx53_add_lcdif(pdata) \
+ platform_device_register_resndata(NULL, "mxc_lcdif",\
+ 0, NULL, 0, pdata, sizeof(*pdata));
+
+#define imx53_add_mxc_pwm_backlight(id, pdata) \
+ platform_device_register_resndata(NULL, "pwm-backlight",\
+ id, NULL, 0, pdata, sizeof(*pdata));
+
+#define imx53_add_v4l2_output(id) \
+ platform_device_register_resndata(NULL, "mxc_v4l2_output",\
+ id, NULL, 0, NULL, 0);
+
+extern const struct imx_vpu_data imx53_vpu_data __initconst;
+#define imx53_add_vpu() imx_add_vpu(&imx53_vpu_data)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 00000000000..d579ce49f64
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/irqs.h>
+
+static struct resource mxc_hsi2c_resources[] = {
+ {
+ .start = MX51_HSI2C_DMA_BASE_ADDR,
+ .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX51_INT_HS_I2C,
+ .end = MX51_INT_HS_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_hsi2c_device = {
+ .name = "imx-i2c",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
+ .resource = mxc_hsi2c_resources
+};
+
+static u64 usb_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource usbotg_resources[] = {
+ {
+ .start = MX51_USB_OTG_BASE_ADDR,
+ .end = MX51_USB_OTG_BASE_ADDR + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX51_INT_USB_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* OTG gadget device */
+struct platform_device mxc_usbdr_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(usbotg_resources),
+ .resource = usbotg_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device mx53_usbdr_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(usbotg_resources),
+ .resource = usbotg_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device mxc_usbdr_host_device = {
+ .name = "mxc-ehci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(usbotg_resources),
+ .resource = usbotg_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device mx53_usbdr_host_device = {
+ .name = "fsl-ehci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(usbotg_resources),
+ .resource = usbotg_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource usbotg_wakeup_resources[] = {
+ {
+ .start = MX51_INT_USB_OTG,/* wakeup irq */
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MX51_INT_USB_OTG,/* usb core irq */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mx53_usbdr_wakeup_device = {
+ .name = "usb_wakeup",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(usbotg_wakeup_resources),
+ .resource = usbotg_wakeup_resources,
+};
+
+static struct resource usbotg_xcvr_resources[] = {
+ {
+ .start = MX51_USB_OTG_BASE_ADDR,
+ .end = MX51_USB_OTG_BASE_ADDR + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX51_INT_USB_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mx53_usbdr_otg_device = {
+ .name = "fsl-usb2-otg",
+ .id = -1,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = usbotg_xcvr_resources,
+ .num_resources = ARRAY_SIZE(usbotg_xcvr_resources),
+};
+
+static struct resource usbh1_resources[] = {
+ {
+ .start = MX51_USB_OTG_BASE_ADDR + 0x200,
+ .end = MX51_USB_OTG_BASE_ADDR + 0x200 + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX51_INT_USB_HS1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_usbh1_device = {
+ .name = "mxc-ehci",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(usbh1_resources),
+ .resource = usbh1_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device mx53_usbh1_device = {
+ .name = "fsl-ehci",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(usbh1_resources),
+ .resource = usbh1_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct resource usbh2_resources[] = {
+ {
+ .start = MX51_USB_OTG_BASE_ADDR + 0x400,
+ .end = MX51_USB_OTG_BASE_ADDR + 0x400 + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX51_INT_USB_HS2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_usbh2_device = {
+ .name = "mxc-ehci",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(usbh2_resources),
+ .resource = usbh2_resources,
+ .dev = {
+ .dma_mask = &usb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device mxc_pm_device = {
+ .name = "mx5_pm",
+ .id = 0,
+};
+
+static struct resource usbh1_wakeup_resources[] = {
+ {
+ .start = MX51_INT_USB_HS1, /*wakeup irq*/
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = MX51_INT_USB_HS1,
+ .flags = IORESOURCE_IRQ,/* usb core irq */
+ },
+};
+
+struct platform_device mx53_usbh1_wakeup_device = {
+ .name = "usb_wakeup",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(usbh1_wakeup_resources),
+ .resource = usbh1_wakeup_resources,
+};
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 00000000000..a0de07b318f
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,12 @@
+extern struct platform_device mxc_usbdr_host_device;
+extern struct platform_device mx53_usbdr_host_device;
+extern struct platform_device mxc_usbh1_device;
+extern struct platform_device mxc_usbh2_device;
+extern struct platform_device mx53_usbh1_device;
+extern struct platform_device mxc_usbdr_udc_device;
+extern struct platform_device mx53_usbdr_udc_device;
+extern struct platform_device mxc_hsi2c_device;
+extern struct platform_device mxc_pm_device;
+extern struct platform_device mx53_usbdr_wakeup_device;
+extern struct platform_device mx53_usbh1_wakeup_device;
+extern struct platform_device mx53_usbdr_otg_device;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index df4a508f240..924395a90b2 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -14,7 +14,9 @@
#include <linux/mm.h>
#include <linux/init.h>
+#include <asm/sizes.h>
#include <asm/mach/map.h>
+#include <asm/pmu.h>
#include <mach/hardware.h>
#include <mach/common.h>
@@ -92,6 +94,9 @@ void __init imx51_init_early(void)
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
pm_idle = imx5_idle;
+
+ if (!system_rev)
+ system_rev = 0x51000;
}
void __init imx53_init_early(void)
@@ -99,6 +104,10 @@ void __init imx53_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX53);
mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+ init_consistent_dma_size(SZ_128M);
+
+ if (!system_rev)
+ system_rev = 0x53000;
}
void __init mx50_init_irq(void)
@@ -130,7 +139,7 @@ static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
};
static struct sdma_platform_data imx51_sdma_pdata __initdata = {
- .fw_name = "sdma-imx51.bin",
+ .fw_name = "imx/sdma/sdma-imx51-to3.bin",
.script_addrs = &imx51_sdma_script,
};
@@ -149,7 +158,7 @@ static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
};
static struct sdma_platform_data imx53_sdma_pdata __initdata = {
- .fw_name = "sdma-imx53.bin",
+ .fw_name = "imx/sdma/sdma-imx53-to1.bin",
.script_addrs = &imx53_sdma_script,
};
@@ -164,6 +173,21 @@ void __init imx50_soc_init(void)
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
}
+static struct resource mx5_pmu_resources[] = {
+ {
+ /* MX51/53 share the same IRQ number */
+ .start = MX51_INT_PMU,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device mx5_pmu_device = {
+ .name = "arm-pmu",
+ .id = ARM_PMU_DEVICE_CPU,
+ .resource = &mx5_pmu_resources,
+ .num_resources = 1,
+};
+
void __init imx51_soc_init(void)
{
/* i.mx51 has the i.mx31 type gpio */
@@ -174,6 +198,8 @@ void __init imx51_soc_init(void)
/* i.mx51 has the i.mx35 type sdma */
imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+
+ platform_device_register(&mx5_pmu_device);
}
void __init imx53_soc_init(void)
@@ -189,4 +215,6 @@ void __init imx53_soc_init(void)
/* i.mx53 has the i.mx35 type sdma */
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+
+ platform_device_register(&mx5_pmu_device);
}
diff --git a/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c
new file mode 100644
index 00000000000..75266141fea
--- /dev/null
+++ b/arch/arm/mach-mx5/mx53_loco_pmic_da9053.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+/*
+ * mx53_loco_pmic_da9053.c -- i.MX53 LOCO driver for pmic da9053
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/da9052/da9052.h>
+#include <linux/mfd/da9052/pm.h>
+#include <linux/mfd/da9052/led.h>
+#include <linux/mfd/da9052/tsi.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx53.h>
+
+#define DA9052_LDO(max, min, rname, suspend_mv) \
+{\
+ .constraints = {\
+ .name = (rname), \
+ .max_uV = (max) * 1000,\
+ .min_uV = (min) * 1000,\
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE\
+ |REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE,\
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,\
+ .state_mem = { \
+ .uV = suspend_mv * 1000, \
+ .mode = REGULATOR_MODE_NORMAL, \
+ .enabled = (0 == suspend_mv) ? 0 : 1, \
+ .disabled = 0, \
+ }, \
+ },\
+}
+
+#ifdef CONFIG_SND_SOC_SGTL5000
+
+static struct regulator_consumer_supply sgtl5000_consumer[] = {
+ REGULATOR_SUPPLY("VDDA", NULL),
+ REGULATOR_SUPPLY("VDDIO", NULL),
+};
+
+static struct regulator_init_data sgtl5000_reg_initdata = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(sgtl5000_consumer),
+ .consumer_supplies = &sgtl5000_consumer[0],
+};
+
+static struct fixed_voltage_config sgtl5000_reg_config = {
+ .supply_name = "VDDA",
+ .microvolts = 3200000,
+ .gpio = -1,
+ .init_data = &sgtl5000_reg_initdata,
+};
+
+static struct platform_device sgtl5000_reg_devices = {
+
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &sgtl5000_reg_config,
+ },
+};
+#endif /* CONFIG_SND_SOC_SGTL5000 */
+
+/* currently the suspend_mv here takes no effects for DA9053
+preset-voltage have to be done in the latest stage during
+suspend*/
+static struct regulator_init_data da9052_regulators_init[] = {
+ DA9052_LDO(DA9052_LDO1_VOLT_UPPER,
+ DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300),
+ DA9052_LDO(DA9052_LDO2_VOLT_UPPER,
+ DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300),
+ DA9052_LDO(DA9052_LDO34_VOLT_UPPER,
+ DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300),
+ DA9052_LDO(DA9052_LDO34_VOLT_UPPER,
+ DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775),
+ DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+ DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300),
+ DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+ DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200),
+ DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+ DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750),
+ DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+ DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800),
+ DA9052_LDO(DA9052_LDO9_VOLT_UPPER,
+ DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500),
+ DA9052_LDO(DA9052_LDO567810_VOLT_UPPER,
+ DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200),
+
+ /* BUCKS */
+ DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+ DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850),
+ DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER,
+ DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950),
+ DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER,
+ DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500),
+ DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER,
+ DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500)
+};
+
+
+static struct da9052_tsi_platform_data da9052_tsi = {
+ .pen_up_interval = 50,
+ .tsi_delay_bit_shift = 6,
+ .tsi_skip_bit_shift = 3,
+ .num_gpio_tsi_register = 3,
+ .tsi_supply_voltage = 2500,
+ /* This is the DA9052 LDO number used for powering the TSI */
+ .tsi_ref_source = 9,
+ .max_tsi_delay = TSI_DELAY_4SLOTS,
+ .max_tsi_skip_slot = TSI_SKIP_330SLOTS,
+};
+
+static struct da9052_led_platform_data da9052_gpio_led[] = {
+ {
+ .id = DA9052_LED_4,
+ .name = "LED_GPIO14",
+ },
+ {
+ .id = DA9052_LED_5,
+ .name = "LED_GPIO15",
+ },
+};
+
+static struct da9052_leds_platform_data da9052_gpio_leds = {
+ .num_leds = ARRAY_SIZE(da9052_gpio_led),
+ .led = da9052_gpio_led,
+};
+
+
+static void da9052_init_ssc_cache(struct da9052 *da9052)
+{
+ unsigned char cnt;
+
+ /* First initialize all registers as Non-volatile */
+ for (cnt = 0; cnt < DA9052_REG_CNT; cnt++) {
+ da9052->ssc_cache[cnt].type = NON_VOLATILE;
+ da9052->ssc_cache[cnt].status = INVALID;
+ da9052->ssc_cache[cnt].val = 0;
+ }
+
+ /* Now selectively set type for all Volatile registers */
+ /* Reg 1 - 9 */
+ da9052->ssc_cache[DA9052_STATUSA_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_STATUSB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_STATUSC_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_STATUSD_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_EVENTA_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_EVENTB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_EVENTC_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_EVENTD_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_FAULTLOG_REG].type = VOLATILE;
+
+ /* Reg 15 */
+ da9052->ssc_cache[DA9052_CONTROLB_REG].type = VOLATILE;
+ /* Reg - 17 */
+ da9052->ssc_cache[DA9052_CONTROLD_REG].type = VOLATILE;
+ /* Reg - 60 */
+ da9052->ssc_cache[DA9052_SUPPLY_REG].type = VOLATILE;
+ /* Reg - 62 */
+ da9052->ssc_cache[DA9052_CHGBUCK_REG].type = VOLATILE;
+
+ /* Reg 67 - 68 */
+ da9052->ssc_cache[DA9052_INPUTCONT_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_CHGTIME_REG].type = VOLATILE;
+
+ /* Reg - 70 */
+ da9052->ssc_cache[DA9052_BOOST_REG].type = VOLATILE;
+
+ /* Reg - 81 */
+ da9052->ssc_cache[DA9052_ADCMAN_REG].type = VOLATILE;
+
+ /* Reg - 83 - 85 */
+ da9052->ssc_cache[DA9052_ADCRESL_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_ADCRESH_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_VDDRES_REG].type = VOLATILE;
+
+ /* Reg - 87 */
+ da9052->ssc_cache[DA9052_ICHGAV_REG].type = VOLATILE;
+
+ /* Reg - 90 */
+ da9052->ssc_cache[DA9052_TBATRES_REG].type = VOLATILE;
+
+ /* Reg - 95 */
+ da9052->ssc_cache[DA9052_ADCIN4RES_REG].type = VOLATILE;
+
+ /* Reg - 98 */
+ da9052->ssc_cache[DA9052_ADCIN5RES_REG].type = VOLATILE;
+
+ /* Reg - 101 */
+ da9052->ssc_cache[DA9052_ADCIN6RES_REG].type = VOLATILE;
+
+ /* Reg - 104 */
+ da9052->ssc_cache[DA9052_TJUNCRES_REG].type = VOLATILE;
+
+ /* Reg 106 - 110 */
+ da9052->ssc_cache[DA9052_TSICONTB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_TSIXMSB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_TSIYMSB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_TSILSB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_TSIZMSB_REG].type = VOLATILE;
+
+ /* Reg 111 - 117 */
+ da9052->ssc_cache[DA9052_COUNTS_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_COUNTMI_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_COUNTH_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_COUNTD_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_COUNTMO_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_COUNTY_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_ALARMMI_REG].type = VOLATILE;
+
+ /* Reg 122 - 125 */
+ da9052->ssc_cache[DA9052_SECONDA_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_SECONDB_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_SECONDC_REG].type = VOLATILE;
+ da9052->ssc_cache[DA9052_SECONDD_REG].type = VOLATILE;
+
+ /* Following addresses are not assigned to any register */
+ da9052->ssc_cache[126].type = VOLATILE;
+ da9052->ssc_cache[127].type = VOLATILE;
+}
+
+
+#define MX53_LOCO_DA9052_IRQ (6*32 + 11) /* GPIO7_11 */
+
+static int __init loco_da9052_init(struct da9052 *da9052)
+{
+ /* Configuring for DA9052 interrupt servce */
+ /* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/
+
+ /* Set interrupt as LOW LEVEL interrupt source */
+ irq_set_irq_type(gpio_to_irq(MX53_LOCO_DA9052_IRQ), IRQF_TRIGGER_LOW);
+
+ da9052_init_ssc_cache(da9052);
+
+#ifdef CONFIG_SND_SOC_SGTL5000
+ platform_device_register(&sgtl5000_reg_devices);
+#endif
+
+ return 0;
+}
+
+static struct da9052_platform_data __initdata da9052_plat = {
+ .init = loco_da9052_init,
+ .num_regulators = ARRAY_SIZE(da9052_regulators_init),
+ .regulators = da9052_regulators_init,
+ .led_data = &da9052_gpio_leds,
+ .tsi_data = &da9052_tsi,
+ /* .bat_data = &da9052_bat, */
+ /* .gpio_base = GPIO_BOARD_START, */
+};
+
+
+static struct i2c_board_info __initdata da9052_i2c_device = {
+ I2C_BOARD_INFO(DA9052_SSC_I2C_DEVICE_NAME, DA9052_I2C_ADDR >> 1),
+ .platform_data = &da9052_plat,
+};
+
+int __init mx53_loco_init_da9052(void)
+{
+ da9052_i2c_device.irq = gpio_to_irq(MX53_LOCO_DA9052_IRQ);
+ return i2c_register_board_info(0, &da9052_i2c_device, 1);
+}
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
index 98052fc852c..120dd9624dd 100644
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -38,6 +38,8 @@ static int mx5_suspend_enter(suspend_state_t state)
return -EINVAL;
}
+ if (tzic_enable_wake(0) != 0)
+ return -EAGAIN;
if (state == PM_SUSPEND_MEM) {
local_flush_tlb_all();
flush_cache_all();
@@ -47,6 +49,10 @@ static int mx5_suspend_enter(suspend_state_t state)
__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
}
cpu_do_idle();
+
+ __raw_writel(0, MXC_CORTEXA8_PLAT_LPC);
+ clk_disable(gpc_dvfs_clk);
+
return 0;
}
@@ -73,8 +79,9 @@ static int __init mx5_pm_init(void)
gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
if (!IS_ERR(gpc_dvfs_clk)) {
- if (cpu_is_mx51())
+ if (cpu_is_mx51() || cpu_is_mx53()) {
suspend_set_ops(&mx5_suspend_ops);
+ }
} else
return -EPERM;
diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c
new file mode 100644
index 00000000000..8d671ad2b0f
--- /dev/null
+++ b/arch/arm/mach-mx5/pm.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/suspend.h>
+#include <linux/regulator/machine.h>
+#include <linux/proc_fs.h>
+#include <linux/cpufreq.h>
+#include <mach/iram.h>
+#include <linux/fsl_devices.h>
+#include <asm/mach-types.h>
+#include <asm/cacheflush.h>
+#include <asm/tlb.h>
+#include <asm/delay.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#ifdef CONFIG_ARCH_MX50
+#include <mach/iomux-mx50.h>
+#endif
+#include "crm_regs.h"
+
+#define DATABAHN_CTL_REG0 0
+#define DATABAHN_CTL_REG19 0x4c
+#define DATABAHN_CTL_REG79 0x13c
+#define DATABAHN_PHY_REG25 0x264
+#define MX53_OFFSET 0x20000000
+
+static struct cpu_op *cpu_op_tbl;
+static int cpu_op_nr;
+static struct clk *cpu_clk;
+static struct mxc_pm_platform_data *pm_data;
+
+#if defined(CONFIG_CPU_FREQ)
+static int org_freq;
+extern int set_cpu_freq(int wp);
+#endif
+
+
+static struct device *pm_dev;
+struct clk *gpc_dvfs_clk;
+extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr);
+extern void mx50_suspend(u32 databahn_addr);
+extern struct cpu_op *(*get_cpu_op)(int *wp);
+extern void __iomem *databahn_base;
+extern void da9053_suspend_cmd(void);
+extern void da9053_resume_dump(void);
+extern void pm_da9053_i2c_init(u32 base_addr);
+
+extern int iram_ready;
+void *suspend_iram_base;
+void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL;
+void __iomem *suspend_param1;
+
+#define TZIC_WAKEUP0_OFFSET 0x0E00
+#define TZIC_WAKEUP1_OFFSET 0x0E04
+#define TZIC_WAKEUP2_OFFSET 0x0E08
+#define TZIC_WAKEUP3_OFFSET 0x0E0C
+#define GPIO7_0_11_IRQ_BIT (0x1<<11)
+
+static void mx53_smd_loco_irq_wake_fixup(void)
+{
+ void __iomem *tzic_base;
+ tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K);
+ if (NULL == tzic_base) {
+ pr_err("fail to map MX53_TZIC_BASE_ADDR\n");
+ return;
+ }
+ __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET);
+ __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET);
+ __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET);
+ /* only enable irq wakeup for da9053 */
+ __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET);
+ iounmap(tzic_base);
+ pr_debug("only da9053 irq is wakeup-enabled\n");
+}
+
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+ if (gpc_dvfs_clk == NULL)
+ gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk");
+ /* gpc clock is needed for SRPG */
+ clk_enable(gpc_dvfs_clk);
+ switch (state) {
+ case PM_SUSPEND_MEM:
+ mx5_cpu_lp_set(STOP_POWER_OFF);
+ break;
+ case PM_SUSPEND_STANDBY:
+ mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (tzic_enable_wake(0) != 0)
+ return -EAGAIN;
+
+ if (state == PM_SUSPEND_MEM) {
+ local_flush_tlb_all();
+ flush_cache_all();
+
+ if (pm_data && pm_data->suspend_enter)
+ pm_data->suspend_enter();
+
+ suspend_in_iram(suspend_param1);
+
+ if (pm_data && pm_data->suspend_exit)
+ pm_data->suspend_exit();
+ } else {
+ cpu_do_idle();
+ }
+ clk_disable(gpc_dvfs_clk);
+
+ return 0;
+}
+
+
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int mx5_suspend_prepare(void)
+{
+#if defined(CONFIG_CPU_FREQ)
+#define MX53_SUSPEND_CPU_WP 1000000000
+ struct cpufreq_freqs freqs;
+ u32 suspend_wp = 0;
+ org_freq = clk_get_rate(cpu_clk);
+ /* workaround for mx53 to suspend on 400MHZ wp */
+ if (cpu_is_mx53())
+ for (suspend_wp = 0; suspend_wp < cpu_op_nr; suspend_wp++)
+ if (cpu_op_tbl[suspend_wp].cpu_rate
+ == MX53_SUSPEND_CPU_WP)
+ break;
+ if (suspend_wp == cpu_op_nr)
+ suspend_wp = 0;
+ pr_info("suspend wp cpu=%d\n", cpu_op_tbl[suspend_wp].cpu_rate);
+ freqs.old = org_freq / 1000;
+ freqs.new = cpu_op_tbl[suspend_wp].cpu_rate / 1000;
+ freqs.cpu = 0;
+ freqs.flags = 0;
+
+ if (clk_get_rate(cpu_clk) != cpu_op_tbl[suspend_wp].cpu_rate) {
+ set_cpu_freq(cpu_op_tbl[suspend_wp].cpu_rate);
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ }
+#endif
+ return 0;
+}
+
+/*
+ * Called before devices are re-setup.
+ */
+static void mx5_suspend_finish(void)
+{
+#if defined(CONFIG_CPU_FREQ)
+ struct cpufreq_freqs freqs;
+
+ freqs.old = clk_get_rate(cpu_clk) / 1000;
+ freqs.new = org_freq / 1000;
+ freqs.cpu = 0;
+ freqs.flags = 0;
+
+
+ if (org_freq != clk_get_rate(cpu_clk)) {
+ set_cpu_freq(org_freq);
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+ }
+#endif
+}
+
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static void mx5_suspend_end(void)
+{
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+ return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+struct platform_suspend_ops mx5_suspend_ops = {
+ .valid = mx5_pm_valid,
+ .prepare = mx5_suspend_prepare,
+ .enter = mx5_suspend_enter,
+ .finish = mx5_suspend_finish,
+ .end = mx5_suspend_end,
+};
+
+static int __devinit mx5_pm_probe(struct platform_device *pdev)
+{
+ pm_dev = &pdev->dev;
+ pm_data = pdev->dev.platform_data;
+
+ return 0;
+}
+
+static struct platform_driver mx5_pm_driver = {
+ .driver = {
+ .name = "mx5_pm",
+ },
+ .probe = mx5_pm_probe,
+};
+
+static int __init pm_init(void)
+{
+ unsigned long iram_paddr, cpaddr;
+
+ pr_info("Static Power Management for Freescale i.MX5\n");
+ if (platform_driver_register(&mx5_pm_driver) != 0) {
+ printk(KERN_ERR "mx5_pm_driver register failed\n");
+ return -ENODEV;
+ }
+ suspend_set_ops(&mx5_suspend_ops);
+ /* Move suspend routine into iRAM */
+ cpaddr = iram_alloc(SZ_4K, &iram_paddr);
+ /* Need to remap the area here since we want the memory region
+ to be executable. */
+ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
+ MT_HIGH_VECTORS);
+ pr_info("cpaddr = %x suspend_iram_base=%x\n", cpaddr, suspend_iram_base);
+
+ if (cpu_is_mx51() || cpu_is_mx53()) {
+ suspend_param1 = MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR + 0x4b8);
+ memcpy(cpaddr, cpu_do_suspend_workaround,
+ SZ_4K);
+ } else if (cpu_is_mx50()) {
+ /*
+ * Need to run the suspend code from IRAM as the DDR needs
+ * to be put into self refresh mode manually.
+ */
+ memcpy(cpaddr, mx50_suspend, SZ_4K);
+
+ suspend_param1 = databahn_base;
+ }
+ suspend_in_iram = (void *)suspend_iram_base;
+
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+
+ cpu_clk = clk_get(NULL, "cpu_clk");
+ if (IS_ERR(cpu_clk)) {
+ printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__);
+ return PTR_ERR(cpu_clk);
+ }
+ printk(KERN_INFO "PM driver module loaded\n");
+
+ return 0;
+}
+
+
+static void __exit pm_cleanup(void)
+{
+ /* Unregister the device structure */
+ platform_driver_unregister(&mx5_pm_driver);
+}
+
+module_init(pm_init);
+module_exit(pm_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("PM driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/sdram_autogating.c b/arch/arm/mach-mx5/sdram_autogating.c
new file mode 100644
index 00000000000..f352d360a9d
--- /dev/null
+++ b/arch/arm/mach-mx5/sdram_autogating.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file sdram_autogating.c
+ *
+ * @brief Enable auto clock gating of the EMI_FAST clock using M4IF.
+ *
+ * The APIs are for enabling and disabling automatic clock gating of EMI_FAST.
+ *
+ * @ingroup PM
+ */
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include <mach/sdram_autogating.h>
+#include "crm_regs.h"
+
+static struct device *sdram_autogating_dev;
+#define M4IF_CNTL_REG0 0x8c
+#define M4IF_CNTL_REG1 0x90
+
+/* Flag used to indicate if SDRAM M4IF autoclock gating feature is active. */
+static int sdram_autogating_is_active;
+static int sdram_autogating_paused;
+static void __iomem *m4if_base;
+
+void start_sdram_autogating(void);
+void stop_sdram_autogating(void);
+int sdram_autogating_active(void);
+
+static void enable(void)
+{
+ u32 reg;
+
+ /* Set the Fast arbitration Power saving timer */
+ reg = __raw_readl(m4if_base + M4IF_CNTL_REG1);
+ reg &= ~0xFF;
+ reg |= 0x09;
+ __raw_writel(reg, m4if_base + M4IF_CNTL_REG1);
+ /*Allow for automatic gating of the EMI internal clock.
+ * If this is done, emi_intr CCGR bits should be set to 11.
+ */
+ reg = __raw_readl(m4if_base + M4IF_CNTL_REG0);
+ reg &= ~0x5;
+ __raw_writel(reg, m4if_base + M4IF_CNTL_REG0);
+
+ sdram_autogating_is_active = 1;
+}
+
+static void disable(void)
+{
+ u32 reg;
+
+ reg = __raw_readl(m4if_base + M4IF_CNTL_REG0);
+ reg |= 0x4;
+ __raw_writel(reg, m4if_base + M4IF_CNTL_REG0);
+ sdram_autogating_is_active = 0;
+}
+
+int sdram_autogating_active()
+{
+ return sdram_autogating_is_active;
+}
+
+void start_sdram_autogating()
+{
+ if (cpu_is_mx50())
+ return;
+ if (sdram_autogating_paused) {
+ enable();
+ sdram_autogating_paused = 0;
+ }
+}
+
+void stop_sdram_autogating()
+{
+ if (cpu_is_mx50())
+ return;
+
+ if (sdram_autogating_is_active) {
+ sdram_autogating_paused = 1;
+ disable();
+ }
+}
+
+static ssize_t sdram_autogating_enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (sdram_autogating_is_active)
+ return sprintf(buf,
+ "M4IF autoclock gating for EMI_FAST enabled\n");
+ else
+ return sprintf(buf,
+ "M4IF autoclock gating for EMI_FAST disabled\n");
+}
+
+static ssize_t sdram_autogating_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ if (strstr(buf, "1") != NULL)
+ enable();
+ else if (strstr(buf, "0") != NULL) {
+ if (sdram_autogating_is_active)
+ disable();
+ }
+ return size;
+}
+
+static DEVICE_ATTR(enable, 0644, sdram_autogating_enable_show,
+ sdram_autogating_enable_store);
+
+/*!
+ * This is the probe routine for the auto clockgating of sdram driver.
+ *
+ * @param pdev The platform device structure
+ *
+ * @return The function returns 0 on success
+ *
+ */
+static int __devinit sdram_autogating_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ int err = 0;
+
+ sdram_autogating_dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ return -ENOMEM;
+ }
+ m4if_base = ioremap(res->start, res->end - res->start + 1);
+
+ err = sysfs_create_file(&sdram_autogating_dev->kobj,
+ &dev_attr_enable.attr);
+ if (err) {
+ printk(KERN_ERR
+ "Unable to register sysdev entry for sdram_autogating");
+ return err;
+ }
+
+ sdram_autogating_is_active = 0;
+
+ return 0;
+}
+
+static struct platform_driver sdram_autogating_driver = {
+ .driver = {
+ .name = "sdram_autogating",
+ },
+ .probe = sdram_autogating_probe,
+};
+
+/*!
+ * Initialise the sdram_autogating_driver.
+ *
+ * @return The function always returns 0.
+ */
+
+static int __init sdram_autogating_init(void)
+{
+ if (platform_driver_register(&sdram_autogating_driver) != 0) {
+ printk(KERN_ERR "sdram_autogating_driver register failed\n");
+ return -ENODEV;
+ }
+
+ printk(KERN_INFO "sdram autogating driver module loaded\n");
+ return 0;
+}
+
+static void __exit sdram_autogating_cleanup(void)
+{
+ sysfs_remove_file(&sdram_autogating_dev->kobj, &dev_attr_enable.attr);
+
+ /* Unregister the device structure */
+ platform_driver_unregister(&sdram_autogating_driver);
+}
+
+module_init(sdram_autogating_init);
+module_exit(sdram_autogating_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("sdram_autogating driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S
new file mode 100644
index 00000000000..c7937ec94d9
--- /dev/null
+++ b/arch/arm/mach-mx5/suspend.S
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+
+#define ARM_CTRL_DCACHE 1 << 2
+#define ARM_CTRL_ICACHE 1 << 12
+#define ARM_AUXCR_L2EN 1 << 1
+
+
+/*
+ * cpu_do_suspend_workaround()
+ *
+ * Suspend the processor (eg, wait for interrupt).
+ *
+ * IRQs are already disabled.
+ */
+ENTRY(cpu_do_suspend_workaround)
+ stmfd sp!, {r4,r5,r6,r7,r9,r10,r11} @ Save registers
+
+ mov r6, r0 @save iomux address
+ /* Disable L1 caches */
+ mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg
+ bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache
+ bic r0, r0, #ARM_CTRL_DCACHE @ Disable DCache
+ mcr p15, 0, r0, c1, c0, 0 @ Update system control reg
+
+ mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR
+ ands r3, r0, #0x7000000 @ Isolate level of coherency
+ mov r3, r3, lsr #23 @ Cache level value (naturally aligned)
+ beq FinishedClean
+ mov r10, #0
+Loop1Clean:
+ add r2, r10, r10, lsr #1 @ Work out cache level
+ mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level
+ and r1, r1, #7 @ Get those 3 bits alone
+ cmp r1, #2
+ blt SkipClean @ No cache or only instruction cache at this level
+ mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register
+ mov r1, #0
+ .long 0xF57FF06F @ ISB
+ mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register
+ and r2, r1, #7 @ Extract the line length field
+ add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes)
+ ldr r4, =0x3FF
+ ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned)
+ clz r5, r4 @ R5 is the bit position of the way size increment
+ ldr r7, =0x00007FFF
+ ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned)
+Loop2Clean:
+ mov r9, r4 @ R9 working copy of the max way size (right aligned)
+Loop3Clean:
+ orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11
+ orr r11, r11, r7, lsl r2 @ Factor in the index number
+ mcr p15, 0, r11, c7, c14, 2 @ Clean and invalidate by set/way
+ subs r9, r9, #1 @ Decrement the way number
+ bge Loop3Clean
+ subs r7, r7, #1 @ Decrement the index
+ bge Loop2Clean
+SkipClean:
+ add r10, r10, #2 @ Increment the cache number
+ cmp r3, r10
+ bgt Loop1Clean
+
+FinishedClean:
+
+ /* Disable L2 cache */
+ mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg
+ bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg
+
+#if 0
+ /*Set the DDR drive strength to low */
+ ldr r10, [r6]
+ and r10, r10, #0xF1 @ clear bits 2-1
+ str r10, [r6]
+#endif
+
+ .long 0xe320f003 @ Opcode for WFI
+
+#if 0
+ /*Set the DDR drive strength to max */
+ orr r10, r10, #0x06 @ set bits 2-1
+ str r10, [r6]
+#endif
+
+ ldr r11, =0x0000fFFF
+TestLoop:
+ subs r11,r11, #1 @ Decrement the index
+ bge TestLoop
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache
+
+ /* Invalidate data caches */
+ mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR
+ ands r3, r0, #0x7000000 @ Isolate level of coherency
+ mov r3, r3, lsr #23 @ Cache level value (naturally aligned)
+ beq FinishedInvalidate
+ mov r10, #0
+Loop1Invalidate:
+ add r2, r10, r10, lsr #1 @ Work out cache level
+ mov r1, r0, lsr r2 @ R0 bottom 3 bits = Cache Type for this level
+ and r1, r1, #7 @ Get those 3 bits alone
+ cmp r1, #2
+ blt SkipInvalidate @ No cache or only instruction cache at this level
+ mcr p15, 2, r10, c0, c0, 0 @ Write the Cache Size selection register
+ mov r1, #0
+ .long 0xF57FF06F @ ISB
+ mrc p15, 1, r1, c0, c0, 0 @ Reads current Cache Size ID register
+ and r2, r1, #7 @ Extract the line length field
+ add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes)
+ ldr r4, =0x3FF
+ ands r4, r4, r1, lsr #3 @ R4 is the max number on the way size (right aligned)
+ clz r5, r4 @ R5 is the bit position of the way size increment
+ ldr r7, =0x00007FFF
+ ands r7, r7, r1, lsr #13 @ R7 is the max number of the index size (right aligned)
+Loop2Invalidate:
+ mov r9, r4 @ R9 working copy of the max way size (right aligned)
+Loop3Invalidate:
+ orr r11, r10, r9, lsl r5 @ Factor in the way number and cache number into R11
+ orr r11, r11, r7, lsl r2 @ Factor in the index number
+ mcr p15, 0, r11, c7, c6, 2 @ Invalidate by set/way
+ subs r9, r9, #1 @ Decrement the way number
+ bge Loop3Invalidate
+ subs r7, r7, #1 @ Decrement the index
+ bge Loop2Invalidate
+SkipInvalidate:
+ add r10, r10, #2 @ Increment the cache number
+ cmp r3, r10
+ bgt Loop1Invalidate
+
+FinishedInvalidate:
+
+ /* Enable L2 cache */
+ mrc p15, 0, r0, c1, c0, 1 @ R0 = auxiliary control reg
+ orr r0, r0, #ARM_AUXCR_L2EN @ Enable L2 cache
+ mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg
+
+ /* Enable L1 caches */
+ mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg
+ orr r0, r0, #ARM_CTRL_ICACHE @ Enable ICache
+ orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache
+ mcr p15, 0, r0, c1, c0, 0 @ Update system control reg
+
+ /* Restore registers */
+ ldmfd sp!, {r4,r5,r6,r7,r9,r10,r11}
+ mov pc, lr
+
+ .type cpu_do_suspend, #object
+ENTRY(cpu_do_suspend)
+ .word cpu_do_suspend_workaround
+ .size cpu_do_suspend_workaround, . - cpu_do_suspend_workaround
diff --git a/arch/arm/mach-mx5/usb.h b/arch/arm/mach-mx5/usb.h
new file mode 100644
index 00000000000..c059f7409e6
--- /dev/null
+++ b/arch/arm/mach-mx5/usb.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <mach/common.h>
+#include "devices.h"
+
+extern int usbotg_init(struct platform_device *pdev);
+extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
+extern struct platform_device *host_pdev_register(struct resource *res,
+ int n_res, struct fsl_usb2_platform_data *config);
+
+extern int fsl_usb_host_init(struct platform_device *pdev);
+extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbotg_utmi_active(void);
+extern void gpio_usbotg_utmi_inactive(void);
+
+extern void __init mx5_usb_dr_init(void);
+extern void __init mx5_usbh1_init(void);
+extern void __init mx5_usbh2_init(void);
+
+typedef void (*driver_vbus_func)(bool);
+extern void mx5_set_host1_vbus_func(driver_vbus_func);
+extern void mx5_set_otghost_vbus_func(driver_vbus_func);
+/*
+ * Used to set pdata->operating_mode before registering the platform_device.
+ * If OTG is configured, the controller operates in OTG mode,
+ * otherwise it's either host or device.
+ */
+#ifdef CONFIG_USB_OTG
+#define DR_UDC_MODE FSL_USB2_DR_OTG
+#define DR_HOST_MODE FSL_USB2_DR_OTG
+#else
+#define DR_UDC_MODE FSL_USB2_DR_DEVICE
+#define DR_HOST_MODE FSL_USB2_DR_HOST
+#endif
+
+extern void __iomem *imx_otg_base;
diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
new file mode 100755
index 00000000000..ae4df535d1e
--- /dev/null
+++ b/arch/arm/mach-mx5/usb_dr.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#define DEBUG 1
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <mach/arc_otg.h>
+#include <mach/hardware.h>
+#include <linux/delay.h>
+#include "usb.h"
+static int usbotg_init_ext(struct platform_device *pdev);
+static void usbotg_uninit_ext(struct platform_device *pdev);
+static void usbotg_clock_gate(bool on);
+
+static struct clk *usb_phy1_clk;
+static struct clk *usb_oh3_clk;
+static struct clk *usb_ahb_clk;
+static void usbotg_wakeup_event_clear(void);
+extern int clk_get_usecount(struct clk *clk);
+
+/* Beginning of Common operation for DR port */
+
+/*
+ * platform data structs
+ * - Which one to use is determined by CONFIG options in usb.h
+ * - operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data dr_utmi_config = {
+ .name = "DR",
+ .init = usbotg_init_ext,
+ .exit = usbotg_uninit_ext,
+ .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
+ .power_budget = 500, /* 500 mA max power */
+ .usb_clock_for_pm = usbotg_clock_gate,
+ .transceiver = "utmi",
+};
+
+/* Platform data for wakeup operation */
+static struct fsl_usb2_wakeup_platform_data dr_wakeup_config = {
+ .name = "DR wakeup",
+ .usb_clock_for_pm = usbotg_clock_gate,
+ .usb_wakeup_exhandle = usbotg_wakeup_event_clear,
+};
+/* Notes: configure USB clock*/
+static int usbotg_init_ext(struct platform_device *pdev)
+{
+ struct clk *usb_clk;
+
+ /* the usb_ahb_clk will be enabled in usb_otg_init */
+ usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
+
+ usb_clk = clk_get(NULL, "usboh3_clk");
+ clk_enable(usb_clk);
+ usb_oh3_clk = usb_clk;
+
+ usb_clk = clk_get(NULL, "usb_phy1_clk");
+ clk_enable(usb_clk);
+ usb_phy1_clk = usb_clk;
+
+ return usbotg_init(pdev);
+}
+
+static void usbotg_uninit_ext(struct platform_device *pdev)
+{
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+ clk_disable(usb_phy1_clk);
+ clk_put(usb_phy1_clk);
+
+ clk_disable(usb_oh3_clk);
+ clk_put(usb_oh3_clk);
+
+ /* usb_ahb_clk will be disabled at usb_common.c */
+ usbotg_uninit(pdata);
+ clk_put(usb_ahb_clk);
+}
+
+/* Below two macros are used at otg mode to indicate usb mode*/
+#define ENABLED_BY_HOST (0x1 << 0)
+#define ENABLED_BY_DEVICE (0x1 << 1)
+static u32 wakeup_irq_enable_src; /* only useful at otg mode */
+static void __wakeup_irq_enable(bool on, int source)
+ {
+ /* otg host and device share the OWIE bit, only when host and device
+ * all enable the wakeup irq, we can enable the OWIE bit
+ */
+ if (on) {
+#ifdef CONFIG_USB_OTG
+ wakeup_irq_enable_src |= source;
+ if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
+ USBCTRL |= UCTRL_OWIE;
+ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
+ }
+#else
+ USBCTRL |= UCTRL_OWIE;
+ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2;
+#endif
+ } else {
+ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2;
+ USBCTRL &= ~UCTRL_OWIE;
+ wakeup_irq_enable_src &= ~source;
+ /* The interrupt must be disabled for at least 3 clock
+ * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+ udelay(100);
+ }
+}
+
+static u32 low_power_enable_src; /* only useful at otg mode */
+static void __phy_lowpower_suspend(bool enable, int source)
+{
+ if (enable) {
+ low_power_enable_src |= source;
+#ifdef CONFIG_USB_OTG
+ if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
+ pr_debug("phy lowpower enabled\n");
+ UOG_PORTSC1 |= PORTSC_PHCD;
+ }
+#else
+ UOG_PORTSC1 |= PORTSC_PHCD;
+#endif
+ } else {
+ pr_debug("phy lowpower disable\n");
+ UOG_PORTSC1 &= ~PORTSC_PHCD;
+ low_power_enable_src &= ~source;
+ }
+}
+
+static void usbotg_clock_gate(bool on)
+{
+ pr_debug("%s: on is %d\n", __func__, on);
+ if (on) {
+ clk_enable(usb_ahb_clk);
+ clk_enable(usb_oh3_clk);
+ clk_enable(usb_phy1_clk);
+ } else {
+ clk_disable(usb_phy1_clk);
+ clk_disable(usb_oh3_clk);
+ clk_disable(usb_ahb_clk);
+ }
+ pr_debug("usb_ahb_ref_count:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_ahb_clk), clk_get_usecount(usb_phy1_clk));
+}
+
+void mx5_set_otghost_vbus_func(driver_vbus_func driver_vbus)
+{
+ dr_utmi_config.platform_driver_vbus = driver_vbus;
+}
+
+/* The wakeup operation for DR port, it will clear the wakeup irq status
+ * and re-enable the wakeup
+ */
+static void usbotg_wakeup_event_clear(void)
+{
+ int wakeup_req = USBCTRL & UCTRL_OWIR;
+
+ if (wakeup_req != 0) {
+ printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
+ /* Disable OWIE to clear OWIR, wait 3 clock
+ * cycles of standly clock(32KHz)
+ */
+ USBCTRL &= ~UCTRL_OWIE;
+ udelay(100);
+ USBCTRL |= UCTRL_OWIE;
+ }
+}
+/* End of Common operation for DR port */
+
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+extern void fsl_usb_recover_hcd(struct platform_device *pdev);
+/* Beginning of host related operation for DR port */
+static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ __wakeup_irq_enable(enable, ENABLED_BY_HOST);
+ /* host only care the ID change wakeup event */
+ if (enable) {
+ pr_debug("host wakeup enable\n");
+ USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN;
+ } else {
+ pr_debug("host wakeup disable\n");
+ USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN;
+ /* The interrupt must be disabled for at least 3 clock
+ * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+ udelay(100);
+ }
+}
+
+static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ __phy_lowpower_suspend(enable, ENABLED_BY_HOST);
+}
+
+static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+ int wakeup_req = USBCTRL & UCTRL_OWIR;
+ int otgsc = UOG_OTGSC;
+
+ /* if ID change sts, it is a host wakeup event */
+ if (wakeup_req && (otgsc & OTGSC_IS_USB_ID)) {
+ printk(KERN_INFO "otg host ID wakeup\n");
+ /* if host ID wakeup, we must clear the b session change sts */
+ UOG_OTGSC = otgsc & (~OTGSC_IS_USB_ID);
+ return WAKEUP_EVENT_ID;
+ }
+ if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) {
+ printk(KERN_INFO "otg host Remote wakeup\n");
+ return WAKEUP_EVENT_DPDM;
+ }
+
+ return WAKEUP_EVENT_INVALID;
+}
+
+static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+ _host_wakeup_enable(pdata, false);
+ _host_phy_lowpower_suspend(pdata, false);
+ fsl_usb_recover_hcd(&mxc_usbdr_host_device);
+}
+/* End of host related operation for DR port */
+#endif /* CONFIG_USB_EHCI_ARC_OTG */
+
+
+#ifdef CONFIG_USB_GADGET_ARC
+/* Beginning of device related operation for DR port */
+static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ __wakeup_irq_enable(enable, ENABLED_BY_DEVICE);
+ /* if udc is not used by any gadget, we can not enable the vbus wakeup */
+ if (!pdata->port_enables) {
+ USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
+ return;
+ }
+ if (enable) {
+ pr_debug("device wakeup enable\n");
+ USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN;
+ } else {
+ pr_debug("device wakeup disable\n");
+ USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN;
+ }
+}
+
+static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ __phy_lowpower_suspend(enable, ENABLED_BY_DEVICE);
+}
+
+static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+ int wakeup_req = USBCTRL & UCTRL_OWIR;
+ u32 otgsc = 0;
+
+ otgsc = UOG_OTGSC;
+ if (wakeup_req &&
+ (otgsc & OTGSC_STS_USB_ID) &&
+ (otgsc & OTGSC_IS_B_SESSION_VALID)) {
+ printk(KERN_INFO "otg udc wakeup\n");
+ return WAKEUP_EVENT_VBUS;
+ }
+ return WAKEUP_EVENT_INVALID;
+
+}
+
+static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+ _device_wakeup_enable(pdata, false);
+ _device_phy_lowpower_suspend(pdata, false);
+}
+
+/* end of device related operation for DR port */
+#endif /* CONFIG_USB_GADGET_ARC */
+
+#define MX53_OFFSET 0x20000000
+
+void __init mx5_usb_dr_init(void)
+{
+ int ret = 0;
+#ifdef CONFIG_USB_OTG
+ if (cpu_is_mx53() || cpu_is_mx50()) {
+ mx53_usbdr_otg_device.resource[0].start -= MX53_OFFSET;
+ mx53_usbdr_otg_device.resource[0].end -= MX53_OFFSET;
+ }
+ /* wake_up_enalbe is useless, just for usb_register_remote_wakeup execution*/
+ dr_utmi_config.wake_up_enable = _device_wakeup_enable;
+ dr_utmi_config.operating_mode = FSL_USB2_DR_OTG;
+ dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+ ret |= platform_device_add_data(&mx53_usbdr_otg_device, &dr_utmi_config, sizeof(dr_utmi_config));
+ ret |= platform_device_register(&mx53_usbdr_otg_device);
+ dr_wakeup_config.usb_pdata[0] = mx53_usbdr_otg_device.dev.platform_data;
+#endif
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+ if (cpu_is_mx53() || cpu_is_mx50()) {
+ mx53_usbdr_host_device.resource[0].start -= MX53_OFFSET;
+ mx53_usbdr_host_device.resource[0].end -= MX53_OFFSET;
+ }
+ dr_utmi_config.operating_mode = DR_HOST_MODE;
+ dr_utmi_config.wake_up_enable = _host_wakeup_enable;
+ dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend;
+ dr_utmi_config.is_wakeup_event = _is_host_wakeup;
+ dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+ dr_utmi_config.wakeup_handler = host_wakeup_handler;
+ ret |= platform_device_add_data(&mx53_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config));
+ ret |= platform_device_register(&mx53_usbdr_host_device);
+ dr_wakeup_config.usb_pdata[1] = mx53_usbdr_host_device.dev.platform_data;
+#endif
+#ifdef CONFIG_USB_GADGET_ARC
+ if (cpu_is_mx53() || cpu_is_mx50()) {
+ mx53_usbdr_udc_device.resource[0].start -= MX53_OFFSET;
+ mx53_usbdr_udc_device.resource[0].end -= MX53_OFFSET;
+ }
+ dr_utmi_config.operating_mode = DR_UDC_MODE;
+ dr_utmi_config.wake_up_enable = _device_wakeup_enable;
+ dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend;
+ dr_utmi_config.is_wakeup_event = _is_device_wakeup;
+ dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
+ dr_utmi_config.wakeup_handler = device_wakeup_handler;
+ ret |= platform_device_add_data(&mx53_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config));
+ ret |= platform_device_register(&mx53_usbdr_udc_device);
+ dr_wakeup_config.usb_pdata[2] = mx53_usbdr_udc_device.dev.platform_data;
+#endif
+ mx53_usbdr_wakeup_device.dev.platform_data = &dr_wakeup_config;
+ ret |= platform_device_register(&mx53_usbdr_wakeup_device);
+ if (ret)
+ printk(KERN_ERR "%s(%d): error occures while init usb dr \n", __func__, __LINE__);
+}
diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c
new file mode 100644
index 00000000000..0336b16a133
--- /dev/null
+++ b/arch/arm/mach-mx5/usb_h1.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/gpio.h>
+
+#include <asm/delay.h>
+#include <mach/hardware.h>
+#include <mach/arc_otg.h>
+#include <mach/iomux-mx51.h>
+#include <mach/iomux-mx53.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include "usb.h"
+
+static struct clk *usb_phy2_clk;
+static struct clk *usb_oh3_clk;
+static struct clk *usb_ahb_clk;
+extern int clk_get_usecount(struct clk *clk);
+
+#define MX5X_USBH1_STP IMX_GPIO_NR(1, 27)
+#define MX51_3DS_PHY_RESET IMX_GPIO_NR(2, 5)
+
+#ifdef CONFIG_USB_EHCI_ARC
+extern void fsl_usb_recover_hcd(struct platform_device *pdev);
+#else
+static void fsl_usb_recover_hcd(struct platform_device *pdev)
+{; }
+#endif
+/*
+ * USB Host1 HS port
+ */
+static int gpio_usbh1_active(void)
+{
+ iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+ iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D17__GPIO2_1;
+ int ret;
+
+ /* Set USBH1_STP to GPIO and toggle it */
+ mxc_iomux_v3_setup_pad(usbh1stp_gpio);
+ ret = gpio_request(MX5X_USBH1_STP, "usbh1_stp");
+
+ if (ret) {
+ pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
+ return ret;
+ }
+ gpio_direction_output(MX5X_USBH1_STP, 0);
+ gpio_set_value(MX5X_USBH1_STP, 1);
+
+ /* Signal only used on MX51-3DS for reset to PHY.*/
+ if (machine_is_mx51_3ds()) {
+ mxc_iomux_v3_setup_pad(phyreset_gpio);
+ ret = gpio_request(MX51_3DS_PHY_RESET, "eim_d17");
+ if (ret) {
+ pr_debug("failed to get MX51_PAD_EIM_D17__GPIO2_1: %d\n", ret);
+ return ret;
+ }
+ gpio_direction_output(MX51_3DS_PHY_RESET, 0);
+ gpio_set_value(MX51_3DS_PHY_RESET, 1);
+ }
+
+ msleep(100);
+
+ return 0;
+}
+
+static void gpio_usbh1_inactive(void)
+{
+ /* Signal only used on MX51-3DS for reset to PHY.*/
+ if (machine_is_mx51_3ds()) {
+ gpio_free(MX51_3DS_PHY_RESET);
+ }
+ gpio_free(MX5X_USBH1_STP);
+}
+
+
+static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ pr_debug("host1, %s, enable is %d\n", __func__, enable);
+ if (enable)
+ USBCTRL |= UCTRL_H1WIE;
+ else {
+ USBCTRL &= ~UCTRL_H1WIE;
+ /* The interrupt must be disabled for at least 3
+ * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
+ udelay(100);
+ }
+}
+
+static void _phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
+{
+ pr_debug("host1, %s, enable is %d\n", __func__, enable);
+ if (enable) {
+ UH1_PORTSC1 |= PORTSC_PHCD;
+ } else {
+ UH1_PORTSC1 &= ~PORTSC_PHCD;
+ }
+}
+
+static void usbh1_clock_gate(bool on)
+{
+ pr_debug("%s: on is %d\n", __func__, on);
+ if (on) {
+ clk_enable(usb_ahb_clk);
+ clk_enable(usb_oh3_clk);
+ clk_enable(usb_phy2_clk);
+ } else {
+ clk_disable(usb_phy2_clk);
+ clk_disable(usb_oh3_clk);
+ clk_disable(usb_ahb_clk);
+ }
+}
+
+static enum usb_wakeup_event _is_usbh1_wakeup(struct fsl_usb2_platform_data *pdata)
+{
+ int wakeup_req = USBCTRL & UCTRL_H1WIR;
+
+ if (wakeup_req)
+ return !WAKEUP_EVENT_INVALID;
+
+ return WAKEUP_EVENT_INVALID;
+}
+
+static void h1_wakeup_handler(struct fsl_usb2_platform_data *pdata)
+{
+ _wake_up_enable(pdata, false);
+ _phy_lowpower_suspend(pdata, false);
+ fsl_usb_recover_hcd(&mxc_usbh1_device);
+}
+
+static void usbh1_wakeup_event_clear(void)
+{
+ int wakeup_req = USBCTRL & UCTRL_H1WIR;
+
+ if (wakeup_req != 0) {
+ printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
+ /* Disable H1WIE to clear H1WIR, wait 3 clock
+ * cycles of standly clock(32KHz)
+ */
+ USBCTRL &= ~UCTRL_H1WIE;
+ udelay(100);
+ USBCTRL |= UCTRL_H1WIE;
+ }
+}
+static int fsl_usb_host_init_ext(struct platform_device *pdev)
+{
+ iomux_v3_cfg_t usbh1stp_func = MX51_PAD_USBH1_STP__USBH1_STP;
+ struct clk *usb_clk;
+ int ret;
+
+ /* the usb_ahb_clk will be enabled in usb_otg_init */
+ usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
+
+ if (cpu_is_mx53()) {
+ usb_clk = clk_get(NULL, "usboh3_clk");
+ if (usb_clk) {
+ clk_enable(usb_clk);
+ usb_oh3_clk = usb_clk;
+ }
+
+ usb_clk = clk_get(NULL, "usb_phy2_clk");
+ if (usb_clk) {
+ clk_enable(usb_clk);
+ usb_phy2_clk = usb_clk;
+ }
+ } else if (cpu_is_mx50()) {
+ usb_clk = clk_get(NULL, "usb_phy2_clk");
+ if (usb_clk) {
+ clk_enable(usb_clk);
+ usb_phy2_clk = usb_clk;
+ }
+ } else if (cpu_is_mx51()) {
+ usb_clk = clk_get(NULL, "usboh3_clk");
+ if (usb_clk) {
+ clk_enable(usb_clk);
+ usb_oh3_clk = usb_clk;
+ }
+ }
+
+ ret = fsl_usb_host_init(pdev);
+ if (ret)
+ return ret;
+
+ if (cpu_is_mx51()) {
+ /* setback USBH1_STP to be function */
+#if 0 /* Jasper: Need to do... */
+ mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
+ PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
+ PAD_CTL_DRV_VOT_LOW);
+ gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
+#endif
+ mxc_iomux_v3_setup_pad(usbh1stp_func);
+ gpio_free(MX5X_USBH1_STP);
+ }
+
+ /* disable remote wakeup irq */
+ USBCTRL &= ~UCTRL_H1WIE;
+ return 0;
+}
+
+static void fsl_usb_host_uninit_ext(struct platform_device *pdev)
+{
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+ if (cpu_is_mx53()) {
+ if (usb_oh3_clk) {
+ clk_disable(usb_oh3_clk);
+ clk_put(usb_oh3_clk);
+ }
+
+ if (usb_phy2_clk) {
+ clk_disable(usb_phy2_clk);
+ clk_put(usb_phy2_clk);
+ }
+ } else if (cpu_is_mx50()) {
+ if (usb_phy2_clk) {
+ clk_disable(usb_phy2_clk);
+ clk_put(usb_phy2_clk);
+ }
+ } else if (cpu_is_mx51()) {
+ if (usb_oh3_clk) {
+ clk_disable(usb_oh3_clk);
+ clk_put(usb_oh3_clk);
+ }
+ }
+
+ fsl_usb_host_uninit(pdata);
+ /* usb_ahb_clk will be disabled at usb_common.c */
+ clk_put(usb_ahb_clk);
+}
+
+static struct fsl_usb2_platform_data usbh1_config = {
+ .name = "Host 1",
+ .init = fsl_usb_host_init_ext,
+ .exit = fsl_usb_host_uninit_ext,
+ .operating_mode = FSL_USB2_MPH_HOST,
+ .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
+ .power_budget = 500, /* 500 mA max power */
+ .wake_up_enable = _wake_up_enable,
+ .usb_clock_for_pm = usbh1_clock_gate,
+ .phy_lowpower_suspend = _phy_lowpower_suspend,
+ .is_wakeup_event = _is_usbh1_wakeup,
+ .wakeup_handler = h1_wakeup_handler,
+ .transceiver = "utmi",
+};
+
+static struct fsl_usb2_wakeup_platform_data usbh1_wakeup_config = {
+ .name = "USBH1 wakeup",
+ .usb_clock_for_pm = usbh1_clock_gate,
+ .usb_pdata = {&usbh1_config, NULL, NULL},
+ .usb_wakeup_exhandle = usbh1_wakeup_event_clear,
+};
+
+void mx5_set_host1_vbus_func(driver_vbus_func driver_vbus)
+{
+ usbh1_config.platform_driver_vbus = driver_vbus;
+}
+
+#define MX53_OFFSET 0x20000000
+void __init mx5_usbh1_init(void)
+{
+ if (cpu_is_mx51()) {
+ usbh1_config.phy_mode = FSL_USB2_PHY_ULPI;
+ usbh1_config.transceiver = "isp1504";
+ usbh1_config.gpio_usb_active = gpio_usbh1_active;
+ usbh1_config.gpio_usb_inactive = gpio_usbh1_inactive;
+ }
+ if (cpu_is_mx53() || cpu_is_mx50()) {
+ mx53_usbh1_device.resource[0].start -= MX53_OFFSET;
+ mx53_usbh1_device.resource[0].end -= MX53_OFFSET;
+ }
+ if (cpu_is_mx53()) {
+ usbh1_config.wakeup_pdata = &usbh1_wakeup_config;
+
+ mx53_usbh1_device.dev.platform_data = &usbh1_config;
+ platform_device_register(&mx53_usbh1_device);
+
+ mx53_usbh1_wakeup_device.dev.platform_data = &usbh1_wakeup_config;
+ platform_device_register(&mx53_usbh1_wakeup_device);
+ }
+}
+
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b3a1f2b3ada..1c920b2b881 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -39,6 +39,12 @@ source "arch/arm/mach-mx5/Kconfig"
endmenu
+# set if we need the UTMI transceiver
+config UTMI_MXC
+ bool
+ default y
+ depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX37 || ARCH_MX503
+
config MXC_IRQ_PRIOR
bool "Use IRQ priority"
help
@@ -106,4 +112,11 @@ config IRAM_ALLOC
bool
select GENERIC_ALLOCATOR
+config CLK_DEBUG
+ bool "clock debug information export to user space"
+ depends on PM_DEBUG && DEBUG_FS
+ default n
+ help
+ export clk debug information to user space
+
endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index b9f0f5f499a..bc2a8237dae 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -25,3 +25,11 @@ obj-y += ssi-fiq-ksym.o
endif
obj-y += devices/
+
+obj-$(CONFIG_ARCH_MX5) += dvfs_core.o
+
+# DVFS-PER support
+obj-$(CONFIG_MXC_DVFS_PER) += dvfs_per.o
+obj-$(CONFIG_UTMI_MXC) += utmixc.o
+
+obj-$(CONFIG_USB_EHCI_ARC) += usb_common.o usb_wakeup.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab173ad..5643be65e46 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -4,7 +4,7 @@
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -37,6 +37,8 @@
#include <linux/proc_fs.h>
#include <linux/semaphore.h>
#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
#include <mach/clock.h>
#include <mach/hardware.h>
@@ -110,6 +112,24 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
+/*!
+ * @brief Function to get the usage count for the requested clock.
+ *
+ * This function returns the reference count for the clock.
+ *
+ * @param clk Handle to clock to disable.
+ *
+ * @return Returns the usage count for the requested clock.
+ */
+int clk_get_usecount(struct clk *clk)
+{
+ if (clk == NULL || IS_ERR(clk))
+ return 0;
+
+ return clk->usecount;
+}
+EXPORT_SYMBOL(clk_get_usecount);
+
/* Retrieve the *current* clock rate. If the clock itself
* does not provide a special calculation routine, ask
* its parent and so on, until one is able to return
@@ -244,3 +264,122 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
return ll;
}
+
+#ifdef CONFIG_CLK_DEBUG
+/*
+ * debugfs support to trace clock tree hierarchy and attributes
+ */
+static int clk_debug_rate_get(void *data, u64 *val)
+{
+ struct clk *clk = data;
+
+ *val = (u64)clk_get_rate(clk);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(clk_debug_rate_fops, clk_debug_rate_get, NULL,
+ "%llu\n");
+
+
+static struct dentry *clk_root;
+static int clk_debug_register_one(struct clk *clk)
+{
+ int err;
+ struct dentry *d, *child, *child_tmp;
+ struct clk *pa = clk_get_parent(clk);
+
+ if (pa && !IS_ERR(pa))
+ d = debugfs_create_dir(clk->name, pa->dentry);
+ else {
+ if (!clk_root)
+ clk_root = debugfs_create_dir("clock", NULL);
+ if (!clk_root)
+ return -ENOMEM;
+ d = debugfs_create_dir(clk->name, clk_root);
+ }
+
+ if (!d)
+ return -ENOMEM;
+
+ clk->dentry = d;
+
+ d = debugfs_create_u8("enable_count", S_IRUGO, clk->dentry,
+ (u8 *)&clk->usecount);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ d = debugfs_create_file("rate", S_IRUGO, clk->dentry, (void *)clk,
+ &clk_debug_rate_fops);
+ if (!d) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ return 0;
+
+err_out:
+ d = clk->dentry;
+ list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+ debugfs_remove(child);
+ debugfs_remove(clk->dentry);
+ return err;
+}
+
+struct preinit_clk {
+ struct list_head list;
+ struct clk *clk;
+};
+static LIST_HEAD(preinit_clks);
+static DEFINE_MUTEX(preinit_lock);
+static int init_done;
+
+void clk_debug_register(struct clk *clk)
+{
+ int err;
+ struct clk *pa;
+
+ if (init_done) {
+ pa = clk_get_parent(clk);
+
+ if (pa && !IS_ERR(pa) && !pa->dentry)
+ clk_debug_register(pa);
+
+ if (!clk->dentry) {
+ err = clk_debug_register_one(clk);
+ if (err)
+ return;
+ }
+ } else {
+ struct preinit_clk *p;
+ mutex_lock(&preinit_lock);
+ p = kmalloc(sizeof(*p), GFP_KERNEL);
+ if (p) {
+ p->clk = clk;
+ list_add(&p->list, &preinit_clks);
+ }
+ mutex_unlock(&preinit_lock);
+ }
+}
+EXPORT_SYMBOL_GPL(clk_debug_register);
+
+static int __init clk_debugfs_init(void)
+{
+ struct preinit_clk *pclk, *tmp;
+
+ init_done = 1;
+
+ mutex_lock(&preinit_lock);
+ list_for_each_entry(pclk, &preinit_clks, list) {
+ clk_debug_register(pclk->clk);
+ }
+
+ list_for_each_entry_safe(pclk, tmp, &preinit_clks, list) {
+ list_del(&pclk->list);
+ kfree(pclk);
+ }
+ mutex_unlock(&preinit_lock);
+ return 0;
+}
+late_initcall(clk_debugfs_init);
+#endif
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237..4fdf4a80c59 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -18,3 +18,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
pr_info("CPU identified as %s, silicon rev %d.%d\n",
cpu, (srev >> 4) & 0xf, srev & 0xf);
}
+
+int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */
+int uart_at_24; /* OFF: 0 (default); ON: 1 */
+/*
+ * Here are the JTAG options from the command line. By default JTAG
+ * is OFF which means JTAG is not connected and WFI is enabled
+ *
+ * "on" -- JTAG is connected, so WFI is disabled
+ * "off" -- JTAG is disconnected, so WFI is enabled
+ */
+
+static int __init jtag_wfi_setup(char *p)
+{
+ if (memcmp(p, "on", 2) == 0) {
+ mxc_jtag_enabled = 1;
+ p += 2;
+ } else if (memcmp(p, "off", 3) == 0) {
+ mxc_jtag_enabled = 0;
+ p += 3;
+ }
+ return 0;
+}
+early_param("jtag", jtag_wfi_setup);
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 73db34bf588..7e8bc5cdfe8 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -39,7 +39,7 @@ static struct cpufreq_frequency_table *imx_freq_table;
static int cpu_op_nr;
static struct cpu_op *cpu_op_tbl;
-static int set_cpu_freq(int freq)
+int set_cpu_freq(int freq)
{
int ret = 0;
int org_cpu_rate;
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index cb3e3eef55c..f7161253297 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -22,6 +22,9 @@ config IMX_HAVE_PLATFORM_IMX2_WDT
config IMX_HAVE_PLATFORM_IMXDI_RTC
bool
+config IMX_HAVE_PLATFORM_IMX_SRTC
+ bool
+
config IMX_HAVE_PLATFORM_IMX_FB
bool
@@ -43,6 +46,15 @@ config IMX_HAVE_PLATFORM_IMX_UART
config IMX_HAVE_PLATFORM_IMX_UDC
bool
+config IMX_HAVE_PLATFORM_IMX_IPUV3
+ bool
+
+config IMX_HAVE_PLATFORM_IMX_TVE
+ bool
+
+config IMX_HAVE_PLATFORM_LDB
+ bool
+
config IMX_HAVE_PLATFORM_IPU_CORE
bool
@@ -55,6 +67,9 @@ config IMX_HAVE_PLATFORM_MX2_CAMERA
config IMX_HAVE_PLATFORM_MXC_EHCI
bool
+config IMX_HAVE_PLATFORM_MXC_GPU
+ bool
+
config IMX_HAVE_PLATFORM_MXC_MMC
bool
@@ -80,6 +95,15 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
config IMX_HAVE_PLATFORM_SPI_IMX
bool
+config IMX_HAVE_PLATFORM_IMX_IIM
+ bool
+
config IMX_HAVE_PLATFORM_AHCI
bool
default y if ARCH_MX53
+
+config IMX_HAVE_PLATFORM_IMX_VPU
+ bool
+
+config IMX_HAVE_PLATFORM_IMX_SPDIF
+ bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index c11ac8472be..615d32f7ef4 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -6,6 +6,7 @@ obj-y += platform-gpio-mxc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC) += platform-imx_srtc.o
obj-y += platform-imx-dma.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
@@ -15,9 +16,14 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3) += platform-imx_ipuv3.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_TVE) += platform-imx_tve.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_VPU) += platform-imx_vpu.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_LDB) += platform-imx_ldb.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_GPU) += platform-mxc_gpu.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
@@ -26,4 +32,8 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_IIM) += platform-imx-iim.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) += platform-ahci-imx.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-dai.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-audio.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-iim.c b/arch/arm/plat-mxc/devices/platform-imx-iim.c
new file mode 100644
index 00000000000..74043ded3c0
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-iim.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_iim_data_entry_single(soc) \
+ { \
+ .iobase = soc ## _IIM_BASE_ADDR, \
+ .irq = soc ## _INT_IIM, \
+ }
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_iim_data imx51_imx_iim_data __initconst =
+ imx5_iim_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_iim_data imx53_imx_iim_data __initconst =
+ imx5_iim_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_iim(
+ const struct imx_iim_data *data,
+ const struct mxc_iim_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_16 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_add_platform_device("mxc_iim", 0,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c
new file mode 100644
index 00000000000..4a0cb7bf9a1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-audio.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spdif_audio_device(void)
+{
+ return imx_add_platform_device("imx-spdif-audio-device", 0,
+ NULL, 0, NULL, 0);
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c
new file mode 100644
index 00000000000..516ebc52467
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif-dai.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define MXC_SPDIF_TX_REG 0x2C
+#define MXC_SPDIF_RX_REG 0x14
+
+#define imx_spdif_dai_data_entry(soc) \
+ { \
+ .iobase = soc ## _SPDIF_BASE_ADDR, \
+ .dmatx = soc ## _DMA_REQ_SPDIF_TX, \
+ .dmarx = soc ## _DMA_REQ_SPDIF_RX, \
+ }
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_spdif_dai_data imx51_spdif_dai_data __initconst = {
+ .iobase = MX51_SPDIF_BASE_ADDR,
+ .dmatx = MX51_DMA_REQ_SPDIF,
+ };
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spdif_dai_data imx53_spdif_dai_data __initconst =
+ imx_spdif_dai_data_entry(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_spdif_dai(
+ const struct imx_spdif_dai_data *data)
+{
+ struct resource res[] = {
+ {
+ .name = "tx_reg",
+ .start = data->iobase + MXC_SPDIF_TX_REG,
+ .end = data->iobase + MXC_SPDIF_TX_REG,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .name = "rx_reg",
+ .start = data->iobase + MXC_SPDIF_RX_REG,
+ .end = data->iobase + MXC_SPDIF_RX_REG,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .name = "tx",
+ .start = data->dmatx,
+ .end = data->dmatx,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .name = "rx",
+ .start = data->dmarx,
+ .end = data->dmarx,
+ .flags = IORESOURCE_DMA,
+ },
+ };
+
+ return imx_add_platform_device("imx-spdif-dai", 0,
+ res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdif.c b/arch/arm/plat-mxc/devices/platform-imx-spdif.c
new file mode 100644
index 00000000000..80a5e782067
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-spdif.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_spdif_data_entry_single(soc) \
+ { \
+ .iobase = soc ## _SPDIF_BASE_ADDR, \
+ .irq = soc ## _INT_SPDIF, \
+ }
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_spdif_data imx50_imx_spdif_data __initconst =
+ imx5_spdif_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX50 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_spdif_data imx51_imx_spdif_data __initconst =
+ imx5_spdif_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_spdif_data imx53_imx_spdif_data __initconst =
+ imx5_spdif_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_spdif(
+ const struct imx_spdif_data *data,
+ const struct mxc_spdif_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + 0x50,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_add_platform_device("mxc_spdif", 0,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c
new file mode 100644
index 00000000000..a353060bc95
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_ipuv3.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#define imx5_ipuv3_data_entry_single(soc, size, ipu_init, ipu_pg) \
+ { \
+ .iobase = soc ## _IPU_CTRL_BASE_ADDR, \
+ .irq_err = soc ## _INT_IPU_ERR, \
+ .irq = soc ## _INT_IPU_SYN, \
+ .irq_start = MXC_IPU_IRQ_START, \
+ .iosize = size, \
+ .init = ipu_init, \
+ .pg = ipu_pg, \
+ }
+
+#define imx6_ipuv3_data_entry_single(soc, id, size, ipu_init, ipu_pg) \
+ { \
+ .iobase = soc ## _IPU ## id ## _ARB_BASE_ADDR, \
+ .irq_err = soc ## _INT_IPU ## id ## _ERR, \
+ .irq = soc ## _INT_IPU ## id ## _SYN, \
+ .irq_start = MXC_IPU_IRQ_START, \
+ .iosize = size, \
+ .init = ipu_init, \
+ .pg = ipu_pg, \
+ }
+
+#ifdef CONFIG_SOC_IMX51
+/*
+ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
+ * the Freescale marketing division. However this did not remove the
+ * hardware from the chip which still needs to be configured...
+ */
+static int __init ipu_mipi_setup(void)
+{
+ struct clk *hsc_clk;
+ void __iomem *hsc_addr;
+ int ret = 0;
+
+ hsc_addr = ioremap(MX51_MIPI_HSC_BASE_ADDR, PAGE_SIZE);
+ if (!hsc_addr)
+ return -ENOMEM;
+
+ hsc_clk = clk_get_sys(NULL, "mipi_hsp");
+ if (IS_ERR(hsc_clk)) {
+ ret = PTR_ERR(hsc_clk);
+ goto unmap;
+ }
+ clk_enable(hsc_clk);
+
+ /* setup MIPI module to legacy mode */
+ writel(0xF00, hsc_addr);
+
+ /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
+ writel(readl(hsc_addr + 0x800) | 0x30ff,
+ hsc_addr + 0x800);
+
+ clk_disable(hsc_clk);
+ clk_put(hsc_clk);
+unmap:
+ iounmap(hsc_addr);
+
+ return ret;
+}
+
+int __init mx51_ipuv3_init(int id)
+{
+ int ret = 0;
+ u32 val;
+
+ ret = ipu_mipi_setup();
+
+ /* hard reset the IPU */
+ val = readl(MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
+ val |= 1 << 3;
+ writel(val, MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
+
+ return ret;
+}
+
+void mx51_ipuv3_pg(int enable)
+{
+ if (enable) {
+ writel(MXC_PGCR_PCR, MX51_PGC_IPU_PGCR);
+ writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+ } else {
+ writel(0x0, MX51_PGC_IPU_PGCR);
+ if (readl(MX51_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+ printk(KERN_DEBUG "power gating successful\n");
+ writel(MXC_PGSR_PSR, MX51_PGC_IPU_PGSR);
+ }
+}
+
+const struct imx_ipuv3_data imx51_ipuv3_data __initconst =
+ imx5_ipuv3_data_entry_single(MX51, SZ_512M,
+ mx51_ipuv3_init, mx51_ipuv3_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+int __init mx53_ipuv3_init(int id)
+{
+ int ret = 0;
+ u32 val;
+
+ /* hard reset the IPU */
+ val = readl(MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR));
+ val |= 1 << 3;
+ writel(val, MX53_IO_ADDRESS(MX53_SRC_BASE_ADDR));
+
+ return ret;
+}
+
+void mx53_ipuv3_pg(int enable)
+{
+ if (enable) {
+ writel(MXC_PGCR_PCR, MX53_PGC_IPU_PGCR);
+ writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+ } else {
+ writel(0x0, MX53_PGC_IPU_PGCR);
+ if (readl(MX53_PGC_IPU_PGSR) & MXC_PGSR_PSR)
+ printk(KERN_DEBUG "power gating successful\n");
+ writel(MXC_PGSR_PSR, MX53_PGC_IPU_PGSR);
+ }
+}
+
+const struct imx_ipuv3_data imx53_ipuv3_data __initconst =
+ imx5_ipuv3_data_entry_single(MX53, SZ_128M,
+ mx53_ipuv3_init, mx53_ipuv3_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+int __init mx6q_ipuv3_init(int id)
+{
+ int ret = 0;
+ u32 val;
+
+ /* hard reset the IPU */
+ val = readl(MX6_IO_ADDRESS(SRC_BASE_ADDR));
+ if (id == 0)
+ val |= 1 << 3;
+ else
+ val |= 1 << 12;
+ writel(val, MX6_IO_ADDRESS(SRC_BASE_ADDR));
+
+ return ret;
+}
+
+void mx6q_ipuv3_pg(int enable)
+{
+ /*TODO*/
+}
+
+const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst = {
+ imx6_ipuv3_data_entry_single(MX6Q, 1, SZ_4M,
+ mx6q_ipuv3_init, mx6q_ipuv3_pg),
+ imx6_ipuv3_data_entry_single(MX6Q, 2, SZ_4M,
+ mx6q_ipuv3_init, mx6q_ipuv3_pg),
+};
+#endif
+
+struct platform_device *__init imx_add_ipuv3(
+ const int id,
+ const struct imx_ipuv3_data *data,
+ struct imx_ipuv3_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + data->iosize - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq_err,
+ .end = data->irq_err,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ pdata->init = data->init;
+ pdata->pg = data->pg;
+
+ return imx_add_platform_device_dmamask("imx-ipuv3", id,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+ DMA_BIT_MASK(32));
+}
+
+struct platform_device *__init imx_add_ipuv3_fb(
+ const int id,
+ const struct ipuv3_fb_platform_data *pdata)
+{
+ if (pdata->res_size > 0) {
+ struct resource res[] = {
+ {
+ .start = pdata->res_base,
+ .end = pdata->res_base + pdata->res_size - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ return imx_add_platform_device_dmamask("mxc_sdc_fb",
+ id, res, ARRAY_SIZE(res), pdata,
+ sizeof(*pdata), DMA_BIT_MASK(32));
+ } else
+ return imx_add_platform_device_dmamask("mxc_sdc_fb", id,
+ NULL, 0, pdata, sizeof(*pdata),
+ DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_ldb.c b/arch/arm/plat-mxc/devices/platform-imx_ldb.c
new file mode 100644
index 00000000000..0269a8165b2
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_ldb.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <linux/clk.h>
+
+#define imx_ldb_data_entry_single(soc, size) \
+ { \
+ .iobase = soc ## _IOMUXC_BASE_ADDR, \
+ .iosize = size, \
+ }
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_ldb_data imx53_ldb_data __initconst =
+ imx_ldb_data_entry_single(MX53, SZ_4K);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+const struct imx_ldb_data imx6q_ldb_data __initconst =
+ imx_ldb_data_entry_single(MX6Q, SZ_4K);
+#endif
+
+struct platform_device *__init imx_add_ldb(
+ const struct imx_ldb_data *data,
+ struct fsl_mxc_ldb_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + data->iosize - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ return imx_add_platform_device("mxc_ldb", -1,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_srtc.c b/arch/arm/plat-mxc/devices/platform-imx_srtc.c
new file mode 100644
index 00000000000..9e4191ecd52
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_srtc.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_srtc_data_entry_single(soc) \
+ { \
+ .iobase = soc ## _SRTC_BASE_ADDR, \
+ .irq = soc ## _INT_SRTC_NTZ, \
+ }
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_srtc_data imx50_imx_srtc_data __initconst =
+ imx_imx_srtc_data_entry_single(MX50);
+#endif /* ifdef CONFIG_SOC_IMX50 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_srtc_data imx51_imx_srtc_data __initconst =
+ imx_imx_srtc_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_srtc_data imx53_imx_srtc_data __initconst =
+ imx_imx_srtc_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_srtc(
+ const struct imx_srtc_data *data)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_add_platform_device("mxc_rtc", 0,
+ res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_tve.c b/arch/arm/plat-mxc/devices/platform-imx_tve.c
new file mode 100644
index 00000000000..7ab501a605c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_tve.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Jason Chen <jason.chen@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_tve_data_entry_single(soc) \
+ { \
+ .iobase = soc ## _TVE_BASE_ADDR, \
+ .irq = soc ## _INT_TVE, \
+ }
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_tve_data imx51_tve_data __initconst =
+ imx5_tve_data_entry_single(MX51);
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_tve_data imx53_tve_data __initconst =
+ imx5_tve_data_entry_single(MX53);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
+struct platform_device *__init imx_add_tve(
+ const struct imx_tve_data *data,
+ const struct fsl_mxc_tve_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_add_platform_device("mxc_tve", -1,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_vpu.c b/arch/arm/plat-mxc/devices/platform-imx_vpu.c
new file mode 100644
index 00000000000..a3a3927e535
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_vpu.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Jason Chen <jason.chen@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx5_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg) \
+ { \
+ .iobase = soc ## _VPU_BASE_ADDR, \
+ .irq_ipi = soc ## _INT_VPU, \
+ .iram_enable = flag, \
+ .iram_size = size, \
+ .reset = vpu_reset, \
+ .pg = vpu_pg, \
+ }
+
+#define imx6_vpu_data_entry_single(soc, flag, size, vpu_reset, vpu_pg) \
+ { \
+ .iobase = soc ## _VPU_BASE_ADDR, \
+ .irq_ipi = soc ## _INT_VPU_IPI, \
+ .irq_jpg = soc ## _INT_VPU_JPG, \
+ .iram_enable = flag, \
+ .iram_size = size, \
+ .reset = vpu_reset, \
+ .pg = vpu_pg, \
+ }
+
+#ifdef CONFIG_SOC_IMX51
+void mx51_vpu_reset(void)
+{
+ u32 reg;
+ void __iomem *src_base;
+
+ src_base = ioremap(MX51_SRC_BASE_ADDR, PAGE_SIZE);
+
+ /* mask interrupt due to vpu passed reset */
+ reg = __raw_readl(src_base + 0x18);
+ reg |= 0x02;
+ __raw_writel(reg, src_base + 0x18);
+
+ reg = __raw_readl(src_base);
+ reg |= 0x5; /* warm reset vpu */
+ __raw_writel(reg, src_base);
+ while (__raw_readl(src_base) & 0x04)
+ ;
+
+ iounmap(src_base);
+}
+
+void mx51_vpu_pg(int enable)
+{
+ if (enable) {
+ __raw_writel(MXC_PGCR_PCR, MX51_PGC_VPU_PGCR);
+ __raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR);
+ } else {
+ __raw_writel(0x0, MX51_PGC_VPU_PGCR);
+ if (__raw_readl(MX51_PGC_VPU_PGSR) & MXC_PGSR_PSR)
+ printk(KERN_DEBUG "power gating successful\n");
+ __raw_writel(MXC_PGSR_PSR, MX51_PGC_VPU_PGSR);
+ }
+}
+const struct imx_vpu_data imx51_vpu_data __initconst =
+ imx5_vpu_data_entry_single(MX51,
+ false, 0x14000, mx51_vpu_reset, mx51_vpu_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+void mx53_vpu_reset(void)
+{
+ u32 reg;
+ void __iomem *src_base;
+
+ src_base = ioremap(MX53_SRC_BASE_ADDR, PAGE_SIZE);
+
+ /* mask interrupt due to vpu passed reset */
+ reg = __raw_readl(src_base + 0x18);
+ reg |= 0x02;
+ __raw_writel(reg, src_base + 0x18);
+
+ reg = __raw_readl(src_base);
+ reg |= 0x5; /* warm reset vpu */
+ __raw_writel(reg, src_base);
+ while (__raw_readl(src_base) & 0x04)
+ ;
+
+ iounmap(src_base);
+}
+
+void mx53_vpu_pg(int enable)
+{
+ if (enable) {
+ __raw_writel(MXC_PGCR_PCR, MX53_PGC_VPU_PGCR);
+ __raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR);
+ } else {
+ __raw_writel(0x0, MX53_PGC_VPU_PGCR);
+ if (__raw_readl(MX53_PGC_VPU_PGSR) & MXC_PGSR_PSR)
+ printk(KERN_DEBUG "power gating successful\n");
+ __raw_writel(MXC_PGSR_PSR, MX53_PGC_VPU_PGSR);
+ }
+}
+
+const struct imx_vpu_data imx53_vpu_data __initconst =
+ imx5_vpu_data_entry_single(MX53,
+ true, 0x14000, mx53_vpu_reset, mx53_vpu_pg);
+#endif
+
+#ifdef CONFIG_SOC_IMX6Q
+const struct imx_vpu_data imx6q_vpu_data __initconst =
+ imx6_vpu_data_entry_single(MX6Q,
+ true, 0x21000, NULL, NULL);
+#endif
+
+struct platform_device *__init imx_add_vpu(
+ const struct imx_vpu_data *data)
+{
+ struct mxc_vpu_platform_data pdata;
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq_ipi,
+ .end = data->irq_ipi,
+ .flags = IORESOURCE_IRQ,
+ },
+#ifdef CONFIG_SOC_IMX6Q
+ {
+ .start = data->irq_jpg,
+ .end = data->irq_jpg,
+ .flags = IORESOURCE_IRQ,
+ },
+#endif
+ };
+
+ pdata.reset = data->reset;
+ pdata.pg = data->pg;
+ pdata.iram_enable = data->iram_enable;
+ pdata.iram_size = data->iram_size;
+
+ return imx_add_platform_device("mxc_vpu", -1,
+ res, ARRAY_SIZE(res), &pdata, sizeof(pdata));
+}
+
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_gpu.c b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
new file mode 100644
index 00000000000..6b0b48b0197
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_gpu.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/dma-mapping.h>
+
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_gpu_entry_3d_2d(soc) \
+ { \
+ .irq_3d = soc ## _INT_GPU, \
+ .irq_2d = soc ## _INT_GPU2_IRQ, \
+ .iobase_3d = soc ## _GPU_BASE_ADDR, \
+ .iobase_2d = soc ## _GPU2D_BASE_ADDR, \
+ .gmem_base = soc ## _GPU_GMEM_BASE_ADDR, \
+ .gmem_size = soc ## _GPU_GMEM_SIZE, \
+ }
+
+#define imx_mxc_gpu_entry_2d(soc) \
+ { \
+ .irq_2d = soc ## _INT_GPU2_IRQ, \
+ .iobase_2d = soc ## _GPU2D_BASE_ADDR, \
+ }
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_gpu_data imx35_gpu_data __initconst =
+ imx_mxc_gpu_entry_2d(MX35);
+#endif
+
+#ifdef CONFIG_SOC_IMX50
+const struct imx_mxc_gpu_data imx50_gpu_data __initconst =
+ imx_mxc_gpu_entry_2d(MX50);
+#endif
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_mxc_gpu_data imx51_gpu_data __initconst =
+ imx_mxc_gpu_entry_3d_2d(MX51);
+#endif
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_mxc_gpu_data imx53_gpu_data __initconst =
+ imx_mxc_gpu_entry_3d_2d(MX53);
+#endif
+
+struct platform_device *__init imx_add_mxc_gpu(
+ const struct imx_mxc_gpu_data *data,
+ const struct mxc_gpu_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->irq_2d,
+ .end = data->irq_2d,
+ .name = "gpu_2d_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = data->irq_3d,
+ .end = data->irq_3d,
+ .name = "gpu_3d_irq",
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = data->iobase_2d,
+ .end = data->iobase_2d + SZ_4K - 1,
+ .name = "gpu_2d_registers",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = data->iobase_3d,
+ .end = data->iobase_3d + SZ_128K - 1,
+ .name = "gpu_3d_registers",
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = data->gmem_base,
+ .end = data->gmem_base + data->gmem_size - 1,
+ .name = "gpu_graphics_mem",
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ return imx_add_platform_device_dmamask("mxc_gpu", 0,
+ res, ARRAY_SIZE(res),
+ pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
index b0c4ae29811..18cfd07ab41 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -49,6 +49,15 @@ const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_mxc_pwm_data imx53_mxc_pwm_data[] __initconst = {
+#define imx53_mxc_pwm_data_entry(_id, _hwid) \
+ imx_mxc_pwm_data_entry(MX53, _id, _hwid, SZ_16K)
+ imx53_mxc_pwm_data_entry(0, 1),
+ imx53_mxc_pwm_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data)
{
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
new file mode 100644
index 00000000000..6f6e9c59e2f
--- /dev/null
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -0,0 +1,994 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dvfs_core.c
+ *
+ * @brief A simplied driver for the Freescale Semiconductor MXC DVFS module.
+ *
+ * Upon initialization, the DVFS driver initializes the DVFS hardware
+ * sets up driver nodes attaches to the DVFS interrupt and initializes internal
+ * data structures. When the DVFS interrupt occurs the driver checks the cause
+ * of the interrupt (lower frequency, increase frequency or emergency) and
+ * changes the CPU voltage according to translation table that is loaded into
+ * the driver.
+ *
+ * @ingroup PM
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/device.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/cpufreq.h>
+#include <mach/hardware.h>
+#include <mach/mxc_dvfs.h>
+
+#define MXC_DVFSTHRS_UPTHR_MASK 0x0FC00000
+#define MXC_DVFSTHRS_UPTHR_OFFSET 22
+#define MXC_DVFSTHRS_DNTHR_MASK 0x003F0000
+#define MXC_DVFSTHRS_DNTHR_OFFSET 16
+#define MXC_DVFSTHRS_PNCTHR_MASK 0x0000003F
+#define MXC_DVFSTHRS_PNCTHR_OFFSET 0
+
+#define MXC_DVFSCOUN_DNCNT_MASK 0x00FF0000
+#define MXC_DVFSCOUN_DNCNT_OFFSET 16
+#define MXC_DVFSCOUN_UPCNT_MASK 0x000000FF
+#define MXC_DVFSCOUN_UPCNT_OFFSET 0
+
+#define MXC_DVFSEMAC_EMAC_MASK 0x000001FF
+#define MXC_DVFSEMAC_EMAC_OFFSET 0
+
+#define MXC_DVFSCNTR_DVFEV 0x10000000
+#define MXC_DVFSCNTR_LBMI 0x08000000
+#define MXC_DVFSCNTR_LBFL 0x06000000
+#define MXC_DVFSCNTR_DVFIS 0x01000000
+#define MXC_DVFSCNTR_FSVAIM 0x00400000
+#define MXC_DVFSCNTR_FSVAI_MASK 0x00300000
+#define MXC_DVFSCNTR_FSVAI_OFFSET 20
+#define MXC_DVFSCNTR_WFIM 0x00080000
+#define MXC_DVFSCNTR_WFIM_OFFSET 19
+#define MXC_DVFSCNTR_MAXF_MASK 0x00040000
+#define MXC_DVFSCNTR_MAXF_OFFSET 18
+#define MXC_DVFSCNTR_MINF_MASK 0x00020000
+#define MXC_DVFSCNTR_MINF_OFFSET 17
+#define MXC_DVFSCNTR_LTBRSR_MASK 0x00000018
+#define MXC_DVFSCNTR_LTBRSR_OFFSET 3
+#define MXC_DVFSCNTR_DVFEN 0x00000001
+
+#define CCM_CDCR_SW_DVFS_EN 0x20
+#define CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER 0x4
+
+int dvfs_core_is_active;
+extern void setup_pll(void);
+static struct mxc_dvfs_platform_data *dvfs_data;
+static struct device *dvfs_dev;
+static struct cpu_op *cpu_op_tbl;
+int dvfs_core_resume;
+int curr_op;
+int old_op;
+
+int cpufreq_trig_needed;
+struct timeval core_prev_intr;
+
+void dump_dvfs_core_regs(void);
+void stop_dvfs(void);
+static struct delayed_work dvfs_core_handler;
+
+/*
+ * Clock structures
+ */
+static struct clk *pll1_sw_clk;
+static struct clk *cpu_clk;
+static struct clk *dvfs_clk;
+static struct regulator *core_regulator;
+
+extern int cpu_op_nr;
+#ifdef CONFIG_ARCH_MX5
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
+enum {
+ FSVAI_FREQ_NOCHANGE = 0x0,
+ FSVAI_FREQ_INCREASE,
+ FSVAI_FREQ_DECREASE,
+ FSVAI_FREQ_EMERG,
+};
+
+/*
+ * Load tracking buffer source: 1 for ld_add; 0 for pre_ld_add; 2 for after EMA
+ */
+#define DVFS_LTBRSR (2 << MXC_DVFSCNTR_LTBRSR_OFFSET)
+
+extern struct dvfs_wp dvfs_core_setpoint[4];
+extern int low_bus_freq_mode;
+extern int high_bus_freq_mode;
+extern int set_low_bus_freq(void);
+extern int set_high_bus_freq(int high_bus_speed);
+extern int low_freq_bus_used(void);
+
+DEFINE_SPINLOCK(mxc_dvfs_core_lock);
+
+static void dvfs_load_config(int set_point)
+{
+ u32 reg;
+ reg = 0;
+
+ reg |= dvfs_core_setpoint[set_point].upthr << MXC_DVFSTHRS_UPTHR_OFFSET;
+ reg |= dvfs_core_setpoint[set_point].downthr <<
+ MXC_DVFSTHRS_DNTHR_OFFSET;
+ reg |= dvfs_core_setpoint[set_point].panicthr;
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS);
+
+ reg = 0;
+ reg |= dvfs_core_setpoint[set_point].downcnt <<
+ MXC_DVFSCOUN_DNCNT_OFFSET;
+ reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET;
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN);
+
+ /* Set EMAC value */
+ __raw_writel((dvfs_core_setpoint[set_point].emac <<
+ MXC_DVFSEMAC_EMAC_OFFSET),
+ dvfs_data->membase
+ + MXC_DVFSCORE_EMAC);
+
+
+}
+
+static int set_cpu_freq(int op)
+{
+ int arm_podf;
+ int podf;
+ int vinc = 0;
+ int ret = 0;
+ int org_cpu_rate;
+ unsigned long rate = 0;
+ int gp_volt = 0;
+ u32 reg;
+ u32 reg1;
+ u32 en_sw_dvfs = 0;
+ unsigned long flags;
+
+ if (cpu_op_tbl[op].pll_rate != cpu_op_tbl[old_op].pll_rate) {
+ org_cpu_rate = clk_get_rate(cpu_clk);
+ rate = cpu_op_tbl[op].cpu_rate;
+
+ if (org_cpu_rate == rate)
+ return ret;
+
+ gp_volt = cpu_op_tbl[op].cpu_voltage;
+ if (gp_volt == 0)
+ return ret;
+
+ /*Set the voltage for the GP domain. */
+ if (rate > org_cpu_rate) {
+ ret = regulator_set_voltage(core_regulator, gp_volt,
+ gp_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE\n");
+ return ret;
+ }
+ udelay(dvfs_data->delay_time);
+ }
+ spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+ /* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ /* Check if software_dvfs_en bit set */
+ if ((reg & CCM_CDCR_SW_DVFS_EN) != 0)
+ en_sw_dvfs = CCM_CDCR_SW_DVFS_EN;
+ else
+ en_sw_dvfs = 0x0;
+ reg &= ~(CCM_CDCR_SW_DVFS_EN);
+ reg &= 0xFFFFFFFB;
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+
+ setup_pll();
+ /* START the GPC main control FSM */
+ /* set VINC */
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+ reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
+ MXC_GPCVCR_VCNT_MASK);
+
+ if (rate > org_cpu_rate)
+ reg |= 1 << MXC_GPCVCR_VINC_OFFSET;
+
+ reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
+ (1 << MXC_GPCVCR_VCNT_OFFSET);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
+ reg |= MXC_GPCCNTR_FUPD;
+ reg |= MXC_GPCCNTR_ADU;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+ reg |= MXC_GPCCNTR_STRT;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+ & 0x4000)
+ udelay(10);
+ spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+ if (rate < org_cpu_rate) {
+ ret = regulator_set_voltage(core_regulator,
+ gp_volt, gp_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG
+ "COULD NOT SET GP VOLTAGE!!!!\n");
+ return ret;
+ }
+ udelay(dvfs_data->delay_time);
+ }
+ /* set software_dvfs_en bit back to original setting*/
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ reg &= ~(CCM_CDCR_SW_DVFS_EN);
+ reg |= en_sw_dvfs;
+ clk_set_rate(cpu_clk, rate);
+ } else {
+ podf = cpu_op_tbl[op].cpu_podf;
+ gp_volt = cpu_op_tbl[op].cpu_voltage;
+
+ /* Change arm_podf only */
+ /* set ARM_FREQ_SHIFT_DIVIDER */
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+
+ /* Check if software_dvfs_en bit set */
+ if ((reg & CCM_CDCR_SW_DVFS_EN) != 0)
+ en_sw_dvfs = CCM_CDCR_SW_DVFS_EN;
+ else
+ en_sw_dvfs = 0x0;
+
+ reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER);
+ reg |= CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER;
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+
+ /* Get ARM_PODF */
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
+ arm_podf = reg & 0x07;
+ if (podf == arm_podf) {
+ printk(KERN_DEBUG
+ "No need to change freq and voltage!!!!\n");
+ return 0;
+ }
+
+ /* Check if FSVAI indicate freq up */
+ if (podf < arm_podf) {
+ ret = regulator_set_voltage(core_regulator,
+ gp_volt, gp_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG
+ "COULD NOT SET GP VOLTAGE!!!!\n");
+ return 0;
+ }
+ udelay(dvfs_data->delay_time);
+ vinc = 1;
+ } else {
+ vinc = 0;
+ }
+
+ arm_podf = podf;
+ /* Set ARM_PODF */
+ reg &= 0xFFFFFFF8;
+ reg |= arm_podf;
+ spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+ reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset);
+ if ((reg1 & 0x00010000) == 0)
+ __raw_writel(reg,
+ ccm_base + dvfs_data->ccm_cacrr_offset);
+ else {
+ printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
+ return 0;
+ }
+ /* set VINC */
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+ reg &=
+ ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
+ MXC_GPCVCR_VCNT_MASK);
+ reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
+ (100 << MXC_GPCVCR_VCNT_OFFSET) |
+ (vinc << MXC_GPCVCR_VINC_OFFSET);
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD
+ | MXC_GPCCNTR_STRT));
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg |= MXC_GPCCNTR_STRT;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+ /* Wait for arm podf Enable */
+ while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
+ MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
+ printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
+ udelay(10);
+ }
+ spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+ if (vinc == 0) {
+ ret = regulator_set_voltage(core_regulator,
+ gp_volt, gp_volt);
+ if (ret < 0) {
+ printk(KERN_DEBUG
+ "COULD NOT SET GP VOLTAGE!!!!\n");
+ return ret;
+ }
+ udelay(dvfs_data->delay_time);
+ }
+
+ /* Clear the ARM_FREQ_SHIFT_DIVIDER and */
+ /* set software_dvfs_en bit back to original setting*/
+ reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ reg &= ~(CCM_CDCR_SW_DVFS_EN | CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER);
+ reg |= en_sw_dvfs;
+ __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+ }
+#if defined(CONFIG_CPU_FREQ)
+ cpufreq_trig_needed = 1;
+#endif
+ old_op = op;
+ return ret;
+}
+
+static int start_dvfs(void)
+{
+ u32 reg, cpu_rate;
+ unsigned long flags;
+
+ if (dvfs_core_is_active)
+ return 0;
+
+ spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+ clk_enable(dvfs_clk);
+
+ dvfs_load_config(0);
+
+ /* get current working point */
+ cpu_rate = clk_get_rate(cpu_clk);
+ curr_op = cpu_op_nr - 1;
+ do {
+ if (cpu_rate <= cpu_op_tbl[curr_op].cpu_rate)
+ break;
+ } while (--curr_op >= 0);
+ old_op = curr_op;
+ /* config reg GPC_CNTR */
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+
+ reg &= ~MXC_GPCCNTR_GPCIRQM;
+ /* GPCIRQ=1, select ARM IRQ */
+ reg |= MXC_GPCCNTR_GPCIRQ_ARM;
+ /* ADU=1, select ARM domain */
+ reg |= MXC_GPCCNTR_ADU;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+ /* Set PREDIV bits */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ reg = (reg & ~(dvfs_data->prediv_mask));
+ reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+ /* Enable DVFS interrupt */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ /* FSVAIM=0 */
+ reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+ /* Set MAXF, MINF */
+ reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK));
+ reg |= 1 << MXC_DVFSCNTR_MAXF_OFFSET;
+ /* Select ARM domain */
+ reg |= MXC_DVFSCNTR_DVFIS;
+ /* Enable DVFS frequency adjustment interrupt */
+ reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+ /* Set load tracking buffer register source */
+ reg = (reg & ~MXC_DVFSCNTR_LTBRSR_MASK);
+ reg |= DVFS_LTBRSR;
+ /* Set DIV3CK */
+ reg = (reg & ~(dvfs_data->div3ck_mask));
+ reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset);
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+ /* Enable DVFS */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ reg |= MXC_DVFSCNTR_DVFEN;
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+ dvfs_core_is_active = 1;
+
+ spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+ printk(KERN_DEBUG "DVFS is started\n");
+
+ return 0;
+}
+
+/*!
+ * This function is called for module initialization.
+ * It sets up the DVFS hardware.
+ * It sets default values for DVFS thresholds and counters. The default
+ * values was chosen from a set of different reasonable values. They was tested
+ * and the default values in the driver gave the best results.
+ * More work should be done to find optimal values.
+ *
+ * @return 0 if successful; non-zero otherwise.
+ *
+ */
+static int init_dvfs_controller(void)
+{
+ /* DVFS loading config */
+ dvfs_load_config(0);
+
+ return 0;
+}
+
+static irqreturn_t dvfs_irq(int irq, void *dev_id)
+{
+ u32 reg;
+
+ /* Check if DVFS0 (ARM) id requesting for freqency/voltage update */
+ if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
+ & MXC_GPCCNTR_DVFS0CR) == 0)
+ return IRQ_NONE;
+
+ /* Mask DVFS irq */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ /* FSVAIM=1 */
+ reg |= MXC_DVFSCNTR_FSVAIM;
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+
+ /* Mask GPC1 irq */
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+ schedule_delayed_work(&dvfs_core_handler, 0);
+ return IRQ_HANDLED;
+}
+
+static void dvfs_core_work_handler(struct work_struct *work)
+{
+ u32 fsvai;
+ u32 reg;
+ u32 curr_cpu;
+ int ret = 0;
+ int maxf = 0, minf = 0;
+ int low_freq_bus_ready = 0;
+ int bus_incr = 0, cpu_dcr = 0;
+
+ low_freq_bus_ready = low_freq_bus_used();
+
+ /* Check DVFS frequency adjustment interrupt status */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET;
+ /* Check FSVAI, FSVAI=0 is error */
+ if (fsvai == FSVAI_FREQ_NOCHANGE) {
+ /* Do nothing. Freq change is not required */
+ goto END;
+ }
+ curr_cpu = clk_get_rate(cpu_clk);
+ /* If FSVAI indicate freq down,
+ check arm-clk is not in lowest frequency 200 MHz */
+ if (fsvai == FSVAI_FREQ_DECREASE) {
+ if (curr_cpu == cpu_op_tbl[cpu_op_nr - 1].cpu_rate) {
+ minf = 1;
+ if (low_bus_freq_mode)
+ goto END;
+ } else {
+ /* freq down */
+ curr_op++;
+ if (curr_op >= cpu_op_nr) {
+ curr_op = cpu_op_nr - 1;
+ goto END;
+ }
+
+ if (curr_op == cpu_op_nr - 1 && !low_freq_bus_ready) {
+ minf = 1;
+ dvfs_load_config(1);
+ } else {
+ cpu_dcr = 1;
+ }
+ }
+ } else {
+ if (curr_cpu == cpu_op_tbl[0].cpu_rate) {
+ maxf = 1;
+ goto END;
+ } else {
+ if (!high_bus_freq_mode && !cpu_is_mx50()) {
+ /* bump up LP freq first. */
+ bus_incr = 1;
+ dvfs_load_config(2);
+ } else {
+ /* freq up */
+ curr_op = 0;
+ maxf = 1;
+ dvfs_load_config(0);
+ }
+ }
+ }
+
+ low_freq_bus_ready = low_freq_bus_used();
+ if ((curr_op == cpu_op_nr - 1) && (!low_bus_freq_mode)
+ && (low_freq_bus_ready) && !bus_incr) {
+ if (cpu_dcr)
+ ret = set_cpu_freq(curr_op);
+ if (!cpu_dcr) {
+ set_low_bus_freq();
+ dvfs_load_config(3);
+ } else {
+ dvfs_load_config(2);
+ cpu_dcr = 0;
+ }
+ } else {
+ if (!high_bus_freq_mode)
+ set_high_bus_freq(1);
+ if (!bus_incr)
+ ret = set_cpu_freq(curr_op);
+ bus_incr = 0;
+ }
+
+
+END: /* Set MAXF, MINF */
+ reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK));
+ reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET;
+ reg |= minf << MXC_DVFSCNTR_MINF_OFFSET;
+
+ /* Enable DVFS interrupt */
+ /* FSVAIM=0 */
+ reg = (reg & ~MXC_DVFSCNTR_FSVAIM);
+ reg |= FSVAI_FREQ_NOCHANGE;
+ /* LBFL=1 */
+ reg = (reg & ~MXC_DVFSCNTR_LBFL);
+ reg |= MXC_DVFSCNTR_LBFL;
+ __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
+ /*Unmask GPC1 IRQ */
+ reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg &= ~MXC_GPCCNTR_GPCIRQM;
+ __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+
+#if defined(CONFIG_CPU_FREQ)
+ if (cpufreq_trig_needed == 1) {
+ cpufreq_trig_needed = 0;
+ cpufreq_update_policy(0);
+ }
+#endif
+}
+
+
+/*!
+ * This function disables the DVFS module.
+ */
+void stop_dvfs(void)
+{
+ u32 reg = 0;
+ unsigned long flags;
+ u32 curr_cpu;
+
+ if (dvfs_core_is_active) {
+
+ /* Mask dvfs irq, disable DVFS */
+ reg = __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
+ /* FSVAIM=1 */
+ reg |= MXC_DVFSCNTR_FSVAIM;
+ __raw_writel(reg, dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
+
+ curr_op = 0;
+ if (!high_bus_freq_mode)
+ set_high_bus_freq(1);
+
+ curr_cpu = clk_get_rate(cpu_clk);
+ if (curr_cpu != cpu_op_tbl[curr_op].cpu_rate) {
+ set_cpu_freq(curr_op);
+#if defined(CONFIG_CPU_FREQ)
+ if (cpufreq_trig_needed == 1) {
+ cpufreq_trig_needed = 0;
+ cpufreq_update_policy(0);
+ }
+#endif
+ }
+ spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
+
+ reg = __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
+ reg = (reg & ~MXC_DVFSCNTR_DVFEN);
+ __raw_writel(reg, dvfs_data->membase
+ + MXC_DVFSCORE_CNTR);
+
+ spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
+
+ dvfs_core_is_active = 0;
+
+ clk_disable(dvfs_clk);
+ }
+
+ printk(KERN_DEBUG "DVFS is stopped\n");
+}
+
+void dump_dvfs_core_regs()
+{
+ struct timeval cur;
+ u32 diff = 0;
+ if (core_prev_intr.tv_sec == 0)
+ do_gettimeofday(&core_prev_intr);
+ else {
+ do_gettimeofday(&cur);
+ diff = (cur.tv_sec - core_prev_intr.tv_sec)*1000000
+ + (cur.tv_usec - core_prev_intr.tv_usec);
+ core_prev_intr = cur;
+ }
+ if (diff < 90000)
+ printk(KERN_DEBUG "diff = %d\n", diff);
+
+ printk(KERN_INFO "THRS = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS));
+ printk(KERN_INFO "COUNT = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x04));
+ printk(KERN_INFO "SIG1 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x08));
+ printk(KERN_INFO "SIG0 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x0c));
+ printk(KERN_INFO "GPC0 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x10));
+ printk(KERN_INFO "GPC1 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x14));
+ printk(KERN_INFO "GPBT = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x18));
+ printk(KERN_INFO "EMAC = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x1c));
+ printk(KERN_INFO "CNTR = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x20));
+ printk(KERN_INFO "LTR0_0 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x24));
+ printk(KERN_INFO "LTR0_1 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x28));
+ printk(KERN_INFO "LTR1_0 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x2c));
+ printk(KERN_DEBUG "LTR1_1 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x30));
+ printk(KERN_INFO "PT0 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x34));
+ printk(KERN_INFO "PT1 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x38));
+ printk(KERN_INFO "PT2 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x3c));
+ printk(KERN_INFO "PT3 = 0x%08x\n",
+ __raw_readl(dvfs_data->membase
+ + MXC_DVFSCORE_THRS + 0x40));
+}
+
+static ssize_t downthreshold_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downthr);
+}
+
+static ssize_t downthreshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ int ret = 0;
+ int val;
+ ret = sscanf(buf, "%u", &val);
+ dvfs_core_setpoint[0].downthr = val;
+
+ return size;
+}
+
+static ssize_t downcount_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", dvfs_core_setpoint[0].downcnt);
+}
+
+static ssize_t downcount_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ int ret = 0;
+ int val;
+ ret = sscanf(buf, "%u", &val);
+ dvfs_core_setpoint[0].downcnt = val;
+
+ return size;
+}
+
+
+static ssize_t dvfs_enable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (dvfs_core_is_active)
+ return sprintf(buf, "DVFS is enabled\n");
+ else
+ return sprintf(buf, "DVFS is disabled\n");
+}
+
+static ssize_t dvfs_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ if (strstr(buf, "1") != NULL) {
+ if (start_dvfs() != 0)
+ printk(KERN_ERR "Failed to start DVFS\n");
+ } else if (strstr(buf, "0") != NULL)
+ stop_dvfs();
+
+ return size;
+}
+
+static ssize_t dvfs_regs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (dvfs_core_is_active)
+ dump_dvfs_core_regs();
+ return 0;
+}
+
+static ssize_t dvfs_regs_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ if (dvfs_core_is_active)
+ dump_dvfs_core_regs();
+ return 0;
+
+ return size;
+}
+
+static DEVICE_ATTR(enable, 0644, dvfs_enable_show, dvfs_enable_store);
+static DEVICE_ATTR(show_regs, 0644, dvfs_regs_show, dvfs_regs_store);
+
+static DEVICE_ATTR(down_threshold, 0644, downthreshold_show,
+ downthreshold_store);
+static DEVICE_ATTR(down_count, 0644, downcount_show, downcount_store);
+
+/*!
+ * This is the probe routine for the DVFS driver.
+ *
+ * @param pdev The platform device structure
+ *
+ * @return The function returns 0 on success
+ */
+static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
+{
+ int err = 0;
+ struct resource *res;
+
+ printk(KERN_INFO "mxc_dvfs_core_probe\n");
+ dvfs_dev = &pdev->dev;
+ dvfs_data = pdev->dev.platform_data;
+
+ INIT_DELAYED_WORK(&dvfs_core_handler, dvfs_core_work_handler);
+
+ pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
+ if (IS_ERR(pll1_sw_clk)) {
+ printk(KERN_INFO "%s: failed to get pll1_sw_clk\n", __func__);
+ return PTR_ERR(pll1_sw_clk);
+ }
+
+ cpu_clk = clk_get(NULL, dvfs_data->clk1_id);
+ if (IS_ERR(cpu_clk)) {
+ printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
+ return PTR_ERR(cpu_clk);
+ }
+
+ dvfs_clk = clk_get(NULL, dvfs_data->clk2_id);
+ if (IS_ERR(dvfs_clk)) {
+ printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__);
+ return PTR_ERR(dvfs_clk);
+ }
+
+ core_regulator = regulator_get(NULL, dvfs_data->reg_id);
+ if (IS_ERR(core_regulator)) {
+ clk_put(cpu_clk);
+ clk_put(dvfs_clk);
+ printk(KERN_ERR "%s: failed to get gp regulator\n", __func__);
+ return PTR_ERR(core_regulator);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ err = -ENODEV;
+ goto err1;
+ }
+ dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
+ /*
+ * Request the DVFS interrupt
+ */
+ dvfs_data->irq = platform_get_irq(pdev, 0);
+ if (dvfs_data->irq < 0) {
+ err = dvfs_data->irq;
+ goto err2;
+ }
+
+ /* request the DVFS interrupt */
+ err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs",
+ dvfs_dev);
+ if (err) {
+ printk(KERN_ERR
+ "DVFS: Unable to attach to DVFS interrupt,err = %d",
+ err);
+ goto err2;
+ }
+
+ clk_enable(dvfs_clk);
+ err = init_dvfs_controller();
+ if (err) {
+ printk(KERN_ERR "DVFS: Unable to initialize DVFS");
+ return err;
+ }
+ clk_disable(dvfs_clk);
+
+ err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
+ if (err) {
+ printk(KERN_ERR
+ "DVFS: Unable to register sysdev entry for DVFS");
+ goto err3;
+ }
+
+ err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr);
+ if (err) {
+ printk(KERN_ERR
+ "DVFS: Unable to register sysdev entry for DVFS");
+ goto err3;
+ }
+
+
+ err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_threshold.attr);
+ if (err) {
+ printk(KERN_ERR
+ "DVFS: Unable to register sysdev entry for DVFS");
+ goto err3;
+ }
+
+ err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr);
+ if (err) {
+ printk(KERN_ERR
+ "DVFS: Unable to register sysdev entry for DVFS");
+ goto err3;
+ }
+
+ /* Set the current working point. */
+ cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+ old_op = 0;
+ curr_op = 0;
+ dvfs_core_resume = 0;
+ cpufreq_trig_needed = 0;
+
+ return err;
+err3:
+ free_irq(dvfs_data->irq, dvfs_dev);
+err2:
+ iounmap(dvfs_data->membase);
+err1:
+ dev_err(&pdev->dev, "Failed to probe DVFS CORE\n");
+ return err;
+}
+
+/*!
+ * This function is called to put DVFS in a low power state.
+ *
+ * @param pdev the device structure
+ * @param state the power state the device is entering
+ *
+ * @return The function always returns 0.
+ */
+static int mxc_dvfs_core_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ if (dvfs_core_is_active) {
+ dvfs_core_resume = 1;
+ stop_dvfs();
+ }
+
+ return 0;
+}
+
+/*!
+ * This function is called to resume the MU from a low power state.
+ *
+ * @param dev the device structure
+ * @param level the stage in device suspension process that we want the
+ * device to be put in
+ *
+ * @return The function always returns 0.
+ */
+static int mxc_dvfs_core_resume(struct platform_device *pdev)
+{
+ if (dvfs_core_resume) {
+ dvfs_core_resume = 0;
+ start_dvfs();
+ }
+
+ return 0;
+}
+
+static struct platform_driver mxc_dvfs_core_driver = {
+ .driver = {
+ .name = "mxc_dvfs_core",
+ },
+ .probe = mxc_dvfs_core_probe,
+ .suspend = mxc_dvfs_core_suspend,
+ .resume = mxc_dvfs_core_resume,
+};
+
+static int __init dvfs_init(void)
+{
+ if (platform_driver_register(&mxc_dvfs_core_driver) != 0) {
+ printk(KERN_ERR "mxc_dvfs_core_driver register failed\n");
+ return -ENODEV;
+ }
+
+ dvfs_core_is_active = 0;
+ printk(KERN_INFO "DVFS driver module loaded\n");
+ return 0;
+}
+
+static void __exit dvfs_cleanup(void)
+{
+ stop_dvfs();
+
+ /* release the DVFS interrupt */
+ free_irq(dvfs_data->irq, dvfs_dev);
+
+ sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
+
+ /* Unregister the device structure */
+ platform_driver_unregister(&mxc_dvfs_core_driver);
+
+ iounmap(ccm_base);
+ iounmap(dvfs_data->membase);
+ clk_put(cpu_clk);
+ clk_put(dvfs_clk);
+
+ dvfs_core_is_active = 0;
+ printk(KERN_INFO "DVFS driver module unloaded\n");
+
+}
+
+module_init(dvfs_init);
+module_exit(dvfs_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("DVFS driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h
new file mode 100755
index 00000000000..f121dc17fe6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/arc_otg.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_ARC_OTG_H__
+#define __ASM_ARCH_MXC_ARC_OTG_H__
+
+#ifdef CONFIG_ARCH_MX3
+extern volatile u32 *mx3_usb_otg_addr;
+#define OTG_BASE_ADDR mx3_usb_otg_addr
+#else
+extern void __iomem *imx_otg_base;
+#define OTG_BASE_ADDR imx_otg_base
+#endif
+
+#define USB_OTGREGS_BASE (OTG_BASE_ADDR + 0x000)
+#define USB_H1REGS_BASE (OTG_BASE_ADDR + 0x200)
+#define USB_H2REGS_BASE (OTG_BASE_ADDR + 0x400)
+#ifdef CONFIG_ARCH_MX5
+#define USB_H3REGS_BASE (OTG_BASE_ADDR + 0x600)
+#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x800)
+#else
+#define USB_OTHERREGS_BASE (OTG_BASE_ADDR + 0x600)
+#endif
+
+
+#define USBOTG_REG32(offset) (*((volatile u32 __force *)(USB_OTGREGS_BASE + (offset))))
+#define USBOTG_REG16(offset) (*((volatile u16 __force *)(USB_OTGREGS_BASE + (offset))))
+
+#define USBH1_REG32(offset) (*((volatile u32 __force *)(USB_H1REGS_BASE + (offset))))
+#define USBH1_REG16(offset) (*((volatile u16 __force *)(USB_H1REGS_BASE + (offset))))
+
+#define USBH2_REG32(offset) (*((volatile u32 __force *)(USB_H2REGS_BASE + (offset))))
+#define USBH2_REG16(offset) (*((volatile u16 __force *)(USB_H2REGS_BASE + (offset))))
+
+#define USBOTHER_REG(offset) (*((volatile u32 __force *)(USB_OTHERREGS_BASE + (offset))))
+
+/*
+ * OTG registers
+ */
+#define UOG_ID USBOTG_REG32(0x00) /* Host ID */
+#define UOG_HWGENERAL USBOTG_REG32(0x04) /* Host General */
+#define UOG_HWHOST USBOTG_REG32(0x08) /* Host h/w params */
+#define UOG_HWTXBUF USBOTG_REG32(0x10) /* TX buffer h/w params */
+#define UOG_HWRXBUF USBOTG_REG32(0x14) /* RX buffer h/w params */
+#define UOG_CAPLENGTH USBOTG_REG16(0x100) /* Capability register length */
+#define UOG_HCIVERSION USBOTG_REG16(0x102) /* Host Interface version */
+#define UOG_HCSPARAMS USBOTG_REG32(0x104) /* Host control structural params */
+#define UOG_HCCPARAMS USBOTG_REG32(0x108) /* control capability params */
+#define UOG_DCIVERSION USBOTG_REG32(0x120) /* device interface version */
+/* start EHCI registers: */
+#define UOG_USBCMD USBOTG_REG32(0x140) /* USB command register */
+#define UOG_USBSTS USBOTG_REG32(0x144) /* USB status register */
+#define UOG_USBINTR USBOTG_REG32(0x148) /* interrupt enable register */
+#define UOG_FRINDEX USBOTG_REG32(0x14c) /* USB frame index */
+/* segment (0x150) addr bits 63:32 if needed */
+#define UOG_PERIODICLISTBASE USBOTG_REG32(0x154) /* host crtlr frame list base addr */
+#define UOG_DEVICEADDR USBOTG_REG32(0x154) /* device crtlr device address */
+#define UOG_ASYNCLISTADDR USBOTG_REG32(0x158) /* host ctrlr next async addr */
+#define UOG_EPLISTADDR USBOTG_REG32(0x158) /* device ctrlr endpoint list addr */
+#define UOG_BURSTSIZE USBOTG_REG32(0x160) /* host ctrlr embedded TT async buf status */
+#define UOG_TXFILLTUNING USBOTG_REG32(0x164) /* TX FIFO fill tuning */
+#define UOG_ULPIVIEW USBOTG_REG32(0x170) /* ULPI viewport */
+#define UOG_CFGFLAG USBOTG_REG32(0x180) /* configflag (supports HS) */
+#define UOG_PORTSC1 USBOTG_REG32(0x184) /* port status and control */
+/* end EHCI registers: */
+#define UOG_OTGSC USBOTG_REG32(0x1a4) /* OTG status and control */
+#define UOG_USBMODE USBOTG_REG32(0x1a8) /* USB device mode */
+#define UOG_ENDPTSETUPSTAT USBOTG_REG32(0x1ac) /* endpoint setup status */
+#define UOG_ENDPTPRIME USBOTG_REG32(0x1b0) /* endpoint initialization */
+#define UOG_ENDPTFLUSH USBOTG_REG32(0x1b4) /* endpoint de-initialize */
+#define UOG_ENDPTSTAT USBOTG_REG32(0x1b8) /* endpoint status */
+#define UOG_ENDPTCOMPLETE USBOTG_REG32(0x1bc) /* endpoint complete */
+#define UOG_EPCTRL0 USBOTG_REG32(0x1c0) /* endpoint control0 */
+#define UOG_EPCTRL1 USBOTG_REG32(0x1c4) /* endpoint control1 */
+#define UOG_EPCTRL2 USBOTG_REG32(0x1c8) /* endpoint control2 */
+#define UOG_EPCTRL3 USBOTG_REG32(0x1cc) /* endpoint control3 */
+#define UOG_EPCTRL4 USBOTG_REG32(0x1d0) /* endpoint control4 */
+#define UOG_EPCTRL5 USBOTG_REG32(0x1d4) /* endpoint control5 */
+#define UOG_EPCTRL6 USBOTG_REG32(0x1d8) /* endpoint control6 */
+#define UOG_EPCTRL7 USBOTG_REG32(0x1dc) /* endpoint control7 */
+
+/*
+ * Host 1 registers
+ */
+#define UH1_ID USBH1_REG32(0x00) /* Host ID */
+#define UH1_HWGENERAL USBH1_REG32(0x04) /* Host General */
+#define UH1_HWHOST USBH1_REG32(0x08) /* Host h/w params */
+#define UH1_HWTXBUF USBH1_REG32(0x10) /* TX buffer h/w params */
+#define UH1_HWRXBUF USBH1_REG32(0x14) /* RX buffer h/w params */
+#define UH1_CAPLENGTH USBH1_REG16(0x100) /* Capability register length */
+#define UH1_HCIVERSION USBH1_REG16(0x102) /* Host Interface version */
+#define UH1_HCSPARAMS USBH1_REG32(0x104) /* Host control structural params */
+#define UH1_HCCPARAMS USBH1_REG32(0x108) /* control capability params */
+/* start EHCI registers: */
+#define UH1_USBCMD USBH1_REG32(0x140) /* USB command register */
+#define UH1_USBSTS USBH1_REG32(0x144) /* USB status register */
+#define UH1_USBINTR USBH1_REG32(0x148) /* interrupt enable register */
+#define UH1_FRINDEX USBH1_REG32(0x14c) /* USB frame index */
+/* segment (0x150) addr bits 63:32 if needed */
+#define UH1_PERIODICLISTBASE USBH1_REG32(0x154) /* host crtlr frame list base addr */
+#define UH1_ASYNCLISTADDR USBH1_REG32(0x158) /* host ctrlr nest async addr */
+#define UH1_BURSTSIZE USBH1_REG32(0x160) /* host ctrlr embedded TT async buf status */
+#define UH1_TXFILLTUNING USBH1_REG32(0x164) /* TX FIFO fill tuning */
+/* configured_flag (0x180) configflag (supports HS) */
+#define UH1_PORTSC1 USBH1_REG32(0x184) /* port status and control */
+/* end EHCI registers: */
+#define UH1_USBMODE USBH1_REG32(0x1a8) /* USB device mode */
+
+/*
+ * Host 2 registers
+ */
+#define UH2_ID USBH2_REG32(0x00) /* Host ID */
+#define UH2_HWGENERAL USBH2_REG32(0x04) /* Host General */
+#define UH2_HWHOST USBH2_REG32(0x08) /* Host h/w params */
+#define UH2_HWTXBUF USBH2_REG32(0x10) /* TX buffer h/w params */
+#define UH2_HWRXBUF USBH2_REG32(0x14) /* RX buffer h/w params */
+#define UH2_CAPLENGTH USBH2_REG16(0x100) /* Capability register length */
+#define UH2_HCIVERSION USBH2_REG16(0x102) /* Host Interface version */
+#define UH2_HCSPARAMS USBH2_REG32(0x104) /* Host control structural params */
+#define UH2_HCCPARAMS USBH2_REG32(0x108) /* control capability params */
+/* start EHCI registers: */
+#define UH2_USBCMD USBH2_REG32(0x140) /* USB command register */
+#define UH2_USBSTS USBH2_REG32(0x144) /* USB status register */
+#define UH2_USBINTR USBH2_REG32(0x148) /* interrupt enable register */
+#define UH2_FRINDEX USBH2_REG32(0x14c) /* USB frame index */
+/* segment (0x150) addr bits 63:32 if needed */
+#define UH2_PERIODICLISTBASE USBH2_REG32(0x154) /* host crtlr frame list base addr */
+#define UH2_ASYNCLISTADDR USBH2_REG32(0x158) /* host ctrlr nest async addr */
+#define UH2_BURSTSIZE USBH2_REG32(0x160) /* host ctrlr embedded TT async buf status */
+#define UH2_TXFILLTUNING USBH2_REG32(0x164) /* TX FIFO fill tuning */
+#define UH2_ULPIVIEW USBH2_REG32(0x170) /* ULPI viewport */
+/* configured_flag (0x180) configflag (supports HS) */
+#define UH2_PORTSC1 USBH2_REG32(0x184) /* port status and control */
+/* end EHCI registers */
+#define UH2_USBMODE USBH2_REG32(0x1a8) /* USB device mode */
+
+/*
+ * other regs (not part of ARC core)
+ */
+#define USBCTRL USBOTHER_REG(0x00) /* USB Control register */
+#define USB_OTG_MIRROR USBOTHER_REG(0x04) /* USB OTG mirror register */
+#define USB_PHY_CTR_FUNC USBOTHER_REG(0x08) /* OTG UTMI PHY Function Control register */
+#define USB_PHY_CTR_FUNC2 USBOTHER_REG(0x0c) /* OTG UTMI PHY Function Control register */
+#define USB_CTRL_1 USBOTHER_REG(0x10) /* USB Cotrol Register 1*/
+#define USBCTRL_HOST2 USBOTHER_REG(0x14) /* USB Cotrol Register 1*/
+#define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/
+#define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/
+#define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/
+#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */
+
+/*
+ * register bits
+ */
+
+/* x_PORTSCx */
+#define PORTSC_PTS_MASK (3 << 30) /* parallel xcvr select mask */
+#define PORTSC_PTS_UTMI (0 << 30) /* UTMI/UTMI+ */
+#define PORTSC_PTS_PHILIPS (1 << 30) /* Philips classic */
+#define PORTSC_PTS_ULPI (2 << 30) /* ULPI */
+#define PORTSC_PTS_SERIAL (3 << 30) /* serial */
+#define PORTSC_STS (1 << 29) /* serial xcvr select */
+#define PORTSC_PTW (1 << 28) /* UTMI width */
+#define PORTSC_PHCD (1 << 23) /* Low Power Suspend */
+#define PORTSC_PORT_POWER (1 << 12) /* port power */
+#define PORTSC_LS_MASK (3 << 10) /* Line State mask */
+#define PORTSC_LS_SE0 (0 << 10) /* SE0 */
+#define PORTSC_LS_K_STATE (1 << 10) /* K-state */
+#define PORTSC_LS_J_STATE (2 << 10) /* J-state */
+#define PORTSC_PORT_RESET (1 << 8) /* Port reset */
+#define PORTSC_PORT_SUSPEND (1 << 7) /* Suspend */
+#define PORTSC_PORT_FORCE_RESUME (1 << 6) /* Force port resume */
+#define PORTSC_OVER_CURRENT_CHG (1 << 5) /* over current change */
+#define PORTSC_OVER_CURRENT_ACT (1 << 4) /* over currrent active */
+#define PORTSC_PORT_EN_DIS_CHANGE (1 << 3) /* port {en,dis}able change */
+#define PORTSC_PORT_ENABLE (1 << 2) /* port enabled */
+#define PORTSC_CONNECT_STATUS_CHANGE (1 << 1) /* connect status change */
+#define PORTSC_CURRENT_CONNECT_STATUS (1 << 0) /* current connect status */
+
+#define PORTSC_W1C_BITS \
+ (PORTSC_CONNECT_STATUS_CHANGE | \
+ PORTSC_PORT_EN_DIS_CHANGE | \
+ PORTSC_OVER_CURRENT_CHG)
+
+/* UOG_OTGSC Register Bits */
+/* control bits: */
+#define OTGSC_CTRL_VBUS_DISCHARGE (1 << 0)
+#define OTGSC_CTRL_VBUS_CHARGE (1 << 1)
+#define OTGSC_CTRL_OTG_TERM (1 << 3) /* controls DM pulldown */
+#define OTGSC_CTRL_DATA_PULSING (1 << 4)
+#define OTGSC_CTRL_USB_ID_PU (1 << 5) /* enable ID pullup */
+/* current status: (R/O) */
+#define OTGSC_STS_USB_ID (1 << 8) /* 0=A-device 1=B-device */
+#define OTGSC_STS_A_VBUS_VALID (1 << 9)
+#define OTGSC_STS_A_SESSION_VALID (1 << 10)
+#define OTGSC_STS_B_SESSION_VALID (1 << 11)
+#define OTGSC_STS_B_SESSION_END (1 << 12)
+#define OTGSC_STS_1ms_TIMER (1 << 13)
+#define OTGSC_STS_DATA_PULSE (1 << 14)
+/* interrupt status: (write to clear) */
+#define OTGSC_IS_MASK (0x7f << 16)
+#define OTGSC_IS_USB_ID (1 << 16)
+#define OTGSC_IS_A_VBUS_VALID (1 << 17)
+#define OTGSC_IS_A_SESSION_VALID (1 << 18)
+#define OTGSC_IS_B_SESSION_VALID (1 << 19)
+#define OTGSC_IS_B_SESSION_END (1 << 20)
+#define OTGSC_IS_1ms_TIMER (1 << 21)
+#define OTGSC_IS_DATA_PULSE (1 << 22)
+/* interrupt enables: */
+#define OTGSC_IE_MASK (0x7f << 24)
+#define OTGSC_IE_USB_ID (1 << 24)
+#define OTGSC_IE_A_VBUS_VALID (1 << 25)
+#define OTGSC_IE_A_SESSION_VALID (1 << 26)
+#define OTGSC_IE_B_SESSION_VALID (1 << 27)
+#define OTGSC_IE_B_SESSION_END (1 << 28)
+#define OTGSC_IE_1ms_TIMER (1 << 29)
+#define OTGSC_IE_DATA_PULSE (1 << 30)
+
+#if 1 /* FIXME these here for compatibility between my names and Leo's */
+/* OTG interrupt enable bit masks */
+#define OTGSC_INTERRUPT_ENABLE_BITS_MASK OTGSC_IE_MASK
+#define OTGSC_INTSTS_MASK OTGSC_IS_MASK
+
+/* OTG interrupt status bit masks */
+#define OTGSC_INTERRUPT_STATUS_BITS_MASK OTGSC_IS_MASK
+#endif
+
+/* x_USBMODE */
+#define USBMODE_SLOM (1 << 3) /* setup lockout mode */
+#define USBMODE_ES (1 << 2) /* (big) endian select */
+#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
+#define USBMODE_CM_HOST (3 << 0) /* host */
+#define USBMODE_CM_DEVICE (2 << 0) /* device */
+#define USBMODE_CM_reserved (1 << 0) /* reserved */
+
+/* USBCTRL */
+#define UCTRL_OWIR (1 << 31) /* OTG wakeup intr request received */
+#define UCTRL_OSIC_MASK (3 << 29) /* OTG Serial Interface Config: */
+#define UCTRL_OSIC_DU6 (0 << 29) /* Differential/unidirectional 6 wire */
+#define UCTRL_OSIC_DB4 (1 << 29) /* Differential/bidirectional 4 wire */
+#define UCTRL_OSIC_SU6 (2 << 29) /* single-ended/unidirectional 6 wire */
+#define UCTRL_OSIC_SB3 (3 << 29) /* single-ended/bidirectional 3 wire */
+
+#define UCTRL_OUIE (1 << 28) /* OTG ULPI intr enable */
+#define UCTRL_OWIE (1 << 27) /* OTG wakeup intr enable */
+#define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */
+#define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */
+#define UCTRL_OPM (1 << 24) /* OTG power mask */
+#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */
+#ifdef CONFIG_ARCH_MX5
+#define UCTRL_H2WIR (1 << 17) /* HOST2 wakeup intr request received */
+#else
+#define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */
+#endif
+#define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */
+#define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */
+#define UCTRL_H2SIC_DB4 (1 << 21) /* Differential/bidirectional 4 wire */
+#define UCTRL_H2SIC_SU6 (2 << 21) /* single-ended/unidirectional 6 wire */
+#define UCTRL_H2SIC_SB3 (3 << 21) /* single-ended/bidirectional 3 wire */
+
+#ifdef CONFIG_ARCH_MX5
+#define UCTRL_H2UIE (1 << 8) /* HOST2 ULPI intr enable */
+#define UCTRL_H2WIE (1 << 7) /* HOST2 wakeup intr enable */
+#define UCTRL_H2PP 0 /* Power Polarity for uh2 */
+#define UCTRL_H2PM (1 << 4) /* HOST2 power mask */
+#else
+#define UCTRL_H2UIE (1 << 20) /* HOST2 ULPI intr enable */
+#define UCTRL_H2WIE (1 << 19) /* HOST2 wakeup intr enable */
+#define UCTRL_H2PP (1 << 18) /* Power Polarity for uh2 */
+#define UCTRL_H2PM (1 << 16) /* HOST2 power mask */
+#endif
+#define UCTRL_H2OVBWK_EN (1 << 6) /* OTG VBUS Wakeup Enable */
+#define UCTRL_H2OIDWK_EN (1 << 5) /* OTG ID Wakeup Enable */
+
+#define UCTRL_H1WIR (1 << 15) /* HOST1 wakeup intr request received */
+#define UCTRL_H1SIC_MASK (3 << 13) /* HOST1 Serial Interface Config: */
+#define UCTRL_H1SIC_DU6 (0 << 13) /* Differential/unidirectional 6 wire */
+#define UCTRL_H1SIC_DB4 (1 << 13) /* Differential/bidirectional 4 wire */
+#define UCTRL_H1SIC_SU6 (2 << 13) /* single-ended/unidirectional 6 wire */
+#define UCTRL_H1SIC_SB3 (3 << 13) /* single-ended/bidirectional 3 wire */
+#define UCTRL_OLOCKD (1 << 13) /* otg lock disable */
+#define UCTRL_H2LOCKD (1 << 12) /* HOST2 lock disable */
+#define UCTRL_H1UIE (1 << 12) /* Host1 ULPI interrupt enable */
+
+#if defined(CONFIG_ARCH_MX37)
+/* VBUS wakeup enable, UTMI only */
+#define UCTRL_VBUS_WKUP_EN (1 << 12)
+#elif defined(CONFIG_ARCH_MX25) || defined(CONFIG_ARCH_MX35)
+#define UCTRL_VBUS_WKUP_EN (1 << 15)
+#endif
+
+#define UCTRL_PP (1 << 11) /* power polarity bit */
+#define UCTRL_H1WIE (1 << 11) /* HOST1 wakeup intr enable */
+#define UCTRL_H1BPVAL_RXDP (1 << 10) /* HOST1 RxDp status in bypass mode */
+#define UCTRL_XCSO (1 << 10) /* Xcvr Clock Select for OTG port */
+#define UCTRL_H1BPVAL_RXDM (1 << 9) /* HOST1 RxDm status in bypass mode */
+#define UCTRL_XCSH2 (1 << 9) /* Xcvr Clock Select for Host port */
+#define UCTRL_H1PM (1 << 8) /* HOST1 power mask */
+#define UCTRL_IP_PULIDP (1 << 8) /* Ipp_Puimpel_Pullup_Dp */
+
+#define UCTRL_IP_PUE_UP (1 << 7) /* ipp_pue_pullup_dp */
+#define UCTRL_IP_PUE_DOWN (1 << 6) /* ipp_pue_pulldwn_dpdm */
+#define UCTRL_H2DT (1 << 5) /* HOST2 TLL disabled */
+#define UCTRL_H1DT (1 << 4) /* HOST1 TLL disabled */
+#define UCTRL_USBTE (1 << 4) /* USBT Transceiver enable */
+#define UCTRL_OCPOL (1 << 3) /* OverCurrent Polarity */
+#define UCTRL_OCE (1 << 2) /* OverCurrent Enable */
+#define UCTRL_H2OCPOL (1 << 2) /* OverCurrent Polarity of Host2 */
+#define UCTRL_H2OCS (1 << 1) /* Host OverCurrent State */
+#define UCTRL_BPE (1 << 0) /* bypass mode enable */
+#define UCTRL_OTD (1 << 0) /* OTG TLL Disable */
+#define UCTRL_OOCS (1 << 0) /* OTG OverCurrent State */
+
+/* USBCMD */
+#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
+#define UCMD_RESET (1 << 1) /* controller reset */
+#define UCMD_ITC_NO_THRESHOLD (~(0xff << 16)) /* Interrupt Threshold Control */
+
+/* OTG_MIRROR */
+#define OTGM_SESEND (1 << 4) /* B device session end */
+#define OTGM_VBUSVAL (1 << 3) /* Vbus valid */
+#define OTGM_BSESVLD (1 << 2) /* B session Valid */
+#define OTGM_ASESVLD (1 << 1) /* A session Valid */
+#define OTGM_IDIDG (1 << 0) /* OTG ID pin status */
+ /* 1=high: Operate as B-device */
+ /* 0=low : Operate as A-device */
+
+/* USB_PHY_CTRL_FUNC */
+/* PHY control0 Register Bit Masks */
+#define USB_UTMI_PHYCTRL_CONF2 (1 << 26)
+
+#define USB_UTMI_PHYCTRL_UTMI_ENABLE (1 << 24)
+#define USB_UTMI_PHYCTRL_CHGRDETEN (1 << 24) /* Enable Charger Detector */
+#define USB_UTMI_PHYCTRL_CHGRDETON (1 << 23) /* Charger Detector Power On Control */
+#define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */
+#define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */
+#define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */
+#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */
+/* USB_PHY_CTRL_FUNC2*/
+#define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3
+#define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_MASK 0x3
+#define USB_UTMI_PHYCTRL2_HSDEVSEL_SHIFT 19
+
+/* USB_CTRL_1 */
+#define USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
+#define USB_CTRL_UH2_EXT_CLK_EN (1 << 26)
+#define USB_CTRL_UH2_CLK_FROM_ULPI_PHY (1 << 2)
+/* ULPIVIEW register bits */
+#define ULPIVW_OFF (0x170)
+#define ULPIVW_WU (1 << 31) /* Wakeup */
+#define ULPIVW_RUN (1 << 30) /* read/write run */
+#define ULPIVW_WRITE (1 << 29) /* 0=read 1=write */
+#define ULPIVW_SS (1 << 27) /* SyncState */
+#define ULPIVW_PORT_MASK 0x07 /* Port field */
+#define ULPIVW_PORT_SHIFT 24
+#define ULPIVW_ADDR_MASK 0xFF /* data address field */
+#define ULPIVW_ADDR_SHIFT 16
+#define ULPIVW_RDATA_MASK 0xFF /* read data field */
+#define ULPIVW_RDATA_SHIFT 8
+#define ULPIVW_WDATA_MASK 0xFF /* write data field */
+#define ULPIVW_WDATA_SHIFT 0
+
+#define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */
+/* USB Clock on/off Control Register */
+#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */
+#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */
+extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata);
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 753a5988d85..3c8802cc54f 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -23,9 +23,14 @@
#ifndef __ASSEMBLY__
#include <linux/list.h>
+#define CLK_NAME_LEN 32
struct module;
struct clk {
+#ifdef CONFIG_CLK_DEBUG
+ char name[CLK_NAME_LEN];
+ struct dentry *dentry;
+#endif
int id;
/* Source clock this clk depends on */
struct clk *parent;
@@ -57,10 +62,26 @@ struct clk {
int (*set_parent) (struct clk *, struct clk *);
};
+int clk_get_usecount(struct clk *clk);
+
int clk_register(struct clk *clk);
void clk_unregister(struct clk *clk);
+/* Clock flags */
+#define RATE_PROPAGATES (1 << 0) /* Program children too */
+#define ALWAYS_ENABLED (1 << 1) /* Clock cannot be disabled */
+#define RATE_FIXED (1 << 2) /* Fixed clock rate */
+#define CPU_FREQ_TRIG_UPDATE (1 << 3) /* CPUFREQ trig update */
+#define AHB_HIGH_SET_POINT (1 << 4) /* Requires max AHB clock */
+#define AHB_MED_SET_POINT (1 << 5) /* Requires med AHB clock */
+
unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
+#ifdef CONFIG_CLK_DEBUG
+void clk_debug_register(struct clk *clk);
+#else
+static inline void clk_debug_register(struct clk *clk) {}
+#endif
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index f4ebdb817ab..a9727648c72 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -87,6 +87,8 @@ enum mxc_cpu_pwr_mode {
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void imx_print_silicon_rev(const char *cpu, int srev);
+struct pt_regs;
+
void avic_handle_irq(struct pt_regs *);
void tzic_handle_irq(struct pt_regs *);
void gic_handle_irq(struct pt_regs *);
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index def9ba53e23..1a0faba6dc3 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -144,6 +144,24 @@ struct platform_device *__init imx_add_imx_ssi(
const struct imx_imx_ssi_data *data,
const struct imx_ssi_platform_data *pdata);
+struct imx_spdif_data {
+ resource_size_t iobase;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_spdif(
+ const struct imx_spdif_data *data,
+ const struct mxc_spdif_platform_data *pdata);
+
+struct imx_spdif_dai_data {
+ resource_size_t iobase;
+ resource_size_t dmatx;
+ resource_size_t dmarx;
+};
+struct platform_device *__init imx_add_spdif_dai(
+ const struct imx_spdif_dai_data *data);
+
+struct platform_device *__init imx_add_spdif_audio_device(void);
+
#include <mach/imx-uart.h>
struct imx_imx_uart_3irq_data {
int id;
@@ -183,23 +201,55 @@ struct platform_device *__init imx_add_imx_udc(
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata);
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/mx3_camera.h>
-struct imx_ipu_core_data {
+#include <mach/mxc_vpu.h>
+struct imx_vpu_data {
+ resource_size_t iobase;
+ resource_size_t irq_ipi;
+ resource_size_t irq_jpg;
+ bool iram_enable;
+ int iram_size;
+ void (*reset) (void);
+ void (*pg) (int);
+};
+struct platform_device *__init imx_add_vpu(
+ const struct imx_vpu_data *data);
+
+#include <mach/ipu-v3.h>
+struct imx_ipuv3_data {
resource_size_t iobase;
- resource_size_t synirq;
- resource_size_t errirq;
+ resource_size_t iosize;
+ resource_size_t irq_err;
+ resource_size_t irq;
+ unsigned int irq_start;
+ int (*init) (int);
+ void (*pg) (int);
};
-struct platform_device *__init imx_add_ipu_core(
- const struct imx_ipu_core_data *data,
- const struct ipu_platform_data *pdata);
-struct platform_device *__init imx_alloc_mx3_camera(
- const struct imx_ipu_core_data *data,
- const struct mx3_camera_pdata *pdata);
-struct platform_device *__init imx_add_mx3_sdc_fb(
- const struct imx_ipu_core_data *data,
- struct mx3fb_platform_data *pdata);
+struct platform_device *__init imx_add_ipuv3(
+ const int id,
+ const struct imx_ipuv3_data *data,
+ struct imx_ipuv3_platform_data *pdata);
+
+struct platform_device *__init imx_add_ipuv3_fb(
+ const int id,
+ const struct ipuv3_fb_platform_data *pdata);
+
+#include <linux/fsl_devices.h>
+struct imx_tve_data {
+ resource_size_t iobase;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_tve(
+ const struct imx_tve_data *data,
+ const struct fsl_mxc_tve_platform_data *pdata);
+
+struct imx_ldb_data {
+ resource_size_t iobase;
+ resource_size_t iosize;
+};
+
+struct platform_device *__init imx_add_ldb(
+ const struct imx_ldb_data *data,
+ struct fsl_mxc_ldb_platform_data *pdata);
#include <mach/mx1_camera.h>
struct imx_mx1_camera_data {
@@ -331,3 +381,32 @@ struct imx_ahci_imx_data {
struct platform_device *__init imx_add_ahci_imx(
const struct imx_ahci_imx_data *data,
const struct ahci_platform_data *pdata);
+
+struct imx_srtc_data {
+ resource_size_t iobase;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_srtc(
+ const struct imx_srtc_data *data);
+
+struct imx_iim_data {
+ resource_size_t iobase;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_iim(
+ const struct imx_iim_data *data,
+ const struct mxc_iim_platform_data *pdata);
+
+#include <mach/mxc_gpu.h>
+struct imx_mxc_gpu_data {
+ resource_size_t irq_2d;
+ resource_size_t irq_3d;
+ resource_size_t iobase_2d;
+ resource_size_t iobase_3d;
+ resource_size_t gmem_base;
+ resource_size_t gmem_size;
+};
+
+struct platform_device *__init imx_add_mxc_gpu(
+ const struct imx_mxc_gpu_data *data,
+ const struct mxc_gpu_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index 233d0a5e2d6..dd41a6475be 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -53,6 +53,13 @@ struct imx_dma_data {
int priority;
};
+struct imx_pcm_dma_params {
+ enum sdma_peripheral_type peripheral_type;
+ int dma;
+ unsigned long dma_addr;
+ int burstsize;
+};
+
static inline int imx_dma_is_ipu(struct dma_chan *chan)
{
return !strcmp(dev_name(chan->device->dev), "ipu-core");
diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h
new file mode 100755
index 00000000000..735e5b3f365
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * USB Host side, platform-specific functionality.
+ */
+
+#include <linux/usb/fsl_xcvr.h>
+#include <mach/hardware.h>
+#include <mach/arc_otg.h>
+
+static void fsl_setup_phy(struct ehci_hcd *ehci,
+ enum fsl_usb2_phy_modes phy_mode,
+ int port_offset);
+
+static inline void fsl_platform_usb_setup(struct ehci_hcd *ehci)
+{
+ struct fsl_usb2_platform_data *pdata;
+
+ pdata = ehci_to_hcd(ehci)->self.controller->platform_data;
+ fsl_setup_phy(ehci, pdata->phy_mode, 0);
+}
+
+static inline void fsl_platform_set_host_mode(struct usb_hcd *hcd)
+{
+ unsigned int temp;
+ struct fsl_usb2_platform_data *pdata;
+
+ pdata = hcd->self.controller->platform_data;
+
+ if (pdata->xcvr_ops && pdata->xcvr_ops->set_host)
+ pdata->xcvr_ops->set_host();
+
+ /* set host mode */
+ temp = readl(hcd->regs + 0x1a8);
+ writel(temp | USBMODE_CM_HOST, hcd->regs + 0x1a8);
+}
+
+/* Needed for enable PP and i2c/serial transceivers */
+static inline void
+fsl_platform_set_vbus_power(struct fsl_usb2_platform_data *pdata, int on)
+{
+ u32 temp;
+
+ /* HCSPARAMS */
+ temp = readl(pdata->regs + 0x104);
+ /* Port Power Control */
+ if (temp & HCSPARAMS_PPC) {
+ temp = readl(pdata->regs + FSL_SOC_USB_PORTSC1);
+ if (on)
+ temp |= PORT_POWER;
+ else
+ temp &= ~PORT_POWER;
+
+ writel(temp, pdata->regs + FSL_SOC_USB_PORTSC1);
+ }
+
+ if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
+ pdata->xcvr_ops->set_vbus_power(pdata->xcvr_ops, pdata, on);
+}
+
+/* Set USB AHB burst length for host */
+static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd)
+{
+ struct fsl_usb2_platform_data *pdata;
+ unsigned int temp;
+
+ pdata = hcd->self.controller->platform_data;
+ if (pdata->change_ahb_burst) {
+ temp = readl(hcd->regs + FSL_SOC_USB_SBUSCFG);
+ writel((temp & (~(0x7))) | pdata->ahb_burst_mode,
+ hcd->regs + FSL_SOC_USB_SBUSCFG);
+ }
+
+ /* Increase TX fifo threshold for USB+ATA for i.mx35 2.0 */
+ if (cpu_is_mx35() && (imx_cpu_ver() >= IMX_CHIP_REVISION_2_0)) {
+ temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ /* Change TX FIFO threshold to be 0x20 */
+ writel((temp & (~(0x3f << 16))) | (0x20 << 16),
+ hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ }
+
+ /* Increase TX fifo threshold for USB+SD in Hostx */
+ if (cpu_is_mx53() && (strcmp("DR", pdata->name))) {
+ temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ /* Change TX FIFO threshold to be 0x08 */
+ writel((temp & (~(0x3f << 16))) | (0x08 << 16),
+ hcd->regs + FSL_SOC_USB_TXFILLTUNING);
+ }
+
+}
diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h
new file mode 100755
index 00000000000..53f9b05a3ba
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/fsl_usb_gadget.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * USB Gadget side, platform-specific functionality.
+ */
+
+#include <linux/usb/fsl_xcvr.h>
+
+/* Needed for i2c/serial transceivers */
+static inline void
+fsl_platform_set_device_mode(struct fsl_usb2_platform_data *pdata)
+{
+ if (pdata->xcvr_ops && pdata->xcvr_ops->set_device)
+ pdata->xcvr_ops->set_device();
+}
+
+static inline void
+fsl_platform_pullup_enable(struct fsl_usb2_platform_data *pdata)
+{
+ if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
+ pdata->xcvr_ops->pullup(1);
+}
+
+static inline void
+fsl_platform_pullup_disable(struct fsl_usb2_platform_data *pdata)
+{
+ if (pdata->xcvr_ops && pdata->xcvr_ops->pullup)
+ pdata->xcvr_ops->pullup(0);
+}
diff --git a/arch/arm/plat-mxc/include/mach/ipu-v3.h b/arch/arm/plat-mxc/include/mach/ipu-v3.h
new file mode 100644
index 00000000000..0816ae9b4c4
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ipu-v3.h
@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef __MACH_IPU_V3_H_
+#define __MACH_IPU_V3_H_
+
+#include <linux/ipu.h>
+
+/* IPU Driver channels definitions. */
+/* Note these are different from IDMA channels */
+#define IPU_MAX_CH 32
+#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
+ ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
+#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
+#define IPU_CHAN_ID(ch) (ch >> 24)
+#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
+#define NO_DMA 0x3F
+#define ALT 1
+/*!
+ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
+ * combination of an input (memory to IPU), output (IPU to memory), and/or
+ * secondary input IDMA channels and in some cases an Image Converter task.
+ * Some channels consist of only an input or output.
+ */
+typedef enum {
+ CHAN_NONE = -1,
+ MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
+ MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
+ MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
+
+ MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
+ MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
+ MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
+
+ MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
+ MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
+ MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
+ MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
+
+ MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
+ MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
+ MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
+ MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
+
+ DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+ DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
+
+ CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
+ CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
+ CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
+ CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
+
+ CSI_MEM = CSI_MEM0,
+
+ CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
+ CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
+
+ MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
+ MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
+ MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
+
+ MEM_PP_ADC = CHAN_NONE,
+ ADC_SYS2 = CHAN_NONE,
+
+} ipu_channel_t;
+
+/*!
+ * Enumeration of types of buffers for a logical channel.
+ */
+typedef enum {
+ IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */
+ IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */
+ IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */
+ IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */
+ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
+ IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
+} ipu_buffer_t;
+
+#define IPU_PANEL_SERIAL 1
+#define IPU_PANEL_PARALLEL 2
+
+/*!
+ * Enumeration of ADC channel operation mode.
+ */
+typedef enum {
+ Disable,
+ WriteTemplateNonSeq,
+ ReadTemplateNonSeq,
+ WriteTemplateUnCon,
+ ReadTemplateUnCon,
+ WriteDataWithRS,
+ WriteDataWoRS,
+ WriteCmd
+} mcu_mode_t;
+
+/*!
+ * Enumeration of ADC channel addressing mode.
+ */
+typedef enum {
+ FullWoBE,
+ FullWithBE,
+ XY
+} display_addressing_t;
+
+/*!
+ * Union of initialization parameters for a logical channel.
+ */
+typedef union {
+ struct {
+ uint32_t csi;
+ uint32_t mipi_id;
+ bool mipi_en;
+ bool interlaced;
+ } csi_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ uint32_t csi;
+ } csi_prp_enc_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ uint32_t outh_resize_ratio;
+ uint32_t outv_resize_ratio;
+ } mem_prp_enc_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ } mem_rot_enc_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ bool graphics_combine_en;
+ bool global_alpha_en;
+ bool key_color_en;
+ uint32_t csi;
+ } csi_prp_vf_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ bool graphics_combine_en;
+ bool global_alpha_en;
+ bool key_color_en;
+ display_port_t disp;
+ uint32_t out_left;
+ uint32_t out_top;
+ } csi_prp_vf_adc;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ uint32_t outh_resize_ratio;
+ uint32_t outv_resize_ratio;
+ bool graphics_combine_en;
+ bool global_alpha_en;
+ bool key_color_en;
+ uint32_t in_g_pixel_fmt;
+ uint8_t alpha;
+ uint32_t key_color;
+ bool alpha_chan_en;
+ ipu_motion_sel motion_sel;
+ enum v4l2_field field_fmt;
+ } mem_prp_vf_mem;
+ struct {
+ uint32_t temp;
+ } mem_prp_vf_adc;
+ struct {
+ uint32_t temp;
+ } mem_rot_vf_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ uint32_t outh_resize_ratio;
+ uint32_t outv_resize_ratio;
+ bool graphics_combine_en;
+ bool global_alpha_en;
+ bool key_color_en;
+ uint32_t in_g_pixel_fmt;
+ uint8_t alpha;
+ uint32_t key_color;
+ bool alpha_chan_en;
+ } mem_pp_mem;
+ struct {
+ uint32_t temp;
+ } mem_rot_mem;
+ struct {
+ uint32_t in_width;
+ uint32_t in_height;
+ uint32_t in_pixel_fmt;
+ uint32_t out_width;
+ uint32_t out_height;
+ uint32_t out_pixel_fmt;
+ bool graphics_combine_en;
+ bool global_alpha_en;
+ bool key_color_en;
+ display_port_t disp;
+ uint32_t out_left;
+ uint32_t out_top;
+ } mem_pp_adc;
+ struct {
+ uint32_t di;
+ bool interlaced;
+ uint32_t in_pixel_fmt;
+ uint32_t out_pixel_fmt;
+ } mem_dc_sync;
+ struct {
+ uint32_t temp;
+ } mem_sdc_fg;
+ struct {
+ uint32_t di;
+ bool interlaced;
+ uint32_t in_pixel_fmt;
+ uint32_t out_pixel_fmt;
+ bool alpha_chan_en;
+ } mem_dp_bg_sync;
+ struct {
+ uint32_t temp;
+ } mem_sdc_bg;
+ struct {
+ uint32_t di;
+ bool interlaced;
+ uint32_t in_pixel_fmt;
+ uint32_t out_pixel_fmt;
+ bool alpha_chan_en;
+ } mem_dp_fg_sync;
+ struct {
+ uint32_t di;
+ } direct_async;
+ struct {
+ display_port_t disp;
+ mcu_mode_t ch_mode;
+ uint32_t out_left;
+ uint32_t out_top;
+ } adc_sys1;
+ struct {
+ display_port_t disp;
+ mcu_mode_t ch_mode;
+ uint32_t out_left;
+ uint32_t out_top;
+ } adc_sys2;
+} ipu_channel_params_t;
+
+/*!
+ * Enumeration of IPU interrupt sources.
+ */
+enum ipu_irq_line {
+ IPU_IRQ_CSI0_OUT_EOF = 0,
+ IPU_IRQ_CSI1_OUT_EOF = 1,
+ IPU_IRQ_CSI2_OUT_EOF = 2,
+ IPU_IRQ_CSI3_OUT_EOF = 3,
+ IPU_IRQ_VDI_P_IN_EOF = 8,
+ IPU_IRQ_VDI_C_IN_EOF = 9,
+ IPU_IRQ_VDI_N_IN_EOF = 10,
+ IPU_IRQ_PP_IN_EOF = 11,
+ IPU_IRQ_PRP_IN_EOF = 12,
+ IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
+ IPU_IRQ_PP_GRAPH_IN_EOF = 15,
+ IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
+ IPU_IRQ_PP_ALPHA_IN_EOF = 18,
+ IPU_IRQ_PRP_ENC_OUT_EOF = 20,
+ IPU_IRQ_PRP_VF_OUT_EOF = 21,
+ IPU_IRQ_PP_OUT_EOF = 22,
+ IPU_IRQ_BG_SYNC_EOF = 23,
+ IPU_IRQ_BG_ASYNC_EOF = 24,
+ IPU_IRQ_FG_SYNC_EOF = 27,
+ IPU_IRQ_DC_SYNC_EOF = 28,
+ IPU_IRQ_FG_ASYNC_EOF = 29,
+ IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
+
+ IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
+ IPU_IRQ_DC_READ_EOF = 40,
+ IPU_IRQ_DC_ASYNC_EOF = 41,
+ IPU_IRQ_DC_CMD1_EOF = 42,
+ IPU_IRQ_DC_CMD2_EOF = 43,
+ IPU_IRQ_DC_MASK_EOF = 44,
+ IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
+ IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
+ IPU_IRQ_PP_ROT_IN_EOF = 47,
+ IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
+ IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
+ IPU_IRQ_PP_ROT_OUT_EOF = 50,
+ IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
+ IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
+
+ IPU_IRQ_DP_SF_START = 448 + 2,
+ IPU_IRQ_DP_SF_END = 448 + 3,
+ IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
+ IPU_IRQ_DC_FC_0 = 448 + 8,
+ IPU_IRQ_DC_FC_1 = 448 + 9,
+ IPU_IRQ_DC_FC_2 = 448 + 10,
+ IPU_IRQ_DC_FC_3 = 448 + 11,
+ IPU_IRQ_DC_FC_4 = 448 + 12,
+ IPU_IRQ_DC_FC_6 = 448 + 13,
+ IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
+ IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
+
+ IPU_IRQ_COUNT
+};
+
+/*!
+ * Bitfield of Display Interface signal polarities.
+ */
+typedef struct {
+ unsigned datamask_en:1;
+ unsigned int_clk:1;
+ unsigned interlaced:1;
+ unsigned odd_field_first:1;
+ unsigned clksel_en:1;
+ unsigned clkidle_en:1;
+ unsigned data_pol:1; /* true = inverted */
+ unsigned clk_pol:1; /* true = rising edge */
+ unsigned enable_pol:1;
+ unsigned Hsync_pol:1; /* true = active high */
+ unsigned Vsync_pol:1;
+} ipu_di_signal_cfg_t;
+
+/*!
+ * Bitfield of CSI signal polarities and modes.
+ */
+
+typedef struct {
+ unsigned data_width:4;
+ unsigned clk_mode:3;
+ unsigned ext_vsync:1;
+ unsigned Vsync_pol:1;
+ unsigned Hsync_pol:1;
+ unsigned pixclk_pol:1;
+ unsigned data_pol:1;
+ unsigned sens_clksrc:1;
+ unsigned pack_tight:1;
+ unsigned force_eof:1;
+ unsigned data_en_pol:1;
+ unsigned data_fmt;
+ unsigned csi;
+ unsigned mclk;
+} ipu_csi_signal_cfg_t;
+
+/*!
+ * Enumeration of CSI data bus widths.
+ */
+enum {
+ IPU_CSI_DATA_WIDTH_4,
+ IPU_CSI_DATA_WIDTH_8,
+ IPU_CSI_DATA_WIDTH_10,
+ IPU_CSI_DATA_WIDTH_16,
+};
+
+/*!
+ * Enumeration of CSI clock modes.
+ */
+enum {
+ IPU_CSI_CLK_MODE_GATED_CLK,
+ IPU_CSI_CLK_MODE_NONGATED_CLK,
+ IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
+ IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
+ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
+ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
+ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
+ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
+};
+
+enum {
+ IPU_CSI_MIPI_DI0,
+ IPU_CSI_MIPI_DI1,
+ IPU_CSI_MIPI_DI2,
+ IPU_CSI_MIPI_DI3,
+};
+
+typedef enum {
+ RGB,
+ YCbCr,
+ YUV
+} ipu_color_space_t;
+
+/*!
+ * Enumeration of ADC vertical sync mode.
+ */
+typedef enum {
+ VsyncNone,
+ VsyncInternal,
+ VsyncCSI,
+ VsyncExternal
+} vsync_t;
+
+typedef enum {
+ DAT,
+ CMD
+} cmddata_t;
+
+/*!
+ * Enumeration of ADC display update mode.
+ */
+typedef enum {
+ IPU_ADC_REFRESH_NONE,
+ IPU_ADC_AUTO_REFRESH,
+ IPU_ADC_AUTO_REFRESH_SNOOP,
+ IPU_ADC_SNOOPING,
+} ipu_adc_update_mode_t;
+
+/*!
+ * Enumeration of ADC display interface types (serial or parallel).
+ */
+enum {
+ IPU_ADC_IFC_MODE_SYS80_TYPE1,
+ IPU_ADC_IFC_MODE_SYS80_TYPE2,
+ IPU_ADC_IFC_MODE_SYS68K_TYPE1,
+ IPU_ADC_IFC_MODE_SYS68K_TYPE2,
+ IPU_ADC_IFC_MODE_3WIRE_SERIAL,
+ IPU_ADC_IFC_MODE_4WIRE_SERIAL,
+ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
+ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
+};
+
+enum {
+ IPU_ADC_IFC_WIDTH_8,
+ IPU_ADC_IFC_WIDTH_16,
+};
+
+/*!
+ * Enumeration of ADC display interface burst mode.
+ */
+enum {
+ IPU_ADC_BURST_WCS,
+ IPU_ADC_BURST_WBLCK,
+ IPU_ADC_BURST_NONE,
+ IPU_ADC_BURST_SERIAL,
+};
+
+/*!
+ * Enumeration of ADC display interface RW signal timing modes.
+ */
+enum {
+ IPU_ADC_SER_NO_RW,
+ IPU_ADC_SER_RW_BEFORE_RS,
+ IPU_ADC_SER_RW_AFTER_RS,
+};
+
+/*!
+ * Bitfield of ADC signal polarities and modes.
+ */
+typedef struct {
+ unsigned data_pol:1;
+ unsigned clk_pol:1;
+ unsigned cs_pol:1;
+ unsigned rs_pol:1;
+ unsigned addr_pol:1;
+ unsigned read_pol:1;
+ unsigned write_pol:1;
+ unsigned Vsync_pol:1;
+ unsigned burst_pol:1;
+ unsigned burst_mode:2;
+ unsigned ifc_mode:3;
+ unsigned ifc_width:5;
+ unsigned ser_preamble_len:4;
+ unsigned ser_preamble:8;
+ unsigned ser_rw_mode:2;
+} ipu_adc_sig_cfg_t;
+
+/*!
+ * Enumeration of ADC template commands.
+ */
+enum {
+ RD_DATA,
+ RD_ACK,
+ RD_WAIT,
+ WR_XADDR,
+ WR_YADDR,
+ WR_ADDR,
+ WR_CMND,
+ WR_DATA,
+};
+
+/*!
+ * Enumeration of ADC template command flow control.
+ */
+enum {
+ SINGLE_STEP,
+ PAUSE,
+ STOP,
+};
+
+
+/*Define template constants*/
+#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */
+#define TEMPLATE_BUF_SIZE 0x20 /*size of template */
+
+/*!
+ * Define to create ADC template command entry.
+ */
+#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
+ ((oc) << 24) | (dat))
+
+typedef struct {
+ u32 reg;
+ u32 value;
+} ipu_lpmc_reg_t;
+
+#define IPU_LPMC_REG_READ 0x80000000L
+
+#define CSI_MCLK_VF 1
+#define CSI_MCLK_ENC 2
+#define CSI_MCLK_RAW 4
+#define CSI_MCLK_I2C 8
+
+struct ipu_soc;
+/* Common IPU API */
+struct ipu_soc *ipu_get_soc(int id);
+int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
+void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
+
+static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
+{
+#ifdef CONFIG_MXC_IPU_V3D
+ return (rot < IPU_ROTATE_HORIZ_FLIP);
+#else
+ return (rot < IPU_ROTATE_90_RIGHT);
+#endif
+}
+
+int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ ipu_rotate_mode_t rot_mode,
+ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
+ dma_addr_t phyaddr_2,
+ uint32_t u_offset, uint32_t v_offset);
+
+int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum, dma_addr_t phyaddr);
+
+int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t pixel_fmt,
+ uint16_t width, uint16_t height,
+ uint32_t stride,
+ uint32_t u, uint32_t v,
+ uint32_t vertical_offset, uint32_t horizontal_offset);
+
+int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
+ ipu_buffer_t type, uint32_t bufNum);
+int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
+
+int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
+int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
+
+int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
+int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum);
+void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
+ uint32_t bufNum);
+uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
+int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
+int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
+int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
+
+int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
+int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
+
+int ipu_lowpwr_display_enable(void);
+int ipu_lowpwr_display_disable(void);
+
+void ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
+void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
+void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
+int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
+ irqreturn_t(*handler) (int, void *),
+ uint32_t irq_flags, const char *devname, void *dev_id);
+void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
+bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
+void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
+
+/* two stripe calculations */
+struct stripe_param{
+ unsigned int input_width; /* width of the input stripe */
+ unsigned int output_width; /* width of the output stripe */
+ unsigned int input_column; /* the first column on the input stripe */
+ unsigned int output_column; /* the first column on the output stripe */
+ unsigned int idr;
+ /* inverse downisizing ratio parameter; expressed as a power of 2 */
+ unsigned int irr;
+ /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
+};
+int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
+ unsigned int output_frame_width,
+ const unsigned int maximal_stripe_width,
+ const unsigned long long cirr,
+ const unsigned int equal_stripes,
+ u32 input_pixelformat,
+ u32 output_pixelformat,
+ struct stripe_param *left,
+ struct stripe_param *right);
+
+/* SDC API */
+int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
+ uint32_t pixel_clk,
+ uint16_t width, uint16_t height,
+ uint32_t pixel_fmt,
+ uint16_t h_start_width, uint16_t h_sync_width,
+ uint16_t h_end_width, uint16_t v_start_width,
+ uint16_t v_sync_width, uint16_t v_end_width,
+ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+
+void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
+
+int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
+ int16_t y_pos);
+int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
+ int16_t *y_pos);
+int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+ uint8_t alpha);
+int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+ uint32_t colorKey);
+int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
+ int constk[], int slopek[]);
+
+int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
+ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
+void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
+void ipu_reset_disp_panel(struct ipu_soc *ipu);
+
+/* CMOS Sensor Interface API */
+int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
+ uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
+
+int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
+
+int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
+
+static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
+ bool flag, bool wait)
+{
+ return ipu_csi_enable_mclk(ipu, csi, flag, wait);
+}
+
+int ipu_csi_read_mclk_flag(void);
+
+void ipu_csi_flash_strobe(bool flag);
+
+void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
+
+void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
+
+void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
+
+uint32_t bytes_per_pixel(uint32_t fmt);
+
+struct ipuv3_fb_platform_data {
+ char disp_dev[32];
+ u32 interface_pix_fmt;
+ char *mode_str;
+ int default_bpp;
+ bool int_clk;
+
+ /* reserved mem */
+ resource_size_t res_base;
+ resource_size_t res_size;
+};
+
+struct imx_ipuv3_platform_data {
+ int rev;
+ int (*init) (int);
+ void (*pg) (int);
+
+ char *csi_clk[2];
+};
+
+#endif /* __MACH_IPU_V3_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
index a9221f1cc1a..f7344ab81e4 100644
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ b/arch/arm/plat-mxc/include/mach/ipu.h
@@ -14,6 +14,7 @@
#include <linux/types.h>
#include <linux/dmaengine.h>
+#include <linux/ipu.h>
/* IPU DMA Controller channel definitions. */
enum ipu_channel {
@@ -95,35 +96,10 @@ enum ipu_color_space {
IPU_COLORSPACE_YUV
};
-/*
- * Enumeration of IPU rotation modes
- */
-enum ipu_rotate_mode {
- /* Note the enum values correspond to BAM value */
- IPU_ROTATE_NONE = 0,
- IPU_ROTATE_VERT_FLIP = 1,
- IPU_ROTATE_HORIZ_FLIP = 2,
- IPU_ROTATE_180 = 3,
- IPU_ROTATE_90_RIGHT = 4,
- IPU_ROTATE_90_RIGHT_VFLIP = 5,
- IPU_ROTATE_90_RIGHT_HFLIP = 6,
- IPU_ROTATE_90_LEFT = 7,
-};
-
struct ipu_platform_data {
unsigned int irq_base;
};
-/*
- * Enumeration of DI ports for ADC.
- */
-enum display_port {
- DISP0,
- DISP1,
- DISP2,
- DISP3
-};
-
struct idmac_video_param {
unsigned short in_width;
unsigned short in_height;
@@ -135,7 +111,7 @@ struct idmac_video_param {
bool graphics_combine_en;
bool global_alpha_en;
bool key_color_en;
- enum display_port disp;
+ display_port_t disp;
unsigned short out_left;
unsigned short out_top;
};
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a47f..aea89f27471 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -21,7 +21,33 @@
/*
* Databahn
*/
-#define MX50_DATABAHN_BASE_ADDR 0x14000000
+#define MX50_DATABAHN_BASE_ADDR 0x14000000
+#define DATABAHN_CTL_REG19 0x4c
+#define DATABAHN_CTL_REG20 0x50
+#define DATABAHN_CTL_REG21 0x54
+#define DATABAHN_CTL_REG22 0x58
+#define DATABAHN_CTL_REG23 0x5c
+#define DATABAHN_CTL_REG42 0xa8
+#define DATABAHN_CTL_REG43 0xac
+#define DATABAHN_CTL_REG55 0xdc
+#define DATABAHN_CTL_REG63 0xFC
+#define DATABAHN_CTL_REG73 0x124
+#define DATABAHN_CTL_REG74 0x128
+#define DATABAHN_CTL_REG75 0x12C
+#define DATABAHN_CTL_REG83 0x14C
+#define LOWPOWER_CONTROL_MASK 0x1F
+#define LOWPOWER_AUTOENABLE_MASK 0x1F
+#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16)
+#define LOWPOWER_EXTERNAL_CNT_OFFSET 16
+#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8)
+#define LOWPOWER_INTERNAL_CNT_OFFSET 8
+#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16)
+#define LOWPOWER_REFRESH_ENABLE_OFFSET 16
+#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF
+#define LOWPOWER_REFRESH_HOLD_OFFSET 0
+#define MX50_LPDDR2 (0x5 << 8)
+#define MX50_MDDR (0x1 << 8)
+
/*
* Graphics Memory of GPU
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index cdf07c65ec1..d198524cfe7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,8 +14,9 @@
#define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
-#define MX51_GPU_BASE_ADDR 0x20000000
-#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
+#define MX51_GPU_GMEM_BASE_ADDR 0x20000000
+#define MX51_GPU_GMEM_SIZE SZ_128K
+#define MX51_GPU_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
/*
@@ -128,6 +129,18 @@
#define MX51_IO_P2V(x) IMX_IO_P2V(x)
#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
+/* PGC */
+#define MX51_GPC_BASE (MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR))
+#define MX51_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
+#define MX51_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
+#define MX51_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
+#define MX51_PGC_IPU_PGCR (MX51_PGC_IPU_BASE + 0x0)
+#define MX51_PGC_IPU_PGSR (MX51_PGC_IPU_BASE + 0xC)
+#define MX51_PGC_VPU_PGCR (MX51_PGC_VPU_BASE + 0x0)
+#define MX51_PGC_VPU_PGSR (MX51_PGC_VPU_BASE + 0xC)
+#define MX51_PGC_GPU_PGCR (MX51_PGC_GPU_BASE + 0x0)
+#define MX51_PGC_GPU_PGSR (MX51_PGC_GPU_BASE + 0xC)
+
/*
* defines for SPBA modules
*/
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index a37e8c35399..1f5097a2ed2 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -33,9 +33,10 @@
* Graphics Memory of GPU
*/
#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
-#define MX53_GPU2D_BASE_ADDR 0x20000000
-#define MX53_GPU_BASE_ADDR 0x30000000
+#define MX53_GPU2D_BASE_ADDR 0x20000000
+#define MX53_GPU_BASE_ADDR 0x30000000
#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
+#define MX53_GPU_GMEM_SIZE SZ_256K
#define MX53_DEBUG_BASE_ADDR 0x40000000
#define MX53_DEBUG_SIZE SZ_1M
@@ -158,6 +159,18 @@
#define MX53_IO_P2V(x) IMX_IO_P2V(x)
#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
+/* PGC */
+#define MX53_GPC_BASE (MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR))
+#define MX53_PGC_IPU_BASE (MX53_GPC_BASE + 0x220)
+#define MX53_PGC_VPU_BASE (MX53_GPC_BASE + 0x240)
+#define MX53_PGC_GPU_BASE (MX53_GPC_BASE + 0x260)
+#define MX53_PGC_IPU_PGCR (MX53_PGC_IPU_BASE + 0x0)
+#define MX53_PGC_IPU_PGSR (MX53_PGC_IPU_BASE + 0xC)
+#define MX53_PGC_VPU_PGCR (MX53_PGC_VPU_BASE + 0x0)
+#define MX53_PGC_VPU_PGSR (MX53_PGC_VPU_BASE + 0xC)
+#define MX53_PGC_GPU_PGCR (MX53_PGC_GPU_BASE + 0x0)
+#define MX53_PGC_GPU_PGSR (MX53_PGC_GPU_BASE + 0xC)
+
/*
* defines for SPBA modules
*/
@@ -338,4 +351,14 @@
#define MX53_INT_GPIO7_LOW 107
#define MX53_INT_GPIO7_HIGH 108
+/*!
+ * IIM bank info
+ */
+#define MXC_IIM_MX51_BANK_START_ADDR 0x0800
+#define MXC_IIM_MX51_BANK_END_ADDR 0x147c
+#define MXC_IIM_MX53_BANK_START_ADDR 0x0800
+#define MXC_IIM_MX53_BANK_END_ADDR 0x183c
+#define MXC_IIM_MX53_BANK_AREA_1_OFFSET 0xc00
+#define MXC_IIM_MX53_MAC_ADDR_OFFSET 0x24
+
#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a4d36d601d5..eb49d7114ca 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -50,6 +50,36 @@
#define IMX_CHIP_REVISION_3_3 0x33
#define IMX_CHIP_REVISION_UNKNOWN 0xff
+#define IMX_CHIP_REVISION_1_0_STRING "1.0"
+#define IMX_CHIP_REVISION_1_1_STRING "1.1"
+#define IMX_CHIP_REVISION_1_2_STRING "1.2"
+#define IMX_CHIP_REVISION_1_3_STRING "1.3"
+#define IMX_CHIP_REVISION_2_0_STRING "2.0"
+#define IMX_CHIP_REVISION_2_1_STRING "2.1"
+#define IMX_CHIP_REVISION_2_2_STRING "2.2"
+#define IMX_CHIP_REVISION_2_3_STRING "2.3"
+#define IMX_CHIP_REVISION_3_0_STRING "3.0"
+#define IMX_CHIP_REVISION_3_1_STRING "3.1"
+#define IMX_CHIP_REVISION_3_2_STRING "3.2"
+#define IMX_CHIP_REVISION_3_3_STRING "3.3"
+#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
+
+#define IMX_BOARD_REV_1 0x000
+#define IMX_BOARD_REV_2 0x100
+#define IMX_BOARD_REV_3 0x200
+
+#ifndef __ASSEMBLY__
+extern unsigned int system_rev;
+#define board_is_rev(rev) (((system_rev & 0x0F00) == rev) ? 1 : 0)
+#define imx_cpu_ver() (system_rev & 0xFF)
+#endif
+
+#ifdef CONFIG_ARCH_MX5
+#define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_2))
+#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_1))
+#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3))
+#endif
+
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif
@@ -162,18 +192,37 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx53() (0)
#endif
+#define cpu_is_mx6q() (0)
+
#ifndef __ASSEMBLY__
+#include <mach/common.h>
+
struct cpu_op {
+ u32 pll_reg;
+ u32 pll_rate;
u32 cpu_rate;
+ u32 pdr0_reg;
+ u32 pdf;
+ u32 mfi;
+ u32 mfd;
+ u32 mfn;
+ u32 cpu_voltage;
+ u32 cpu_podf;
};
int tzic_enable_wake(int is_idle);
+extern void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern struct cpu_op *(*get_cpu_op)(int *op);
#endif
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
+#define MXC_PGCR_PCR 1
+#define MXC_SRPGCR_PCR 1
+#define MXC_EMPGCR_PCR 1
+#define MXC_PGSR_PSR 1
+
#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
new file mode 100644
index 00000000000..35aefaa8796
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver
+ */
+
+/*!
+ * @file arch-mxc/mxc_dvfs.h
+ *
+ * @brief This file contains the DVFS configuration structure definition.
+ *
+ *
+ * @ingroup DVFS
+ */
+
+#ifndef __ASM_ARCH_MXC_DVFS_H__
+#define __ASM_ARCH_MXC_DVFS_H__
+
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+
+extern void __iomem *gpc_base;
+extern void __iomem *ccm_base;
+
+#define MXC_GPCCNTR_GPCIRQ2M (1 << 25)
+#define MXC_GPCCNTR_GPCIRQ2 (1 << 24)
+#define MXC_GPCCNTR_GPCIRQM (1 << 21)
+#define MXC_GPCCNTR_GPCIRQ_ARM (1 << 20)
+#define MXC_GPCCNTR_GPCIRQ_SDMA (0 << 20)
+#define MXC_GPCCNTR_DVFS0CR (1 << 16)
+#define MXC_GPCCNTR_DVFS1CR (1 << 17)
+#define MXC_GPCCNTR_ADU_MASK 0x8000
+#define MXC_GPCCNTR_ADU (1 << 15)
+#define MXC_GPCCNTR_STRT (1 << 14)
+#define MXC_GPCCNTR_FUPD_MASK 0x2000
+#define MXC_GPCCNTR_FUPD (1 << 13)
+#define MXC_GPCCNTR_HTRI_MASK 0x0000000F
+#define MXC_GPCCNTR_HTRI_OFFSET 0
+
+#define MXC_GPCVCR_VINC_MASK 0x00020000
+#define MXC_GPCVCR_VINC_OFFSET 17
+#define MXC_GPCVCR_VCNTU_MASK 0x00010000
+#define MXC_GPCVCR_VCNTU_OFFSET 16
+#define MXC_GPCVCR_VCNT_MASK 0x00007FFF
+#define MXC_GPCVCR_VCNT_OFFSET 0
+
+/* DVFS-PER */
+#define MXC_DVFSPER_PMCR0_UDCS (1 << 27)
+#define MXC_DVFSPER_PMCR0_UDCS_MASK 0x8000000
+#define MXC_DVFSPER_PMCR0_ENABLE_MASK 0x10
+#define MXC_DVFSPER_PMCR0_ENABLE (1 << 4)
+
+#define MXC_DVFSLTR0_UPTHR_MASK 0x0FC00000
+#define MXC_DVFSLTR0_UPTHR_OFFSET 22
+#define MXC_DVFSLTR0_DNTHR_MASK 0x003F0000
+#define MXC_DVFSLTR0_DNTHR_OFFSET 16
+
+#define MXC_DVFSLTR1_PNCTHR_MASK 0x0000003F
+#define MXC_DVFSLTR1_PNCTHR_OFFSET 0
+#define MXC_DVFSLTR1_DNCNT_MASK 0x003FC000
+#define MXC_DVFSLTR1_DNCNT_OFFSET 14
+#define MXC_DVFSLTR1_UPCNT_MASK 0x00003FC0
+#define MXC_DVFSLTR1_UPCNT_OFFSET 6
+#define MXC_DVFSLTR1_LTBRSR 0x800000
+#define MXC_DVFSLTR1_LTBRSH 0x400000
+
+#define MXC_DVFSLTR2_EMAC_MASK 0x000001FF
+#define MXC_DVFSLTR2_EMAC_OFFSET 0
+
+#define MXC_DVFSPMCR0_UDCS 0x8000000
+#define MXC_DVFSPMCR0_DVFEV 0x800000
+#define MXC_DVFSPMCR0_DVFIS 0x400000
+#define MXC_DVFSPMCR0_LBMI 0x200000
+#define MXC_DVFSPMCR0_LBFL 0x100000
+#define MXC_DVFSPMCR0_LBFC_MASK 0xC0000
+#define MXC_DVFSPMCR0_LBFC_OFFSET 18
+#define MXC_DVFSPMCR0_FSVAIM 0x00008000
+#define MXC_DVFSPMCR0_FSVAI_MASK 0x00006000
+#define MXC_DVFSPMCR0_FSVAI_OFFSET 13
+#define MXC_DVFSPMCR0_WFIM 0x00000400
+#define MXC_DVFSPMCR0_WFIM_OFFSET 10
+#define MXC_DVFSPMCR0_DVFEN 0x00000010
+
+#define MXC_DVFSPMCR1_P1INM 0x00100000
+#define MXC_DVFSPMCR1_P1ISM 0x00080000
+#define MXC_DVFSPMCR1_P1IFM 0x00040000
+#define MXC_DVFSPMCR1_P4PM 0x00020000
+#define MXC_DVFSPMCR1_P2PM 0x00010000
+
+/* DVFS CORE register offsets*/
+#define MXC_DVFSCORE_THRS 0x00
+#define MXC_DVFSCORE_COUN 0x04
+#define MXC_DVFSCORE_SIG1 0x08
+#define MXC_DVFSCORE_SIG0 0x0C
+#define MXC_DVFSCORE_GPC0 0x10
+#define MXC_DVFSCORE_GPC1 0x14
+#define MXC_DVFSCORE_GPBT 0x18
+#define MXC_DVFSCORE_EMAC 0x1C
+#define MXC_DVFSCORE_CNTR 0x20
+#define MXC_DVFSCORE_LTR0_0 0x24
+#define MXC_DVFSCORE_LTR0_1 0x28
+#define MXC_DVFSCORE_LTR1_0 0x2C
+#define MXC_DVFSCORE_LTR1_1 0x30
+#define MXC_DVFSCORE_PT0 0x34
+#define MXC_DVFSCORE_PT1 0x38
+#define MXC_DVFSCORE_PT2 0x3C
+#define MXC_DVFSCORE_PT3 0x40
+
+/*
+ * DVFS structure
+ */
+struct dvfs_wp {
+ int upthr;
+ int downthr;
+ int panicthr;
+ int upcnt;
+ int downcnt;
+ int emac;
+};
+
+struct mxc_dvfs_platform_data {
+ /** Supply voltage regulator name string */
+ char *reg_id;
+ /* CPU clock name string */
+ char *clk1_id;
+ /* DVFS clock name string */
+ char *clk2_id;
+ /* The base address of the DVFS core */
+ void __iomem *membase;
+ /* The interrupt number used by the DVFS core */
+ int irq;
+ /* GPC control reg offset */
+ int gpc_cntr_offset;
+ /* GPC voltage counter reg offset */
+ int gpc_vcr_offset;
+ /* CCM DVFS control reg offset */
+ int ccm_cdcr_offset;
+ /* CCM ARM clock root reg offset */
+ int ccm_cacrr_offset;
+ /* CCM divider handshake in-progress reg offset */
+ int ccm_cdhipr_offset;
+ /* PREDIV mask */
+ u32 prediv_mask;
+ /* PREDIV offset */
+ int prediv_offset;
+ /* PREDIV value */
+ int prediv_val;
+ /* DIV3CK mask */
+ u32 div3ck_mask;
+ /* DIV3CK offset */
+ int div3ck_offset;
+ /* DIV3CK value */
+ int div3ck_val;
+ /* EMAC value */
+ int emac_val;
+ /* Frequency increase threshold. Increase frequency change request
+ will be sent if DVFS counter value will be more than this value */
+ int upthr_val;
+ /* Frequency decrease threshold. Decrease frequency change request
+ will be sent if DVFS counter value will be less than this value */
+ int dnthr_val;
+ /* Panic threshold. Panic frequency change request
+ will be sent if DVFS counter value will be more than this value */
+ int pncthr_val;
+ /* The amount of times the up threshold should be exceeded
+ before DVFS will trigger frequency increase request */
+ int upcnt_val;
+ /* The amount of times the down threshold should be exceeded
+ before DVFS will trigger frequency decrease request */
+ int dncnt_val;
+ /* Delay time in us */
+ int delay_time;
+ /* Number of woking points supported */
+ int num_wp;
+};
+
+/*!
+ * This structure is used to define the dvfs controller's platform
+ * data. It includes the regulator name string and DVFS clock name string.
+ */
+struct mxc_dvfsper_data {
+ /** Regulator name string */
+ char *reg_id;
+ /* DVFS clock name string */
+ char *clk_id;
+ /* The base address of the DVFS per */
+ void __iomem *membase;
+ /* GPC control reg address */
+ void __iomem *gpc_cntr_reg_addr;
+ /* GPC VCR reg address */
+ void __iomem *gpc_vcr_reg_addr;
+ /* DVFS enable bit */
+ u32 dvfs_enable_bit;
+ /* DVFS ADU bit */
+ int gpc_adu;
+ /* VAI mask */
+ u32 vai_mask;
+ /* VAI offset */
+ int vai_offset;
+ /* Mask DVFS interrupt */
+ u32 irq_mask;
+ /* Div3 clock offset. */
+ u32 div3_offset;
+ /*div3 clock mask. */
+ u32 div3_mask;
+ /*div3 clock divider */
+ u32 div3_div;
+ /* LP voltage - high setpoint*/
+ u32 lp_high;
+ /* LP voltage - low setpoint*/
+ u32 lp_low;
+};
+
+/*!
+ * This structure is used to define the platform data of bus freq
+ * driver. It includes the regulator name strings.
+ */
+
+struct mxc_bus_freq_platform_data {
+ /* VDDGP regulator name */
+ char *gp_reg_id;
+ /* VCC regulator name */
+ char *lp_reg_id;
+};
+
+#if defined(CONFIG_MXC_DVFS_PER)
+extern int start_dvfs_per(void);
+extern void stop_dvfs_per(void);
+extern int dvfs_per_active(void);
+extern int dvfs_per_divider_active(void);
+extern int dvfs_per_pixel_clk_limit(void);
+#else
+static inline int start_dvfs_per(void)
+{
+ return 0;
+}
+
+static inline void stop_dvfs_per(void)
+{
+}
+
+static inline int dvfs_per_active(void)
+{
+ return 0;
+}
+
+static inline int dvfs_per_divider_active(void)
+{
+ return 0;
+}
+
+static inline int dvfs_per_pixel_clk_limit(void)
+{
+ return 0;
+}
+
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_ARCH_MXC_DVFS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_gpu.h b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
new file mode 100644
index 00000000000..a43d6ec99bf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_gpu.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef __MACH_MXC_GPU_H_
+#define __MACH_MXC_GPU_H_
+
+struct mxc_gpu_platform_data {
+ int z160_revision;
+ resource_size_t reserved_mem_base;
+ resource_size_t reserved_mem_size;
+};
+
+#endif /* __MACH_MXC_GPU_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_vpu.h b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
new file mode 100644
index 00000000000..0f81fb9eb7d
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc_vpu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU Lesser General
+ * Public License. You may obtain a copy of the GNU Lesser General
+ * Public License Version 2.1 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/lgpl-license.html
+ * http://www.gnu.org/copyleft/lgpl.html
+ */
+
+/*!
+ * @defgroup VPU Video Processor Unit Driver
+ */
+
+/*!
+ * @file arch-mxc/mxc_vpu.h
+ *
+ * @brief VPU system initialization and file operation definition
+ *
+ * @ingroup VPU
+ */
+
+#ifndef __ASM_ARCH_MXC_VPU_H__
+#define __ASM_ARCH_MXC_VPU_H__
+
+#include <linux/fs.h>
+
+struct mxc_vpu_platform_data {
+ bool iram_enable;
+ int iram_size;
+ void (*reset) (void);
+ void (*pg) (int);
+};
+
+struct vpu_mem_desc {
+ u32 size;
+ dma_addr_t phy_addr;
+ u32 cpu_addr; /* cpu address to free the dma mem */
+ u32 virt_uaddr; /* virtual user space address */
+};
+
+#define VPU_IOC_MAGIC 'V'
+
+#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
+#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
+#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
+#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3)
+#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4)
+#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6)
+#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7)
+#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8)
+#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
+#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
+#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
+
+#define BIT_CODE_RUN 0x000
+#define BIT_CODE_DOWN 0x004
+#define BIT_INT_CLEAR 0x00C
+#define BIT_INT_STATUS 0x010
+
+#define MJPEG_PIC_STATUS_REG 0x3004
+
+#define BIT_WORK_CTRL_BUF_BASE 0x100
+#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4)
+#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0)
+#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1)
+#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2)
+#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3)
+#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4)
+#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5)
+
+#define BIT_RESET_CTRL 0x11C
+
+/* i could be 0, 1, 2, 3 */
+#define BIT_RD_PTR_BASE 0x120
+#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8)
+#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4)
+
+/* i could be 0, 1, 2, 3 */
+#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140)
+#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4)
+
+#define BIT_BUSY_FLAG 0x160
+#define BIT_RUN_COMMAND 0x164
+#define BIT_INT_ENABLE 0x170
+
+#define BITVAL_PIC_RUN 8
+
+#define VPU_SLEEP_REG_VALUE 10
+#define VPU_WAKE_REG_VALUE 11
+
+int vl2cc_init(u32 vl2cc_hw_base);
+void vl2cc_enable(void);
+void vl2cc_flush(void);
+void vl2cc_disable(void);
+void vl2cc_cleanup(void);
+
+int vl2cc_init(u32 vl2cc_hw_base);
+void vl2cc_enable(void);
+void vl2cc_flush(void);
+void vl2cc_disable(void);
+void vl2cc_cleanup(void);
+
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/sdram_autogating.h b/arch/arm/plat-mxc/include/mach/sdram_autogating.h
new file mode 100644
index 00000000000..e102add8a4c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/sdram_autogating.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup DVFS Dynamic Voltage and Frequency Scaling (DVFS) Driver
+ */
+
+/*!
+ * @file arch-mxc/sdram_autogating.h
+ *
+ * @brief This file contains the SDRAM autogating function prototypes
+ *
+ *
+ * @ingroup PM
+ */
+
+#ifndef __ASM_ARCH_SDRAM_AUTOGATING_H__
+#define __ASM_ARCH_SDRAM_AUTOGATING_H__
+
+#ifdef __KERNEL__
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+#include <linux/device.h>
+
+
+#ifdef CONFIG_ARCH_MX5
+extern void start_sdram_autogating(void);
+extern void stop_sdram_autogating(void);
+extern int sdram_autogating_active(void);
+#else
+static inline void start_sdram_autogating(void)
+{}
+
+static inline void stop_sdram_autogating(void)
+{}
+
+static inline int sdram_autogating_active(void)
+{
+ return 0;
+}
+#endif
+
+#endif /*__KERNEL__ */
+#endif /* __ASM_ARCH_MXC_DVFS_H__ */
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 4b0fe285e83..dd6b74e378c 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -57,6 +57,7 @@
/* MX31, MX35, MX25, MX5 */
#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG (1 << 6)
+#define V2_TCTL_CLK_PER (2 << 6)
#define V2_TCTL_FRR (1 << 9)
#define V2_IR 0x0c
#define V2_TSTAT 0x08
@@ -304,7 +305,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
__raw_writel(0, timer_base + MXC_TPRER); /* see da