* Patch by Rishi Bhattacharya, 08 May 2004:

  Add support for TI OMAP5912 OSK Board

* Patch by Sam Song May, 07 May 2004:
  Fix typo of UPM table for rmu board

10 files changed, 1546 insertions, 166 deletions

diff --git a/board/netta/codec.c b/board/netta/codec.c
index fb2dab813..01ab14bc5 100644
--- a/board/netta/codec.c
+++ b/board/netta/codec.c
@@ -38,8 +38,8 @@
 #define PCM_RESYNC_CMD_CH_A	0x42
 #define PCM_RESYNC_CMD_CH_B	0x4A
 
-#define ACTIVE_HOOK_LEV_4       0
-#define ACTIVE_HOOK_LEV_12      1
+#define ACTIVE_HOOK_LEV_4	0
+#define ACTIVE_HOOK_LEV_12	1
 
 #define SLIC_P_NORMAL		0x01
 
@@ -140,17 +140,17 @@
 
 #define CIS_DAT_ADDR		0x00
 
-#define	LEC_LEN_ADDR		0x3A
-#define	LEC_POWR_ADDR		0x3B
-#define	LEC_DELP_ADDR		0x3C
-#define	LEC_DELQ_ADDR		0x3D
-#define	LEC_GAIN_XI_ADDR	0x3E
-#define	LEC_GAIN_RI_ADDR	0x3F
-#define	LEC_GAIN_XO_ADDR	0x40
-#define	LEC_RES_1_ADDR		0x41
+#define LEC_LEN_ADDR		0x3A
+#define LEC_POWR_ADDR		0x3B
+#define LEC_DELP_ADDR		0x3C
+#define LEC_DELQ_ADDR		0x3D
+#define LEC_GAIN_XI_ADDR	0x3E
+#define LEC_GAIN_RI_ADDR	0x3F
+#define LEC_GAIN_XO_ADDR	0x40
+#define LEC_RES_1_ADDR		0x41
 #define LEC_RES_2_ADDR		0x42
 
-#define NLP_POW_LPF_ADDR    	0x30
+#define NLP_POW_LPF_ADDR	0x30
 #define NLP_POW_LPS_ADDR	0x31
 #define NLP_BN_LEV_X_ADDR	0x32
 #define NLP_BN_LEV_R_ADDR	0x33
@@ -170,18 +170,18 @@
 #define NLP_CT_LEV_RE_ADDR	0x41
 #define NLP_CTRL_ADDR		0x42
 
-#define UTD_CF_H_ADDR           0x4B
-#define UTD_CF_L_ADDR           0x4C
-#define UTD_BW_H_ADDR           0x4D
-#define UTD_BW_L_ADDR           0x4E
-#define UTD_NLEV_ADDR           0x4F
-#define UTD_SLEV_H_ADDR         0x50
-#define UTD_SLEV_L_ADDR         0x51
-#define UTD_DELT_ADDR           0x52
-#define UTD_RBRK_ADDR           0x53
-#define UTD_RTIME_ADDR          0x54
-#define UTD_EBRK_ADDR           0x55
-#define UTD_ETIME_ADDR          0x56
+#define UTD_CF_H_ADDR		0x4B
+#define UTD_CF_L_ADDR		0x4C
+#define UTD_BW_H_ADDR		0x4D
+#define UTD_BW_L_ADDR		0x4E
+#define UTD_NLEV_ADDR		0x4F
+#define UTD_SLEV_H_ADDR		0x50
+#define UTD_SLEV_L_ADDR		0x51
+#define UTD_DELT_ADDR		0x52
+#define UTD_RBRK_ADDR		0x53
+#define UTD_RTIME_ADDR		0x54
+#define UTD_EBRK_ADDR		0x55
+#define UTD_ETIME_ADDR		0x56
 
 #define DTMF_LEV_ADDR		0x30
 #define DTMF_TWI_ADDR		0x31
@@ -205,45 +205,45 @@
 
 /*=====================================*/
 
-#define HOOK_LEV_ACT_START_ADDR	0x89
+#define HOOK_LEV_ACT_START_ADDR 0x89
 #define RO1_START_ADDR		0x70
 #define RO2_START_ADDR		0x95
 #define RO3_START_ADDR		0x96
 
 #define TG1_FREQ_START_ADDR	0x38
 #define TG1_GAIN_START_ADDR	0x39
-#define TG1_BANDPASS_START_ADDR	0x3B
+#define TG1_BANDPASS_START_ADDR 0x3B
 #define TG1_BANDPASS_END_ADDR	0x3D
 
 #define TG2_FREQ_START_ADDR	0x40
 #define TG2_GAIN_START_ADDR	0x41
-#define TG2_BANDPASS_START_ADDR	0x43
+#define TG2_BANDPASS_START_ADDR 0x43
 #define TG2_BANDPASS_END_ADDR	0x45
 
 /*====================================*/
 
-#define PCM_HW_B         	0x80
+#define PCM_HW_B		0x80
 #define PCM_HW_A		0x00
-#define PCM_TIME_SLOT_0  	0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
-#define PCM_TIME_SLOT_1  	0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
-#define PCM_TIME_SLOT_4  	0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
+#define PCM_TIME_SLOT_0		0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
+#define PCM_TIME_SLOT_1		0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
+#define PCM_TIME_SLOT_4		0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
 
 #define	 RX_LEV_ADDR	0x28
 #define	 TX_LEV_ADDR	0x30
-#define  Ik1_ADDR	0x83
+#define	 Ik1_ADDR	0x83
 
-#define  AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct  */
-#define  AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct  */
-#define  DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
+#define	 AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
 
 /* Mark the start byte of Duslic parameters that we use with configurator */
-#define  Ik1_START_BYTE		3
+#define	 Ik1_START_BYTE		3
 #define	 RX_LEV_START_BYTE	0
 #define	 TX_LEV_START_BYTE	0
 
 /************************************************/
 
-#define INTREG4_CIS_ACT         (1 << 0)
+#define INTREG4_CIS_ACT		(1 << 0)
 
 #define BCR1_SLEEP		0x20
 #define BCR1_REVPOL		0x10
@@ -257,30 +257,30 @@
 #define BCR2_HIMAN		0x08
 #define BCR2_PDOT		0x01
 
-#define BCR3_PCMX_EN            (1 << 4)
-
-#define BCR5_DTMF_EN            (1 << 0)
-#define BCR5_DTMF_SRC           (1 << 1)
-#define BCR5_LEC_EN             (1 << 2)
-#define BCR5_LEC_OUT            (1 << 3)
-#define BCR5_CIS_EN             (1 << 4)
-#define BCR5_CIS_AUTO           (1 << 5)
-#define BCR5_UTDX_EN            (1 << 6)
-#define BCR5_UTDR_EN            (1 << 7)
-
-#define DSCR_TG1_EN             (1 << 0)
-#define DSCR_TG2_EN             (1 << 1)
-#define DSCR_PTG                (1 << 2)
-#define DSCR_COR8               (1 << 3)
-#define DSCR_DG_KEY(x)          (((x) & 0x0F) << 4)
-
-#define CIS_LEC_MODE_CIS_V23    (1 << 0)
-#define CIS_LEC_MODE_CIS_FRM    (1 << 1)
-#define CIS_LEC_MODE_NLP_EN     (1 << 2)
-#define CIS_LEC_MODE_UTDR_SUM   (1 << 4)
-#define CIS_LEC_MODE_UTDX_SUM   (1 << 5)
+#define BCR3_PCMX_EN		(1 << 4)
+
+#define BCR5_DTMF_EN		(1 << 0)
+#define BCR5_DTMF_SRC		(1 << 1)
+#define BCR5_LEC_EN		(1 << 2)
+#define BCR5_LEC_OUT		(1 << 3)
+#define BCR5_CIS_EN		(1 << 4)
+#define BCR5_CIS_AUTO		(1 << 5)
+#define BCR5_UTDX_EN		(1 << 6)
+#define BCR5_UTDR_EN		(1 << 7)
+
+#define DSCR_TG1_EN		(1 << 0)
+#define DSCR_TG2_EN		(1 << 1)
+#define DSCR_PTG		(1 << 2)
+#define DSCR_COR8		(1 << 3)
+#define DSCR_DG_KEY(x)		(((x) & 0x0F) << 4)
+
+#define CIS_LEC_MODE_CIS_V23	(1 << 0)
+#define CIS_LEC_MODE_CIS_FRM	(1 << 1)
+#define CIS_LEC_MODE_NLP_EN	(1 << 2)
+#define CIS_LEC_MODE_UTDR_SUM	(1 << 4)
+#define CIS_LEC_MODE_UTDX_SUM	(1 << 5)
 #define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
-#define CIS_LEC_MODE_LEC_ADAPT  (1 << 7)
+#define CIS_LEC_MODE_LEC_ADAPT	(1 << 7)
 
 #define TSTR4_COR_64		(1 << 5)
 
@@ -290,12 +290,12 @@
 
 
 #define LMCR1_TEST_EN		(1 << 7)
-#define	LMCR1_LM_EN		(1 << 6)
+#define LMCR1_LM_EN		(1 << 6)
 #define LMCR1_LM_THM		(1 << 5)
-#define	LMCR1_LM_ONCE		(1 << 2)
+#define LMCR1_LM_ONCE		(1 << 2)
 #define LMCR1_LM_MASK		(1 << 1)
 
-#define LMCR2_LM_RECT           	(1 << 5)
+#define LMCR2_LM_RECT			(1 << 5)
 #define LMCR2_LM_SEL_VDD		0x0D
 #define LMCR2_LM_SEL_IO3		0x0A
 #define LMCR2_LM_SEL_IO4		0x0B
@@ -313,27 +313,27 @@
 /************************************************/
 
 #define TARGET_ONHOOK_BATH_x100		4600	/* 46.0 Volt */
-#define TARGET_ONHOOK_BATL_x100		2500    /* 25.0 Volt */
+#define TARGET_ONHOOK_BATL_x100		2500	/* 25.0 Volt */
 #define TARGET_V_DIVIDER_RATIO_x100	21376L	/* (R1+R2)/R2 = 213.76 */
 #define DIVIDER_RATIO_ACCURx100		(22 * 100)
 #define V_AD_x10000			10834L	/* VAD = 1.0834 */
 #define TARGET_VDDx100			330	/* VDD = 3.3 * 10 */
 #define VDD_MAX_DIFFx100		20	/* VDD Accur = 0.2*100 */
 
-#define RMS_MULTIPLIERx100              111     /* pi/(2xsqrt(2)) = 1.11*/
-#define K_INTDC_RECT_ON                 4       /* When Rectifier is ON this value is necessary(2^4) */
-#define K_INTDC_RECT_OFF                2       /* 2^2 */
-#define RNG_FREQ                        25
-#define SAMPLING_FREQ                   (2000L)
-#define N_SAMPLES                       (SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
-#define HOOK_THRESH_RING_START_ADDR     0x8B
-#define RING_PARAMS_START_ADDR          0x70
+#define RMS_MULTIPLIERx100		111	/* pi/(2xsqrt(2)) = 1.11*/
+#define K_INTDC_RECT_ON			4	/* When Rectifier is ON this value is necessary(2^4) */
+#define K_INTDC_RECT_OFF		2	/* 2^2 */
+#define RNG_FREQ			25
+#define SAMPLING_FREQ			(2000L)
+#define N_SAMPLES			(SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
+#define HOOK_THRESH_RING_START_ADDR	0x8B
+#define RING_PARAMS_START_ADDR		0x70
 
 #define V_OUT_BATH_MAX_DIFFx100		300	/* 3.0 x100 */
 #define V_OUT_BATL_MAX_DIFFx100		400	/* 4.0 x100 */
-#define MAX_V_RING_MEANx100             50
-#define TARGET_V_RING_RMSx100           2720
-#define V_RMS_RING_MAX_DIFFx100         250
+#define MAX_V_RING_MEANx100		50
+#define TARGET_V_RING_RMSx100		2720
+#define V_RMS_RING_MAX_DIFFx100		250
 
 #define LM_OK_SRC_IRG_2			(1 << 4)
 
@@ -624,97 +624,106 @@ unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char ad
 
 /****************************************************************************/
 
-#define MAX_POP_BLOCK   50
+#define MAX_POP_BLOCK	50
 
-void codsp_write_pop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block, int len)
+void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
+			    const unsigned char *block, int len)
 {
 	unsigned char cmd[2 + MAX_POP_BLOCK];
 
-    if (len > MAX_POP_BLOCK) /* truncate */
-            len = MAX_POP_BLOCK;
+	if (len > MAX_POP_BLOCK)	/* truncate */
+		len = MAX_POP_BLOCK;
 
-	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = addr;
-	memcpy(cmd + 2, block, len);
-	codsp_send(duslic_id, cmd, 2 + len, 0, 0);
+	memcpy (cmd + 2, block, len);
+	codsp_send (duslic_id, cmd, 2 + len, 0, 0);
 }
 
-void codsp_write_pop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
+void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
+			   unsigned char val)
 {
 	unsigned char cmd[3];
 
-	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
 	cmd[2] = val;
 
-	codsp_send(duslic_id, cmd, 3, 0, 0);
+	codsp_send (duslic_id, cmd, 3, 0, 0);
 }
 
-void codsp_write_pop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
+void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
+			    unsigned short val)
 {
 	unsigned char cmd[4];
 
-	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
-	cmd[2] = (unsigned char)(val >> 8);
-	cmd[3] = (unsigned char)val;
+	cmd[2] = (unsigned char) (val >> 8);
+	cmd[3] = (unsigned char) val;
 
-	codsp_send(duslic_id, cmd, 4, 0, 0);
+	codsp_send (duslic_id, cmd, 4, 0, 0);
 }
 
-void codsp_write_pop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
+void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
+			  unsigned int val)
 {
 	unsigned char cmd[5];
 
-	cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
-	cmd[2] = (unsigned char)(val >> 24);
-	cmd[3] = (unsigned char)(val >> 16);
-	cmd[4] = (unsigned char)(val >> 8);
-	cmd[5] = (unsigned char)val;
+	cmd[2] = (unsigned char) (val >> 24);
+	cmd[3] = (unsigned char) (val >> 16);
+	cmd[4] = (unsigned char) (val >> 8);
+	cmd[5] = (unsigned char) val;
 
-	codsp_send(duslic_id, cmd, 6, 0, 0);
+	codsp_send (duslic_id, cmd, 6, 0, 0);
 }
 
-unsigned char codsp_read_pop_char(int duslic_id, int channel, unsigned char regno)
+unsigned char codsp_read_pop_char (int duslic_id, int channel,
+				   unsigned char regno)
 {
 	unsigned char cmd[3];
 	unsigned char res[2];
 
-	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
 
-	codsp_send(duslic_id, cmd, 2, res, 2);
+	codsp_send (duslic_id, cmd, 2, res, 2);
 
 	return res[1];
 }
 
-unsigned short codsp_read_pop_short(int duslic_id, int channel, unsigned char regno)
+unsigned short codsp_read_pop_short (int duslic_id, int channel,
+				     unsigned char regno)
 {
 	unsigned char cmd[2];
 	unsigned char res[3];
 
-	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
 
-	codsp_send(duslic_id, cmd, 2, res, 3);
+	codsp_send (duslic_id, cmd, 2, res, 3);
 
-	return ((unsigned short)res[1] << 8) | res[2];
+	return ((unsigned short) res[1] << 8) | res[2];
 }
 
-unsigned int codsp_read_pop_int(int duslic_id, int channel, unsigned char regno)
+unsigned int codsp_read_pop_int (int duslic_id, int channel,
+				 unsigned char regno)
 {
 	unsigned char cmd[2];
 	unsigned char res[5];
 
-	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_POP;
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
 	cmd[1] = regno;
 
-	codsp_send(duslic_id, cmd, 2, res, 5);
+	codsp_send (duslic_id, cmd, 2, res, 5);
 
-	return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
+	return (((unsigned int) res[1] << 24) |
+		((unsigned int) res[2] << 16) |
+		((unsigned int) res[3] <<  8) |
+		res[4] );
 }
-
 /****************************************************************************/
 
 struct _coeffs {
@@ -725,12 +734,12 @@ struct _coeffs {
 struct _coeffs ac_coeffs[11] = {
 	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
 	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
-	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter       */
-	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter        */
-	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter       */
-	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter       */
-	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter        */
-	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter       */
+	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter	      */
+	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter	      */
+	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter	      */
+	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter	      */
+	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter	      */
+	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter	      */
 	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
 	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
 	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} }  /* 0x10 TH-Filter part 3 */
@@ -752,14 +761,14 @@ struct _coeffs ac_coeffs_0dB[11] = {
 
 struct _coeffs dc_coeffs[9] = {
 	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter     */
-	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing          */
-	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters       */
+	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing	      */
+	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters	      */
 	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels      */
 	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator   */
-	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX              */
-	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1              */
-	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2              */
-	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved         */
+	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX	      */
+	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1	      */
+	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2	      */
+	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved	      */
 };
 
 void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
@@ -767,7 +776,7 @@ void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_
 	int i;
 
 	for (i = 0; i < tab_size; i++)
-    	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
+	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
 }
 
 #define SS_OPEN_CIRCUIT			0
@@ -800,7 +809,7 @@ static void codsp_set_slic(int duslic_id, int channel, int state)
 			break;
 
 		case SS_ACTIVE_RING:
-        	case SS_ONHOOKTRNSM:
+		case SS_ONHOOKTRNSM:
 			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
 			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
 			break;
@@ -864,7 +873,7 @@ int wait_level_metering_finish(int duslic_id, int channel)
 }
 
 int measure_on_hook_voltages(int slic_id, long *vdd,
-        	long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
+		long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
 {
 	short LM_Result, Offset_Compensation;	/* Signed 16 bit */
 	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
@@ -1029,7 +1038,7 @@ int measure_on_hook_voltages(int slic_id, long *vdd,
 			udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
 
 			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-			/*                                  ==>After that Result Regs will be updated every 500us !!!) */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
 			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
 			V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ;  /* Vin x 10000*/
 
@@ -1080,7 +1089,7 @@ int measure_on_hook_voltages(int slic_id, long *vdd,
 		udelay(10000);
 
 		/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-		/*                                  ==>After that Result Regs will be updated every 500us !!!) */
+		/*				    ==>After that Result Regs will be updated every 500us !!!) */
 		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
 		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
 
@@ -1107,7 +1116,7 @@ int measure_on_hook_voltages(int slic_id, long *vdd,
 			udelay(10000);
 
 			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-			/*                                  ==>After that Result Regs will be updated every 500us !!!) */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
 			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
 			V_in = (-1) *  ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ;  /* Vin x 10000*/
 
@@ -1149,22 +1158,22 @@ int test_dtmf(int slic_id)
 	int channel = slic_id & 1;
 
 	for (code = 0; code < 16; code++) {
-    		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
-    		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-            		(b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
-        	udelay(80000);
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+			(b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
+		udelay(80000);
 
 		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
-    		if ((intreg & CODSP_INTREG_INT_CH) == 0)
+		if ((intreg & CODSP_INTREG_INT_CH) == 0)
 			break;
 
 		if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
 				codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
 			break;
 
-        	b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
-        	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-	                	b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
 
 		udelay(80000);
 
@@ -1172,9 +1181,9 @@ int test_dtmf(int slic_id)
 	}
 
 	if (code != 16) {
-    		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
-    		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-	            		b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
 		return(1);
 	}
 
@@ -1276,7 +1285,7 @@ static int codsp_chip_full_reset(int duslic_id)
 	}
 
 	if (cnt == 5) {
-	        printf("PCM_Resync(%u) not completed\n", duslic_id);
+		printf("PCM_Resync(%u) not completed\n", duslic_id);
 		return -2;
 	}
 
@@ -1305,11 +1314,11 @@ int slic_self_test(int duslic_mask)
 	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
 		if (duslic_mask & (1 << (slic >> 1))) {
 			r = measure_on_hook_voltages(slic, &vdd,
-        			&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
+				&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
 
 			printf("SLIC %u measured voltages (x100):\n\t"
-        			    "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
-        			    slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
+				    "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
+				    slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
 
 			if (r != 0)
 				error |= 1 << slic;
diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile
new file mode 100644
index 000000000..ef60dd211
--- /dev/null
+++ b/board/omap5912osk/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap5912osk.o flash.o
+SOBJS	:= platform.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap5912osk/config.mk b/board/omap5912osk/config.mk
new file mode 100644
index 000000000..037579613
--- /dev/null
+++ b/board/omap5912osk/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002-2004
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+# Rishi Bhattacharya <rishi@ti.com>
+#
+# TI OSK board with OMAP5912 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# OSK has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/omap5912osk/flash.c b/board/omap5912osk/flash.c
new file mode 100644
index 000000000..36d881702
--- /dev/null
+++ b/board/omap5912osk/flash.c
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+
+ * (C) Copyright 2004
+ * Texas Instruments <www.ti.com>
+ * Rishi Bhattacharya
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("FLASH 28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	      case (FPW) MT2_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash	*/
+	}
+
+	mb ();
+	value = addr[1];	/* device ID	    */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB	*/
+
+	      case (FPW) (INTEL_ID_28F256K3):
+		info->flash_id +=FLASH_28F256K3;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+			    printf ("\Intel StrataFlash 28F256K3C device initialized\n");
+		break;			/* => 32 MB	*/
+
+	case (FPW) (INTEL_ID_28F128J3A):
+		info->flash_id +=FLASH_28F128J3A;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+			    printf ("\Micron StrataFlash MT28F128J3 device initialized\n");
+		break;			/* => 32 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+FPW status;
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+
+	      while (((status =*addr) & (FPW) 0x00800080) != (FPW) 0x00800080);
+
+	      *addr = (FPW) 0x00FF00FF;
+
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.	*/
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c
new file mode 100644
index 000000000..27457a198
--- /dev/null
+++ b/board/omap5912osk/omap5912osk.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Rishi Bhattacharya <rishi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	/* to be changed for OMAP 1610 Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0480000b
+	int i;
+
+	*((volatile unsigned short *) 0xfffece08) = 0x03FF;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8000;
+	*((volatile unsigned short *) 0xfffb3830) = 0x0000;
+	*((volatile unsigned short *) 0xfffb3834) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3838) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3818) = 0x0002;
+	*((volatile unsigned short *) 0xfffb382C) = 0x0048;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8603;
+	udelay (3);
+	for (i=0;i<2000;i++);
+	*((volatile unsigned short *) 0xfffb381C) = 0x6610;
+	udelay (30);
+	for (i=0;i<10000;i++);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+
+
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!	 */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
+	*MuxConfReg |= 0x00000020;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
diff --git a/board/omap5912osk/platform.S b/board/omap5912osk/platform.S
new file mode 100644
index 000000000..33c72423a
--- /dev/null
+++ b/board/omap5912osk/platform.S
@@ -0,0 +1,442 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov 	r0, 	#0x10000000
+	/* Get current execution location. */
+	mov 	r1, 	pc
+	/* Compare. */
+	cmp 	r1, 	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec600
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_OSK_OMAP5912
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds
new file mode 100644
index 000000000..901f0809d
--- /dev/null
+++ b/board/omap5912osk/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c
index 5e2fa3b62..585b6ee56 100644
--- a/board/omap730p2/omap730p2.c
+++ b/board/omap730p2/omap730p2.c
@@ -20,7 +20,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -41,12 +41,12 @@ void ether__init (void);
 void set_muxconf_regs (void);
 void peripheral_power_enable (void);
 
-#define FLASH_ON_CS0    1
-#define FLASH_ON_CS3    0
+#define FLASH_ON_CS0	1
+#define FLASH_ON_CS3	0
 
 static inline void delay (unsigned long loops)
 {
-        __asm__ volatile ("1:\n"
+	__asm__ volatile ("1:\n"
 			  "subs %0, %1, #1\n"
 			  "bne 1b":"=r" (loops):"0" (loops));
 }
@@ -63,7 +63,7 @@ int test_boot_mode(void)
 /* Toggle backup LED indication */
 void toggle_backup_led(void)
 {
-	static int  backupLEDState = 0;  /* Init variable so that the LED will be ON the first time */
+	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
 	volatile unsigned int *IOConfReg;
 
 
@@ -145,18 +145,18 @@ int misc_init_r (void)
 ******************************/
 void flash__init (void)
 {
-        unsigned int regval;
+	unsigned int regval;
 
-        regval = *((volatile unsigned int *) EMIFS_CONFIG);
-        /* Turn off write protection for flash devices. */
-        regval = regval | 0x0001;
-        *((volatile unsigned int *) EMIFS_CONFIG) = regval;
+	regval = *((volatile unsigned int *) EMIFS_CONFIG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
 }
 
 /*************************************************************
  Routine:ether__init
  Description: take the Ethernet controller out of reset and wait
-	  		   for the EEPROM load to complete.
+			   for the EEPROM load to complete.
 *************************************************************/
 void ether__init (void)
 {
@@ -196,7 +196,7 @@ int dram_init (void)
 /******************************************************
  Routine: set_muxconf_regs
  Description: Setting up the configuration Mux registers
- 			  specific to the hardware
+			  specific to the hardware
 *******************************************************/
 void set_muxconf_regs (void)
 {
@@ -209,12 +209,12 @@ void set_muxconf_regs (void)
 
 	/* Configure MUXed pin. Mode 6: GPIO_140 */
 	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
-	*MuxConfReg &= (0xFFFFFF1F);         /* Clear D_MPU_LPG1 */
-	*MuxConfReg |= 0x000000C0;           /* Set D_MPU_LPG1 to 0x6 */
+	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
+	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
 
 	/* Configure GPIO_140 as output */
 	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg &= (0xFFFFEFFF);         /* Clear direction (output) for GPIO 140 */
+	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
 
 	/*
 	 * Configure GPIOs for battery charge & feedback
@@ -222,24 +222,24 @@ void set_muxconf_regs (void)
 
 	/* Configure MUXed pin. Mode 6: GPIO_35 */
 	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
-	*MuxConfReg &= 0xFFFFFFF1;           /* Clear M_CLK_OUT */
-	*MuxConfReg |= 0x0000000C;           /* Set M_CLK_OUT = 0x6 (GPIOs) */
+	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
+	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
 
 	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
 	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
-	*MuxConfReg &= 0xFFFF1FFF;           /* Clear D_DDR */
-	*MuxConfReg |= 0x0000C000;           /* Set D_DDR = 0x6 (GPIOs) */
+	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
+	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
 
 	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg |= 0x00000100;           /* Configure GPIO_72 as input */
-	*MuxConfReg &= 0xFFFFFDFF;           /* Configure GPIO_73 as output	*/
+	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
+	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
 
 	/*
 	 * Allow battery charge
 	 */
 
 	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
-	*MuxConfReg &= (0xFFFFFDFF);         /* Clear GPIO_73 pin */
+	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
 
 	/*
 	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
diff --git a/board/omap730p2/platform.S b/board/omap730p2/platform.S
index 1f1c95a89..f30c2424f 100644
--- a/board/omap730p2/platform.S
+++ b/board/omap730p2/platform.S
@@ -391,5 +391,5 @@ PERSEUS2_CONFIG_BASE:
 .equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
 
 /* misc values */
-.equ	IRQ_MASK,		0x80           // IRQ mask value
-.equ	FIQ_MASK,		0x40           // FIQ mask value
+.equ	IRQ_MASK,		0x80           /* IRQ mask value */
+.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c
index e11b5b89b..cf00efc78 100644
--- a/board/rmu/rmu.c
+++ b/board/rmu/rmu.c
@@ -69,7 +69,7 @@ const uint sdram_table[] =
 	 */
 	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
-	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
 
 	/*
 	 * Exception. (Offset 3Ch in UPMA RAM)