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author | Martyn Capewell <martyn.capewell@arm.com> | 2019-02-12 10:41:17 +0000 |
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committer | Martyn Capewell <martyn.capewell@arm.com> | 2019-02-13 10:11:05 +0000 |
commit | dddf02dba39e6b3f59a8052ee605f31c199d27ff (patch) | |
tree | 1dc3ea05991c18de8b66aae1752778ace2068463 /test | |
parent | a1bc22a184728f79ee6f76f51c18c1afb5ec7299 (diff) |
Fix BTI support for PACIXSP
All BTI types, including the authenticating variety, should accept a BTYPE of
zero. Fix the simulator and add a test for falling into a BTI with BTYPE zero.
Change-Id: I14931fa9ba561cd03969e96701742b173927bca6
Diffstat (limited to 'test')
-rw-r--r-- | test/aarch64/test-assembler-aarch64.cc | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc index 49429e78..39802fd8 100644 --- a/test/aarch64/test-assembler-aarch64.cc +++ b/test/aarch64/test-assembler-aarch64.cc @@ -15700,6 +15700,33 @@ TEST(bti_call_to_j) { } #endif // VIXL_NEGATIVE_TESTING +TEST(fall_through_bti) { + SETUP_WITH_FEATURES(CPUFeatures::kBTI, CPUFeatures::kPAuth); + + START(); + Label target, target_j, target_c, target_jc; + __ Mov(x0, 0); // 'Normal' instruction sets BTYPE to zero. + __ Bind(&target, EmitBTI); + __ Add(x0, x0, 1); + __ Bind(&target_j, EmitBTI_j); + __ Add(x0, x0, 1); + __ Bind(&target_c, EmitBTI_c); + __ Add(x0, x0, 1); + __ Bind(&target_jc, EmitBTI_jc); + __ Add(x0, x0, 1); + __ Paciasp(); + END(); + +#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64 + simulator.SetGuardedPages(true); +#endif // VIXL_INCLUDE_SIMULATOR_AARCH64 + RUN(); + + ASSERT_EQUAL_64(4, x0); + + TEARDOWN(); +} + TEST(zero_dest) { // RegisterDump::Dump uses NEON. SETUP_WITH_FEATURES(CPUFeatures::kNEON); |